pccbb.c revision 1.29
1 /* $NetBSD: pccbb.c,v 1.29 2000/03/12 04:25:57 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and disallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 int loopend = sizeof(yc_chipsets) / sizeof(yc_chipsets[0]); 355 struct yenta_chipinfo *ycp, *ycend; 356 357 ycend = yc_chipsets + loopend; 358 359 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 360 361 if (ycp == ycend) { 362 /* not found -- point at sentinel */ 363 ycp = yc_chipsets + loopend - 1; 364 } 365 366 if (flagp != NULL) { 367 *flagp = ycp->yc_flags; 368 } 369 370 return ycp->yc_chiptype; 371 } 372 373 static void 374 pccbb_shutdown(void *arg) 375 { 376 struct pccbb_softc *sc = arg; 377 pcireg_t command; 378 379 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 380 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 381 0); 382 383 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 384 385 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 386 PCI_COMMAND_MASTER_ENABLE); 387 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 388 389 } 390 391 void 392 pccbbattach(parent, self, aux) 393 struct device *parent; 394 struct device *self; 395 void *aux; 396 { 397 struct pccbb_softc *sc = (void *)self; 398 struct pci_attach_args *pa = aux; 399 pci_chipset_tag_t pc = pa->pa_pc; 400 pcireg_t sock_base, busreg; 401 bus_addr_t sockbase; 402 char devinfo[256]; 403 int flags; 404 405 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 406 407 pci_devinfo(pa->pa_id, 0, 0, devinfo); 408 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 409 #ifdef CBB_DEBUG 410 printf(" (chipflags %x)", flags); 411 #endif 412 printf("\n"); 413 414 TAILQ_INIT(&sc->sc_memwindow); 415 TAILQ_INIT(&sc->sc_iowindow); 416 417 #if rbus 418 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 419 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 420 #endif /* rbus */ 421 422 sc->sc_base_memh = 0; 423 424 /* 425 * MAP socket registers and ExCA registers on memory-space 426 * When no valid address is set on socket base registers (on pci 427 * config space), get it not polite way. 428 */ 429 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 430 431 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 432 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 433 /* The address must be valid. */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 435 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 436 printf("%s: can't map socket base address 0x%x\n", 437 sc->sc_dev.dv_xname, sock_base); 438 /* 439 * I think it's funny: socket base registers must be 440 * mapped on memory space, but ... 441 */ 442 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 443 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 444 NULL)) { 445 printf("%s: can't map socket base address" 446 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 447 sockbase); 448 /* give up... allocate reg space via rbus. */ 449 sc->sc_base_memh = 0; 450 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 451 } 452 } else { 453 DPRINTF(("%s: socket base address 0x%lx\n", 454 sc->sc_dev.dv_xname, sockbase)); 455 } 456 } 457 458 sc->sc_mem_start = 0; /* XXX */ 459 sc->sc_mem_end = 0xffffffff; /* XXX */ 460 461 /* 462 * When interrupt isn't routed correctly, give up probing cbb and do 463 * not kill pcic-compatible port. 464 */ 465 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 466 printf("%s: NOT USED because of unconfigured interrupt\n", 467 sc->sc_dev.dv_xname); 468 return; 469 } 470 471 /* 472 * When bus number isn't set correctly, give up using 32-bit CardBus 473 * mode. 474 */ 475 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 476 #if notyet 477 if (((busreg >> 8) & 0xff) == 0) { 478 printf("%s: CardBus support disabled because of unconfigured bus number\n", 479 sc->sc_dev.dv_xname); 480 flags |= PCCBB_PCMCIA_16BITONLY; 481 } 482 #endif 483 484 /* pccbb_machdep.c end */ 485 486 #if defined CBB_DEBUG 487 { 488 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 489 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 490 intrname[pa->pa_intrpin], pa->pa_intrline); 491 } 492 #endif 493 494 /* setup softc */ 495 sc->sc_pc = pc; 496 sc->sc_iot = pa->pa_iot; 497 sc->sc_memt = pa->pa_memt; 498 sc->sc_dmat = pa->pa_dmat; 499 sc->sc_tag = pa->pa_tag; 500 sc->sc_function = pa->pa_function; 501 502 sc->sc_intrline = pa->pa_intrline; 503 sc->sc_intrtag = pa->pa_intrtag; 504 sc->sc_intrpin = pa->pa_intrpin; 505 506 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 507 508 shutdownhook_establish(pccbb_shutdown, sc); 509 510 #if __NetBSD_Version__ > 103060000 511 config_defer(self, pccbb_pci_callback); 512 #else 513 pccbb_pci_callback(self); 514 #endif 515 } 516 517 518 519 520 /* 521 * static void pccbb_pci_callback(struct device *self) 522 * 523 * The actual attach routine: get memory space for YENTA register 524 * space, setup YENTA register and route interrupt. 525 * 526 * This function should be deferred because this device may obtain 527 * memory space dynamically. This function must avoid obtaining 528 * memory area which has already kept for another device. Also, 529 * this function MUST be done before ISA attach process because this 530 * function kills pcic compatible port used by ISA pcic. 531 */ 532 static void 533 pccbb_pci_callback(self) 534 struct device *self; 535 { 536 struct pccbb_softc *sc = (void *)self; 537 pci_chipset_tag_t pc = sc->sc_pc; 538 bus_space_tag_t base_memt; 539 bus_space_handle_t base_memh; 540 u_int32_t maskreg; 541 pci_intr_handle_t ih; 542 const char *intrstr = NULL; 543 bus_addr_t sockbase; 544 struct cbslot_attach_args cba; 545 struct pcmciabus_attach_args paa; 546 struct cardslot_attach_args caa; 547 struct cardslot_softc *csc; 548 549 if (0 == sc->sc_base_memh) { 550 /* The socket registers aren't mapped correctly. */ 551 #if rbus 552 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 553 (sc->sc_chipset == CB_RX5C47X 554 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 555 0, &sockbase, &sc->sc_base_memh)) { 556 return; 557 } 558 sc->sc_base_memt = sc->sc_memt; 559 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 560 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 561 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 562 PCI_SOCKBASE))); 563 #else 564 sc->sc_base_memt = sc->sc_memt; 565 #if !defined CBB_PCI_BASE 566 #define CBB_PCI_BASE 0x20000000 567 #endif 568 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 569 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 570 /* cannot allocate memory space */ 571 return; 572 } 573 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 574 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 575 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 576 sc->sc_tag, PCI_SOCKBASE))); 577 #endif 578 } 579 580 /* bus bridge initialisation */ 581 pccbb_chipinit(sc); 582 583 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 584 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 585 586 /* CSC Interrupt: Card detect interrupt on */ 587 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 588 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 589 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 590 /* reset interrupt */ 591 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 592 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 593 594 /* Map and establish the interrupt. */ 595 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 596 sc->sc_intrline, &ih)) { 597 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 598 return; 599 } 600 intrstr = pci_intr_string(pc, ih); 601 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 602 603 if (sc->sc_ih == NULL) { 604 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 605 if (intrstr != NULL) { 606 printf(" at %s", intrstr); 607 } 608 printf("\n"); 609 return; 610 } 611 612 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 613 powerhook_establish(pccbb_powerhook, sc); 614 615 { 616 u_int32_t sockstat = 617 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 618 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 619 sc->sc_flags |= CBB_CARDEXIST; 620 } 621 } 622 623 /* 624 * attach cardbus 625 */ 626 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 627 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 628 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 629 630 /* initialise cbslot_attach */ 631 cba.cba_busname = "cardbus"; 632 cba.cba_iot = sc->sc_iot; 633 cba.cba_memt = sc->sc_memt; 634 cba.cba_dmat = sc->sc_dmat; 635 cba.cba_function = 0; 636 cba.cba_bus = (busreg >> 8) & 0x0ff; 637 cba.cba_cc = (void *)sc; 638 cba.cba_cf = &pccbb_funcs; 639 cba.cba_intrline = sc->sc_intrline; 640 641 #if rbus 642 cba.cba_rbus_iot = sc->sc_rbus_iot; 643 cba.cba_rbus_memt = sc->sc_rbus_memt; 644 #endif 645 646 cba.cba_cacheline = PCI_CACHELINE(bhlc); 647 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 648 649 printf("%s: cacheline 0x%x lattimer 0x%x\n", 650 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 651 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 652 busreg); 653 #if defined SHOW_REGS 654 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 655 sc->sc_base_memh); 656 #endif 657 } 658 659 pccbb_pcmcia_attach_setup(sc, &paa); 660 caa.caa_cb_attach = NULL; 661 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 662 caa.caa_cb_attach = &cba; 663 } 664 caa.caa_16_attach = &paa; 665 caa.caa_ph = &sc->sc_pcmcia_h; 666 667 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 668 DPRINTF(("pccbbattach: found cardslot\n")); 669 sc->sc_csc = csc; 670 } 671 672 return; 673 } 674 675 676 677 678 679 /* 680 * static void pccbb_chipinit(struct pccbb_softc *sc) 681 * 682 * This function initialise YENTA chip registers listed below: 683 * 1) PCI command reg, 684 * 2) PCI and CardBus latency timer, 685 * 3) disable legacy (PCIC-compatible) io, 686 * 4) route PCI interrupt, 687 * 5) close all memory and io windows. 688 */ 689 static void 690 pccbb_chipinit(sc) 691 struct pccbb_softc *sc; 692 { 693 pci_chipset_tag_t pc = sc->sc_pc; 694 pcitag_t tag = sc->sc_tag; 695 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 696 bus_space_handle_t base_memh = sc->sc_base_memh; 697 pcireg_t cbctrl; 698 699 /* 700 * Set PCI command reg. 701 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 702 */ 703 { 704 pcireg_t command = 705 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 706 707 /* I believe it is harmless. */ 708 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 709 PCI_COMMAND_MASTER_ENABLE); 710 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 711 } 712 713 /* 714 * Set CardBus latency timer 715 */ 716 { 717 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 718 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 719 pci_lscp &= 720 ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 721 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 722 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 723 } 724 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 725 PCI_CB_LATENCY(pci_lscp), pci_conf_read(pc, tag, 726 PCI_CB_LSCP_REG))); 727 } 728 729 /* 730 * Set PCI latency timer 731 */ 732 { 733 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 734 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 735 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 736 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 737 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 738 } 739 DPRINTF(("PCI latency timer 0x%x (%x)\n", 740 PCI_LATTIMER(pci_bhlc), pci_conf_read(pc, tag, 741 PCI_BHLC_REG))); 742 } 743 744 /* disable Legacy IO */ 745 746 switch (sc->sc_chipset) { 747 case CB_RX5C46X: /* fallthrogh */ 748 #if 0 749 case CB_RX5C47X: 750 #endif 751 /* 752 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 753 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 754 * CardBus bridges have special bits on Bridge control reg (addr 755 * 0x3e on PCI config space). 756 */ 757 { 758 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 759 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 760 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 761 } 762 break; 763 default: 764 /* XXX: I don't know proper way to kill Legacy IO properly. */ 765 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 766 break; 767 } 768 769 /* 770 * Interrupt routing: use PCI interrupt 771 */ 772 { 773 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 774 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 775 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 776 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 777 } 778 779 if (CB_TI113X == sc->sc_chipset) { 780 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 781 if (0 == sc->sc_function) { 782 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 783 } 784 /* XXX: bug in PCI113X */ 785 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 786 /* CSC intr enable */ 787 cbctrl |= PCI113X_CBCTRL_PCI_CSC; 788 /* functional intr prohibit */ 789 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 790 /* prohibit ISA routing */ 791 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; 792 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 793 794 /* 795 * set ExCA regs: PCI113X required to be set bit 4 at Interrupt 796 * and General Register, which is IRQ Enable Register, and 797 * clear bit 3:0 to zero in order to route CSC interrupt to 798 * PCI interrupt pin. 799 */ 800 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 801 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 802 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 803 #if 1 804 DPRINTF(("ExCA regs:")); 805 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 806 0x803))); 807 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 808 0x805))); 809 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt, 810 base_memh, 0x81e))); 811 #endif 812 } else if (sc->sc_chipset == CB_TI12XX) { 813 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 814 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 815 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 816 /* 817 * set ExCA regs: PCI12XX required to be set bit 4 at 818 * Interrupt and General Register, which is IRQ Enable 819 * Register, and clear bit 3:0 to zero in order to 820 * route CSC interrupt to PCI interrupt pin. 821 */ 822 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 823 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 824 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 825 } else if (sc->sc_chipset == CB_TOPIC95B) { 826 cardbusreg_t sock_ctrl, slot_ctrl; 827 828 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 829 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 830 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 831 832 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 833 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 834 sc->sc_dev.dv_xname, slot_ctrl)); 835 slot_ctrl |= 836 (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 837 TOPIC_SLOT_CTRL_ID_LOCK); 838 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 839 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 840 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 841 DPRINTF(("0x%x\n", slot_ctrl)); 842 } 843 844 /* close all memory and io windows */ 845 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 846 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 847 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 848 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 849 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 850 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 851 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 852 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 853 854 return; 855 } 856 857 858 859 860 /* 861 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 862 * struct pcmciabus_attach_args *paa) 863 * 864 * This function attaches 16-bit PCcard bus. 865 */ 866 STATIC void 867 pccbb_pcmcia_attach_setup(sc, paa) 868 struct pccbb_softc *sc; 869 struct pcmciabus_attach_args *paa; 870 { 871 struct pcic_handle *ph = &sc->sc_pcmcia_h; 872 #if rbus 873 rbus_tag_t rb; 874 #endif 875 876 /* initialise pcmcia part in pccbb_softc */ 877 ph->ph_parent = (struct device *)sc; 878 ph->sock = sc->sc_function; 879 ph->flags = 0; 880 ph->shutdown = 0; 881 ph->ih_irq = sc->sc_intrline; 882 ph->ph_bus_t = sc->sc_base_memt; 883 ph->ph_bus_h = sc->sc_base_memh; 884 ph->ph_read = pccbb_pcmcia_read; 885 ph->ph_write = pccbb_pcmcia_write; 886 sc->sc_pct = &pccbb_pcmcia_funcs; 887 888 Pcic_write(ph, PCIC_CSC_INTR, 0); 889 Pcic_read(ph, PCIC_CSC); 890 891 /* initialise pcmcia bus attachment */ 892 paa->paa_busname = "pcmcia"; 893 paa->pct = sc->sc_pct; 894 paa->pch = ph; 895 paa->iobase = 0; /* I don't use them */ 896 paa->iosize = 0; 897 #if rbus 898 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 899 paa->iobase = rb->rb_start + rb->rb_offset; 900 paa->iosize = rb->rb_end - rb->rb_start; 901 #endif 902 903 return; 904 } 905 906 #if 0 907 STATIC void 908 pccbb_pcmcia_attach_card(ph) 909 struct pcic_handle *ph; 910 { 911 if (ph->flags & PCIC_FLAG_CARDP) { 912 panic("pccbb_pcmcia_attach_card: already attached"); 913 } 914 915 /* call the MI attach function */ 916 pcmcia_card_attach(ph->pcmcia); 917 918 ph->flags |= PCIC_FLAG_CARDP; 919 } 920 921 STATIC void 922 pccbb_pcmcia_detach_card(ph, flags) 923 struct pcic_handle *ph; 924 int flags; 925 { 926 if (!(ph->flags & PCIC_FLAG_CARDP)) { 927 panic("pccbb_pcmcia_detach_card: already detached"); 928 } 929 930 ph->flags &= ~PCIC_FLAG_CARDP; 931 932 /* call the MI detach function */ 933 pcmcia_card_detach(ph->pcmcia, flags); 934 } 935 #endif 936 937 /* 938 * int pccbbintr(arg) 939 * void *arg; 940 * This routine handles the interrupt from Yenta PCI-CardBus bridge 941 * itself. 942 */ 943 int 944 pccbbintr(arg) 945 void *arg; 946 { 947 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 948 u_int32_t sockevent; 949 bus_space_tag_t memt = sc->sc_base_memt; 950 bus_space_handle_t memh = sc->sc_base_memh; 951 u_int32_t sockstate; 952 953 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 954 if (0 == sockevent) { 955 /* This intr is not for me: it may be for my child devices. */ 956 return pccbbintr_function(sc); 957 } else { 958 /* reset bit */ 959 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 960 } 961 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 962 963 if (sockevent & CB_SOCKET_EVENT_CD) { 964 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 965 /* A card should be removed. */ 966 if (sc->sc_flags & CBB_CARDEXIST) { 967 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 968 sockevent)); 969 DPRINTF((" card removed, 0x%08x\n", sockstate)); 970 sc->sc_flags &= ~CBB_CARDEXIST; 971 if (sc-> 972 sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) 973 { 974 #if 0 975 struct pcic_handle *ph = 976 &sc->sc_pcmcia_h; 977 978 pcmcia_card_deactivate(ph->pcmcia); 979 pccbb_pcmcia_socket_disable(ph); 980 pccbb_pcmcia_detach_card(ph, 981 DETACH_FORCE); 982 #endif 983 cardslot_event_throw(sc->sc_csc, 984 CARDSLOT_EVENT_REMOVAL_16); 985 } else if (sc-> 986 sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) 987 { 988 /* Cardbus intr removed */ 989 cardslot_event_throw(sc->sc_csc, 990 CARDSLOT_EVENT_REMOVAL_CB); 991 } 992 } 993 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 994 if (sc->sc_flags & CBB_INSERTING) { 995 untimeout(pci113x_insert, sc); 996 } 997 timeout(pci113x_insert, sc, hz / 10); 998 sc->sc_flags |= CBB_INSERTING; 999 } 1000 } else { 1001 DPRINTF(("%s: sockevent = %b\n", 1002 sc->sc_dev.dv_xname, sockevent, PCCBB_SOCKEVENT_BITS)); 1003 DPRINTF(("%s: sockstate = %b\n", 1004 sc->sc_dev.dv_xname, sockstate, PCCBB_SOCKSTATE_BITS)); 1005 } 1006 1007 return 1; 1008 } 1009 1010 /* 1011 * static int pccbbintr_function(struct pccbb_softc *sc) 1012 * 1013 * This function calls each interrupt handler registered at the 1014 * bridge. The interrupt handlers are called in registerd order. 1015 */ 1016 static int 1017 pccbbintr_function(sc) 1018 struct pccbb_softc *sc; 1019 { 1020 int retval = 0, val; 1021 struct pccbb_intrhand_list *pil; 1022 1023 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1024 val = (*pil->pil_func) (pil->pil_arg); 1025 retval = retval == 1 ? 1 : 1026 retval == 0 ? val : val != 0 ? val : retval; 1027 } 1028 1029 return retval; 1030 } 1031 1032 static void 1033 pci113x_insert(arg) 1034 void *arg; 1035 { 1036 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1037 u_int32_t sockevent, sockstate; 1038 1039 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1040 CB_SOCKET_EVENT); 1041 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1042 CB_SOCKET_STAT); 1043 1044 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1045 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1046 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1047 sc->sc_flags |= CBB_CARDEXIST; 1048 /* call pccard intterupt handler here */ 1049 if (sockstate & CB_SOCKET_STAT_16BIT) { 1050 /* 16-bit card found */ 1051 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1052 cardslot_event_throw(sc->sc_csc, 1053 CARDSLOT_EVENT_INSERTION_16); 1054 } else if (sockstate & CB_SOCKET_STAT_CB) { 1055 /* cardbus card fuond */ 1056 /* cardbus_attach_card(sc->sc_csc); */ 1057 cardslot_event_throw(sc->sc_csc, 1058 CARDSLOT_EVENT_INSERTION_CB); 1059 } else { 1060 /* who are you? */ 1061 } 1062 } else { 1063 timeout(pci113x_insert, sc, hz / 10); 1064 } 1065 } 1066 1067 #define PCCBB_PCMCIA_OFFSET 0x800 1068 static u_int8_t 1069 pccbb_pcmcia_read(ph, reg) 1070 struct pcic_handle *ph; 1071 int reg; 1072 { 1073 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1074 PCCBB_PCMCIA_OFFSET + reg); 1075 } 1076 1077 static void 1078 pccbb_pcmcia_write(ph, reg, val) 1079 struct pcic_handle *ph; 1080 int reg; 1081 u_int8_t val; 1082 { 1083 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1084 val); 1085 } 1086 1087 /* 1088 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1089 */ 1090 STATIC int 1091 pccbb_ctrl(ct, command) 1092 cardbus_chipset_tag_t ct; 1093 int command; 1094 { 1095 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1096 1097 switch (command) { 1098 case CARDBUS_CD: 1099 if (2 == pccbb_detect_card(sc)) { 1100 int retval = 0; 1101 int status = cb_detect_voltage(sc); 1102 if (PCCARD_VCC_5V & status) { 1103 retval |= CARDBUS_5V_CARD; 1104 } 1105 if (PCCARD_VCC_3V & status) { 1106 retval |= CARDBUS_3V_CARD; 1107 } 1108 if (PCCARD_VCC_XV & status) { 1109 retval |= CARDBUS_XV_CARD; 1110 } 1111 if (PCCARD_VCC_YV & status) { 1112 retval |= CARDBUS_YV_CARD; 1113 } 1114 return retval; 1115 } else { 1116 return 0; 1117 } 1118 break; 1119 case CARDBUS_RESET: 1120 return cb_reset(sc); 1121 break; 1122 case CARDBUS_IO_ENABLE: /* fallthrough */ 1123 case CARDBUS_IO_DISABLE: /* fallthrough */ 1124 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1125 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1126 case CARDBUS_BM_ENABLE: /* fallthrough */ 1127 case CARDBUS_BM_DISABLE: /* fallthrough */ 1128 return pccbb_cardenable(sc, command); 1129 break; 1130 } 1131 1132 return 0; 1133 } 1134 1135 /* 1136 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1137 * This function returns true when it succeeds and returns false when 1138 * it fails. 1139 */ 1140 STATIC int 1141 pccbb_power(ct, command) 1142 cardbus_chipset_tag_t ct; 1143 int command; 1144 { 1145 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1146 1147 u_int32_t status, sock_ctrl; 1148 bus_space_tag_t memt = sc->sc_base_memt; 1149 bus_space_handle_t memh = sc->sc_base_memh; 1150 1151 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1152 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1153 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1154 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1155 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1156 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1157 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1158 "UNKNOWN", 1159 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1160 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1161 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1162 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1163 "UNKNOWN", command)); 1164 1165 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1166 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1167 1168 switch (command & CARDBUS_VCCMASK) { 1169 case CARDBUS_VCC_UC: 1170 break; 1171 case CARDBUS_VCC_5V: 1172 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1173 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1174 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1175 } else { 1176 printf("%s: BAD voltage request: no 5 V card\n", 1177 sc->sc_dev.dv_xname); 1178 } 1179 break; 1180 case CARDBUS_VCC_3V: 1181 if (CB_SOCKET_STAT_3VCARD & status) { 1182 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1183 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1184 } else { 1185 printf("%s: BAD voltage request: no 3.3 V card\n", 1186 sc->sc_dev.dv_xname); 1187 } 1188 break; 1189 case CARDBUS_VCC_0V: 1190 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1191 break; 1192 default: 1193 return 0; /* power NEVER changed */ 1194 break; 1195 } 1196 1197 switch (command & CARDBUS_VPPMASK) { 1198 case CARDBUS_VPP_UC: 1199 break; 1200 case CARDBUS_VPP_0V: 1201 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1202 break; 1203 case CARDBUS_VPP_VCC: 1204 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1205 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1206 break; 1207 case CARDBUS_VPP_12V: 1208 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1209 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1210 break; 1211 } 1212 1213 #if 0 1214 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1215 #endif 1216 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1217 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1218 1219 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1220 /* 1221 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1222 * time is 20 ms, some PC-Card bridge requires longer duration. 1223 */ 1224 delay(200 * 1000); 1225 1226 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1227 printf 1228 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1229 sc->sc_dev.dv_xname, sock_ctrl, status); 1230 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1231 (command & CARDBUS_VCCMASK) == 1232 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1233 CARDBUS_VCCMASK) == 1234 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1235 CARDBUS_VCCMASK) == 1236 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1237 CARDBUS_VCCMASK) == 1238 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1239 CARDBUS_VCCMASK) == 1240 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1241 CARDBUS_VCCMASK) == 1242 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1243 (command & CARDBUS_VPPMASK) == 1244 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1245 CARDBUS_VPPMASK) == 1246 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1247 CARDBUS_VPPMASK) == 1248 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1249 CARDBUS_VPPMASK) == 1250 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1251 #if 0 1252 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1253 u_int32_t force = 1254 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1255 /* Reset Bad Vcc request */ 1256 force &= ~CB_SOCKET_FORCE_BADVCC; 1257 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1258 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1259 CB_SOCKET_STAT)); 1260 return 1; 1261 } 1262 #endif 1263 return 0; 1264 } 1265 return 1; /* power changed correctly */ 1266 } 1267 1268 #if defined CB_PCMCIA_POLL 1269 struct cb_poll_str { 1270 void *arg; 1271 int (*func) __P((void *)); 1272 int level; 1273 pccard_chipset_tag_t ct; 1274 int count; 1275 }; 1276 1277 static struct cb_poll_str cb_poll[10]; 1278 static int cb_poll_n = 0; 1279 1280 static void cb_pcmcia_poll __P((void *arg)); 1281 1282 static void 1283 cb_pcmcia_poll(arg) 1284 void *arg; 1285 { 1286 struct cb_poll_str *poll = arg; 1287 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1288 struct pccbb_softc *sc = psc->cpc_parent; 1289 int s; 1290 u_int32_t spsr; /* socket present-state reg */ 1291 1292 timeout(cb_pcmcia_poll, arg, hz / 10); 1293 switch (poll->level) { 1294 case IPL_NET: 1295 s = splnet(); 1296 break; 1297 case IPL_BIO: 1298 s = splbio(); 1299 break; 1300 case IPL_TTY: /* fallthrough */ 1301 default: 1302 s = spltty(); 1303 break; 1304 } 1305 1306 spsr = 1307 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1308 CB_SOCKET_STAT); 1309 1310 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1311 if (!(spsr & 0x40)) { /* CINT low */ 1312 #else 1313 if (1) { 1314 #endif 1315 if ((*poll->func) (poll->arg) == 1) { 1316 ++poll->count; 1317 printf("intr: reported from poller, 0x%x\n", spsr); 1318 #if defined LEVEL2 1319 } else { 1320 printf("intr: miss! 0x%x\n", spsr); 1321 #endif 1322 } 1323 } 1324 splx(s); 1325 } 1326 #endif /* defined CB_PCMCIA_POLL */ 1327 1328 /* 1329 * static int pccbb_detect_card(struct pccbb_softc *sc) 1330 * return value: 0 if no card exists. 1331 * 1 if 16-bit card exists. 1332 * 2 if cardbus card exists. 1333 */ 1334 static int 1335 pccbb_detect_card(sc) 1336 struct pccbb_softc *sc; 1337 { 1338 bus_space_handle_t base_memh = sc->sc_base_memh; 1339 bus_space_tag_t base_memt = sc->sc_base_memt; 1340 u_int32_t sockstat = 1341 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1342 int retval = 0; 1343 1344 /* CD1 and CD2 asserted */ 1345 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1346 /* card must be present */ 1347 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1348 /* NOTACARD DEASSERTED */ 1349 if (CB_SOCKET_STAT_CB & sockstat) { 1350 /* CardBus mode */ 1351 retval = 2; 1352 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1353 /* 16-bit mode */ 1354 retval = 1; 1355 } 1356 } 1357 } 1358 return retval; 1359 } 1360 1361 /* 1362 * STATIC int cb_reset(struct pccbb_softc *sc) 1363 * This function resets CardBus card. 1364 */ 1365 STATIC int 1366 cb_reset(sc) 1367 struct pccbb_softc *sc; 1368 { 1369 /* 1370 * Reset Assert at least 20 ms 1371 * Some machines request longer duration. 1372 */ 1373 int reset_duration = 1374 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1375 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1376 1377 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1378 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1379 delay(reset_duration); 1380 1381 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1382 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1383 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1384 delay(reset_duration); 1385 } 1386 /* No card found on the slot. Keep Reset. */ 1387 return 1; 1388 } 1389 1390 /* 1391 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1392 * This function detect card Voltage. 1393 */ 1394 STATIC int 1395 cb_detect_voltage(sc) 1396 struct pccbb_softc *sc; 1397 { 1398 u_int32_t psr; /* socket present-state reg */ 1399 bus_space_tag_t iot = sc->sc_base_memt; 1400 bus_space_handle_t ioh = sc->sc_base_memh; 1401 int vol = PCCARD_VCC_UKN; /* set 0 */ 1402 1403 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1404 1405 if (0x400u & psr) { 1406 vol |= PCCARD_VCC_5V; 1407 } 1408 if (0x800u & psr) { 1409 vol |= PCCARD_VCC_3V; 1410 } 1411 1412 return vol; 1413 } 1414 1415 STATIC int 1416 cbbprint(aux, pcic) 1417 void *aux; 1418 const char *pcic; 1419 { 1420 /* 1421 struct cbslot_attach_args *cba = aux; 1422 1423 if (cba->cba_slot >= 0) { 1424 printf(" slot %d", cba->cba_slot); 1425 } 1426 */ 1427 return UNCONF; 1428 } 1429 1430 /* 1431 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1432 * This function enables and disables the card 1433 */ 1434 STATIC int 1435 pccbb_cardenable(sc, function) 1436 struct pccbb_softc *sc; 1437 int function; 1438 { 1439 u_int32_t command = 1440 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1441 1442 DPRINTF(("pccbb_cardenable:")); 1443 switch (function) { 1444 case CARDBUS_IO_ENABLE: 1445 command |= PCI_COMMAND_IO_ENABLE; 1446 break; 1447 case CARDBUS_IO_DISABLE: 1448 command &= ~PCI_COMMAND_IO_ENABLE; 1449 break; 1450 case CARDBUS_MEM_ENABLE: 1451 command |= PCI_COMMAND_MEM_ENABLE; 1452 break; 1453 case CARDBUS_MEM_DISABLE: 1454 command &= ~PCI_COMMAND_MEM_ENABLE; 1455 break; 1456 case CARDBUS_BM_ENABLE: 1457 command |= PCI_COMMAND_MASTER_ENABLE; 1458 break; 1459 case CARDBUS_BM_DISABLE: 1460 command &= ~PCI_COMMAND_MASTER_ENABLE; 1461 break; 1462 default: 1463 return 0; 1464 } 1465 1466 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1467 DPRINTF((" command reg 0x%x\n", command)); 1468 return 1; 1469 } 1470 1471 #if !rbus 1472 /* 1473 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1474 */ 1475 static int 1476 pccbb_io_open(ct, win, start, end) 1477 cardbus_chipset_tag_t ct; 1478 int win; 1479 u_int32_t start, end; 1480 { 1481 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1482 int basereg; 1483 int limitreg; 1484 1485 if ((win < 0) || (win > 2)) { 1486 #if defined DIAGNOSTIC 1487 printf("cardbus_io_open: window out of range %d\n", win); 1488 #endif 1489 return 0; 1490 } 1491 1492 basereg = win * 8 + 0x2c; 1493 limitreg = win * 8 + 0x30; 1494 1495 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1496 start, basereg, end, limitreg)); 1497 1498 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1499 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1500 return 1; 1501 } 1502 1503 /* 1504 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1505 */ 1506 static int 1507 pccbb_io_close(ct, win) 1508 cardbus_chipset_tag_t ct; 1509 int win; 1510 { 1511 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1512 int basereg; 1513 int limitreg; 1514 1515 if ((win < 0) || (win > 2)) { 1516 #if defined DIAGNOSTIC 1517 printf("cardbus_io_close: window out of range %d\n", win); 1518 #endif 1519 return 0; 1520 } 1521 1522 basereg = win * 8 + 0x2c; 1523 limitreg = win * 8 + 0x30; 1524 1525 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1526 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1527 return 1; 1528 } 1529 1530 /* 1531 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1532 */ 1533 static int 1534 pccbb_mem_open(ct, win, start, end) 1535 cardbus_chipset_tag_t ct; 1536 int win; 1537 u_int32_t start, end; 1538 { 1539 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1540 int basereg; 1541 int limitreg; 1542 1543 if ((win < 0) || (win > 2)) { 1544 #if defined DIAGNOSTIC 1545 printf("cardbus_mem_open: window out of range %d\n", win); 1546 #endif 1547 return 0; 1548 } 1549 1550 basereg = win * 8 + 0x1c; 1551 limitreg = win * 8 + 0x20; 1552 1553 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1554 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1555 return 1; 1556 } 1557 1558 /* 1559 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1560 */ 1561 static int 1562 pccbb_mem_close(ct, win) 1563 cardbus_chipset_tag_t ct; 1564 int win; 1565 { 1566 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1567 int basereg; 1568 int limitreg; 1569 1570 if ((win < 0) || (win > 2)) { 1571 #if defined DIAGNOSTIC 1572 printf("cardbus_mem_close: window out of range %d\n", win); 1573 #endif 1574 return 0; 1575 } 1576 1577 basereg = win * 8 + 0x1c; 1578 limitreg = win * 8 + 0x20; 1579 1580 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1581 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1582 return 1; 1583 } 1584 #endif 1585 1586 /* 1587 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1588 * int irq, 1589 * int level, 1590 * int (* func) __P((void *)), 1591 * void *arg) 1592 * 1593 * This function registers an interrupt handler at the bridge, in 1594 * order not to call the interrput handlers of child devices when 1595 * a card-deletion interrput occurs. 1596 * 1597 * The arguments irq and level are not used. 1598 */ 1599 static void * 1600 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1601 cardbus_chipset_tag_t ct; 1602 int irq, level; 1603 int (*func) __P((void *)); 1604 void *arg; 1605 { 1606 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1607 1608 return pccbb_intr_establish(sc, irq, level, func, arg); 1609 } 1610 1611 1612 /* 1613 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1614 * void *ih) 1615 * 1616 * This function removes an interrupt handler pointed by ih. 1617 */ 1618 static void 1619 pccbb_cb_intr_disestablish(ct, ih) 1620 cardbus_chipset_tag_t ct; 1621 void *ih; 1622 { 1623 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1624 1625 pccbb_intr_disestablish(sc, ih); 1626 } 1627 1628 1629 /* 1630 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1631 * int irq, 1632 * int level, 1633 * int (* func) __P((void *)), 1634 * void *arg) 1635 * 1636 * This function registers an interrupt handler at the bridge, in 1637 * order not to call the interrput handlers of child devices when 1638 * a card-deletion interrput occurs. 1639 * 1640 * The arguments irq and level are not used. 1641 */ 1642 static void * 1643 pccbb_intr_establish(sc, irq, level, func, arg) 1644 struct pccbb_softc *sc; 1645 int irq, level; 1646 int (*func) __P((void *)); 1647 void *arg; 1648 { 1649 struct pccbb_intrhand_list *pil, *newpil; 1650 1651 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1652 1653 if (sc->sc_pil == NULL) { 1654 /* initialise bridge intr routing */ 1655 1656 switch (sc->sc_chipset) { 1657 case CB_TI113X: 1658 { 1659 pcireg_t cbctrl = 1660 pci_conf_read(sc->sc_pc, sc->sc_tag, 1661 PCI_CBCTRL); 1662 /* functional intr enabled */ 1663 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1664 pci_conf_write(sc->sc_pc, sc->sc_tag, 1665 PCI_CBCTRL, cbctrl); 1666 break; 1667 } 1668 default: 1669 break; 1670 } 1671 } 1672 1673 /* 1674 * Allocate a room for interrut handler structure. 1675 */ 1676 if (NULL == (newpil = 1677 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1678 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1679 return NULL; 1680 } 1681 1682 newpil->pil_func = func; 1683 newpil->pil_arg = arg; 1684 newpil->pil_next = NULL; 1685 1686 if (sc->sc_pil == NULL) { 1687 sc->sc_pil = newpil; 1688 } else { 1689 for (pil = sc->sc_pil; pil->pil_next != NULL; 1690 pil = pil->pil_next); 1691 pil->pil_next = newpil; 1692 } 1693 1694 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1695 1696 return newpil; 1697 } 1698 1699 /* 1700 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1701 * void *ih) 1702 * 1703 * This function removes an interrupt handler pointed by ih. 1704 */ 1705 static void 1706 pccbb_intr_disestablish(sc, ih) 1707 struct pccbb_softc *sc; 1708 void *ih; 1709 { 1710 struct pccbb_intrhand_list *pil, **pil_prev; 1711 1712 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1713 1714 pil_prev = &sc->sc_pil; 1715 1716 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1717 if (pil == ih) { 1718 *pil_prev = pil->pil_next; 1719 free(pil, M_DEVBUF); 1720 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1721 break; 1722 } 1723 pil_prev = &pil->pil_next; 1724 } 1725 1726 if (sc->sc_pil == NULL) { 1727 /* No interrupt handlers */ 1728 1729 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1730 1731 switch (sc->sc_chipset) { 1732 case CB_TI113X: 1733 { 1734 pcireg_t cbctrl = 1735 pci_conf_read(sc->sc_pc, sc->sc_tag, 1736 PCI_CBCTRL); 1737 /* functional intr disabled */ 1738 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1739 pci_conf_write(sc->sc_pc, sc->sc_tag, 1740 PCI_CBCTRL, cbctrl); 1741 break; 1742 } 1743 default: 1744 break; 1745 } 1746 } 1747 } 1748 1749 #if defined SHOW_REGS 1750 static void 1751 cb_show_regs(pc, tag, memt, memh) 1752 pci_chipset_tag_t pc; 1753 pcitag_t tag; 1754 bus_space_tag_t memt; 1755 bus_space_handle_t memh; 1756 { 1757 int i; 1758 printf("PCI config regs:"); 1759 for (i = 0; i < 0x50; i += 4) { 1760 if (i % 16 == 0) { 1761 printf("\n 0x%02x:", i); 1762 } 1763 printf(" %08x", pci_conf_read(pc, tag, i)); 1764 } 1765 for (i = 0x80; i < 0xb0; i += 4) { 1766 if (i % 16 == 0) { 1767 printf("\n 0x%02x:", i); 1768 } 1769 printf(" %08x", pci_conf_read(pc, tag, i)); 1770 } 1771 1772 if (memh == 0) { 1773 printf("\n"); 1774 return; 1775 } 1776 1777 printf("\nsocket regs:"); 1778 for (i = 0; i <= 0x10; i += 0x04) { 1779 printf(" %08x", bus_space_read_4(memt, memh, i)); 1780 } 1781 printf("\nExCA regs:"); 1782 for (i = 0; i < 0x08; ++i) { 1783 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1784 } 1785 printf("\n"); 1786 return; 1787 } 1788 #endif 1789 1790 /* 1791 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1792 * int busno, int devno, int function) 1793 * This is the function to make a tag to access config space of 1794 * a CardBus Card. It works same as pci_conf_read. 1795 */ 1796 static cardbustag_t 1797 pccbb_make_tag(cc, busno, devno, function) 1798 cardbus_chipset_tag_t cc; 1799 int busno, devno, function; 1800 { 1801 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1802 1803 return pci_make_tag(sc->sc_pc, busno, devno, function); 1804 } 1805 1806 static void 1807 pccbb_free_tag(cc, tag) 1808 cardbus_chipset_tag_t cc; 1809 cardbustag_t tag; 1810 { 1811 } 1812 1813 /* 1814 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1815 * cardbustag_t tag, int offset) 1816 * This is the function to read the config space of a CardBus Card. 1817 * It works same as pci_conf_read. 1818 */ 1819 static cardbusreg_t 1820 pccbb_conf_read(cc, tag, offset) 1821 cardbus_chipset_tag_t cc; 1822 cardbustag_t tag; 1823 int offset; /* register offset */ 1824 { 1825 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1826 1827 return pci_conf_read(sc->sc_pc, tag, offset); 1828 } 1829 1830 /* 1831 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1832 * int offs, cardbusreg_t val) 1833 * This is the function to write the config space of a CardBus Card. 1834 * It works same as pci_conf_write. 1835 */ 1836 static void 1837 pccbb_conf_write(cc, tag, reg, val) 1838 cardbus_chipset_tag_t cc; 1839 cardbustag_t tag; 1840 int reg; /* register offset */ 1841 cardbusreg_t val; 1842 { 1843 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1844 1845 pci_conf_write(sc->sc_pc, tag, reg, val); 1846 } 1847 1848 #if 0 1849 STATIC int 1850 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1851 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1852 int speed, int flags, 1853 bus_space_handle_t * iohp) 1854 #endif 1855 /* 1856 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1857 * bus_addr_t start, bus_size_t size, 1858 * bus_size_t align, 1859 * struct pcmcia_io_handle *pcihp 1860 * 1861 * This function only allocates I/O region for pccard. This function 1862 * never maps the allcated region to pccard I/O area. 1863 * 1864 * XXX: The interface of this function is not very good, I believe. 1865 */ 1866 STATIC int 1867 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1868 pcmcia_chipset_handle_t pch; 1869 bus_addr_t start; /* start address */ 1870 bus_size_t size; 1871 bus_size_t align; 1872 struct pcmcia_io_handle *pcihp; 1873 { 1874 struct pcic_handle *ph = (struct pcic_handle *)pch; 1875 bus_addr_t ioaddr; 1876 int flags = 0; 1877 bus_space_tag_t iot; 1878 bus_space_handle_t ioh; 1879 #if rbus 1880 rbus_tag_t rb; 1881 #endif 1882 if (align == 0) { 1883 align = size; /* XXX: funny??? */ 1884 } 1885 1886 /* 1887 * Allocate some arbitrary I/O space. 1888 */ 1889 1890 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1891 1892 #if rbus 1893 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1894 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1895 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1896 return 1; 1897 } 1898 #else 1899 if (start) { 1900 ioaddr = start; 1901 if (bus_space_map(iot, start, size, 0, &ioh)) { 1902 return 1; 1903 } 1904 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1905 (u_long) ioaddr, (u_long) size)); 1906 } else { 1907 flags |= PCMCIA_IO_ALLOCATED; 1908 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1909 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1910 size, align, 0, 0, &ioaddr, &ioh)) { 1911 /* No room be able to be get. */ 1912 return 1; 1913 } 1914 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1915 (u_long) ioaddr, (u_long) size)); 1916 } 1917 #endif 1918 1919 pcihp->iot = iot; 1920 pcihp->ioh = ioh; 1921 pcihp->addr = ioaddr; 1922 pcihp->size = size; 1923 pcihp->flags = flags; 1924 1925 return 0; 1926 } 1927 1928 /* 1929 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1930 * struct pcmcia_io_handle *pcihp) 1931 * 1932 * This function only frees I/O region for pccard. 1933 * 1934 * XXX: The interface of this function is not very good, I believe. 1935 */ 1936 void 1937 pccbb_pcmcia_io_free(pch, pcihp) 1938 pcmcia_chipset_handle_t pch; 1939 struct pcmcia_io_handle *pcihp; 1940 { 1941 #if !rbus 1942 bus_space_tag_t iot = pcihp->iot; 1943 #endif 1944 bus_space_handle_t ioh = pcihp->ioh; 1945 bus_size_t size = pcihp->size; 1946 1947 #if rbus 1948 struct pccbb_softc *sc = 1949 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1950 rbus_tag_t rb = sc->sc_rbus_iot; 1951 1952 rbus_space_free(rb, ioh, size, NULL); 1953 #else 1954 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1955 bus_space_free(iot, ioh, size); 1956 else 1957 bus_space_unmap(iot, ioh, size); 1958 #endif 1959 } 1960 1961 /* 1962 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1963 * bus_addr_t offset, bus_size_t size, 1964 * struct pcmcia_io_handle *pcihp, 1965 * int *windowp) 1966 * 1967 * This function maps the allocated I/O region to pccard. This function 1968 * never allocates any I/O region for pccard I/O area. I don't 1969 * understand why the original authors of pcmciabus separated alloc and 1970 * map. I believe the two must be unite. 1971 * 1972 * XXX: no wait timing control? 1973 */ 1974 int 1975 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1976 pcmcia_chipset_handle_t pch; 1977 int width; 1978 bus_addr_t offset; 1979 bus_size_t size; 1980 struct pcmcia_io_handle *pcihp; 1981 int *windowp; 1982 { 1983 struct pcic_handle *ph = (struct pcic_handle *)pch; 1984 bus_addr_t ioaddr = pcihp->addr + offset; 1985 int i, win; 1986 #if defined CBB_DEBUG 1987 static char *width_names[] = { "dynamic", "io8", "io16" }; 1988 #endif 1989 1990 /* Sanity check I/O handle. */ 1991 1992 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1993 panic("pccbb_pcmcia_io_map iot is bogus"); 1994 } 1995 1996 /* XXX Sanity check offset/size. */ 1997 1998 win = -1; 1999 for (i = 0; i < PCIC_IO_WINS; i++) { 2000 if ((ph->ioalloc & (1 << i)) == 0) { 2001 win = i; 2002 ph->ioalloc |= (1 << i); 2003 break; 2004 } 2005 } 2006 2007 if (win == -1) { 2008 return 1; 2009 } 2010 2011 *windowp = win; 2012 2013 /* XXX this is pretty gross */ 2014 2015 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2016 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2017 2018 /* XXX wtf is this doing here? */ 2019 2020 #if 0 2021 printf(" port 0x%lx", (u_long) ioaddr); 2022 if (size > 1) { 2023 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2024 } 2025 #endif 2026 2027 ph->io[win].addr = ioaddr; 2028 ph->io[win].size = size; 2029 ph->io[win].width = width; 2030 2031 /* actual dirty register-value changing in the function below. */ 2032 pccbb_pcmcia_do_io_map(ph, win); 2033 2034 return 0; 2035 } 2036 2037 /* 2038 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2039 * 2040 * This function changes register-value to map I/O region for pccard. 2041 */ 2042 static void 2043 pccbb_pcmcia_do_io_map(ph, win) 2044 struct pcic_handle *ph; 2045 int win; 2046 { 2047 static u_int8_t pcic_iowidth[3] = { 2048 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2049 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2050 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2051 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2052 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2053 }; 2054 2055 #define PCIC_SIA_START_LOW 0 2056 #define PCIC_SIA_START_HIGH 1 2057 #define PCIC_SIA_STOP_LOW 2 2058 #define PCIC_SIA_STOP_HIGH 3 2059 2060 int regbase_win = 0x8 + win * 0x04; 2061 u_int8_t ioctl, enable; 2062 2063 DPRINTF( 2064 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2065 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2066 ph->io[win].width * 8)); 2067 2068 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2069 ph->io[win].addr & 0xff); 2070 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2071 (ph->io[win].addr >> 8) & 0xff); 2072 2073 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2074 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2075 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2076 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2077 2078 ioctl = Pcic_read(ph, PCIC_IOCTL); 2079 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2080 switch (win) { 2081 case 0: 2082 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2083 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2084 PCIC_IOCTL_IO0_DATASIZE_MASK); 2085 ioctl |= pcic_iowidth[ph->io[win].width]; 2086 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2087 break; 2088 case 1: 2089 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2090 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2091 PCIC_IOCTL_IO1_DATASIZE_MASK); 2092 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2093 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2094 break; 2095 } 2096 Pcic_write(ph, PCIC_IOCTL, ioctl); 2097 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2098 #if defined CBB_DEBUG 2099 { 2100 u_int8_t start_low = 2101 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2102 u_int8_t start_high = 2103 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2104 u_int8_t stop_low = 2105 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2106 u_int8_t stop_high = 2107 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2108 printf 2109 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2110 start_low, start_high, stop_low, stop_high, ioctl, enable); 2111 } 2112 #endif 2113 } 2114 2115 /* 2116 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2117 * 2118 * This function unmapss I/O region. No return value. 2119 */ 2120 STATIC void 2121 pccbb_pcmcia_io_unmap(pch, win) 2122 pcmcia_chipset_handle_t pch; 2123 int win; 2124 { 2125 struct pcic_handle *ph = (struct pcic_handle *)pch; 2126 int reg; 2127 2128 if (win >= PCIC_IO_WINS || win < 0) { 2129 panic("pccbb_pcmcia_io_unmap: window out of range"); 2130 } 2131 2132 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2133 switch (win) { 2134 case 0: 2135 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2136 break; 2137 case 1: 2138 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2139 break; 2140 } 2141 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2142 2143 ph->ioalloc &= ~(1 << win); 2144 } 2145 2146 /* 2147 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2148 * 2149 * This function enables the card. All information is stored in 2150 * the first argument, pcmcia_chipset_handle_t. 2151 */ 2152 static void 2153 pccbb_pcmcia_wait_ready(ph) 2154 struct pcic_handle *ph; 2155 { 2156 int i; 2157 2158 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2159 Pcic_read(ph, PCIC_IF_STATUS))); 2160 2161 for (i = 0; i < 10000; i++) { 2162 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2163 return; 2164 } 2165 delay(500); 2166 #ifdef CBB_DEBUG 2167 if ((i > 5000) && (i % 100 == 99)) 2168 printf("."); 2169 #endif 2170 } 2171 2172 #ifdef DIAGNOSTIC 2173 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2174 Pcic_read(ph, PCIC_IF_STATUS)); 2175 #endif 2176 } 2177 2178 /* 2179 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2180 * 2181 * This function enables the card. All information is stored in 2182 * the first argument, pcmcia_chipset_handle_t. 2183 */ 2184 STATIC void 2185 pccbb_pcmcia_socket_enable(pch) 2186 pcmcia_chipset_handle_t pch; 2187 { 2188 struct pcic_handle *ph = (struct pcic_handle *)pch; 2189 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2190 int cardtype, win; 2191 u_int8_t power, intr; 2192 pcireg_t spsr; 2193 int voltage; 2194 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2195 2196 /* this bit is mostly stolen from pcic_attach_card */ 2197 2198 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2199 2200 /* get card Vcc info */ 2201 2202 spsr = 2203 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2204 CB_SOCKET_STAT); 2205 if (spsr & CB_SOCKET_STAT_5VCARD) { 2206 DPRINTF(("5V card\n")); 2207 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2208 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2209 DPRINTF(("3V card\n")); 2210 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2211 } else { 2212 printf("?V card, 0x%x\n", spsr); /* XXX */ 2213 return; 2214 } 2215 2216 /* assert reset bit */ 2217 intr = Pcic_read(ph, PCIC_INTR); 2218 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2219 Pcic_write(ph, PCIC_INTR, intr); 2220 2221 /* disable socket i/o: negate output enable bit */ 2222 2223 power = Pcic_read(ph, PCIC_PWRCTL); 2224 power &= ~PCIC_PWRCTL_OE; 2225 Pcic_write(ph, PCIC_PWRCTL, power); 2226 2227 /* power down the socket to reset it, clear the card reset pin */ 2228 2229 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2230 2231 /* 2232 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2233 * we are changing Vcc (Toff). 2234 */ 2235 /* delay(300*1000); too much */ 2236 2237 /* power up the socket */ 2238 pccbb_power(sc, voltage); 2239 2240 /* 2241 * wait 100ms until power raise (Tpr) and 20ms to become 2242 * stable (Tsu(Vcc)). 2243 * 2244 * some machines require some more time to be settled 2245 * (another 200ms is added here). 2246 */ 2247 /* delay((100 + 20 + 200)*1000); too much */ 2248 2249 power = Pcic_read(ph, PCIC_PWRCTL); 2250 power |= PCIC_PWRCTL_OE; 2251 Pcic_write(ph, PCIC_PWRCTL, power); 2252 2253 /* 2254 * hold RESET at least 10us. 2255 */ 2256 delay(10); 2257 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2258 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2259 2260 /* clear the reset flag */ 2261 2262 intr |= PCIC_INTR_RESET; 2263 Pcic_write(ph, PCIC_INTR, intr); 2264 2265 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2266 2267 delay(20000); 2268 2269 /* wait for the chip to finish initializing */ 2270 2271 pccbb_pcmcia_wait_ready(ph); 2272 2273 /* zero out the address windows */ 2274 2275 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2276 2277 /* set the card type */ 2278 2279 cardtype = pcmcia_card_gettype(ph->pcmcia); 2280 2281 intr |= PCIC_INTR_PCI; 2282 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2283 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2284 Pcic_write(ph, PCIC_INTR, intr); 2285 2286 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2287 ph->ph_parent->dv_xname, ph->sock, 2288 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2289 2290 /* reinstall all the memory and io mappings */ 2291 2292 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2293 if (ph->memalloc & (1 << win)) { 2294 pccbb_pcmcia_do_mem_map(ph, win); 2295 } 2296 } 2297 2298 for (win = 0; win < PCIC_IO_WINS; ++win) { 2299 if (ph->ioalloc & (1 << win)) { 2300 pccbb_pcmcia_do_io_map(ph, win); 2301 } 2302 } 2303 } 2304 2305 /* 2306 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2307 * 2308 * This function disables the card. All information is stored in 2309 * the first argument, pcmcia_chipset_handle_t. 2310 */ 2311 STATIC void 2312 pccbb_pcmcia_socket_disable(pch) 2313 pcmcia_chipset_handle_t pch; 2314 { 2315 struct pcic_handle *ph = (struct pcic_handle *)pch; 2316 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2317 u_int8_t power, intr; 2318 2319 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2320 2321 /* reset signal asserting... */ 2322 2323 intr = Pcic_read(ph, PCIC_INTR); 2324 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2325 Pcic_write(ph, PCIC_INTR, intr); 2326 delay(2 * 1000); 2327 2328 /* power down the socket */ 2329 power = Pcic_read(ph, PCIC_PWRCTL); 2330 power &= ~PCIC_PWRCTL_OE; 2331 Pcic_write(ph, PCIC_PWRCTL, power); 2332 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2333 /* 2334 * wait 300ms until power fails (Tpf). 2335 */ 2336 delay(300 * 1000); 2337 } 2338 2339 /* 2340 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2341 * 2342 * This function detects whether a card is in the slot or not. 2343 * If a card is inserted, return 1. Otherwise, return 0. 2344 */ 2345 STATIC int 2346 pccbb_pcmcia_card_detect(pch) 2347 pcmcia_chipset_handle_t pch; 2348 { 2349 struct pcic_handle *ph = (struct pcic_handle *)pch; 2350 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2351 2352 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2353 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2354 } 2355 2356 #if 0 2357 STATIC int 2358 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2359 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2360 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2361 #endif 2362 /* 2363 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2364 * bus_size_t size, 2365 * struct pcmcia_mem_handle *pcmhp) 2366 * 2367 * This function only allocates memory region for pccard. This 2368 * function never maps the allcated region to pccard memory area. 2369 * 2370 * XXX: Why the argument of start address is not in? 2371 */ 2372 STATIC int 2373 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2374 pcmcia_chipset_handle_t pch; 2375 bus_size_t size; 2376 struct pcmcia_mem_handle *pcmhp; 2377 { 2378 struct pcic_handle *ph = (struct pcic_handle *)pch; 2379 bus_space_handle_t memh; 2380 bus_addr_t addr; 2381 bus_size_t sizepg; 2382 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2383 #if rbus 2384 rbus_tag_t rb; 2385 #endif 2386 2387 /* out of sc->memh, allocate as many pages as necessary */ 2388 2389 /* convert size to PCIC pages */ 2390 /* 2391 * This is not enough; when the requested region is on the page 2392 * boundaries, this may calculate wrong result. 2393 */ 2394 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2395 #if 0 2396 if (sizepg > PCIC_MAX_MEM_PAGES) { 2397 return 1; 2398 } 2399 #endif 2400 2401 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2402 return 1; 2403 } 2404 2405 addr = 0; /* XXX gcc -Wuninitialized */ 2406 2407 #if rbus 2408 rb = sc->sc_rbus_memt; 2409 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2410 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2411 &addr, &memh)) { 2412 return 1; 2413 } 2414 #else 2415 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2416 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2417 0, /* boundary */ 2418 0, /* flags */ 2419 &addr, &memh)) { 2420 return 1; 2421 } 2422 #endif 2423 2424 DPRINTF( 2425 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2426 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2427 2428 pcmhp->memt = sc->sc_memt; 2429 pcmhp->memh = memh; 2430 pcmhp->addr = addr; 2431 pcmhp->size = size; 2432 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2433 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2434 pcmhp->mhandle = 0; 2435 /* No offset??? Funny. */ 2436 2437 return 0; 2438 } 2439 2440 /* 2441 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2442 * struct pcmcia_mem_handle *pcmhp) 2443 * 2444 * This function release the memory space allocated by the fuction 2445 * pccbb_pcmcia_mem_alloc(). 2446 */ 2447 STATIC void 2448 pccbb_pcmcia_mem_free(pch, pcmhp) 2449 pcmcia_chipset_handle_t pch; 2450 struct pcmcia_mem_handle *pcmhp; 2451 { 2452 #if rbus 2453 struct pcic_handle *ph = (struct pcic_handle *)pch; 2454 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2455 2456 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2457 #else 2458 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2459 #endif 2460 } 2461 2462 /* 2463 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2464 * 2465 * This function release the memory space allocated by the fuction 2466 * pccbb_pcmcia_mem_alloc(). 2467 */ 2468 STATIC void 2469 pccbb_pcmcia_do_mem_map(ph, win) 2470 struct pcic_handle *ph; 2471 int win; 2472 { 2473 int regbase_win; 2474 bus_addr_t phys_addr; 2475 bus_addr_t phys_end; 2476 2477 #define PCIC_SMM_START_LOW 0 2478 #define PCIC_SMM_START_HIGH 1 2479 #define PCIC_SMM_STOP_LOW 2 2480 #define PCIC_SMM_STOP_HIGH 3 2481 #define PCIC_CMA_LOW 4 2482 #define PCIC_CMA_HIGH 5 2483 2484 u_int8_t start_low, start_high = 0; 2485 u_int8_t stop_low, stop_high; 2486 u_int8_t off_low, off_high; 2487 u_int8_t mem_window; 2488 int reg; 2489 2490 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2491 int mem8 = 2492 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2493 || (kind == PCMCIA_MEM_ATTR); 2494 2495 regbase_win = 0x10 + win * 0x08; 2496 2497 phys_addr = ph->mem[win].addr; 2498 phys_end = phys_addr + ph->mem[win].size; 2499 2500 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2501 phys_addr, phys_end, ph->mem[win].offset)); 2502 2503 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2504 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2505 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2506 2507 /* bit 19:12 */ 2508 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2509 /* bit 23:20 and bit 7 on */ 2510 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2511 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2512 /* bit 31:24, for 32-bit address */ 2513 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2514 2515 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2516 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2517 2518 if (((struct pccbb_softc *)ph-> 2519 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2520 Pcic_write(ph, 0x40 + win, mem_window); 2521 } 2522 2523 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2524 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2525 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2526 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2527 2528 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2529 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2530 2531 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2532 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2533 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2534 | ((kind == PCMCIA_MEM_ATTR) ? 2535 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2536 2537 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2538 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2539 2540 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2541 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2542 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2543 2544 #if defined CBB_DEBUG 2545 { 2546 int r1, r2, r3, r4, r5, r6, r7 = 0; 2547 2548 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2549 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2550 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2551 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2552 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2553 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2554 if (((struct pccbb_softc *)(ph-> 2555 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2556 r7 = Pcic_read(ph, 0x40 + win); 2557 } 2558 2559 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2560 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2561 if (((struct pccbb_softc *)(ph-> 2562 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2563 DPRINTF((" %02x", r7)); 2564 } 2565 DPRINTF(("\n")); 2566 } 2567 #endif 2568 } 2569 2570 /* 2571 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2572 * bus_addr_t card_addr, bus_size_t size, 2573 * struct pcmcia_mem_handle *pcmhp, 2574 * bus_addr_t *offsetp, int *windowp) 2575 * 2576 * This function maps memory space allocated by the fuction 2577 * pccbb_pcmcia_mem_alloc(). 2578 */ 2579 STATIC int 2580 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2581 pcmcia_chipset_handle_t pch; 2582 int kind; 2583 bus_addr_t card_addr; 2584 bus_size_t size; 2585 struct pcmcia_mem_handle *pcmhp; 2586 bus_addr_t *offsetp; 2587 int *windowp; 2588 { 2589 struct pcic_handle *ph = (struct pcic_handle *)pch; 2590 bus_addr_t busaddr; 2591 long card_offset; 2592 int win; 2593 2594 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2595 if ((ph->memalloc & (1 << win)) == 0) { 2596 ph->memalloc |= (1 << win); 2597 break; 2598 } 2599 } 2600 2601 if (win == PCIC_MEM_WINS) { 2602 return 1; 2603 } 2604 2605 *windowp = win; 2606 2607 /* XXX this is pretty gross */ 2608 2609 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2610 panic("pccbb_pcmcia_mem_map memt is bogus"); 2611 } 2612 2613 busaddr = pcmhp->addr; 2614 2615 /* 2616 * compute the address offset to the pcmcia address space for the 2617 * pcic. this is intentionally signed. The masks and shifts below 2618 * will cause TRT to happen in the pcic registers. Deal with making 2619 * sure the address is aligned, and return the alignment offset. 2620 */ 2621 2622 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2623 card_addr -= *offsetp; 2624 2625 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2626 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2627 (u_long) card_addr)); 2628 2629 /* 2630 * include the offset in the size, and decrement size by one, since 2631 * the hw wants start/stop 2632 */ 2633 size += *offsetp - 1; 2634 2635 card_offset = (((long)card_addr) - ((long)busaddr)); 2636 2637 ph->mem[win].addr = busaddr; 2638 ph->mem[win].size = size; 2639 ph->mem[win].offset = card_offset; 2640 ph->mem[win].kind = kind; 2641 2642 pccbb_pcmcia_do_mem_map(ph, win); 2643 2644 return 0; 2645 } 2646 2647 /* 2648 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2649 * int window) 2650 * 2651 * This function unmaps memory space which mapped by the fuction 2652 * pccbb_pcmcia_mem_map(). 2653 */ 2654 STATIC void 2655 pccbb_pcmcia_mem_unmap(pch, window) 2656 pcmcia_chipset_handle_t pch; 2657 int window; 2658 { 2659 struct pcic_handle *ph = (struct pcic_handle *)pch; 2660 int reg; 2661 2662 if (window >= PCIC_MEM_WINS) { 2663 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2664 } 2665 2666 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2667 reg &= ~(1 << window); 2668 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2669 2670 ph->memalloc &= ~(1 << window); 2671 } 2672 2673 #if defined PCCBB_PCMCIA_POLL 2674 struct pccbb_poll_str { 2675 void *arg; 2676 int (*func) __P((void *)); 2677 int level; 2678 struct pcic_handle *ph; 2679 int count; 2680 int num; 2681 }; 2682 2683 static struct pccbb_poll_str pccbb_poll[10]; 2684 static int pccbb_poll_n = 0; 2685 2686 static void pccbb_pcmcia_poll __P((void *arg)); 2687 2688 static void 2689 pccbb_pcmcia_poll(arg) 2690 void *arg; 2691 { 2692 struct pccbb_poll_str *poll = arg; 2693 struct pcic_handle *ph = poll->ph; 2694 struct pccbb_softc *sc = ph->sc; 2695 int s; 2696 u_int32_t spsr; /* socket present-state reg */ 2697 2698 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2699 switch (poll->level) { 2700 case IPL_NET: 2701 s = splnet(); 2702 break; 2703 case IPL_BIO: 2704 s = splbio(); 2705 break; 2706 case IPL_TTY: /* fallthrough */ 2707 default: 2708 s = spltty(); 2709 break; 2710 } 2711 2712 spsr = 2713 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2714 CB_SOCKET_STAT); 2715 2716 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2717 if (!(spsr & 0x40)) /* CINT low */ 2718 #else 2719 if (1) 2720 #endif 2721 { 2722 if ((*poll->func) (poll->arg) > 0) { 2723 ++poll->count; 2724 // printf("intr: reported from poller, 0x%x\n", spsr); 2725 #if defined LEVEL2 2726 } else { 2727 printf("intr: miss! 0x%x\n", spsr); 2728 #endif 2729 } 2730 } 2731 splx(s); 2732 } 2733 #endif /* defined CB_PCMCIA_POLL */ 2734 2735 /* 2736 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2737 * struct pcmcia_function *pf, 2738 * int ipl, 2739 * int (*func)(void *), 2740 * void *arg); 2741 * 2742 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2743 */ 2744 STATIC void * 2745 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2746 pcmcia_chipset_handle_t pch; 2747 struct pcmcia_function *pf; 2748 int ipl; 2749 int (*func) __P((void *)); 2750 void *arg; 2751 { 2752 struct pcic_handle *ph = (struct pcic_handle *)pch; 2753 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2754 2755 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2756 /* what should I do? */ 2757 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2758 DPRINTF( 2759 ("%s does not provide edge nor pulse interrupt\n", 2760 sc->sc_dev.dv_xname)); 2761 return NULL; 2762 } 2763 /* 2764 * XXX Noooooo! The interrupt flag must set properly!! 2765 * dumb pcmcia driver!! 2766 */ 2767 } 2768 2769 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2770 } 2771 2772 /* 2773 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2774 * void *ih) 2775 * 2776 * This function disables PC-Card interrupt. 2777 */ 2778 STATIC void 2779 pccbb_pcmcia_intr_disestablish(pch, ih) 2780 pcmcia_chipset_handle_t pch; 2781 void *ih; 2782 { 2783 struct pcic_handle *ph = (struct pcic_handle *)pch; 2784 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2785 2786 pccbb_intr_disestablish(sc, ih); 2787 } 2788 2789 #if rbus 2790 /* 2791 * static int 2792 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2793 * bus_addr_t addr, bus_size_t size, 2794 * bus_addr_t mask, bus_size_t align, 2795 * int flags, bus_addr_t *addrp; 2796 * bus_space_handle_t *bshp) 2797 * 2798 * This function allocates a portion of memory or io space for 2799 * clients. This function is called from CardBus card drivers. 2800 */ 2801 static int 2802 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2803 cardbus_chipset_tag_t ct; 2804 rbus_tag_t rb; 2805 bus_addr_t addr; 2806 bus_size_t size; 2807 bus_addr_t mask; 2808 bus_size_t align; 2809 int flags; 2810 bus_addr_t *addrp; 2811 bus_space_handle_t *bshp; 2812 { 2813 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2814 2815 DPRINTF( 2816 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2817 addr, size, mask, align)); 2818 2819 if (align == 0) { 2820 align = size; 2821 } 2822 2823 if (rb->rb_bt == sc->sc_memt) { 2824 if (align < 16) { 2825 return 1; 2826 } 2827 } else if (rb->rb_bt == sc->sc_iot) { 2828 if (align < 4) { 2829 return 1; 2830 } 2831 } else { 2832 DPRINTF( 2833 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2834 rb->rb_bt)); 2835 return 1; 2836 /* XXX: panic here? */ 2837 } 2838 2839 /* XXX: hack for avoiding ISA image */ 2840 if (mask < 0x3ff) { 2841 mask = 0x3ff; 2842 addr = 0x300; 2843 } 2844 2845 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2846 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2847 return 1; 2848 } 2849 2850 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2851 2852 return 0; 2853 } 2854 2855 /* 2856 * static int 2857 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2858 * bus_space_handle_t *bshp, bus_size_t size); 2859 * 2860 * This function is called from CardBus card drivers. 2861 */ 2862 static int 2863 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2864 cardbus_chipset_tag_t ct; 2865 rbus_tag_t rb; 2866 bus_space_handle_t bsh; 2867 bus_size_t size; 2868 { 2869 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2870 bus_space_tag_t bt = rb->rb_bt; 2871 2872 pccbb_close_win(sc, bt, bsh, size); 2873 2874 if (bt == sc->sc_memt) { 2875 } else if (bt == sc->sc_iot) { 2876 } else { 2877 return 1; 2878 /* XXX: panic here? */ 2879 } 2880 2881 return rbus_space_free(rb, bsh, size, NULL); 2882 } 2883 #endif /* rbus */ 2884 2885 #if rbus 2886 2887 static int 2888 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2889 struct pccbb_softc *sc; 2890 bus_space_tag_t bst; 2891 bus_addr_t addr; 2892 bus_size_t size; 2893 bus_space_handle_t bsh; 2894 int flags; 2895 { 2896 struct pccbb_win_chain_head *head; 2897 bus_addr_t align; 2898 2899 head = &sc->sc_iowindow; 2900 align = 0x04; 2901 if (sc->sc_memt == bst) { 2902 head = &sc->sc_memwindow; 2903 align = 0x1000; 2904 DPRINTF(("using memory window, %x %x %x\n\n", 2905 sc->sc_iot, sc->sc_memt, bst)); 2906 } 2907 2908 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2909 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2910 sc->sc_dev.dv_xname, 2911 (head == &sc->sc_memwindow) ? "mem" : "io"); 2912 } 2913 pccbb_winset(align, sc, bst); 2914 2915 return 0; 2916 } 2917 2918 static int 2919 pccbb_close_win(sc, bst, bsh, size) 2920 struct pccbb_softc *sc; 2921 bus_space_tag_t bst; 2922 bus_space_handle_t bsh; 2923 bus_size_t size; 2924 { 2925 struct pccbb_win_chain_head *head; 2926 bus_addr_t align; 2927 2928 head = &sc->sc_iowindow; 2929 align = 0x04; 2930 if (sc->sc_memt == bst) { 2931 head = &sc->sc_memwindow; 2932 align = 0x1000; 2933 } 2934 2935 if (pccbb_winlist_delete(head, bsh, size)) { 2936 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2937 sc->sc_dev.dv_xname, 2938 (head == &sc->sc_memwindow) ? "mem" : "io"); 2939 } 2940 pccbb_winset(align, sc, bst); 2941 2942 return 0; 2943 } 2944 2945 static int 2946 pccbb_winlist_insert(head, start, size, bsh, flags) 2947 struct pccbb_win_chain_head *head; 2948 bus_addr_t start; 2949 bus_size_t size; 2950 bus_space_handle_t bsh; 2951 int flags; 2952 { 2953 struct pccbb_win_chain *chainp, *elem; 2954 2955 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2956 M_NOWAIT)) == NULL) 2957 return 1; /* fail */ 2958 2959 elem->wc_start = start; 2960 elem->wc_end = start + (size - 1); 2961 elem->wc_handle = bsh; 2962 elem->wc_flags = flags; 2963 2964 if ((chainp = TAILQ_FIRST(head)) == NULL) { 2965 TAILQ_INSERT_HEAD(head, elem, wc_list); 2966 return 0; 2967 } 2968 2969 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2970 if (chainp->wc_end < start) 2971 continue; 2972 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2973 return 0; 2974 } 2975 2976 TAILQ_INSERT_TAIL(head, elem, wc_list); 2977 2978 return 0; 2979 } 2980 2981 static int 2982 pccbb_winlist_delete(head, bsh, size) 2983 struct pccbb_win_chain_head *head; 2984 bus_space_handle_t bsh; 2985 bus_size_t size; 2986 { 2987 struct pccbb_win_chain *chainp; 2988 2989 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2990 chainp = TAILQ_NEXT(chainp, wc_list)) { 2991 if (chainp->wc_handle != bsh) 2992 continue; 2993 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2994 printf("pccbb_winlist_delete: window 0x%lx size " 2995 "inconsistent: 0x%lx, 0x%lx\n", 2996 chainp->wc_start, 2997 chainp->wc_end - chainp->wc_start, 2998 size - 1); 2999 return 1; 3000 } 3001 3002 TAILQ_REMOVE(head, chainp, wc_list); 3003 free(chainp, M_DEVBUF); 3004 3005 return 0; 3006 } 3007 3008 return 1; /* fail: no candidate to remove */ 3009 } 3010 3011 static void 3012 pccbb_winset(align, sc, bst) 3013 bus_addr_t align; 3014 struct pccbb_softc *sc; 3015 bus_space_tag_t bst; 3016 { 3017 pci_chipset_tag_t pc; 3018 pcitag_t tag; 3019 bus_addr_t mask = ~(align - 1); 3020 struct { 3021 cardbusreg_t win_start; 3022 cardbusreg_t win_limit; 3023 int win_flags; 3024 } win[2]; 3025 struct pccbb_win_chain *chainp; 3026 int offs; 3027 3028 win[0].win_start = 0xffffffff; 3029 win[0].win_limit = 0; 3030 win[1].win_start = 0xffffffff; 3031 win[1].win_limit = 0; 3032 3033 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3034 offs = 0x2c; 3035 if (sc->sc_memt == bst) { 3036 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3037 offs = 0x1c; 3038 } 3039 3040 if (chainp != NULL) { 3041 win[0].win_start = chainp->wc_start & mask; 3042 win[0].win_limit = chainp->wc_end & mask; 3043 win[0].win_flags = chainp->wc_flags; 3044 chainp = TAILQ_NEXT(chainp, wc_list); 3045 } 3046 3047 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3048 if (win[1].win_start == 0xffffffff) { 3049 /* window 1 is not used */ 3050 if ((win[0].win_flags == chainp->wc_flags) && 3051 (win[0].win_limit + align >= 3052 (chainp->wc_start & mask))) { 3053 /* concatenate */ 3054 win[0].win_limit = chainp->wc_end & mask; 3055 } else { 3056 /* make new window */ 3057 win[1].win_start = chainp->wc_start & mask; 3058 win[1].win_limit = chainp->wc_end & mask; 3059 win[1].win_flags = chainp->wc_flags; 3060 } 3061 continue; 3062 } 3063 3064 /* Both windows are engagad. */ 3065 if (win[0].win_flags == win[1].win_flags) { 3066 /* same flags */ 3067 if (win[0].win_flags == chainp->wc_flags) { 3068 if (win[1].win_start - (win[0].win_limit + 3069 align) < 3070 (chainp->wc_start & mask) - 3071 ((chainp->wc_end & mask) + align)) { 3072 /* 3073 * merge window 0 and 1, and set win1 3074 * to chainp 3075 */ 3076 win[0].win_limit = win[1].win_limit; 3077 win[1].win_start = 3078 chainp->wc_start & mask; 3079 win[1].win_limit = 3080 chainp->wc_end & mask; 3081 } else { 3082 win[1].win_limit = 3083 chainp->wc_end & mask; 3084 } 3085 } else { 3086 /* different flags */ 3087 3088 /* concatenate win0 and win1 */ 3089 win[0].win_limit = win[1].win_limit; 3090 /* allocate win[1] to new space */ 3091 win[1].win_start = chainp->wc_start & mask; 3092 win[1].win_limit = chainp->wc_end & mask; 3093 win[1].win_flags = chainp->wc_flags; 3094 } 3095 } else { 3096 /* the flags of win[0] and win[1] is different */ 3097 if (win[0].win_flags == chainp->wc_flags) { 3098 win[0].win_limit = chainp->wc_end & mask; 3099 /* 3100 * XXX this creates overlapping windows, so 3101 * what should the poor bridge do if one is 3102 * cachable, and the other is not? 3103 */ 3104 printf("%s: overlapping windows\n", 3105 sc->sc_dev.dv_xname); 3106 } else { 3107 win[1].win_limit = chainp->wc_end & mask; 3108 } 3109 } 3110 } 3111 3112 pc = sc->sc_pc; 3113 tag = sc->sc_tag; 3114 pci_conf_write(pc, tag, offs, win[0].win_start); 3115 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3116 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3117 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3118 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3119 pci_conf_read(pc, tag, offs), 3120 pci_conf_read(pc, tag, offs + 4) + align, 3121 pci_conf_read(pc, tag, offs + 8), 3122 pci_conf_read(pc, tag, offs + 12) + align)); 3123 3124 if (bst == sc->sc_memt) { 3125 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3126 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3127 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3128 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3129 } 3130 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3131 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3132 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3133 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3134 } 3135 } 3136 } 3137 3138 #endif /* rbus */ 3139 3140 static void 3141 pccbb_powerhook(why, arg) 3142 int why; 3143 void *arg; 3144 { 3145 struct pccbb_softc *sc = arg; 3146 u_int32_t reg; 3147 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3148 bus_space_handle_t base_memh = sc->sc_base_memh; 3149 3150 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3151 3152 if (why == PWR_RESUME) { 3153 /* CSC Interrupt: Card detect interrupt on */ 3154 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3155 /* Card detect intr is turned on. */ 3156 reg |= CB_SOCKET_MASK_CD; 3157 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3158 /* reset interrupt */ 3159 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3160 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3161 3162 /* 3163 * check for card insertion or removal during suspend period. 3164 * XXX: the code can't cope with card swap (remove then insert). 3165 * how can we detect such situation? 3166 */ 3167 if (why == PWR_RESUME) 3168 (void)pccbbintr(sc); 3169 } 3170 } 3171
Indexes created Sat Sep 27 22:09:54 GMT 2025