pccbb.c revision 1.30
1 /* $NetBSD: pccbb.c,v 1.30 2000/03/12 04:34:29 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and disallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 int loopend = sizeof(yc_chipsets) / sizeof(yc_chipsets[0]); 355 struct yenta_chipinfo *ycp, *ycend; 356 357 ycend = yc_chipsets + loopend; 358 359 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 360 361 if (ycp == ycend) { 362 /* not found -- point at sentinel */ 363 ycp = yc_chipsets + loopend - 1; 364 } 365 366 if (flagp != NULL) { 367 *flagp = ycp->yc_flags; 368 } 369 370 return ycp->yc_chiptype; 371 } 372 373 static void 374 pccbb_shutdown(void *arg) 375 { 376 struct pccbb_softc *sc = arg; 377 pcireg_t command; 378 379 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 380 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 381 0); 382 383 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 384 385 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 386 PCI_COMMAND_MASTER_ENABLE); 387 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 388 389 } 390 391 void 392 pccbbattach(parent, self, aux) 393 struct device *parent; 394 struct device *self; 395 void *aux; 396 { 397 struct pccbb_softc *sc = (void *)self; 398 struct pci_attach_args *pa = aux; 399 pci_chipset_tag_t pc = pa->pa_pc; 400 pcireg_t sock_base, busreg; 401 bus_addr_t sockbase; 402 char devinfo[256]; 403 int flags; 404 405 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 406 407 pci_devinfo(pa->pa_id, 0, 0, devinfo); 408 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 409 #ifdef CBB_DEBUG 410 printf(" (chipflags %x)", flags); 411 #endif 412 printf("\n"); 413 414 TAILQ_INIT(&sc->sc_memwindow); 415 TAILQ_INIT(&sc->sc_iowindow); 416 417 #if rbus 418 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 419 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 420 #endif /* rbus */ 421 422 sc->sc_base_memh = 0; 423 424 /* 425 * MAP socket registers and ExCA registers on memory-space 426 * When no valid address is set on socket base registers (on pci 427 * config space), get it not polite way. 428 */ 429 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 430 431 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 432 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 433 /* The address must be valid. */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 435 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 436 printf("%s: can't map socket base address 0x%x\n", 437 sc->sc_dev.dv_xname, sock_base); 438 /* 439 * I think it's funny: socket base registers must be 440 * mapped on memory space, but ... 441 */ 442 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 443 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 444 NULL)) { 445 printf("%s: can't map socket base address" 446 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 447 sockbase); 448 /* give up... allocate reg space via rbus. */ 449 sc->sc_base_memh = 0; 450 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 451 } 452 } else { 453 DPRINTF(("%s: socket base address 0x%lx\n", 454 sc->sc_dev.dv_xname, sockbase)); 455 } 456 } 457 458 sc->sc_mem_start = 0; /* XXX */ 459 sc->sc_mem_end = 0xffffffff; /* XXX */ 460 461 /* 462 * When interrupt isn't routed correctly, give up probing cbb and do 463 * not kill pcic-compatible port. 464 */ 465 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 466 printf("%s: NOT USED because of unconfigured interrupt\n", 467 sc->sc_dev.dv_xname); 468 return; 469 } 470 471 /* 472 * When bus number isn't set correctly, give up using 32-bit CardBus 473 * mode. 474 */ 475 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 476 #if notyet 477 if (((busreg >> 8) & 0xff) == 0) { 478 printf("%s: CardBus support disabled because of unconfigured bus number\n", 479 sc->sc_dev.dv_xname); 480 flags |= PCCBB_PCMCIA_16BITONLY; 481 } 482 #endif 483 484 /* pccbb_machdep.c end */ 485 486 #if defined CBB_DEBUG 487 { 488 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 489 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 490 intrname[pa->pa_intrpin], pa->pa_intrline); 491 } 492 #endif 493 494 /* setup softc */ 495 sc->sc_pc = pc; 496 sc->sc_iot = pa->pa_iot; 497 sc->sc_memt = pa->pa_memt; 498 sc->sc_dmat = pa->pa_dmat; 499 sc->sc_tag = pa->pa_tag; 500 sc->sc_function = pa->pa_function; 501 502 sc->sc_intrline = pa->pa_intrline; 503 sc->sc_intrtag = pa->pa_intrtag; 504 sc->sc_intrpin = pa->pa_intrpin; 505 506 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 507 508 shutdownhook_establish(pccbb_shutdown, sc); 509 510 #if __NetBSD_Version__ > 103060000 511 config_defer(self, pccbb_pci_callback); 512 #else 513 pccbb_pci_callback(self); 514 #endif 515 } 516 517 518 519 520 /* 521 * static void pccbb_pci_callback(struct device *self) 522 * 523 * The actual attach routine: get memory space for YENTA register 524 * space, setup YENTA register and route interrupt. 525 * 526 * This function should be deferred because this device may obtain 527 * memory space dynamically. This function must avoid obtaining 528 * memory area which has already kept for another device. Also, 529 * this function MUST be done before ISA attach process because this 530 * function kills pcic compatible port used by ISA pcic. 531 */ 532 static void 533 pccbb_pci_callback(self) 534 struct device *self; 535 { 536 struct pccbb_softc *sc = (void *)self; 537 pci_chipset_tag_t pc = sc->sc_pc; 538 bus_space_tag_t base_memt; 539 bus_space_handle_t base_memh; 540 u_int32_t maskreg; 541 pci_intr_handle_t ih; 542 const char *intrstr = NULL; 543 bus_addr_t sockbase; 544 struct cbslot_attach_args cba; 545 struct pcmciabus_attach_args paa; 546 struct cardslot_attach_args caa; 547 struct cardslot_softc *csc; 548 549 if (0 == sc->sc_base_memh) { 550 /* The socket registers aren't mapped correctly. */ 551 #if rbus 552 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 553 (sc->sc_chipset == CB_RX5C47X 554 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 555 0, &sockbase, &sc->sc_base_memh)) { 556 return; 557 } 558 sc->sc_base_memt = sc->sc_memt; 559 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 560 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 561 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 562 PCI_SOCKBASE))); 563 #else 564 sc->sc_base_memt = sc->sc_memt; 565 #if !defined CBB_PCI_BASE 566 #define CBB_PCI_BASE 0x20000000 567 #endif 568 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 569 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 570 /* cannot allocate memory space */ 571 return; 572 } 573 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 574 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 575 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 576 sc->sc_tag, PCI_SOCKBASE))); 577 #endif 578 } 579 580 /* bus bridge initialisation */ 581 pccbb_chipinit(sc); 582 583 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 584 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 585 586 /* CSC Interrupt: Card detect interrupt on */ 587 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 588 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 589 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 590 /* reset interrupt */ 591 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 592 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 593 594 /* Map and establish the interrupt. */ 595 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 596 sc->sc_intrline, &ih)) { 597 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 598 return; 599 } 600 intrstr = pci_intr_string(pc, ih); 601 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 602 603 if (sc->sc_ih == NULL) { 604 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 605 if (intrstr != NULL) { 606 printf(" at %s", intrstr); 607 } 608 printf("\n"); 609 return; 610 } 611 612 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 613 powerhook_establish(pccbb_powerhook, sc); 614 615 { 616 u_int32_t sockstat = 617 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 618 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 619 sc->sc_flags |= CBB_CARDEXIST; 620 } 621 } 622 623 /* 624 * attach cardbus 625 */ 626 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 627 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 628 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 629 630 /* initialise cbslot_attach */ 631 cba.cba_busname = "cardbus"; 632 cba.cba_iot = sc->sc_iot; 633 cba.cba_memt = sc->sc_memt; 634 cba.cba_dmat = sc->sc_dmat; 635 cba.cba_function = 0; 636 cba.cba_bus = (busreg >> 8) & 0x0ff; 637 cba.cba_cc = (void *)sc; 638 cba.cba_cf = &pccbb_funcs; 639 cba.cba_intrline = sc->sc_intrline; 640 641 #if rbus 642 cba.cba_rbus_iot = sc->sc_rbus_iot; 643 cba.cba_rbus_memt = sc->sc_rbus_memt; 644 #endif 645 646 cba.cba_cacheline = PCI_CACHELINE(bhlc); 647 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 648 649 printf("%s: cacheline 0x%x lattimer 0x%x\n", 650 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 651 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 652 busreg); 653 #if defined SHOW_REGS 654 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 655 sc->sc_base_memh); 656 #endif 657 } 658 659 pccbb_pcmcia_attach_setup(sc, &paa); 660 caa.caa_cb_attach = NULL; 661 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 662 caa.caa_cb_attach = &cba; 663 } 664 caa.caa_16_attach = &paa; 665 caa.caa_ph = &sc->sc_pcmcia_h; 666 667 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 668 DPRINTF(("pccbbattach: found cardslot\n")); 669 sc->sc_csc = csc; 670 } 671 672 return; 673 } 674 675 676 677 678 679 /* 680 * static void pccbb_chipinit(struct pccbb_softc *sc) 681 * 682 * This function initialise YENTA chip registers listed below: 683 * 1) PCI command reg, 684 * 2) PCI and CardBus latency timer, 685 * 3) disable legacy (PCIC-compatible) io, 686 * 4) route PCI interrupt, 687 * 5) close all memory and io windows. 688 */ 689 static void 690 pccbb_chipinit(sc) 691 struct pccbb_softc *sc; 692 { 693 pci_chipset_tag_t pc = sc->sc_pc; 694 pcitag_t tag = sc->sc_tag; 695 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 696 bus_space_handle_t base_memh = sc->sc_base_memh; 697 pcireg_t reg; 698 699 /* 700 * Set PCI command reg. 701 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 702 */ 703 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 704 /* I believe it is harmless. */ 705 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 706 PCI_COMMAND_MASTER_ENABLE); 707 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 708 709 /* 710 * Set CardBus latency timer. 711 */ 712 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 713 if (PCI_CB_LATENCY(reg) < 0x20) { 714 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 715 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 716 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 717 } 718 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 719 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 720 721 /* 722 * Set PCI latency timer. 723 */ 724 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 725 if (PCI_LATTIMER(reg) < 0x10) { 726 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 727 reg |= (0x10 << PCI_LATTIMER_SHIFT); 728 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 729 } 730 DPRINTF(("PCI latency timer 0x%x (%x)\n", 731 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 732 733 /* Disable legacy register mapping. */ 734 switch (sc->sc_chipset) { 735 case CB_RX5C46X: /* fallthrough */ 736 #if 0 737 case CB_RX5C47X: 738 #endif 739 /* 740 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 741 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 742 * CardBus bridges have special bits on Bridge control reg (addr 743 * 0x3e on PCI config space). 744 */ 745 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 746 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 747 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 748 break; 749 750 default: 751 /* XXX I don't know proper way to kill legacy I/O. */ 752 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 753 break; 754 } 755 756 /* Route functional interrupts to PCI. */ 757 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 758 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 759 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 760 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 761 762 switch (sc->sc_chipset) { 763 case CB_TI113X: 764 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 765 /* This bit is shared, but may read as 0 on some chips, so set 766 it explicitly on both functions. */ 767 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 768 /* CSC intr enable */ 769 reg |= PCI113X_CBCTRL_PCI_CSC; 770 /* functional intr prohibit */ 771 reg &= ~PCI113X_CBCTRL_PCI_INTR; 772 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 773 774 /* FALLTHROUGH */ 775 case CB_TI12XX: 776 /* 777 * Register 03 bits 0-3 contain the functional IRQ number. 778 * Register 05 bits 4-7 contain the CSC IRQ number. 779 * Setting these to 0 disables ISA interrupt routing. 780 * Setting register 03 bit 4 is required to enable PCI 781 * interrupt routing on some chips. 782 */ 783 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 784 bus_space_write_1(base_memt, base_memh, 0x0805, 0x08); 785 break; 786 787 case CB_TOPIC95B: 788 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 789 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 790 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 791 792 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 793 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 794 sc->sc_dev.dv_xname, reg)); 795 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 796 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 797 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 798 DPRINTF(("0x%x\n", reg)); 799 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 800 break; 801 } 802 803 /* Close all memory and I/O windows. */ 804 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 805 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 806 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 807 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 808 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 809 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 810 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 811 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 812 } 813 814 815 816 817 /* 818 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 819 * struct pcmciabus_attach_args *paa) 820 * 821 * This function attaches 16-bit PCcard bus. 822 */ 823 STATIC void 824 pccbb_pcmcia_attach_setup(sc, paa) 825 struct pccbb_softc *sc; 826 struct pcmciabus_attach_args *paa; 827 { 828 struct pcic_handle *ph = &sc->sc_pcmcia_h; 829 #if rbus 830 rbus_tag_t rb; 831 #endif 832 833 /* initialise pcmcia part in pccbb_softc */ 834 ph->ph_parent = (struct device *)sc; 835 ph->sock = sc->sc_function; 836 ph->flags = 0; 837 ph->shutdown = 0; 838 ph->ih_irq = sc->sc_intrline; 839 ph->ph_bus_t = sc->sc_base_memt; 840 ph->ph_bus_h = sc->sc_base_memh; 841 ph->ph_read = pccbb_pcmcia_read; 842 ph->ph_write = pccbb_pcmcia_write; 843 sc->sc_pct = &pccbb_pcmcia_funcs; 844 845 Pcic_write(ph, PCIC_CSC_INTR, 0); 846 Pcic_read(ph, PCIC_CSC); 847 848 /* initialise pcmcia bus attachment */ 849 paa->paa_busname = "pcmcia"; 850 paa->pct = sc->sc_pct; 851 paa->pch = ph; 852 paa->iobase = 0; /* I don't use them */ 853 paa->iosize = 0; 854 #if rbus 855 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 856 paa->iobase = rb->rb_start + rb->rb_offset; 857 paa->iosize = rb->rb_end - rb->rb_start; 858 #endif 859 860 return; 861 } 862 863 #if 0 864 STATIC void 865 pccbb_pcmcia_attach_card(ph) 866 struct pcic_handle *ph; 867 { 868 if (ph->flags & PCIC_FLAG_CARDP) { 869 panic("pccbb_pcmcia_attach_card: already attached"); 870 } 871 872 /* call the MI attach function */ 873 pcmcia_card_attach(ph->pcmcia); 874 875 ph->flags |= PCIC_FLAG_CARDP; 876 } 877 878 STATIC void 879 pccbb_pcmcia_detach_card(ph, flags) 880 struct pcic_handle *ph; 881 int flags; 882 { 883 if (!(ph->flags & PCIC_FLAG_CARDP)) { 884 panic("pccbb_pcmcia_detach_card: already detached"); 885 } 886 887 ph->flags &= ~PCIC_FLAG_CARDP; 888 889 /* call the MI detach function */ 890 pcmcia_card_detach(ph->pcmcia, flags); 891 } 892 #endif 893 894 /* 895 * int pccbbintr(arg) 896 * void *arg; 897 * This routine handles the interrupt from Yenta PCI-CardBus bridge 898 * itself. 899 */ 900 int 901 pccbbintr(arg) 902 void *arg; 903 { 904 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 905 u_int32_t sockevent; 906 bus_space_tag_t memt = sc->sc_base_memt; 907 bus_space_handle_t memh = sc->sc_base_memh; 908 u_int32_t sockstate; 909 910 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 911 if (0 == sockevent) { 912 /* This intr is not for me: it may be for my child devices. */ 913 return pccbbintr_function(sc); 914 } else { 915 /* reset bit */ 916 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 917 } 918 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 919 920 if (sockevent & CB_SOCKET_EVENT_CD) { 921 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 922 /* A card should be removed. */ 923 if (sc->sc_flags & CBB_CARDEXIST) { 924 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 925 sockevent)); 926 DPRINTF((" card removed, 0x%08x\n", sockstate)); 927 sc->sc_flags &= ~CBB_CARDEXIST; 928 if (sc-> 929 sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) 930 { 931 #if 0 932 struct pcic_handle *ph = 933 &sc->sc_pcmcia_h; 934 935 pcmcia_card_deactivate(ph->pcmcia); 936 pccbb_pcmcia_socket_disable(ph); 937 pccbb_pcmcia_detach_card(ph, 938 DETACH_FORCE); 939 #endif 940 cardslot_event_throw(sc->sc_csc, 941 CARDSLOT_EVENT_REMOVAL_16); 942 } else if (sc-> 943 sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) 944 { 945 /* Cardbus intr removed */ 946 cardslot_event_throw(sc->sc_csc, 947 CARDSLOT_EVENT_REMOVAL_CB); 948 } 949 } 950 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 951 if (sc->sc_flags & CBB_INSERTING) { 952 untimeout(pci113x_insert, sc); 953 } 954 timeout(pci113x_insert, sc, hz / 10); 955 sc->sc_flags |= CBB_INSERTING; 956 } 957 } else { 958 DPRINTF(("%s: sockevent = %b\n", 959 sc->sc_dev.dv_xname, sockevent, PCCBB_SOCKEVENT_BITS)); 960 DPRINTF(("%s: sockstate = %b\n", 961 sc->sc_dev.dv_xname, sockstate, PCCBB_SOCKSTATE_BITS)); 962 } 963 964 return 1; 965 } 966 967 /* 968 * static int pccbbintr_function(struct pccbb_softc *sc) 969 * 970 * This function calls each interrupt handler registered at the 971 * bridge. The interrupt handlers are called in registerd order. 972 */ 973 static int 974 pccbbintr_function(sc) 975 struct pccbb_softc *sc; 976 { 977 int retval = 0, val; 978 struct pccbb_intrhand_list *pil; 979 980 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 981 val = (*pil->pil_func) (pil->pil_arg); 982 retval = retval == 1 ? 1 : 983 retval == 0 ? val : val != 0 ? val : retval; 984 } 985 986 return retval; 987 } 988 989 static void 990 pci113x_insert(arg) 991 void *arg; 992 { 993 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 994 u_int32_t sockevent, sockstate; 995 996 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 997 CB_SOCKET_EVENT); 998 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 999 CB_SOCKET_STAT); 1000 1001 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1002 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1003 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1004 sc->sc_flags |= CBB_CARDEXIST; 1005 /* call pccard intterupt handler here */ 1006 if (sockstate & CB_SOCKET_STAT_16BIT) { 1007 /* 16-bit card found */ 1008 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1009 cardslot_event_throw(sc->sc_csc, 1010 CARDSLOT_EVENT_INSERTION_16); 1011 } else if (sockstate & CB_SOCKET_STAT_CB) { 1012 /* cardbus card fuond */ 1013 /* cardbus_attach_card(sc->sc_csc); */ 1014 cardslot_event_throw(sc->sc_csc, 1015 CARDSLOT_EVENT_INSERTION_CB); 1016 } else { 1017 /* who are you? */ 1018 } 1019 } else { 1020 timeout(pci113x_insert, sc, hz / 10); 1021 } 1022 } 1023 1024 #define PCCBB_PCMCIA_OFFSET 0x800 1025 static u_int8_t 1026 pccbb_pcmcia_read(ph, reg) 1027 struct pcic_handle *ph; 1028 int reg; 1029 { 1030 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1031 PCCBB_PCMCIA_OFFSET + reg); 1032 } 1033 1034 static void 1035 pccbb_pcmcia_write(ph, reg, val) 1036 struct pcic_handle *ph; 1037 int reg; 1038 u_int8_t val; 1039 { 1040 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1041 val); 1042 } 1043 1044 /* 1045 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1046 */ 1047 STATIC int 1048 pccbb_ctrl(ct, command) 1049 cardbus_chipset_tag_t ct; 1050 int command; 1051 { 1052 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1053 1054 switch (command) { 1055 case CARDBUS_CD: 1056 if (2 == pccbb_detect_card(sc)) { 1057 int retval = 0; 1058 int status = cb_detect_voltage(sc); 1059 if (PCCARD_VCC_5V & status) { 1060 retval |= CARDBUS_5V_CARD; 1061 } 1062 if (PCCARD_VCC_3V & status) { 1063 retval |= CARDBUS_3V_CARD; 1064 } 1065 if (PCCARD_VCC_XV & status) { 1066 retval |= CARDBUS_XV_CARD; 1067 } 1068 if (PCCARD_VCC_YV & status) { 1069 retval |= CARDBUS_YV_CARD; 1070 } 1071 return retval; 1072 } else { 1073 return 0; 1074 } 1075 break; 1076 case CARDBUS_RESET: 1077 return cb_reset(sc); 1078 break; 1079 case CARDBUS_IO_ENABLE: /* fallthrough */ 1080 case CARDBUS_IO_DISABLE: /* fallthrough */ 1081 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1082 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1083 case CARDBUS_BM_ENABLE: /* fallthrough */ 1084 case CARDBUS_BM_DISABLE: /* fallthrough */ 1085 return pccbb_cardenable(sc, command); 1086 break; 1087 } 1088 1089 return 0; 1090 } 1091 1092 /* 1093 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1094 * This function returns true when it succeeds and returns false when 1095 * it fails. 1096 */ 1097 STATIC int 1098 pccbb_power(ct, command) 1099 cardbus_chipset_tag_t ct; 1100 int command; 1101 { 1102 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1103 1104 u_int32_t status, sock_ctrl; 1105 bus_space_tag_t memt = sc->sc_base_memt; 1106 bus_space_handle_t memh = sc->sc_base_memh; 1107 1108 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1109 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1110 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1111 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1112 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1113 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1114 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1115 "UNKNOWN", 1116 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1117 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1118 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1119 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1120 "UNKNOWN", command)); 1121 1122 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1123 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1124 1125 switch (command & CARDBUS_VCCMASK) { 1126 case CARDBUS_VCC_UC: 1127 break; 1128 case CARDBUS_VCC_5V: 1129 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1130 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1131 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1132 } else { 1133 printf("%s: BAD voltage request: no 5 V card\n", 1134 sc->sc_dev.dv_xname); 1135 } 1136 break; 1137 case CARDBUS_VCC_3V: 1138 if (CB_SOCKET_STAT_3VCARD & status) { 1139 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1140 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1141 } else { 1142 printf("%s: BAD voltage request: no 3.3 V card\n", 1143 sc->sc_dev.dv_xname); 1144 } 1145 break; 1146 case CARDBUS_VCC_0V: 1147 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1148 break; 1149 default: 1150 return 0; /* power NEVER changed */ 1151 break; 1152 } 1153 1154 switch (command & CARDBUS_VPPMASK) { 1155 case CARDBUS_VPP_UC: 1156 break; 1157 case CARDBUS_VPP_0V: 1158 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1159 break; 1160 case CARDBUS_VPP_VCC: 1161 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1162 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1163 break; 1164 case CARDBUS_VPP_12V: 1165 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1166 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1167 break; 1168 } 1169 1170 #if 0 1171 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1172 #endif 1173 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1174 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1175 1176 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1177 /* 1178 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1179 * time is 20 ms, some PC-Card bridge requires longer duration. 1180 */ 1181 delay(200 * 1000); 1182 1183 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1184 printf 1185 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1186 sc->sc_dev.dv_xname, sock_ctrl, status); 1187 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1188 (command & CARDBUS_VCCMASK) == 1189 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1190 CARDBUS_VCCMASK) == 1191 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1192 CARDBUS_VCCMASK) == 1193 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1194 CARDBUS_VCCMASK) == 1195 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1196 CARDBUS_VCCMASK) == 1197 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1198 CARDBUS_VCCMASK) == 1199 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1200 (command & CARDBUS_VPPMASK) == 1201 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1202 CARDBUS_VPPMASK) == 1203 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1204 CARDBUS_VPPMASK) == 1205 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1206 CARDBUS_VPPMASK) == 1207 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1208 #if 0 1209 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1210 u_int32_t force = 1211 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1212 /* Reset Bad Vcc request */ 1213 force &= ~CB_SOCKET_FORCE_BADVCC; 1214 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1215 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1216 CB_SOCKET_STAT)); 1217 return 1; 1218 } 1219 #endif 1220 return 0; 1221 } 1222 return 1; /* power changed correctly */ 1223 } 1224 1225 #if defined CB_PCMCIA_POLL 1226 struct cb_poll_str { 1227 void *arg; 1228 int (*func) __P((void *)); 1229 int level; 1230 pccard_chipset_tag_t ct; 1231 int count; 1232 }; 1233 1234 static struct cb_poll_str cb_poll[10]; 1235 static int cb_poll_n = 0; 1236 1237 static void cb_pcmcia_poll __P((void *arg)); 1238 1239 static void 1240 cb_pcmcia_poll(arg) 1241 void *arg; 1242 { 1243 struct cb_poll_str *poll = arg; 1244 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1245 struct pccbb_softc *sc = psc->cpc_parent; 1246 int s; 1247 u_int32_t spsr; /* socket present-state reg */ 1248 1249 timeout(cb_pcmcia_poll, arg, hz / 10); 1250 switch (poll->level) { 1251 case IPL_NET: 1252 s = splnet(); 1253 break; 1254 case IPL_BIO: 1255 s = splbio(); 1256 break; 1257 case IPL_TTY: /* fallthrough */ 1258 default: 1259 s = spltty(); 1260 break; 1261 } 1262 1263 spsr = 1264 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1265 CB_SOCKET_STAT); 1266 1267 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1268 if (!(spsr & 0x40)) { /* CINT low */ 1269 #else 1270 if (1) { 1271 #endif 1272 if ((*poll->func) (poll->arg) == 1) { 1273 ++poll->count; 1274 printf("intr: reported from poller, 0x%x\n", spsr); 1275 #if defined LEVEL2 1276 } else { 1277 printf("intr: miss! 0x%x\n", spsr); 1278 #endif 1279 } 1280 } 1281 splx(s); 1282 } 1283 #endif /* defined CB_PCMCIA_POLL */ 1284 1285 /* 1286 * static int pccbb_detect_card(struct pccbb_softc *sc) 1287 * return value: 0 if no card exists. 1288 * 1 if 16-bit card exists. 1289 * 2 if cardbus card exists. 1290 */ 1291 static int 1292 pccbb_detect_card(sc) 1293 struct pccbb_softc *sc; 1294 { 1295 bus_space_handle_t base_memh = sc->sc_base_memh; 1296 bus_space_tag_t base_memt = sc->sc_base_memt; 1297 u_int32_t sockstat = 1298 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1299 int retval = 0; 1300 1301 /* CD1 and CD2 asserted */ 1302 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1303 /* card must be present */ 1304 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1305 /* NOTACARD DEASSERTED */ 1306 if (CB_SOCKET_STAT_CB & sockstat) { 1307 /* CardBus mode */ 1308 retval = 2; 1309 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1310 /* 16-bit mode */ 1311 retval = 1; 1312 } 1313 } 1314 } 1315 return retval; 1316 } 1317 1318 /* 1319 * STATIC int cb_reset(struct pccbb_softc *sc) 1320 * This function resets CardBus card. 1321 */ 1322 STATIC int 1323 cb_reset(sc) 1324 struct pccbb_softc *sc; 1325 { 1326 /* 1327 * Reset Assert at least 20 ms 1328 * Some machines request longer duration. 1329 */ 1330 int reset_duration = 1331 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1332 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1333 1334 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1335 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1336 delay(reset_duration); 1337 1338 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1339 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1340 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1341 delay(reset_duration); 1342 } 1343 /* No card found on the slot. Keep Reset. */ 1344 return 1; 1345 } 1346 1347 /* 1348 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1349 * This function detect card Voltage. 1350 */ 1351 STATIC int 1352 cb_detect_voltage(sc) 1353 struct pccbb_softc *sc; 1354 { 1355 u_int32_t psr; /* socket present-state reg */ 1356 bus_space_tag_t iot = sc->sc_base_memt; 1357 bus_space_handle_t ioh = sc->sc_base_memh; 1358 int vol = PCCARD_VCC_UKN; /* set 0 */ 1359 1360 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1361 1362 if (0x400u & psr) { 1363 vol |= PCCARD_VCC_5V; 1364 } 1365 if (0x800u & psr) { 1366 vol |= PCCARD_VCC_3V; 1367 } 1368 1369 return vol; 1370 } 1371 1372 STATIC int 1373 cbbprint(aux, pcic) 1374 void *aux; 1375 const char *pcic; 1376 { 1377 /* 1378 struct cbslot_attach_args *cba = aux; 1379 1380 if (cba->cba_slot >= 0) { 1381 printf(" slot %d", cba->cba_slot); 1382 } 1383 */ 1384 return UNCONF; 1385 } 1386 1387 /* 1388 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1389 * This function enables and disables the card 1390 */ 1391 STATIC int 1392 pccbb_cardenable(sc, function) 1393 struct pccbb_softc *sc; 1394 int function; 1395 { 1396 u_int32_t command = 1397 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1398 1399 DPRINTF(("pccbb_cardenable:")); 1400 switch (function) { 1401 case CARDBUS_IO_ENABLE: 1402 command |= PCI_COMMAND_IO_ENABLE; 1403 break; 1404 case CARDBUS_IO_DISABLE: 1405 command &= ~PCI_COMMAND_IO_ENABLE; 1406 break; 1407 case CARDBUS_MEM_ENABLE: 1408 command |= PCI_COMMAND_MEM_ENABLE; 1409 break; 1410 case CARDBUS_MEM_DISABLE: 1411 command &= ~PCI_COMMAND_MEM_ENABLE; 1412 break; 1413 case CARDBUS_BM_ENABLE: 1414 command |= PCI_COMMAND_MASTER_ENABLE; 1415 break; 1416 case CARDBUS_BM_DISABLE: 1417 command &= ~PCI_COMMAND_MASTER_ENABLE; 1418 break; 1419 default: 1420 return 0; 1421 } 1422 1423 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1424 DPRINTF((" command reg 0x%x\n", command)); 1425 return 1; 1426 } 1427 1428 #if !rbus 1429 /* 1430 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1431 */ 1432 static int 1433 pccbb_io_open(ct, win, start, end) 1434 cardbus_chipset_tag_t ct; 1435 int win; 1436 u_int32_t start, end; 1437 { 1438 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1439 int basereg; 1440 int limitreg; 1441 1442 if ((win < 0) || (win > 2)) { 1443 #if defined DIAGNOSTIC 1444 printf("cardbus_io_open: window out of range %d\n", win); 1445 #endif 1446 return 0; 1447 } 1448 1449 basereg = win * 8 + 0x2c; 1450 limitreg = win * 8 + 0x30; 1451 1452 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1453 start, basereg, end, limitreg)); 1454 1455 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1456 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1457 return 1; 1458 } 1459 1460 /* 1461 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1462 */ 1463 static int 1464 pccbb_io_close(ct, win) 1465 cardbus_chipset_tag_t ct; 1466 int win; 1467 { 1468 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1469 int basereg; 1470 int limitreg; 1471 1472 if ((win < 0) || (win > 2)) { 1473 #if defined DIAGNOSTIC 1474 printf("cardbus_io_close: window out of range %d\n", win); 1475 #endif 1476 return 0; 1477 } 1478 1479 basereg = win * 8 + 0x2c; 1480 limitreg = win * 8 + 0x30; 1481 1482 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1483 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1484 return 1; 1485 } 1486 1487 /* 1488 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1489 */ 1490 static int 1491 pccbb_mem_open(ct, win, start, end) 1492 cardbus_chipset_tag_t ct; 1493 int win; 1494 u_int32_t start, end; 1495 { 1496 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1497 int basereg; 1498 int limitreg; 1499 1500 if ((win < 0) || (win > 2)) { 1501 #if defined DIAGNOSTIC 1502 printf("cardbus_mem_open: window out of range %d\n", win); 1503 #endif 1504 return 0; 1505 } 1506 1507 basereg = win * 8 + 0x1c; 1508 limitreg = win * 8 + 0x20; 1509 1510 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1511 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1512 return 1; 1513 } 1514 1515 /* 1516 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1517 */ 1518 static int 1519 pccbb_mem_close(ct, win) 1520 cardbus_chipset_tag_t ct; 1521 int win; 1522 { 1523 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1524 int basereg; 1525 int limitreg; 1526 1527 if ((win < 0) || (win > 2)) { 1528 #if defined DIAGNOSTIC 1529 printf("cardbus_mem_close: window out of range %d\n", win); 1530 #endif 1531 return 0; 1532 } 1533 1534 basereg = win * 8 + 0x1c; 1535 limitreg = win * 8 + 0x20; 1536 1537 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1538 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1539 return 1; 1540 } 1541 #endif 1542 1543 /* 1544 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1545 * int irq, 1546 * int level, 1547 * int (* func) __P((void *)), 1548 * void *arg) 1549 * 1550 * This function registers an interrupt handler at the bridge, in 1551 * order not to call the interrput handlers of child devices when 1552 * a card-deletion interrput occurs. 1553 * 1554 * The arguments irq and level are not used. 1555 */ 1556 static void * 1557 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1558 cardbus_chipset_tag_t ct; 1559 int irq, level; 1560 int (*func) __P((void *)); 1561 void *arg; 1562 { 1563 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1564 1565 return pccbb_intr_establish(sc, irq, level, func, arg); 1566 } 1567 1568 1569 /* 1570 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1571 * void *ih) 1572 * 1573 * This function removes an interrupt handler pointed by ih. 1574 */ 1575 static void 1576 pccbb_cb_intr_disestablish(ct, ih) 1577 cardbus_chipset_tag_t ct; 1578 void *ih; 1579 { 1580 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1581 1582 pccbb_intr_disestablish(sc, ih); 1583 } 1584 1585 1586 /* 1587 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1588 * int irq, 1589 * int level, 1590 * int (* func) __P((void *)), 1591 * void *arg) 1592 * 1593 * This function registers an interrupt handler at the bridge, in 1594 * order not to call the interrput handlers of child devices when 1595 * a card-deletion interrput occurs. 1596 * 1597 * The arguments irq and level are not used. 1598 */ 1599 static void * 1600 pccbb_intr_establish(sc, irq, level, func, arg) 1601 struct pccbb_softc *sc; 1602 int irq, level; 1603 int (*func) __P((void *)); 1604 void *arg; 1605 { 1606 struct pccbb_intrhand_list *pil, *newpil; 1607 1608 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1609 1610 if (sc->sc_pil == NULL) { 1611 /* initialise bridge intr routing */ 1612 1613 switch (sc->sc_chipset) { 1614 case CB_TI113X: 1615 { 1616 pcireg_t cbctrl = 1617 pci_conf_read(sc->sc_pc, sc->sc_tag, 1618 PCI_CBCTRL); 1619 /* functional intr enabled */ 1620 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1621 pci_conf_write(sc->sc_pc, sc->sc_tag, 1622 PCI_CBCTRL, cbctrl); 1623 break; 1624 } 1625 default: 1626 break; 1627 } 1628 } 1629 1630 /* 1631 * Allocate a room for interrut handler structure. 1632 */ 1633 if (NULL == (newpil = 1634 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1635 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1636 return NULL; 1637 } 1638 1639 newpil->pil_func = func; 1640 newpil->pil_arg = arg; 1641 newpil->pil_next = NULL; 1642 1643 if (sc->sc_pil == NULL) { 1644 sc->sc_pil = newpil; 1645 } else { 1646 for (pil = sc->sc_pil; pil->pil_next != NULL; 1647 pil = pil->pil_next); 1648 pil->pil_next = newpil; 1649 } 1650 1651 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1652 1653 return newpil; 1654 } 1655 1656 /* 1657 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1658 * void *ih) 1659 * 1660 * This function removes an interrupt handler pointed by ih. 1661 */ 1662 static void 1663 pccbb_intr_disestablish(sc, ih) 1664 struct pccbb_softc *sc; 1665 void *ih; 1666 { 1667 struct pccbb_intrhand_list *pil, **pil_prev; 1668 1669 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1670 1671 pil_prev = &sc->sc_pil; 1672 1673 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1674 if (pil == ih) { 1675 *pil_prev = pil->pil_next; 1676 free(pil, M_DEVBUF); 1677 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1678 break; 1679 } 1680 pil_prev = &pil->pil_next; 1681 } 1682 1683 if (sc->sc_pil == NULL) { 1684 /* No interrupt handlers */ 1685 1686 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1687 1688 switch (sc->sc_chipset) { 1689 case CB_TI113X: 1690 { 1691 pcireg_t cbctrl = 1692 pci_conf_read(sc->sc_pc, sc->sc_tag, 1693 PCI_CBCTRL); 1694 /* functional intr disabled */ 1695 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1696 pci_conf_write(sc->sc_pc, sc->sc_tag, 1697 PCI_CBCTRL, cbctrl); 1698 break; 1699 } 1700 default: 1701 break; 1702 } 1703 } 1704 } 1705 1706 #if defined SHOW_REGS 1707 static void 1708 cb_show_regs(pc, tag, memt, memh) 1709 pci_chipset_tag_t pc; 1710 pcitag_t tag; 1711 bus_space_tag_t memt; 1712 bus_space_handle_t memh; 1713 { 1714 int i; 1715 printf("PCI config regs:"); 1716 for (i = 0; i < 0x50; i += 4) { 1717 if (i % 16 == 0) { 1718 printf("\n 0x%02x:", i); 1719 } 1720 printf(" %08x", pci_conf_read(pc, tag, i)); 1721 } 1722 for (i = 0x80; i < 0xb0; i += 4) { 1723 if (i % 16 == 0) { 1724 printf("\n 0x%02x:", i); 1725 } 1726 printf(" %08x", pci_conf_read(pc, tag, i)); 1727 } 1728 1729 if (memh == 0) { 1730 printf("\n"); 1731 return; 1732 } 1733 1734 printf("\nsocket regs:"); 1735 for (i = 0; i <= 0x10; i += 0x04) { 1736 printf(" %08x", bus_space_read_4(memt, memh, i)); 1737 } 1738 printf("\nExCA regs:"); 1739 for (i = 0; i < 0x08; ++i) { 1740 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1741 } 1742 printf("\n"); 1743 return; 1744 } 1745 #endif 1746 1747 /* 1748 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1749 * int busno, int devno, int function) 1750 * This is the function to make a tag to access config space of 1751 * a CardBus Card. It works same as pci_conf_read. 1752 */ 1753 static cardbustag_t 1754 pccbb_make_tag(cc, busno, devno, function) 1755 cardbus_chipset_tag_t cc; 1756 int busno, devno, function; 1757 { 1758 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1759 1760 return pci_make_tag(sc->sc_pc, busno, devno, function); 1761 } 1762 1763 static void 1764 pccbb_free_tag(cc, tag) 1765 cardbus_chipset_tag_t cc; 1766 cardbustag_t tag; 1767 { 1768 } 1769 1770 /* 1771 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1772 * cardbustag_t tag, int offset) 1773 * This is the function to read the config space of a CardBus Card. 1774 * It works same as pci_conf_read. 1775 */ 1776 static cardbusreg_t 1777 pccbb_conf_read(cc, tag, offset) 1778 cardbus_chipset_tag_t cc; 1779 cardbustag_t tag; 1780 int offset; /* register offset */ 1781 { 1782 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1783 1784 return pci_conf_read(sc->sc_pc, tag, offset); 1785 } 1786 1787 /* 1788 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1789 * int offs, cardbusreg_t val) 1790 * This is the function to write the config space of a CardBus Card. 1791 * It works same as pci_conf_write. 1792 */ 1793 static void 1794 pccbb_conf_write(cc, tag, reg, val) 1795 cardbus_chipset_tag_t cc; 1796 cardbustag_t tag; 1797 int reg; /* register offset */ 1798 cardbusreg_t val; 1799 { 1800 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1801 1802 pci_conf_write(sc->sc_pc, tag, reg, val); 1803 } 1804 1805 #if 0 1806 STATIC int 1807 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1808 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1809 int speed, int flags, 1810 bus_space_handle_t * iohp) 1811 #endif 1812 /* 1813 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1814 * bus_addr_t start, bus_size_t size, 1815 * bus_size_t align, 1816 * struct pcmcia_io_handle *pcihp 1817 * 1818 * This function only allocates I/O region for pccard. This function 1819 * never maps the allcated region to pccard I/O area. 1820 * 1821 * XXX: The interface of this function is not very good, I believe. 1822 */ 1823 STATIC int 1824 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1825 pcmcia_chipset_handle_t pch; 1826 bus_addr_t start; /* start address */ 1827 bus_size_t size; 1828 bus_size_t align; 1829 struct pcmcia_io_handle *pcihp; 1830 { 1831 struct pcic_handle *ph = (struct pcic_handle *)pch; 1832 bus_addr_t ioaddr; 1833 int flags = 0; 1834 bus_space_tag_t iot; 1835 bus_space_handle_t ioh; 1836 #if rbus 1837 rbus_tag_t rb; 1838 #endif 1839 if (align == 0) { 1840 align = size; /* XXX: funny??? */ 1841 } 1842 1843 /* 1844 * Allocate some arbitrary I/O space. 1845 */ 1846 1847 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1848 1849 #if rbus 1850 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1851 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1852 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1853 return 1; 1854 } 1855 #else 1856 if (start) { 1857 ioaddr = start; 1858 if (bus_space_map(iot, start, size, 0, &ioh)) { 1859 return 1; 1860 } 1861 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1862 (u_long) ioaddr, (u_long) size)); 1863 } else { 1864 flags |= PCMCIA_IO_ALLOCATED; 1865 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1866 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1867 size, align, 0, 0, &ioaddr, &ioh)) { 1868 /* No room be able to be get. */ 1869 return 1; 1870 } 1871 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1872 (u_long) ioaddr, (u_long) size)); 1873 } 1874 #endif 1875 1876 pcihp->iot = iot; 1877 pcihp->ioh = ioh; 1878 pcihp->addr = ioaddr; 1879 pcihp->size = size; 1880 pcihp->flags = flags; 1881 1882 return 0; 1883 } 1884 1885 /* 1886 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1887 * struct pcmcia_io_handle *pcihp) 1888 * 1889 * This function only frees I/O region for pccard. 1890 * 1891 * XXX: The interface of this function is not very good, I believe. 1892 */ 1893 void 1894 pccbb_pcmcia_io_free(pch, pcihp) 1895 pcmcia_chipset_handle_t pch; 1896 struct pcmcia_io_handle *pcihp; 1897 { 1898 #if !rbus 1899 bus_space_tag_t iot = pcihp->iot; 1900 #endif 1901 bus_space_handle_t ioh = pcihp->ioh; 1902 bus_size_t size = pcihp->size; 1903 1904 #if rbus 1905 struct pccbb_softc *sc = 1906 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1907 rbus_tag_t rb = sc->sc_rbus_iot; 1908 1909 rbus_space_free(rb, ioh, size, NULL); 1910 #else 1911 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1912 bus_space_free(iot, ioh, size); 1913 else 1914 bus_space_unmap(iot, ioh, size); 1915 #endif 1916 } 1917 1918 /* 1919 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1920 * bus_addr_t offset, bus_size_t size, 1921 * struct pcmcia_io_handle *pcihp, 1922 * int *windowp) 1923 * 1924 * This function maps the allocated I/O region to pccard. This function 1925 * never allocates any I/O region for pccard I/O area. I don't 1926 * understand why the original authors of pcmciabus separated alloc and 1927 * map. I believe the two must be unite. 1928 * 1929 * XXX: no wait timing control? 1930 */ 1931 int 1932 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1933 pcmcia_chipset_handle_t pch; 1934 int width; 1935 bus_addr_t offset; 1936 bus_size_t size; 1937 struct pcmcia_io_handle *pcihp; 1938 int *windowp; 1939 { 1940 struct pcic_handle *ph = (struct pcic_handle *)pch; 1941 bus_addr_t ioaddr = pcihp->addr + offset; 1942 int i, win; 1943 #if defined CBB_DEBUG 1944 static char *width_names[] = { "dynamic", "io8", "io16" }; 1945 #endif 1946 1947 /* Sanity check I/O handle. */ 1948 1949 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1950 panic("pccbb_pcmcia_io_map iot is bogus"); 1951 } 1952 1953 /* XXX Sanity check offset/size. */ 1954 1955 win = -1; 1956 for (i = 0; i < PCIC_IO_WINS; i++) { 1957 if ((ph->ioalloc & (1 << i)) == 0) { 1958 win = i; 1959 ph->ioalloc |= (1 << i); 1960 break; 1961 } 1962 } 1963 1964 if (win == -1) { 1965 return 1; 1966 } 1967 1968 *windowp = win; 1969 1970 /* XXX this is pretty gross */ 1971 1972 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1973 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1974 1975 /* XXX wtf is this doing here? */ 1976 1977 #if 0 1978 printf(" port 0x%lx", (u_long) ioaddr); 1979 if (size > 1) { 1980 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1981 } 1982 #endif 1983 1984 ph->io[win].addr = ioaddr; 1985 ph->io[win].size = size; 1986 ph->io[win].width = width; 1987 1988 /* actual dirty register-value changing in the function below. */ 1989 pccbb_pcmcia_do_io_map(ph, win); 1990 1991 return 0; 1992 } 1993 1994 /* 1995 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1996 * 1997 * This function changes register-value to map I/O region for pccard. 1998 */ 1999 static void 2000 pccbb_pcmcia_do_io_map(ph, win) 2001 struct pcic_handle *ph; 2002 int win; 2003 { 2004 static u_int8_t pcic_iowidth[3] = { 2005 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2006 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2007 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2008 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2009 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2010 }; 2011 2012 #define PCIC_SIA_START_LOW 0 2013 #define PCIC_SIA_START_HIGH 1 2014 #define PCIC_SIA_STOP_LOW 2 2015 #define PCIC_SIA_STOP_HIGH 3 2016 2017 int regbase_win = 0x8 + win * 0x04; 2018 u_int8_t ioctl, enable; 2019 2020 DPRINTF( 2021 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2022 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2023 ph->io[win].width * 8)); 2024 2025 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2026 ph->io[win].addr & 0xff); 2027 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2028 (ph->io[win].addr >> 8) & 0xff); 2029 2030 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2031 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2032 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2033 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2034 2035 ioctl = Pcic_read(ph, PCIC_IOCTL); 2036 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2037 switch (win) { 2038 case 0: 2039 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2040 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2041 PCIC_IOCTL_IO0_DATASIZE_MASK); 2042 ioctl |= pcic_iowidth[ph->io[win].width]; 2043 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2044 break; 2045 case 1: 2046 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2047 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2048 PCIC_IOCTL_IO1_DATASIZE_MASK); 2049 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2050 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2051 break; 2052 } 2053 Pcic_write(ph, PCIC_IOCTL, ioctl); 2054 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2055 #if defined CBB_DEBUG 2056 { 2057 u_int8_t start_low = 2058 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2059 u_int8_t start_high = 2060 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2061 u_int8_t stop_low = 2062 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2063 u_int8_t stop_high = 2064 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2065 printf 2066 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2067 start_low, start_high, stop_low, stop_high, ioctl, enable); 2068 } 2069 #endif 2070 } 2071 2072 /* 2073 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2074 * 2075 * This function unmapss I/O region. No return value. 2076 */ 2077 STATIC void 2078 pccbb_pcmcia_io_unmap(pch, win) 2079 pcmcia_chipset_handle_t pch; 2080 int win; 2081 { 2082 struct pcic_handle *ph = (struct pcic_handle *)pch; 2083 int reg; 2084 2085 if (win >= PCIC_IO_WINS || win < 0) { 2086 panic("pccbb_pcmcia_io_unmap: window out of range"); 2087 } 2088 2089 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2090 switch (win) { 2091 case 0: 2092 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2093 break; 2094 case 1: 2095 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2096 break; 2097 } 2098 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2099 2100 ph->ioalloc &= ~(1 << win); 2101 } 2102 2103 /* 2104 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2105 * 2106 * This function enables the card. All information is stored in 2107 * the first argument, pcmcia_chipset_handle_t. 2108 */ 2109 static void 2110 pccbb_pcmcia_wait_ready(ph) 2111 struct pcic_handle *ph; 2112 { 2113 int i; 2114 2115 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2116 Pcic_read(ph, PCIC_IF_STATUS))); 2117 2118 for (i = 0; i < 10000; i++) { 2119 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2120 return; 2121 } 2122 delay(500); 2123 #ifdef CBB_DEBUG 2124 if ((i > 5000) && (i % 100 == 99)) 2125 printf("."); 2126 #endif 2127 } 2128 2129 #ifdef DIAGNOSTIC 2130 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2131 Pcic_read(ph, PCIC_IF_STATUS)); 2132 #endif 2133 } 2134 2135 /* 2136 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2137 * 2138 * This function enables the card. All information is stored in 2139 * the first argument, pcmcia_chipset_handle_t. 2140 */ 2141 STATIC void 2142 pccbb_pcmcia_socket_enable(pch) 2143 pcmcia_chipset_handle_t pch; 2144 { 2145 struct pcic_handle *ph = (struct pcic_handle *)pch; 2146 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2147 int cardtype, win; 2148 u_int8_t power, intr; 2149 pcireg_t spsr; 2150 int voltage; 2151 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2152 2153 /* this bit is mostly stolen from pcic_attach_card */ 2154 2155 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2156 2157 /* get card Vcc info */ 2158 2159 spsr = 2160 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2161 CB_SOCKET_STAT); 2162 if (spsr & CB_SOCKET_STAT_5VCARD) { 2163 DPRINTF(("5V card\n")); 2164 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2165 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2166 DPRINTF(("3V card\n")); 2167 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2168 } else { 2169 printf("?V card, 0x%x\n", spsr); /* XXX */ 2170 return; 2171 } 2172 2173 /* assert reset bit */ 2174 intr = Pcic_read(ph, PCIC_INTR); 2175 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2176 Pcic_write(ph, PCIC_INTR, intr); 2177 2178 /* disable socket i/o: negate output enable bit */ 2179 2180 power = Pcic_read(ph, PCIC_PWRCTL); 2181 power &= ~PCIC_PWRCTL_OE; 2182 Pcic_write(ph, PCIC_PWRCTL, power); 2183 2184 /* power down the socket to reset it, clear the card reset pin */ 2185 2186 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2187 2188 /* 2189 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2190 * we are changing Vcc (Toff). 2191 */ 2192 /* delay(300*1000); too much */ 2193 2194 /* power up the socket */ 2195 pccbb_power(sc, voltage); 2196 2197 /* 2198 * wait 100ms until power raise (Tpr) and 20ms to become 2199 * stable (Tsu(Vcc)). 2200 * 2201 * some machines require some more time to be settled 2202 * (another 200ms is added here). 2203 */ 2204 /* delay((100 + 20 + 200)*1000); too much */ 2205 2206 power = Pcic_read(ph, PCIC_PWRCTL); 2207 power |= PCIC_PWRCTL_OE; 2208 Pcic_write(ph, PCIC_PWRCTL, power); 2209 2210 /* 2211 * hold RESET at least 10us. 2212 */ 2213 delay(10); 2214 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2215 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2216 2217 /* clear the reset flag */ 2218 2219 intr |= PCIC_INTR_RESET; 2220 Pcic_write(ph, PCIC_INTR, intr); 2221 2222 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2223 2224 delay(20000); 2225 2226 /* wait for the chip to finish initializing */ 2227 2228 pccbb_pcmcia_wait_ready(ph); 2229 2230 /* zero out the address windows */ 2231 2232 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2233 2234 /* set the card type */ 2235 2236 cardtype = pcmcia_card_gettype(ph->pcmcia); 2237 2238 intr |= PCIC_INTR_PCI; 2239 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2240 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2241 Pcic_write(ph, PCIC_INTR, intr); 2242 2243 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2244 ph->ph_parent->dv_xname, ph->sock, 2245 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2246 2247 /* reinstall all the memory and io mappings */ 2248 2249 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2250 if (ph->memalloc & (1 << win)) { 2251 pccbb_pcmcia_do_mem_map(ph, win); 2252 } 2253 } 2254 2255 for (win = 0; win < PCIC_IO_WINS; ++win) { 2256 if (ph->ioalloc & (1 << win)) { 2257 pccbb_pcmcia_do_io_map(ph, win); 2258 } 2259 } 2260 } 2261 2262 /* 2263 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2264 * 2265 * This function disables the card. All information is stored in 2266 * the first argument, pcmcia_chipset_handle_t. 2267 */ 2268 STATIC void 2269 pccbb_pcmcia_socket_disable(pch) 2270 pcmcia_chipset_handle_t pch; 2271 { 2272 struct pcic_handle *ph = (struct pcic_handle *)pch; 2273 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2274 u_int8_t power, intr; 2275 2276 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2277 2278 /* reset signal asserting... */ 2279 2280 intr = Pcic_read(ph, PCIC_INTR); 2281 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_ENABLE | PCIC_INTR_CARDTYPE_MASK); 2282 Pcic_write(ph, PCIC_INTR, intr); 2283 delay(2 * 1000); 2284 2285 /* power down the socket */ 2286 power = Pcic_read(ph, PCIC_PWRCTL); 2287 power &= ~PCIC_PWRCTL_OE; 2288 Pcic_write(ph, PCIC_PWRCTL, power); 2289 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2290 /* 2291 * wait 300ms until power fails (Tpf). 2292 */ 2293 delay(300 * 1000); 2294 } 2295 2296 /* 2297 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2298 * 2299 * This function detects whether a card is in the slot or not. 2300 * If a card is inserted, return 1. Otherwise, return 0. 2301 */ 2302 STATIC int 2303 pccbb_pcmcia_card_detect(pch) 2304 pcmcia_chipset_handle_t pch; 2305 { 2306 struct pcic_handle *ph = (struct pcic_handle *)pch; 2307 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2308 2309 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2310 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2311 } 2312 2313 #if 0 2314 STATIC int 2315 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2316 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2317 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2318 #endif 2319 /* 2320 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2321 * bus_size_t size, 2322 * struct pcmcia_mem_handle *pcmhp) 2323 * 2324 * This function only allocates memory region for pccard. This 2325 * function never maps the allcated region to pccard memory area. 2326 * 2327 * XXX: Why the argument of start address is not in? 2328 */ 2329 STATIC int 2330 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2331 pcmcia_chipset_handle_t pch; 2332 bus_size_t size; 2333 struct pcmcia_mem_handle *pcmhp; 2334 { 2335 struct pcic_handle *ph = (struct pcic_handle *)pch; 2336 bus_space_handle_t memh; 2337 bus_addr_t addr; 2338 bus_size_t sizepg; 2339 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2340 #if rbus 2341 rbus_tag_t rb; 2342 #endif 2343 2344 /* out of sc->memh, allocate as many pages as necessary */ 2345 2346 /* convert size to PCIC pages */ 2347 /* 2348 * This is not enough; when the requested region is on the page 2349 * boundaries, this may calculate wrong result. 2350 */ 2351 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2352 #if 0 2353 if (sizepg > PCIC_MAX_MEM_PAGES) { 2354 return 1; 2355 } 2356 #endif 2357 2358 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2359 return 1; 2360 } 2361 2362 addr = 0; /* XXX gcc -Wuninitialized */ 2363 2364 #if rbus 2365 rb = sc->sc_rbus_memt; 2366 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2367 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2368 &addr, &memh)) { 2369 return 1; 2370 } 2371 #else 2372 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2373 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2374 0, /* boundary */ 2375 0, /* flags */ 2376 &addr, &memh)) { 2377 return 1; 2378 } 2379 #endif 2380 2381 DPRINTF( 2382 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2383 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2384 2385 pcmhp->memt = sc->sc_memt; 2386 pcmhp->memh = memh; 2387 pcmhp->addr = addr; 2388 pcmhp->size = size; 2389 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2390 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2391 pcmhp->mhandle = 0; 2392 /* No offset??? Funny. */ 2393 2394 return 0; 2395 } 2396 2397 /* 2398 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2399 * struct pcmcia_mem_handle *pcmhp) 2400 * 2401 * This function release the memory space allocated by the fuction 2402 * pccbb_pcmcia_mem_alloc(). 2403 */ 2404 STATIC void 2405 pccbb_pcmcia_mem_free(pch, pcmhp) 2406 pcmcia_chipset_handle_t pch; 2407 struct pcmcia_mem_handle *pcmhp; 2408 { 2409 #if rbus 2410 struct pcic_handle *ph = (struct pcic_handle *)pch; 2411 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2412 2413 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2414 #else 2415 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2416 #endif 2417 } 2418 2419 /* 2420 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2421 * 2422 * This function release the memory space allocated by the fuction 2423 * pccbb_pcmcia_mem_alloc(). 2424 */ 2425 STATIC void 2426 pccbb_pcmcia_do_mem_map(ph, win) 2427 struct pcic_handle *ph; 2428 int win; 2429 { 2430 int regbase_win; 2431 bus_addr_t phys_addr; 2432 bus_addr_t phys_end; 2433 2434 #define PCIC_SMM_START_LOW 0 2435 #define PCIC_SMM_START_HIGH 1 2436 #define PCIC_SMM_STOP_LOW 2 2437 #define PCIC_SMM_STOP_HIGH 3 2438 #define PCIC_CMA_LOW 4 2439 #define PCIC_CMA_HIGH 5 2440 2441 u_int8_t start_low, start_high = 0; 2442 u_int8_t stop_low, stop_high; 2443 u_int8_t off_low, off_high; 2444 u_int8_t mem_window; 2445 int reg; 2446 2447 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2448 int mem8 = 2449 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2450 || (kind == PCMCIA_MEM_ATTR); 2451 2452 regbase_win = 0x10 + win * 0x08; 2453 2454 phys_addr = ph->mem[win].addr; 2455 phys_end = phys_addr + ph->mem[win].size; 2456 2457 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2458 phys_addr, phys_end, ph->mem[win].offset)); 2459 2460 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2461 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2462 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2463 2464 /* bit 19:12 */ 2465 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2466 /* bit 23:20 and bit 7 on */ 2467 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2468 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2469 /* bit 31:24, for 32-bit address */ 2470 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2471 2472 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2473 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2474 2475 if (((struct pccbb_softc *)ph-> 2476 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2477 Pcic_write(ph, 0x40 + win, mem_window); 2478 } 2479 2480 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2481 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2482 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2483 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2484 2485 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2486 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2487 2488 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2489 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2490 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2491 | ((kind == PCMCIA_MEM_ATTR) ? 2492 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2493 2494 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2495 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2496 2497 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2498 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2499 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2500 2501 #if defined CBB_DEBUG 2502 { 2503 int r1, r2, r3, r4, r5, r6, r7 = 0; 2504 2505 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2506 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2507 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2508 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2509 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2510 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2511 if (((struct pccbb_softc *)(ph-> 2512 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2513 r7 = Pcic_read(ph, 0x40 + win); 2514 } 2515 2516 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2517 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2518 if (((struct pccbb_softc *)(ph-> 2519 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2520 DPRINTF((" %02x", r7)); 2521 } 2522 DPRINTF(("\n")); 2523 } 2524 #endif 2525 } 2526 2527 /* 2528 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2529 * bus_addr_t card_addr, bus_size_t size, 2530 * struct pcmcia_mem_handle *pcmhp, 2531 * bus_addr_t *offsetp, int *windowp) 2532 * 2533 * This function maps memory space allocated by the fuction 2534 * pccbb_pcmcia_mem_alloc(). 2535 */ 2536 STATIC int 2537 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2538 pcmcia_chipset_handle_t pch; 2539 int kind; 2540 bus_addr_t card_addr; 2541 bus_size_t size; 2542 struct pcmcia_mem_handle *pcmhp; 2543 bus_addr_t *offsetp; 2544 int *windowp; 2545 { 2546 struct pcic_handle *ph = (struct pcic_handle *)pch; 2547 bus_addr_t busaddr; 2548 long card_offset; 2549 int win; 2550 2551 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2552 if ((ph->memalloc & (1 << win)) == 0) { 2553 ph->memalloc |= (1 << win); 2554 break; 2555 } 2556 } 2557 2558 if (win == PCIC_MEM_WINS) { 2559 return 1; 2560 } 2561 2562 *windowp = win; 2563 2564 /* XXX this is pretty gross */ 2565 2566 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2567 panic("pccbb_pcmcia_mem_map memt is bogus"); 2568 } 2569 2570 busaddr = pcmhp->addr; 2571 2572 /* 2573 * compute the address offset to the pcmcia address space for the 2574 * pcic. this is intentionally signed. The masks and shifts below 2575 * will cause TRT to happen in the pcic registers. Deal with making 2576 * sure the address is aligned, and return the alignment offset. 2577 */ 2578 2579 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2580 card_addr -= *offsetp; 2581 2582 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2583 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2584 (u_long) card_addr)); 2585 2586 /* 2587 * include the offset in the size, and decrement size by one, since 2588 * the hw wants start/stop 2589 */ 2590 size += *offsetp - 1; 2591 2592 card_offset = (((long)card_addr) - ((long)busaddr)); 2593 2594 ph->mem[win].addr = busaddr; 2595 ph->mem[win].size = size; 2596 ph->mem[win].offset = card_offset; 2597 ph->mem[win].kind = kind; 2598 2599 pccbb_pcmcia_do_mem_map(ph, win); 2600 2601 return 0; 2602 } 2603 2604 /* 2605 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2606 * int window) 2607 * 2608 * This function unmaps memory space which mapped by the fuction 2609 * pccbb_pcmcia_mem_map(). 2610 */ 2611 STATIC void 2612 pccbb_pcmcia_mem_unmap(pch, window) 2613 pcmcia_chipset_handle_t pch; 2614 int window; 2615 { 2616 struct pcic_handle *ph = (struct pcic_handle *)pch; 2617 int reg; 2618 2619 if (window >= PCIC_MEM_WINS) { 2620 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2621 } 2622 2623 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2624 reg &= ~(1 << window); 2625 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2626 2627 ph->memalloc &= ~(1 << window); 2628 } 2629 2630 #if defined PCCBB_PCMCIA_POLL 2631 struct pccbb_poll_str { 2632 void *arg; 2633 int (*func) __P((void *)); 2634 int level; 2635 struct pcic_handle *ph; 2636 int count; 2637 int num; 2638 }; 2639 2640 static struct pccbb_poll_str pccbb_poll[10]; 2641 static int pccbb_poll_n = 0; 2642 2643 static void pccbb_pcmcia_poll __P((void *arg)); 2644 2645 static void 2646 pccbb_pcmcia_poll(arg) 2647 void *arg; 2648 { 2649 struct pccbb_poll_str *poll = arg; 2650 struct pcic_handle *ph = poll->ph; 2651 struct pccbb_softc *sc = ph->sc; 2652 int s; 2653 u_int32_t spsr; /* socket present-state reg */ 2654 2655 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2656 switch (poll->level) { 2657 case IPL_NET: 2658 s = splnet(); 2659 break; 2660 case IPL_BIO: 2661 s = splbio(); 2662 break; 2663 case IPL_TTY: /* fallthrough */ 2664 default: 2665 s = spltty(); 2666 break; 2667 } 2668 2669 spsr = 2670 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2671 CB_SOCKET_STAT); 2672 2673 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2674 if (!(spsr & 0x40)) /* CINT low */ 2675 #else 2676 if (1) 2677 #endif 2678 { 2679 if ((*poll->func) (poll->arg) > 0) { 2680 ++poll->count; 2681 // printf("intr: reported from poller, 0x%x\n", spsr); 2682 #if defined LEVEL2 2683 } else { 2684 printf("intr: miss! 0x%x\n", spsr); 2685 #endif 2686 } 2687 } 2688 splx(s); 2689 } 2690 #endif /* defined CB_PCMCIA_POLL */ 2691 2692 /* 2693 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2694 * struct pcmcia_function *pf, 2695 * int ipl, 2696 * int (*func)(void *), 2697 * void *arg); 2698 * 2699 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2700 */ 2701 STATIC void * 2702 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2703 pcmcia_chipset_handle_t pch; 2704 struct pcmcia_function *pf; 2705 int ipl; 2706 int (*func) __P((void *)); 2707 void *arg; 2708 { 2709 struct pcic_handle *ph = (struct pcic_handle *)pch; 2710 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2711 2712 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2713 /* what should I do? */ 2714 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2715 DPRINTF( 2716 ("%s does not provide edge nor pulse interrupt\n", 2717 sc->sc_dev.dv_xname)); 2718 return NULL; 2719 } 2720 /* 2721 * XXX Noooooo! The interrupt flag must set properly!! 2722 * dumb pcmcia driver!! 2723 */ 2724 } 2725 2726 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2727 } 2728 2729 /* 2730 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2731 * void *ih) 2732 * 2733 * This function disables PC-Card interrupt. 2734 */ 2735 STATIC void 2736 pccbb_pcmcia_intr_disestablish(pch, ih) 2737 pcmcia_chipset_handle_t pch; 2738 void *ih; 2739 { 2740 struct pcic_handle *ph = (struct pcic_handle *)pch; 2741 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2742 2743 pccbb_intr_disestablish(sc, ih); 2744 } 2745 2746 #if rbus 2747 /* 2748 * static int 2749 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2750 * bus_addr_t addr, bus_size_t size, 2751 * bus_addr_t mask, bus_size_t align, 2752 * int flags, bus_addr_t *addrp; 2753 * bus_space_handle_t *bshp) 2754 * 2755 * This function allocates a portion of memory or io space for 2756 * clients. This function is called from CardBus card drivers. 2757 */ 2758 static int 2759 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2760 cardbus_chipset_tag_t ct; 2761 rbus_tag_t rb; 2762 bus_addr_t addr; 2763 bus_size_t size; 2764 bus_addr_t mask; 2765 bus_size_t align; 2766 int flags; 2767 bus_addr_t *addrp; 2768 bus_space_handle_t *bshp; 2769 { 2770 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2771 2772 DPRINTF( 2773 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2774 addr, size, mask, align)); 2775 2776 if (align == 0) { 2777 align = size; 2778 } 2779 2780 if (rb->rb_bt == sc->sc_memt) { 2781 if (align < 16) { 2782 return 1; 2783 } 2784 } else if (rb->rb_bt == sc->sc_iot) { 2785 if (align < 4) { 2786 return 1; 2787 } 2788 } else { 2789 DPRINTF( 2790 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2791 rb->rb_bt)); 2792 return 1; 2793 /* XXX: panic here? */ 2794 } 2795 2796 /* XXX: hack for avoiding ISA image */ 2797 if (mask < 0x3ff) { 2798 mask = 0x3ff; 2799 addr = 0x300; 2800 } 2801 2802 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2803 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2804 return 1; 2805 } 2806 2807 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2808 2809 return 0; 2810 } 2811 2812 /* 2813 * static int 2814 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2815 * bus_space_handle_t *bshp, bus_size_t size); 2816 * 2817 * This function is called from CardBus card drivers. 2818 */ 2819 static int 2820 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2821 cardbus_chipset_tag_t ct; 2822 rbus_tag_t rb; 2823 bus_space_handle_t bsh; 2824 bus_size_t size; 2825 { 2826 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2827 bus_space_tag_t bt = rb->rb_bt; 2828 2829 pccbb_close_win(sc, bt, bsh, size); 2830 2831 if (bt == sc->sc_memt) { 2832 } else if (bt == sc->sc_iot) { 2833 } else { 2834 return 1; 2835 /* XXX: panic here? */ 2836 } 2837 2838 return rbus_space_free(rb, bsh, size, NULL); 2839 } 2840 #endif /* rbus */ 2841 2842 #if rbus 2843 2844 static int 2845 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2846 struct pccbb_softc *sc; 2847 bus_space_tag_t bst; 2848 bus_addr_t addr; 2849 bus_size_t size; 2850 bus_space_handle_t bsh; 2851 int flags; 2852 { 2853 struct pccbb_win_chain_head *head; 2854 bus_addr_t align; 2855 2856 head = &sc->sc_iowindow; 2857 align = 0x04; 2858 if (sc->sc_memt == bst) { 2859 head = &sc->sc_memwindow; 2860 align = 0x1000; 2861 DPRINTF(("using memory window, %x %x %x\n\n", 2862 sc->sc_iot, sc->sc_memt, bst)); 2863 } 2864 2865 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2866 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2867 sc->sc_dev.dv_xname, 2868 (head == &sc->sc_memwindow) ? "mem" : "io"); 2869 } 2870 pccbb_winset(align, sc, bst); 2871 2872 return 0; 2873 } 2874 2875 static int 2876 pccbb_close_win(sc, bst, bsh, size) 2877 struct pccbb_softc *sc; 2878 bus_space_tag_t bst; 2879 bus_space_handle_t bsh; 2880 bus_size_t size; 2881 { 2882 struct pccbb_win_chain_head *head; 2883 bus_addr_t align; 2884 2885 head = &sc->sc_iowindow; 2886 align = 0x04; 2887 if (sc->sc_memt == bst) { 2888 head = &sc->sc_memwindow; 2889 align = 0x1000; 2890 } 2891 2892 if (pccbb_winlist_delete(head, bsh, size)) { 2893 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2894 sc->sc_dev.dv_xname, 2895 (head == &sc->sc_memwindow) ? "mem" : "io"); 2896 } 2897 pccbb_winset(align, sc, bst); 2898 2899 return 0; 2900 } 2901 2902 static int 2903 pccbb_winlist_insert(head, start, size, bsh, flags) 2904 struct pccbb_win_chain_head *head; 2905 bus_addr_t start; 2906 bus_size_t size; 2907 bus_space_handle_t bsh; 2908 int flags; 2909 { 2910 struct pccbb_win_chain *chainp, *elem; 2911 2912 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2913 M_NOWAIT)) == NULL) 2914 return 1; /* fail */ 2915 2916 elem->wc_start = start; 2917 elem->wc_end = start + (size - 1); 2918 elem->wc_handle = bsh; 2919 elem->wc_flags = flags; 2920 2921 if ((chainp = TAILQ_FIRST(head)) == NULL) { 2922 TAILQ_INSERT_HEAD(head, elem, wc_list); 2923 return 0; 2924 } 2925 2926 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2927 if (chainp->wc_end < start) 2928 continue; 2929 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2930 return 0; 2931 } 2932 2933 TAILQ_INSERT_TAIL(head, elem, wc_list); 2934 2935 return 0; 2936 } 2937 2938 static int 2939 pccbb_winlist_delete(head, bsh, size) 2940 struct pccbb_win_chain_head *head; 2941 bus_space_handle_t bsh; 2942 bus_size_t size; 2943 { 2944 struct pccbb_win_chain *chainp; 2945 2946 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2947 chainp = TAILQ_NEXT(chainp, wc_list)) { 2948 if (chainp->wc_handle != bsh) 2949 continue; 2950 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2951 printf("pccbb_winlist_delete: window 0x%lx size " 2952 "inconsistent: 0x%lx, 0x%lx\n", 2953 chainp->wc_start, 2954 chainp->wc_end - chainp->wc_start, 2955 size - 1); 2956 return 1; 2957 } 2958 2959 TAILQ_REMOVE(head, chainp, wc_list); 2960 free(chainp, M_DEVBUF); 2961 2962 return 0; 2963 } 2964 2965 return 1; /* fail: no candidate to remove */ 2966 } 2967 2968 static void 2969 pccbb_winset(align, sc, bst) 2970 bus_addr_t align; 2971 struct pccbb_softc *sc; 2972 bus_space_tag_t bst; 2973 { 2974 pci_chipset_tag_t pc; 2975 pcitag_t tag; 2976 bus_addr_t mask = ~(align - 1); 2977 struct { 2978 cardbusreg_t win_start; 2979 cardbusreg_t win_limit; 2980 int win_flags; 2981 } win[2]; 2982 struct pccbb_win_chain *chainp; 2983 int offs; 2984 2985 win[0].win_start = 0xffffffff; 2986 win[0].win_limit = 0; 2987 win[1].win_start = 0xffffffff; 2988 win[1].win_limit = 0; 2989 2990 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2991 offs = 0x2c; 2992 if (sc->sc_memt == bst) { 2993 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2994 offs = 0x1c; 2995 } 2996 2997 if (chainp != NULL) { 2998 win[0].win_start = chainp->wc_start & mask; 2999 win[0].win_limit = chainp->wc_end & mask; 3000 win[0].win_flags = chainp->wc_flags; 3001 chainp = TAILQ_NEXT(chainp, wc_list); 3002 } 3003 3004 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3005 if (win[1].win_start == 0xffffffff) { 3006 /* window 1 is not used */ 3007 if ((win[0].win_flags == chainp->wc_flags) && 3008 (win[0].win_limit + align >= 3009 (chainp->wc_start & mask))) { 3010 /* concatenate */ 3011 win[0].win_limit = chainp->wc_end & mask; 3012 } else { 3013 /* make new window */ 3014 win[1].win_start = chainp->wc_start & mask; 3015 win[1].win_limit = chainp->wc_end & mask; 3016 win[1].win_flags = chainp->wc_flags; 3017 } 3018 continue; 3019 } 3020 3021 /* Both windows are engagad. */ 3022 if (win[0].win_flags == win[1].win_flags) { 3023 /* same flags */ 3024 if (win[0].win_flags == chainp->wc_flags) { 3025 if (win[1].win_start - (win[0].win_limit + 3026 align) < 3027 (chainp->wc_start & mask) - 3028 ((chainp->wc_end & mask) + align)) { 3029 /* 3030 * merge window 0 and 1, and set win1 3031 * to chainp 3032 */ 3033 win[0].win_limit = win[1].win_limit; 3034 win[1].win_start = 3035 chainp->wc_start & mask; 3036 win[1].win_limit = 3037 chainp->wc_end & mask; 3038 } else { 3039 win[1].win_limit = 3040 chainp->wc_end & mask; 3041 } 3042 } else { 3043 /* different flags */ 3044 3045 /* concatenate win0 and win1 */ 3046 win[0].win_limit = win[1].win_limit; 3047 /* allocate win[1] to new space */ 3048 win[1].win_start = chainp->wc_start & mask; 3049 win[1].win_limit = chainp->wc_end & mask; 3050 win[1].win_flags = chainp->wc_flags; 3051 } 3052 } else { 3053 /* the flags of win[0] and win[1] is different */ 3054 if (win[0].win_flags == chainp->wc_flags) { 3055 win[0].win_limit = chainp->wc_end & mask; 3056 /* 3057 * XXX this creates overlapping windows, so 3058 * what should the poor bridge do if one is 3059 * cachable, and the other is not? 3060 */ 3061 printf("%s: overlapping windows\n", 3062 sc->sc_dev.dv_xname); 3063 } else { 3064 win[1].win_limit = chainp->wc_end & mask; 3065 } 3066 } 3067 } 3068 3069 pc = sc->sc_pc; 3070 tag = sc->sc_tag; 3071 pci_conf_write(pc, tag, offs, win[0].win_start); 3072 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3073 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3074 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3075 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3076 pci_conf_read(pc, tag, offs), 3077 pci_conf_read(pc, tag, offs + 4) + align, 3078 pci_conf_read(pc, tag, offs + 8), 3079 pci_conf_read(pc, tag, offs + 12) + align)); 3080 3081 if (bst == sc->sc_memt) { 3082 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3083 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3084 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3085 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3086 } 3087 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3088 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3089 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3090 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3091 } 3092 } 3093 } 3094 3095 #endif /* rbus */ 3096 3097 static void 3098 pccbb_powerhook(why, arg) 3099 int why; 3100 void *arg; 3101 { 3102 struct pccbb_softc *sc = arg; 3103 u_int32_t reg; 3104 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3105 bus_space_handle_t base_memh = sc->sc_base_memh; 3106 3107 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3108 3109 if (why == PWR_RESUME) { 3110 /* CSC Interrupt: Card detect interrupt on */ 3111 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3112 /* Card detect intr is turned on. */ 3113 reg |= CB_SOCKET_MASK_CD; 3114 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3115 /* reset interrupt */ 3116 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3117 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3118 3119 /* 3120 * check for card insertion or removal during suspend period. 3121 * XXX: the code can't cope with card swap (remove then insert). 3122 * how can we detect such situation? 3123 */ 3124 if (why == PWR_RESUME) 3125 (void)pccbbintr(sc); 3126 } 3127 } 3128
Indexes created Thu Sep 25 16:09:42 GMT 2025