pccbb.c revision 1.31
1 /* $NetBSD: pccbb.c,v 1.31 2000/03/12 11:31:53 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and disallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 int loopend = sizeof(yc_chipsets) / sizeof(yc_chipsets[0]); 355 struct yenta_chipinfo *ycp, *ycend; 356 357 ycend = yc_chipsets + loopend; 358 359 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 360 361 if (ycp == ycend) { 362 /* not found -- point at sentinel */ 363 ycp = yc_chipsets + loopend - 1; 364 } 365 366 if (flagp != NULL) { 367 *flagp = ycp->yc_flags; 368 } 369 370 return ycp->yc_chiptype; 371 } 372 373 static void 374 pccbb_shutdown(void *arg) 375 { 376 struct pccbb_softc *sc = arg; 377 pcireg_t command; 378 379 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 380 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 381 0); 382 383 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 384 385 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 386 PCI_COMMAND_MASTER_ENABLE); 387 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 388 389 } 390 391 void 392 pccbbattach(parent, self, aux) 393 struct device *parent; 394 struct device *self; 395 void *aux; 396 { 397 struct pccbb_softc *sc = (void *)self; 398 struct pci_attach_args *pa = aux; 399 pci_chipset_tag_t pc = pa->pa_pc; 400 pcireg_t sock_base, busreg; 401 bus_addr_t sockbase; 402 char devinfo[256]; 403 int flags; 404 405 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 406 407 pci_devinfo(pa->pa_id, 0, 0, devinfo); 408 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 409 #ifdef CBB_DEBUG 410 printf(" (chipflags %x)", flags); 411 #endif 412 printf("\n"); 413 414 TAILQ_INIT(&sc->sc_memwindow); 415 TAILQ_INIT(&sc->sc_iowindow); 416 417 #if rbus 418 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 419 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 420 #endif /* rbus */ 421 422 sc->sc_base_memh = 0; 423 424 /* 425 * MAP socket registers and ExCA registers on memory-space 426 * When no valid address is set on socket base registers (on pci 427 * config space), get it not polite way. 428 */ 429 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 430 431 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 432 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 433 /* The address must be valid. */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 435 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 436 printf("%s: can't map socket base address 0x%x\n", 437 sc->sc_dev.dv_xname, sock_base); 438 /* 439 * I think it's funny: socket base registers must be 440 * mapped on memory space, but ... 441 */ 442 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 443 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 444 NULL)) { 445 printf("%s: can't map socket base address" 446 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 447 sockbase); 448 /* give up... allocate reg space via rbus. */ 449 sc->sc_base_memh = 0; 450 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 451 } 452 } else { 453 DPRINTF(("%s: socket base address 0x%lx\n", 454 sc->sc_dev.dv_xname, sockbase)); 455 } 456 } 457 458 sc->sc_mem_start = 0; /* XXX */ 459 sc->sc_mem_end = 0xffffffff; /* XXX */ 460 461 /* 462 * When interrupt isn't routed correctly, give up probing cbb and do 463 * not kill pcic-compatible port. 464 */ 465 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 466 printf("%s: NOT USED because of unconfigured interrupt\n", 467 sc->sc_dev.dv_xname); 468 return; 469 } 470 471 /* 472 * When bus number isn't set correctly, give up using 32-bit CardBus 473 * mode. 474 */ 475 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 476 #if notyet 477 if (((busreg >> 8) & 0xff) == 0) { 478 printf("%s: CardBus support disabled because of unconfigured bus number\n", 479 sc->sc_dev.dv_xname); 480 flags |= PCCBB_PCMCIA_16BITONLY; 481 } 482 #endif 483 484 /* pccbb_machdep.c end */ 485 486 #if defined CBB_DEBUG 487 { 488 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 489 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 490 intrname[pa->pa_intrpin], pa->pa_intrline); 491 } 492 #endif 493 494 /* setup softc */ 495 sc->sc_pc = pc; 496 sc->sc_iot = pa->pa_iot; 497 sc->sc_memt = pa->pa_memt; 498 sc->sc_dmat = pa->pa_dmat; 499 sc->sc_tag = pa->pa_tag; 500 sc->sc_function = pa->pa_function; 501 502 sc->sc_intrline = pa->pa_intrline; 503 sc->sc_intrtag = pa->pa_intrtag; 504 sc->sc_intrpin = pa->pa_intrpin; 505 506 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 507 508 shutdownhook_establish(pccbb_shutdown, sc); 509 510 #if __NetBSD_Version__ > 103060000 511 config_defer(self, pccbb_pci_callback); 512 #else 513 pccbb_pci_callback(self); 514 #endif 515 } 516 517 518 519 520 /* 521 * static void pccbb_pci_callback(struct device *self) 522 * 523 * The actual attach routine: get memory space for YENTA register 524 * space, setup YENTA register and route interrupt. 525 * 526 * This function should be deferred because this device may obtain 527 * memory space dynamically. This function must avoid obtaining 528 * memory area which has already kept for another device. Also, 529 * this function MUST be done before ISA attach process because this 530 * function kills pcic compatible port used by ISA pcic. 531 */ 532 static void 533 pccbb_pci_callback(self) 534 struct device *self; 535 { 536 struct pccbb_softc *sc = (void *)self; 537 pci_chipset_tag_t pc = sc->sc_pc; 538 bus_space_tag_t base_memt; 539 bus_space_handle_t base_memh; 540 u_int32_t maskreg; 541 pci_intr_handle_t ih; 542 const char *intrstr = NULL; 543 bus_addr_t sockbase; 544 struct cbslot_attach_args cba; 545 struct pcmciabus_attach_args paa; 546 struct cardslot_attach_args caa; 547 struct cardslot_softc *csc; 548 549 if (0 == sc->sc_base_memh) { 550 /* The socket registers aren't mapped correctly. */ 551 #if rbus 552 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 553 (sc->sc_chipset == CB_RX5C47X 554 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 555 0, &sockbase, &sc->sc_base_memh)) { 556 return; 557 } 558 sc->sc_base_memt = sc->sc_memt; 559 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 560 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 561 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 562 PCI_SOCKBASE))); 563 #else 564 sc->sc_base_memt = sc->sc_memt; 565 #if !defined CBB_PCI_BASE 566 #define CBB_PCI_BASE 0x20000000 567 #endif 568 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 569 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 570 /* cannot allocate memory space */ 571 return; 572 } 573 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 574 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 575 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 576 sc->sc_tag, PCI_SOCKBASE))); 577 #endif 578 } 579 580 /* bus bridge initialisation */ 581 pccbb_chipinit(sc); 582 583 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 584 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 585 586 /* CSC Interrupt: Card detect interrupt on */ 587 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 588 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 589 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 590 /* reset interrupt */ 591 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 592 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 593 594 /* Map and establish the interrupt. */ 595 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 596 sc->sc_intrline, &ih)) { 597 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 598 return; 599 } 600 intrstr = pci_intr_string(pc, ih); 601 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 602 603 if (sc->sc_ih == NULL) { 604 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 605 if (intrstr != NULL) { 606 printf(" at %s", intrstr); 607 } 608 printf("\n"); 609 return; 610 } 611 612 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 613 powerhook_establish(pccbb_powerhook, sc); 614 615 { 616 u_int32_t sockstat = 617 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 618 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 619 sc->sc_flags |= CBB_CARDEXIST; 620 } 621 } 622 623 /* 624 * attach cardbus 625 */ 626 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 627 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 628 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 629 630 /* initialise cbslot_attach */ 631 cba.cba_busname = "cardbus"; 632 cba.cba_iot = sc->sc_iot; 633 cba.cba_memt = sc->sc_memt; 634 cba.cba_dmat = sc->sc_dmat; 635 cba.cba_function = 0; 636 cba.cba_bus = (busreg >> 8) & 0x0ff; 637 cba.cba_cc = (void *)sc; 638 cba.cba_cf = &pccbb_funcs; 639 cba.cba_intrline = sc->sc_intrline; 640 641 #if rbus 642 cba.cba_rbus_iot = sc->sc_rbus_iot; 643 cba.cba_rbus_memt = sc->sc_rbus_memt; 644 #endif 645 646 cba.cba_cacheline = PCI_CACHELINE(bhlc); 647 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 648 649 printf("%s: cacheline 0x%x lattimer 0x%x\n", 650 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 651 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 652 busreg); 653 #if defined SHOW_REGS 654 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 655 sc->sc_base_memh); 656 #endif 657 } 658 659 pccbb_pcmcia_attach_setup(sc, &paa); 660 caa.caa_cb_attach = NULL; 661 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 662 caa.caa_cb_attach = &cba; 663 } 664 caa.caa_16_attach = &paa; 665 caa.caa_ph = &sc->sc_pcmcia_h; 666 667 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 668 DPRINTF(("pccbbattach: found cardslot\n")); 669 sc->sc_csc = csc; 670 } 671 672 return; 673 } 674 675 676 677 678 679 /* 680 * static void pccbb_chipinit(struct pccbb_softc *sc) 681 * 682 * This function initialise YENTA chip registers listed below: 683 * 1) PCI command reg, 684 * 2) PCI and CardBus latency timer, 685 * 3) disable legacy (PCIC-compatible) io, 686 * 4) route PCI interrupt, 687 * 5) close all memory and io windows. 688 */ 689 static void 690 pccbb_chipinit(sc) 691 struct pccbb_softc *sc; 692 { 693 pci_chipset_tag_t pc = sc->sc_pc; 694 pcitag_t tag = sc->sc_tag; 695 pcireg_t reg; 696 697 /* 698 * Set PCI command reg. 699 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 700 */ 701 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 702 /* I believe it is harmless. */ 703 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 704 PCI_COMMAND_MASTER_ENABLE); 705 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 706 707 /* 708 * Set CardBus latency timer. 709 */ 710 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 711 if (PCI_CB_LATENCY(reg) < 0x20) { 712 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 713 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 714 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 715 } 716 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 717 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 718 719 /* 720 * Set PCI latency timer. 721 */ 722 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 723 if (PCI_LATTIMER(reg) < 0x10) { 724 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 725 reg |= (0x10 << PCI_LATTIMER_SHIFT); 726 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 727 } 728 DPRINTF(("PCI latency timer 0x%x (%x)\n", 729 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 730 731 /* Disable legacy register mapping. */ 732 switch (sc->sc_chipset) { 733 case CB_RX5C46X: /* fallthrough */ 734 #if 0 735 case CB_RX5C47X: 736 #endif 737 /* 738 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 739 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 740 * CardBus bridges have special bits on Bridge control reg (addr 741 * 0x3e on PCI config space). 742 */ 743 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 744 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 745 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 746 break; 747 748 default: 749 /* XXX I don't know proper way to kill legacy I/O. */ 750 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 751 break; 752 } 753 754 /* Route functional interrupts to PCI. */ 755 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 756 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 757 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 758 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 759 760 switch (sc->sc_chipset) { 761 case CB_TI113X: 762 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 763 /* This bit is shared, but may read as 0 on some chips, so set 764 it explicitly on both functions. */ 765 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 766 /* CSC intr enable */ 767 reg |= PCI113X_CBCTRL_PCI_CSC; 768 /* functional intr prohibit */ 769 reg &= ~PCI113X_CBCTRL_PCI_INTR; 770 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 771 break; 772 773 case CB_TOPIC95B: 774 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 775 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 776 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 777 778 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 779 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 780 sc->sc_dev.dv_xname, reg)); 781 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 782 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 783 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 784 DPRINTF(("0x%x\n", reg)); 785 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 786 break; 787 } 788 789 /* Close all memory and I/O windows. */ 790 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 791 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 792 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 793 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 794 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 795 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 796 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 797 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 798 } 799 800 801 802 803 /* 804 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 805 * struct pcmciabus_attach_args *paa) 806 * 807 * This function attaches 16-bit PCcard bus. 808 */ 809 STATIC void 810 pccbb_pcmcia_attach_setup(sc, paa) 811 struct pccbb_softc *sc; 812 struct pcmciabus_attach_args *paa; 813 { 814 struct pcic_handle *ph = &sc->sc_pcmcia_h; 815 #if rbus 816 rbus_tag_t rb; 817 #endif 818 819 /* initialise pcmcia part in pccbb_softc */ 820 ph->ph_parent = (struct device *)sc; 821 ph->sock = sc->sc_function; 822 ph->flags = 0; 823 ph->shutdown = 0; 824 ph->ih_irq = sc->sc_intrline; 825 ph->ph_bus_t = sc->sc_base_memt; 826 ph->ph_bus_h = sc->sc_base_memh; 827 ph->ph_read = pccbb_pcmcia_read; 828 ph->ph_write = pccbb_pcmcia_write; 829 sc->sc_pct = &pccbb_pcmcia_funcs; 830 831 /* 832 * We need to do a few things here: 833 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 834 * setting the IRQ numbers to 0. 835 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 836 * routing of CSC interrupts (e.g. card removal) to PCI while in 837 * PCMCIA mode. We just leave this set all the time. 838 * 3) Enable card insertion/removal interrupts in case the chip also 839 * needs that while in PCMCIA mode. 840 * 4) Clear any pending CSC interrupt. 841 */ 842 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 843 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 844 Pcic_read(ph, PCIC_CSC); 845 846 /* initialise pcmcia bus attachment */ 847 paa->paa_busname = "pcmcia"; 848 paa->pct = sc->sc_pct; 849 paa->pch = ph; 850 paa->iobase = 0; /* I don't use them */ 851 paa->iosize = 0; 852 #if rbus 853 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 854 paa->iobase = rb->rb_start + rb->rb_offset; 855 paa->iosize = rb->rb_end - rb->rb_start; 856 #endif 857 858 return; 859 } 860 861 #if 0 862 STATIC void 863 pccbb_pcmcia_attach_card(ph) 864 struct pcic_handle *ph; 865 { 866 if (ph->flags & PCIC_FLAG_CARDP) { 867 panic("pccbb_pcmcia_attach_card: already attached"); 868 } 869 870 /* call the MI attach function */ 871 pcmcia_card_attach(ph->pcmcia); 872 873 ph->flags |= PCIC_FLAG_CARDP; 874 } 875 876 STATIC void 877 pccbb_pcmcia_detach_card(ph, flags) 878 struct pcic_handle *ph; 879 int flags; 880 { 881 if (!(ph->flags & PCIC_FLAG_CARDP)) { 882 panic("pccbb_pcmcia_detach_card: already detached"); 883 } 884 885 ph->flags &= ~PCIC_FLAG_CARDP; 886 887 /* call the MI detach function */ 888 pcmcia_card_detach(ph->pcmcia, flags); 889 } 890 #endif 891 892 /* 893 * int pccbbintr(arg) 894 * void *arg; 895 * This routine handles the interrupt from Yenta PCI-CardBus bridge 896 * itself. 897 */ 898 int 899 pccbbintr(arg) 900 void *arg; 901 { 902 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 903 u_int32_t sockevent, sockstate; 904 bus_space_tag_t memt = sc->sc_base_memt; 905 bus_space_handle_t memh = sc->sc_base_memh; 906 struct pcic_handle *ph = &sc->sc_pcmcia_h; 907 908 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 909 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 910 Pcic_read(ph, PCIC_CSC); 911 912 if (sockevent == 0) { 913 /* This intr is not for me: it may be for my child devices. */ 914 return pccbbintr_function(sc); 915 } 916 917 if (sockevent & CB_SOCKET_EVENT_CD) { 918 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 919 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 920 /* A card should be removed. */ 921 if (sc->sc_flags & CBB_CARDEXIST) { 922 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 923 sockevent)); 924 DPRINTF((" card removed, 0x%08x\n", sockstate)); 925 sc->sc_flags &= ~CBB_CARDEXIST; 926 if (sc-> 927 sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) 928 { 929 #if 0 930 struct pcic_handle *ph = 931 &sc->sc_pcmcia_h; 932 933 pcmcia_card_deactivate(ph->pcmcia); 934 pccbb_pcmcia_socket_disable(ph); 935 pccbb_pcmcia_detach_card(ph, 936 DETACH_FORCE); 937 #endif 938 cardslot_event_throw(sc->sc_csc, 939 CARDSLOT_EVENT_REMOVAL_16); 940 } else if (sc-> 941 sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) 942 { 943 /* Cardbus intr removed */ 944 cardslot_event_throw(sc->sc_csc, 945 CARDSLOT_EVENT_REMOVAL_CB); 946 } 947 } 948 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 949 if (sc->sc_flags & CBB_INSERTING) { 950 untimeout(pci113x_insert, sc); 951 } 952 timeout(pci113x_insert, sc, hz / 10); 953 sc->sc_flags |= CBB_INSERTING; 954 } 955 } 956 957 return 1; 958 } 959 960 /* 961 * static int pccbbintr_function(struct pccbb_softc *sc) 962 * 963 * This function calls each interrupt handler registered at the 964 * bridge. The interrupt handlers are called in registerd order. 965 */ 966 static int 967 pccbbintr_function(sc) 968 struct pccbb_softc *sc; 969 { 970 int retval = 0, val; 971 struct pccbb_intrhand_list *pil; 972 973 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 974 val = (*pil->pil_func) (pil->pil_arg); 975 retval = retval == 1 ? 1 : 976 retval == 0 ? val : val != 0 ? val : retval; 977 } 978 979 return retval; 980 } 981 982 static void 983 pci113x_insert(arg) 984 void *arg; 985 { 986 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 987 u_int32_t sockevent, sockstate; 988 989 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 990 CB_SOCKET_EVENT); 991 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 992 CB_SOCKET_STAT); 993 994 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 995 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 996 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 997 sc->sc_flags |= CBB_CARDEXIST; 998 /* call pccard intterupt handler here */ 999 if (sockstate & CB_SOCKET_STAT_16BIT) { 1000 /* 16-bit card found */ 1001 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1002 cardslot_event_throw(sc->sc_csc, 1003 CARDSLOT_EVENT_INSERTION_16); 1004 } else if (sockstate & CB_SOCKET_STAT_CB) { 1005 /* cardbus card fuond */ 1006 /* cardbus_attach_card(sc->sc_csc); */ 1007 cardslot_event_throw(sc->sc_csc, 1008 CARDSLOT_EVENT_INSERTION_CB); 1009 } else { 1010 /* who are you? */ 1011 } 1012 } else { 1013 timeout(pci113x_insert, sc, hz / 10); 1014 } 1015 } 1016 1017 #define PCCBB_PCMCIA_OFFSET 0x800 1018 static u_int8_t 1019 pccbb_pcmcia_read(ph, reg) 1020 struct pcic_handle *ph; 1021 int reg; 1022 { 1023 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1024 PCCBB_PCMCIA_OFFSET + reg); 1025 } 1026 1027 static void 1028 pccbb_pcmcia_write(ph, reg, val) 1029 struct pcic_handle *ph; 1030 int reg; 1031 u_int8_t val; 1032 { 1033 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1034 val); 1035 } 1036 1037 /* 1038 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1039 */ 1040 STATIC int 1041 pccbb_ctrl(ct, command) 1042 cardbus_chipset_tag_t ct; 1043 int command; 1044 { 1045 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1046 1047 switch (command) { 1048 case CARDBUS_CD: 1049 if (2 == pccbb_detect_card(sc)) { 1050 int retval = 0; 1051 int status = cb_detect_voltage(sc); 1052 if (PCCARD_VCC_5V & status) { 1053 retval |= CARDBUS_5V_CARD; 1054 } 1055 if (PCCARD_VCC_3V & status) { 1056 retval |= CARDBUS_3V_CARD; 1057 } 1058 if (PCCARD_VCC_XV & status) { 1059 retval |= CARDBUS_XV_CARD; 1060 } 1061 if (PCCARD_VCC_YV & status) { 1062 retval |= CARDBUS_YV_CARD; 1063 } 1064 return retval; 1065 } else { 1066 return 0; 1067 } 1068 break; 1069 case CARDBUS_RESET: 1070 return cb_reset(sc); 1071 break; 1072 case CARDBUS_IO_ENABLE: /* fallthrough */ 1073 case CARDBUS_IO_DISABLE: /* fallthrough */ 1074 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1075 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1076 case CARDBUS_BM_ENABLE: /* fallthrough */ 1077 case CARDBUS_BM_DISABLE: /* fallthrough */ 1078 return pccbb_cardenable(sc, command); 1079 break; 1080 } 1081 1082 return 0; 1083 } 1084 1085 /* 1086 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1087 * This function returns true when it succeeds and returns false when 1088 * it fails. 1089 */ 1090 STATIC int 1091 pccbb_power(ct, command) 1092 cardbus_chipset_tag_t ct; 1093 int command; 1094 { 1095 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1096 1097 u_int32_t status, sock_ctrl; 1098 bus_space_tag_t memt = sc->sc_base_memt; 1099 bus_space_handle_t memh = sc->sc_base_memh; 1100 1101 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1102 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1103 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1104 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1105 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1106 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1107 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1108 "UNKNOWN", 1109 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1110 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1111 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1112 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1113 "UNKNOWN", command)); 1114 1115 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1116 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1117 1118 switch (command & CARDBUS_VCCMASK) { 1119 case CARDBUS_VCC_UC: 1120 break; 1121 case CARDBUS_VCC_5V: 1122 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1123 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1124 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1125 } else { 1126 printf("%s: BAD voltage request: no 5 V card\n", 1127 sc->sc_dev.dv_xname); 1128 } 1129 break; 1130 case CARDBUS_VCC_3V: 1131 if (CB_SOCKET_STAT_3VCARD & status) { 1132 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1133 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1134 } else { 1135 printf("%s: BAD voltage request: no 3.3 V card\n", 1136 sc->sc_dev.dv_xname); 1137 } 1138 break; 1139 case CARDBUS_VCC_0V: 1140 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1141 break; 1142 default: 1143 return 0; /* power NEVER changed */ 1144 break; 1145 } 1146 1147 switch (command & CARDBUS_VPPMASK) { 1148 case CARDBUS_VPP_UC: 1149 break; 1150 case CARDBUS_VPP_0V: 1151 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1152 break; 1153 case CARDBUS_VPP_VCC: 1154 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1155 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1156 break; 1157 case CARDBUS_VPP_12V: 1158 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1159 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1160 break; 1161 } 1162 1163 #if 0 1164 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1165 #endif 1166 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1167 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1168 1169 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1170 /* 1171 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1172 * time is 20 ms, some PC-Card bridge requires longer duration. 1173 */ 1174 delay(200 * 1000); 1175 1176 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1177 printf 1178 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1179 sc->sc_dev.dv_xname, sock_ctrl, status); 1180 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1181 (command & CARDBUS_VCCMASK) == 1182 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1183 CARDBUS_VCCMASK) == 1184 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1185 CARDBUS_VCCMASK) == 1186 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1187 CARDBUS_VCCMASK) == 1188 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1189 CARDBUS_VCCMASK) == 1190 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1191 CARDBUS_VCCMASK) == 1192 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1193 (command & CARDBUS_VPPMASK) == 1194 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1195 CARDBUS_VPPMASK) == 1196 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1197 CARDBUS_VPPMASK) == 1198 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1199 CARDBUS_VPPMASK) == 1200 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1201 #if 0 1202 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1203 u_int32_t force = 1204 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1205 /* Reset Bad Vcc request */ 1206 force &= ~CB_SOCKET_FORCE_BADVCC; 1207 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1208 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1209 CB_SOCKET_STAT)); 1210 return 1; 1211 } 1212 #endif 1213 return 0; 1214 } 1215 return 1; /* power changed correctly */ 1216 } 1217 1218 #if defined CB_PCMCIA_POLL 1219 struct cb_poll_str { 1220 void *arg; 1221 int (*func) __P((void *)); 1222 int level; 1223 pccard_chipset_tag_t ct; 1224 int count; 1225 }; 1226 1227 static struct cb_poll_str cb_poll[10]; 1228 static int cb_poll_n = 0; 1229 1230 static void cb_pcmcia_poll __P((void *arg)); 1231 1232 static void 1233 cb_pcmcia_poll(arg) 1234 void *arg; 1235 { 1236 struct cb_poll_str *poll = arg; 1237 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1238 struct pccbb_softc *sc = psc->cpc_parent; 1239 int s; 1240 u_int32_t spsr; /* socket present-state reg */ 1241 1242 timeout(cb_pcmcia_poll, arg, hz / 10); 1243 switch (poll->level) { 1244 case IPL_NET: 1245 s = splnet(); 1246 break; 1247 case IPL_BIO: 1248 s = splbio(); 1249 break; 1250 case IPL_TTY: /* fallthrough */ 1251 default: 1252 s = spltty(); 1253 break; 1254 } 1255 1256 spsr = 1257 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1258 CB_SOCKET_STAT); 1259 1260 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1261 if (!(spsr & 0x40)) { /* CINT low */ 1262 #else 1263 if (1) { 1264 #endif 1265 if ((*poll->func) (poll->arg) == 1) { 1266 ++poll->count; 1267 printf("intr: reported from poller, 0x%x\n", spsr); 1268 #if defined LEVEL2 1269 } else { 1270 printf("intr: miss! 0x%x\n", spsr); 1271 #endif 1272 } 1273 } 1274 splx(s); 1275 } 1276 #endif /* defined CB_PCMCIA_POLL */ 1277 1278 /* 1279 * static int pccbb_detect_card(struct pccbb_softc *sc) 1280 * return value: 0 if no card exists. 1281 * 1 if 16-bit card exists. 1282 * 2 if cardbus card exists. 1283 */ 1284 static int 1285 pccbb_detect_card(sc) 1286 struct pccbb_softc *sc; 1287 { 1288 bus_space_handle_t base_memh = sc->sc_base_memh; 1289 bus_space_tag_t base_memt = sc->sc_base_memt; 1290 u_int32_t sockstat = 1291 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1292 int retval = 0; 1293 1294 /* CD1 and CD2 asserted */ 1295 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1296 /* card must be present */ 1297 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1298 /* NOTACARD DEASSERTED */ 1299 if (CB_SOCKET_STAT_CB & sockstat) { 1300 /* CardBus mode */ 1301 retval = 2; 1302 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1303 /* 16-bit mode */ 1304 retval = 1; 1305 } 1306 } 1307 } 1308 return retval; 1309 } 1310 1311 /* 1312 * STATIC int cb_reset(struct pccbb_softc *sc) 1313 * This function resets CardBus card. 1314 */ 1315 STATIC int 1316 cb_reset(sc) 1317 struct pccbb_softc *sc; 1318 { 1319 /* 1320 * Reset Assert at least 20 ms 1321 * Some machines request longer duration. 1322 */ 1323 int reset_duration = 1324 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1325 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1326 1327 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1328 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1329 delay(reset_duration); 1330 1331 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1332 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1333 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1334 delay(reset_duration); 1335 } 1336 /* No card found on the slot. Keep Reset. */ 1337 return 1; 1338 } 1339 1340 /* 1341 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1342 * This function detect card Voltage. 1343 */ 1344 STATIC int 1345 cb_detect_voltage(sc) 1346 struct pccbb_softc *sc; 1347 { 1348 u_int32_t psr; /* socket present-state reg */ 1349 bus_space_tag_t iot = sc->sc_base_memt; 1350 bus_space_handle_t ioh = sc->sc_base_memh; 1351 int vol = PCCARD_VCC_UKN; /* set 0 */ 1352 1353 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1354 1355 if (0x400u & psr) { 1356 vol |= PCCARD_VCC_5V; 1357 } 1358 if (0x800u & psr) { 1359 vol |= PCCARD_VCC_3V; 1360 } 1361 1362 return vol; 1363 } 1364 1365 STATIC int 1366 cbbprint(aux, pcic) 1367 void *aux; 1368 const char *pcic; 1369 { 1370 /* 1371 struct cbslot_attach_args *cba = aux; 1372 1373 if (cba->cba_slot >= 0) { 1374 printf(" slot %d", cba->cba_slot); 1375 } 1376 */ 1377 return UNCONF; 1378 } 1379 1380 /* 1381 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1382 * This function enables and disables the card 1383 */ 1384 STATIC int 1385 pccbb_cardenable(sc, function) 1386 struct pccbb_softc *sc; 1387 int function; 1388 { 1389 u_int32_t command = 1390 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1391 1392 DPRINTF(("pccbb_cardenable:")); 1393 switch (function) { 1394 case CARDBUS_IO_ENABLE: 1395 command |= PCI_COMMAND_IO_ENABLE; 1396 break; 1397 case CARDBUS_IO_DISABLE: 1398 command &= ~PCI_COMMAND_IO_ENABLE; 1399 break; 1400 case CARDBUS_MEM_ENABLE: 1401 command |= PCI_COMMAND_MEM_ENABLE; 1402 break; 1403 case CARDBUS_MEM_DISABLE: 1404 command &= ~PCI_COMMAND_MEM_ENABLE; 1405 break; 1406 case CARDBUS_BM_ENABLE: 1407 command |= PCI_COMMAND_MASTER_ENABLE; 1408 break; 1409 case CARDBUS_BM_DISABLE: 1410 command &= ~PCI_COMMAND_MASTER_ENABLE; 1411 break; 1412 default: 1413 return 0; 1414 } 1415 1416 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1417 DPRINTF((" command reg 0x%x\n", command)); 1418 return 1; 1419 } 1420 1421 #if !rbus 1422 /* 1423 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1424 */ 1425 static int 1426 pccbb_io_open(ct, win, start, end) 1427 cardbus_chipset_tag_t ct; 1428 int win; 1429 u_int32_t start, end; 1430 { 1431 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1432 int basereg; 1433 int limitreg; 1434 1435 if ((win < 0) || (win > 2)) { 1436 #if defined DIAGNOSTIC 1437 printf("cardbus_io_open: window out of range %d\n", win); 1438 #endif 1439 return 0; 1440 } 1441 1442 basereg = win * 8 + 0x2c; 1443 limitreg = win * 8 + 0x30; 1444 1445 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1446 start, basereg, end, limitreg)); 1447 1448 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1449 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1450 return 1; 1451 } 1452 1453 /* 1454 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1455 */ 1456 static int 1457 pccbb_io_close(ct, win) 1458 cardbus_chipset_tag_t ct; 1459 int win; 1460 { 1461 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1462 int basereg; 1463 int limitreg; 1464 1465 if ((win < 0) || (win > 2)) { 1466 #if defined DIAGNOSTIC 1467 printf("cardbus_io_close: window out of range %d\n", win); 1468 #endif 1469 return 0; 1470 } 1471 1472 basereg = win * 8 + 0x2c; 1473 limitreg = win * 8 + 0x30; 1474 1475 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1476 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1477 return 1; 1478 } 1479 1480 /* 1481 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1482 */ 1483 static int 1484 pccbb_mem_open(ct, win, start, end) 1485 cardbus_chipset_tag_t ct; 1486 int win; 1487 u_int32_t start, end; 1488 { 1489 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1490 int basereg; 1491 int limitreg; 1492 1493 if ((win < 0) || (win > 2)) { 1494 #if defined DIAGNOSTIC 1495 printf("cardbus_mem_open: window out of range %d\n", win); 1496 #endif 1497 return 0; 1498 } 1499 1500 basereg = win * 8 + 0x1c; 1501 limitreg = win * 8 + 0x20; 1502 1503 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1504 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1505 return 1; 1506 } 1507 1508 /* 1509 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1510 */ 1511 static int 1512 pccbb_mem_close(ct, win) 1513 cardbus_chipset_tag_t ct; 1514 int win; 1515 { 1516 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1517 int basereg; 1518 int limitreg; 1519 1520 if ((win < 0) || (win > 2)) { 1521 #if defined DIAGNOSTIC 1522 printf("cardbus_mem_close: window out of range %d\n", win); 1523 #endif 1524 return 0; 1525 } 1526 1527 basereg = win * 8 + 0x1c; 1528 limitreg = win * 8 + 0x20; 1529 1530 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1531 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1532 return 1; 1533 } 1534 #endif 1535 1536 /* 1537 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1538 * int irq, 1539 * int level, 1540 * int (* func) __P((void *)), 1541 * void *arg) 1542 * 1543 * This function registers an interrupt handler at the bridge, in 1544 * order not to call the interrput handlers of child devices when 1545 * a card-deletion interrput occurs. 1546 * 1547 * The arguments irq and level are not used. 1548 */ 1549 static void * 1550 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1551 cardbus_chipset_tag_t ct; 1552 int irq, level; 1553 int (*func) __P((void *)); 1554 void *arg; 1555 { 1556 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1557 1558 return pccbb_intr_establish(sc, irq, level, func, arg); 1559 } 1560 1561 1562 /* 1563 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1564 * void *ih) 1565 * 1566 * This function removes an interrupt handler pointed by ih. 1567 */ 1568 static void 1569 pccbb_cb_intr_disestablish(ct, ih) 1570 cardbus_chipset_tag_t ct; 1571 void *ih; 1572 { 1573 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1574 1575 pccbb_intr_disestablish(sc, ih); 1576 } 1577 1578 1579 /* 1580 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1581 * int irq, 1582 * int level, 1583 * int (* func) __P((void *)), 1584 * void *arg) 1585 * 1586 * This function registers an interrupt handler at the bridge, in 1587 * order not to call the interrput handlers of child devices when 1588 * a card-deletion interrput occurs. 1589 * 1590 * The arguments irq and level are not used. 1591 */ 1592 static void * 1593 pccbb_intr_establish(sc, irq, level, func, arg) 1594 struct pccbb_softc *sc; 1595 int irq, level; 1596 int (*func) __P((void *)); 1597 void *arg; 1598 { 1599 struct pccbb_intrhand_list *pil, *newpil; 1600 1601 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1602 1603 if (sc->sc_pil == NULL) { 1604 /* initialise bridge intr routing */ 1605 1606 switch (sc->sc_chipset) { 1607 case CB_TI113X: 1608 { 1609 pcireg_t cbctrl = 1610 pci_conf_read(sc->sc_pc, sc->sc_tag, 1611 PCI_CBCTRL); 1612 /* functional intr enabled */ 1613 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1614 pci_conf_write(sc->sc_pc, sc->sc_tag, 1615 PCI_CBCTRL, cbctrl); 1616 break; 1617 } 1618 default: 1619 break; 1620 } 1621 } 1622 1623 /* 1624 * Allocate a room for interrut handler structure. 1625 */ 1626 if (NULL == (newpil = 1627 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1628 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1629 return NULL; 1630 } 1631 1632 newpil->pil_func = func; 1633 newpil->pil_arg = arg; 1634 newpil->pil_next = NULL; 1635 1636 if (sc->sc_pil == NULL) { 1637 sc->sc_pil = newpil; 1638 } else { 1639 for (pil = sc->sc_pil; pil->pil_next != NULL; 1640 pil = pil->pil_next); 1641 pil->pil_next = newpil; 1642 } 1643 1644 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1645 1646 return newpil; 1647 } 1648 1649 /* 1650 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1651 * void *ih) 1652 * 1653 * This function removes an interrupt handler pointed by ih. 1654 */ 1655 static void 1656 pccbb_intr_disestablish(sc, ih) 1657 struct pccbb_softc *sc; 1658 void *ih; 1659 { 1660 struct pccbb_intrhand_list *pil, **pil_prev; 1661 1662 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1663 1664 pil_prev = &sc->sc_pil; 1665 1666 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1667 if (pil == ih) { 1668 *pil_prev = pil->pil_next; 1669 free(pil, M_DEVBUF); 1670 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1671 break; 1672 } 1673 pil_prev = &pil->pil_next; 1674 } 1675 1676 if (sc->sc_pil == NULL) { 1677 /* No interrupt handlers */ 1678 1679 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1680 1681 switch (sc->sc_chipset) { 1682 case CB_TI113X: 1683 { 1684 pcireg_t cbctrl = 1685 pci_conf_read(sc->sc_pc, sc->sc_tag, 1686 PCI_CBCTRL); 1687 /* functional intr disabled */ 1688 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1689 pci_conf_write(sc->sc_pc, sc->sc_tag, 1690 PCI_CBCTRL, cbctrl); 1691 break; 1692 } 1693 default: 1694 break; 1695 } 1696 } 1697 } 1698 1699 #if defined SHOW_REGS 1700 static void 1701 cb_show_regs(pc, tag, memt, memh) 1702 pci_chipset_tag_t pc; 1703 pcitag_t tag; 1704 bus_space_tag_t memt; 1705 bus_space_handle_t memh; 1706 { 1707 int i; 1708 printf("PCI config regs:"); 1709 for (i = 0; i < 0x50; i += 4) { 1710 if (i % 16 == 0) { 1711 printf("\n 0x%02x:", i); 1712 } 1713 printf(" %08x", pci_conf_read(pc, tag, i)); 1714 } 1715 for (i = 0x80; i < 0xb0; i += 4) { 1716 if (i % 16 == 0) { 1717 printf("\n 0x%02x:", i); 1718 } 1719 printf(" %08x", pci_conf_read(pc, tag, i)); 1720 } 1721 1722 if (memh == 0) { 1723 printf("\n"); 1724 return; 1725 } 1726 1727 printf("\nsocket regs:"); 1728 for (i = 0; i <= 0x10; i += 0x04) { 1729 printf(" %08x", bus_space_read_4(memt, memh, i)); 1730 } 1731 printf("\nExCA regs:"); 1732 for (i = 0; i < 0x08; ++i) { 1733 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1734 } 1735 printf("\n"); 1736 return; 1737 } 1738 #endif 1739 1740 /* 1741 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1742 * int busno, int devno, int function) 1743 * This is the function to make a tag to access config space of 1744 * a CardBus Card. It works same as pci_conf_read. 1745 */ 1746 static cardbustag_t 1747 pccbb_make_tag(cc, busno, devno, function) 1748 cardbus_chipset_tag_t cc; 1749 int busno, devno, function; 1750 { 1751 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1752 1753 return pci_make_tag(sc->sc_pc, busno, devno, function); 1754 } 1755 1756 static void 1757 pccbb_free_tag(cc, tag) 1758 cardbus_chipset_tag_t cc; 1759 cardbustag_t tag; 1760 { 1761 } 1762 1763 /* 1764 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1765 * cardbustag_t tag, int offset) 1766 * This is the function to read the config space of a CardBus Card. 1767 * It works same as pci_conf_read. 1768 */ 1769 static cardbusreg_t 1770 pccbb_conf_read(cc, tag, offset) 1771 cardbus_chipset_tag_t cc; 1772 cardbustag_t tag; 1773 int offset; /* register offset */ 1774 { 1775 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1776 1777 return pci_conf_read(sc->sc_pc, tag, offset); 1778 } 1779 1780 /* 1781 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1782 * int offs, cardbusreg_t val) 1783 * This is the function to write the config space of a CardBus Card. 1784 * It works same as pci_conf_write. 1785 */ 1786 static void 1787 pccbb_conf_write(cc, tag, reg, val) 1788 cardbus_chipset_tag_t cc; 1789 cardbustag_t tag; 1790 int reg; /* register offset */ 1791 cardbusreg_t val; 1792 { 1793 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1794 1795 pci_conf_write(sc->sc_pc, tag, reg, val); 1796 } 1797 1798 #if 0 1799 STATIC int 1800 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1801 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1802 int speed, int flags, 1803 bus_space_handle_t * iohp) 1804 #endif 1805 /* 1806 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1807 * bus_addr_t start, bus_size_t size, 1808 * bus_size_t align, 1809 * struct pcmcia_io_handle *pcihp 1810 * 1811 * This function only allocates I/O region for pccard. This function 1812 * never maps the allcated region to pccard I/O area. 1813 * 1814 * XXX: The interface of this function is not very good, I believe. 1815 */ 1816 STATIC int 1817 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1818 pcmcia_chipset_handle_t pch; 1819 bus_addr_t start; /* start address */ 1820 bus_size_t size; 1821 bus_size_t align; 1822 struct pcmcia_io_handle *pcihp; 1823 { 1824 struct pcic_handle *ph = (struct pcic_handle *)pch; 1825 bus_addr_t ioaddr; 1826 int flags = 0; 1827 bus_space_tag_t iot; 1828 bus_space_handle_t ioh; 1829 #if rbus 1830 rbus_tag_t rb; 1831 #endif 1832 if (align == 0) { 1833 align = size; /* XXX: funny??? */ 1834 } 1835 1836 /* 1837 * Allocate some arbitrary I/O space. 1838 */ 1839 1840 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1841 1842 #if rbus 1843 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1844 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1845 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1846 return 1; 1847 } 1848 #else 1849 if (start) { 1850 ioaddr = start; 1851 if (bus_space_map(iot, start, size, 0, &ioh)) { 1852 return 1; 1853 } 1854 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1855 (u_long) ioaddr, (u_long) size)); 1856 } else { 1857 flags |= PCMCIA_IO_ALLOCATED; 1858 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1859 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1860 size, align, 0, 0, &ioaddr, &ioh)) { 1861 /* No room be able to be get. */ 1862 return 1; 1863 } 1864 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1865 (u_long) ioaddr, (u_long) size)); 1866 } 1867 #endif 1868 1869 pcihp->iot = iot; 1870 pcihp->ioh = ioh; 1871 pcihp->addr = ioaddr; 1872 pcihp->size = size; 1873 pcihp->flags = flags; 1874 1875 return 0; 1876 } 1877 1878 /* 1879 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1880 * struct pcmcia_io_handle *pcihp) 1881 * 1882 * This function only frees I/O region for pccard. 1883 * 1884 * XXX: The interface of this function is not very good, I believe. 1885 */ 1886 void 1887 pccbb_pcmcia_io_free(pch, pcihp) 1888 pcmcia_chipset_handle_t pch; 1889 struct pcmcia_io_handle *pcihp; 1890 { 1891 #if !rbus 1892 bus_space_tag_t iot = pcihp->iot; 1893 #endif 1894 bus_space_handle_t ioh = pcihp->ioh; 1895 bus_size_t size = pcihp->size; 1896 1897 #if rbus 1898 struct pccbb_softc *sc = 1899 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1900 rbus_tag_t rb = sc->sc_rbus_iot; 1901 1902 rbus_space_free(rb, ioh, size, NULL); 1903 #else 1904 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1905 bus_space_free(iot, ioh, size); 1906 else 1907 bus_space_unmap(iot, ioh, size); 1908 #endif 1909 } 1910 1911 /* 1912 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1913 * bus_addr_t offset, bus_size_t size, 1914 * struct pcmcia_io_handle *pcihp, 1915 * int *windowp) 1916 * 1917 * This function maps the allocated I/O region to pccard. This function 1918 * never allocates any I/O region for pccard I/O area. I don't 1919 * understand why the original authors of pcmciabus separated alloc and 1920 * map. I believe the two must be unite. 1921 * 1922 * XXX: no wait timing control? 1923 */ 1924 int 1925 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1926 pcmcia_chipset_handle_t pch; 1927 int width; 1928 bus_addr_t offset; 1929 bus_size_t size; 1930 struct pcmcia_io_handle *pcihp; 1931 int *windowp; 1932 { 1933 struct pcic_handle *ph = (struct pcic_handle *)pch; 1934 bus_addr_t ioaddr = pcihp->addr + offset; 1935 int i, win; 1936 #if defined CBB_DEBUG 1937 static char *width_names[] = { "dynamic", "io8", "io16" }; 1938 #endif 1939 1940 /* Sanity check I/O handle. */ 1941 1942 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1943 panic("pccbb_pcmcia_io_map iot is bogus"); 1944 } 1945 1946 /* XXX Sanity check offset/size. */ 1947 1948 win = -1; 1949 for (i = 0; i < PCIC_IO_WINS; i++) { 1950 if ((ph->ioalloc & (1 << i)) == 0) { 1951 win = i; 1952 ph->ioalloc |= (1 << i); 1953 break; 1954 } 1955 } 1956 1957 if (win == -1) { 1958 return 1; 1959 } 1960 1961 *windowp = win; 1962 1963 /* XXX this is pretty gross */ 1964 1965 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1966 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1967 1968 /* XXX wtf is this doing here? */ 1969 1970 #if 0 1971 printf(" port 0x%lx", (u_long) ioaddr); 1972 if (size > 1) { 1973 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1974 } 1975 #endif 1976 1977 ph->io[win].addr = ioaddr; 1978 ph->io[win].size = size; 1979 ph->io[win].width = width; 1980 1981 /* actual dirty register-value changing in the function below. */ 1982 pccbb_pcmcia_do_io_map(ph, win); 1983 1984 return 0; 1985 } 1986 1987 /* 1988 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1989 * 1990 * This function changes register-value to map I/O region for pccard. 1991 */ 1992 static void 1993 pccbb_pcmcia_do_io_map(ph, win) 1994 struct pcic_handle *ph; 1995 int win; 1996 { 1997 static u_int8_t pcic_iowidth[3] = { 1998 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1999 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2000 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2001 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2002 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2003 }; 2004 2005 #define PCIC_SIA_START_LOW 0 2006 #define PCIC_SIA_START_HIGH 1 2007 #define PCIC_SIA_STOP_LOW 2 2008 #define PCIC_SIA_STOP_HIGH 3 2009 2010 int regbase_win = 0x8 + win * 0x04; 2011 u_int8_t ioctl, enable; 2012 2013 DPRINTF( 2014 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2015 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2016 ph->io[win].width * 8)); 2017 2018 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2019 ph->io[win].addr & 0xff); 2020 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2021 (ph->io[win].addr >> 8) & 0xff); 2022 2023 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2024 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2025 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2026 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2027 2028 ioctl = Pcic_read(ph, PCIC_IOCTL); 2029 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2030 switch (win) { 2031 case 0: 2032 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2033 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2034 PCIC_IOCTL_IO0_DATASIZE_MASK); 2035 ioctl |= pcic_iowidth[ph->io[win].width]; 2036 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2037 break; 2038 case 1: 2039 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2040 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2041 PCIC_IOCTL_IO1_DATASIZE_MASK); 2042 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2043 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2044 break; 2045 } 2046 Pcic_write(ph, PCIC_IOCTL, ioctl); 2047 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2048 #if defined CBB_DEBUG 2049 { 2050 u_int8_t start_low = 2051 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2052 u_int8_t start_high = 2053 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2054 u_int8_t stop_low = 2055 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2056 u_int8_t stop_high = 2057 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2058 printf 2059 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2060 start_low, start_high, stop_low, stop_high, ioctl, enable); 2061 } 2062 #endif 2063 } 2064 2065 /* 2066 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2067 * 2068 * This function unmapss I/O region. No return value. 2069 */ 2070 STATIC void 2071 pccbb_pcmcia_io_unmap(pch, win) 2072 pcmcia_chipset_handle_t pch; 2073 int win; 2074 { 2075 struct pcic_handle *ph = (struct pcic_handle *)pch; 2076 int reg; 2077 2078 if (win >= PCIC_IO_WINS || win < 0) { 2079 panic("pccbb_pcmcia_io_unmap: window out of range"); 2080 } 2081 2082 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2083 switch (win) { 2084 case 0: 2085 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2086 break; 2087 case 1: 2088 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2089 break; 2090 } 2091 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2092 2093 ph->ioalloc &= ~(1 << win); 2094 } 2095 2096 /* 2097 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2098 * 2099 * This function enables the card. All information is stored in 2100 * the first argument, pcmcia_chipset_handle_t. 2101 */ 2102 static void 2103 pccbb_pcmcia_wait_ready(ph) 2104 struct pcic_handle *ph; 2105 { 2106 int i; 2107 2108 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2109 Pcic_read(ph, PCIC_IF_STATUS))); 2110 2111 for (i = 0; i < 10000; i++) { 2112 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2113 return; 2114 } 2115 delay(500); 2116 #ifdef CBB_DEBUG 2117 if ((i > 5000) && (i % 100 == 99)) 2118 printf("."); 2119 #endif 2120 } 2121 2122 #ifdef DIAGNOSTIC 2123 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2124 Pcic_read(ph, PCIC_IF_STATUS)); 2125 #endif 2126 } 2127 2128 /* 2129 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2130 * 2131 * This function enables the card. All information is stored in 2132 * the first argument, pcmcia_chipset_handle_t. 2133 */ 2134 STATIC void 2135 pccbb_pcmcia_socket_enable(pch) 2136 pcmcia_chipset_handle_t pch; 2137 { 2138 struct pcic_handle *ph = (struct pcic_handle *)pch; 2139 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2140 int cardtype, win; 2141 u_int8_t power, intr; 2142 pcireg_t spsr; 2143 int voltage; 2144 2145 /* this bit is mostly stolen from pcic_attach_card */ 2146 2147 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2148 2149 /* get card Vcc info */ 2150 2151 spsr = 2152 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2153 CB_SOCKET_STAT); 2154 if (spsr & CB_SOCKET_STAT_5VCARD) { 2155 DPRINTF(("5V card\n")); 2156 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2157 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2158 DPRINTF(("3V card\n")); 2159 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2160 } else { 2161 printf("?V card, 0x%x\n", spsr); /* XXX */ 2162 return; 2163 } 2164 2165 /* assert reset bit */ 2166 intr = Pcic_read(ph, PCIC_INTR); 2167 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2168 Pcic_write(ph, PCIC_INTR, intr); 2169 2170 /* disable socket i/o: negate output enable bit */ 2171 2172 power = Pcic_read(ph, PCIC_PWRCTL); 2173 power &= ~PCIC_PWRCTL_OE; 2174 Pcic_write(ph, PCIC_PWRCTL, power); 2175 2176 /* power down the socket to reset it, clear the card reset pin */ 2177 2178 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2179 2180 /* 2181 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2182 * we are changing Vcc (Toff). 2183 */ 2184 /* delay(300*1000); too much */ 2185 2186 /* power up the socket */ 2187 pccbb_power(sc, voltage); 2188 2189 /* 2190 * wait 100ms until power raise (Tpr) and 20ms to become 2191 * stable (Tsu(Vcc)). 2192 * 2193 * some machines require some more time to be settled 2194 * (another 200ms is added here). 2195 */ 2196 /* delay((100 + 20 + 200)*1000); too much */ 2197 2198 power = Pcic_read(ph, PCIC_PWRCTL); 2199 power |= PCIC_PWRCTL_OE; 2200 Pcic_write(ph, PCIC_PWRCTL, power); 2201 2202 /* 2203 * hold RESET at least 10us. 2204 */ 2205 delay(10); 2206 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2207 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2208 2209 /* clear the reset flag */ 2210 2211 intr |= PCIC_INTR_RESET; 2212 Pcic_write(ph, PCIC_INTR, intr); 2213 2214 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2215 2216 delay(20000); 2217 2218 /* wait for the chip to finish initializing */ 2219 2220 pccbb_pcmcia_wait_ready(ph); 2221 2222 /* zero out the address windows */ 2223 2224 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2225 2226 /* set the card type */ 2227 2228 cardtype = pcmcia_card_gettype(ph->pcmcia); 2229 2230 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2231 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2232 Pcic_write(ph, PCIC_INTR, intr); 2233 2234 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2235 ph->ph_parent->dv_xname, ph->sock, 2236 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2237 2238 /* reinstall all the memory and io mappings */ 2239 2240 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2241 if (ph->memalloc & (1 << win)) { 2242 pccbb_pcmcia_do_mem_map(ph, win); 2243 } 2244 } 2245 2246 for (win = 0; win < PCIC_IO_WINS; ++win) { 2247 if (ph->ioalloc & (1 << win)) { 2248 pccbb_pcmcia_do_io_map(ph, win); 2249 } 2250 } 2251 } 2252 2253 /* 2254 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2255 * 2256 * This function disables the card. All information is stored in 2257 * the first argument, pcmcia_chipset_handle_t. 2258 */ 2259 STATIC void 2260 pccbb_pcmcia_socket_disable(pch) 2261 pcmcia_chipset_handle_t pch; 2262 { 2263 struct pcic_handle *ph = (struct pcic_handle *)pch; 2264 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2265 u_int8_t power, intr; 2266 2267 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2268 2269 /* reset signal asserting... */ 2270 2271 intr = Pcic_read(ph, PCIC_INTR); 2272 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2273 Pcic_write(ph, PCIC_INTR, intr); 2274 delay(2 * 1000); 2275 2276 /* power down the socket */ 2277 power = Pcic_read(ph, PCIC_PWRCTL); 2278 power &= ~PCIC_PWRCTL_OE; 2279 Pcic_write(ph, PCIC_PWRCTL, power); 2280 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2281 /* 2282 * wait 300ms until power fails (Tpf). 2283 */ 2284 delay(300 * 1000); 2285 } 2286 2287 /* 2288 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2289 * 2290 * This function detects whether a card is in the slot or not. 2291 * If a card is inserted, return 1. Otherwise, return 0. 2292 */ 2293 STATIC int 2294 pccbb_pcmcia_card_detect(pch) 2295 pcmcia_chipset_handle_t pch; 2296 { 2297 struct pcic_handle *ph = (struct pcic_handle *)pch; 2298 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2299 2300 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2301 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2302 } 2303 2304 #if 0 2305 STATIC int 2306 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2307 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2308 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2309 #endif 2310 /* 2311 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2312 * bus_size_t size, 2313 * struct pcmcia_mem_handle *pcmhp) 2314 * 2315 * This function only allocates memory region for pccard. This 2316 * function never maps the allcated region to pccard memory area. 2317 * 2318 * XXX: Why the argument of start address is not in? 2319 */ 2320 STATIC int 2321 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2322 pcmcia_chipset_handle_t pch; 2323 bus_size_t size; 2324 struct pcmcia_mem_handle *pcmhp; 2325 { 2326 struct pcic_handle *ph = (struct pcic_handle *)pch; 2327 bus_space_handle_t memh; 2328 bus_addr_t addr; 2329 bus_size_t sizepg; 2330 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2331 #if rbus 2332 rbus_tag_t rb; 2333 #endif 2334 2335 /* out of sc->memh, allocate as many pages as necessary */ 2336 2337 /* convert size to PCIC pages */ 2338 /* 2339 * This is not enough; when the requested region is on the page 2340 * boundaries, this may calculate wrong result. 2341 */ 2342 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2343 #if 0 2344 if (sizepg > PCIC_MAX_MEM_PAGES) { 2345 return 1; 2346 } 2347 #endif 2348 2349 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2350 return 1; 2351 } 2352 2353 addr = 0; /* XXX gcc -Wuninitialized */ 2354 2355 #if rbus 2356 rb = sc->sc_rbus_memt; 2357 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2358 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2359 &addr, &memh)) { 2360 return 1; 2361 } 2362 #else 2363 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2364 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2365 0, /* boundary */ 2366 0, /* flags */ 2367 &addr, &memh)) { 2368 return 1; 2369 } 2370 #endif 2371 2372 DPRINTF( 2373 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2374 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2375 2376 pcmhp->memt = sc->sc_memt; 2377 pcmhp->memh = memh; 2378 pcmhp->addr = addr; 2379 pcmhp->size = size; 2380 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2381 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2382 pcmhp->mhandle = 0; 2383 /* No offset??? Funny. */ 2384 2385 return 0; 2386 } 2387 2388 /* 2389 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2390 * struct pcmcia_mem_handle *pcmhp) 2391 * 2392 * This function release the memory space allocated by the fuction 2393 * pccbb_pcmcia_mem_alloc(). 2394 */ 2395 STATIC void 2396 pccbb_pcmcia_mem_free(pch, pcmhp) 2397 pcmcia_chipset_handle_t pch; 2398 struct pcmcia_mem_handle *pcmhp; 2399 { 2400 #if rbus 2401 struct pcic_handle *ph = (struct pcic_handle *)pch; 2402 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2403 2404 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2405 #else 2406 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2407 #endif 2408 } 2409 2410 /* 2411 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2412 * 2413 * This function release the memory space allocated by the fuction 2414 * pccbb_pcmcia_mem_alloc(). 2415 */ 2416 STATIC void 2417 pccbb_pcmcia_do_mem_map(ph, win) 2418 struct pcic_handle *ph; 2419 int win; 2420 { 2421 int regbase_win; 2422 bus_addr_t phys_addr; 2423 bus_addr_t phys_end; 2424 2425 #define PCIC_SMM_START_LOW 0 2426 #define PCIC_SMM_START_HIGH 1 2427 #define PCIC_SMM_STOP_LOW 2 2428 #define PCIC_SMM_STOP_HIGH 3 2429 #define PCIC_CMA_LOW 4 2430 #define PCIC_CMA_HIGH 5 2431 2432 u_int8_t start_low, start_high = 0; 2433 u_int8_t stop_low, stop_high; 2434 u_int8_t off_low, off_high; 2435 u_int8_t mem_window; 2436 int reg; 2437 2438 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2439 int mem8 = 2440 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2441 || (kind == PCMCIA_MEM_ATTR); 2442 2443 regbase_win = 0x10 + win * 0x08; 2444 2445 phys_addr = ph->mem[win].addr; 2446 phys_end = phys_addr + ph->mem[win].size; 2447 2448 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2449 phys_addr, phys_end, ph->mem[win].offset)); 2450 2451 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2452 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2453 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2454 2455 /* bit 19:12 */ 2456 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2457 /* bit 23:20 and bit 7 on */ 2458 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2459 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2460 /* bit 31:24, for 32-bit address */ 2461 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2462 2463 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2464 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2465 2466 if (((struct pccbb_softc *)ph-> 2467 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2468 Pcic_write(ph, 0x40 + win, mem_window); 2469 } 2470 2471 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2472 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2473 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2474 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2475 2476 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2477 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2478 2479 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2480 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2481 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2482 | ((kind == PCMCIA_MEM_ATTR) ? 2483 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2484 2485 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2486 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2487 2488 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2489 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2490 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2491 2492 #if defined CBB_DEBUG 2493 { 2494 int r1, r2, r3, r4, r5, r6, r7 = 0; 2495 2496 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2497 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2498 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2499 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2500 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2501 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2502 if (((struct pccbb_softc *)(ph-> 2503 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2504 r7 = Pcic_read(ph, 0x40 + win); 2505 } 2506 2507 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2508 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2509 if (((struct pccbb_softc *)(ph-> 2510 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2511 DPRINTF((" %02x", r7)); 2512 } 2513 DPRINTF(("\n")); 2514 } 2515 #endif 2516 } 2517 2518 /* 2519 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2520 * bus_addr_t card_addr, bus_size_t size, 2521 * struct pcmcia_mem_handle *pcmhp, 2522 * bus_addr_t *offsetp, int *windowp) 2523 * 2524 * This function maps memory space allocated by the fuction 2525 * pccbb_pcmcia_mem_alloc(). 2526 */ 2527 STATIC int 2528 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2529 pcmcia_chipset_handle_t pch; 2530 int kind; 2531 bus_addr_t card_addr; 2532 bus_size_t size; 2533 struct pcmcia_mem_handle *pcmhp; 2534 bus_addr_t *offsetp; 2535 int *windowp; 2536 { 2537 struct pcic_handle *ph = (struct pcic_handle *)pch; 2538 bus_addr_t busaddr; 2539 long card_offset; 2540 int win; 2541 2542 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2543 if ((ph->memalloc & (1 << win)) == 0) { 2544 ph->memalloc |= (1 << win); 2545 break; 2546 } 2547 } 2548 2549 if (win == PCIC_MEM_WINS) { 2550 return 1; 2551 } 2552 2553 *windowp = win; 2554 2555 /* XXX this is pretty gross */ 2556 2557 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2558 panic("pccbb_pcmcia_mem_map memt is bogus"); 2559 } 2560 2561 busaddr = pcmhp->addr; 2562 2563 /* 2564 * compute the address offset to the pcmcia address space for the 2565 * pcic. this is intentionally signed. The masks and shifts below 2566 * will cause TRT to happen in the pcic registers. Deal with making 2567 * sure the address is aligned, and return the alignment offset. 2568 */ 2569 2570 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2571 card_addr -= *offsetp; 2572 2573 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2574 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2575 (u_long) card_addr)); 2576 2577 /* 2578 * include the offset in the size, and decrement size by one, since 2579 * the hw wants start/stop 2580 */ 2581 size += *offsetp - 1; 2582 2583 card_offset = (((long)card_addr) - ((long)busaddr)); 2584 2585 ph->mem[win].addr = busaddr; 2586 ph->mem[win].size = size; 2587 ph->mem[win].offset = card_offset; 2588 ph->mem[win].kind = kind; 2589 2590 pccbb_pcmcia_do_mem_map(ph, win); 2591 2592 return 0; 2593 } 2594 2595 /* 2596 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2597 * int window) 2598 * 2599 * This function unmaps memory space which mapped by the fuction 2600 * pccbb_pcmcia_mem_map(). 2601 */ 2602 STATIC void 2603 pccbb_pcmcia_mem_unmap(pch, window) 2604 pcmcia_chipset_handle_t pch; 2605 int window; 2606 { 2607 struct pcic_handle *ph = (struct pcic_handle *)pch; 2608 int reg; 2609 2610 if (window >= PCIC_MEM_WINS) { 2611 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2612 } 2613 2614 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2615 reg &= ~(1 << window); 2616 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2617 2618 ph->memalloc &= ~(1 << window); 2619 } 2620 2621 #if defined PCCBB_PCMCIA_POLL 2622 struct pccbb_poll_str { 2623 void *arg; 2624 int (*func) __P((void *)); 2625 int level; 2626 struct pcic_handle *ph; 2627 int count; 2628 int num; 2629 }; 2630 2631 static struct pccbb_poll_str pccbb_poll[10]; 2632 static int pccbb_poll_n = 0; 2633 2634 static void pccbb_pcmcia_poll __P((void *arg)); 2635 2636 static void 2637 pccbb_pcmcia_poll(arg) 2638 void *arg; 2639 { 2640 struct pccbb_poll_str *poll = arg; 2641 struct pcic_handle *ph = poll->ph; 2642 struct pccbb_softc *sc = ph->sc; 2643 int s; 2644 u_int32_t spsr; /* socket present-state reg */ 2645 2646 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2647 switch (poll->level) { 2648 case IPL_NET: 2649 s = splnet(); 2650 break; 2651 case IPL_BIO: 2652 s = splbio(); 2653 break; 2654 case IPL_TTY: /* fallthrough */ 2655 default: 2656 s = spltty(); 2657 break; 2658 } 2659 2660 spsr = 2661 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2662 CB_SOCKET_STAT); 2663 2664 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2665 if (!(spsr & 0x40)) /* CINT low */ 2666 #else 2667 if (1) 2668 #endif 2669 { 2670 if ((*poll->func) (poll->arg) > 0) { 2671 ++poll->count; 2672 // printf("intr: reported from poller, 0x%x\n", spsr); 2673 #if defined LEVEL2 2674 } else { 2675 printf("intr: miss! 0x%x\n", spsr); 2676 #endif 2677 } 2678 } 2679 splx(s); 2680 } 2681 #endif /* defined CB_PCMCIA_POLL */ 2682 2683 /* 2684 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2685 * struct pcmcia_function *pf, 2686 * int ipl, 2687 * int (*func)(void *), 2688 * void *arg); 2689 * 2690 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2691 */ 2692 STATIC void * 2693 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2694 pcmcia_chipset_handle_t pch; 2695 struct pcmcia_function *pf; 2696 int ipl; 2697 int (*func) __P((void *)); 2698 void *arg; 2699 { 2700 struct pcic_handle *ph = (struct pcic_handle *)pch; 2701 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2702 2703 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2704 /* what should I do? */ 2705 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2706 DPRINTF( 2707 ("%s does not provide edge nor pulse interrupt\n", 2708 sc->sc_dev.dv_xname)); 2709 return NULL; 2710 } 2711 /* 2712 * XXX Noooooo! The interrupt flag must set properly!! 2713 * dumb pcmcia driver!! 2714 */ 2715 } 2716 2717 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2718 } 2719 2720 /* 2721 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2722 * void *ih) 2723 * 2724 * This function disables PC-Card interrupt. 2725 */ 2726 STATIC void 2727 pccbb_pcmcia_intr_disestablish(pch, ih) 2728 pcmcia_chipset_handle_t pch; 2729 void *ih; 2730 { 2731 struct pcic_handle *ph = (struct pcic_handle *)pch; 2732 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2733 2734 pccbb_intr_disestablish(sc, ih); 2735 } 2736 2737 #if rbus 2738 /* 2739 * static int 2740 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2741 * bus_addr_t addr, bus_size_t size, 2742 * bus_addr_t mask, bus_size_t align, 2743 * int flags, bus_addr_t *addrp; 2744 * bus_space_handle_t *bshp) 2745 * 2746 * This function allocates a portion of memory or io space for 2747 * clients. This function is called from CardBus card drivers. 2748 */ 2749 static int 2750 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2751 cardbus_chipset_tag_t ct; 2752 rbus_tag_t rb; 2753 bus_addr_t addr; 2754 bus_size_t size; 2755 bus_addr_t mask; 2756 bus_size_t align; 2757 int flags; 2758 bus_addr_t *addrp; 2759 bus_space_handle_t *bshp; 2760 { 2761 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2762 2763 DPRINTF( 2764 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2765 addr, size, mask, align)); 2766 2767 if (align == 0) { 2768 align = size; 2769 } 2770 2771 if (rb->rb_bt == sc->sc_memt) { 2772 if (align < 16) { 2773 return 1; 2774 } 2775 } else if (rb->rb_bt == sc->sc_iot) { 2776 if (align < 4) { 2777 return 1; 2778 } 2779 } else { 2780 DPRINTF( 2781 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2782 rb->rb_bt)); 2783 return 1; 2784 /* XXX: panic here? */ 2785 } 2786 2787 /* XXX: hack for avoiding ISA image */ 2788 if (mask < 0x3ff) { 2789 mask = 0x3ff; 2790 addr = 0x300; 2791 } 2792 2793 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2794 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2795 return 1; 2796 } 2797 2798 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2799 2800 return 0; 2801 } 2802 2803 /* 2804 * static int 2805 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2806 * bus_space_handle_t *bshp, bus_size_t size); 2807 * 2808 * This function is called from CardBus card drivers. 2809 */ 2810 static int 2811 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2812 cardbus_chipset_tag_t ct; 2813 rbus_tag_t rb; 2814 bus_space_handle_t bsh; 2815 bus_size_t size; 2816 { 2817 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2818 bus_space_tag_t bt = rb->rb_bt; 2819 2820 pccbb_close_win(sc, bt, bsh, size); 2821 2822 if (bt == sc->sc_memt) { 2823 } else if (bt == sc->sc_iot) { 2824 } else { 2825 return 1; 2826 /* XXX: panic here? */ 2827 } 2828 2829 return rbus_space_free(rb, bsh, size, NULL); 2830 } 2831 #endif /* rbus */ 2832 2833 #if rbus 2834 2835 static int 2836 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2837 struct pccbb_softc *sc; 2838 bus_space_tag_t bst; 2839 bus_addr_t addr; 2840 bus_size_t size; 2841 bus_space_handle_t bsh; 2842 int flags; 2843 { 2844 struct pccbb_win_chain_head *head; 2845 bus_addr_t align; 2846 2847 head = &sc->sc_iowindow; 2848 align = 0x04; 2849 if (sc->sc_memt == bst) { 2850 head = &sc->sc_memwindow; 2851 align = 0x1000; 2852 DPRINTF(("using memory window, %x %x %x\n\n", 2853 sc->sc_iot, sc->sc_memt, bst)); 2854 } 2855 2856 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2857 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2858 sc->sc_dev.dv_xname, 2859 (head == &sc->sc_memwindow) ? "mem" : "io"); 2860 } 2861 pccbb_winset(align, sc, bst); 2862 2863 return 0; 2864 } 2865 2866 static int 2867 pccbb_close_win(sc, bst, bsh, size) 2868 struct pccbb_softc *sc; 2869 bus_space_tag_t bst; 2870 bus_space_handle_t bsh; 2871 bus_size_t size; 2872 { 2873 struct pccbb_win_chain_head *head; 2874 bus_addr_t align; 2875 2876 head = &sc->sc_iowindow; 2877 align = 0x04; 2878 if (sc->sc_memt == bst) { 2879 head = &sc->sc_memwindow; 2880 align = 0x1000; 2881 } 2882 2883 if (pccbb_winlist_delete(head, bsh, size)) { 2884 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2885 sc->sc_dev.dv_xname, 2886 (head == &sc->sc_memwindow) ? "mem" : "io"); 2887 } 2888 pccbb_winset(align, sc, bst); 2889 2890 return 0; 2891 } 2892 2893 static int 2894 pccbb_winlist_insert(head, start, size, bsh, flags) 2895 struct pccbb_win_chain_head *head; 2896 bus_addr_t start; 2897 bus_size_t size; 2898 bus_space_handle_t bsh; 2899 int flags; 2900 { 2901 struct pccbb_win_chain *chainp, *elem; 2902 2903 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2904 M_NOWAIT)) == NULL) 2905 return 1; /* fail */ 2906 2907 elem->wc_start = start; 2908 elem->wc_end = start + (size - 1); 2909 elem->wc_handle = bsh; 2910 elem->wc_flags = flags; 2911 2912 if ((chainp = TAILQ_FIRST(head)) == NULL) { 2913 TAILQ_INSERT_HEAD(head, elem, wc_list); 2914 return 0; 2915 } 2916 2917 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2918 if (chainp->wc_end < start) 2919 continue; 2920 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2921 return 0; 2922 } 2923 2924 TAILQ_INSERT_TAIL(head, elem, wc_list); 2925 2926 return 0; 2927 } 2928 2929 static int 2930 pccbb_winlist_delete(head, bsh, size) 2931 struct pccbb_win_chain_head *head; 2932 bus_space_handle_t bsh; 2933 bus_size_t size; 2934 { 2935 struct pccbb_win_chain *chainp; 2936 2937 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2938 chainp = TAILQ_NEXT(chainp, wc_list)) { 2939 if (chainp->wc_handle != bsh) 2940 continue; 2941 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2942 printf("pccbb_winlist_delete: window 0x%lx size " 2943 "inconsistent: 0x%lx, 0x%lx\n", 2944 chainp->wc_start, 2945 chainp->wc_end - chainp->wc_start, 2946 size - 1); 2947 return 1; 2948 } 2949 2950 TAILQ_REMOVE(head, chainp, wc_list); 2951 free(chainp, M_DEVBUF); 2952 2953 return 0; 2954 } 2955 2956 return 1; /* fail: no candidate to remove */ 2957 } 2958 2959 static void 2960 pccbb_winset(align, sc, bst) 2961 bus_addr_t align; 2962 struct pccbb_softc *sc; 2963 bus_space_tag_t bst; 2964 { 2965 pci_chipset_tag_t pc; 2966 pcitag_t tag; 2967 bus_addr_t mask = ~(align - 1); 2968 struct { 2969 cardbusreg_t win_start; 2970 cardbusreg_t win_limit; 2971 int win_flags; 2972 } win[2]; 2973 struct pccbb_win_chain *chainp; 2974 int offs; 2975 2976 win[0].win_start = 0xffffffff; 2977 win[0].win_limit = 0; 2978 win[1].win_start = 0xffffffff; 2979 win[1].win_limit = 0; 2980 2981 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2982 offs = 0x2c; 2983 if (sc->sc_memt == bst) { 2984 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2985 offs = 0x1c; 2986 } 2987 2988 if (chainp != NULL) { 2989 win[0].win_start = chainp->wc_start & mask; 2990 win[0].win_limit = chainp->wc_end & mask; 2991 win[0].win_flags = chainp->wc_flags; 2992 chainp = TAILQ_NEXT(chainp, wc_list); 2993 } 2994 2995 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2996 if (win[1].win_start == 0xffffffff) { 2997 /* window 1 is not used */ 2998 if ((win[0].win_flags == chainp->wc_flags) && 2999 (win[0].win_limit + align >= 3000 (chainp->wc_start & mask))) { 3001 /* concatenate */ 3002 win[0].win_limit = chainp->wc_end & mask; 3003 } else { 3004 /* make new window */ 3005 win[1].win_start = chainp->wc_start & mask; 3006 win[1].win_limit = chainp->wc_end & mask; 3007 win[1].win_flags = chainp->wc_flags; 3008 } 3009 continue; 3010 } 3011 3012 /* Both windows are engagad. */ 3013 if (win[0].win_flags == win[1].win_flags) { 3014 /* same flags */ 3015 if (win[0].win_flags == chainp->wc_flags) { 3016 if (win[1].win_start - (win[0].win_limit + 3017 align) < 3018 (chainp->wc_start & mask) - 3019 ((chainp->wc_end & mask) + align)) { 3020 /* 3021 * merge window 0 and 1, and set win1 3022 * to chainp 3023 */ 3024 win[0].win_limit = win[1].win_limit; 3025 win[1].win_start = 3026 chainp->wc_start & mask; 3027 win[1].win_limit = 3028 chainp->wc_end & mask; 3029 } else { 3030 win[1].win_limit = 3031 chainp->wc_end & mask; 3032 } 3033 } else { 3034 /* different flags */ 3035 3036 /* concatenate win0 and win1 */ 3037 win[0].win_limit = win[1].win_limit; 3038 /* allocate win[1] to new space */ 3039 win[1].win_start = chainp->wc_start & mask; 3040 win[1].win_limit = chainp->wc_end & mask; 3041 win[1].win_flags = chainp->wc_flags; 3042 } 3043 } else { 3044 /* the flags of win[0] and win[1] is different */ 3045 if (win[0].win_flags == chainp->wc_flags) { 3046 win[0].win_limit = chainp->wc_end & mask; 3047 /* 3048 * XXX this creates overlapping windows, so 3049 * what should the poor bridge do if one is 3050 * cachable, and the other is not? 3051 */ 3052 printf("%s: overlapping windows\n", 3053 sc->sc_dev.dv_xname); 3054 } else { 3055 win[1].win_limit = chainp->wc_end & mask; 3056 } 3057 } 3058 } 3059 3060 pc = sc->sc_pc; 3061 tag = sc->sc_tag; 3062 pci_conf_write(pc, tag, offs, win[0].win_start); 3063 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3064 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3065 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3066 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3067 pci_conf_read(pc, tag, offs), 3068 pci_conf_read(pc, tag, offs + 4) + align, 3069 pci_conf_read(pc, tag, offs + 8), 3070 pci_conf_read(pc, tag, offs + 12) + align)); 3071 3072 if (bst == sc->sc_memt) { 3073 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3074 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3075 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3076 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3077 } 3078 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3079 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3080 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3081 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3082 } 3083 } 3084 } 3085 3086 #endif /* rbus */ 3087 3088 static void 3089 pccbb_powerhook(why, arg) 3090 int why; 3091 void *arg; 3092 { 3093 struct pccbb_softc *sc = arg; 3094 u_int32_t reg; 3095 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3096 bus_space_handle_t base_memh = sc->sc_base_memh; 3097 3098 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3099 3100 if (why == PWR_RESUME) { 3101 /* CSC Interrupt: Card detect interrupt on */ 3102 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3103 /* Card detect intr is turned on. */ 3104 reg |= CB_SOCKET_MASK_CD; 3105 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3106 /* reset interrupt */ 3107 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3108 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3109 3110 /* 3111 * check for card insertion or removal during suspend period. 3112 * XXX: the code can't cope with card swap (remove then insert). 3113 * how can we detect such situation? 3114 */ 3115 if (why == PWR_RESUME) 3116 (void)pccbbintr(sc); 3117 } 3118 } 3119
Indexes created Thu Sep 25 16:09:42 GMT 2025