pccbb.c revision 1.33
1 /* $NetBSD: pccbb.c,v 1.33 2000/03/14 10:20:09 enami Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 int loopend = sizeof(yc_chipsets) / sizeof(yc_chipsets[0]); 355 struct yenta_chipinfo *ycp, *ycend; 356 357 ycend = yc_chipsets + loopend; 358 359 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 360 361 if (ycp == ycend) { 362 /* not found -- point at sentinel */ 363 ycp = yc_chipsets + loopend - 1; 364 } 365 366 if (flagp != NULL) { 367 *flagp = ycp->yc_flags; 368 } 369 370 return ycp->yc_chiptype; 371 } 372 373 static void 374 pccbb_shutdown(void *arg) 375 { 376 struct pccbb_softc *sc = arg; 377 pcireg_t command; 378 379 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 380 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 381 0); 382 383 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 384 385 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 386 PCI_COMMAND_MASTER_ENABLE); 387 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 388 389 } 390 391 void 392 pccbbattach(parent, self, aux) 393 struct device *parent; 394 struct device *self; 395 void *aux; 396 { 397 struct pccbb_softc *sc = (void *)self; 398 struct pci_attach_args *pa = aux; 399 pci_chipset_tag_t pc = pa->pa_pc; 400 pcireg_t sock_base, busreg; 401 bus_addr_t sockbase; 402 char devinfo[256]; 403 int flags; 404 405 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 406 407 pci_devinfo(pa->pa_id, 0, 0, devinfo); 408 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 409 #ifdef CBB_DEBUG 410 printf(" (chipflags %x)", flags); 411 #endif 412 printf("\n"); 413 414 TAILQ_INIT(&sc->sc_memwindow); 415 TAILQ_INIT(&sc->sc_iowindow); 416 417 #if rbus 418 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 419 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 420 #endif /* rbus */ 421 422 sc->sc_base_memh = 0; 423 424 /* 425 * MAP socket registers and ExCA registers on memory-space 426 * When no valid address is set on socket base registers (on pci 427 * config space), get it not polite way. 428 */ 429 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 430 431 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 432 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 433 /* The address must be valid. */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 435 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 436 printf("%s: can't map socket base address 0x%x\n", 437 sc->sc_dev.dv_xname, sock_base); 438 /* 439 * I think it's funny: socket base registers must be 440 * mapped on memory space, but ... 441 */ 442 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 443 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 444 NULL)) { 445 printf("%s: can't map socket base address" 446 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 447 sockbase); 448 /* give up... allocate reg space via rbus. */ 449 sc->sc_base_memh = 0; 450 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 451 } 452 } else { 453 DPRINTF(("%s: socket base address 0x%lx\n", 454 sc->sc_dev.dv_xname, sockbase)); 455 } 456 } 457 458 sc->sc_mem_start = 0; /* XXX */ 459 sc->sc_mem_end = 0xffffffff; /* XXX */ 460 461 /* 462 * When interrupt isn't routed correctly, give up probing cbb and do 463 * not kill pcic-compatible port. 464 */ 465 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 466 printf("%s: NOT USED because of unconfigured interrupt\n", 467 sc->sc_dev.dv_xname); 468 return; 469 } 470 471 /* 472 * When bus number isn't set correctly, give up using 32-bit CardBus 473 * mode. 474 */ 475 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 476 #if notyet 477 if (((busreg >> 8) & 0xff) == 0) { 478 printf("%s: CardBus support disabled because of unconfigured bus number\n", 479 sc->sc_dev.dv_xname); 480 flags |= PCCBB_PCMCIA_16BITONLY; 481 } 482 #endif 483 484 /* pccbb_machdep.c end */ 485 486 #if defined CBB_DEBUG 487 { 488 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 489 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 490 intrname[pa->pa_intrpin], pa->pa_intrline); 491 } 492 #endif 493 494 /* setup softc */ 495 sc->sc_pc = pc; 496 sc->sc_iot = pa->pa_iot; 497 sc->sc_memt = pa->pa_memt; 498 sc->sc_dmat = pa->pa_dmat; 499 sc->sc_tag = pa->pa_tag; 500 sc->sc_function = pa->pa_function; 501 502 sc->sc_intrline = pa->pa_intrline; 503 sc->sc_intrtag = pa->pa_intrtag; 504 sc->sc_intrpin = pa->pa_intrpin; 505 506 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 507 508 shutdownhook_establish(pccbb_shutdown, sc); 509 510 #if __NetBSD_Version__ > 103060000 511 config_defer(self, pccbb_pci_callback); 512 #else 513 pccbb_pci_callback(self); 514 #endif 515 } 516 517 518 519 520 /* 521 * static void pccbb_pci_callback(struct device *self) 522 * 523 * The actual attach routine: get memory space for YENTA register 524 * space, setup YENTA register and route interrupt. 525 * 526 * This function should be deferred because this device may obtain 527 * memory space dynamically. This function must avoid obtaining 528 * memory area which has already kept for another device. Also, 529 * this function MUST be done before ISA attach process because this 530 * function kills pcic compatible port used by ISA pcic. 531 */ 532 static void 533 pccbb_pci_callback(self) 534 struct device *self; 535 { 536 struct pccbb_softc *sc = (void *)self; 537 pci_chipset_tag_t pc = sc->sc_pc; 538 bus_space_tag_t base_memt; 539 bus_space_handle_t base_memh; 540 u_int32_t maskreg; 541 pci_intr_handle_t ih; 542 const char *intrstr = NULL; 543 bus_addr_t sockbase; 544 struct cbslot_attach_args cba; 545 struct pcmciabus_attach_args paa; 546 struct cardslot_attach_args caa; 547 struct cardslot_softc *csc; 548 549 if (0 == sc->sc_base_memh) { 550 /* The socket registers aren't mapped correctly. */ 551 #if rbus 552 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 553 (sc->sc_chipset == CB_RX5C47X 554 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 555 0, &sockbase, &sc->sc_base_memh)) { 556 return; 557 } 558 sc->sc_base_memt = sc->sc_memt; 559 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 560 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 561 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 562 PCI_SOCKBASE))); 563 #else 564 sc->sc_base_memt = sc->sc_memt; 565 #if !defined CBB_PCI_BASE 566 #define CBB_PCI_BASE 0x20000000 567 #endif 568 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 569 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 570 /* cannot allocate memory space */ 571 return; 572 } 573 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 574 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 575 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 576 sc->sc_tag, PCI_SOCKBASE))); 577 #endif 578 } 579 580 /* bus bridge initialization */ 581 pccbb_chipinit(sc); 582 583 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 584 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 585 586 /* CSC Interrupt: Card detect interrupt on */ 587 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 588 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 589 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 590 /* reset interrupt */ 591 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 592 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 593 594 /* Map and establish the interrupt. */ 595 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 596 sc->sc_intrline, &ih)) { 597 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 598 return; 599 } 600 intrstr = pci_intr_string(pc, ih); 601 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 602 603 if (sc->sc_ih == NULL) { 604 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 605 if (intrstr != NULL) { 606 printf(" at %s", intrstr); 607 } 608 printf("\n"); 609 return; 610 } 611 612 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 613 powerhook_establish(pccbb_powerhook, sc); 614 615 { 616 u_int32_t sockstat = 617 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 618 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 619 sc->sc_flags |= CBB_CARDEXIST; 620 } 621 } 622 623 /* 624 * attach cardbus 625 */ 626 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 627 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 628 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 629 630 /* initialize cbslot_attach */ 631 cba.cba_busname = "cardbus"; 632 cba.cba_iot = sc->sc_iot; 633 cba.cba_memt = sc->sc_memt; 634 cba.cba_dmat = sc->sc_dmat; 635 cba.cba_function = 0; 636 cba.cba_bus = (busreg >> 8) & 0x0ff; 637 cba.cba_cc = (void *)sc; 638 cba.cba_cf = &pccbb_funcs; 639 cba.cba_intrline = sc->sc_intrline; 640 641 #if rbus 642 cba.cba_rbus_iot = sc->sc_rbus_iot; 643 cba.cba_rbus_memt = sc->sc_rbus_memt; 644 #endif 645 646 cba.cba_cacheline = PCI_CACHELINE(bhlc); 647 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 648 649 printf("%s: cacheline 0x%x lattimer 0x%x\n", 650 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 651 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 652 busreg); 653 #if defined SHOW_REGS 654 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 655 sc->sc_base_memh); 656 #endif 657 } 658 659 pccbb_pcmcia_attach_setup(sc, &paa); 660 caa.caa_cb_attach = NULL; 661 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 662 caa.caa_cb_attach = &cba; 663 } 664 caa.caa_16_attach = &paa; 665 caa.caa_ph = &sc->sc_pcmcia_h; 666 667 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 668 DPRINTF(("pccbbattach: found cardslot\n")); 669 sc->sc_csc = csc; 670 } 671 672 return; 673 } 674 675 676 677 678 679 /* 680 * static void pccbb_chipinit(struct pccbb_softc *sc) 681 * 682 * This function initialize YENTA chip registers listed below: 683 * 1) PCI command reg, 684 * 2) PCI and CardBus latency timer, 685 * 3) disable legacy (PCIC-compatible) io, 686 * 4) route PCI interrupt, 687 * 5) close all memory and io windows. 688 */ 689 static void 690 pccbb_chipinit(sc) 691 struct pccbb_softc *sc; 692 { 693 pci_chipset_tag_t pc = sc->sc_pc; 694 pcitag_t tag = sc->sc_tag; 695 pcireg_t reg; 696 697 /* 698 * Set PCI command reg. 699 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 700 */ 701 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 702 /* I believe it is harmless. */ 703 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 704 PCI_COMMAND_MASTER_ENABLE); 705 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 706 707 /* 708 * Set CardBus latency timer. 709 */ 710 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 711 if (PCI_CB_LATENCY(reg) < 0x20) { 712 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 713 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 714 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 715 } 716 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 717 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 718 719 /* 720 * Set PCI latency timer. 721 */ 722 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 723 if (PCI_LATTIMER(reg) < 0x10) { 724 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 725 reg |= (0x10 << PCI_LATTIMER_SHIFT); 726 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 727 } 728 DPRINTF(("PCI latency timer 0x%x (%x)\n", 729 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 730 731 /* Disable legacy register mapping. */ 732 switch (sc->sc_chipset) { 733 case CB_RX5C46X: /* fallthrough */ 734 #if 0 735 case CB_RX5C47X: 736 #endif 737 /* 738 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 739 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 740 * CardBus bridges have special bits on Bridge control reg (addr 741 * 0x3e on PCI config space). 742 */ 743 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 744 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 745 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 746 break; 747 748 default: 749 /* XXX I don't know proper way to kill legacy I/O. */ 750 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 751 break; 752 } 753 754 /* Route functional interrupts to PCI. */ 755 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 756 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 757 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 758 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 759 760 switch (sc->sc_chipset) { 761 case CB_TI113X: 762 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 763 /* This bit is shared, but may read as 0 on some chips, so set 764 it explicitly on both functions. */ 765 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 766 /* CSC intr enable */ 767 reg |= PCI113X_CBCTRL_PCI_CSC; 768 /* functional intr prohibit */ 769 reg &= ~PCI113X_CBCTRL_PCI_INTR; 770 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 771 break; 772 773 case CB_TOPIC95B: 774 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 775 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 776 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 777 778 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 779 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 780 sc->sc_dev.dv_xname, reg)); 781 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 782 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 783 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 784 DPRINTF(("0x%x\n", reg)); 785 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 786 break; 787 } 788 789 /* Close all memory and I/O windows. */ 790 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 791 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 792 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 793 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 794 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 795 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 796 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 797 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 798 } 799 800 801 802 803 /* 804 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 805 * struct pcmciabus_attach_args *paa) 806 * 807 * This function attaches 16-bit PCcard bus. 808 */ 809 STATIC void 810 pccbb_pcmcia_attach_setup(sc, paa) 811 struct pccbb_softc *sc; 812 struct pcmciabus_attach_args *paa; 813 { 814 struct pcic_handle *ph = &sc->sc_pcmcia_h; 815 #if rbus 816 rbus_tag_t rb; 817 #endif 818 819 /* initialize pcmcia part in pccbb_softc */ 820 ph->ph_parent = (struct device *)sc; 821 ph->sock = sc->sc_function; 822 ph->flags = 0; 823 ph->shutdown = 0; 824 ph->ih_irq = sc->sc_intrline; 825 ph->ph_bus_t = sc->sc_base_memt; 826 ph->ph_bus_h = sc->sc_base_memh; 827 ph->ph_read = pccbb_pcmcia_read; 828 ph->ph_write = pccbb_pcmcia_write; 829 sc->sc_pct = &pccbb_pcmcia_funcs; 830 831 /* 832 * We need to do a few things here: 833 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 834 * setting the IRQ numbers to 0. 835 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 836 * routing of CSC interrupts (e.g. card removal) to PCI while in 837 * PCMCIA mode. We just leave this set all the time. 838 * 3) Enable card insertion/removal interrupts in case the chip also 839 * needs that while in PCMCIA mode. 840 * 4) Clear any pending CSC interrupt. 841 */ 842 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 843 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 844 Pcic_read(ph, PCIC_CSC); 845 846 /* initialize pcmcia bus attachment */ 847 paa->paa_busname = "pcmcia"; 848 paa->pct = sc->sc_pct; 849 paa->pch = ph; 850 paa->iobase = 0; /* I don't use them */ 851 paa->iosize = 0; 852 #if rbus 853 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 854 paa->iobase = rb->rb_start + rb->rb_offset; 855 paa->iosize = rb->rb_end - rb->rb_start; 856 #endif 857 858 return; 859 } 860 861 #if 0 862 STATIC void 863 pccbb_pcmcia_attach_card(ph) 864 struct pcic_handle *ph; 865 { 866 if (ph->flags & PCIC_FLAG_CARDP) { 867 panic("pccbb_pcmcia_attach_card: already attached"); 868 } 869 870 /* call the MI attach function */ 871 pcmcia_card_attach(ph->pcmcia); 872 873 ph->flags |= PCIC_FLAG_CARDP; 874 } 875 876 STATIC void 877 pccbb_pcmcia_detach_card(ph, flags) 878 struct pcic_handle *ph; 879 int flags; 880 { 881 if (!(ph->flags & PCIC_FLAG_CARDP)) { 882 panic("pccbb_pcmcia_detach_card: already detached"); 883 } 884 885 ph->flags &= ~PCIC_FLAG_CARDP; 886 887 /* call the MI detach function */ 888 pcmcia_card_detach(ph->pcmcia, flags); 889 } 890 #endif 891 892 /* 893 * int pccbbintr(arg) 894 * void *arg; 895 * This routine handles the interrupt from Yenta PCI-CardBus bridge 896 * itself. 897 */ 898 int 899 pccbbintr(arg) 900 void *arg; 901 { 902 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 903 u_int32_t sockevent, sockstate; 904 bus_space_tag_t memt = sc->sc_base_memt; 905 bus_space_handle_t memh = sc->sc_base_memh; 906 struct pcic_handle *ph = &sc->sc_pcmcia_h; 907 908 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 909 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 910 Pcic_read(ph, PCIC_CSC); 911 912 if (sockevent == 0) { 913 /* This intr is not for me: it may be for my child devices. */ 914 return (pccbbintr_function(sc)); 915 } 916 917 if (sockevent & CB_SOCKET_EVENT_CD) { 918 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 919 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 920 /* A card should be removed. */ 921 if (sc->sc_flags & CBB_CARDEXIST) { 922 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 923 sockevent)); 924 DPRINTF((" card removed, 0x%08x\n", sockstate)); 925 sc->sc_flags &= ~CBB_CARDEXIST; 926 if (sc->sc_csc->sc_status & 927 CARDSLOT_STATUS_CARD_16) { 928 #if 0 929 struct pcic_handle *ph = 930 &sc->sc_pcmcia_h; 931 932 pcmcia_card_deactivate(ph->pcmcia); 933 pccbb_pcmcia_socket_disable(ph); 934 pccbb_pcmcia_detach_card(ph, 935 DETACH_FORCE); 936 #endif 937 cardslot_event_throw(sc->sc_csc, 938 CARDSLOT_EVENT_REMOVAL_16); 939 } else if (sc->sc_csc->sc_status & 940 CARDSLOT_STATUS_CARD_CB) { 941 /* Cardbus intr removed */ 942 cardslot_event_throw(sc->sc_csc, 943 CARDSLOT_EVENT_REMOVAL_CB); 944 } 945 } 946 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 947 if (sc->sc_flags & CBB_INSERTING) { 948 untimeout(pci113x_insert, sc); 949 } 950 timeout(pci113x_insert, sc, hz / 10); 951 sc->sc_flags |= CBB_INSERTING; 952 } 953 } 954 955 return (1); 956 } 957 958 /* 959 * static int pccbbintr_function(struct pccbb_softc *sc) 960 * 961 * This function calls each interrupt handler registered at the 962 * bridge. The interrupt handlers are called in registered order. 963 */ 964 static int 965 pccbbintr_function(sc) 966 struct pccbb_softc *sc; 967 { 968 int retval = 0, val; 969 struct pccbb_intrhand_list *pil; 970 971 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 972 val = (*pil->pil_func) (pil->pil_arg); 973 retval = retval == 1 ? 1 : 974 retval == 0 ? val : val != 0 ? val : retval; 975 } 976 977 return retval; 978 } 979 980 static void 981 pci113x_insert(arg) 982 void *arg; 983 { 984 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 985 u_int32_t sockevent, sockstate; 986 987 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 988 CB_SOCKET_EVENT); 989 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 990 CB_SOCKET_STAT); 991 992 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 993 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 994 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 995 sc->sc_flags |= CBB_CARDEXIST; 996 /* call pccard interrupt handler here */ 997 if (sockstate & CB_SOCKET_STAT_16BIT) { 998 /* 16-bit card found */ 999 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1000 cardslot_event_throw(sc->sc_csc, 1001 CARDSLOT_EVENT_INSERTION_16); 1002 } else if (sockstate & CB_SOCKET_STAT_CB) { 1003 /* cardbus card found */ 1004 /* cardbus_attach_card(sc->sc_csc); */ 1005 cardslot_event_throw(sc->sc_csc, 1006 CARDSLOT_EVENT_INSERTION_CB); 1007 } else { 1008 /* who are you? */ 1009 } 1010 } else { 1011 timeout(pci113x_insert, sc, hz / 10); 1012 } 1013 } 1014 1015 #define PCCBB_PCMCIA_OFFSET 0x800 1016 static u_int8_t 1017 pccbb_pcmcia_read(ph, reg) 1018 struct pcic_handle *ph; 1019 int reg; 1020 { 1021 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1022 PCCBB_PCMCIA_OFFSET + reg); 1023 } 1024 1025 static void 1026 pccbb_pcmcia_write(ph, reg, val) 1027 struct pcic_handle *ph; 1028 int reg; 1029 u_int8_t val; 1030 { 1031 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1032 val); 1033 } 1034 1035 /* 1036 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1037 */ 1038 STATIC int 1039 pccbb_ctrl(ct, command) 1040 cardbus_chipset_tag_t ct; 1041 int command; 1042 { 1043 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1044 1045 switch (command) { 1046 case CARDBUS_CD: 1047 if (2 == pccbb_detect_card(sc)) { 1048 int retval = 0; 1049 int status = cb_detect_voltage(sc); 1050 if (PCCARD_VCC_5V & status) { 1051 retval |= CARDBUS_5V_CARD; 1052 } 1053 if (PCCARD_VCC_3V & status) { 1054 retval |= CARDBUS_3V_CARD; 1055 } 1056 if (PCCARD_VCC_XV & status) { 1057 retval |= CARDBUS_XV_CARD; 1058 } 1059 if (PCCARD_VCC_YV & status) { 1060 retval |= CARDBUS_YV_CARD; 1061 } 1062 return retval; 1063 } else { 1064 return 0; 1065 } 1066 break; 1067 case CARDBUS_RESET: 1068 return cb_reset(sc); 1069 break; 1070 case CARDBUS_IO_ENABLE: /* fallthrough */ 1071 case CARDBUS_IO_DISABLE: /* fallthrough */ 1072 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1073 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1074 case CARDBUS_BM_ENABLE: /* fallthrough */ 1075 case CARDBUS_BM_DISABLE: /* fallthrough */ 1076 return pccbb_cardenable(sc, command); 1077 break; 1078 } 1079 1080 return 0; 1081 } 1082 1083 /* 1084 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1085 * This function returns true when it succeeds and returns false when 1086 * it fails. 1087 */ 1088 STATIC int 1089 pccbb_power(ct, command) 1090 cardbus_chipset_tag_t ct; 1091 int command; 1092 { 1093 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1094 1095 u_int32_t status, sock_ctrl; 1096 bus_space_tag_t memt = sc->sc_base_memt; 1097 bus_space_handle_t memh = sc->sc_base_memh; 1098 1099 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1100 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1101 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1102 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1103 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1104 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1105 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1106 "UNKNOWN", 1107 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1108 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1109 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1110 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1111 "UNKNOWN", command)); 1112 1113 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1114 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1115 1116 switch (command & CARDBUS_VCCMASK) { 1117 case CARDBUS_VCC_UC: 1118 break; 1119 case CARDBUS_VCC_5V: 1120 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1121 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1122 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1123 } else { 1124 printf("%s: BAD voltage request: no 5 V card\n", 1125 sc->sc_dev.dv_xname); 1126 } 1127 break; 1128 case CARDBUS_VCC_3V: 1129 if (CB_SOCKET_STAT_3VCARD & status) { 1130 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1131 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1132 } else { 1133 printf("%s: BAD voltage request: no 3.3 V card\n", 1134 sc->sc_dev.dv_xname); 1135 } 1136 break; 1137 case CARDBUS_VCC_0V: 1138 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1139 break; 1140 default: 1141 return 0; /* power NEVER changed */ 1142 break; 1143 } 1144 1145 switch (command & CARDBUS_VPPMASK) { 1146 case CARDBUS_VPP_UC: 1147 break; 1148 case CARDBUS_VPP_0V: 1149 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1150 break; 1151 case CARDBUS_VPP_VCC: 1152 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1153 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1154 break; 1155 case CARDBUS_VPP_12V: 1156 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1157 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1158 break; 1159 } 1160 1161 #if 0 1162 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1163 #endif 1164 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1165 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1166 1167 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1168 /* 1169 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1170 * time is 20 ms, some PC-Card bridge requires longer duration. 1171 */ 1172 delay(200 * 1000); 1173 1174 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1175 printf 1176 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1177 sc->sc_dev.dv_xname, sock_ctrl, status); 1178 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1179 (command & CARDBUS_VCCMASK) == 1180 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1181 CARDBUS_VCCMASK) == 1182 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1183 CARDBUS_VCCMASK) == 1184 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1185 CARDBUS_VCCMASK) == 1186 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1187 CARDBUS_VCCMASK) == 1188 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1189 CARDBUS_VCCMASK) == 1190 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1191 (command & CARDBUS_VPPMASK) == 1192 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1193 CARDBUS_VPPMASK) == 1194 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1195 CARDBUS_VPPMASK) == 1196 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1197 CARDBUS_VPPMASK) == 1198 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1199 #if 0 1200 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1201 u_int32_t force = 1202 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1203 /* Reset Bad Vcc request */ 1204 force &= ~CB_SOCKET_FORCE_BADVCC; 1205 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1206 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1207 CB_SOCKET_STAT)); 1208 return 1; 1209 } 1210 #endif 1211 return 0; 1212 } 1213 return 1; /* power changed correctly */ 1214 } 1215 1216 #if defined CB_PCMCIA_POLL 1217 struct cb_poll_str { 1218 void *arg; 1219 int (*func) __P((void *)); 1220 int level; 1221 pccard_chipset_tag_t ct; 1222 int count; 1223 }; 1224 1225 static struct cb_poll_str cb_poll[10]; 1226 static int cb_poll_n = 0; 1227 1228 static void cb_pcmcia_poll __P((void *arg)); 1229 1230 static void 1231 cb_pcmcia_poll(arg) 1232 void *arg; 1233 { 1234 struct cb_poll_str *poll = arg; 1235 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1236 struct pccbb_softc *sc = psc->cpc_parent; 1237 int s; 1238 u_int32_t spsr; /* socket present-state reg */ 1239 1240 timeout(cb_pcmcia_poll, arg, hz / 10); 1241 switch (poll->level) { 1242 case IPL_NET: 1243 s = splnet(); 1244 break; 1245 case IPL_BIO: 1246 s = splbio(); 1247 break; 1248 case IPL_TTY: /* fallthrough */ 1249 default: 1250 s = spltty(); 1251 break; 1252 } 1253 1254 spsr = 1255 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1256 CB_SOCKET_STAT); 1257 1258 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1259 if (!(spsr & 0x40)) { /* CINT low */ 1260 #else 1261 if (1) { 1262 #endif 1263 if ((*poll->func) (poll->arg) == 1) { 1264 ++poll->count; 1265 printf("intr: reported from poller, 0x%x\n", spsr); 1266 #if defined LEVEL2 1267 } else { 1268 printf("intr: miss! 0x%x\n", spsr); 1269 #endif 1270 } 1271 } 1272 splx(s); 1273 } 1274 #endif /* defined CB_PCMCIA_POLL */ 1275 1276 /* 1277 * static int pccbb_detect_card(struct pccbb_softc *sc) 1278 * return value: 0 if no card exists. 1279 * 1 if 16-bit card exists. 1280 * 2 if cardbus card exists. 1281 */ 1282 static int 1283 pccbb_detect_card(sc) 1284 struct pccbb_softc *sc; 1285 { 1286 bus_space_handle_t base_memh = sc->sc_base_memh; 1287 bus_space_tag_t base_memt = sc->sc_base_memt; 1288 u_int32_t sockstat = 1289 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1290 int retval = 0; 1291 1292 /* CD1 and CD2 asserted */ 1293 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1294 /* card must be present */ 1295 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1296 /* NOTACARD DEASSERTED */ 1297 if (CB_SOCKET_STAT_CB & sockstat) { 1298 /* CardBus mode */ 1299 retval = 2; 1300 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1301 /* 16-bit mode */ 1302 retval = 1; 1303 } 1304 } 1305 } 1306 return retval; 1307 } 1308 1309 /* 1310 * STATIC int cb_reset(struct pccbb_softc *sc) 1311 * This function resets CardBus card. 1312 */ 1313 STATIC int 1314 cb_reset(sc) 1315 struct pccbb_softc *sc; 1316 { 1317 /* 1318 * Reset Assert at least 20 ms 1319 * Some machines request longer duration. 1320 */ 1321 int reset_duration = 1322 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1323 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1324 1325 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1326 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1327 delay(reset_duration); 1328 1329 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1330 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1331 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1332 delay(reset_duration); 1333 } 1334 /* No card found on the slot. Keep Reset. */ 1335 return 1; 1336 } 1337 1338 /* 1339 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1340 * This function detect card Voltage. 1341 */ 1342 STATIC int 1343 cb_detect_voltage(sc) 1344 struct pccbb_softc *sc; 1345 { 1346 u_int32_t psr; /* socket present-state reg */ 1347 bus_space_tag_t iot = sc->sc_base_memt; 1348 bus_space_handle_t ioh = sc->sc_base_memh; 1349 int vol = PCCARD_VCC_UKN; /* set 0 */ 1350 1351 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1352 1353 if (0x400u & psr) { 1354 vol |= PCCARD_VCC_5V; 1355 } 1356 if (0x800u & psr) { 1357 vol |= PCCARD_VCC_3V; 1358 } 1359 1360 return vol; 1361 } 1362 1363 STATIC int 1364 cbbprint(aux, pcic) 1365 void *aux; 1366 const char *pcic; 1367 { 1368 /* 1369 struct cbslot_attach_args *cba = aux; 1370 1371 if (cba->cba_slot >= 0) { 1372 printf(" slot %d", cba->cba_slot); 1373 } 1374 */ 1375 return UNCONF; 1376 } 1377 1378 /* 1379 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1380 * This function enables and disables the card 1381 */ 1382 STATIC int 1383 pccbb_cardenable(sc, function) 1384 struct pccbb_softc *sc; 1385 int function; 1386 { 1387 u_int32_t command = 1388 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1389 1390 DPRINTF(("pccbb_cardenable:")); 1391 switch (function) { 1392 case CARDBUS_IO_ENABLE: 1393 command |= PCI_COMMAND_IO_ENABLE; 1394 break; 1395 case CARDBUS_IO_DISABLE: 1396 command &= ~PCI_COMMAND_IO_ENABLE; 1397 break; 1398 case CARDBUS_MEM_ENABLE: 1399 command |= PCI_COMMAND_MEM_ENABLE; 1400 break; 1401 case CARDBUS_MEM_DISABLE: 1402 command &= ~PCI_COMMAND_MEM_ENABLE; 1403 break; 1404 case CARDBUS_BM_ENABLE: 1405 command |= PCI_COMMAND_MASTER_ENABLE; 1406 break; 1407 case CARDBUS_BM_DISABLE: 1408 command &= ~PCI_COMMAND_MASTER_ENABLE; 1409 break; 1410 default: 1411 return 0; 1412 } 1413 1414 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1415 DPRINTF((" command reg 0x%x\n", command)); 1416 return 1; 1417 } 1418 1419 #if !rbus 1420 /* 1421 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1422 */ 1423 static int 1424 pccbb_io_open(ct, win, start, end) 1425 cardbus_chipset_tag_t ct; 1426 int win; 1427 u_int32_t start, end; 1428 { 1429 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1430 int basereg; 1431 int limitreg; 1432 1433 if ((win < 0) || (win > 2)) { 1434 #if defined DIAGNOSTIC 1435 printf("cardbus_io_open: window out of range %d\n", win); 1436 #endif 1437 return 0; 1438 } 1439 1440 basereg = win * 8 + 0x2c; 1441 limitreg = win * 8 + 0x30; 1442 1443 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1444 start, basereg, end, limitreg)); 1445 1446 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1447 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1448 return 1; 1449 } 1450 1451 /* 1452 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1453 */ 1454 static int 1455 pccbb_io_close(ct, win) 1456 cardbus_chipset_tag_t ct; 1457 int win; 1458 { 1459 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1460 int basereg; 1461 int limitreg; 1462 1463 if ((win < 0) || (win > 2)) { 1464 #if defined DIAGNOSTIC 1465 printf("cardbus_io_close: window out of range %d\n", win); 1466 #endif 1467 return 0; 1468 } 1469 1470 basereg = win * 8 + 0x2c; 1471 limitreg = win * 8 + 0x30; 1472 1473 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1474 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1475 return 1; 1476 } 1477 1478 /* 1479 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1480 */ 1481 static int 1482 pccbb_mem_open(ct, win, start, end) 1483 cardbus_chipset_tag_t ct; 1484 int win; 1485 u_int32_t start, end; 1486 { 1487 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1488 int basereg; 1489 int limitreg; 1490 1491 if ((win < 0) || (win > 2)) { 1492 #if defined DIAGNOSTIC 1493 printf("cardbus_mem_open: window out of range %d\n", win); 1494 #endif 1495 return 0; 1496 } 1497 1498 basereg = win * 8 + 0x1c; 1499 limitreg = win * 8 + 0x20; 1500 1501 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1502 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1503 return 1; 1504 } 1505 1506 /* 1507 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1508 */ 1509 static int 1510 pccbb_mem_close(ct, win) 1511 cardbus_chipset_tag_t ct; 1512 int win; 1513 { 1514 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1515 int basereg; 1516 int limitreg; 1517 1518 if ((win < 0) || (win > 2)) { 1519 #if defined DIAGNOSTIC 1520 printf("cardbus_mem_close: window out of range %d\n", win); 1521 #endif 1522 return 0; 1523 } 1524 1525 basereg = win * 8 + 0x1c; 1526 limitreg = win * 8 + 0x20; 1527 1528 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1529 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1530 return 1; 1531 } 1532 #endif 1533 1534 /* 1535 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1536 * int irq, 1537 * int level, 1538 * int (* func) __P((void *)), 1539 * void *arg) 1540 * 1541 * This function registers an interrupt handler at the bridge, in 1542 * order not to call the interrupt handlers of child devices when 1543 * a card-deletion interrupt occurs. 1544 * 1545 * The arguments irq and level are not used. 1546 */ 1547 static void * 1548 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1549 cardbus_chipset_tag_t ct; 1550 int irq, level; 1551 int (*func) __P((void *)); 1552 void *arg; 1553 { 1554 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1555 1556 return pccbb_intr_establish(sc, irq, level, func, arg); 1557 } 1558 1559 1560 /* 1561 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1562 * void *ih) 1563 * 1564 * This function removes an interrupt handler pointed by ih. 1565 */ 1566 static void 1567 pccbb_cb_intr_disestablish(ct, ih) 1568 cardbus_chipset_tag_t ct; 1569 void *ih; 1570 { 1571 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1572 1573 pccbb_intr_disestablish(sc, ih); 1574 } 1575 1576 1577 /* 1578 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1579 * int irq, 1580 * int level, 1581 * int (* func) __P((void *)), 1582 * void *arg) 1583 * 1584 * This function registers an interrupt handler at the bridge, in 1585 * order not to call the interrupt handlers of child devices when 1586 * a card-deletion interrupt occurs. 1587 * 1588 * The arguments irq and level are not used. 1589 */ 1590 static void * 1591 pccbb_intr_establish(sc, irq, level, func, arg) 1592 struct pccbb_softc *sc; 1593 int irq, level; 1594 int (*func) __P((void *)); 1595 void *arg; 1596 { 1597 struct pccbb_intrhand_list *pil, *newpil; 1598 1599 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1600 1601 if (sc->sc_pil == NULL) { 1602 /* initialize bridge intr routing */ 1603 1604 switch (sc->sc_chipset) { 1605 case CB_TI113X: 1606 { 1607 pcireg_t cbctrl = 1608 pci_conf_read(sc->sc_pc, sc->sc_tag, 1609 PCI_CBCTRL); 1610 /* functional intr enabled */ 1611 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, 1613 PCI_CBCTRL, cbctrl); 1614 break; 1615 } 1616 default: 1617 break; 1618 } 1619 } 1620 1621 /* 1622 * Allocate a room for interrupt handler structure. 1623 */ 1624 if (NULL == (newpil = 1625 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1626 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1627 return NULL; 1628 } 1629 1630 newpil->pil_func = func; 1631 newpil->pil_arg = arg; 1632 newpil->pil_next = NULL; 1633 1634 if (sc->sc_pil == NULL) { 1635 sc->sc_pil = newpil; 1636 } else { 1637 for (pil = sc->sc_pil; pil->pil_next != NULL; 1638 pil = pil->pil_next); 1639 pil->pil_next = newpil; 1640 } 1641 1642 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1643 1644 return newpil; 1645 } 1646 1647 /* 1648 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1649 * void *ih) 1650 * 1651 * This function removes an interrupt handler pointed by ih. 1652 */ 1653 static void 1654 pccbb_intr_disestablish(sc, ih) 1655 struct pccbb_softc *sc; 1656 void *ih; 1657 { 1658 struct pccbb_intrhand_list *pil, **pil_prev; 1659 1660 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1661 1662 pil_prev = &sc->sc_pil; 1663 1664 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1665 if (pil == ih) { 1666 *pil_prev = pil->pil_next; 1667 free(pil, M_DEVBUF); 1668 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1669 break; 1670 } 1671 pil_prev = &pil->pil_next; 1672 } 1673 1674 if (sc->sc_pil == NULL) { 1675 /* No interrupt handlers */ 1676 1677 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1678 1679 switch (sc->sc_chipset) { 1680 case CB_TI113X: 1681 { 1682 pcireg_t cbctrl = 1683 pci_conf_read(sc->sc_pc, sc->sc_tag, 1684 PCI_CBCTRL); 1685 /* functional intr disabled */ 1686 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1687 pci_conf_write(sc->sc_pc, sc->sc_tag, 1688 PCI_CBCTRL, cbctrl); 1689 break; 1690 } 1691 default: 1692 break; 1693 } 1694 } 1695 } 1696 1697 #if defined SHOW_REGS 1698 static void 1699 cb_show_regs(pc, tag, memt, memh) 1700 pci_chipset_tag_t pc; 1701 pcitag_t tag; 1702 bus_space_tag_t memt; 1703 bus_space_handle_t memh; 1704 { 1705 int i; 1706 printf("PCI config regs:"); 1707 for (i = 0; i < 0x50; i += 4) { 1708 if (i % 16 == 0) { 1709 printf("\n 0x%02x:", i); 1710 } 1711 printf(" %08x", pci_conf_read(pc, tag, i)); 1712 } 1713 for (i = 0x80; i < 0xb0; i += 4) { 1714 if (i % 16 == 0) { 1715 printf("\n 0x%02x:", i); 1716 } 1717 printf(" %08x", pci_conf_read(pc, tag, i)); 1718 } 1719 1720 if (memh == 0) { 1721 printf("\n"); 1722 return; 1723 } 1724 1725 printf("\nsocket regs:"); 1726 for (i = 0; i <= 0x10; i += 0x04) { 1727 printf(" %08x", bus_space_read_4(memt, memh, i)); 1728 } 1729 printf("\nExCA regs:"); 1730 for (i = 0; i < 0x08; ++i) { 1731 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1732 } 1733 printf("\n"); 1734 return; 1735 } 1736 #endif 1737 1738 /* 1739 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1740 * int busno, int devno, int function) 1741 * This is the function to make a tag to access config space of 1742 * a CardBus Card. It works same as pci_conf_read. 1743 */ 1744 static cardbustag_t 1745 pccbb_make_tag(cc, busno, devno, function) 1746 cardbus_chipset_tag_t cc; 1747 int busno, devno, function; 1748 { 1749 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1750 1751 return pci_make_tag(sc->sc_pc, busno, devno, function); 1752 } 1753 1754 static void 1755 pccbb_free_tag(cc, tag) 1756 cardbus_chipset_tag_t cc; 1757 cardbustag_t tag; 1758 { 1759 } 1760 1761 /* 1762 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1763 * cardbustag_t tag, int offset) 1764 * This is the function to read the config space of a CardBus Card. 1765 * It works same as pci_conf_read. 1766 */ 1767 static cardbusreg_t 1768 pccbb_conf_read(cc, tag, offset) 1769 cardbus_chipset_tag_t cc; 1770 cardbustag_t tag; 1771 int offset; /* register offset */ 1772 { 1773 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1774 1775 return pci_conf_read(sc->sc_pc, tag, offset); 1776 } 1777 1778 /* 1779 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1780 * int offs, cardbusreg_t val) 1781 * This is the function to write the config space of a CardBus Card. 1782 * It works same as pci_conf_write. 1783 */ 1784 static void 1785 pccbb_conf_write(cc, tag, reg, val) 1786 cardbus_chipset_tag_t cc; 1787 cardbustag_t tag; 1788 int reg; /* register offset */ 1789 cardbusreg_t val; 1790 { 1791 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1792 1793 pci_conf_write(sc->sc_pc, tag, reg, val); 1794 } 1795 1796 #if 0 1797 STATIC int 1798 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1799 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1800 int speed, int flags, 1801 bus_space_handle_t * iohp) 1802 #endif 1803 /* 1804 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1805 * bus_addr_t start, bus_size_t size, 1806 * bus_size_t align, 1807 * struct pcmcia_io_handle *pcihp 1808 * 1809 * This function only allocates I/O region for pccard. This function 1810 * never maps the allocated region to pccard I/O area. 1811 * 1812 * XXX: The interface of this function is not very good, I believe. 1813 */ 1814 STATIC int 1815 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1816 pcmcia_chipset_handle_t pch; 1817 bus_addr_t start; /* start address */ 1818 bus_size_t size; 1819 bus_size_t align; 1820 struct pcmcia_io_handle *pcihp; 1821 { 1822 struct pcic_handle *ph = (struct pcic_handle *)pch; 1823 bus_addr_t ioaddr; 1824 int flags = 0; 1825 bus_space_tag_t iot; 1826 bus_space_handle_t ioh; 1827 #if rbus 1828 rbus_tag_t rb; 1829 #endif 1830 if (align == 0) { 1831 align = size; /* XXX: funny??? */ 1832 } 1833 1834 /* 1835 * Allocate some arbitrary I/O space. 1836 */ 1837 1838 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1839 1840 #if rbus 1841 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1842 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1843 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1844 return 1; 1845 } 1846 #else 1847 if (start) { 1848 ioaddr = start; 1849 if (bus_space_map(iot, start, size, 0, &ioh)) { 1850 return 1; 1851 } 1852 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1853 (u_long) ioaddr, (u_long) size)); 1854 } else { 1855 flags |= PCMCIA_IO_ALLOCATED; 1856 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1857 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1858 size, align, 0, 0, &ioaddr, &ioh)) { 1859 /* No room be able to be get. */ 1860 return 1; 1861 } 1862 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1863 (u_long) ioaddr, (u_long) size)); 1864 } 1865 #endif 1866 1867 pcihp->iot = iot; 1868 pcihp->ioh = ioh; 1869 pcihp->addr = ioaddr; 1870 pcihp->size = size; 1871 pcihp->flags = flags; 1872 1873 return 0; 1874 } 1875 1876 /* 1877 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1878 * struct pcmcia_io_handle *pcihp) 1879 * 1880 * This function only frees I/O region for pccard. 1881 * 1882 * XXX: The interface of this function is not very good, I believe. 1883 */ 1884 void 1885 pccbb_pcmcia_io_free(pch, pcihp) 1886 pcmcia_chipset_handle_t pch; 1887 struct pcmcia_io_handle *pcihp; 1888 { 1889 #if !rbus 1890 bus_space_tag_t iot = pcihp->iot; 1891 #endif 1892 bus_space_handle_t ioh = pcihp->ioh; 1893 bus_size_t size = pcihp->size; 1894 1895 #if rbus 1896 struct pccbb_softc *sc = 1897 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1898 rbus_tag_t rb = sc->sc_rbus_iot; 1899 1900 rbus_space_free(rb, ioh, size, NULL); 1901 #else 1902 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1903 bus_space_free(iot, ioh, size); 1904 else 1905 bus_space_unmap(iot, ioh, size); 1906 #endif 1907 } 1908 1909 /* 1910 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1911 * bus_addr_t offset, bus_size_t size, 1912 * struct pcmcia_io_handle *pcihp, 1913 * int *windowp) 1914 * 1915 * This function maps the allocated I/O region to pccard. This function 1916 * never allocates any I/O region for pccard I/O area. I don't 1917 * understand why the original authors of pcmciabus separated alloc and 1918 * map. I believe the two must be unite. 1919 * 1920 * XXX: no wait timing control? 1921 */ 1922 int 1923 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1924 pcmcia_chipset_handle_t pch; 1925 int width; 1926 bus_addr_t offset; 1927 bus_size_t size; 1928 struct pcmcia_io_handle *pcihp; 1929 int *windowp; 1930 { 1931 struct pcic_handle *ph = (struct pcic_handle *)pch; 1932 bus_addr_t ioaddr = pcihp->addr + offset; 1933 int i, win; 1934 #if defined CBB_DEBUG 1935 static char *width_names[] = { "dynamic", "io8", "io16" }; 1936 #endif 1937 1938 /* Sanity check I/O handle. */ 1939 1940 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1941 panic("pccbb_pcmcia_io_map iot is bogus"); 1942 } 1943 1944 /* XXX Sanity check offset/size. */ 1945 1946 win = -1; 1947 for (i = 0; i < PCIC_IO_WINS; i++) { 1948 if ((ph->ioalloc & (1 << i)) == 0) { 1949 win = i; 1950 ph->ioalloc |= (1 << i); 1951 break; 1952 } 1953 } 1954 1955 if (win == -1) { 1956 return 1; 1957 } 1958 1959 *windowp = win; 1960 1961 /* XXX this is pretty gross */ 1962 1963 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1964 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1965 1966 /* XXX wtf is this doing here? */ 1967 1968 #if 0 1969 printf(" port 0x%lx", (u_long) ioaddr); 1970 if (size > 1) { 1971 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1972 } 1973 #endif 1974 1975 ph->io[win].addr = ioaddr; 1976 ph->io[win].size = size; 1977 ph->io[win].width = width; 1978 1979 /* actual dirty register-value changing in the function below. */ 1980 pccbb_pcmcia_do_io_map(ph, win); 1981 1982 return 0; 1983 } 1984 1985 /* 1986 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1987 * 1988 * This function changes register-value to map I/O region for pccard. 1989 */ 1990 static void 1991 pccbb_pcmcia_do_io_map(ph, win) 1992 struct pcic_handle *ph; 1993 int win; 1994 { 1995 static u_int8_t pcic_iowidth[3] = { 1996 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1997 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1998 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1999 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2000 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2001 }; 2002 2003 #define PCIC_SIA_START_LOW 0 2004 #define PCIC_SIA_START_HIGH 1 2005 #define PCIC_SIA_STOP_LOW 2 2006 #define PCIC_SIA_STOP_HIGH 3 2007 2008 int regbase_win = 0x8 + win * 0x04; 2009 u_int8_t ioctl, enable; 2010 2011 DPRINTF( 2012 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2013 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2014 ph->io[win].width * 8)); 2015 2016 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2017 ph->io[win].addr & 0xff); 2018 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2019 (ph->io[win].addr >> 8) & 0xff); 2020 2021 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2022 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2023 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2024 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2025 2026 ioctl = Pcic_read(ph, PCIC_IOCTL); 2027 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2028 switch (win) { 2029 case 0: 2030 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2031 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2032 PCIC_IOCTL_IO0_DATASIZE_MASK); 2033 ioctl |= pcic_iowidth[ph->io[win].width]; 2034 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2035 break; 2036 case 1: 2037 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2038 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2039 PCIC_IOCTL_IO1_DATASIZE_MASK); 2040 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2041 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2042 break; 2043 } 2044 Pcic_write(ph, PCIC_IOCTL, ioctl); 2045 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2046 #if defined CBB_DEBUG 2047 { 2048 u_int8_t start_low = 2049 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2050 u_int8_t start_high = 2051 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2052 u_int8_t stop_low = 2053 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2054 u_int8_t stop_high = 2055 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2056 printf 2057 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2058 start_low, start_high, stop_low, stop_high, ioctl, enable); 2059 } 2060 #endif 2061 } 2062 2063 /* 2064 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2065 * 2066 * This function unmaps I/O region. No return value. 2067 */ 2068 STATIC void 2069 pccbb_pcmcia_io_unmap(pch, win) 2070 pcmcia_chipset_handle_t pch; 2071 int win; 2072 { 2073 struct pcic_handle *ph = (struct pcic_handle *)pch; 2074 int reg; 2075 2076 if (win >= PCIC_IO_WINS || win < 0) { 2077 panic("pccbb_pcmcia_io_unmap: window out of range"); 2078 } 2079 2080 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2081 switch (win) { 2082 case 0: 2083 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2084 break; 2085 case 1: 2086 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2087 break; 2088 } 2089 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2090 2091 ph->ioalloc &= ~(1 << win); 2092 } 2093 2094 /* 2095 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2096 * 2097 * This function enables the card. All information is stored in 2098 * the first argument, pcmcia_chipset_handle_t. 2099 */ 2100 static void 2101 pccbb_pcmcia_wait_ready(ph) 2102 struct pcic_handle *ph; 2103 { 2104 int i; 2105 2106 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2107 Pcic_read(ph, PCIC_IF_STATUS))); 2108 2109 for (i = 0; i < 10000; i++) { 2110 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2111 return; 2112 } 2113 delay(500); 2114 #ifdef CBB_DEBUG 2115 if ((i > 5000) && (i % 100 == 99)) 2116 printf("."); 2117 #endif 2118 } 2119 2120 #ifdef DIAGNOSTIC 2121 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2122 Pcic_read(ph, PCIC_IF_STATUS)); 2123 #endif 2124 } 2125 2126 /* 2127 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2128 * 2129 * This function enables the card. All information is stored in 2130 * the first argument, pcmcia_chipset_handle_t. 2131 */ 2132 STATIC void 2133 pccbb_pcmcia_socket_enable(pch) 2134 pcmcia_chipset_handle_t pch; 2135 { 2136 struct pcic_handle *ph = (struct pcic_handle *)pch; 2137 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2138 int cardtype, win; 2139 u_int8_t power, intr; 2140 pcireg_t spsr; 2141 int voltage; 2142 2143 /* this bit is mostly stolen from pcic_attach_card */ 2144 2145 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2146 2147 /* get card Vcc info */ 2148 2149 spsr = 2150 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2151 CB_SOCKET_STAT); 2152 if (spsr & CB_SOCKET_STAT_5VCARD) { 2153 DPRINTF(("5V card\n")); 2154 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2155 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2156 DPRINTF(("3V card\n")); 2157 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2158 } else { 2159 printf("?V card, 0x%x\n", spsr); /* XXX */ 2160 return; 2161 } 2162 2163 /* assert reset bit */ 2164 intr = Pcic_read(ph, PCIC_INTR); 2165 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2166 Pcic_write(ph, PCIC_INTR, intr); 2167 2168 /* disable socket i/o: negate output enable bit */ 2169 2170 power = Pcic_read(ph, PCIC_PWRCTL); 2171 power &= ~PCIC_PWRCTL_OE; 2172 Pcic_write(ph, PCIC_PWRCTL, power); 2173 2174 /* power down the socket to reset it, clear the card reset pin */ 2175 2176 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2177 2178 /* 2179 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2180 * we are changing Vcc (Toff). 2181 */ 2182 /* delay(300*1000); too much */ 2183 2184 /* power up the socket */ 2185 pccbb_power(sc, voltage); 2186 2187 /* 2188 * wait 100ms until power raise (Tpr) and 20ms to become 2189 * stable (Tsu(Vcc)). 2190 * 2191 * some machines require some more time to be settled 2192 * (another 200ms is added here). 2193 */ 2194 /* delay((100 + 20 + 200)*1000); too much */ 2195 2196 power = Pcic_read(ph, PCIC_PWRCTL); 2197 power |= PCIC_PWRCTL_OE; 2198 Pcic_write(ph, PCIC_PWRCTL, power); 2199 2200 /* 2201 * hold RESET at least 10us. 2202 */ 2203 delay(10); 2204 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2205 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2206 2207 /* clear the reset flag */ 2208 2209 intr |= PCIC_INTR_RESET; 2210 Pcic_write(ph, PCIC_INTR, intr); 2211 2212 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2213 2214 delay(20000); 2215 2216 /* wait for the chip to finish initializing */ 2217 2218 pccbb_pcmcia_wait_ready(ph); 2219 2220 /* zero out the address windows */ 2221 2222 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2223 2224 /* set the card type */ 2225 2226 cardtype = pcmcia_card_gettype(ph->pcmcia); 2227 2228 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2229 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2230 Pcic_write(ph, PCIC_INTR, intr); 2231 2232 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2233 ph->ph_parent->dv_xname, ph->sock, 2234 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2235 2236 /* reinstall all the memory and io mappings */ 2237 2238 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2239 if (ph->memalloc & (1 << win)) { 2240 pccbb_pcmcia_do_mem_map(ph, win); 2241 } 2242 } 2243 2244 for (win = 0; win < PCIC_IO_WINS; ++win) { 2245 if (ph->ioalloc & (1 << win)) { 2246 pccbb_pcmcia_do_io_map(ph, win); 2247 } 2248 } 2249 } 2250 2251 /* 2252 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2253 * 2254 * This function disables the card. All information is stored in 2255 * the first argument, pcmcia_chipset_handle_t. 2256 */ 2257 STATIC void 2258 pccbb_pcmcia_socket_disable(pch) 2259 pcmcia_chipset_handle_t pch; 2260 { 2261 struct pcic_handle *ph = (struct pcic_handle *)pch; 2262 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2263 u_int8_t power, intr; 2264 2265 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2266 2267 /* reset signal asserting... */ 2268 2269 intr = Pcic_read(ph, PCIC_INTR); 2270 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2271 Pcic_write(ph, PCIC_INTR, intr); 2272 delay(2 * 1000); 2273 2274 /* power down the socket */ 2275 power = Pcic_read(ph, PCIC_PWRCTL); 2276 power &= ~PCIC_PWRCTL_OE; 2277 Pcic_write(ph, PCIC_PWRCTL, power); 2278 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2279 /* 2280 * wait 300ms until power fails (Tpf). 2281 */ 2282 delay(300 * 1000); 2283 } 2284 2285 /* 2286 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2287 * 2288 * This function detects whether a card is in the slot or not. 2289 * If a card is inserted, return 1. Otherwise, return 0. 2290 */ 2291 STATIC int 2292 pccbb_pcmcia_card_detect(pch) 2293 pcmcia_chipset_handle_t pch; 2294 { 2295 struct pcic_handle *ph = (struct pcic_handle *)pch; 2296 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2297 2298 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2299 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2300 } 2301 2302 #if 0 2303 STATIC int 2304 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2305 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2306 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2307 #endif 2308 /* 2309 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2310 * bus_size_t size, 2311 * struct pcmcia_mem_handle *pcmhp) 2312 * 2313 * This function only allocates memory region for pccard. This 2314 * function never maps the allocated region to pccard memory area. 2315 * 2316 * XXX: Why the argument of start address is not in? 2317 */ 2318 STATIC int 2319 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2320 pcmcia_chipset_handle_t pch; 2321 bus_size_t size; 2322 struct pcmcia_mem_handle *pcmhp; 2323 { 2324 struct pcic_handle *ph = (struct pcic_handle *)pch; 2325 bus_space_handle_t memh; 2326 bus_addr_t addr; 2327 bus_size_t sizepg; 2328 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2329 #if rbus 2330 rbus_tag_t rb; 2331 #endif 2332 2333 /* out of sc->memh, allocate as many pages as necessary */ 2334 2335 /* convert size to PCIC pages */ 2336 /* 2337 * This is not enough; when the requested region is on the page 2338 * boundaries, this may calculate wrong result. 2339 */ 2340 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2341 #if 0 2342 if (sizepg > PCIC_MAX_MEM_PAGES) { 2343 return 1; 2344 } 2345 #endif 2346 2347 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2348 return 1; 2349 } 2350 2351 addr = 0; /* XXX gcc -Wuninitialized */ 2352 2353 #if rbus 2354 rb = sc->sc_rbus_memt; 2355 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2356 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2357 &addr, &memh)) { 2358 return 1; 2359 } 2360 #else 2361 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2362 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2363 0, /* boundary */ 2364 0, /* flags */ 2365 &addr, &memh)) { 2366 return 1; 2367 } 2368 #endif 2369 2370 DPRINTF( 2371 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2372 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2373 2374 pcmhp->memt = sc->sc_memt; 2375 pcmhp->memh = memh; 2376 pcmhp->addr = addr; 2377 pcmhp->size = size; 2378 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2379 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2380 pcmhp->mhandle = 0; 2381 /* No offset??? Funny. */ 2382 2383 return 0; 2384 } 2385 2386 /* 2387 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2388 * struct pcmcia_mem_handle *pcmhp) 2389 * 2390 * This function release the memory space allocated by the function 2391 * pccbb_pcmcia_mem_alloc(). 2392 */ 2393 STATIC void 2394 pccbb_pcmcia_mem_free(pch, pcmhp) 2395 pcmcia_chipset_handle_t pch; 2396 struct pcmcia_mem_handle *pcmhp; 2397 { 2398 #if rbus 2399 struct pcic_handle *ph = (struct pcic_handle *)pch; 2400 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2401 2402 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2403 #else 2404 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2405 #endif 2406 } 2407 2408 /* 2409 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2410 * 2411 * This function release the memory space allocated by the function 2412 * pccbb_pcmcia_mem_alloc(). 2413 */ 2414 STATIC void 2415 pccbb_pcmcia_do_mem_map(ph, win) 2416 struct pcic_handle *ph; 2417 int win; 2418 { 2419 int regbase_win; 2420 bus_addr_t phys_addr; 2421 bus_addr_t phys_end; 2422 2423 #define PCIC_SMM_START_LOW 0 2424 #define PCIC_SMM_START_HIGH 1 2425 #define PCIC_SMM_STOP_LOW 2 2426 #define PCIC_SMM_STOP_HIGH 3 2427 #define PCIC_CMA_LOW 4 2428 #define PCIC_CMA_HIGH 5 2429 2430 u_int8_t start_low, start_high = 0; 2431 u_int8_t stop_low, stop_high; 2432 u_int8_t off_low, off_high; 2433 u_int8_t mem_window; 2434 int reg; 2435 2436 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2437 int mem8 = 2438 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2439 || (kind == PCMCIA_MEM_ATTR); 2440 2441 regbase_win = 0x10 + win * 0x08; 2442 2443 phys_addr = ph->mem[win].addr; 2444 phys_end = phys_addr + ph->mem[win].size; 2445 2446 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2447 phys_addr, phys_end, ph->mem[win].offset)); 2448 2449 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2450 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2451 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2452 2453 /* bit 19:12 */ 2454 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2455 /* bit 23:20 and bit 7 on */ 2456 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2457 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2458 /* bit 31:24, for 32-bit address */ 2459 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2460 2461 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2462 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2463 2464 if (((struct pccbb_softc *)ph-> 2465 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2466 Pcic_write(ph, 0x40 + win, mem_window); 2467 } 2468 2469 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2470 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2471 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2472 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2473 2474 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2475 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2476 2477 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2478 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2479 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2480 | ((kind == PCMCIA_MEM_ATTR) ? 2481 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2482 2483 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2484 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2485 2486 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2487 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2488 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2489 2490 #if defined CBB_DEBUG 2491 { 2492 int r1, r2, r3, r4, r5, r6, r7 = 0; 2493 2494 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2495 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2496 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2497 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2498 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2499 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2500 if (((struct pccbb_softc *)(ph-> 2501 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2502 r7 = Pcic_read(ph, 0x40 + win); 2503 } 2504 2505 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2506 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2507 if (((struct pccbb_softc *)(ph-> 2508 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2509 DPRINTF((" %02x", r7)); 2510 } 2511 DPRINTF(("\n")); 2512 } 2513 #endif 2514 } 2515 2516 /* 2517 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2518 * bus_addr_t card_addr, bus_size_t size, 2519 * struct pcmcia_mem_handle *pcmhp, 2520 * bus_addr_t *offsetp, int *windowp) 2521 * 2522 * This function maps memory space allocated by the function 2523 * pccbb_pcmcia_mem_alloc(). 2524 */ 2525 STATIC int 2526 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2527 pcmcia_chipset_handle_t pch; 2528 int kind; 2529 bus_addr_t card_addr; 2530 bus_size_t size; 2531 struct pcmcia_mem_handle *pcmhp; 2532 bus_addr_t *offsetp; 2533 int *windowp; 2534 { 2535 struct pcic_handle *ph = (struct pcic_handle *)pch; 2536 bus_addr_t busaddr; 2537 long card_offset; 2538 int win; 2539 2540 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2541 if ((ph->memalloc & (1 << win)) == 0) { 2542 ph->memalloc |= (1 << win); 2543 break; 2544 } 2545 } 2546 2547 if (win == PCIC_MEM_WINS) { 2548 return 1; 2549 } 2550 2551 *windowp = win; 2552 2553 /* XXX this is pretty gross */ 2554 2555 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2556 panic("pccbb_pcmcia_mem_map memt is bogus"); 2557 } 2558 2559 busaddr = pcmhp->addr; 2560 2561 /* 2562 * compute the address offset to the pcmcia address space for the 2563 * pcic. this is intentionally signed. The masks and shifts below 2564 * will cause TRT to happen in the pcic registers. Deal with making 2565 * sure the address is aligned, and return the alignment offset. 2566 */ 2567 2568 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2569 card_addr -= *offsetp; 2570 2571 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2572 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2573 (u_long) card_addr)); 2574 2575 /* 2576 * include the offset in the size, and decrement size by one, since 2577 * the hw wants start/stop 2578 */ 2579 size += *offsetp - 1; 2580 2581 card_offset = (((long)card_addr) - ((long)busaddr)); 2582 2583 ph->mem[win].addr = busaddr; 2584 ph->mem[win].size = size; 2585 ph->mem[win].offset = card_offset; 2586 ph->mem[win].kind = kind; 2587 2588 pccbb_pcmcia_do_mem_map(ph, win); 2589 2590 return 0; 2591 } 2592 2593 /* 2594 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2595 * int window) 2596 * 2597 * This function unmaps memory space which mapped by the function 2598 * pccbb_pcmcia_mem_map(). 2599 */ 2600 STATIC void 2601 pccbb_pcmcia_mem_unmap(pch, window) 2602 pcmcia_chipset_handle_t pch; 2603 int window; 2604 { 2605 struct pcic_handle *ph = (struct pcic_handle *)pch; 2606 int reg; 2607 2608 if (window >= PCIC_MEM_WINS) { 2609 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2610 } 2611 2612 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2613 reg &= ~(1 << window); 2614 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2615 2616 ph->memalloc &= ~(1 << window); 2617 } 2618 2619 #if defined PCCBB_PCMCIA_POLL 2620 struct pccbb_poll_str { 2621 void *arg; 2622 int (*func) __P((void *)); 2623 int level; 2624 struct pcic_handle *ph; 2625 int count; 2626 int num; 2627 }; 2628 2629 static struct pccbb_poll_str pccbb_poll[10]; 2630 static int pccbb_poll_n = 0; 2631 2632 static void pccbb_pcmcia_poll __P((void *arg)); 2633 2634 static void 2635 pccbb_pcmcia_poll(arg) 2636 void *arg; 2637 { 2638 struct pccbb_poll_str *poll = arg; 2639 struct pcic_handle *ph = poll->ph; 2640 struct pccbb_softc *sc = ph->sc; 2641 int s; 2642 u_int32_t spsr; /* socket present-state reg */ 2643 2644 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2645 switch (poll->level) { 2646 case IPL_NET: 2647 s = splnet(); 2648 break; 2649 case IPL_BIO: 2650 s = splbio(); 2651 break; 2652 case IPL_TTY: /* fallthrough */ 2653 default: 2654 s = spltty(); 2655 break; 2656 } 2657 2658 spsr = 2659 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2660 CB_SOCKET_STAT); 2661 2662 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2663 if (!(spsr & 0x40)) /* CINT low */ 2664 #else 2665 if (1) 2666 #endif 2667 { 2668 if ((*poll->func) (poll->arg) > 0) { 2669 ++poll->count; 2670 // printf("intr: reported from poller, 0x%x\n", spsr); 2671 #if defined LEVEL2 2672 } else { 2673 printf("intr: miss! 0x%x\n", spsr); 2674 #endif 2675 } 2676 } 2677 splx(s); 2678 } 2679 #endif /* defined CB_PCMCIA_POLL */ 2680 2681 /* 2682 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2683 * struct pcmcia_function *pf, 2684 * int ipl, 2685 * int (*func)(void *), 2686 * void *arg); 2687 * 2688 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2689 */ 2690 STATIC void * 2691 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2692 pcmcia_chipset_handle_t pch; 2693 struct pcmcia_function *pf; 2694 int ipl; 2695 int (*func) __P((void *)); 2696 void *arg; 2697 { 2698 struct pcic_handle *ph = (struct pcic_handle *)pch; 2699 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2700 2701 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2702 /* what should I do? */ 2703 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2704 DPRINTF( 2705 ("%s does not provide edge nor pulse interrupt\n", 2706 sc->sc_dev.dv_xname)); 2707 return NULL; 2708 } 2709 /* 2710 * XXX Noooooo! The interrupt flag must set properly!! 2711 * dumb pcmcia driver!! 2712 */ 2713 } 2714 2715 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2716 } 2717 2718 /* 2719 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2720 * void *ih) 2721 * 2722 * This function disables PC-Card interrupt. 2723 */ 2724 STATIC void 2725 pccbb_pcmcia_intr_disestablish(pch, ih) 2726 pcmcia_chipset_handle_t pch; 2727 void *ih; 2728 { 2729 struct pcic_handle *ph = (struct pcic_handle *)pch; 2730 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2731 2732 pccbb_intr_disestablish(sc, ih); 2733 } 2734 2735 #if rbus 2736 /* 2737 * static int 2738 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2739 * bus_addr_t addr, bus_size_t size, 2740 * bus_addr_t mask, bus_size_t align, 2741 * int flags, bus_addr_t *addrp; 2742 * bus_space_handle_t *bshp) 2743 * 2744 * This function allocates a portion of memory or io space for 2745 * clients. This function is called from CardBus card drivers. 2746 */ 2747 static int 2748 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2749 cardbus_chipset_tag_t ct; 2750 rbus_tag_t rb; 2751 bus_addr_t addr; 2752 bus_size_t size; 2753 bus_addr_t mask; 2754 bus_size_t align; 2755 int flags; 2756 bus_addr_t *addrp; 2757 bus_space_handle_t *bshp; 2758 { 2759 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2760 2761 DPRINTF( 2762 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2763 addr, size, mask, align)); 2764 2765 if (align == 0) { 2766 align = size; 2767 } 2768 2769 if (rb->rb_bt == sc->sc_memt) { 2770 if (align < 16) { 2771 return 1; 2772 } 2773 } else if (rb->rb_bt == sc->sc_iot) { 2774 if (align < 4) { 2775 return 1; 2776 } 2777 } else { 2778 DPRINTF( 2779 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2780 rb->rb_bt)); 2781 return 1; 2782 /* XXX: panic here? */ 2783 } 2784 2785 /* XXX: hack for avoiding ISA image */ 2786 if (mask < 0x3ff) { 2787 mask = 0x3ff; 2788 addr = 0x300; 2789 } 2790 2791 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2792 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2793 return 1; 2794 } 2795 2796 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2797 2798 return 0; 2799 } 2800 2801 /* 2802 * static int 2803 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2804 * bus_space_handle_t *bshp, bus_size_t size); 2805 * 2806 * This function is called from CardBus card drivers. 2807 */ 2808 static int 2809 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2810 cardbus_chipset_tag_t ct; 2811 rbus_tag_t rb; 2812 bus_space_handle_t bsh; 2813 bus_size_t size; 2814 { 2815 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2816 bus_space_tag_t bt = rb->rb_bt; 2817 2818 pccbb_close_win(sc, bt, bsh, size); 2819 2820 if (bt == sc->sc_memt) { 2821 } else if (bt == sc->sc_iot) { 2822 } else { 2823 return 1; 2824 /* XXX: panic here? */ 2825 } 2826 2827 return rbus_space_free(rb, bsh, size, NULL); 2828 } 2829 #endif /* rbus */ 2830 2831 #if rbus 2832 2833 static int 2834 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2835 struct pccbb_softc *sc; 2836 bus_space_tag_t bst; 2837 bus_addr_t addr; 2838 bus_size_t size; 2839 bus_space_handle_t bsh; 2840 int flags; 2841 { 2842 struct pccbb_win_chain_head *head; 2843 bus_addr_t align; 2844 2845 head = &sc->sc_iowindow; 2846 align = 0x04; 2847 if (sc->sc_memt == bst) { 2848 head = &sc->sc_memwindow; 2849 align = 0x1000; 2850 DPRINTF(("using memory window, %x %x %x\n\n", 2851 sc->sc_iot, sc->sc_memt, bst)); 2852 } 2853 2854 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2855 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2856 sc->sc_dev.dv_xname, 2857 (head == &sc->sc_memwindow) ? "mem" : "io"); 2858 } 2859 pccbb_winset(align, sc, bst); 2860 2861 return 0; 2862 } 2863 2864 static int 2865 pccbb_close_win(sc, bst, bsh, size) 2866 struct pccbb_softc *sc; 2867 bus_space_tag_t bst; 2868 bus_space_handle_t bsh; 2869 bus_size_t size; 2870 { 2871 struct pccbb_win_chain_head *head; 2872 bus_addr_t align; 2873 2874 head = &sc->sc_iowindow; 2875 align = 0x04; 2876 if (sc->sc_memt == bst) { 2877 head = &sc->sc_memwindow; 2878 align = 0x1000; 2879 } 2880 2881 if (pccbb_winlist_delete(head, bsh, size)) { 2882 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2883 sc->sc_dev.dv_xname, 2884 (head == &sc->sc_memwindow) ? "mem" : "io"); 2885 } 2886 pccbb_winset(align, sc, bst); 2887 2888 return 0; 2889 } 2890 2891 static int 2892 pccbb_winlist_insert(head, start, size, bsh, flags) 2893 struct pccbb_win_chain_head *head; 2894 bus_addr_t start; 2895 bus_size_t size; 2896 bus_space_handle_t bsh; 2897 int flags; 2898 { 2899 struct pccbb_win_chain *chainp, *elem; 2900 2901 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2902 M_NOWAIT)) == NULL) 2903 return 1; /* fail */ 2904 2905 elem->wc_start = start; 2906 elem->wc_end = start + (size - 1); 2907 elem->wc_handle = bsh; 2908 elem->wc_flags = flags; 2909 2910 if ((chainp = TAILQ_FIRST(head)) == NULL) { 2911 TAILQ_INSERT_HEAD(head, elem, wc_list); 2912 return 0; 2913 } 2914 2915 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2916 if (chainp->wc_end < start) 2917 continue; 2918 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2919 return 0; 2920 } 2921 2922 TAILQ_INSERT_TAIL(head, elem, wc_list); 2923 2924 return 0; 2925 } 2926 2927 static int 2928 pccbb_winlist_delete(head, bsh, size) 2929 struct pccbb_win_chain_head *head; 2930 bus_space_handle_t bsh; 2931 bus_size_t size; 2932 { 2933 struct pccbb_win_chain *chainp; 2934 2935 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2936 chainp = TAILQ_NEXT(chainp, wc_list)) { 2937 if (chainp->wc_handle != bsh) 2938 continue; 2939 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2940 printf("pccbb_winlist_delete: window 0x%lx size " 2941 "inconsistent: 0x%lx, 0x%lx\n", 2942 chainp->wc_start, 2943 chainp->wc_end - chainp->wc_start, 2944 size - 1); 2945 return 1; 2946 } 2947 2948 TAILQ_REMOVE(head, chainp, wc_list); 2949 free(chainp, M_DEVBUF); 2950 2951 return 0; 2952 } 2953 2954 return 1; /* fail: no candidate to remove */ 2955 } 2956 2957 static void 2958 pccbb_winset(align, sc, bst) 2959 bus_addr_t align; 2960 struct pccbb_softc *sc; 2961 bus_space_tag_t bst; 2962 { 2963 pci_chipset_tag_t pc; 2964 pcitag_t tag; 2965 bus_addr_t mask = ~(align - 1); 2966 struct { 2967 cardbusreg_t win_start; 2968 cardbusreg_t win_limit; 2969 int win_flags; 2970 } win[2]; 2971 struct pccbb_win_chain *chainp; 2972 int offs; 2973 2974 win[0].win_start = 0xffffffff; 2975 win[0].win_limit = 0; 2976 win[1].win_start = 0xffffffff; 2977 win[1].win_limit = 0; 2978 2979 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2980 offs = 0x2c; 2981 if (sc->sc_memt == bst) { 2982 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2983 offs = 0x1c; 2984 } 2985 2986 if (chainp != NULL) { 2987 win[0].win_start = chainp->wc_start & mask; 2988 win[0].win_limit = chainp->wc_end & mask; 2989 win[0].win_flags = chainp->wc_flags; 2990 chainp = TAILQ_NEXT(chainp, wc_list); 2991 } 2992 2993 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2994 if (win[1].win_start == 0xffffffff) { 2995 /* window 1 is not used */ 2996 if ((win[0].win_flags == chainp->wc_flags) && 2997 (win[0].win_limit + align >= 2998 (chainp->wc_start & mask))) { 2999 /* concatenate */ 3000 win[0].win_limit = chainp->wc_end & mask; 3001 } else { 3002 /* make new window */ 3003 win[1].win_start = chainp->wc_start & mask; 3004 win[1].win_limit = chainp->wc_end & mask; 3005 win[1].win_flags = chainp->wc_flags; 3006 } 3007 continue; 3008 } 3009 3010 /* Both windows are engaged. */ 3011 if (win[0].win_flags == win[1].win_flags) { 3012 /* same flags */ 3013 if (win[0].win_flags == chainp->wc_flags) { 3014 if (win[1].win_start - (win[0].win_limit + 3015 align) < 3016 (chainp->wc_start & mask) - 3017 ((chainp->wc_end & mask) + align)) { 3018 /* 3019 * merge window 0 and 1, and set win1 3020 * to chainp 3021 */ 3022 win[0].win_limit = win[1].win_limit; 3023 win[1].win_start = 3024 chainp->wc_start & mask; 3025 win[1].win_limit = 3026 chainp->wc_end & mask; 3027 } else { 3028 win[1].win_limit = 3029 chainp->wc_end & mask; 3030 } 3031 } else { 3032 /* different flags */ 3033 3034 /* concatenate win0 and win1 */ 3035 win[0].win_limit = win[1].win_limit; 3036 /* allocate win[1] to new space */ 3037 win[1].win_start = chainp->wc_start & mask; 3038 win[1].win_limit = chainp->wc_end & mask; 3039 win[1].win_flags = chainp->wc_flags; 3040 } 3041 } else { 3042 /* the flags of win[0] and win[1] is different */ 3043 if (win[0].win_flags == chainp->wc_flags) { 3044 win[0].win_limit = chainp->wc_end & mask; 3045 /* 3046 * XXX this creates overlapping windows, so 3047 * what should the poor bridge do if one is 3048 * cachable, and the other is not? 3049 */ 3050 printf("%s: overlapping windows\n", 3051 sc->sc_dev.dv_xname); 3052 } else { 3053 win[1].win_limit = chainp->wc_end & mask; 3054 } 3055 } 3056 } 3057 3058 pc = sc->sc_pc; 3059 tag = sc->sc_tag; 3060 pci_conf_write(pc, tag, offs, win[0].win_start); 3061 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3062 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3063 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3064 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3065 pci_conf_read(pc, tag, offs), 3066 pci_conf_read(pc, tag, offs + 4) + align, 3067 pci_conf_read(pc, tag, offs + 8), 3068 pci_conf_read(pc, tag, offs + 12) + align)); 3069 3070 if (bst == sc->sc_memt) { 3071 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3072 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3073 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3074 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3075 } 3076 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3077 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3078 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3079 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3080 } 3081 } 3082 } 3083 3084 #endif /* rbus */ 3085 3086 static void 3087 pccbb_powerhook(why, arg) 3088 int why; 3089 void *arg; 3090 { 3091 struct pccbb_softc *sc = arg; 3092 u_int32_t reg; 3093 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3094 bus_space_handle_t base_memh = sc->sc_base_memh; 3095 3096 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3097 3098 if (why == PWR_RESUME) { 3099 /* CSC Interrupt: Card detect interrupt on */ 3100 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3101 /* Card detect intr is turned on. */ 3102 reg |= CB_SOCKET_MASK_CD; 3103 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3104 /* reset interrupt */ 3105 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3106 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3107 3108 /* 3109 * check for card insertion or removal during suspend period. 3110 * XXX: the code can't cope with card swap (remove then insert). 3111 * how can we detect such situation? 3112 */ 3113 if (why == PWR_RESUME) 3114 (void)pccbbintr(sc); 3115 } 3116 } 3117
Indexes created Fri Sep 26 08:10:20 GMT 2025