pccbb.c revision 1.34
1 /* $NetBSD: pccbb.c,v 1.34 2000/03/14 10:23:16 enami Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 int loopend = sizeof(yc_chipsets) / sizeof(yc_chipsets[0]); 355 struct yenta_chipinfo *ycp, *ycend; 356 357 ycend = yc_chipsets + loopend; 358 359 for (ycp = yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 360 361 if (ycp == ycend) { 362 /* not found -- point at sentinel */ 363 ycp = yc_chipsets + loopend - 1; 364 } 365 366 if (flagp != NULL) { 367 *flagp = ycp->yc_flags; 368 } 369 370 return ycp->yc_chiptype; 371 } 372 373 static void 374 pccbb_shutdown(void *arg) 375 { 376 struct pccbb_softc *sc = arg; 377 pcireg_t command; 378 379 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 380 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 381 0); 382 383 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 384 385 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 386 PCI_COMMAND_MASTER_ENABLE); 387 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 388 389 } 390 391 void 392 pccbbattach(parent, self, aux) 393 struct device *parent; 394 struct device *self; 395 void *aux; 396 { 397 struct pccbb_softc *sc = (void *)self; 398 struct pci_attach_args *pa = aux; 399 pci_chipset_tag_t pc = pa->pa_pc; 400 pcireg_t sock_base, busreg; 401 bus_addr_t sockbase; 402 char devinfo[256]; 403 int flags; 404 405 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 406 407 pci_devinfo(pa->pa_id, 0, 0, devinfo); 408 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 409 #ifdef CBB_DEBUG 410 printf(" (chipflags %x)", flags); 411 #endif 412 printf("\n"); 413 414 TAILQ_INIT(&sc->sc_memwindow); 415 TAILQ_INIT(&sc->sc_iowindow); 416 417 #if rbus 418 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 419 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 420 #endif /* rbus */ 421 422 sc->sc_base_memh = 0; 423 424 /* 425 * MAP socket registers and ExCA registers on memory-space 426 * When no valid address is set on socket base registers (on pci 427 * config space), get it not polite way. 428 */ 429 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 430 431 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 432 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 433 /* The address must be valid. */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 435 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 436 printf("%s: can't map socket base address 0x%x\n", 437 sc->sc_dev.dv_xname, sock_base); 438 /* 439 * I think it's funny: socket base registers must be 440 * mapped on memory space, but ... 441 */ 442 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 443 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 444 NULL)) { 445 printf("%s: can't map socket base address" 446 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 447 sockbase); 448 /* give up... allocate reg space via rbus. */ 449 sc->sc_base_memh = 0; 450 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 451 } 452 } else { 453 DPRINTF(("%s: socket base address 0x%lx\n", 454 sc->sc_dev.dv_xname, sockbase)); 455 } 456 } 457 458 sc->sc_mem_start = 0; /* XXX */ 459 sc->sc_mem_end = 0xffffffff; /* XXX */ 460 461 /* 462 * When interrupt isn't routed correctly, give up probing cbb and do 463 * not kill pcic-compatible port. 464 */ 465 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 466 printf("%s: NOT USED because of unconfigured interrupt\n", 467 sc->sc_dev.dv_xname); 468 return; 469 } 470 471 /* 472 * When bus number isn't set correctly, give up using 32-bit CardBus 473 * mode. 474 */ 475 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 476 #if notyet 477 if (((busreg >> 8) & 0xff) == 0) { 478 printf("%s: CardBus support disabled because of unconfigured bus number\n", 479 sc->sc_dev.dv_xname); 480 flags |= PCCBB_PCMCIA_16BITONLY; 481 } 482 #endif 483 484 /* pccbb_machdep.c end */ 485 486 #if defined CBB_DEBUG 487 { 488 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 489 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 490 intrname[pa->pa_intrpin], pa->pa_intrline); 491 } 492 #endif 493 494 /* setup softc */ 495 sc->sc_pc = pc; 496 sc->sc_iot = pa->pa_iot; 497 sc->sc_memt = pa->pa_memt; 498 sc->sc_dmat = pa->pa_dmat; 499 sc->sc_tag = pa->pa_tag; 500 sc->sc_function = pa->pa_function; 501 502 sc->sc_intrline = pa->pa_intrline; 503 sc->sc_intrtag = pa->pa_intrtag; 504 sc->sc_intrpin = pa->pa_intrpin; 505 506 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 507 508 shutdownhook_establish(pccbb_shutdown, sc); 509 510 #if __NetBSD_Version__ > 103060000 511 config_defer(self, pccbb_pci_callback); 512 #else 513 pccbb_pci_callback(self); 514 #endif 515 } 516 517 518 519 520 /* 521 * static void pccbb_pci_callback(struct device *self) 522 * 523 * The actual attach routine: get memory space for YENTA register 524 * space, setup YENTA register and route interrupt. 525 * 526 * This function should be deferred because this device may obtain 527 * memory space dynamically. This function must avoid obtaining 528 * memory area which has already kept for another device. Also, 529 * this function MUST be done before ISA attach process because this 530 * function kills pcic compatible port used by ISA pcic. 531 */ 532 static void 533 pccbb_pci_callback(self) 534 struct device *self; 535 { 536 struct pccbb_softc *sc = (void *)self; 537 pci_chipset_tag_t pc = sc->sc_pc; 538 bus_space_tag_t base_memt; 539 bus_space_handle_t base_memh; 540 u_int32_t maskreg; 541 pci_intr_handle_t ih; 542 const char *intrstr = NULL; 543 bus_addr_t sockbase; 544 struct cbslot_attach_args cba; 545 struct pcmciabus_attach_args paa; 546 struct cardslot_attach_args caa; 547 struct cardslot_softc *csc; 548 549 if (0 == sc->sc_base_memh) { 550 /* The socket registers aren't mapped correctly. */ 551 #if rbus 552 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 553 (sc->sc_chipset == CB_RX5C47X 554 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 555 0, &sockbase, &sc->sc_base_memh)) { 556 return; 557 } 558 sc->sc_base_memt = sc->sc_memt; 559 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 560 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 561 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 562 PCI_SOCKBASE))); 563 #else 564 sc->sc_base_memt = sc->sc_memt; 565 #if !defined CBB_PCI_BASE 566 #define CBB_PCI_BASE 0x20000000 567 #endif 568 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 569 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 570 /* cannot allocate memory space */ 571 return; 572 } 573 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 574 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 575 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 576 sc->sc_tag, PCI_SOCKBASE))); 577 #endif 578 } 579 580 /* bus bridge initialization */ 581 pccbb_chipinit(sc); 582 583 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 584 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 585 586 /* CSC Interrupt: Card detect interrupt on */ 587 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 588 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 589 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 590 /* reset interrupt */ 591 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 592 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 593 594 /* Map and establish the interrupt. */ 595 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 596 sc->sc_intrline, &ih)) { 597 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 598 return; 599 } 600 intrstr = pci_intr_string(pc, ih); 601 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 602 603 if (sc->sc_ih == NULL) { 604 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 605 if (intrstr != NULL) { 606 printf(" at %s", intrstr); 607 } 608 printf("\n"); 609 return; 610 } 611 612 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 613 powerhook_establish(pccbb_powerhook, sc); 614 615 { 616 u_int32_t sockstat = 617 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 618 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 619 sc->sc_flags |= CBB_CARDEXIST; 620 } 621 } 622 623 /* 624 * attach cardbus 625 */ 626 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 627 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 628 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 629 630 /* initialize cbslot_attach */ 631 cba.cba_busname = "cardbus"; 632 cba.cba_iot = sc->sc_iot; 633 cba.cba_memt = sc->sc_memt; 634 cba.cba_dmat = sc->sc_dmat; 635 cba.cba_function = 0; 636 cba.cba_bus = (busreg >> 8) & 0x0ff; 637 cba.cba_cc = (void *)sc; 638 cba.cba_cf = &pccbb_funcs; 639 cba.cba_intrline = sc->sc_intrline; 640 641 #if rbus 642 cba.cba_rbus_iot = sc->sc_rbus_iot; 643 cba.cba_rbus_memt = sc->sc_rbus_memt; 644 #endif 645 646 cba.cba_cacheline = PCI_CACHELINE(bhlc); 647 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 648 649 printf("%s: cacheline 0x%x lattimer 0x%x\n", 650 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 651 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 652 busreg); 653 #if defined SHOW_REGS 654 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 655 sc->sc_base_memh); 656 #endif 657 } 658 659 pccbb_pcmcia_attach_setup(sc, &paa); 660 caa.caa_cb_attach = NULL; 661 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 662 caa.caa_cb_attach = &cba; 663 } 664 caa.caa_16_attach = &paa; 665 caa.caa_ph = &sc->sc_pcmcia_h; 666 667 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 668 DPRINTF(("pccbbattach: found cardslot\n")); 669 sc->sc_csc = csc; 670 } 671 672 return; 673 } 674 675 676 677 678 679 /* 680 * static void pccbb_chipinit(struct pccbb_softc *sc) 681 * 682 * This function initialize YENTA chip registers listed below: 683 * 1) PCI command reg, 684 * 2) PCI and CardBus latency timer, 685 * 3) disable legacy (PCIC-compatible) io, 686 * 4) route PCI interrupt, 687 * 5) close all memory and io windows. 688 */ 689 static void 690 pccbb_chipinit(sc) 691 struct pccbb_softc *sc; 692 { 693 pci_chipset_tag_t pc = sc->sc_pc; 694 pcitag_t tag = sc->sc_tag; 695 pcireg_t reg; 696 697 /* 698 * Set PCI command reg. 699 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 700 */ 701 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 702 /* I believe it is harmless. */ 703 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 704 PCI_COMMAND_MASTER_ENABLE); 705 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 706 707 /* 708 * Set CardBus latency timer. 709 */ 710 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 711 if (PCI_CB_LATENCY(reg) < 0x20) { 712 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 713 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 714 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 715 } 716 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 717 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 718 719 /* 720 * Set PCI latency timer. 721 */ 722 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 723 if (PCI_LATTIMER(reg) < 0x10) { 724 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 725 reg |= (0x10 << PCI_LATTIMER_SHIFT); 726 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 727 } 728 DPRINTF(("PCI latency timer 0x%x (%x)\n", 729 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 730 731 /* Disable legacy register mapping. */ 732 switch (sc->sc_chipset) { 733 case CB_RX5C46X: /* fallthrough */ 734 #if 0 735 case CB_RX5C47X: 736 #endif 737 /* 738 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 739 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 740 * CardBus bridges have special bits on Bridge control reg (addr 741 * 0x3e on PCI config space). 742 */ 743 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 744 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 745 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 746 break; 747 748 default: 749 /* XXX I don't know proper way to kill legacy I/O. */ 750 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 751 break; 752 } 753 754 /* Route functional interrupts to PCI. */ 755 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 756 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 757 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 758 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 759 760 switch (sc->sc_chipset) { 761 case CB_TI113X: 762 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 763 /* This bit is shared, but may read as 0 on some chips, so set 764 it explicitly on both functions. */ 765 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 766 /* CSC intr enable */ 767 reg |= PCI113X_CBCTRL_PCI_CSC; 768 /* functional intr prohibit */ 769 reg &= ~PCI113X_CBCTRL_PCI_INTR; 770 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 771 break; 772 773 case CB_TOPIC95B: 774 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 775 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 776 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 777 778 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 779 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 780 sc->sc_dev.dv_xname, reg)); 781 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 782 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 783 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 784 DPRINTF(("0x%x\n", reg)); 785 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 786 break; 787 } 788 789 /* Close all memory and I/O windows. */ 790 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 791 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 792 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 793 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 794 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 795 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 796 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 797 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 798 } 799 800 801 802 803 /* 804 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 805 * struct pcmciabus_attach_args *paa) 806 * 807 * This function attaches 16-bit PCcard bus. 808 */ 809 STATIC void 810 pccbb_pcmcia_attach_setup(sc, paa) 811 struct pccbb_softc *sc; 812 struct pcmciabus_attach_args *paa; 813 { 814 struct pcic_handle *ph = &sc->sc_pcmcia_h; 815 #if rbus 816 rbus_tag_t rb; 817 #endif 818 819 /* initialize pcmcia part in pccbb_softc */ 820 ph->ph_parent = (struct device *)sc; 821 ph->sock = sc->sc_function; 822 ph->flags = 0; 823 ph->shutdown = 0; 824 ph->ih_irq = sc->sc_intrline; 825 ph->ph_bus_t = sc->sc_base_memt; 826 ph->ph_bus_h = sc->sc_base_memh; 827 ph->ph_read = pccbb_pcmcia_read; 828 ph->ph_write = pccbb_pcmcia_write; 829 sc->sc_pct = &pccbb_pcmcia_funcs; 830 831 /* 832 * We need to do a few things here: 833 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 834 * setting the IRQ numbers to 0. 835 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 836 * routing of CSC interrupts (e.g. card removal) to PCI while in 837 * PCMCIA mode. We just leave this set all the time. 838 * 3) Enable card insertion/removal interrupts in case the chip also 839 * needs that while in PCMCIA mode. 840 * 4) Clear any pending CSC interrupt. 841 */ 842 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 843 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 844 Pcic_read(ph, PCIC_CSC); 845 846 /* initialize pcmcia bus attachment */ 847 paa->paa_busname = "pcmcia"; 848 paa->pct = sc->sc_pct; 849 paa->pch = ph; 850 paa->iobase = 0; /* I don't use them */ 851 paa->iosize = 0; 852 #if rbus 853 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 854 paa->iobase = rb->rb_start + rb->rb_offset; 855 paa->iosize = rb->rb_end - rb->rb_start; 856 #endif 857 858 return; 859 } 860 861 #if 0 862 STATIC void 863 pccbb_pcmcia_attach_card(ph) 864 struct pcic_handle *ph; 865 { 866 if (ph->flags & PCIC_FLAG_CARDP) { 867 panic("pccbb_pcmcia_attach_card: already attached"); 868 } 869 870 /* call the MI attach function */ 871 pcmcia_card_attach(ph->pcmcia); 872 873 ph->flags |= PCIC_FLAG_CARDP; 874 } 875 876 STATIC void 877 pccbb_pcmcia_detach_card(ph, flags) 878 struct pcic_handle *ph; 879 int flags; 880 { 881 if (!(ph->flags & PCIC_FLAG_CARDP)) { 882 panic("pccbb_pcmcia_detach_card: already detached"); 883 } 884 885 ph->flags &= ~PCIC_FLAG_CARDP; 886 887 /* call the MI detach function */ 888 pcmcia_card_detach(ph->pcmcia, flags); 889 } 890 #endif 891 892 /* 893 * int pccbbintr(arg) 894 * void *arg; 895 * This routine handles the interrupt from Yenta PCI-CardBus bridge 896 * itself. 897 */ 898 int 899 pccbbintr(arg) 900 void *arg; 901 { 902 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 903 u_int32_t sockevent, sockstate; 904 bus_space_tag_t memt = sc->sc_base_memt; 905 bus_space_handle_t memh = sc->sc_base_memh; 906 struct pcic_handle *ph = &sc->sc_pcmcia_h; 907 908 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 909 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 910 Pcic_read(ph, PCIC_CSC); 911 912 if (sockevent == 0) { 913 /* This intr is not for me: it may be for my child devices. */ 914 return (pccbbintr_function(sc)); 915 } 916 917 if (sockevent & CB_SOCKET_EVENT_CD) { 918 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 919 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 920 /* A card should be removed. */ 921 if (sc->sc_flags & CBB_CARDEXIST) { 922 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 923 sockevent)); 924 DPRINTF((" card removed, 0x%08x\n", sockstate)); 925 sc->sc_flags &= ~CBB_CARDEXIST; 926 if (sc->sc_csc->sc_status & 927 CARDSLOT_STATUS_CARD_16) { 928 #if 0 929 struct pcic_handle *ph = 930 &sc->sc_pcmcia_h; 931 932 pcmcia_card_deactivate(ph->pcmcia); 933 pccbb_pcmcia_socket_disable(ph); 934 pccbb_pcmcia_detach_card(ph, 935 DETACH_FORCE); 936 #endif 937 cardslot_event_throw(sc->sc_csc, 938 CARDSLOT_EVENT_REMOVAL_16); 939 } else if (sc->sc_csc->sc_status & 940 CARDSLOT_STATUS_CARD_CB) { 941 /* Cardbus intr removed */ 942 cardslot_event_throw(sc->sc_csc, 943 CARDSLOT_EVENT_REMOVAL_CB); 944 } 945 } 946 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 947 /* 948 * The pccbbintr may called from powerdown hook when 949 * the system resumed, to detect the card 950 * insertion/removal during suspension. 951 */ 952 (sc->sc_flags & CBB_CARDEXIST) == 0) { 953 if (sc->sc_flags & CBB_INSERTING) { 954 untimeout(pci113x_insert, sc); 955 } 956 timeout(pci113x_insert, sc, hz / 10); 957 sc->sc_flags |= CBB_INSERTING; 958 } 959 } 960 961 return (1); 962 } 963 964 /* 965 * static int pccbbintr_function(struct pccbb_softc *sc) 966 * 967 * This function calls each interrupt handler registered at the 968 * bridge. The interrupt handlers are called in registered order. 969 */ 970 static int 971 pccbbintr_function(sc) 972 struct pccbb_softc *sc; 973 { 974 int retval = 0, val; 975 struct pccbb_intrhand_list *pil; 976 977 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 978 val = (*pil->pil_func) (pil->pil_arg); 979 retval = retval == 1 ? 1 : 980 retval == 0 ? val : val != 0 ? val : retval; 981 } 982 983 return retval; 984 } 985 986 static void 987 pci113x_insert(arg) 988 void *arg; 989 { 990 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 991 u_int32_t sockevent, sockstate; 992 993 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 994 CB_SOCKET_EVENT); 995 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 996 CB_SOCKET_STAT); 997 998 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 999 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1000 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1001 sc->sc_flags |= CBB_CARDEXIST; 1002 /* call pccard interrupt handler here */ 1003 if (sockstate & CB_SOCKET_STAT_16BIT) { 1004 /* 16-bit card found */ 1005 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1006 cardslot_event_throw(sc->sc_csc, 1007 CARDSLOT_EVENT_INSERTION_16); 1008 } else if (sockstate & CB_SOCKET_STAT_CB) { 1009 /* cardbus card found */ 1010 /* cardbus_attach_card(sc->sc_csc); */ 1011 cardslot_event_throw(sc->sc_csc, 1012 CARDSLOT_EVENT_INSERTION_CB); 1013 } else { 1014 /* who are you? */ 1015 } 1016 } else { 1017 timeout(pci113x_insert, sc, hz / 10); 1018 } 1019 } 1020 1021 #define PCCBB_PCMCIA_OFFSET 0x800 1022 static u_int8_t 1023 pccbb_pcmcia_read(ph, reg) 1024 struct pcic_handle *ph; 1025 int reg; 1026 { 1027 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1028 PCCBB_PCMCIA_OFFSET + reg); 1029 } 1030 1031 static void 1032 pccbb_pcmcia_write(ph, reg, val) 1033 struct pcic_handle *ph; 1034 int reg; 1035 u_int8_t val; 1036 { 1037 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1038 val); 1039 } 1040 1041 /* 1042 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1043 */ 1044 STATIC int 1045 pccbb_ctrl(ct, command) 1046 cardbus_chipset_tag_t ct; 1047 int command; 1048 { 1049 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1050 1051 switch (command) { 1052 case CARDBUS_CD: 1053 if (2 == pccbb_detect_card(sc)) { 1054 int retval = 0; 1055 int status = cb_detect_voltage(sc); 1056 if (PCCARD_VCC_5V & status) { 1057 retval |= CARDBUS_5V_CARD; 1058 } 1059 if (PCCARD_VCC_3V & status) { 1060 retval |= CARDBUS_3V_CARD; 1061 } 1062 if (PCCARD_VCC_XV & status) { 1063 retval |= CARDBUS_XV_CARD; 1064 } 1065 if (PCCARD_VCC_YV & status) { 1066 retval |= CARDBUS_YV_CARD; 1067 } 1068 return retval; 1069 } else { 1070 return 0; 1071 } 1072 break; 1073 case CARDBUS_RESET: 1074 return cb_reset(sc); 1075 break; 1076 case CARDBUS_IO_ENABLE: /* fallthrough */ 1077 case CARDBUS_IO_DISABLE: /* fallthrough */ 1078 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1079 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1080 case CARDBUS_BM_ENABLE: /* fallthrough */ 1081 case CARDBUS_BM_DISABLE: /* fallthrough */ 1082 return pccbb_cardenable(sc, command); 1083 break; 1084 } 1085 1086 return 0; 1087 } 1088 1089 /* 1090 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1091 * This function returns true when it succeeds and returns false when 1092 * it fails. 1093 */ 1094 STATIC int 1095 pccbb_power(ct, command) 1096 cardbus_chipset_tag_t ct; 1097 int command; 1098 { 1099 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1100 1101 u_int32_t status, sock_ctrl; 1102 bus_space_tag_t memt = sc->sc_base_memt; 1103 bus_space_handle_t memh = sc->sc_base_memh; 1104 1105 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1106 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1107 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1108 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1109 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1110 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1111 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1112 "UNKNOWN", 1113 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1114 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1115 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1116 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1117 "UNKNOWN", command)); 1118 1119 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1120 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1121 1122 switch (command & CARDBUS_VCCMASK) { 1123 case CARDBUS_VCC_UC: 1124 break; 1125 case CARDBUS_VCC_5V: 1126 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1127 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1128 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1129 } else { 1130 printf("%s: BAD voltage request: no 5 V card\n", 1131 sc->sc_dev.dv_xname); 1132 } 1133 break; 1134 case CARDBUS_VCC_3V: 1135 if (CB_SOCKET_STAT_3VCARD & status) { 1136 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1137 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1138 } else { 1139 printf("%s: BAD voltage request: no 3.3 V card\n", 1140 sc->sc_dev.dv_xname); 1141 } 1142 break; 1143 case CARDBUS_VCC_0V: 1144 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1145 break; 1146 default: 1147 return 0; /* power NEVER changed */ 1148 break; 1149 } 1150 1151 switch (command & CARDBUS_VPPMASK) { 1152 case CARDBUS_VPP_UC: 1153 break; 1154 case CARDBUS_VPP_0V: 1155 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1156 break; 1157 case CARDBUS_VPP_VCC: 1158 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1159 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1160 break; 1161 case CARDBUS_VPP_12V: 1162 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1163 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1164 break; 1165 } 1166 1167 #if 0 1168 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1169 #endif 1170 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1171 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1172 1173 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1174 /* 1175 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1176 * time is 20 ms, some PC-Card bridge requires longer duration. 1177 */ 1178 delay(200 * 1000); 1179 1180 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1181 printf 1182 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1183 sc->sc_dev.dv_xname, sock_ctrl, status); 1184 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1185 (command & CARDBUS_VCCMASK) == 1186 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1187 CARDBUS_VCCMASK) == 1188 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1189 CARDBUS_VCCMASK) == 1190 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1191 CARDBUS_VCCMASK) == 1192 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1193 CARDBUS_VCCMASK) == 1194 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1195 CARDBUS_VCCMASK) == 1196 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1197 (command & CARDBUS_VPPMASK) == 1198 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1199 CARDBUS_VPPMASK) == 1200 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1201 CARDBUS_VPPMASK) == 1202 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1203 CARDBUS_VPPMASK) == 1204 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1205 #if 0 1206 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1207 u_int32_t force = 1208 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1209 /* Reset Bad Vcc request */ 1210 force &= ~CB_SOCKET_FORCE_BADVCC; 1211 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1212 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1213 CB_SOCKET_STAT)); 1214 return 1; 1215 } 1216 #endif 1217 return 0; 1218 } 1219 return 1; /* power changed correctly */ 1220 } 1221 1222 #if defined CB_PCMCIA_POLL 1223 struct cb_poll_str { 1224 void *arg; 1225 int (*func) __P((void *)); 1226 int level; 1227 pccard_chipset_tag_t ct; 1228 int count; 1229 }; 1230 1231 static struct cb_poll_str cb_poll[10]; 1232 static int cb_poll_n = 0; 1233 1234 static void cb_pcmcia_poll __P((void *arg)); 1235 1236 static void 1237 cb_pcmcia_poll(arg) 1238 void *arg; 1239 { 1240 struct cb_poll_str *poll = arg; 1241 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1242 struct pccbb_softc *sc = psc->cpc_parent; 1243 int s; 1244 u_int32_t spsr; /* socket present-state reg */ 1245 1246 timeout(cb_pcmcia_poll, arg, hz / 10); 1247 switch (poll->level) { 1248 case IPL_NET: 1249 s = splnet(); 1250 break; 1251 case IPL_BIO: 1252 s = splbio(); 1253 break; 1254 case IPL_TTY: /* fallthrough */ 1255 default: 1256 s = spltty(); 1257 break; 1258 } 1259 1260 spsr = 1261 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1262 CB_SOCKET_STAT); 1263 1264 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1265 if (!(spsr & 0x40)) { /* CINT low */ 1266 #else 1267 if (1) { 1268 #endif 1269 if ((*poll->func) (poll->arg) == 1) { 1270 ++poll->count; 1271 printf("intr: reported from poller, 0x%x\n", spsr); 1272 #if defined LEVEL2 1273 } else { 1274 printf("intr: miss! 0x%x\n", spsr); 1275 #endif 1276 } 1277 } 1278 splx(s); 1279 } 1280 #endif /* defined CB_PCMCIA_POLL */ 1281 1282 /* 1283 * static int pccbb_detect_card(struct pccbb_softc *sc) 1284 * return value: 0 if no card exists. 1285 * 1 if 16-bit card exists. 1286 * 2 if cardbus card exists. 1287 */ 1288 static int 1289 pccbb_detect_card(sc) 1290 struct pccbb_softc *sc; 1291 { 1292 bus_space_handle_t base_memh = sc->sc_base_memh; 1293 bus_space_tag_t base_memt = sc->sc_base_memt; 1294 u_int32_t sockstat = 1295 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1296 int retval = 0; 1297 1298 /* CD1 and CD2 asserted */ 1299 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1300 /* card must be present */ 1301 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1302 /* NOTACARD DEASSERTED */ 1303 if (CB_SOCKET_STAT_CB & sockstat) { 1304 /* CardBus mode */ 1305 retval = 2; 1306 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1307 /* 16-bit mode */ 1308 retval = 1; 1309 } 1310 } 1311 } 1312 return retval; 1313 } 1314 1315 /* 1316 * STATIC int cb_reset(struct pccbb_softc *sc) 1317 * This function resets CardBus card. 1318 */ 1319 STATIC int 1320 cb_reset(sc) 1321 struct pccbb_softc *sc; 1322 { 1323 /* 1324 * Reset Assert at least 20 ms 1325 * Some machines request longer duration. 1326 */ 1327 int reset_duration = 1328 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1329 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1330 1331 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1332 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1333 delay(reset_duration); 1334 1335 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1336 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1337 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1338 delay(reset_duration); 1339 } 1340 /* No card found on the slot. Keep Reset. */ 1341 return 1; 1342 } 1343 1344 /* 1345 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1346 * This function detect card Voltage. 1347 */ 1348 STATIC int 1349 cb_detect_voltage(sc) 1350 struct pccbb_softc *sc; 1351 { 1352 u_int32_t psr; /* socket present-state reg */ 1353 bus_space_tag_t iot = sc->sc_base_memt; 1354 bus_space_handle_t ioh = sc->sc_base_memh; 1355 int vol = PCCARD_VCC_UKN; /* set 0 */ 1356 1357 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1358 1359 if (0x400u & psr) { 1360 vol |= PCCARD_VCC_5V; 1361 } 1362 if (0x800u & psr) { 1363 vol |= PCCARD_VCC_3V; 1364 } 1365 1366 return vol; 1367 } 1368 1369 STATIC int 1370 cbbprint(aux, pcic) 1371 void *aux; 1372 const char *pcic; 1373 { 1374 /* 1375 struct cbslot_attach_args *cba = aux; 1376 1377 if (cba->cba_slot >= 0) { 1378 printf(" slot %d", cba->cba_slot); 1379 } 1380 */ 1381 return UNCONF; 1382 } 1383 1384 /* 1385 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1386 * This function enables and disables the card 1387 */ 1388 STATIC int 1389 pccbb_cardenable(sc, function) 1390 struct pccbb_softc *sc; 1391 int function; 1392 { 1393 u_int32_t command = 1394 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1395 1396 DPRINTF(("pccbb_cardenable:")); 1397 switch (function) { 1398 case CARDBUS_IO_ENABLE: 1399 command |= PCI_COMMAND_IO_ENABLE; 1400 break; 1401 case CARDBUS_IO_DISABLE: 1402 command &= ~PCI_COMMAND_IO_ENABLE; 1403 break; 1404 case CARDBUS_MEM_ENABLE: 1405 command |= PCI_COMMAND_MEM_ENABLE; 1406 break; 1407 case CARDBUS_MEM_DISABLE: 1408 command &= ~PCI_COMMAND_MEM_ENABLE; 1409 break; 1410 case CARDBUS_BM_ENABLE: 1411 command |= PCI_COMMAND_MASTER_ENABLE; 1412 break; 1413 case CARDBUS_BM_DISABLE: 1414 command &= ~PCI_COMMAND_MASTER_ENABLE; 1415 break; 1416 default: 1417 return 0; 1418 } 1419 1420 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1421 DPRINTF((" command reg 0x%x\n", command)); 1422 return 1; 1423 } 1424 1425 #if !rbus 1426 /* 1427 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1428 */ 1429 static int 1430 pccbb_io_open(ct, win, start, end) 1431 cardbus_chipset_tag_t ct; 1432 int win; 1433 u_int32_t start, end; 1434 { 1435 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1436 int basereg; 1437 int limitreg; 1438 1439 if ((win < 0) || (win > 2)) { 1440 #if defined DIAGNOSTIC 1441 printf("cardbus_io_open: window out of range %d\n", win); 1442 #endif 1443 return 0; 1444 } 1445 1446 basereg = win * 8 + 0x2c; 1447 limitreg = win * 8 + 0x30; 1448 1449 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1450 start, basereg, end, limitreg)); 1451 1452 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1453 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1454 return 1; 1455 } 1456 1457 /* 1458 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1459 */ 1460 static int 1461 pccbb_io_close(ct, win) 1462 cardbus_chipset_tag_t ct; 1463 int win; 1464 { 1465 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1466 int basereg; 1467 int limitreg; 1468 1469 if ((win < 0) || (win > 2)) { 1470 #if defined DIAGNOSTIC 1471 printf("cardbus_io_close: window out of range %d\n", win); 1472 #endif 1473 return 0; 1474 } 1475 1476 basereg = win * 8 + 0x2c; 1477 limitreg = win * 8 + 0x30; 1478 1479 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1480 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1481 return 1; 1482 } 1483 1484 /* 1485 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1486 */ 1487 static int 1488 pccbb_mem_open(ct, win, start, end) 1489 cardbus_chipset_tag_t ct; 1490 int win; 1491 u_int32_t start, end; 1492 { 1493 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1494 int basereg; 1495 int limitreg; 1496 1497 if ((win < 0) || (win > 2)) { 1498 #if defined DIAGNOSTIC 1499 printf("cardbus_mem_open: window out of range %d\n", win); 1500 #endif 1501 return 0; 1502 } 1503 1504 basereg = win * 8 + 0x1c; 1505 limitreg = win * 8 + 0x20; 1506 1507 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1508 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1509 return 1; 1510 } 1511 1512 /* 1513 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1514 */ 1515 static int 1516 pccbb_mem_close(ct, win) 1517 cardbus_chipset_tag_t ct; 1518 int win; 1519 { 1520 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1521 int basereg; 1522 int limitreg; 1523 1524 if ((win < 0) || (win > 2)) { 1525 #if defined DIAGNOSTIC 1526 printf("cardbus_mem_close: window out of range %d\n", win); 1527 #endif 1528 return 0; 1529 } 1530 1531 basereg = win * 8 + 0x1c; 1532 limitreg = win * 8 + 0x20; 1533 1534 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1535 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1536 return 1; 1537 } 1538 #endif 1539 1540 /* 1541 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1542 * int irq, 1543 * int level, 1544 * int (* func) __P((void *)), 1545 * void *arg) 1546 * 1547 * This function registers an interrupt handler at the bridge, in 1548 * order not to call the interrupt handlers of child devices when 1549 * a card-deletion interrupt occurs. 1550 * 1551 * The arguments irq and level are not used. 1552 */ 1553 static void * 1554 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1555 cardbus_chipset_tag_t ct; 1556 int irq, level; 1557 int (*func) __P((void *)); 1558 void *arg; 1559 { 1560 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1561 1562 return pccbb_intr_establish(sc, irq, level, func, arg); 1563 } 1564 1565 1566 /* 1567 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1568 * void *ih) 1569 * 1570 * This function removes an interrupt handler pointed by ih. 1571 */ 1572 static void 1573 pccbb_cb_intr_disestablish(ct, ih) 1574 cardbus_chipset_tag_t ct; 1575 void *ih; 1576 { 1577 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1578 1579 pccbb_intr_disestablish(sc, ih); 1580 } 1581 1582 1583 /* 1584 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1585 * int irq, 1586 * int level, 1587 * int (* func) __P((void *)), 1588 * void *arg) 1589 * 1590 * This function registers an interrupt handler at the bridge, in 1591 * order not to call the interrupt handlers of child devices when 1592 * a card-deletion interrupt occurs. 1593 * 1594 * The arguments irq and level are not used. 1595 */ 1596 static void * 1597 pccbb_intr_establish(sc, irq, level, func, arg) 1598 struct pccbb_softc *sc; 1599 int irq, level; 1600 int (*func) __P((void *)); 1601 void *arg; 1602 { 1603 struct pccbb_intrhand_list *pil, *newpil; 1604 1605 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1606 1607 if (sc->sc_pil == NULL) { 1608 /* initialize bridge intr routing */ 1609 1610 switch (sc->sc_chipset) { 1611 case CB_TI113X: 1612 { 1613 pcireg_t cbctrl = 1614 pci_conf_read(sc->sc_pc, sc->sc_tag, 1615 PCI_CBCTRL); 1616 /* functional intr enabled */ 1617 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1618 pci_conf_write(sc->sc_pc, sc->sc_tag, 1619 PCI_CBCTRL, cbctrl); 1620 break; 1621 } 1622 default: 1623 break; 1624 } 1625 } 1626 1627 /* 1628 * Allocate a room for interrupt handler structure. 1629 */ 1630 if (NULL == (newpil = 1631 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1632 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1633 return NULL; 1634 } 1635 1636 newpil->pil_func = func; 1637 newpil->pil_arg = arg; 1638 newpil->pil_next = NULL; 1639 1640 if (sc->sc_pil == NULL) { 1641 sc->sc_pil = newpil; 1642 } else { 1643 for (pil = sc->sc_pil; pil->pil_next != NULL; 1644 pil = pil->pil_next); 1645 pil->pil_next = newpil; 1646 } 1647 1648 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1649 1650 return newpil; 1651 } 1652 1653 /* 1654 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1655 * void *ih) 1656 * 1657 * This function removes an interrupt handler pointed by ih. 1658 */ 1659 static void 1660 pccbb_intr_disestablish(sc, ih) 1661 struct pccbb_softc *sc; 1662 void *ih; 1663 { 1664 struct pccbb_intrhand_list *pil, **pil_prev; 1665 1666 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1667 1668 pil_prev = &sc->sc_pil; 1669 1670 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1671 if (pil == ih) { 1672 *pil_prev = pil->pil_next; 1673 free(pil, M_DEVBUF); 1674 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1675 break; 1676 } 1677 pil_prev = &pil->pil_next; 1678 } 1679 1680 if (sc->sc_pil == NULL) { 1681 /* No interrupt handlers */ 1682 1683 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1684 1685 switch (sc->sc_chipset) { 1686 case CB_TI113X: 1687 { 1688 pcireg_t cbctrl = 1689 pci_conf_read(sc->sc_pc, sc->sc_tag, 1690 PCI_CBCTRL); 1691 /* functional intr disabled */ 1692 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1693 pci_conf_write(sc->sc_pc, sc->sc_tag, 1694 PCI_CBCTRL, cbctrl); 1695 break; 1696 } 1697 default: 1698 break; 1699 } 1700 } 1701 } 1702 1703 #if defined SHOW_REGS 1704 static void 1705 cb_show_regs(pc, tag, memt, memh) 1706 pci_chipset_tag_t pc; 1707 pcitag_t tag; 1708 bus_space_tag_t memt; 1709 bus_space_handle_t memh; 1710 { 1711 int i; 1712 printf("PCI config regs:"); 1713 for (i = 0; i < 0x50; i += 4) { 1714 if (i % 16 == 0) { 1715 printf("\n 0x%02x:", i); 1716 } 1717 printf(" %08x", pci_conf_read(pc, tag, i)); 1718 } 1719 for (i = 0x80; i < 0xb0; i += 4) { 1720 if (i % 16 == 0) { 1721 printf("\n 0x%02x:", i); 1722 } 1723 printf(" %08x", pci_conf_read(pc, tag, i)); 1724 } 1725 1726 if (memh == 0) { 1727 printf("\n"); 1728 return; 1729 } 1730 1731 printf("\nsocket regs:"); 1732 for (i = 0; i <= 0x10; i += 0x04) { 1733 printf(" %08x", bus_space_read_4(memt, memh, i)); 1734 } 1735 printf("\nExCA regs:"); 1736 for (i = 0; i < 0x08; ++i) { 1737 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1738 } 1739 printf("\n"); 1740 return; 1741 } 1742 #endif 1743 1744 /* 1745 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1746 * int busno, int devno, int function) 1747 * This is the function to make a tag to access config space of 1748 * a CardBus Card. It works same as pci_conf_read. 1749 */ 1750 static cardbustag_t 1751 pccbb_make_tag(cc, busno, devno, function) 1752 cardbus_chipset_tag_t cc; 1753 int busno, devno, function; 1754 { 1755 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1756 1757 return pci_make_tag(sc->sc_pc, busno, devno, function); 1758 } 1759 1760 static void 1761 pccbb_free_tag(cc, tag) 1762 cardbus_chipset_tag_t cc; 1763 cardbustag_t tag; 1764 { 1765 } 1766 1767 /* 1768 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1769 * cardbustag_t tag, int offset) 1770 * This is the function to read the config space of a CardBus Card. 1771 * It works same as pci_conf_read. 1772 */ 1773 static cardbusreg_t 1774 pccbb_conf_read(cc, tag, offset) 1775 cardbus_chipset_tag_t cc; 1776 cardbustag_t tag; 1777 int offset; /* register offset */ 1778 { 1779 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1780 1781 return pci_conf_read(sc->sc_pc, tag, offset); 1782 } 1783 1784 /* 1785 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1786 * int offs, cardbusreg_t val) 1787 * This is the function to write the config space of a CardBus Card. 1788 * It works same as pci_conf_write. 1789 */ 1790 static void 1791 pccbb_conf_write(cc, tag, reg, val) 1792 cardbus_chipset_tag_t cc; 1793 cardbustag_t tag; 1794 int reg; /* register offset */ 1795 cardbusreg_t val; 1796 { 1797 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1798 1799 pci_conf_write(sc->sc_pc, tag, reg, val); 1800 } 1801 1802 #if 0 1803 STATIC int 1804 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1805 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1806 int speed, int flags, 1807 bus_space_handle_t * iohp) 1808 #endif 1809 /* 1810 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1811 * bus_addr_t start, bus_size_t size, 1812 * bus_size_t align, 1813 * struct pcmcia_io_handle *pcihp 1814 * 1815 * This function only allocates I/O region for pccard. This function 1816 * never maps the allocated region to pccard I/O area. 1817 * 1818 * XXX: The interface of this function is not very good, I believe. 1819 */ 1820 STATIC int 1821 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1822 pcmcia_chipset_handle_t pch; 1823 bus_addr_t start; /* start address */ 1824 bus_size_t size; 1825 bus_size_t align; 1826 struct pcmcia_io_handle *pcihp; 1827 { 1828 struct pcic_handle *ph = (struct pcic_handle *)pch; 1829 bus_addr_t ioaddr; 1830 int flags = 0; 1831 bus_space_tag_t iot; 1832 bus_space_handle_t ioh; 1833 #if rbus 1834 rbus_tag_t rb; 1835 #endif 1836 if (align == 0) { 1837 align = size; /* XXX: funny??? */ 1838 } 1839 1840 /* 1841 * Allocate some arbitrary I/O space. 1842 */ 1843 1844 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1845 1846 #if rbus 1847 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1848 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1849 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1850 return 1; 1851 } 1852 #else 1853 if (start) { 1854 ioaddr = start; 1855 if (bus_space_map(iot, start, size, 0, &ioh)) { 1856 return 1; 1857 } 1858 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1859 (u_long) ioaddr, (u_long) size)); 1860 } else { 1861 flags |= PCMCIA_IO_ALLOCATED; 1862 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1863 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1864 size, align, 0, 0, &ioaddr, &ioh)) { 1865 /* No room be able to be get. */ 1866 return 1; 1867 } 1868 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1869 (u_long) ioaddr, (u_long) size)); 1870 } 1871 #endif 1872 1873 pcihp->iot = iot; 1874 pcihp->ioh = ioh; 1875 pcihp->addr = ioaddr; 1876 pcihp->size = size; 1877 pcihp->flags = flags; 1878 1879 return 0; 1880 } 1881 1882 /* 1883 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1884 * struct pcmcia_io_handle *pcihp) 1885 * 1886 * This function only frees I/O region for pccard. 1887 * 1888 * XXX: The interface of this function is not very good, I believe. 1889 */ 1890 void 1891 pccbb_pcmcia_io_free(pch, pcihp) 1892 pcmcia_chipset_handle_t pch; 1893 struct pcmcia_io_handle *pcihp; 1894 { 1895 #if !rbus 1896 bus_space_tag_t iot = pcihp->iot; 1897 #endif 1898 bus_space_handle_t ioh = pcihp->ioh; 1899 bus_size_t size = pcihp->size; 1900 1901 #if rbus 1902 struct pccbb_softc *sc = 1903 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1904 rbus_tag_t rb = sc->sc_rbus_iot; 1905 1906 rbus_space_free(rb, ioh, size, NULL); 1907 #else 1908 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1909 bus_space_free(iot, ioh, size); 1910 else 1911 bus_space_unmap(iot, ioh, size); 1912 #endif 1913 } 1914 1915 /* 1916 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1917 * bus_addr_t offset, bus_size_t size, 1918 * struct pcmcia_io_handle *pcihp, 1919 * int *windowp) 1920 * 1921 * This function maps the allocated I/O region to pccard. This function 1922 * never allocates any I/O region for pccard I/O area. I don't 1923 * understand why the original authors of pcmciabus separated alloc and 1924 * map. I believe the two must be unite. 1925 * 1926 * XXX: no wait timing control? 1927 */ 1928 int 1929 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1930 pcmcia_chipset_handle_t pch; 1931 int width; 1932 bus_addr_t offset; 1933 bus_size_t size; 1934 struct pcmcia_io_handle *pcihp; 1935 int *windowp; 1936 { 1937 struct pcic_handle *ph = (struct pcic_handle *)pch; 1938 bus_addr_t ioaddr = pcihp->addr + offset; 1939 int i, win; 1940 #if defined CBB_DEBUG 1941 static char *width_names[] = { "dynamic", "io8", "io16" }; 1942 #endif 1943 1944 /* Sanity check I/O handle. */ 1945 1946 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1947 panic("pccbb_pcmcia_io_map iot is bogus"); 1948 } 1949 1950 /* XXX Sanity check offset/size. */ 1951 1952 win = -1; 1953 for (i = 0; i < PCIC_IO_WINS; i++) { 1954 if ((ph->ioalloc & (1 << i)) == 0) { 1955 win = i; 1956 ph->ioalloc |= (1 << i); 1957 break; 1958 } 1959 } 1960 1961 if (win == -1) { 1962 return 1; 1963 } 1964 1965 *windowp = win; 1966 1967 /* XXX this is pretty gross */ 1968 1969 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1970 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1971 1972 /* XXX wtf is this doing here? */ 1973 1974 #if 0 1975 printf(" port 0x%lx", (u_long) ioaddr); 1976 if (size > 1) { 1977 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1978 } 1979 #endif 1980 1981 ph->io[win].addr = ioaddr; 1982 ph->io[win].size = size; 1983 ph->io[win].width = width; 1984 1985 /* actual dirty register-value changing in the function below. */ 1986 pccbb_pcmcia_do_io_map(ph, win); 1987 1988 return 0; 1989 } 1990 1991 /* 1992 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1993 * 1994 * This function changes register-value to map I/O region for pccard. 1995 */ 1996 static void 1997 pccbb_pcmcia_do_io_map(ph, win) 1998 struct pcic_handle *ph; 1999 int win; 2000 { 2001 static u_int8_t pcic_iowidth[3] = { 2002 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2003 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2004 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2005 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2006 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2007 }; 2008 2009 #define PCIC_SIA_START_LOW 0 2010 #define PCIC_SIA_START_HIGH 1 2011 #define PCIC_SIA_STOP_LOW 2 2012 #define PCIC_SIA_STOP_HIGH 3 2013 2014 int regbase_win = 0x8 + win * 0x04; 2015 u_int8_t ioctl, enable; 2016 2017 DPRINTF( 2018 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2019 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2020 ph->io[win].width * 8)); 2021 2022 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2023 ph->io[win].addr & 0xff); 2024 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2025 (ph->io[win].addr >> 8) & 0xff); 2026 2027 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2028 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2029 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2030 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2031 2032 ioctl = Pcic_read(ph, PCIC_IOCTL); 2033 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2034 switch (win) { 2035 case 0: 2036 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2037 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2038 PCIC_IOCTL_IO0_DATASIZE_MASK); 2039 ioctl |= pcic_iowidth[ph->io[win].width]; 2040 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2041 break; 2042 case 1: 2043 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2044 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2045 PCIC_IOCTL_IO1_DATASIZE_MASK); 2046 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2047 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2048 break; 2049 } 2050 Pcic_write(ph, PCIC_IOCTL, ioctl); 2051 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2052 #if defined CBB_DEBUG 2053 { 2054 u_int8_t start_low = 2055 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2056 u_int8_t start_high = 2057 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2058 u_int8_t stop_low = 2059 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2060 u_int8_t stop_high = 2061 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2062 printf 2063 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2064 start_low, start_high, stop_low, stop_high, ioctl, enable); 2065 } 2066 #endif 2067 } 2068 2069 /* 2070 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2071 * 2072 * This function unmaps I/O region. No return value. 2073 */ 2074 STATIC void 2075 pccbb_pcmcia_io_unmap(pch, win) 2076 pcmcia_chipset_handle_t pch; 2077 int win; 2078 { 2079 struct pcic_handle *ph = (struct pcic_handle *)pch; 2080 int reg; 2081 2082 if (win >= PCIC_IO_WINS || win < 0) { 2083 panic("pccbb_pcmcia_io_unmap: window out of range"); 2084 } 2085 2086 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2087 switch (win) { 2088 case 0: 2089 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2090 break; 2091 case 1: 2092 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2093 break; 2094 } 2095 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2096 2097 ph->ioalloc &= ~(1 << win); 2098 } 2099 2100 /* 2101 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2102 * 2103 * This function enables the card. All information is stored in 2104 * the first argument, pcmcia_chipset_handle_t. 2105 */ 2106 static void 2107 pccbb_pcmcia_wait_ready(ph) 2108 struct pcic_handle *ph; 2109 { 2110 int i; 2111 2112 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2113 Pcic_read(ph, PCIC_IF_STATUS))); 2114 2115 for (i = 0; i < 10000; i++) { 2116 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2117 return; 2118 } 2119 delay(500); 2120 #ifdef CBB_DEBUG 2121 if ((i > 5000) && (i % 100 == 99)) 2122 printf("."); 2123 #endif 2124 } 2125 2126 #ifdef DIAGNOSTIC 2127 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2128 Pcic_read(ph, PCIC_IF_STATUS)); 2129 #endif 2130 } 2131 2132 /* 2133 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2134 * 2135 * This function enables the card. All information is stored in 2136 * the first argument, pcmcia_chipset_handle_t. 2137 */ 2138 STATIC void 2139 pccbb_pcmcia_socket_enable(pch) 2140 pcmcia_chipset_handle_t pch; 2141 { 2142 struct pcic_handle *ph = (struct pcic_handle *)pch; 2143 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2144 int cardtype, win; 2145 u_int8_t power, intr; 2146 pcireg_t spsr; 2147 int voltage; 2148 2149 /* this bit is mostly stolen from pcic_attach_card */ 2150 2151 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2152 2153 /* get card Vcc info */ 2154 2155 spsr = 2156 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2157 CB_SOCKET_STAT); 2158 if (spsr & CB_SOCKET_STAT_5VCARD) { 2159 DPRINTF(("5V card\n")); 2160 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2161 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2162 DPRINTF(("3V card\n")); 2163 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2164 } else { 2165 printf("?V card, 0x%x\n", spsr); /* XXX */ 2166 return; 2167 } 2168 2169 /* assert reset bit */ 2170 intr = Pcic_read(ph, PCIC_INTR); 2171 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2172 Pcic_write(ph, PCIC_INTR, intr); 2173 2174 /* disable socket i/o: negate output enable bit */ 2175 2176 power = Pcic_read(ph, PCIC_PWRCTL); 2177 power &= ~PCIC_PWRCTL_OE; 2178 Pcic_write(ph, PCIC_PWRCTL, power); 2179 2180 /* power down the socket to reset it, clear the card reset pin */ 2181 2182 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2183 2184 /* 2185 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2186 * we are changing Vcc (Toff). 2187 */ 2188 /* delay(300*1000); too much */ 2189 2190 /* power up the socket */ 2191 pccbb_power(sc, voltage); 2192 2193 /* 2194 * wait 100ms until power raise (Tpr) and 20ms to become 2195 * stable (Tsu(Vcc)). 2196 * 2197 * some machines require some more time to be settled 2198 * (another 200ms is added here). 2199 */ 2200 /* delay((100 + 20 + 200)*1000); too much */ 2201 2202 power = Pcic_read(ph, PCIC_PWRCTL); 2203 power |= PCIC_PWRCTL_OE; 2204 Pcic_write(ph, PCIC_PWRCTL, power); 2205 2206 /* 2207 * hold RESET at least 10us. 2208 */ 2209 delay(10); 2210 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2211 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2212 2213 /* clear the reset flag */ 2214 2215 intr |= PCIC_INTR_RESET; 2216 Pcic_write(ph, PCIC_INTR, intr); 2217 2218 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2219 2220 delay(20000); 2221 2222 /* wait for the chip to finish initializing */ 2223 2224 pccbb_pcmcia_wait_ready(ph); 2225 2226 /* zero out the address windows */ 2227 2228 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2229 2230 /* set the card type */ 2231 2232 cardtype = pcmcia_card_gettype(ph->pcmcia); 2233 2234 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2235 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2236 Pcic_write(ph, PCIC_INTR, intr); 2237 2238 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2239 ph->ph_parent->dv_xname, ph->sock, 2240 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2241 2242 /* reinstall all the memory and io mappings */ 2243 2244 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2245 if (ph->memalloc & (1 << win)) { 2246 pccbb_pcmcia_do_mem_map(ph, win); 2247 } 2248 } 2249 2250 for (win = 0; win < PCIC_IO_WINS; ++win) { 2251 if (ph->ioalloc & (1 << win)) { 2252 pccbb_pcmcia_do_io_map(ph, win); 2253 } 2254 } 2255 } 2256 2257 /* 2258 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2259 * 2260 * This function disables the card. All information is stored in 2261 * the first argument, pcmcia_chipset_handle_t. 2262 */ 2263 STATIC void 2264 pccbb_pcmcia_socket_disable(pch) 2265 pcmcia_chipset_handle_t pch; 2266 { 2267 struct pcic_handle *ph = (struct pcic_handle *)pch; 2268 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2269 u_int8_t power, intr; 2270 2271 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2272 2273 /* reset signal asserting... */ 2274 2275 intr = Pcic_read(ph, PCIC_INTR); 2276 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2277 Pcic_write(ph, PCIC_INTR, intr); 2278 delay(2 * 1000); 2279 2280 /* power down the socket */ 2281 power = Pcic_read(ph, PCIC_PWRCTL); 2282 power &= ~PCIC_PWRCTL_OE; 2283 Pcic_write(ph, PCIC_PWRCTL, power); 2284 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2285 /* 2286 * wait 300ms until power fails (Tpf). 2287 */ 2288 delay(300 * 1000); 2289 } 2290 2291 /* 2292 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2293 * 2294 * This function detects whether a card is in the slot or not. 2295 * If a card is inserted, return 1. Otherwise, return 0. 2296 */ 2297 STATIC int 2298 pccbb_pcmcia_card_detect(pch) 2299 pcmcia_chipset_handle_t pch; 2300 { 2301 struct pcic_handle *ph = (struct pcic_handle *)pch; 2302 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2303 2304 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2305 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2306 } 2307 2308 #if 0 2309 STATIC int 2310 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2311 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2312 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2313 #endif 2314 /* 2315 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2316 * bus_size_t size, 2317 * struct pcmcia_mem_handle *pcmhp) 2318 * 2319 * This function only allocates memory region for pccard. This 2320 * function never maps the allocated region to pccard memory area. 2321 * 2322 * XXX: Why the argument of start address is not in? 2323 */ 2324 STATIC int 2325 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2326 pcmcia_chipset_handle_t pch; 2327 bus_size_t size; 2328 struct pcmcia_mem_handle *pcmhp; 2329 { 2330 struct pcic_handle *ph = (struct pcic_handle *)pch; 2331 bus_space_handle_t memh; 2332 bus_addr_t addr; 2333 bus_size_t sizepg; 2334 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2335 #if rbus 2336 rbus_tag_t rb; 2337 #endif 2338 2339 /* out of sc->memh, allocate as many pages as necessary */ 2340 2341 /* convert size to PCIC pages */ 2342 /* 2343 * This is not enough; when the requested region is on the page 2344 * boundaries, this may calculate wrong result. 2345 */ 2346 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2347 #if 0 2348 if (sizepg > PCIC_MAX_MEM_PAGES) { 2349 return 1; 2350 } 2351 #endif 2352 2353 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2354 return 1; 2355 } 2356 2357 addr = 0; /* XXX gcc -Wuninitialized */ 2358 2359 #if rbus 2360 rb = sc->sc_rbus_memt; 2361 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2362 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2363 &addr, &memh)) { 2364 return 1; 2365 } 2366 #else 2367 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2368 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2369 0, /* boundary */ 2370 0, /* flags */ 2371 &addr, &memh)) { 2372 return 1; 2373 } 2374 #endif 2375 2376 DPRINTF( 2377 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2378 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2379 2380 pcmhp->memt = sc->sc_memt; 2381 pcmhp->memh = memh; 2382 pcmhp->addr = addr; 2383 pcmhp->size = size; 2384 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2385 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2386 pcmhp->mhandle = 0; 2387 /* No offset??? Funny. */ 2388 2389 return 0; 2390 } 2391 2392 /* 2393 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2394 * struct pcmcia_mem_handle *pcmhp) 2395 * 2396 * This function release the memory space allocated by the function 2397 * pccbb_pcmcia_mem_alloc(). 2398 */ 2399 STATIC void 2400 pccbb_pcmcia_mem_free(pch, pcmhp) 2401 pcmcia_chipset_handle_t pch; 2402 struct pcmcia_mem_handle *pcmhp; 2403 { 2404 #if rbus 2405 struct pcic_handle *ph = (struct pcic_handle *)pch; 2406 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2407 2408 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2409 #else 2410 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2411 #endif 2412 } 2413 2414 /* 2415 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2416 * 2417 * This function release the memory space allocated by the function 2418 * pccbb_pcmcia_mem_alloc(). 2419 */ 2420 STATIC void 2421 pccbb_pcmcia_do_mem_map(ph, win) 2422 struct pcic_handle *ph; 2423 int win; 2424 { 2425 int regbase_win; 2426 bus_addr_t phys_addr; 2427 bus_addr_t phys_end; 2428 2429 #define PCIC_SMM_START_LOW 0 2430 #define PCIC_SMM_START_HIGH 1 2431 #define PCIC_SMM_STOP_LOW 2 2432 #define PCIC_SMM_STOP_HIGH 3 2433 #define PCIC_CMA_LOW 4 2434 #define PCIC_CMA_HIGH 5 2435 2436 u_int8_t start_low, start_high = 0; 2437 u_int8_t stop_low, stop_high; 2438 u_int8_t off_low, off_high; 2439 u_int8_t mem_window; 2440 int reg; 2441 2442 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2443 int mem8 = 2444 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2445 || (kind == PCMCIA_MEM_ATTR); 2446 2447 regbase_win = 0x10 + win * 0x08; 2448 2449 phys_addr = ph->mem[win].addr; 2450 phys_end = phys_addr + ph->mem[win].size; 2451 2452 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2453 phys_addr, phys_end, ph->mem[win].offset)); 2454 2455 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2456 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2457 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2458 2459 /* bit 19:12 */ 2460 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2461 /* bit 23:20 and bit 7 on */ 2462 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2463 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2464 /* bit 31:24, for 32-bit address */ 2465 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2466 2467 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2468 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2469 2470 if (((struct pccbb_softc *)ph-> 2471 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2472 Pcic_write(ph, 0x40 + win, mem_window); 2473 } 2474 2475 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2476 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2477 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2478 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2479 2480 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2481 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2482 2483 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2484 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2485 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2486 | ((kind == PCMCIA_MEM_ATTR) ? 2487 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2488 2489 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2490 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2491 2492 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2493 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2494 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2495 2496 #if defined CBB_DEBUG 2497 { 2498 int r1, r2, r3, r4, r5, r6, r7 = 0; 2499 2500 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2501 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2502 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2503 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2504 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2505 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2506 if (((struct pccbb_softc *)(ph-> 2507 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2508 r7 = Pcic_read(ph, 0x40 + win); 2509 } 2510 2511 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2512 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2513 if (((struct pccbb_softc *)(ph-> 2514 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2515 DPRINTF((" %02x", r7)); 2516 } 2517 DPRINTF(("\n")); 2518 } 2519 #endif 2520 } 2521 2522 /* 2523 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2524 * bus_addr_t card_addr, bus_size_t size, 2525 * struct pcmcia_mem_handle *pcmhp, 2526 * bus_addr_t *offsetp, int *windowp) 2527 * 2528 * This function maps memory space allocated by the function 2529 * pccbb_pcmcia_mem_alloc(). 2530 */ 2531 STATIC int 2532 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2533 pcmcia_chipset_handle_t pch; 2534 int kind; 2535 bus_addr_t card_addr; 2536 bus_size_t size; 2537 struct pcmcia_mem_handle *pcmhp; 2538 bus_addr_t *offsetp; 2539 int *windowp; 2540 { 2541 struct pcic_handle *ph = (struct pcic_handle *)pch; 2542 bus_addr_t busaddr; 2543 long card_offset; 2544 int win; 2545 2546 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2547 if ((ph->memalloc & (1 << win)) == 0) { 2548 ph->memalloc |= (1 << win); 2549 break; 2550 } 2551 } 2552 2553 if (win == PCIC_MEM_WINS) { 2554 return 1; 2555 } 2556 2557 *windowp = win; 2558 2559 /* XXX this is pretty gross */ 2560 2561 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2562 panic("pccbb_pcmcia_mem_map memt is bogus"); 2563 } 2564 2565 busaddr = pcmhp->addr; 2566 2567 /* 2568 * compute the address offset to the pcmcia address space for the 2569 * pcic. this is intentionally signed. The masks and shifts below 2570 * will cause TRT to happen in the pcic registers. Deal with making 2571 * sure the address is aligned, and return the alignment offset. 2572 */ 2573 2574 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2575 card_addr -= *offsetp; 2576 2577 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2578 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2579 (u_long) card_addr)); 2580 2581 /* 2582 * include the offset in the size, and decrement size by one, since 2583 * the hw wants start/stop 2584 */ 2585 size += *offsetp - 1; 2586 2587 card_offset = (((long)card_addr) - ((long)busaddr)); 2588 2589 ph->mem[win].addr = busaddr; 2590 ph->mem[win].size = size; 2591 ph->mem[win].offset = card_offset; 2592 ph->mem[win].kind = kind; 2593 2594 pccbb_pcmcia_do_mem_map(ph, win); 2595 2596 return 0; 2597 } 2598 2599 /* 2600 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2601 * int window) 2602 * 2603 * This function unmaps memory space which mapped by the function 2604 * pccbb_pcmcia_mem_map(). 2605 */ 2606 STATIC void 2607 pccbb_pcmcia_mem_unmap(pch, window) 2608 pcmcia_chipset_handle_t pch; 2609 int window; 2610 { 2611 struct pcic_handle *ph = (struct pcic_handle *)pch; 2612 int reg; 2613 2614 if (window >= PCIC_MEM_WINS) { 2615 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2616 } 2617 2618 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2619 reg &= ~(1 << window); 2620 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2621 2622 ph->memalloc &= ~(1 << window); 2623 } 2624 2625 #if defined PCCBB_PCMCIA_POLL 2626 struct pccbb_poll_str { 2627 void *arg; 2628 int (*func) __P((void *)); 2629 int level; 2630 struct pcic_handle *ph; 2631 int count; 2632 int num; 2633 }; 2634 2635 static struct pccbb_poll_str pccbb_poll[10]; 2636 static int pccbb_poll_n = 0; 2637 2638 static void pccbb_pcmcia_poll __P((void *arg)); 2639 2640 static void 2641 pccbb_pcmcia_poll(arg) 2642 void *arg; 2643 { 2644 struct pccbb_poll_str *poll = arg; 2645 struct pcic_handle *ph = poll->ph; 2646 struct pccbb_softc *sc = ph->sc; 2647 int s; 2648 u_int32_t spsr; /* socket present-state reg */ 2649 2650 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2651 switch (poll->level) { 2652 case IPL_NET: 2653 s = splnet(); 2654 break; 2655 case IPL_BIO: 2656 s = splbio(); 2657 break; 2658 case IPL_TTY: /* fallthrough */ 2659 default: 2660 s = spltty(); 2661 break; 2662 } 2663 2664 spsr = 2665 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2666 CB_SOCKET_STAT); 2667 2668 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2669 if (!(spsr & 0x40)) /* CINT low */ 2670 #else 2671 if (1) 2672 #endif 2673 { 2674 if ((*poll->func) (poll->arg) > 0) { 2675 ++poll->count; 2676 // printf("intr: reported from poller, 0x%x\n", spsr); 2677 #if defined LEVEL2 2678 } else { 2679 printf("intr: miss! 0x%x\n", spsr); 2680 #endif 2681 } 2682 } 2683 splx(s); 2684 } 2685 #endif /* defined CB_PCMCIA_POLL */ 2686 2687 /* 2688 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2689 * struct pcmcia_function *pf, 2690 * int ipl, 2691 * int (*func)(void *), 2692 * void *arg); 2693 * 2694 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2695 */ 2696 STATIC void * 2697 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2698 pcmcia_chipset_handle_t pch; 2699 struct pcmcia_function *pf; 2700 int ipl; 2701 int (*func) __P((void *)); 2702 void *arg; 2703 { 2704 struct pcic_handle *ph = (struct pcic_handle *)pch; 2705 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2706 2707 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2708 /* what should I do? */ 2709 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2710 DPRINTF( 2711 ("%s does not provide edge nor pulse interrupt\n", 2712 sc->sc_dev.dv_xname)); 2713 return NULL; 2714 } 2715 /* 2716 * XXX Noooooo! The interrupt flag must set properly!! 2717 * dumb pcmcia driver!! 2718 */ 2719 } 2720 2721 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2722 } 2723 2724 /* 2725 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2726 * void *ih) 2727 * 2728 * This function disables PC-Card interrupt. 2729 */ 2730 STATIC void 2731 pccbb_pcmcia_intr_disestablish(pch, ih) 2732 pcmcia_chipset_handle_t pch; 2733 void *ih; 2734 { 2735 struct pcic_handle *ph = (struct pcic_handle *)pch; 2736 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2737 2738 pccbb_intr_disestablish(sc, ih); 2739 } 2740 2741 #if rbus 2742 /* 2743 * static int 2744 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2745 * bus_addr_t addr, bus_size_t size, 2746 * bus_addr_t mask, bus_size_t align, 2747 * int flags, bus_addr_t *addrp; 2748 * bus_space_handle_t *bshp) 2749 * 2750 * This function allocates a portion of memory or io space for 2751 * clients. This function is called from CardBus card drivers. 2752 */ 2753 static int 2754 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2755 cardbus_chipset_tag_t ct; 2756 rbus_tag_t rb; 2757 bus_addr_t addr; 2758 bus_size_t size; 2759 bus_addr_t mask; 2760 bus_size_t align; 2761 int flags; 2762 bus_addr_t *addrp; 2763 bus_space_handle_t *bshp; 2764 { 2765 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2766 2767 DPRINTF( 2768 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2769 addr, size, mask, align)); 2770 2771 if (align == 0) { 2772 align = size; 2773 } 2774 2775 if (rb->rb_bt == sc->sc_memt) { 2776 if (align < 16) { 2777 return 1; 2778 } 2779 } else if (rb->rb_bt == sc->sc_iot) { 2780 if (align < 4) { 2781 return 1; 2782 } 2783 } else { 2784 DPRINTF( 2785 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2786 rb->rb_bt)); 2787 return 1; 2788 /* XXX: panic here? */ 2789 } 2790 2791 /* XXX: hack for avoiding ISA image */ 2792 if (mask < 0x3ff) { 2793 mask = 0x3ff; 2794 addr = 0x300; 2795 } 2796 2797 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2798 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2799 return 1; 2800 } 2801 2802 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2803 2804 return 0; 2805 } 2806 2807 /* 2808 * static int 2809 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2810 * bus_space_handle_t *bshp, bus_size_t size); 2811 * 2812 * This function is called from CardBus card drivers. 2813 */ 2814 static int 2815 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2816 cardbus_chipset_tag_t ct; 2817 rbus_tag_t rb; 2818 bus_space_handle_t bsh; 2819 bus_size_t size; 2820 { 2821 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2822 bus_space_tag_t bt = rb->rb_bt; 2823 2824 pccbb_close_win(sc, bt, bsh, size); 2825 2826 if (bt == sc->sc_memt) { 2827 } else if (bt == sc->sc_iot) { 2828 } else { 2829 return 1; 2830 /* XXX: panic here? */ 2831 } 2832 2833 return rbus_space_free(rb, bsh, size, NULL); 2834 } 2835 #endif /* rbus */ 2836 2837 #if rbus 2838 2839 static int 2840 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2841 struct pccbb_softc *sc; 2842 bus_space_tag_t bst; 2843 bus_addr_t addr; 2844 bus_size_t size; 2845 bus_space_handle_t bsh; 2846 int flags; 2847 { 2848 struct pccbb_win_chain_head *head; 2849 bus_addr_t align; 2850 2851 head = &sc->sc_iowindow; 2852 align = 0x04; 2853 if (sc->sc_memt == bst) { 2854 head = &sc->sc_memwindow; 2855 align = 0x1000; 2856 DPRINTF(("using memory window, %x %x %x\n\n", 2857 sc->sc_iot, sc->sc_memt, bst)); 2858 } 2859 2860 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2861 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2862 sc->sc_dev.dv_xname, 2863 (head == &sc->sc_memwindow) ? "mem" : "io"); 2864 } 2865 pccbb_winset(align, sc, bst); 2866 2867 return 0; 2868 } 2869 2870 static int 2871 pccbb_close_win(sc, bst, bsh, size) 2872 struct pccbb_softc *sc; 2873 bus_space_tag_t bst; 2874 bus_space_handle_t bsh; 2875 bus_size_t size; 2876 { 2877 struct pccbb_win_chain_head *head; 2878 bus_addr_t align; 2879 2880 head = &sc->sc_iowindow; 2881 align = 0x04; 2882 if (sc->sc_memt == bst) { 2883 head = &sc->sc_memwindow; 2884 align = 0x1000; 2885 } 2886 2887 if (pccbb_winlist_delete(head, bsh, size)) { 2888 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2889 sc->sc_dev.dv_xname, 2890 (head == &sc->sc_memwindow) ? "mem" : "io"); 2891 } 2892 pccbb_winset(align, sc, bst); 2893 2894 return 0; 2895 } 2896 2897 static int 2898 pccbb_winlist_insert(head, start, size, bsh, flags) 2899 struct pccbb_win_chain_head *head; 2900 bus_addr_t start; 2901 bus_size_t size; 2902 bus_space_handle_t bsh; 2903 int flags; 2904 { 2905 struct pccbb_win_chain *chainp, *elem; 2906 2907 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2908 M_NOWAIT)) == NULL) 2909 return 1; /* fail */ 2910 2911 elem->wc_start = start; 2912 elem->wc_end = start + (size - 1); 2913 elem->wc_handle = bsh; 2914 elem->wc_flags = flags; 2915 2916 if ((chainp = TAILQ_FIRST(head)) == NULL) { 2917 TAILQ_INSERT_HEAD(head, elem, wc_list); 2918 return 0; 2919 } 2920 2921 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2922 if (chainp->wc_end < start) 2923 continue; 2924 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2925 return 0; 2926 } 2927 2928 TAILQ_INSERT_TAIL(head, elem, wc_list); 2929 2930 return 0; 2931 } 2932 2933 static int 2934 pccbb_winlist_delete(head, bsh, size) 2935 struct pccbb_win_chain_head *head; 2936 bus_space_handle_t bsh; 2937 bus_size_t size; 2938 { 2939 struct pccbb_win_chain *chainp; 2940 2941 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2942 chainp = TAILQ_NEXT(chainp, wc_list)) { 2943 if (chainp->wc_handle != bsh) 2944 continue; 2945 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2946 printf("pccbb_winlist_delete: window 0x%lx size " 2947 "inconsistent: 0x%lx, 0x%lx\n", 2948 chainp->wc_start, 2949 chainp->wc_end - chainp->wc_start, 2950 size - 1); 2951 return 1; 2952 } 2953 2954 TAILQ_REMOVE(head, chainp, wc_list); 2955 free(chainp, M_DEVBUF); 2956 2957 return 0; 2958 } 2959 2960 return 1; /* fail: no candidate to remove */ 2961 } 2962 2963 static void 2964 pccbb_winset(align, sc, bst) 2965 bus_addr_t align; 2966 struct pccbb_softc *sc; 2967 bus_space_tag_t bst; 2968 { 2969 pci_chipset_tag_t pc; 2970 pcitag_t tag; 2971 bus_addr_t mask = ~(align - 1); 2972 struct { 2973 cardbusreg_t win_start; 2974 cardbusreg_t win_limit; 2975 int win_flags; 2976 } win[2]; 2977 struct pccbb_win_chain *chainp; 2978 int offs; 2979 2980 win[0].win_start = 0xffffffff; 2981 win[0].win_limit = 0; 2982 win[1].win_start = 0xffffffff; 2983 win[1].win_limit = 0; 2984 2985 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2986 offs = 0x2c; 2987 if (sc->sc_memt == bst) { 2988 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2989 offs = 0x1c; 2990 } 2991 2992 if (chainp != NULL) { 2993 win[0].win_start = chainp->wc_start & mask; 2994 win[0].win_limit = chainp->wc_end & mask; 2995 win[0].win_flags = chainp->wc_flags; 2996 chainp = TAILQ_NEXT(chainp, wc_list); 2997 } 2998 2999 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3000 if (win[1].win_start == 0xffffffff) { 3001 /* window 1 is not used */ 3002 if ((win[0].win_flags == chainp->wc_flags) && 3003 (win[0].win_limit + align >= 3004 (chainp->wc_start & mask))) { 3005 /* concatenate */ 3006 win[0].win_limit = chainp->wc_end & mask; 3007 } else { 3008 /* make new window */ 3009 win[1].win_start = chainp->wc_start & mask; 3010 win[1].win_limit = chainp->wc_end & mask; 3011 win[1].win_flags = chainp->wc_flags; 3012 } 3013 continue; 3014 } 3015 3016 /* Both windows are engaged. */ 3017 if (win[0].win_flags == win[1].win_flags) { 3018 /* same flags */ 3019 if (win[0].win_flags == chainp->wc_flags) { 3020 if (win[1].win_start - (win[0].win_limit + 3021 align) < 3022 (chainp->wc_start & mask) - 3023 ((chainp->wc_end & mask) + align)) { 3024 /* 3025 * merge window 0 and 1, and set win1 3026 * to chainp 3027 */ 3028 win[0].win_limit = win[1].win_limit; 3029 win[1].win_start = 3030 chainp->wc_start & mask; 3031 win[1].win_limit = 3032 chainp->wc_end & mask; 3033 } else { 3034 win[1].win_limit = 3035 chainp->wc_end & mask; 3036 } 3037 } else { 3038 /* different flags */ 3039 3040 /* concatenate win0 and win1 */ 3041 win[0].win_limit = win[1].win_limit; 3042 /* allocate win[1] to new space */ 3043 win[1].win_start = chainp->wc_start & mask; 3044 win[1].win_limit = chainp->wc_end & mask; 3045 win[1].win_flags = chainp->wc_flags; 3046 } 3047 } else { 3048 /* the flags of win[0] and win[1] is different */ 3049 if (win[0].win_flags == chainp->wc_flags) { 3050 win[0].win_limit = chainp->wc_end & mask; 3051 /* 3052 * XXX this creates overlapping windows, so 3053 * what should the poor bridge do if one is 3054 * cachable, and the other is not? 3055 */ 3056 printf("%s: overlapping windows\n", 3057 sc->sc_dev.dv_xname); 3058 } else { 3059 win[1].win_limit = chainp->wc_end & mask; 3060 } 3061 } 3062 } 3063 3064 pc = sc->sc_pc; 3065 tag = sc->sc_tag; 3066 pci_conf_write(pc, tag, offs, win[0].win_start); 3067 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3068 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3069 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3070 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3071 pci_conf_read(pc, tag, offs), 3072 pci_conf_read(pc, tag, offs + 4) + align, 3073 pci_conf_read(pc, tag, offs + 8), 3074 pci_conf_read(pc, tag, offs + 12) + align)); 3075 3076 if (bst == sc->sc_memt) { 3077 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3078 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3079 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3080 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3081 } 3082 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3083 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3084 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3085 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3086 } 3087 } 3088 } 3089 3090 #endif /* rbus */ 3091 3092 static void 3093 pccbb_powerhook(why, arg) 3094 int why; 3095 void *arg; 3096 { 3097 struct pccbb_softc *sc = arg; 3098 u_int32_t reg; 3099 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3100 bus_space_handle_t base_memh = sc->sc_base_memh; 3101 3102 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3103 3104 if (why == PWR_RESUME) { 3105 /* CSC Interrupt: Card detect interrupt on */ 3106 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3107 /* Card detect intr is turned on. */ 3108 reg |= CB_SOCKET_MASK_CD; 3109 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3110 /* reset interrupt */ 3111 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3112 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3113 3114 /* 3115 * check for card insertion or removal during suspend period. 3116 * XXX: the code can't cope with card swap (remove then insert). 3117 * how can we detect such situation? 3118 */ 3119 if (why == PWR_RESUME) 3120 (void)pccbbintr(sc); 3121 } 3122 } 3123
Indexes created Fri Sep 26 08:10:20 GMT 2025