pccbb.c revision 1.35
1 /* $NetBSD: pccbb.c,v 1.35 2000/03/14 10:26:10 enami Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 struct yenta_chipinfo *yc; 355 356 /* Loop over except the last default entry. */ 357 for (yc = yc_chipsets; yc < yc_chipsets + 358 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 359 if (pci_id != yc->yc_id) 360 break; 361 362 if (flagp != NULL) 363 *flagp = yc->yc_flags; 364 365 return (yc->yc_chiptype); 366 } 367 368 static void 369 pccbb_shutdown(void *arg) 370 { 371 struct pccbb_softc *sc = arg; 372 pcireg_t command; 373 374 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 375 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 376 0); 377 378 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 379 380 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 381 PCI_COMMAND_MASTER_ENABLE); 382 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 383 384 } 385 386 void 387 pccbbattach(parent, self, aux) 388 struct device *parent; 389 struct device *self; 390 void *aux; 391 { 392 struct pccbb_softc *sc = (void *)self; 393 struct pci_attach_args *pa = aux; 394 pci_chipset_tag_t pc = pa->pa_pc; 395 pcireg_t sock_base, busreg; 396 bus_addr_t sockbase; 397 char devinfo[256]; 398 int flags; 399 400 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 401 402 pci_devinfo(pa->pa_id, 0, 0, devinfo); 403 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 404 #ifdef CBB_DEBUG 405 printf(" (chipflags %x)", flags); 406 #endif 407 printf("\n"); 408 409 TAILQ_INIT(&sc->sc_memwindow); 410 TAILQ_INIT(&sc->sc_iowindow); 411 412 #if rbus 413 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 414 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 415 #endif /* rbus */ 416 417 sc->sc_base_memh = 0; 418 419 /* 420 * MAP socket registers and ExCA registers on memory-space 421 * When no valid address is set on socket base registers (on pci 422 * config space), get it not polite way. 423 */ 424 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 425 426 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 427 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 428 /* The address must be valid. */ 429 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 430 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 431 printf("%s: can't map socket base address 0x%x\n", 432 sc->sc_dev.dv_xname, sock_base); 433 /* 434 * I think it's funny: socket base registers must be 435 * mapped on memory space, but ... 436 */ 437 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 438 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 439 NULL)) { 440 printf("%s: can't map socket base address" 441 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 442 sockbase); 443 /* give up... allocate reg space via rbus. */ 444 sc->sc_base_memh = 0; 445 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 446 } 447 } else { 448 DPRINTF(("%s: socket base address 0x%lx\n", 449 sc->sc_dev.dv_xname, sockbase)); 450 } 451 } 452 453 sc->sc_mem_start = 0; /* XXX */ 454 sc->sc_mem_end = 0xffffffff; /* XXX */ 455 456 /* 457 * When interrupt isn't routed correctly, give up probing cbb and do 458 * not kill pcic-compatible port. 459 */ 460 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 461 printf("%s: NOT USED because of unconfigured interrupt\n", 462 sc->sc_dev.dv_xname); 463 return; 464 } 465 466 /* 467 * When bus number isn't set correctly, give up using 32-bit CardBus 468 * mode. 469 */ 470 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 471 #if notyet 472 if (((busreg >> 8) & 0xff) == 0) { 473 printf("%s: CardBus support disabled because of unconfigured bus number\n", 474 sc->sc_dev.dv_xname); 475 flags |= PCCBB_PCMCIA_16BITONLY; 476 } 477 #endif 478 479 /* pccbb_machdep.c end */ 480 481 #if defined CBB_DEBUG 482 { 483 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 484 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 485 intrname[pa->pa_intrpin], pa->pa_intrline); 486 } 487 #endif 488 489 /* setup softc */ 490 sc->sc_pc = pc; 491 sc->sc_iot = pa->pa_iot; 492 sc->sc_memt = pa->pa_memt; 493 sc->sc_dmat = pa->pa_dmat; 494 sc->sc_tag = pa->pa_tag; 495 sc->sc_function = pa->pa_function; 496 497 sc->sc_intrline = pa->pa_intrline; 498 sc->sc_intrtag = pa->pa_intrtag; 499 sc->sc_intrpin = pa->pa_intrpin; 500 501 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 502 503 shutdownhook_establish(pccbb_shutdown, sc); 504 505 #if __NetBSD_Version__ > 103060000 506 config_defer(self, pccbb_pci_callback); 507 #else 508 pccbb_pci_callback(self); 509 #endif 510 } 511 512 513 514 515 /* 516 * static void pccbb_pci_callback(struct device *self) 517 * 518 * The actual attach routine: get memory space for YENTA register 519 * space, setup YENTA register and route interrupt. 520 * 521 * This function should be deferred because this device may obtain 522 * memory space dynamically. This function must avoid obtaining 523 * memory area which has already kept for another device. Also, 524 * this function MUST be done before ISA attach process because this 525 * function kills pcic compatible port used by ISA pcic. 526 */ 527 static void 528 pccbb_pci_callback(self) 529 struct device *self; 530 { 531 struct pccbb_softc *sc = (void *)self; 532 pci_chipset_tag_t pc = sc->sc_pc; 533 bus_space_tag_t base_memt; 534 bus_space_handle_t base_memh; 535 u_int32_t maskreg; 536 pci_intr_handle_t ih; 537 const char *intrstr = NULL; 538 bus_addr_t sockbase; 539 struct cbslot_attach_args cba; 540 struct pcmciabus_attach_args paa; 541 struct cardslot_attach_args caa; 542 struct cardslot_softc *csc; 543 544 if (0 == sc->sc_base_memh) { 545 /* The socket registers aren't mapped correctly. */ 546 #if rbus 547 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 548 (sc->sc_chipset == CB_RX5C47X 549 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 550 0, &sockbase, &sc->sc_base_memh)) { 551 return; 552 } 553 sc->sc_base_memt = sc->sc_memt; 554 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 555 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 556 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 557 PCI_SOCKBASE))); 558 #else 559 sc->sc_base_memt = sc->sc_memt; 560 #if !defined CBB_PCI_BASE 561 #define CBB_PCI_BASE 0x20000000 562 #endif 563 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 564 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 565 /* cannot allocate memory space */ 566 return; 567 } 568 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 569 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 570 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 571 sc->sc_tag, PCI_SOCKBASE))); 572 #endif 573 } 574 575 /* bus bridge initialization */ 576 pccbb_chipinit(sc); 577 578 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 579 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 580 581 /* CSC Interrupt: Card detect interrupt on */ 582 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 583 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 584 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 585 /* reset interrupt */ 586 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 587 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 588 589 /* Map and establish the interrupt. */ 590 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 591 sc->sc_intrline, &ih)) { 592 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 593 return; 594 } 595 intrstr = pci_intr_string(pc, ih); 596 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 597 598 if (sc->sc_ih == NULL) { 599 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 600 if (intrstr != NULL) { 601 printf(" at %s", intrstr); 602 } 603 printf("\n"); 604 return; 605 } 606 607 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 608 powerhook_establish(pccbb_powerhook, sc); 609 610 { 611 u_int32_t sockstat = 612 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 613 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 614 sc->sc_flags |= CBB_CARDEXIST; 615 } 616 } 617 618 /* 619 * attach cardbus 620 */ 621 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 622 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 623 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 624 625 /* initialize cbslot_attach */ 626 cba.cba_busname = "cardbus"; 627 cba.cba_iot = sc->sc_iot; 628 cba.cba_memt = sc->sc_memt; 629 cba.cba_dmat = sc->sc_dmat; 630 cba.cba_function = 0; 631 cba.cba_bus = (busreg >> 8) & 0x0ff; 632 cba.cba_cc = (void *)sc; 633 cba.cba_cf = &pccbb_funcs; 634 cba.cba_intrline = sc->sc_intrline; 635 636 #if rbus 637 cba.cba_rbus_iot = sc->sc_rbus_iot; 638 cba.cba_rbus_memt = sc->sc_rbus_memt; 639 #endif 640 641 cba.cba_cacheline = PCI_CACHELINE(bhlc); 642 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 643 644 printf("%s: cacheline 0x%x lattimer 0x%x\n", 645 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 646 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 647 busreg); 648 #if defined SHOW_REGS 649 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 650 sc->sc_base_memh); 651 #endif 652 } 653 654 pccbb_pcmcia_attach_setup(sc, &paa); 655 caa.caa_cb_attach = NULL; 656 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 657 caa.caa_cb_attach = &cba; 658 } 659 caa.caa_16_attach = &paa; 660 caa.caa_ph = &sc->sc_pcmcia_h; 661 662 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 663 DPRINTF(("pccbbattach: found cardslot\n")); 664 sc->sc_csc = csc; 665 } 666 667 return; 668 } 669 670 671 672 673 674 /* 675 * static void pccbb_chipinit(struct pccbb_softc *sc) 676 * 677 * This function initialize YENTA chip registers listed below: 678 * 1) PCI command reg, 679 * 2) PCI and CardBus latency timer, 680 * 3) disable legacy (PCIC-compatible) io, 681 * 4) route PCI interrupt, 682 * 5) close all memory and io windows. 683 */ 684 static void 685 pccbb_chipinit(sc) 686 struct pccbb_softc *sc; 687 { 688 pci_chipset_tag_t pc = sc->sc_pc; 689 pcitag_t tag = sc->sc_tag; 690 pcireg_t reg; 691 692 /* 693 * Set PCI command reg. 694 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 695 */ 696 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 697 /* I believe it is harmless. */ 698 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 699 PCI_COMMAND_MASTER_ENABLE); 700 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 701 702 /* 703 * Set CardBus latency timer. 704 */ 705 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 706 if (PCI_CB_LATENCY(reg) < 0x20) { 707 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 708 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 709 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 710 } 711 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 712 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 713 714 /* 715 * Set PCI latency timer. 716 */ 717 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 718 if (PCI_LATTIMER(reg) < 0x10) { 719 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 720 reg |= (0x10 << PCI_LATTIMER_SHIFT); 721 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 722 } 723 DPRINTF(("PCI latency timer 0x%x (%x)\n", 724 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 725 726 /* Disable legacy register mapping. */ 727 switch (sc->sc_chipset) { 728 case CB_RX5C46X: /* fallthrough */ 729 #if 0 730 case CB_RX5C47X: 731 #endif 732 /* 733 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 734 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 735 * CardBus bridges have special bits on Bridge control reg (addr 736 * 0x3e on PCI config space). 737 */ 738 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 739 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 740 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 741 break; 742 743 default: 744 /* XXX I don't know proper way to kill legacy I/O. */ 745 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 746 break; 747 } 748 749 /* Route functional interrupts to PCI. */ 750 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 751 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 752 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 753 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 754 755 switch (sc->sc_chipset) { 756 case CB_TI113X: 757 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 758 /* This bit is shared, but may read as 0 on some chips, so set 759 it explicitly on both functions. */ 760 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 761 /* CSC intr enable */ 762 reg |= PCI113X_CBCTRL_PCI_CSC; 763 /* functional intr prohibit */ 764 reg &= ~PCI113X_CBCTRL_PCI_INTR; 765 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 766 break; 767 768 case CB_TOPIC95B: 769 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 770 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 771 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 772 773 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 774 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 775 sc->sc_dev.dv_xname, reg)); 776 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 777 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 778 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 779 DPRINTF(("0x%x\n", reg)); 780 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 781 break; 782 } 783 784 /* Close all memory and I/O windows. */ 785 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 786 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 787 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 788 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 789 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 790 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 791 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 792 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 793 } 794 795 796 797 798 /* 799 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 800 * struct pcmciabus_attach_args *paa) 801 * 802 * This function attaches 16-bit PCcard bus. 803 */ 804 STATIC void 805 pccbb_pcmcia_attach_setup(sc, paa) 806 struct pccbb_softc *sc; 807 struct pcmciabus_attach_args *paa; 808 { 809 struct pcic_handle *ph = &sc->sc_pcmcia_h; 810 #if rbus 811 rbus_tag_t rb; 812 #endif 813 814 /* initialize pcmcia part in pccbb_softc */ 815 ph->ph_parent = (struct device *)sc; 816 ph->sock = sc->sc_function; 817 ph->flags = 0; 818 ph->shutdown = 0; 819 ph->ih_irq = sc->sc_intrline; 820 ph->ph_bus_t = sc->sc_base_memt; 821 ph->ph_bus_h = sc->sc_base_memh; 822 ph->ph_read = pccbb_pcmcia_read; 823 ph->ph_write = pccbb_pcmcia_write; 824 sc->sc_pct = &pccbb_pcmcia_funcs; 825 826 /* 827 * We need to do a few things here: 828 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 829 * setting the IRQ numbers to 0. 830 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 831 * routing of CSC interrupts (e.g. card removal) to PCI while in 832 * PCMCIA mode. We just leave this set all the time. 833 * 3) Enable card insertion/removal interrupts in case the chip also 834 * needs that while in PCMCIA mode. 835 * 4) Clear any pending CSC interrupt. 836 */ 837 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 838 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 839 Pcic_read(ph, PCIC_CSC); 840 841 /* initialize pcmcia bus attachment */ 842 paa->paa_busname = "pcmcia"; 843 paa->pct = sc->sc_pct; 844 paa->pch = ph; 845 paa->iobase = 0; /* I don't use them */ 846 paa->iosize = 0; 847 #if rbus 848 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 849 paa->iobase = rb->rb_start + rb->rb_offset; 850 paa->iosize = rb->rb_end - rb->rb_start; 851 #endif 852 853 return; 854 } 855 856 #if 0 857 STATIC void 858 pccbb_pcmcia_attach_card(ph) 859 struct pcic_handle *ph; 860 { 861 if (ph->flags & PCIC_FLAG_CARDP) { 862 panic("pccbb_pcmcia_attach_card: already attached"); 863 } 864 865 /* call the MI attach function */ 866 pcmcia_card_attach(ph->pcmcia); 867 868 ph->flags |= PCIC_FLAG_CARDP; 869 } 870 871 STATIC void 872 pccbb_pcmcia_detach_card(ph, flags) 873 struct pcic_handle *ph; 874 int flags; 875 { 876 if (!(ph->flags & PCIC_FLAG_CARDP)) { 877 panic("pccbb_pcmcia_detach_card: already detached"); 878 } 879 880 ph->flags &= ~PCIC_FLAG_CARDP; 881 882 /* call the MI detach function */ 883 pcmcia_card_detach(ph->pcmcia, flags); 884 } 885 #endif 886 887 /* 888 * int pccbbintr(arg) 889 * void *arg; 890 * This routine handles the interrupt from Yenta PCI-CardBus bridge 891 * itself. 892 */ 893 int 894 pccbbintr(arg) 895 void *arg; 896 { 897 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 898 u_int32_t sockevent, sockstate; 899 bus_space_tag_t memt = sc->sc_base_memt; 900 bus_space_handle_t memh = sc->sc_base_memh; 901 struct pcic_handle *ph = &sc->sc_pcmcia_h; 902 903 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 904 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 905 Pcic_read(ph, PCIC_CSC); 906 907 if (sockevent == 0) { 908 /* This intr is not for me: it may be for my child devices. */ 909 return (pccbbintr_function(sc)); 910 } 911 912 if (sockevent & CB_SOCKET_EVENT_CD) { 913 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 914 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 915 /* A card should be removed. */ 916 if (sc->sc_flags & CBB_CARDEXIST) { 917 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 918 sockevent)); 919 DPRINTF((" card removed, 0x%08x\n", sockstate)); 920 sc->sc_flags &= ~CBB_CARDEXIST; 921 if (sc->sc_csc->sc_status & 922 CARDSLOT_STATUS_CARD_16) { 923 #if 0 924 struct pcic_handle *ph = 925 &sc->sc_pcmcia_h; 926 927 pcmcia_card_deactivate(ph->pcmcia); 928 pccbb_pcmcia_socket_disable(ph); 929 pccbb_pcmcia_detach_card(ph, 930 DETACH_FORCE); 931 #endif 932 cardslot_event_throw(sc->sc_csc, 933 CARDSLOT_EVENT_REMOVAL_16); 934 } else if (sc->sc_csc->sc_status & 935 CARDSLOT_STATUS_CARD_CB) { 936 /* Cardbus intr removed */ 937 cardslot_event_throw(sc->sc_csc, 938 CARDSLOT_EVENT_REMOVAL_CB); 939 } 940 } 941 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 942 /* 943 * The pccbbintr may called from powerdown hook when 944 * the system resumed, to detect the card 945 * insertion/removal during suspension. 946 */ 947 (sc->sc_flags & CBB_CARDEXIST) == 0) { 948 if (sc->sc_flags & CBB_INSERTING) { 949 untimeout(pci113x_insert, sc); 950 } 951 timeout(pci113x_insert, sc, hz / 10); 952 sc->sc_flags |= CBB_INSERTING; 953 } 954 } 955 956 return (1); 957 } 958 959 /* 960 * static int pccbbintr_function(struct pccbb_softc *sc) 961 * 962 * This function calls each interrupt handler registered at the 963 * bridge. The interrupt handlers are called in registered order. 964 */ 965 static int 966 pccbbintr_function(sc) 967 struct pccbb_softc *sc; 968 { 969 int retval = 0, val; 970 struct pccbb_intrhand_list *pil; 971 972 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 973 val = (*pil->pil_func) (pil->pil_arg); 974 retval = retval == 1 ? 1 : 975 retval == 0 ? val : val != 0 ? val : retval; 976 } 977 978 return retval; 979 } 980 981 static void 982 pci113x_insert(arg) 983 void *arg; 984 { 985 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 986 u_int32_t sockevent, sockstate; 987 988 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 989 CB_SOCKET_EVENT); 990 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 991 CB_SOCKET_STAT); 992 993 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 994 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 995 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 996 sc->sc_flags |= CBB_CARDEXIST; 997 /* call pccard interrupt handler here */ 998 if (sockstate & CB_SOCKET_STAT_16BIT) { 999 /* 16-bit card found */ 1000 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1001 cardslot_event_throw(sc->sc_csc, 1002 CARDSLOT_EVENT_INSERTION_16); 1003 } else if (sockstate & CB_SOCKET_STAT_CB) { 1004 /* cardbus card found */ 1005 /* cardbus_attach_card(sc->sc_csc); */ 1006 cardslot_event_throw(sc->sc_csc, 1007 CARDSLOT_EVENT_INSERTION_CB); 1008 } else { 1009 /* who are you? */ 1010 } 1011 } else { 1012 timeout(pci113x_insert, sc, hz / 10); 1013 } 1014 } 1015 1016 #define PCCBB_PCMCIA_OFFSET 0x800 1017 static u_int8_t 1018 pccbb_pcmcia_read(ph, reg) 1019 struct pcic_handle *ph; 1020 int reg; 1021 { 1022 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1023 PCCBB_PCMCIA_OFFSET + reg); 1024 } 1025 1026 static void 1027 pccbb_pcmcia_write(ph, reg, val) 1028 struct pcic_handle *ph; 1029 int reg; 1030 u_int8_t val; 1031 { 1032 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1033 val); 1034 } 1035 1036 /* 1037 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1038 */ 1039 STATIC int 1040 pccbb_ctrl(ct, command) 1041 cardbus_chipset_tag_t ct; 1042 int command; 1043 { 1044 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1045 1046 switch (command) { 1047 case CARDBUS_CD: 1048 if (2 == pccbb_detect_card(sc)) { 1049 int retval = 0; 1050 int status = cb_detect_voltage(sc); 1051 if (PCCARD_VCC_5V & status) { 1052 retval |= CARDBUS_5V_CARD; 1053 } 1054 if (PCCARD_VCC_3V & status) { 1055 retval |= CARDBUS_3V_CARD; 1056 } 1057 if (PCCARD_VCC_XV & status) { 1058 retval |= CARDBUS_XV_CARD; 1059 } 1060 if (PCCARD_VCC_YV & status) { 1061 retval |= CARDBUS_YV_CARD; 1062 } 1063 return retval; 1064 } else { 1065 return 0; 1066 } 1067 break; 1068 case CARDBUS_RESET: 1069 return cb_reset(sc); 1070 break; 1071 case CARDBUS_IO_ENABLE: /* fallthrough */ 1072 case CARDBUS_IO_DISABLE: /* fallthrough */ 1073 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1074 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1075 case CARDBUS_BM_ENABLE: /* fallthrough */ 1076 case CARDBUS_BM_DISABLE: /* fallthrough */ 1077 return pccbb_cardenable(sc, command); 1078 break; 1079 } 1080 1081 return 0; 1082 } 1083 1084 /* 1085 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1086 * This function returns true when it succeeds and returns false when 1087 * it fails. 1088 */ 1089 STATIC int 1090 pccbb_power(ct, command) 1091 cardbus_chipset_tag_t ct; 1092 int command; 1093 { 1094 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1095 1096 u_int32_t status, sock_ctrl; 1097 bus_space_tag_t memt = sc->sc_base_memt; 1098 bus_space_handle_t memh = sc->sc_base_memh; 1099 1100 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1101 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1102 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1103 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1104 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1105 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1106 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1107 "UNKNOWN", 1108 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1109 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1110 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1111 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1112 "UNKNOWN", command)); 1113 1114 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1115 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1116 1117 switch (command & CARDBUS_VCCMASK) { 1118 case CARDBUS_VCC_UC: 1119 break; 1120 case CARDBUS_VCC_5V: 1121 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1122 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1123 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1124 } else { 1125 printf("%s: BAD voltage request: no 5 V card\n", 1126 sc->sc_dev.dv_xname); 1127 } 1128 break; 1129 case CARDBUS_VCC_3V: 1130 if (CB_SOCKET_STAT_3VCARD & status) { 1131 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1132 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1133 } else { 1134 printf("%s: BAD voltage request: no 3.3 V card\n", 1135 sc->sc_dev.dv_xname); 1136 } 1137 break; 1138 case CARDBUS_VCC_0V: 1139 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1140 break; 1141 default: 1142 return 0; /* power NEVER changed */ 1143 break; 1144 } 1145 1146 switch (command & CARDBUS_VPPMASK) { 1147 case CARDBUS_VPP_UC: 1148 break; 1149 case CARDBUS_VPP_0V: 1150 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1151 break; 1152 case CARDBUS_VPP_VCC: 1153 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1154 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1155 break; 1156 case CARDBUS_VPP_12V: 1157 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1158 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1159 break; 1160 } 1161 1162 #if 0 1163 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1164 #endif 1165 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1166 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1167 1168 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1169 /* 1170 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1171 * time is 20 ms, some PC-Card bridge requires longer duration. 1172 */ 1173 delay(200 * 1000); 1174 1175 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1176 printf 1177 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1178 sc->sc_dev.dv_xname, sock_ctrl, status); 1179 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1180 (command & CARDBUS_VCCMASK) == 1181 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1182 CARDBUS_VCCMASK) == 1183 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1184 CARDBUS_VCCMASK) == 1185 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1186 CARDBUS_VCCMASK) == 1187 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1188 CARDBUS_VCCMASK) == 1189 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1190 CARDBUS_VCCMASK) == 1191 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1192 (command & CARDBUS_VPPMASK) == 1193 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1194 CARDBUS_VPPMASK) == 1195 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1196 CARDBUS_VPPMASK) == 1197 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1198 CARDBUS_VPPMASK) == 1199 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1200 #if 0 1201 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1202 u_int32_t force = 1203 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1204 /* Reset Bad Vcc request */ 1205 force &= ~CB_SOCKET_FORCE_BADVCC; 1206 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1207 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1208 CB_SOCKET_STAT)); 1209 return 1; 1210 } 1211 #endif 1212 return 0; 1213 } 1214 return 1; /* power changed correctly */ 1215 } 1216 1217 #if defined CB_PCMCIA_POLL 1218 struct cb_poll_str { 1219 void *arg; 1220 int (*func) __P((void *)); 1221 int level; 1222 pccard_chipset_tag_t ct; 1223 int count; 1224 }; 1225 1226 static struct cb_poll_str cb_poll[10]; 1227 static int cb_poll_n = 0; 1228 1229 static void cb_pcmcia_poll __P((void *arg)); 1230 1231 static void 1232 cb_pcmcia_poll(arg) 1233 void *arg; 1234 { 1235 struct cb_poll_str *poll = arg; 1236 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1237 struct pccbb_softc *sc = psc->cpc_parent; 1238 int s; 1239 u_int32_t spsr; /* socket present-state reg */ 1240 1241 timeout(cb_pcmcia_poll, arg, hz / 10); 1242 switch (poll->level) { 1243 case IPL_NET: 1244 s = splnet(); 1245 break; 1246 case IPL_BIO: 1247 s = splbio(); 1248 break; 1249 case IPL_TTY: /* fallthrough */ 1250 default: 1251 s = spltty(); 1252 break; 1253 } 1254 1255 spsr = 1256 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1257 CB_SOCKET_STAT); 1258 1259 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1260 if (!(spsr & 0x40)) { /* CINT low */ 1261 #else 1262 if (1) { 1263 #endif 1264 if ((*poll->func) (poll->arg) == 1) { 1265 ++poll->count; 1266 printf("intr: reported from poller, 0x%x\n", spsr); 1267 #if defined LEVEL2 1268 } else { 1269 printf("intr: miss! 0x%x\n", spsr); 1270 #endif 1271 } 1272 } 1273 splx(s); 1274 } 1275 #endif /* defined CB_PCMCIA_POLL */ 1276 1277 /* 1278 * static int pccbb_detect_card(struct pccbb_softc *sc) 1279 * return value: 0 if no card exists. 1280 * 1 if 16-bit card exists. 1281 * 2 if cardbus card exists. 1282 */ 1283 static int 1284 pccbb_detect_card(sc) 1285 struct pccbb_softc *sc; 1286 { 1287 bus_space_handle_t base_memh = sc->sc_base_memh; 1288 bus_space_tag_t base_memt = sc->sc_base_memt; 1289 u_int32_t sockstat = 1290 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1291 int retval = 0; 1292 1293 /* CD1 and CD2 asserted */ 1294 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1295 /* card must be present */ 1296 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1297 /* NOTACARD DEASSERTED */ 1298 if (CB_SOCKET_STAT_CB & sockstat) { 1299 /* CardBus mode */ 1300 retval = 2; 1301 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1302 /* 16-bit mode */ 1303 retval = 1; 1304 } 1305 } 1306 } 1307 return retval; 1308 } 1309 1310 /* 1311 * STATIC int cb_reset(struct pccbb_softc *sc) 1312 * This function resets CardBus card. 1313 */ 1314 STATIC int 1315 cb_reset(sc) 1316 struct pccbb_softc *sc; 1317 { 1318 /* 1319 * Reset Assert at least 20 ms 1320 * Some machines request longer duration. 1321 */ 1322 int reset_duration = 1323 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1324 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1325 1326 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1327 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1328 delay(reset_duration); 1329 1330 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1331 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1332 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1333 delay(reset_duration); 1334 } 1335 /* No card found on the slot. Keep Reset. */ 1336 return 1; 1337 } 1338 1339 /* 1340 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1341 * This function detect card Voltage. 1342 */ 1343 STATIC int 1344 cb_detect_voltage(sc) 1345 struct pccbb_softc *sc; 1346 { 1347 u_int32_t psr; /* socket present-state reg */ 1348 bus_space_tag_t iot = sc->sc_base_memt; 1349 bus_space_handle_t ioh = sc->sc_base_memh; 1350 int vol = PCCARD_VCC_UKN; /* set 0 */ 1351 1352 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1353 1354 if (0x400u & psr) { 1355 vol |= PCCARD_VCC_5V; 1356 } 1357 if (0x800u & psr) { 1358 vol |= PCCARD_VCC_3V; 1359 } 1360 1361 return vol; 1362 } 1363 1364 STATIC int 1365 cbbprint(aux, pcic) 1366 void *aux; 1367 const char *pcic; 1368 { 1369 /* 1370 struct cbslot_attach_args *cba = aux; 1371 1372 if (cba->cba_slot >= 0) { 1373 printf(" slot %d", cba->cba_slot); 1374 } 1375 */ 1376 return UNCONF; 1377 } 1378 1379 /* 1380 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1381 * This function enables and disables the card 1382 */ 1383 STATIC int 1384 pccbb_cardenable(sc, function) 1385 struct pccbb_softc *sc; 1386 int function; 1387 { 1388 u_int32_t command = 1389 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1390 1391 DPRINTF(("pccbb_cardenable:")); 1392 switch (function) { 1393 case CARDBUS_IO_ENABLE: 1394 command |= PCI_COMMAND_IO_ENABLE; 1395 break; 1396 case CARDBUS_IO_DISABLE: 1397 command &= ~PCI_COMMAND_IO_ENABLE; 1398 break; 1399 case CARDBUS_MEM_ENABLE: 1400 command |= PCI_COMMAND_MEM_ENABLE; 1401 break; 1402 case CARDBUS_MEM_DISABLE: 1403 command &= ~PCI_COMMAND_MEM_ENABLE; 1404 break; 1405 case CARDBUS_BM_ENABLE: 1406 command |= PCI_COMMAND_MASTER_ENABLE; 1407 break; 1408 case CARDBUS_BM_DISABLE: 1409 command &= ~PCI_COMMAND_MASTER_ENABLE; 1410 break; 1411 default: 1412 return 0; 1413 } 1414 1415 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1416 DPRINTF((" command reg 0x%x\n", command)); 1417 return 1; 1418 } 1419 1420 #if !rbus 1421 /* 1422 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1423 */ 1424 static int 1425 pccbb_io_open(ct, win, start, end) 1426 cardbus_chipset_tag_t ct; 1427 int win; 1428 u_int32_t start, end; 1429 { 1430 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1431 int basereg; 1432 int limitreg; 1433 1434 if ((win < 0) || (win > 2)) { 1435 #if defined DIAGNOSTIC 1436 printf("cardbus_io_open: window out of range %d\n", win); 1437 #endif 1438 return 0; 1439 } 1440 1441 basereg = win * 8 + 0x2c; 1442 limitreg = win * 8 + 0x30; 1443 1444 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1445 start, basereg, end, limitreg)); 1446 1447 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1448 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1449 return 1; 1450 } 1451 1452 /* 1453 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1454 */ 1455 static int 1456 pccbb_io_close(ct, win) 1457 cardbus_chipset_tag_t ct; 1458 int win; 1459 { 1460 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1461 int basereg; 1462 int limitreg; 1463 1464 if ((win < 0) || (win > 2)) { 1465 #if defined DIAGNOSTIC 1466 printf("cardbus_io_close: window out of range %d\n", win); 1467 #endif 1468 return 0; 1469 } 1470 1471 basereg = win * 8 + 0x2c; 1472 limitreg = win * 8 + 0x30; 1473 1474 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1475 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1476 return 1; 1477 } 1478 1479 /* 1480 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1481 */ 1482 static int 1483 pccbb_mem_open(ct, win, start, end) 1484 cardbus_chipset_tag_t ct; 1485 int win; 1486 u_int32_t start, end; 1487 { 1488 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1489 int basereg; 1490 int limitreg; 1491 1492 if ((win < 0) || (win > 2)) { 1493 #if defined DIAGNOSTIC 1494 printf("cardbus_mem_open: window out of range %d\n", win); 1495 #endif 1496 return 0; 1497 } 1498 1499 basereg = win * 8 + 0x1c; 1500 limitreg = win * 8 + 0x20; 1501 1502 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1503 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1504 return 1; 1505 } 1506 1507 /* 1508 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1509 */ 1510 static int 1511 pccbb_mem_close(ct, win) 1512 cardbus_chipset_tag_t ct; 1513 int win; 1514 { 1515 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1516 int basereg; 1517 int limitreg; 1518 1519 if ((win < 0) || (win > 2)) { 1520 #if defined DIAGNOSTIC 1521 printf("cardbus_mem_close: window out of range %d\n", win); 1522 #endif 1523 return 0; 1524 } 1525 1526 basereg = win * 8 + 0x1c; 1527 limitreg = win * 8 + 0x20; 1528 1529 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1530 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1531 return 1; 1532 } 1533 #endif 1534 1535 /* 1536 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1537 * int irq, 1538 * int level, 1539 * int (* func) __P((void *)), 1540 * void *arg) 1541 * 1542 * This function registers an interrupt handler at the bridge, in 1543 * order not to call the interrupt handlers of child devices when 1544 * a card-deletion interrupt occurs. 1545 * 1546 * The arguments irq and level are not used. 1547 */ 1548 static void * 1549 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1550 cardbus_chipset_tag_t ct; 1551 int irq, level; 1552 int (*func) __P((void *)); 1553 void *arg; 1554 { 1555 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1556 1557 return pccbb_intr_establish(sc, irq, level, func, arg); 1558 } 1559 1560 1561 /* 1562 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1563 * void *ih) 1564 * 1565 * This function removes an interrupt handler pointed by ih. 1566 */ 1567 static void 1568 pccbb_cb_intr_disestablish(ct, ih) 1569 cardbus_chipset_tag_t ct; 1570 void *ih; 1571 { 1572 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1573 1574 pccbb_intr_disestablish(sc, ih); 1575 } 1576 1577 1578 /* 1579 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1580 * int irq, 1581 * int level, 1582 * int (* func) __P((void *)), 1583 * void *arg) 1584 * 1585 * This function registers an interrupt handler at the bridge, in 1586 * order not to call the interrupt handlers of child devices when 1587 * a card-deletion interrupt occurs. 1588 * 1589 * The arguments irq and level are not used. 1590 */ 1591 static void * 1592 pccbb_intr_establish(sc, irq, level, func, arg) 1593 struct pccbb_softc *sc; 1594 int irq, level; 1595 int (*func) __P((void *)); 1596 void *arg; 1597 { 1598 struct pccbb_intrhand_list *pil, *newpil; 1599 1600 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1601 1602 if (sc->sc_pil == NULL) { 1603 /* initialize bridge intr routing */ 1604 1605 switch (sc->sc_chipset) { 1606 case CB_TI113X: 1607 { 1608 pcireg_t cbctrl = 1609 pci_conf_read(sc->sc_pc, sc->sc_tag, 1610 PCI_CBCTRL); 1611 /* functional intr enabled */ 1612 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1613 pci_conf_write(sc->sc_pc, sc->sc_tag, 1614 PCI_CBCTRL, cbctrl); 1615 break; 1616 } 1617 default: 1618 break; 1619 } 1620 } 1621 1622 /* 1623 * Allocate a room for interrupt handler structure. 1624 */ 1625 if (NULL == (newpil = 1626 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1627 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1628 return NULL; 1629 } 1630 1631 newpil->pil_func = func; 1632 newpil->pil_arg = arg; 1633 newpil->pil_next = NULL; 1634 1635 if (sc->sc_pil == NULL) { 1636 sc->sc_pil = newpil; 1637 } else { 1638 for (pil = sc->sc_pil; pil->pil_next != NULL; 1639 pil = pil->pil_next); 1640 pil->pil_next = newpil; 1641 } 1642 1643 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1644 1645 return newpil; 1646 } 1647 1648 /* 1649 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1650 * void *ih) 1651 * 1652 * This function removes an interrupt handler pointed by ih. 1653 */ 1654 static void 1655 pccbb_intr_disestablish(sc, ih) 1656 struct pccbb_softc *sc; 1657 void *ih; 1658 { 1659 struct pccbb_intrhand_list *pil, **pil_prev; 1660 1661 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1662 1663 pil_prev = &sc->sc_pil; 1664 1665 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1666 if (pil == ih) { 1667 *pil_prev = pil->pil_next; 1668 free(pil, M_DEVBUF); 1669 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1670 break; 1671 } 1672 pil_prev = &pil->pil_next; 1673 } 1674 1675 if (sc->sc_pil == NULL) { 1676 /* No interrupt handlers */ 1677 1678 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1679 1680 switch (sc->sc_chipset) { 1681 case CB_TI113X: 1682 { 1683 pcireg_t cbctrl = 1684 pci_conf_read(sc->sc_pc, sc->sc_tag, 1685 PCI_CBCTRL); 1686 /* functional intr disabled */ 1687 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1688 pci_conf_write(sc->sc_pc, sc->sc_tag, 1689 PCI_CBCTRL, cbctrl); 1690 break; 1691 } 1692 default: 1693 break; 1694 } 1695 } 1696 } 1697 1698 #if defined SHOW_REGS 1699 static void 1700 cb_show_regs(pc, tag, memt, memh) 1701 pci_chipset_tag_t pc; 1702 pcitag_t tag; 1703 bus_space_tag_t memt; 1704 bus_space_handle_t memh; 1705 { 1706 int i; 1707 printf("PCI config regs:"); 1708 for (i = 0; i < 0x50; i += 4) { 1709 if (i % 16 == 0) { 1710 printf("\n 0x%02x:", i); 1711 } 1712 printf(" %08x", pci_conf_read(pc, tag, i)); 1713 } 1714 for (i = 0x80; i < 0xb0; i += 4) { 1715 if (i % 16 == 0) { 1716 printf("\n 0x%02x:", i); 1717 } 1718 printf(" %08x", pci_conf_read(pc, tag, i)); 1719 } 1720 1721 if (memh == 0) { 1722 printf("\n"); 1723 return; 1724 } 1725 1726 printf("\nsocket regs:"); 1727 for (i = 0; i <= 0x10; i += 0x04) { 1728 printf(" %08x", bus_space_read_4(memt, memh, i)); 1729 } 1730 printf("\nExCA regs:"); 1731 for (i = 0; i < 0x08; ++i) { 1732 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1733 } 1734 printf("\n"); 1735 return; 1736 } 1737 #endif 1738 1739 /* 1740 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1741 * int busno, int devno, int function) 1742 * This is the function to make a tag to access config space of 1743 * a CardBus Card. It works same as pci_conf_read. 1744 */ 1745 static cardbustag_t 1746 pccbb_make_tag(cc, busno, devno, function) 1747 cardbus_chipset_tag_t cc; 1748 int busno, devno, function; 1749 { 1750 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1751 1752 return pci_make_tag(sc->sc_pc, busno, devno, function); 1753 } 1754 1755 static void 1756 pccbb_free_tag(cc, tag) 1757 cardbus_chipset_tag_t cc; 1758 cardbustag_t tag; 1759 { 1760 } 1761 1762 /* 1763 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1764 * cardbustag_t tag, int offset) 1765 * This is the function to read the config space of a CardBus Card. 1766 * It works same as pci_conf_read. 1767 */ 1768 static cardbusreg_t 1769 pccbb_conf_read(cc, tag, offset) 1770 cardbus_chipset_tag_t cc; 1771 cardbustag_t tag; 1772 int offset; /* register offset */ 1773 { 1774 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1775 1776 return pci_conf_read(sc->sc_pc, tag, offset); 1777 } 1778 1779 /* 1780 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1781 * int offs, cardbusreg_t val) 1782 * This is the function to write the config space of a CardBus Card. 1783 * It works same as pci_conf_write. 1784 */ 1785 static void 1786 pccbb_conf_write(cc, tag, reg, val) 1787 cardbus_chipset_tag_t cc; 1788 cardbustag_t tag; 1789 int reg; /* register offset */ 1790 cardbusreg_t val; 1791 { 1792 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1793 1794 pci_conf_write(sc->sc_pc, tag, reg, val); 1795 } 1796 1797 #if 0 1798 STATIC int 1799 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1800 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1801 int speed, int flags, 1802 bus_space_handle_t * iohp) 1803 #endif 1804 /* 1805 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1806 * bus_addr_t start, bus_size_t size, 1807 * bus_size_t align, 1808 * struct pcmcia_io_handle *pcihp 1809 * 1810 * This function only allocates I/O region for pccard. This function 1811 * never maps the allocated region to pccard I/O area. 1812 * 1813 * XXX: The interface of this function is not very good, I believe. 1814 */ 1815 STATIC int 1816 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1817 pcmcia_chipset_handle_t pch; 1818 bus_addr_t start; /* start address */ 1819 bus_size_t size; 1820 bus_size_t align; 1821 struct pcmcia_io_handle *pcihp; 1822 { 1823 struct pcic_handle *ph = (struct pcic_handle *)pch; 1824 bus_addr_t ioaddr; 1825 int flags = 0; 1826 bus_space_tag_t iot; 1827 bus_space_handle_t ioh; 1828 #if rbus 1829 rbus_tag_t rb; 1830 #endif 1831 if (align == 0) { 1832 align = size; /* XXX: funny??? */ 1833 } 1834 1835 /* 1836 * Allocate some arbitrary I/O space. 1837 */ 1838 1839 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1840 1841 #if rbus 1842 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1843 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1844 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1845 return 1; 1846 } 1847 #else 1848 if (start) { 1849 ioaddr = start; 1850 if (bus_space_map(iot, start, size, 0, &ioh)) { 1851 return 1; 1852 } 1853 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1854 (u_long) ioaddr, (u_long) size)); 1855 } else { 1856 flags |= PCMCIA_IO_ALLOCATED; 1857 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1858 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1859 size, align, 0, 0, &ioaddr, &ioh)) { 1860 /* No room be able to be get. */ 1861 return 1; 1862 } 1863 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1864 (u_long) ioaddr, (u_long) size)); 1865 } 1866 #endif 1867 1868 pcihp->iot = iot; 1869 pcihp->ioh = ioh; 1870 pcihp->addr = ioaddr; 1871 pcihp->size = size; 1872 pcihp->flags = flags; 1873 1874 return 0; 1875 } 1876 1877 /* 1878 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1879 * struct pcmcia_io_handle *pcihp) 1880 * 1881 * This function only frees I/O region for pccard. 1882 * 1883 * XXX: The interface of this function is not very good, I believe. 1884 */ 1885 void 1886 pccbb_pcmcia_io_free(pch, pcihp) 1887 pcmcia_chipset_handle_t pch; 1888 struct pcmcia_io_handle *pcihp; 1889 { 1890 #if !rbus 1891 bus_space_tag_t iot = pcihp->iot; 1892 #endif 1893 bus_space_handle_t ioh = pcihp->ioh; 1894 bus_size_t size = pcihp->size; 1895 1896 #if rbus 1897 struct pccbb_softc *sc = 1898 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1899 rbus_tag_t rb = sc->sc_rbus_iot; 1900 1901 rbus_space_free(rb, ioh, size, NULL); 1902 #else 1903 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1904 bus_space_free(iot, ioh, size); 1905 else 1906 bus_space_unmap(iot, ioh, size); 1907 #endif 1908 } 1909 1910 /* 1911 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1912 * bus_addr_t offset, bus_size_t size, 1913 * struct pcmcia_io_handle *pcihp, 1914 * int *windowp) 1915 * 1916 * This function maps the allocated I/O region to pccard. This function 1917 * never allocates any I/O region for pccard I/O area. I don't 1918 * understand why the original authors of pcmciabus separated alloc and 1919 * map. I believe the two must be unite. 1920 * 1921 * XXX: no wait timing control? 1922 */ 1923 int 1924 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1925 pcmcia_chipset_handle_t pch; 1926 int width; 1927 bus_addr_t offset; 1928 bus_size_t size; 1929 struct pcmcia_io_handle *pcihp; 1930 int *windowp; 1931 { 1932 struct pcic_handle *ph = (struct pcic_handle *)pch; 1933 bus_addr_t ioaddr = pcihp->addr + offset; 1934 int i, win; 1935 #if defined CBB_DEBUG 1936 static char *width_names[] = { "dynamic", "io8", "io16" }; 1937 #endif 1938 1939 /* Sanity check I/O handle. */ 1940 1941 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1942 panic("pccbb_pcmcia_io_map iot is bogus"); 1943 } 1944 1945 /* XXX Sanity check offset/size. */ 1946 1947 win = -1; 1948 for (i = 0; i < PCIC_IO_WINS; i++) { 1949 if ((ph->ioalloc & (1 << i)) == 0) { 1950 win = i; 1951 ph->ioalloc |= (1 << i); 1952 break; 1953 } 1954 } 1955 1956 if (win == -1) { 1957 return 1; 1958 } 1959 1960 *windowp = win; 1961 1962 /* XXX this is pretty gross */ 1963 1964 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1965 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1966 1967 /* XXX wtf is this doing here? */ 1968 1969 #if 0 1970 printf(" port 0x%lx", (u_long) ioaddr); 1971 if (size > 1) { 1972 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1973 } 1974 #endif 1975 1976 ph->io[win].addr = ioaddr; 1977 ph->io[win].size = size; 1978 ph->io[win].width = width; 1979 1980 /* actual dirty register-value changing in the function below. */ 1981 pccbb_pcmcia_do_io_map(ph, win); 1982 1983 return 0; 1984 } 1985 1986 /* 1987 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1988 * 1989 * This function changes register-value to map I/O region for pccard. 1990 */ 1991 static void 1992 pccbb_pcmcia_do_io_map(ph, win) 1993 struct pcic_handle *ph; 1994 int win; 1995 { 1996 static u_int8_t pcic_iowidth[3] = { 1997 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1998 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1999 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2000 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2001 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2002 }; 2003 2004 #define PCIC_SIA_START_LOW 0 2005 #define PCIC_SIA_START_HIGH 1 2006 #define PCIC_SIA_STOP_LOW 2 2007 #define PCIC_SIA_STOP_HIGH 3 2008 2009 int regbase_win = 0x8 + win * 0x04; 2010 u_int8_t ioctl, enable; 2011 2012 DPRINTF( 2013 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2014 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2015 ph->io[win].width * 8)); 2016 2017 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2018 ph->io[win].addr & 0xff); 2019 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2020 (ph->io[win].addr >> 8) & 0xff); 2021 2022 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2023 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2024 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2025 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2026 2027 ioctl = Pcic_read(ph, PCIC_IOCTL); 2028 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2029 switch (win) { 2030 case 0: 2031 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2032 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2033 PCIC_IOCTL_IO0_DATASIZE_MASK); 2034 ioctl |= pcic_iowidth[ph->io[win].width]; 2035 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2036 break; 2037 case 1: 2038 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2039 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2040 PCIC_IOCTL_IO1_DATASIZE_MASK); 2041 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2042 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2043 break; 2044 } 2045 Pcic_write(ph, PCIC_IOCTL, ioctl); 2046 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2047 #if defined CBB_DEBUG 2048 { 2049 u_int8_t start_low = 2050 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2051 u_int8_t start_high = 2052 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2053 u_int8_t stop_low = 2054 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2055 u_int8_t stop_high = 2056 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2057 printf 2058 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2059 start_low, start_high, stop_low, stop_high, ioctl, enable); 2060 } 2061 #endif 2062 } 2063 2064 /* 2065 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2066 * 2067 * This function unmaps I/O region. No return value. 2068 */ 2069 STATIC void 2070 pccbb_pcmcia_io_unmap(pch, win) 2071 pcmcia_chipset_handle_t pch; 2072 int win; 2073 { 2074 struct pcic_handle *ph = (struct pcic_handle *)pch; 2075 int reg; 2076 2077 if (win >= PCIC_IO_WINS || win < 0) { 2078 panic("pccbb_pcmcia_io_unmap: window out of range"); 2079 } 2080 2081 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2082 switch (win) { 2083 case 0: 2084 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2085 break; 2086 case 1: 2087 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2088 break; 2089 } 2090 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2091 2092 ph->ioalloc &= ~(1 << win); 2093 } 2094 2095 /* 2096 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2097 * 2098 * This function enables the card. All information is stored in 2099 * the first argument, pcmcia_chipset_handle_t. 2100 */ 2101 static void 2102 pccbb_pcmcia_wait_ready(ph) 2103 struct pcic_handle *ph; 2104 { 2105 int i; 2106 2107 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2108 Pcic_read(ph, PCIC_IF_STATUS))); 2109 2110 for (i = 0; i < 10000; i++) { 2111 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2112 return; 2113 } 2114 delay(500); 2115 #ifdef CBB_DEBUG 2116 if ((i > 5000) && (i % 100 == 99)) 2117 printf("."); 2118 #endif 2119 } 2120 2121 #ifdef DIAGNOSTIC 2122 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2123 Pcic_read(ph, PCIC_IF_STATUS)); 2124 #endif 2125 } 2126 2127 /* 2128 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2129 * 2130 * This function enables the card. All information is stored in 2131 * the first argument, pcmcia_chipset_handle_t. 2132 */ 2133 STATIC void 2134 pccbb_pcmcia_socket_enable(pch) 2135 pcmcia_chipset_handle_t pch; 2136 { 2137 struct pcic_handle *ph = (struct pcic_handle *)pch; 2138 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2139 int cardtype, win; 2140 u_int8_t power, intr; 2141 pcireg_t spsr; 2142 int voltage; 2143 2144 /* this bit is mostly stolen from pcic_attach_card */ 2145 2146 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2147 2148 /* get card Vcc info */ 2149 2150 spsr = 2151 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2152 CB_SOCKET_STAT); 2153 if (spsr & CB_SOCKET_STAT_5VCARD) { 2154 DPRINTF(("5V card\n")); 2155 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2156 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2157 DPRINTF(("3V card\n")); 2158 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2159 } else { 2160 printf("?V card, 0x%x\n", spsr); /* XXX */ 2161 return; 2162 } 2163 2164 /* assert reset bit */ 2165 intr = Pcic_read(ph, PCIC_INTR); 2166 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2167 Pcic_write(ph, PCIC_INTR, intr); 2168 2169 /* disable socket i/o: negate output enable bit */ 2170 2171 power = Pcic_read(ph, PCIC_PWRCTL); 2172 power &= ~PCIC_PWRCTL_OE; 2173 Pcic_write(ph, PCIC_PWRCTL, power); 2174 2175 /* power down the socket to reset it, clear the card reset pin */ 2176 2177 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2178 2179 /* 2180 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2181 * we are changing Vcc (Toff). 2182 */ 2183 /* delay(300*1000); too much */ 2184 2185 /* power up the socket */ 2186 pccbb_power(sc, voltage); 2187 2188 /* 2189 * wait 100ms until power raise (Tpr) and 20ms to become 2190 * stable (Tsu(Vcc)). 2191 * 2192 * some machines require some more time to be settled 2193 * (another 200ms is added here). 2194 */ 2195 /* delay((100 + 20 + 200)*1000); too much */ 2196 2197 power = Pcic_read(ph, PCIC_PWRCTL); 2198 power |= PCIC_PWRCTL_OE; 2199 Pcic_write(ph, PCIC_PWRCTL, power); 2200 2201 /* 2202 * hold RESET at least 10us. 2203 */ 2204 delay(10); 2205 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2206 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2207 2208 /* clear the reset flag */ 2209 2210 intr |= PCIC_INTR_RESET; 2211 Pcic_write(ph, PCIC_INTR, intr); 2212 2213 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2214 2215 delay(20000); 2216 2217 /* wait for the chip to finish initializing */ 2218 2219 pccbb_pcmcia_wait_ready(ph); 2220 2221 /* zero out the address windows */ 2222 2223 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2224 2225 /* set the card type */ 2226 2227 cardtype = pcmcia_card_gettype(ph->pcmcia); 2228 2229 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2230 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2231 Pcic_write(ph, PCIC_INTR, intr); 2232 2233 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2234 ph->ph_parent->dv_xname, ph->sock, 2235 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2236 2237 /* reinstall all the memory and io mappings */ 2238 2239 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2240 if (ph->memalloc & (1 << win)) { 2241 pccbb_pcmcia_do_mem_map(ph, win); 2242 } 2243 } 2244 2245 for (win = 0; win < PCIC_IO_WINS; ++win) { 2246 if (ph->ioalloc & (1 << win)) { 2247 pccbb_pcmcia_do_io_map(ph, win); 2248 } 2249 } 2250 } 2251 2252 /* 2253 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2254 * 2255 * This function disables the card. All information is stored in 2256 * the first argument, pcmcia_chipset_handle_t. 2257 */ 2258 STATIC void 2259 pccbb_pcmcia_socket_disable(pch) 2260 pcmcia_chipset_handle_t pch; 2261 { 2262 struct pcic_handle *ph = (struct pcic_handle *)pch; 2263 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2264 u_int8_t power, intr; 2265 2266 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2267 2268 /* reset signal asserting... */ 2269 2270 intr = Pcic_read(ph, PCIC_INTR); 2271 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2272 Pcic_write(ph, PCIC_INTR, intr); 2273 delay(2 * 1000); 2274 2275 /* power down the socket */ 2276 power = Pcic_read(ph, PCIC_PWRCTL); 2277 power &= ~PCIC_PWRCTL_OE; 2278 Pcic_write(ph, PCIC_PWRCTL, power); 2279 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2280 /* 2281 * wait 300ms until power fails (Tpf). 2282 */ 2283 delay(300 * 1000); 2284 } 2285 2286 /* 2287 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2288 * 2289 * This function detects whether a card is in the slot or not. 2290 * If a card is inserted, return 1. Otherwise, return 0. 2291 */ 2292 STATIC int 2293 pccbb_pcmcia_card_detect(pch) 2294 pcmcia_chipset_handle_t pch; 2295 { 2296 struct pcic_handle *ph = (struct pcic_handle *)pch; 2297 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2298 2299 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2300 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2301 } 2302 2303 #if 0 2304 STATIC int 2305 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2306 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2307 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2308 #endif 2309 /* 2310 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2311 * bus_size_t size, 2312 * struct pcmcia_mem_handle *pcmhp) 2313 * 2314 * This function only allocates memory region for pccard. This 2315 * function never maps the allocated region to pccard memory area. 2316 * 2317 * XXX: Why the argument of start address is not in? 2318 */ 2319 STATIC int 2320 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2321 pcmcia_chipset_handle_t pch; 2322 bus_size_t size; 2323 struct pcmcia_mem_handle *pcmhp; 2324 { 2325 struct pcic_handle *ph = (struct pcic_handle *)pch; 2326 bus_space_handle_t memh; 2327 bus_addr_t addr; 2328 bus_size_t sizepg; 2329 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2330 #if rbus 2331 rbus_tag_t rb; 2332 #endif 2333 2334 /* out of sc->memh, allocate as many pages as necessary */ 2335 2336 /* convert size to PCIC pages */ 2337 /* 2338 * This is not enough; when the requested region is on the page 2339 * boundaries, this may calculate wrong result. 2340 */ 2341 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2342 #if 0 2343 if (sizepg > PCIC_MAX_MEM_PAGES) { 2344 return 1; 2345 } 2346 #endif 2347 2348 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2349 return 1; 2350 } 2351 2352 addr = 0; /* XXX gcc -Wuninitialized */ 2353 2354 #if rbus 2355 rb = sc->sc_rbus_memt; 2356 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2357 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2358 &addr, &memh)) { 2359 return 1; 2360 } 2361 #else 2362 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2363 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2364 0, /* boundary */ 2365 0, /* flags */ 2366 &addr, &memh)) { 2367 return 1; 2368 } 2369 #endif 2370 2371 DPRINTF( 2372 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2373 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2374 2375 pcmhp->memt = sc->sc_memt; 2376 pcmhp->memh = memh; 2377 pcmhp->addr = addr; 2378 pcmhp->size = size; 2379 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2380 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2381 pcmhp->mhandle = 0; 2382 /* No offset??? Funny. */ 2383 2384 return 0; 2385 } 2386 2387 /* 2388 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2389 * struct pcmcia_mem_handle *pcmhp) 2390 * 2391 * This function release the memory space allocated by the function 2392 * pccbb_pcmcia_mem_alloc(). 2393 */ 2394 STATIC void 2395 pccbb_pcmcia_mem_free(pch, pcmhp) 2396 pcmcia_chipset_handle_t pch; 2397 struct pcmcia_mem_handle *pcmhp; 2398 { 2399 #if rbus 2400 struct pcic_handle *ph = (struct pcic_handle *)pch; 2401 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2402 2403 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2404 #else 2405 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2406 #endif 2407 } 2408 2409 /* 2410 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2411 * 2412 * This function release the memory space allocated by the function 2413 * pccbb_pcmcia_mem_alloc(). 2414 */ 2415 STATIC void 2416 pccbb_pcmcia_do_mem_map(ph, win) 2417 struct pcic_handle *ph; 2418 int win; 2419 { 2420 int regbase_win; 2421 bus_addr_t phys_addr; 2422 bus_addr_t phys_end; 2423 2424 #define PCIC_SMM_START_LOW 0 2425 #define PCIC_SMM_START_HIGH 1 2426 #define PCIC_SMM_STOP_LOW 2 2427 #define PCIC_SMM_STOP_HIGH 3 2428 #define PCIC_CMA_LOW 4 2429 #define PCIC_CMA_HIGH 5 2430 2431 u_int8_t start_low, start_high = 0; 2432 u_int8_t stop_low, stop_high; 2433 u_int8_t off_low, off_high; 2434 u_int8_t mem_window; 2435 int reg; 2436 2437 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2438 int mem8 = 2439 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2440 || (kind == PCMCIA_MEM_ATTR); 2441 2442 regbase_win = 0x10 + win * 0x08; 2443 2444 phys_addr = ph->mem[win].addr; 2445 phys_end = phys_addr + ph->mem[win].size; 2446 2447 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2448 phys_addr, phys_end, ph->mem[win].offset)); 2449 2450 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2451 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2452 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2453 2454 /* bit 19:12 */ 2455 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2456 /* bit 23:20 and bit 7 on */ 2457 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2458 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2459 /* bit 31:24, for 32-bit address */ 2460 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2461 2462 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2463 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2464 2465 if (((struct pccbb_softc *)ph-> 2466 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2467 Pcic_write(ph, 0x40 + win, mem_window); 2468 } 2469 2470 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2471 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2472 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2473 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2474 2475 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2476 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2477 2478 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2479 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2480 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2481 | ((kind == PCMCIA_MEM_ATTR) ? 2482 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2483 2484 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2485 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2486 2487 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2488 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2489 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2490 2491 #if defined CBB_DEBUG 2492 { 2493 int r1, r2, r3, r4, r5, r6, r7 = 0; 2494 2495 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2496 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2497 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2498 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2499 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2500 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2501 if (((struct pccbb_softc *)(ph-> 2502 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2503 r7 = Pcic_read(ph, 0x40 + win); 2504 } 2505 2506 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2507 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2508 if (((struct pccbb_softc *)(ph-> 2509 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2510 DPRINTF((" %02x", r7)); 2511 } 2512 DPRINTF(("\n")); 2513 } 2514 #endif 2515 } 2516 2517 /* 2518 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2519 * bus_addr_t card_addr, bus_size_t size, 2520 * struct pcmcia_mem_handle *pcmhp, 2521 * bus_addr_t *offsetp, int *windowp) 2522 * 2523 * This function maps memory space allocated by the function 2524 * pccbb_pcmcia_mem_alloc(). 2525 */ 2526 STATIC int 2527 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2528 pcmcia_chipset_handle_t pch; 2529 int kind; 2530 bus_addr_t card_addr; 2531 bus_size_t size; 2532 struct pcmcia_mem_handle *pcmhp; 2533 bus_addr_t *offsetp; 2534 int *windowp; 2535 { 2536 struct pcic_handle *ph = (struct pcic_handle *)pch; 2537 bus_addr_t busaddr; 2538 long card_offset; 2539 int win; 2540 2541 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2542 if ((ph->memalloc & (1 << win)) == 0) { 2543 ph->memalloc |= (1 << win); 2544 break; 2545 } 2546 } 2547 2548 if (win == PCIC_MEM_WINS) { 2549 return 1; 2550 } 2551 2552 *windowp = win; 2553 2554 /* XXX this is pretty gross */ 2555 2556 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2557 panic("pccbb_pcmcia_mem_map memt is bogus"); 2558 } 2559 2560 busaddr = pcmhp->addr; 2561 2562 /* 2563 * compute the address offset to the pcmcia address space for the 2564 * pcic. this is intentionally signed. The masks and shifts below 2565 * will cause TRT to happen in the pcic registers. Deal with making 2566 * sure the address is aligned, and return the alignment offset. 2567 */ 2568 2569 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2570 card_addr -= *offsetp; 2571 2572 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2573 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2574 (u_long) card_addr)); 2575 2576 /* 2577 * include the offset in the size, and decrement size by one, since 2578 * the hw wants start/stop 2579 */ 2580 size += *offsetp - 1; 2581 2582 card_offset = (((long)card_addr) - ((long)busaddr)); 2583 2584 ph->mem[win].addr = busaddr; 2585 ph->mem[win].size = size; 2586 ph->mem[win].offset = card_offset; 2587 ph->mem[win].kind = kind; 2588 2589 pccbb_pcmcia_do_mem_map(ph, win); 2590 2591 return 0; 2592 } 2593 2594 /* 2595 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2596 * int window) 2597 * 2598 * This function unmaps memory space which mapped by the function 2599 * pccbb_pcmcia_mem_map(). 2600 */ 2601 STATIC void 2602 pccbb_pcmcia_mem_unmap(pch, window) 2603 pcmcia_chipset_handle_t pch; 2604 int window; 2605 { 2606 struct pcic_handle *ph = (struct pcic_handle *)pch; 2607 int reg; 2608 2609 if (window >= PCIC_MEM_WINS) { 2610 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2611 } 2612 2613 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2614 reg &= ~(1 << window); 2615 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2616 2617 ph->memalloc &= ~(1 << window); 2618 } 2619 2620 #if defined PCCBB_PCMCIA_POLL 2621 struct pccbb_poll_str { 2622 void *arg; 2623 int (*func) __P((void *)); 2624 int level; 2625 struct pcic_handle *ph; 2626 int count; 2627 int num; 2628 }; 2629 2630 static struct pccbb_poll_str pccbb_poll[10]; 2631 static int pccbb_poll_n = 0; 2632 2633 static void pccbb_pcmcia_poll __P((void *arg)); 2634 2635 static void 2636 pccbb_pcmcia_poll(arg) 2637 void *arg; 2638 { 2639 struct pccbb_poll_str *poll = arg; 2640 struct pcic_handle *ph = poll->ph; 2641 struct pccbb_softc *sc = ph->sc; 2642 int s; 2643 u_int32_t spsr; /* socket present-state reg */ 2644 2645 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2646 switch (poll->level) { 2647 case IPL_NET: 2648 s = splnet(); 2649 break; 2650 case IPL_BIO: 2651 s = splbio(); 2652 break; 2653 case IPL_TTY: /* fallthrough */ 2654 default: 2655 s = spltty(); 2656 break; 2657 } 2658 2659 spsr = 2660 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2661 CB_SOCKET_STAT); 2662 2663 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2664 if (!(spsr & 0x40)) /* CINT low */ 2665 #else 2666 if (1) 2667 #endif 2668 { 2669 if ((*poll->func) (poll->arg) > 0) { 2670 ++poll->count; 2671 // printf("intr: reported from poller, 0x%x\n", spsr); 2672 #if defined LEVEL2 2673 } else { 2674 printf("intr: miss! 0x%x\n", spsr); 2675 #endif 2676 } 2677 } 2678 splx(s); 2679 } 2680 #endif /* defined CB_PCMCIA_POLL */ 2681 2682 /* 2683 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2684 * struct pcmcia_function *pf, 2685 * int ipl, 2686 * int (*func)(void *), 2687 * void *arg); 2688 * 2689 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2690 */ 2691 STATIC void * 2692 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2693 pcmcia_chipset_handle_t pch; 2694 struct pcmcia_function *pf; 2695 int ipl; 2696 int (*func) __P((void *)); 2697 void *arg; 2698 { 2699 struct pcic_handle *ph = (struct pcic_handle *)pch; 2700 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2701 2702 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2703 /* what should I do? */ 2704 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2705 DPRINTF( 2706 ("%s does not provide edge nor pulse interrupt\n", 2707 sc->sc_dev.dv_xname)); 2708 return NULL; 2709 } 2710 /* 2711 * XXX Noooooo! The interrupt flag must set properly!! 2712 * dumb pcmcia driver!! 2713 */ 2714 } 2715 2716 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2717 } 2718 2719 /* 2720 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2721 * void *ih) 2722 * 2723 * This function disables PC-Card interrupt. 2724 */ 2725 STATIC void 2726 pccbb_pcmcia_intr_disestablish(pch, ih) 2727 pcmcia_chipset_handle_t pch; 2728 void *ih; 2729 { 2730 struct pcic_handle *ph = (struct pcic_handle *)pch; 2731 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2732 2733 pccbb_intr_disestablish(sc, ih); 2734 } 2735 2736 #if rbus 2737 /* 2738 * static int 2739 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2740 * bus_addr_t addr, bus_size_t size, 2741 * bus_addr_t mask, bus_size_t align, 2742 * int flags, bus_addr_t *addrp; 2743 * bus_space_handle_t *bshp) 2744 * 2745 * This function allocates a portion of memory or io space for 2746 * clients. This function is called from CardBus card drivers. 2747 */ 2748 static int 2749 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2750 cardbus_chipset_tag_t ct; 2751 rbus_tag_t rb; 2752 bus_addr_t addr; 2753 bus_size_t size; 2754 bus_addr_t mask; 2755 bus_size_t align; 2756 int flags; 2757 bus_addr_t *addrp; 2758 bus_space_handle_t *bshp; 2759 { 2760 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2761 2762 DPRINTF( 2763 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2764 addr, size, mask, align)); 2765 2766 if (align == 0) { 2767 align = size; 2768 } 2769 2770 if (rb->rb_bt == sc->sc_memt) { 2771 if (align < 16) { 2772 return 1; 2773 } 2774 } else if (rb->rb_bt == sc->sc_iot) { 2775 if (align < 4) { 2776 return 1; 2777 } 2778 } else { 2779 DPRINTF( 2780 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2781 rb->rb_bt)); 2782 return 1; 2783 /* XXX: panic here? */ 2784 } 2785 2786 /* XXX: hack for avoiding ISA image */ 2787 if (mask < 0x3ff) { 2788 mask = 0x3ff; 2789 addr = 0x300; 2790 } 2791 2792 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2793 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2794 return 1; 2795 } 2796 2797 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2798 2799 return 0; 2800 } 2801 2802 /* 2803 * static int 2804 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2805 * bus_space_handle_t *bshp, bus_size_t size); 2806 * 2807 * This function is called from CardBus card drivers. 2808 */ 2809 static int 2810 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2811 cardbus_chipset_tag_t ct; 2812 rbus_tag_t rb; 2813 bus_space_handle_t bsh; 2814 bus_size_t size; 2815 { 2816 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2817 bus_space_tag_t bt = rb->rb_bt; 2818 2819 pccbb_close_win(sc, bt, bsh, size); 2820 2821 if (bt == sc->sc_memt) { 2822 } else if (bt == sc->sc_iot) { 2823 } else { 2824 return 1; 2825 /* XXX: panic here? */ 2826 } 2827 2828 return rbus_space_free(rb, bsh, size, NULL); 2829 } 2830 #endif /* rbus */ 2831 2832 #if rbus 2833 2834 static int 2835 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2836 struct pccbb_softc *sc; 2837 bus_space_tag_t bst; 2838 bus_addr_t addr; 2839 bus_size_t size; 2840 bus_space_handle_t bsh; 2841 int flags; 2842 { 2843 struct pccbb_win_chain_head *head; 2844 bus_addr_t align; 2845 2846 head = &sc->sc_iowindow; 2847 align = 0x04; 2848 if (sc->sc_memt == bst) { 2849 head = &sc->sc_memwindow; 2850 align = 0x1000; 2851 DPRINTF(("using memory window, %x %x %x\n\n", 2852 sc->sc_iot, sc->sc_memt, bst)); 2853 } 2854 2855 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2856 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2857 sc->sc_dev.dv_xname, 2858 (head == &sc->sc_memwindow) ? "mem" : "io"); 2859 } 2860 pccbb_winset(align, sc, bst); 2861 2862 return 0; 2863 } 2864 2865 static int 2866 pccbb_close_win(sc, bst, bsh, size) 2867 struct pccbb_softc *sc; 2868 bus_space_tag_t bst; 2869 bus_space_handle_t bsh; 2870 bus_size_t size; 2871 { 2872 struct pccbb_win_chain_head *head; 2873 bus_addr_t align; 2874 2875 head = &sc->sc_iowindow; 2876 align = 0x04; 2877 if (sc->sc_memt == bst) { 2878 head = &sc->sc_memwindow; 2879 align = 0x1000; 2880 } 2881 2882 if (pccbb_winlist_delete(head, bsh, size)) { 2883 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2884 sc->sc_dev.dv_xname, 2885 (head == &sc->sc_memwindow) ? "mem" : "io"); 2886 } 2887 pccbb_winset(align, sc, bst); 2888 2889 return 0; 2890 } 2891 2892 static int 2893 pccbb_winlist_insert(head, start, size, bsh, flags) 2894 struct pccbb_win_chain_head *head; 2895 bus_addr_t start; 2896 bus_size_t size; 2897 bus_space_handle_t bsh; 2898 int flags; 2899 { 2900 struct pccbb_win_chain *chainp, *elem; 2901 2902 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2903 M_NOWAIT)) == NULL) 2904 return (1); /* fail */ 2905 2906 elem->wc_start = start; 2907 elem->wc_end = start + (size - 1); 2908 elem->wc_handle = bsh; 2909 elem->wc_flags = flags; 2910 2911 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2912 chainp = TAILQ_NEXT(chainp, wc_list)) { 2913 if (chainp->wc_end < start) 2914 continue; 2915 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2916 return (0); 2917 } 2918 2919 TAILQ_INSERT_TAIL(head, elem, wc_list); 2920 return (0); 2921 } 2922 2923 static int 2924 pccbb_winlist_delete(head, bsh, size) 2925 struct pccbb_win_chain_head *head; 2926 bus_space_handle_t bsh; 2927 bus_size_t size; 2928 { 2929 struct pccbb_win_chain *chainp; 2930 2931 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2932 chainp = TAILQ_NEXT(chainp, wc_list)) { 2933 if (chainp->wc_handle != bsh) 2934 continue; 2935 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2936 printf("pccbb_winlist_delete: window 0x%lx size " 2937 "inconsistent: 0x%lx, 0x%lx\n", 2938 chainp->wc_start, 2939 chainp->wc_end - chainp->wc_start, 2940 size - 1); 2941 return 1; 2942 } 2943 2944 TAILQ_REMOVE(head, chainp, wc_list); 2945 free(chainp, M_DEVBUF); 2946 2947 return 0; 2948 } 2949 2950 return 1; /* fail: no candidate to remove */ 2951 } 2952 2953 static void 2954 pccbb_winset(align, sc, bst) 2955 bus_addr_t align; 2956 struct pccbb_softc *sc; 2957 bus_space_tag_t bst; 2958 { 2959 pci_chipset_tag_t pc; 2960 pcitag_t tag; 2961 bus_addr_t mask = ~(align - 1); 2962 struct { 2963 cardbusreg_t win_start; 2964 cardbusreg_t win_limit; 2965 int win_flags; 2966 } win[2]; 2967 struct pccbb_win_chain *chainp; 2968 int offs; 2969 2970 win[0].win_start = 0xffffffff; 2971 win[0].win_limit = 0; 2972 win[1].win_start = 0xffffffff; 2973 win[1].win_limit = 0; 2974 2975 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2976 offs = 0x2c; 2977 if (sc->sc_memt == bst) { 2978 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2979 offs = 0x1c; 2980 } 2981 2982 if (chainp != NULL) { 2983 win[0].win_start = chainp->wc_start & mask; 2984 win[0].win_limit = chainp->wc_end & mask; 2985 win[0].win_flags = chainp->wc_flags; 2986 chainp = TAILQ_NEXT(chainp, wc_list); 2987 } 2988 2989 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2990 if (win[1].win_start == 0xffffffff) { 2991 /* window 1 is not used */ 2992 if ((win[0].win_flags == chainp->wc_flags) && 2993 (win[0].win_limit + align >= 2994 (chainp->wc_start & mask))) { 2995 /* concatenate */ 2996 win[0].win_limit = chainp->wc_end & mask; 2997 } else { 2998 /* make new window */ 2999 win[1].win_start = chainp->wc_start & mask; 3000 win[1].win_limit = chainp->wc_end & mask; 3001 win[1].win_flags = chainp->wc_flags; 3002 } 3003 continue; 3004 } 3005 3006 /* Both windows are engaged. */ 3007 if (win[0].win_flags == win[1].win_flags) { 3008 /* same flags */ 3009 if (win[0].win_flags == chainp->wc_flags) { 3010 if (win[1].win_start - (win[0].win_limit + 3011 align) < 3012 (chainp->wc_start & mask) - 3013 ((chainp->wc_end & mask) + align)) { 3014 /* 3015 * merge window 0 and 1, and set win1 3016 * to chainp 3017 */ 3018 win[0].win_limit = win[1].win_limit; 3019 win[1].win_start = 3020 chainp->wc_start & mask; 3021 win[1].win_limit = 3022 chainp->wc_end & mask; 3023 } else { 3024 win[1].win_limit = 3025 chainp->wc_end & mask; 3026 } 3027 } else { 3028 /* different flags */ 3029 3030 /* concatenate win0 and win1 */ 3031 win[0].win_limit = win[1].win_limit; 3032 /* allocate win[1] to new space */ 3033 win[1].win_start = chainp->wc_start & mask; 3034 win[1].win_limit = chainp->wc_end & mask; 3035 win[1].win_flags = chainp->wc_flags; 3036 } 3037 } else { 3038 /* the flags of win[0] and win[1] is different */ 3039 if (win[0].win_flags == chainp->wc_flags) { 3040 win[0].win_limit = chainp->wc_end & mask; 3041 /* 3042 * XXX this creates overlapping windows, so 3043 * what should the poor bridge do if one is 3044 * cachable, and the other is not? 3045 */ 3046 printf("%s: overlapping windows\n", 3047 sc->sc_dev.dv_xname); 3048 } else { 3049 win[1].win_limit = chainp->wc_end & mask; 3050 } 3051 } 3052 } 3053 3054 pc = sc->sc_pc; 3055 tag = sc->sc_tag; 3056 pci_conf_write(pc, tag, offs, win[0].win_start); 3057 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3058 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3059 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3060 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3061 pci_conf_read(pc, tag, offs), 3062 pci_conf_read(pc, tag, offs + 4) + align, 3063 pci_conf_read(pc, tag, offs + 8), 3064 pci_conf_read(pc, tag, offs + 12) + align)); 3065 3066 if (bst == sc->sc_memt) { 3067 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3068 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3069 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3070 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3071 } 3072 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3073 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3074 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3075 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3076 } 3077 } 3078 } 3079 3080 #endif /* rbus */ 3081 3082 static void 3083 pccbb_powerhook(why, arg) 3084 int why; 3085 void *arg; 3086 { 3087 struct pccbb_softc *sc = arg; 3088 u_int32_t reg; 3089 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3090 bus_space_handle_t base_memh = sc->sc_base_memh; 3091 3092 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3093 3094 if (why == PWR_RESUME) { 3095 /* CSC Interrupt: Card detect interrupt on */ 3096 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3097 /* Card detect intr is turned on. */ 3098 reg |= CB_SOCKET_MASK_CD; 3099 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3100 /* reset interrupt */ 3101 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3102 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3103 3104 /* 3105 * check for card insertion or removal during suspend period. 3106 * XXX: the code can't cope with card swap (remove then 3107 * insert). how can we detect such situation? 3108 */ 3109 (void)pccbbintr(sc); 3110 } 3111 } 3112
Indexes created Fri Sep 26 20:09:58 GMT 2025