pccbb.c revision 1.37
1 /* $NetBSD: pccbb.c,v 1.37 2000/03/23 07:01:40 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 struct yenta_chipinfo *yc; 355 356 /* Loop over except the last default entry. */ 357 for (yc = yc_chipsets; yc < yc_chipsets + 358 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 359 if (pci_id != yc->yc_id) 360 break; 361 362 if (flagp != NULL) 363 *flagp = yc->yc_flags; 364 365 return (yc->yc_chiptype); 366 } 367 368 static void 369 pccbb_shutdown(void *arg) 370 { 371 struct pccbb_softc *sc = arg; 372 pcireg_t command; 373 374 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 375 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 376 0); 377 378 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 379 380 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 381 PCI_COMMAND_MASTER_ENABLE); 382 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 383 384 } 385 386 void 387 pccbbattach(parent, self, aux) 388 struct device *parent; 389 struct device *self; 390 void *aux; 391 { 392 struct pccbb_softc *sc = (void *)self; 393 struct pci_attach_args *pa = aux; 394 pci_chipset_tag_t pc = pa->pa_pc; 395 pcireg_t sock_base, busreg; 396 bus_addr_t sockbase; 397 char devinfo[256]; 398 int flags; 399 400 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 401 402 pci_devinfo(pa->pa_id, 0, 0, devinfo); 403 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 404 #ifdef CBB_DEBUG 405 printf(" (chipflags %x)", flags); 406 #endif 407 printf("\n"); 408 409 TAILQ_INIT(&sc->sc_memwindow); 410 TAILQ_INIT(&sc->sc_iowindow); 411 412 #if rbus 413 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 414 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 415 #endif /* rbus */ 416 417 sc->sc_base_memh = 0; 418 419 /* 420 * MAP socket registers and ExCA registers on memory-space 421 * When no valid address is set on socket base registers (on pci 422 * config space), get it not polite way. 423 */ 424 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 425 426 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 427 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 428 /* The address must be valid. */ 429 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 430 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 431 printf("%s: can't map socket base address 0x%x\n", 432 sc->sc_dev.dv_xname, sock_base); 433 /* 434 * I think it's funny: socket base registers must be 435 * mapped on memory space, but ... 436 */ 437 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 438 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 439 NULL)) { 440 printf("%s: can't map socket base address" 441 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 442 sockbase); 443 /* give up... allocate reg space via rbus. */ 444 sc->sc_base_memh = 0; 445 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 446 } 447 } else { 448 DPRINTF(("%s: socket base address 0x%lx\n", 449 sc->sc_dev.dv_xname, sockbase)); 450 } 451 } 452 453 sc->sc_mem_start = 0; /* XXX */ 454 sc->sc_mem_end = 0xffffffff; /* XXX */ 455 456 /* 457 * When interrupt isn't routed correctly, give up probing cbb and do 458 * not kill pcic-compatible port. 459 */ 460 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 461 printf("%s: NOT USED because of unconfigured interrupt\n", 462 sc->sc_dev.dv_xname); 463 return; 464 } 465 466 /* 467 * When bus number isn't set correctly, give up using 32-bit CardBus 468 * mode. 469 */ 470 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 471 #if notyet 472 if (((busreg >> 8) & 0xff) == 0) { 473 printf("%s: CardBus support disabled because of unconfigured bus number\n", 474 sc->sc_dev.dv_xname); 475 flags |= PCCBB_PCMCIA_16BITONLY; 476 } 477 #endif 478 479 /* pccbb_machdep.c end */ 480 481 #if defined CBB_DEBUG 482 { 483 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 484 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 485 intrname[pa->pa_intrpin], pa->pa_intrline); 486 } 487 #endif 488 489 /* setup softc */ 490 sc->sc_pc = pc; 491 sc->sc_iot = pa->pa_iot; 492 sc->sc_memt = pa->pa_memt; 493 sc->sc_dmat = pa->pa_dmat; 494 sc->sc_tag = pa->pa_tag; 495 sc->sc_function = pa->pa_function; 496 497 sc->sc_intrline = pa->pa_intrline; 498 sc->sc_intrtag = pa->pa_intrtag; 499 sc->sc_intrpin = pa->pa_intrpin; 500 501 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 502 503 shutdownhook_establish(pccbb_shutdown, sc); 504 505 #if __NetBSD_Version__ > 103060000 506 config_defer(self, pccbb_pci_callback); 507 #else 508 pccbb_pci_callback(self); 509 #endif 510 } 511 512 513 514 515 /* 516 * static void pccbb_pci_callback(struct device *self) 517 * 518 * The actual attach routine: get memory space for YENTA register 519 * space, setup YENTA register and route interrupt. 520 * 521 * This function should be deferred because this device may obtain 522 * memory space dynamically. This function must avoid obtaining 523 * memory area which has already kept for another device. Also, 524 * this function MUST be done before ISA attach process because this 525 * function kills pcic compatible port used by ISA pcic. 526 */ 527 static void 528 pccbb_pci_callback(self) 529 struct device *self; 530 { 531 struct pccbb_softc *sc = (void *)self; 532 pci_chipset_tag_t pc = sc->sc_pc; 533 bus_space_tag_t base_memt; 534 bus_space_handle_t base_memh; 535 u_int32_t maskreg; 536 pci_intr_handle_t ih; 537 const char *intrstr = NULL; 538 bus_addr_t sockbase; 539 struct cbslot_attach_args cba; 540 struct pcmciabus_attach_args paa; 541 struct cardslot_attach_args caa; 542 struct cardslot_softc *csc; 543 544 if (0 == sc->sc_base_memh) { 545 /* The socket registers aren't mapped correctly. */ 546 #if rbus 547 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 548 (sc->sc_chipset == CB_RX5C47X 549 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 550 0, &sockbase, &sc->sc_base_memh)) { 551 return; 552 } 553 sc->sc_base_memt = sc->sc_memt; 554 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 555 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 556 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 557 PCI_SOCKBASE))); 558 #else 559 sc->sc_base_memt = sc->sc_memt; 560 #if !defined CBB_PCI_BASE 561 #define CBB_PCI_BASE 0x20000000 562 #endif 563 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 564 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 565 /* cannot allocate memory space */ 566 return; 567 } 568 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 569 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 570 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 571 sc->sc_tag, PCI_SOCKBASE))); 572 #endif 573 } 574 575 /* bus bridge initialization */ 576 pccbb_chipinit(sc); 577 578 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 579 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 580 581 /* CSC Interrupt: Card detect interrupt on */ 582 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 583 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 584 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 585 /* reset interrupt */ 586 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 587 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 588 589 /* Map and establish the interrupt. */ 590 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 591 sc->sc_intrline, &ih)) { 592 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 593 return; 594 } 595 intrstr = pci_intr_string(pc, ih); 596 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 597 598 if (sc->sc_ih == NULL) { 599 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 600 if (intrstr != NULL) { 601 printf(" at %s", intrstr); 602 } 603 printf("\n"); 604 return; 605 } 606 607 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 608 powerhook_establish(pccbb_powerhook, sc); 609 610 { 611 u_int32_t sockstat = 612 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 613 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 614 sc->sc_flags |= CBB_CARDEXIST; 615 } 616 } 617 618 /* 619 * attach cardbus 620 */ 621 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 622 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 623 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 624 625 /* initialize cbslot_attach */ 626 cba.cba_busname = "cardbus"; 627 cba.cba_iot = sc->sc_iot; 628 cba.cba_memt = sc->sc_memt; 629 cba.cba_dmat = sc->sc_dmat; 630 cba.cba_bus = (busreg >> 8) & 0x0ff; 631 cba.cba_cc = (void *)sc; 632 cba.cba_cf = &pccbb_funcs; 633 cba.cba_intrline = sc->sc_intrline; 634 635 #if rbus 636 cba.cba_rbus_iot = sc->sc_rbus_iot; 637 cba.cba_rbus_memt = sc->sc_rbus_memt; 638 #endif 639 640 cba.cba_cacheline = PCI_CACHELINE(bhlc); 641 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 642 643 printf("%s: cacheline 0x%x lattimer 0x%x\n", 644 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 645 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 646 busreg); 647 #if defined SHOW_REGS 648 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 649 sc->sc_base_memh); 650 #endif 651 } 652 653 pccbb_pcmcia_attach_setup(sc, &paa); 654 caa.caa_cb_attach = NULL; 655 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 656 caa.caa_cb_attach = &cba; 657 } 658 caa.caa_16_attach = &paa; 659 caa.caa_ph = &sc->sc_pcmcia_h; 660 661 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 662 DPRINTF(("pccbbattach: found cardslot\n")); 663 sc->sc_csc = csc; 664 } 665 666 return; 667 } 668 669 670 671 672 673 /* 674 * static void pccbb_chipinit(struct pccbb_softc *sc) 675 * 676 * This function initialize YENTA chip registers listed below: 677 * 1) PCI command reg, 678 * 2) PCI and CardBus latency timer, 679 * 3) disable legacy (PCIC-compatible) io, 680 * 4) route PCI interrupt, 681 * 5) close all memory and io windows. 682 */ 683 static void 684 pccbb_chipinit(sc) 685 struct pccbb_softc *sc; 686 { 687 pci_chipset_tag_t pc = sc->sc_pc; 688 pcitag_t tag = sc->sc_tag; 689 pcireg_t reg; 690 691 /* 692 * Set PCI command reg. 693 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 694 */ 695 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 696 /* I believe it is harmless. */ 697 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 698 PCI_COMMAND_MASTER_ENABLE); 699 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 700 701 /* 702 * Set CardBus latency timer. 703 */ 704 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 705 if (PCI_CB_LATENCY(reg) < 0x20) { 706 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 707 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 708 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 709 } 710 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 711 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 712 713 /* 714 * Set PCI latency timer. 715 */ 716 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 717 if (PCI_LATTIMER(reg) < 0x10) { 718 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 719 reg |= (0x10 << PCI_LATTIMER_SHIFT); 720 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 721 } 722 DPRINTF(("PCI latency timer 0x%x (%x)\n", 723 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 724 725 /* Disable legacy register mapping. */ 726 switch (sc->sc_chipset) { 727 case CB_RX5C46X: /* fallthrough */ 728 #if 0 729 case CB_RX5C47X: 730 #endif 731 /* 732 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 733 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 734 * CardBus bridges have special bits on Bridge control reg (addr 735 * 0x3e on PCI config space). 736 */ 737 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 738 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 739 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 740 break; 741 742 default: 743 /* XXX I don't know proper way to kill legacy I/O. */ 744 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 745 break; 746 } 747 748 /* Route functional interrupts to PCI. */ 749 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 750 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 751 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 752 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 753 754 switch (sc->sc_chipset) { 755 case CB_TI113X: 756 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 757 /* This bit is shared, but may read as 0 on some chips, so set 758 it explicitly on both functions. */ 759 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 760 /* CSC intr enable */ 761 reg |= PCI113X_CBCTRL_PCI_CSC; 762 /* functional intr prohibit */ 763 reg &= ~PCI113X_CBCTRL_PCI_INTR; 764 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 765 break; 766 767 case CB_TOPIC95B: 768 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 769 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 770 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 771 772 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 773 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 774 sc->sc_dev.dv_xname, reg)); 775 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 776 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 777 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 778 DPRINTF(("0x%x\n", reg)); 779 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 780 break; 781 } 782 783 /* Close all memory and I/O windows. */ 784 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 785 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 786 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 787 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 788 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 789 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 790 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 791 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 792 } 793 794 795 796 797 /* 798 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 799 * struct pcmciabus_attach_args *paa) 800 * 801 * This function attaches 16-bit PCcard bus. 802 */ 803 STATIC void 804 pccbb_pcmcia_attach_setup(sc, paa) 805 struct pccbb_softc *sc; 806 struct pcmciabus_attach_args *paa; 807 { 808 struct pcic_handle *ph = &sc->sc_pcmcia_h; 809 #if rbus 810 rbus_tag_t rb; 811 #endif 812 813 /* initialize pcmcia part in pccbb_softc */ 814 ph->ph_parent = (struct device *)sc; 815 ph->sock = sc->sc_function; 816 ph->flags = 0; 817 ph->shutdown = 0; 818 ph->ih_irq = sc->sc_intrline; 819 ph->ph_bus_t = sc->sc_base_memt; 820 ph->ph_bus_h = sc->sc_base_memh; 821 ph->ph_read = pccbb_pcmcia_read; 822 ph->ph_write = pccbb_pcmcia_write; 823 sc->sc_pct = &pccbb_pcmcia_funcs; 824 825 /* 826 * We need to do a few things here: 827 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 828 * setting the IRQ numbers to 0. 829 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 830 * routing of CSC interrupts (e.g. card removal) to PCI while in 831 * PCMCIA mode. We just leave this set all the time. 832 * 3) Enable card insertion/removal interrupts in case the chip also 833 * needs that while in PCMCIA mode. 834 * 4) Clear any pending CSC interrupt. 835 */ 836 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 837 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 838 Pcic_read(ph, PCIC_CSC); 839 840 /* initialize pcmcia bus attachment */ 841 paa->paa_busname = "pcmcia"; 842 paa->pct = sc->sc_pct; 843 paa->pch = ph; 844 paa->iobase = 0; /* I don't use them */ 845 paa->iosize = 0; 846 #if rbus 847 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 848 paa->iobase = rb->rb_start + rb->rb_offset; 849 paa->iosize = rb->rb_end - rb->rb_start; 850 #endif 851 852 return; 853 } 854 855 #if 0 856 STATIC void 857 pccbb_pcmcia_attach_card(ph) 858 struct pcic_handle *ph; 859 { 860 if (ph->flags & PCIC_FLAG_CARDP) { 861 panic("pccbb_pcmcia_attach_card: already attached"); 862 } 863 864 /* call the MI attach function */ 865 pcmcia_card_attach(ph->pcmcia); 866 867 ph->flags |= PCIC_FLAG_CARDP; 868 } 869 870 STATIC void 871 pccbb_pcmcia_detach_card(ph, flags) 872 struct pcic_handle *ph; 873 int flags; 874 { 875 if (!(ph->flags & PCIC_FLAG_CARDP)) { 876 panic("pccbb_pcmcia_detach_card: already detached"); 877 } 878 879 ph->flags &= ~PCIC_FLAG_CARDP; 880 881 /* call the MI detach function */ 882 pcmcia_card_detach(ph->pcmcia, flags); 883 } 884 #endif 885 886 /* 887 * int pccbbintr(arg) 888 * void *arg; 889 * This routine handles the interrupt from Yenta PCI-CardBus bridge 890 * itself. 891 */ 892 int 893 pccbbintr(arg) 894 void *arg; 895 { 896 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 897 u_int32_t sockevent, sockstate; 898 bus_space_tag_t memt = sc->sc_base_memt; 899 bus_space_handle_t memh = sc->sc_base_memh; 900 struct pcic_handle *ph = &sc->sc_pcmcia_h; 901 902 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 903 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 904 Pcic_read(ph, PCIC_CSC); 905 906 if (sockevent == 0) { 907 /* This intr is not for me: it may be for my child devices. */ 908 return (pccbbintr_function(sc)); 909 } 910 911 if (sockevent & CB_SOCKET_EVENT_CD) { 912 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 913 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 914 /* A card should be removed. */ 915 if (sc->sc_flags & CBB_CARDEXIST) { 916 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 917 sockevent)); 918 DPRINTF((" card removed, 0x%08x\n", sockstate)); 919 sc->sc_flags &= ~CBB_CARDEXIST; 920 if (sc->sc_csc->sc_status & 921 CARDSLOT_STATUS_CARD_16) { 922 #if 0 923 struct pcic_handle *ph = 924 &sc->sc_pcmcia_h; 925 926 pcmcia_card_deactivate(ph->pcmcia); 927 pccbb_pcmcia_socket_disable(ph); 928 pccbb_pcmcia_detach_card(ph, 929 DETACH_FORCE); 930 #endif 931 cardslot_event_throw(sc->sc_csc, 932 CARDSLOT_EVENT_REMOVAL_16); 933 } else if (sc->sc_csc->sc_status & 934 CARDSLOT_STATUS_CARD_CB) { 935 /* Cardbus intr removed */ 936 cardslot_event_throw(sc->sc_csc, 937 CARDSLOT_EVENT_REMOVAL_CB); 938 } 939 } 940 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 941 /* 942 * The pccbbintr may called from powerdown hook when 943 * the system resumed, to detect the card 944 * insertion/removal during suspension. 945 */ 946 (sc->sc_flags & CBB_CARDEXIST) == 0) { 947 if (sc->sc_flags & CBB_INSERTING) { 948 callout_stop(&sc->sc_insert_ch); 949 } 950 callout_reset(&sc->sc_insert_ch, hz / 10, 951 pci113x_insert, sc); 952 sc->sc_flags |= CBB_INSERTING; 953 } 954 } 955 956 return (1); 957 } 958 959 /* 960 * static int pccbbintr_function(struct pccbb_softc *sc) 961 * 962 * This function calls each interrupt handler registered at the 963 * bridge. The interrupt handlers are called in registered order. 964 */ 965 static int 966 pccbbintr_function(sc) 967 struct pccbb_softc *sc; 968 { 969 int retval = 0, val; 970 struct pccbb_intrhand_list *pil; 971 972 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 973 val = (*pil->pil_func) (pil->pil_arg); 974 retval = retval == 1 ? 1 : 975 retval == 0 ? val : val != 0 ? val : retval; 976 } 977 978 return retval; 979 } 980 981 static void 982 pci113x_insert(arg) 983 void *arg; 984 { 985 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 986 u_int32_t sockevent, sockstate; 987 988 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 989 CB_SOCKET_EVENT); 990 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 991 CB_SOCKET_STAT); 992 993 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 994 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 995 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 996 sc->sc_flags |= CBB_CARDEXIST; 997 /* call pccard interrupt handler here */ 998 if (sockstate & CB_SOCKET_STAT_16BIT) { 999 /* 16-bit card found */ 1000 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1001 cardslot_event_throw(sc->sc_csc, 1002 CARDSLOT_EVENT_INSERTION_16); 1003 } else if (sockstate & CB_SOCKET_STAT_CB) { 1004 /* cardbus card found */ 1005 /* cardbus_attach_card(sc->sc_csc); */ 1006 cardslot_event_throw(sc->sc_csc, 1007 CARDSLOT_EVENT_INSERTION_CB); 1008 } else { 1009 /* who are you? */ 1010 } 1011 } else { 1012 callout_reset(&sc->sc_insert_ch, hz / 10, 1013 pci113x_insert, sc); 1014 } 1015 } 1016 1017 #define PCCBB_PCMCIA_OFFSET 0x800 1018 static u_int8_t 1019 pccbb_pcmcia_read(ph, reg) 1020 struct pcic_handle *ph; 1021 int reg; 1022 { 1023 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1024 PCCBB_PCMCIA_OFFSET + reg); 1025 } 1026 1027 static void 1028 pccbb_pcmcia_write(ph, reg, val) 1029 struct pcic_handle *ph; 1030 int reg; 1031 u_int8_t val; 1032 { 1033 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1034 val); 1035 } 1036 1037 /* 1038 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1039 */ 1040 STATIC int 1041 pccbb_ctrl(ct, command) 1042 cardbus_chipset_tag_t ct; 1043 int command; 1044 { 1045 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1046 1047 switch (command) { 1048 case CARDBUS_CD: 1049 if (2 == pccbb_detect_card(sc)) { 1050 int retval = 0; 1051 int status = cb_detect_voltage(sc); 1052 if (PCCARD_VCC_5V & status) { 1053 retval |= CARDBUS_5V_CARD; 1054 } 1055 if (PCCARD_VCC_3V & status) { 1056 retval |= CARDBUS_3V_CARD; 1057 } 1058 if (PCCARD_VCC_XV & status) { 1059 retval |= CARDBUS_XV_CARD; 1060 } 1061 if (PCCARD_VCC_YV & status) { 1062 retval |= CARDBUS_YV_CARD; 1063 } 1064 return retval; 1065 } else { 1066 return 0; 1067 } 1068 break; 1069 case CARDBUS_RESET: 1070 return cb_reset(sc); 1071 break; 1072 case CARDBUS_IO_ENABLE: /* fallthrough */ 1073 case CARDBUS_IO_DISABLE: /* fallthrough */ 1074 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1075 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1076 case CARDBUS_BM_ENABLE: /* fallthrough */ 1077 case CARDBUS_BM_DISABLE: /* fallthrough */ 1078 return pccbb_cardenable(sc, command); 1079 break; 1080 } 1081 1082 return 0; 1083 } 1084 1085 /* 1086 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1087 * This function returns true when it succeeds and returns false when 1088 * it fails. 1089 */ 1090 STATIC int 1091 pccbb_power(ct, command) 1092 cardbus_chipset_tag_t ct; 1093 int command; 1094 { 1095 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1096 1097 u_int32_t status, sock_ctrl; 1098 bus_space_tag_t memt = sc->sc_base_memt; 1099 bus_space_handle_t memh = sc->sc_base_memh; 1100 1101 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1102 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1103 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1104 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1105 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1106 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1107 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1108 "UNKNOWN", 1109 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1110 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1111 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1112 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1113 "UNKNOWN", command)); 1114 1115 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1116 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1117 1118 switch (command & CARDBUS_VCCMASK) { 1119 case CARDBUS_VCC_UC: 1120 break; 1121 case CARDBUS_VCC_5V: 1122 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1123 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1124 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1125 } else { 1126 printf("%s: BAD voltage request: no 5 V card\n", 1127 sc->sc_dev.dv_xname); 1128 } 1129 break; 1130 case CARDBUS_VCC_3V: 1131 if (CB_SOCKET_STAT_3VCARD & status) { 1132 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1133 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1134 } else { 1135 printf("%s: BAD voltage request: no 3.3 V card\n", 1136 sc->sc_dev.dv_xname); 1137 } 1138 break; 1139 case CARDBUS_VCC_0V: 1140 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1141 break; 1142 default: 1143 return 0; /* power NEVER changed */ 1144 break; 1145 } 1146 1147 switch (command & CARDBUS_VPPMASK) { 1148 case CARDBUS_VPP_UC: 1149 break; 1150 case CARDBUS_VPP_0V: 1151 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1152 break; 1153 case CARDBUS_VPP_VCC: 1154 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1155 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1156 break; 1157 case CARDBUS_VPP_12V: 1158 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1159 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1160 break; 1161 } 1162 1163 #if 0 1164 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1165 #endif 1166 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1167 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1168 1169 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1170 /* 1171 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1172 * time is 20 ms, some PC-Card bridge requires longer duration. 1173 */ 1174 delay(200 * 1000); 1175 1176 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1177 printf 1178 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1179 sc->sc_dev.dv_xname, sock_ctrl, status); 1180 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1181 (command & CARDBUS_VCCMASK) == 1182 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1183 CARDBUS_VCCMASK) == 1184 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1185 CARDBUS_VCCMASK) == 1186 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1187 CARDBUS_VCCMASK) == 1188 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1189 CARDBUS_VCCMASK) == 1190 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1191 CARDBUS_VCCMASK) == 1192 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1193 (command & CARDBUS_VPPMASK) == 1194 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1195 CARDBUS_VPPMASK) == 1196 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1197 CARDBUS_VPPMASK) == 1198 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1199 CARDBUS_VPPMASK) == 1200 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1201 #if 0 1202 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1203 u_int32_t force = 1204 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1205 /* Reset Bad Vcc request */ 1206 force &= ~CB_SOCKET_FORCE_BADVCC; 1207 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1208 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1209 CB_SOCKET_STAT)); 1210 return 1; 1211 } 1212 #endif 1213 return 0; 1214 } 1215 return 1; /* power changed correctly */ 1216 } 1217 1218 #if defined CB_PCMCIA_POLL 1219 struct cb_poll_str { 1220 void *arg; 1221 int (*func) __P((void *)); 1222 int level; 1223 pccard_chipset_tag_t ct; 1224 int count; 1225 struct callout poll_ch; 1226 }; 1227 1228 static struct cb_poll_str cb_poll[10]; 1229 static int cb_poll_n = 0; 1230 1231 static void cb_pcmcia_poll __P((void *arg)); 1232 1233 static void 1234 cb_pcmcia_poll(arg) 1235 void *arg; 1236 { 1237 struct cb_poll_str *poll = arg; 1238 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1239 struct pccbb_softc *sc = psc->cpc_parent; 1240 int s; 1241 u_int32_t spsr; /* socket present-state reg */ 1242 1243 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1244 switch (poll->level) { 1245 case IPL_NET: 1246 s = splnet(); 1247 break; 1248 case IPL_BIO: 1249 s = splbio(); 1250 break; 1251 case IPL_TTY: /* fallthrough */ 1252 default: 1253 s = spltty(); 1254 break; 1255 } 1256 1257 spsr = 1258 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1259 CB_SOCKET_STAT); 1260 1261 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1262 if (!(spsr & 0x40)) { /* CINT low */ 1263 #else 1264 if (1) { 1265 #endif 1266 if ((*poll->func) (poll->arg) == 1) { 1267 ++poll->count; 1268 printf("intr: reported from poller, 0x%x\n", spsr); 1269 #if defined LEVEL2 1270 } else { 1271 printf("intr: miss! 0x%x\n", spsr); 1272 #endif 1273 } 1274 } 1275 splx(s); 1276 } 1277 #endif /* defined CB_PCMCIA_POLL */ 1278 1279 /* 1280 * static int pccbb_detect_card(struct pccbb_softc *sc) 1281 * return value: 0 if no card exists. 1282 * 1 if 16-bit card exists. 1283 * 2 if cardbus card exists. 1284 */ 1285 static int 1286 pccbb_detect_card(sc) 1287 struct pccbb_softc *sc; 1288 { 1289 bus_space_handle_t base_memh = sc->sc_base_memh; 1290 bus_space_tag_t base_memt = sc->sc_base_memt; 1291 u_int32_t sockstat = 1292 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1293 int retval = 0; 1294 1295 /* CD1 and CD2 asserted */ 1296 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1297 /* card must be present */ 1298 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1299 /* NOTACARD DEASSERTED */ 1300 if (CB_SOCKET_STAT_CB & sockstat) { 1301 /* CardBus mode */ 1302 retval = 2; 1303 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1304 /* 16-bit mode */ 1305 retval = 1; 1306 } 1307 } 1308 } 1309 return retval; 1310 } 1311 1312 /* 1313 * STATIC int cb_reset(struct pccbb_softc *sc) 1314 * This function resets CardBus card. 1315 */ 1316 STATIC int 1317 cb_reset(sc) 1318 struct pccbb_softc *sc; 1319 { 1320 /* 1321 * Reset Assert at least 20 ms 1322 * Some machines request longer duration. 1323 */ 1324 int reset_duration = 1325 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1326 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1327 1328 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1329 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1330 delay(reset_duration); 1331 1332 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1333 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1334 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1335 delay(reset_duration); 1336 } 1337 /* No card found on the slot. Keep Reset. */ 1338 return 1; 1339 } 1340 1341 /* 1342 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1343 * This function detect card Voltage. 1344 */ 1345 STATIC int 1346 cb_detect_voltage(sc) 1347 struct pccbb_softc *sc; 1348 { 1349 u_int32_t psr; /* socket present-state reg */ 1350 bus_space_tag_t iot = sc->sc_base_memt; 1351 bus_space_handle_t ioh = sc->sc_base_memh; 1352 int vol = PCCARD_VCC_UKN; /* set 0 */ 1353 1354 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1355 1356 if (0x400u & psr) { 1357 vol |= PCCARD_VCC_5V; 1358 } 1359 if (0x800u & psr) { 1360 vol |= PCCARD_VCC_3V; 1361 } 1362 1363 return vol; 1364 } 1365 1366 STATIC int 1367 cbbprint(aux, pcic) 1368 void *aux; 1369 const char *pcic; 1370 { 1371 /* 1372 struct cbslot_attach_args *cba = aux; 1373 1374 if (cba->cba_slot >= 0) { 1375 printf(" slot %d", cba->cba_slot); 1376 } 1377 */ 1378 return UNCONF; 1379 } 1380 1381 /* 1382 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1383 * This function enables and disables the card 1384 */ 1385 STATIC int 1386 pccbb_cardenable(sc, function) 1387 struct pccbb_softc *sc; 1388 int function; 1389 { 1390 u_int32_t command = 1391 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1392 1393 DPRINTF(("pccbb_cardenable:")); 1394 switch (function) { 1395 case CARDBUS_IO_ENABLE: 1396 command |= PCI_COMMAND_IO_ENABLE; 1397 break; 1398 case CARDBUS_IO_DISABLE: 1399 command &= ~PCI_COMMAND_IO_ENABLE; 1400 break; 1401 case CARDBUS_MEM_ENABLE: 1402 command |= PCI_COMMAND_MEM_ENABLE; 1403 break; 1404 case CARDBUS_MEM_DISABLE: 1405 command &= ~PCI_COMMAND_MEM_ENABLE; 1406 break; 1407 case CARDBUS_BM_ENABLE: 1408 command |= PCI_COMMAND_MASTER_ENABLE; 1409 break; 1410 case CARDBUS_BM_DISABLE: 1411 command &= ~PCI_COMMAND_MASTER_ENABLE; 1412 break; 1413 default: 1414 return 0; 1415 } 1416 1417 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1418 DPRINTF((" command reg 0x%x\n", command)); 1419 return 1; 1420 } 1421 1422 #if !rbus 1423 /* 1424 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1425 */ 1426 static int 1427 pccbb_io_open(ct, win, start, end) 1428 cardbus_chipset_tag_t ct; 1429 int win; 1430 u_int32_t start, end; 1431 { 1432 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1433 int basereg; 1434 int limitreg; 1435 1436 if ((win < 0) || (win > 2)) { 1437 #if defined DIAGNOSTIC 1438 printf("cardbus_io_open: window out of range %d\n", win); 1439 #endif 1440 return 0; 1441 } 1442 1443 basereg = win * 8 + 0x2c; 1444 limitreg = win * 8 + 0x30; 1445 1446 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1447 start, basereg, end, limitreg)); 1448 1449 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1450 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1451 return 1; 1452 } 1453 1454 /* 1455 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1456 */ 1457 static int 1458 pccbb_io_close(ct, win) 1459 cardbus_chipset_tag_t ct; 1460 int win; 1461 { 1462 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1463 int basereg; 1464 int limitreg; 1465 1466 if ((win < 0) || (win > 2)) { 1467 #if defined DIAGNOSTIC 1468 printf("cardbus_io_close: window out of range %d\n", win); 1469 #endif 1470 return 0; 1471 } 1472 1473 basereg = win * 8 + 0x2c; 1474 limitreg = win * 8 + 0x30; 1475 1476 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1477 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1478 return 1; 1479 } 1480 1481 /* 1482 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1483 */ 1484 static int 1485 pccbb_mem_open(ct, win, start, end) 1486 cardbus_chipset_tag_t ct; 1487 int win; 1488 u_int32_t start, end; 1489 { 1490 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1491 int basereg; 1492 int limitreg; 1493 1494 if ((win < 0) || (win > 2)) { 1495 #if defined DIAGNOSTIC 1496 printf("cardbus_mem_open: window out of range %d\n", win); 1497 #endif 1498 return 0; 1499 } 1500 1501 basereg = win * 8 + 0x1c; 1502 limitreg = win * 8 + 0x20; 1503 1504 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1505 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1506 return 1; 1507 } 1508 1509 /* 1510 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1511 */ 1512 static int 1513 pccbb_mem_close(ct, win) 1514 cardbus_chipset_tag_t ct; 1515 int win; 1516 { 1517 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1518 int basereg; 1519 int limitreg; 1520 1521 if ((win < 0) || (win > 2)) { 1522 #if defined DIAGNOSTIC 1523 printf("cardbus_mem_close: window out of range %d\n", win); 1524 #endif 1525 return 0; 1526 } 1527 1528 basereg = win * 8 + 0x1c; 1529 limitreg = win * 8 + 0x20; 1530 1531 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1532 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1533 return 1; 1534 } 1535 #endif 1536 1537 /* 1538 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1539 * int irq, 1540 * int level, 1541 * int (* func) __P((void *)), 1542 * void *arg) 1543 * 1544 * This function registers an interrupt handler at the bridge, in 1545 * order not to call the interrupt handlers of child devices when 1546 * a card-deletion interrupt occurs. 1547 * 1548 * The arguments irq and level are not used. 1549 */ 1550 static void * 1551 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1552 cardbus_chipset_tag_t ct; 1553 int irq, level; 1554 int (*func) __P((void *)); 1555 void *arg; 1556 { 1557 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1558 1559 return pccbb_intr_establish(sc, irq, level, func, arg); 1560 } 1561 1562 1563 /* 1564 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1565 * void *ih) 1566 * 1567 * This function removes an interrupt handler pointed by ih. 1568 */ 1569 static void 1570 pccbb_cb_intr_disestablish(ct, ih) 1571 cardbus_chipset_tag_t ct; 1572 void *ih; 1573 { 1574 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1575 1576 pccbb_intr_disestablish(sc, ih); 1577 } 1578 1579 1580 /* 1581 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1582 * int irq, 1583 * int level, 1584 * int (* func) __P((void *)), 1585 * void *arg) 1586 * 1587 * This function registers an interrupt handler at the bridge, in 1588 * order not to call the interrupt handlers of child devices when 1589 * a card-deletion interrupt occurs. 1590 * 1591 * The arguments irq and level are not used. 1592 */ 1593 static void * 1594 pccbb_intr_establish(sc, irq, level, func, arg) 1595 struct pccbb_softc *sc; 1596 int irq, level; 1597 int (*func) __P((void *)); 1598 void *arg; 1599 { 1600 struct pccbb_intrhand_list *pil, *newpil; 1601 1602 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1603 1604 if (sc->sc_pil == NULL) { 1605 /* initialize bridge intr routing */ 1606 1607 switch (sc->sc_chipset) { 1608 case CB_TI113X: 1609 { 1610 pcireg_t cbctrl = 1611 pci_conf_read(sc->sc_pc, sc->sc_tag, 1612 PCI_CBCTRL); 1613 /* functional intr enabled */ 1614 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1615 pci_conf_write(sc->sc_pc, sc->sc_tag, 1616 PCI_CBCTRL, cbctrl); 1617 break; 1618 } 1619 default: 1620 break; 1621 } 1622 } 1623 1624 /* 1625 * Allocate a room for interrupt handler structure. 1626 */ 1627 if (NULL == (newpil = 1628 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1629 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1630 return NULL; 1631 } 1632 1633 newpil->pil_func = func; 1634 newpil->pil_arg = arg; 1635 newpil->pil_next = NULL; 1636 1637 if (sc->sc_pil == NULL) { 1638 sc->sc_pil = newpil; 1639 } else { 1640 for (pil = sc->sc_pil; pil->pil_next != NULL; 1641 pil = pil->pil_next); 1642 pil->pil_next = newpil; 1643 } 1644 1645 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1646 1647 return newpil; 1648 } 1649 1650 /* 1651 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1652 * void *ih) 1653 * 1654 * This function removes an interrupt handler pointed by ih. 1655 */ 1656 static void 1657 pccbb_intr_disestablish(sc, ih) 1658 struct pccbb_softc *sc; 1659 void *ih; 1660 { 1661 struct pccbb_intrhand_list *pil, **pil_prev; 1662 1663 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1664 1665 pil_prev = &sc->sc_pil; 1666 1667 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1668 if (pil == ih) { 1669 *pil_prev = pil->pil_next; 1670 free(pil, M_DEVBUF); 1671 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1672 break; 1673 } 1674 pil_prev = &pil->pil_next; 1675 } 1676 1677 if (sc->sc_pil == NULL) { 1678 /* No interrupt handlers */ 1679 1680 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1681 1682 switch (sc->sc_chipset) { 1683 case CB_TI113X: 1684 { 1685 pcireg_t cbctrl = 1686 pci_conf_read(sc->sc_pc, sc->sc_tag, 1687 PCI_CBCTRL); 1688 /* functional intr disabled */ 1689 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1690 pci_conf_write(sc->sc_pc, sc->sc_tag, 1691 PCI_CBCTRL, cbctrl); 1692 break; 1693 } 1694 default: 1695 break; 1696 } 1697 } 1698 } 1699 1700 #if defined SHOW_REGS 1701 static void 1702 cb_show_regs(pc, tag, memt, memh) 1703 pci_chipset_tag_t pc; 1704 pcitag_t tag; 1705 bus_space_tag_t memt; 1706 bus_space_handle_t memh; 1707 { 1708 int i; 1709 printf("PCI config regs:"); 1710 for (i = 0; i < 0x50; i += 4) { 1711 if (i % 16 == 0) { 1712 printf("\n 0x%02x:", i); 1713 } 1714 printf(" %08x", pci_conf_read(pc, tag, i)); 1715 } 1716 for (i = 0x80; i < 0xb0; i += 4) { 1717 if (i % 16 == 0) { 1718 printf("\n 0x%02x:", i); 1719 } 1720 printf(" %08x", pci_conf_read(pc, tag, i)); 1721 } 1722 1723 if (memh == 0) { 1724 printf("\n"); 1725 return; 1726 } 1727 1728 printf("\nsocket regs:"); 1729 for (i = 0; i <= 0x10; i += 0x04) { 1730 printf(" %08x", bus_space_read_4(memt, memh, i)); 1731 } 1732 printf("\nExCA regs:"); 1733 for (i = 0; i < 0x08; ++i) { 1734 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1735 } 1736 printf("\n"); 1737 return; 1738 } 1739 #endif 1740 1741 /* 1742 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1743 * int busno, int devno, int function) 1744 * This is the function to make a tag to access config space of 1745 * a CardBus Card. It works same as pci_conf_read. 1746 */ 1747 static cardbustag_t 1748 pccbb_make_tag(cc, busno, devno, function) 1749 cardbus_chipset_tag_t cc; 1750 int busno, devno, function; 1751 { 1752 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1753 1754 return pci_make_tag(sc->sc_pc, busno, devno, function); 1755 } 1756 1757 static void 1758 pccbb_free_tag(cc, tag) 1759 cardbus_chipset_tag_t cc; 1760 cardbustag_t tag; 1761 { 1762 } 1763 1764 /* 1765 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1766 * cardbustag_t tag, int offset) 1767 * This is the function to read the config space of a CardBus Card. 1768 * It works same as pci_conf_read. 1769 */ 1770 static cardbusreg_t 1771 pccbb_conf_read(cc, tag, offset) 1772 cardbus_chipset_tag_t cc; 1773 cardbustag_t tag; 1774 int offset; /* register offset */ 1775 { 1776 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1777 1778 return pci_conf_read(sc->sc_pc, tag, offset); 1779 } 1780 1781 /* 1782 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1783 * int offs, cardbusreg_t val) 1784 * This is the function to write the config space of a CardBus Card. 1785 * It works same as pci_conf_write. 1786 */ 1787 static void 1788 pccbb_conf_write(cc, tag, reg, val) 1789 cardbus_chipset_tag_t cc; 1790 cardbustag_t tag; 1791 int reg; /* register offset */ 1792 cardbusreg_t val; 1793 { 1794 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1795 1796 pci_conf_write(sc->sc_pc, tag, reg, val); 1797 } 1798 1799 #if 0 1800 STATIC int 1801 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1802 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1803 int speed, int flags, 1804 bus_space_handle_t * iohp) 1805 #endif 1806 /* 1807 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1808 * bus_addr_t start, bus_size_t size, 1809 * bus_size_t align, 1810 * struct pcmcia_io_handle *pcihp 1811 * 1812 * This function only allocates I/O region for pccard. This function 1813 * never maps the allocated region to pccard I/O area. 1814 * 1815 * XXX: The interface of this function is not very good, I believe. 1816 */ 1817 STATIC int 1818 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1819 pcmcia_chipset_handle_t pch; 1820 bus_addr_t start; /* start address */ 1821 bus_size_t size; 1822 bus_size_t align; 1823 struct pcmcia_io_handle *pcihp; 1824 { 1825 struct pcic_handle *ph = (struct pcic_handle *)pch; 1826 bus_addr_t ioaddr; 1827 int flags = 0; 1828 bus_space_tag_t iot; 1829 bus_space_handle_t ioh; 1830 #if rbus 1831 rbus_tag_t rb; 1832 #endif 1833 if (align == 0) { 1834 align = size; /* XXX: funny??? */ 1835 } 1836 1837 /* 1838 * Allocate some arbitrary I/O space. 1839 */ 1840 1841 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1842 1843 #if rbus 1844 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1845 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1846 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1847 return 1; 1848 } 1849 #else 1850 if (start) { 1851 ioaddr = start; 1852 if (bus_space_map(iot, start, size, 0, &ioh)) { 1853 return 1; 1854 } 1855 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1856 (u_long) ioaddr, (u_long) size)); 1857 } else { 1858 flags |= PCMCIA_IO_ALLOCATED; 1859 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1860 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1861 size, align, 0, 0, &ioaddr, &ioh)) { 1862 /* No room be able to be get. */ 1863 return 1; 1864 } 1865 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1866 (u_long) ioaddr, (u_long) size)); 1867 } 1868 #endif 1869 1870 pcihp->iot = iot; 1871 pcihp->ioh = ioh; 1872 pcihp->addr = ioaddr; 1873 pcihp->size = size; 1874 pcihp->flags = flags; 1875 1876 return 0; 1877 } 1878 1879 /* 1880 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1881 * struct pcmcia_io_handle *pcihp) 1882 * 1883 * This function only frees I/O region for pccard. 1884 * 1885 * XXX: The interface of this function is not very good, I believe. 1886 */ 1887 void 1888 pccbb_pcmcia_io_free(pch, pcihp) 1889 pcmcia_chipset_handle_t pch; 1890 struct pcmcia_io_handle *pcihp; 1891 { 1892 #if !rbus 1893 bus_space_tag_t iot = pcihp->iot; 1894 #endif 1895 bus_space_handle_t ioh = pcihp->ioh; 1896 bus_size_t size = pcihp->size; 1897 1898 #if rbus 1899 struct pccbb_softc *sc = 1900 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1901 rbus_tag_t rb = sc->sc_rbus_iot; 1902 1903 rbus_space_free(rb, ioh, size, NULL); 1904 #else 1905 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1906 bus_space_free(iot, ioh, size); 1907 else 1908 bus_space_unmap(iot, ioh, size); 1909 #endif 1910 } 1911 1912 /* 1913 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1914 * bus_addr_t offset, bus_size_t size, 1915 * struct pcmcia_io_handle *pcihp, 1916 * int *windowp) 1917 * 1918 * This function maps the allocated I/O region to pccard. This function 1919 * never allocates any I/O region for pccard I/O area. I don't 1920 * understand why the original authors of pcmciabus separated alloc and 1921 * map. I believe the two must be unite. 1922 * 1923 * XXX: no wait timing control? 1924 */ 1925 int 1926 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1927 pcmcia_chipset_handle_t pch; 1928 int width; 1929 bus_addr_t offset; 1930 bus_size_t size; 1931 struct pcmcia_io_handle *pcihp; 1932 int *windowp; 1933 { 1934 struct pcic_handle *ph = (struct pcic_handle *)pch; 1935 bus_addr_t ioaddr = pcihp->addr + offset; 1936 int i, win; 1937 #if defined CBB_DEBUG 1938 static char *width_names[] = { "dynamic", "io8", "io16" }; 1939 #endif 1940 1941 /* Sanity check I/O handle. */ 1942 1943 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1944 panic("pccbb_pcmcia_io_map iot is bogus"); 1945 } 1946 1947 /* XXX Sanity check offset/size. */ 1948 1949 win = -1; 1950 for (i = 0; i < PCIC_IO_WINS; i++) { 1951 if ((ph->ioalloc & (1 << i)) == 0) { 1952 win = i; 1953 ph->ioalloc |= (1 << i); 1954 break; 1955 } 1956 } 1957 1958 if (win == -1) { 1959 return 1; 1960 } 1961 1962 *windowp = win; 1963 1964 /* XXX this is pretty gross */ 1965 1966 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1967 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1968 1969 /* XXX wtf is this doing here? */ 1970 1971 #if 0 1972 printf(" port 0x%lx", (u_long) ioaddr); 1973 if (size > 1) { 1974 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1975 } 1976 #endif 1977 1978 ph->io[win].addr = ioaddr; 1979 ph->io[win].size = size; 1980 ph->io[win].width = width; 1981 1982 /* actual dirty register-value changing in the function below. */ 1983 pccbb_pcmcia_do_io_map(ph, win); 1984 1985 return 0; 1986 } 1987 1988 /* 1989 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1990 * 1991 * This function changes register-value to map I/O region for pccard. 1992 */ 1993 static void 1994 pccbb_pcmcia_do_io_map(ph, win) 1995 struct pcic_handle *ph; 1996 int win; 1997 { 1998 static u_int8_t pcic_iowidth[3] = { 1999 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2000 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2001 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2002 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2003 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2004 }; 2005 2006 #define PCIC_SIA_START_LOW 0 2007 #define PCIC_SIA_START_HIGH 1 2008 #define PCIC_SIA_STOP_LOW 2 2009 #define PCIC_SIA_STOP_HIGH 3 2010 2011 int regbase_win = 0x8 + win * 0x04; 2012 u_int8_t ioctl, enable; 2013 2014 DPRINTF( 2015 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2016 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2017 ph->io[win].width * 8)); 2018 2019 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2020 ph->io[win].addr & 0xff); 2021 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2022 (ph->io[win].addr >> 8) & 0xff); 2023 2024 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2025 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2026 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2027 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2028 2029 ioctl = Pcic_read(ph, PCIC_IOCTL); 2030 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2031 switch (win) { 2032 case 0: 2033 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2034 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2035 PCIC_IOCTL_IO0_DATASIZE_MASK); 2036 ioctl |= pcic_iowidth[ph->io[win].width]; 2037 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2038 break; 2039 case 1: 2040 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2041 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2042 PCIC_IOCTL_IO1_DATASIZE_MASK); 2043 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2044 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2045 break; 2046 } 2047 Pcic_write(ph, PCIC_IOCTL, ioctl); 2048 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2049 #if defined CBB_DEBUG 2050 { 2051 u_int8_t start_low = 2052 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2053 u_int8_t start_high = 2054 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2055 u_int8_t stop_low = 2056 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2057 u_int8_t stop_high = 2058 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2059 printf 2060 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2061 start_low, start_high, stop_low, stop_high, ioctl, enable); 2062 } 2063 #endif 2064 } 2065 2066 /* 2067 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2068 * 2069 * This function unmaps I/O region. No return value. 2070 */ 2071 STATIC void 2072 pccbb_pcmcia_io_unmap(pch, win) 2073 pcmcia_chipset_handle_t pch; 2074 int win; 2075 { 2076 struct pcic_handle *ph = (struct pcic_handle *)pch; 2077 int reg; 2078 2079 if (win >= PCIC_IO_WINS || win < 0) { 2080 panic("pccbb_pcmcia_io_unmap: window out of range"); 2081 } 2082 2083 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2084 switch (win) { 2085 case 0: 2086 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2087 break; 2088 case 1: 2089 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2090 break; 2091 } 2092 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2093 2094 ph->ioalloc &= ~(1 << win); 2095 } 2096 2097 /* 2098 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2099 * 2100 * This function enables the card. All information is stored in 2101 * the first argument, pcmcia_chipset_handle_t. 2102 */ 2103 static void 2104 pccbb_pcmcia_wait_ready(ph) 2105 struct pcic_handle *ph; 2106 { 2107 int i; 2108 2109 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2110 Pcic_read(ph, PCIC_IF_STATUS))); 2111 2112 for (i = 0; i < 10000; i++) { 2113 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2114 return; 2115 } 2116 delay(500); 2117 #ifdef CBB_DEBUG 2118 if ((i > 5000) && (i % 100 == 99)) 2119 printf("."); 2120 #endif 2121 } 2122 2123 #ifdef DIAGNOSTIC 2124 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2125 Pcic_read(ph, PCIC_IF_STATUS)); 2126 #endif 2127 } 2128 2129 /* 2130 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2131 * 2132 * This function enables the card. All information is stored in 2133 * the first argument, pcmcia_chipset_handle_t. 2134 */ 2135 STATIC void 2136 pccbb_pcmcia_socket_enable(pch) 2137 pcmcia_chipset_handle_t pch; 2138 { 2139 struct pcic_handle *ph = (struct pcic_handle *)pch; 2140 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2141 int cardtype, win; 2142 u_int8_t power, intr; 2143 pcireg_t spsr; 2144 int voltage; 2145 2146 /* this bit is mostly stolen from pcic_attach_card */ 2147 2148 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2149 2150 /* get card Vcc info */ 2151 2152 spsr = 2153 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2154 CB_SOCKET_STAT); 2155 if (spsr & CB_SOCKET_STAT_5VCARD) { 2156 DPRINTF(("5V card\n")); 2157 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2158 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2159 DPRINTF(("3V card\n")); 2160 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2161 } else { 2162 printf("?V card, 0x%x\n", spsr); /* XXX */ 2163 return; 2164 } 2165 2166 /* assert reset bit */ 2167 intr = Pcic_read(ph, PCIC_INTR); 2168 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2169 Pcic_write(ph, PCIC_INTR, intr); 2170 2171 /* disable socket i/o: negate output enable bit */ 2172 2173 power = Pcic_read(ph, PCIC_PWRCTL); 2174 power &= ~PCIC_PWRCTL_OE; 2175 Pcic_write(ph, PCIC_PWRCTL, power); 2176 2177 /* power down the socket to reset it, clear the card reset pin */ 2178 2179 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2180 2181 /* 2182 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2183 * we are changing Vcc (Toff). 2184 */ 2185 /* delay(300*1000); too much */ 2186 2187 /* power up the socket */ 2188 pccbb_power(sc, voltage); 2189 2190 /* 2191 * wait 100ms until power raise (Tpr) and 20ms to become 2192 * stable (Tsu(Vcc)). 2193 * 2194 * some machines require some more time to be settled 2195 * (another 200ms is added here). 2196 */ 2197 /* delay((100 + 20 + 200)*1000); too much */ 2198 2199 power = Pcic_read(ph, PCIC_PWRCTL); 2200 power |= PCIC_PWRCTL_OE; 2201 Pcic_write(ph, PCIC_PWRCTL, power); 2202 2203 /* 2204 * hold RESET at least 10us. 2205 */ 2206 delay(10); 2207 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2208 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2209 2210 /* clear the reset flag */ 2211 2212 intr |= PCIC_INTR_RESET; 2213 Pcic_write(ph, PCIC_INTR, intr); 2214 2215 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2216 2217 delay(20000); 2218 2219 /* wait for the chip to finish initializing */ 2220 2221 pccbb_pcmcia_wait_ready(ph); 2222 2223 /* zero out the address windows */ 2224 2225 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2226 2227 /* set the card type */ 2228 2229 cardtype = pcmcia_card_gettype(ph->pcmcia); 2230 2231 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2232 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2233 Pcic_write(ph, PCIC_INTR, intr); 2234 2235 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2236 ph->ph_parent->dv_xname, ph->sock, 2237 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2238 2239 /* reinstall all the memory and io mappings */ 2240 2241 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2242 if (ph->memalloc & (1 << win)) { 2243 pccbb_pcmcia_do_mem_map(ph, win); 2244 } 2245 } 2246 2247 for (win = 0; win < PCIC_IO_WINS; ++win) { 2248 if (ph->ioalloc & (1 << win)) { 2249 pccbb_pcmcia_do_io_map(ph, win); 2250 } 2251 } 2252 } 2253 2254 /* 2255 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2256 * 2257 * This function disables the card. All information is stored in 2258 * the first argument, pcmcia_chipset_handle_t. 2259 */ 2260 STATIC void 2261 pccbb_pcmcia_socket_disable(pch) 2262 pcmcia_chipset_handle_t pch; 2263 { 2264 struct pcic_handle *ph = (struct pcic_handle *)pch; 2265 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2266 u_int8_t power, intr; 2267 2268 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2269 2270 /* reset signal asserting... */ 2271 2272 intr = Pcic_read(ph, PCIC_INTR); 2273 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2274 Pcic_write(ph, PCIC_INTR, intr); 2275 delay(2 * 1000); 2276 2277 /* power down the socket */ 2278 power = Pcic_read(ph, PCIC_PWRCTL); 2279 power &= ~PCIC_PWRCTL_OE; 2280 Pcic_write(ph, PCIC_PWRCTL, power); 2281 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2282 /* 2283 * wait 300ms until power fails (Tpf). 2284 */ 2285 delay(300 * 1000); 2286 } 2287 2288 /* 2289 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2290 * 2291 * This function detects whether a card is in the slot or not. 2292 * If a card is inserted, return 1. Otherwise, return 0. 2293 */ 2294 STATIC int 2295 pccbb_pcmcia_card_detect(pch) 2296 pcmcia_chipset_handle_t pch; 2297 { 2298 struct pcic_handle *ph = (struct pcic_handle *)pch; 2299 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2300 2301 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2302 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2303 } 2304 2305 #if 0 2306 STATIC int 2307 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2308 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2309 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2310 #endif 2311 /* 2312 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2313 * bus_size_t size, 2314 * struct pcmcia_mem_handle *pcmhp) 2315 * 2316 * This function only allocates memory region for pccard. This 2317 * function never maps the allocated region to pccard memory area. 2318 * 2319 * XXX: Why the argument of start address is not in? 2320 */ 2321 STATIC int 2322 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2323 pcmcia_chipset_handle_t pch; 2324 bus_size_t size; 2325 struct pcmcia_mem_handle *pcmhp; 2326 { 2327 struct pcic_handle *ph = (struct pcic_handle *)pch; 2328 bus_space_handle_t memh; 2329 bus_addr_t addr; 2330 bus_size_t sizepg; 2331 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2332 #if rbus 2333 rbus_tag_t rb; 2334 #endif 2335 2336 /* out of sc->memh, allocate as many pages as necessary */ 2337 2338 /* convert size to PCIC pages */ 2339 /* 2340 * This is not enough; when the requested region is on the page 2341 * boundaries, this may calculate wrong result. 2342 */ 2343 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2344 #if 0 2345 if (sizepg > PCIC_MAX_MEM_PAGES) { 2346 return 1; 2347 } 2348 #endif 2349 2350 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2351 return 1; 2352 } 2353 2354 addr = 0; /* XXX gcc -Wuninitialized */ 2355 2356 #if rbus 2357 rb = sc->sc_rbus_memt; 2358 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2359 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2360 &addr, &memh)) { 2361 return 1; 2362 } 2363 #else 2364 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2365 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2366 0, /* boundary */ 2367 0, /* flags */ 2368 &addr, &memh)) { 2369 return 1; 2370 } 2371 #endif 2372 2373 DPRINTF( 2374 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2375 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2376 2377 pcmhp->memt = sc->sc_memt; 2378 pcmhp->memh = memh; 2379 pcmhp->addr = addr; 2380 pcmhp->size = size; 2381 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2382 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2383 pcmhp->mhandle = 0; 2384 /* No offset??? Funny. */ 2385 2386 return 0; 2387 } 2388 2389 /* 2390 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2391 * struct pcmcia_mem_handle *pcmhp) 2392 * 2393 * This function release the memory space allocated by the function 2394 * pccbb_pcmcia_mem_alloc(). 2395 */ 2396 STATIC void 2397 pccbb_pcmcia_mem_free(pch, pcmhp) 2398 pcmcia_chipset_handle_t pch; 2399 struct pcmcia_mem_handle *pcmhp; 2400 { 2401 #if rbus 2402 struct pcic_handle *ph = (struct pcic_handle *)pch; 2403 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2404 2405 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2406 #else 2407 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2408 #endif 2409 } 2410 2411 /* 2412 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2413 * 2414 * This function release the memory space allocated by the function 2415 * pccbb_pcmcia_mem_alloc(). 2416 */ 2417 STATIC void 2418 pccbb_pcmcia_do_mem_map(ph, win) 2419 struct pcic_handle *ph; 2420 int win; 2421 { 2422 int regbase_win; 2423 bus_addr_t phys_addr; 2424 bus_addr_t phys_end; 2425 2426 #define PCIC_SMM_START_LOW 0 2427 #define PCIC_SMM_START_HIGH 1 2428 #define PCIC_SMM_STOP_LOW 2 2429 #define PCIC_SMM_STOP_HIGH 3 2430 #define PCIC_CMA_LOW 4 2431 #define PCIC_CMA_HIGH 5 2432 2433 u_int8_t start_low, start_high = 0; 2434 u_int8_t stop_low, stop_high; 2435 u_int8_t off_low, off_high; 2436 u_int8_t mem_window; 2437 int reg; 2438 2439 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2440 int mem8 = 2441 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2442 || (kind == PCMCIA_MEM_ATTR); 2443 2444 regbase_win = 0x10 + win * 0x08; 2445 2446 phys_addr = ph->mem[win].addr; 2447 phys_end = phys_addr + ph->mem[win].size; 2448 2449 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2450 phys_addr, phys_end, ph->mem[win].offset)); 2451 2452 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2453 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2454 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2455 2456 /* bit 19:12 */ 2457 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2458 /* bit 23:20 and bit 7 on */ 2459 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2460 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2461 /* bit 31:24, for 32-bit address */ 2462 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2463 2464 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2465 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2466 2467 if (((struct pccbb_softc *)ph-> 2468 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2469 Pcic_write(ph, 0x40 + win, mem_window); 2470 } 2471 2472 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2473 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2474 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2475 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2476 2477 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2478 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2479 2480 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2481 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2482 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2483 | ((kind == PCMCIA_MEM_ATTR) ? 2484 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2485 2486 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2487 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2488 2489 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2490 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2491 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2492 2493 #if defined CBB_DEBUG 2494 { 2495 int r1, r2, r3, r4, r5, r6, r7 = 0; 2496 2497 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2498 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2499 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2500 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2501 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2502 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2503 if (((struct pccbb_softc *)(ph-> 2504 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2505 r7 = Pcic_read(ph, 0x40 + win); 2506 } 2507 2508 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2509 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2510 if (((struct pccbb_softc *)(ph-> 2511 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2512 DPRINTF((" %02x", r7)); 2513 } 2514 DPRINTF(("\n")); 2515 } 2516 #endif 2517 } 2518 2519 /* 2520 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2521 * bus_addr_t card_addr, bus_size_t size, 2522 * struct pcmcia_mem_handle *pcmhp, 2523 * bus_addr_t *offsetp, int *windowp) 2524 * 2525 * This function maps memory space allocated by the function 2526 * pccbb_pcmcia_mem_alloc(). 2527 */ 2528 STATIC int 2529 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2530 pcmcia_chipset_handle_t pch; 2531 int kind; 2532 bus_addr_t card_addr; 2533 bus_size_t size; 2534 struct pcmcia_mem_handle *pcmhp; 2535 bus_addr_t *offsetp; 2536 int *windowp; 2537 { 2538 struct pcic_handle *ph = (struct pcic_handle *)pch; 2539 bus_addr_t busaddr; 2540 long card_offset; 2541 int win; 2542 2543 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2544 if ((ph->memalloc & (1 << win)) == 0) { 2545 ph->memalloc |= (1 << win); 2546 break; 2547 } 2548 } 2549 2550 if (win == PCIC_MEM_WINS) { 2551 return 1; 2552 } 2553 2554 *windowp = win; 2555 2556 /* XXX this is pretty gross */ 2557 2558 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2559 panic("pccbb_pcmcia_mem_map memt is bogus"); 2560 } 2561 2562 busaddr = pcmhp->addr; 2563 2564 /* 2565 * compute the address offset to the pcmcia address space for the 2566 * pcic. this is intentionally signed. The masks and shifts below 2567 * will cause TRT to happen in the pcic registers. Deal with making 2568 * sure the address is aligned, and return the alignment offset. 2569 */ 2570 2571 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2572 card_addr -= *offsetp; 2573 2574 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2575 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2576 (u_long) card_addr)); 2577 2578 /* 2579 * include the offset in the size, and decrement size by one, since 2580 * the hw wants start/stop 2581 */ 2582 size += *offsetp - 1; 2583 2584 card_offset = (((long)card_addr) - ((long)busaddr)); 2585 2586 ph->mem[win].addr = busaddr; 2587 ph->mem[win].size = size; 2588 ph->mem[win].offset = card_offset; 2589 ph->mem[win].kind = kind; 2590 2591 pccbb_pcmcia_do_mem_map(ph, win); 2592 2593 return 0; 2594 } 2595 2596 /* 2597 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2598 * int window) 2599 * 2600 * This function unmaps memory space which mapped by the function 2601 * pccbb_pcmcia_mem_map(). 2602 */ 2603 STATIC void 2604 pccbb_pcmcia_mem_unmap(pch, window) 2605 pcmcia_chipset_handle_t pch; 2606 int window; 2607 { 2608 struct pcic_handle *ph = (struct pcic_handle *)pch; 2609 int reg; 2610 2611 if (window >= PCIC_MEM_WINS) { 2612 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2613 } 2614 2615 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2616 reg &= ~(1 << window); 2617 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2618 2619 ph->memalloc &= ~(1 << window); 2620 } 2621 2622 #if defined PCCBB_PCMCIA_POLL 2623 struct pccbb_poll_str { 2624 void *arg; 2625 int (*func) __P((void *)); 2626 int level; 2627 struct pcic_handle *ph; 2628 int count; 2629 int num; 2630 struct callout poll_ch; 2631 }; 2632 2633 static struct pccbb_poll_str pccbb_poll[10]; 2634 static int pccbb_poll_n = 0; 2635 2636 static void pccbb_pcmcia_poll __P((void *arg)); 2637 2638 static void 2639 pccbb_pcmcia_poll(arg) 2640 void *arg; 2641 { 2642 struct pccbb_poll_str *poll = arg; 2643 struct pcic_handle *ph = poll->ph; 2644 struct pccbb_softc *sc = ph->sc; 2645 int s; 2646 u_int32_t spsr; /* socket present-state reg */ 2647 2648 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2649 switch (poll->level) { 2650 case IPL_NET: 2651 s = splnet(); 2652 break; 2653 case IPL_BIO: 2654 s = splbio(); 2655 break; 2656 case IPL_TTY: /* fallthrough */ 2657 default: 2658 s = spltty(); 2659 break; 2660 } 2661 2662 spsr = 2663 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2664 CB_SOCKET_STAT); 2665 2666 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2667 if (!(spsr & 0x40)) /* CINT low */ 2668 #else 2669 if (1) 2670 #endif 2671 { 2672 if ((*poll->func) (poll->arg) > 0) { 2673 ++poll->count; 2674 // printf("intr: reported from poller, 0x%x\n", spsr); 2675 #if defined LEVEL2 2676 } else { 2677 printf("intr: miss! 0x%x\n", spsr); 2678 #endif 2679 } 2680 } 2681 splx(s); 2682 } 2683 #endif /* defined CB_PCMCIA_POLL */ 2684 2685 /* 2686 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2687 * struct pcmcia_function *pf, 2688 * int ipl, 2689 * int (*func)(void *), 2690 * void *arg); 2691 * 2692 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2693 */ 2694 STATIC void * 2695 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2696 pcmcia_chipset_handle_t pch; 2697 struct pcmcia_function *pf; 2698 int ipl; 2699 int (*func) __P((void *)); 2700 void *arg; 2701 { 2702 struct pcic_handle *ph = (struct pcic_handle *)pch; 2703 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2704 2705 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2706 /* what should I do? */ 2707 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2708 DPRINTF( 2709 ("%s does not provide edge nor pulse interrupt\n", 2710 sc->sc_dev.dv_xname)); 2711 return NULL; 2712 } 2713 /* 2714 * XXX Noooooo! The interrupt flag must set properly!! 2715 * dumb pcmcia driver!! 2716 */ 2717 } 2718 2719 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2720 } 2721 2722 /* 2723 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2724 * void *ih) 2725 * 2726 * This function disables PC-Card interrupt. 2727 */ 2728 STATIC void 2729 pccbb_pcmcia_intr_disestablish(pch, ih) 2730 pcmcia_chipset_handle_t pch; 2731 void *ih; 2732 { 2733 struct pcic_handle *ph = (struct pcic_handle *)pch; 2734 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2735 2736 pccbb_intr_disestablish(sc, ih); 2737 } 2738 2739 #if rbus 2740 /* 2741 * static int 2742 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2743 * bus_addr_t addr, bus_size_t size, 2744 * bus_addr_t mask, bus_size_t align, 2745 * int flags, bus_addr_t *addrp; 2746 * bus_space_handle_t *bshp) 2747 * 2748 * This function allocates a portion of memory or io space for 2749 * clients. This function is called from CardBus card drivers. 2750 */ 2751 static int 2752 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2753 cardbus_chipset_tag_t ct; 2754 rbus_tag_t rb; 2755 bus_addr_t addr; 2756 bus_size_t size; 2757 bus_addr_t mask; 2758 bus_size_t align; 2759 int flags; 2760 bus_addr_t *addrp; 2761 bus_space_handle_t *bshp; 2762 { 2763 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2764 2765 DPRINTF( 2766 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2767 addr, size, mask, align)); 2768 2769 if (align == 0) { 2770 align = size; 2771 } 2772 2773 if (rb->rb_bt == sc->sc_memt) { 2774 if (align < 16) { 2775 return 1; 2776 } 2777 } else if (rb->rb_bt == sc->sc_iot) { 2778 if (align < 4) { 2779 return 1; 2780 } 2781 /* XXX: hack for avoiding ISA image */ 2782 if (mask < 0x0100) { 2783 mask = 0x3ff; 2784 addr = 0x300; 2785 } 2786 2787 } else { 2788 DPRINTF( 2789 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2790 rb->rb_bt)); 2791 return 1; 2792 /* XXX: panic here? */ 2793 } 2794 2795 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2796 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2797 return 1; 2798 } 2799 2800 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2801 2802 return 0; 2803 } 2804 2805 /* 2806 * static int 2807 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2808 * bus_space_handle_t *bshp, bus_size_t size); 2809 * 2810 * This function is called from CardBus card drivers. 2811 */ 2812 static int 2813 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2814 cardbus_chipset_tag_t ct; 2815 rbus_tag_t rb; 2816 bus_space_handle_t bsh; 2817 bus_size_t size; 2818 { 2819 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2820 bus_space_tag_t bt = rb->rb_bt; 2821 2822 pccbb_close_win(sc, bt, bsh, size); 2823 2824 if (bt == sc->sc_memt) { 2825 } else if (bt == sc->sc_iot) { 2826 } else { 2827 return 1; 2828 /* XXX: panic here? */ 2829 } 2830 2831 return rbus_space_free(rb, bsh, size, NULL); 2832 } 2833 #endif /* rbus */ 2834 2835 #if rbus 2836 2837 static int 2838 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2839 struct pccbb_softc *sc; 2840 bus_space_tag_t bst; 2841 bus_addr_t addr; 2842 bus_size_t size; 2843 bus_space_handle_t bsh; 2844 int flags; 2845 { 2846 struct pccbb_win_chain_head *head; 2847 bus_addr_t align; 2848 2849 head = &sc->sc_iowindow; 2850 align = 0x04; 2851 if (sc->sc_memt == bst) { 2852 head = &sc->sc_memwindow; 2853 align = 0x1000; 2854 DPRINTF(("using memory window, %x %x %x\n\n", 2855 sc->sc_iot, sc->sc_memt, bst)); 2856 } 2857 2858 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2859 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2860 sc->sc_dev.dv_xname, 2861 (head == &sc->sc_memwindow) ? "mem" : "io"); 2862 } 2863 pccbb_winset(align, sc, bst); 2864 2865 return 0; 2866 } 2867 2868 static int 2869 pccbb_close_win(sc, bst, bsh, size) 2870 struct pccbb_softc *sc; 2871 bus_space_tag_t bst; 2872 bus_space_handle_t bsh; 2873 bus_size_t size; 2874 { 2875 struct pccbb_win_chain_head *head; 2876 bus_addr_t align; 2877 2878 head = &sc->sc_iowindow; 2879 align = 0x04; 2880 if (sc->sc_memt == bst) { 2881 head = &sc->sc_memwindow; 2882 align = 0x1000; 2883 } 2884 2885 if (pccbb_winlist_delete(head, bsh, size)) { 2886 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2887 sc->sc_dev.dv_xname, 2888 (head == &sc->sc_memwindow) ? "mem" : "io"); 2889 } 2890 pccbb_winset(align, sc, bst); 2891 2892 return 0; 2893 } 2894 2895 static int 2896 pccbb_winlist_insert(head, start, size, bsh, flags) 2897 struct pccbb_win_chain_head *head; 2898 bus_addr_t start; 2899 bus_size_t size; 2900 bus_space_handle_t bsh; 2901 int flags; 2902 { 2903 struct pccbb_win_chain *chainp, *elem; 2904 2905 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2906 M_NOWAIT)) == NULL) 2907 return (1); /* fail */ 2908 2909 elem->wc_start = start; 2910 elem->wc_end = start + (size - 1); 2911 elem->wc_handle = bsh; 2912 elem->wc_flags = flags; 2913 2914 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2915 chainp = TAILQ_NEXT(chainp, wc_list)) { 2916 if (chainp->wc_end < start) 2917 continue; 2918 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2919 return (0); 2920 } 2921 2922 TAILQ_INSERT_TAIL(head, elem, wc_list); 2923 return (0); 2924 } 2925 2926 static int 2927 pccbb_winlist_delete(head, bsh, size) 2928 struct pccbb_win_chain_head *head; 2929 bus_space_handle_t bsh; 2930 bus_size_t size; 2931 { 2932 struct pccbb_win_chain *chainp; 2933 2934 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2935 chainp = TAILQ_NEXT(chainp, wc_list)) { 2936 if (chainp->wc_handle != bsh) 2937 continue; 2938 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2939 printf("pccbb_winlist_delete: window 0x%lx size " 2940 "inconsistent: 0x%lx, 0x%lx\n", 2941 chainp->wc_start, 2942 chainp->wc_end - chainp->wc_start, 2943 size - 1); 2944 return 1; 2945 } 2946 2947 TAILQ_REMOVE(head, chainp, wc_list); 2948 free(chainp, M_DEVBUF); 2949 2950 return 0; 2951 } 2952 2953 return 1; /* fail: no candidate to remove */ 2954 } 2955 2956 static void 2957 pccbb_winset(align, sc, bst) 2958 bus_addr_t align; 2959 struct pccbb_softc *sc; 2960 bus_space_tag_t bst; 2961 { 2962 pci_chipset_tag_t pc; 2963 pcitag_t tag; 2964 bus_addr_t mask = ~(align - 1); 2965 struct { 2966 cardbusreg_t win_start; 2967 cardbusreg_t win_limit; 2968 int win_flags; 2969 } win[2]; 2970 struct pccbb_win_chain *chainp; 2971 int offs; 2972 2973 win[0].win_start = 0xffffffff; 2974 win[0].win_limit = 0; 2975 win[1].win_start = 0xffffffff; 2976 win[1].win_limit = 0; 2977 2978 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2979 offs = 0x2c; 2980 if (sc->sc_memt == bst) { 2981 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2982 offs = 0x1c; 2983 } 2984 2985 if (chainp != NULL) { 2986 win[0].win_start = chainp->wc_start & mask; 2987 win[0].win_limit = chainp->wc_end & mask; 2988 win[0].win_flags = chainp->wc_flags; 2989 chainp = TAILQ_NEXT(chainp, wc_list); 2990 } 2991 2992 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2993 if (win[1].win_start == 0xffffffff) { 2994 /* window 1 is not used */ 2995 if ((win[0].win_flags == chainp->wc_flags) && 2996 (win[0].win_limit + align >= 2997 (chainp->wc_start & mask))) { 2998 /* concatenate */ 2999 win[0].win_limit = chainp->wc_end & mask; 3000 } else { 3001 /* make new window */ 3002 win[1].win_start = chainp->wc_start & mask; 3003 win[1].win_limit = chainp->wc_end & mask; 3004 win[1].win_flags = chainp->wc_flags; 3005 } 3006 continue; 3007 } 3008 3009 /* Both windows are engaged. */ 3010 if (win[0].win_flags == win[1].win_flags) { 3011 /* same flags */ 3012 if (win[0].win_flags == chainp->wc_flags) { 3013 if (win[1].win_start - (win[0].win_limit + 3014 align) < 3015 (chainp->wc_start & mask) - 3016 ((chainp->wc_end & mask) + align)) { 3017 /* 3018 * merge window 0 and 1, and set win1 3019 * to chainp 3020 */ 3021 win[0].win_limit = win[1].win_limit; 3022 win[1].win_start = 3023 chainp->wc_start & mask; 3024 win[1].win_limit = 3025 chainp->wc_end & mask; 3026 } else { 3027 win[1].win_limit = 3028 chainp->wc_end & mask; 3029 } 3030 } else { 3031 /* different flags */ 3032 3033 /* concatenate win0 and win1 */ 3034 win[0].win_limit = win[1].win_limit; 3035 /* allocate win[1] to new space */ 3036 win[1].win_start = chainp->wc_start & mask; 3037 win[1].win_limit = chainp->wc_end & mask; 3038 win[1].win_flags = chainp->wc_flags; 3039 } 3040 } else { 3041 /* the flags of win[0] and win[1] is different */ 3042 if (win[0].win_flags == chainp->wc_flags) { 3043 win[0].win_limit = chainp->wc_end & mask; 3044 /* 3045 * XXX this creates overlapping windows, so 3046 * what should the poor bridge do if one is 3047 * cachable, and the other is not? 3048 */ 3049 printf("%s: overlapping windows\n", 3050 sc->sc_dev.dv_xname); 3051 } else { 3052 win[1].win_limit = chainp->wc_end & mask; 3053 } 3054 } 3055 } 3056 3057 pc = sc->sc_pc; 3058 tag = sc->sc_tag; 3059 pci_conf_write(pc, tag, offs, win[0].win_start); 3060 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3061 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3062 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3063 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3064 pci_conf_read(pc, tag, offs), 3065 pci_conf_read(pc, tag, offs + 4) + align, 3066 pci_conf_read(pc, tag, offs + 8), 3067 pci_conf_read(pc, tag, offs + 12) + align)); 3068 3069 if (bst == sc->sc_memt) { 3070 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3071 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3072 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3073 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3074 } 3075 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3076 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3077 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3078 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3079 } 3080 } 3081 } 3082 3083 #endif /* rbus */ 3084 3085 static void 3086 pccbb_powerhook(why, arg) 3087 int why; 3088 void *arg; 3089 { 3090 struct pccbb_softc *sc = arg; 3091 u_int32_t reg; 3092 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3093 bus_space_handle_t base_memh = sc->sc_base_memh; 3094 3095 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3096 3097 if (why == PWR_RESUME) { 3098 /* CSC Interrupt: Card detect interrupt on */ 3099 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3100 /* Card detect intr is turned on. */ 3101 reg |= CB_SOCKET_MASK_CD; 3102 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3103 /* reset interrupt */ 3104 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3105 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3106 3107 /* 3108 * check for card insertion or removal during suspend period. 3109 * XXX: the code can't cope with card swap (remove then 3110 * insert). how can we detect such situation? 3111 */ 3112 (void)pccbbintr(sc); 3113 } 3114 } 3115
Indexes created Fri Sep 26 20:09:58 GMT 2025