pccbb.c revision 1.39
1 /* $NetBSD: pccbb.c,v 1.39 2000/05/08 07:31:20 kleink Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 struct yenta_chipinfo *yc; 355 356 /* Loop over except the last default entry. */ 357 for (yc = yc_chipsets; yc < yc_chipsets + 358 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 359 if (pci_id == yc->yc_id) 360 break; 361 362 if (flagp != NULL) 363 *flagp = yc->yc_flags; 364 365 return (yc->yc_chiptype); 366 } 367 368 static void 369 pccbb_shutdown(void *arg) 370 { 371 struct pccbb_softc *sc = arg; 372 pcireg_t command; 373 374 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 375 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 376 0); 377 378 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 379 380 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 381 PCI_COMMAND_MASTER_ENABLE); 382 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 383 384 } 385 386 void 387 pccbbattach(parent, self, aux) 388 struct device *parent; 389 struct device *self; 390 void *aux; 391 { 392 struct pccbb_softc *sc = (void *)self; 393 struct pci_attach_args *pa = aux; 394 pci_chipset_tag_t pc = pa->pa_pc; 395 pcireg_t sock_base, busreg; 396 bus_addr_t sockbase; 397 char devinfo[256]; 398 int flags; 399 400 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 401 402 pci_devinfo(pa->pa_id, 0, 0, devinfo); 403 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 404 #ifdef CBB_DEBUG 405 printf(" (chipflags %x)", flags); 406 #endif 407 printf("\n"); 408 409 TAILQ_INIT(&sc->sc_memwindow); 410 TAILQ_INIT(&sc->sc_iowindow); 411 412 #if rbus 413 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 414 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 415 #endif /* rbus */ 416 417 sc->sc_base_memh = 0; 418 419 /* 420 * MAP socket registers and ExCA registers on memory-space 421 * When no valid address is set on socket base registers (on pci 422 * config space), get it not polite way. 423 */ 424 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 425 426 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 427 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 428 /* The address must be valid. */ 429 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 430 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 431 printf("%s: can't map socket base address 0x%x\n", 432 sc->sc_dev.dv_xname, sock_base); 433 /* 434 * I think it's funny: socket base registers must be 435 * mapped on memory space, but ... 436 */ 437 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 438 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 439 NULL)) { 440 printf("%s: can't map socket base address" 441 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 442 sockbase); 443 /* give up... allocate reg space via rbus. */ 444 sc->sc_base_memh = 0; 445 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 446 } 447 } else { 448 DPRINTF(("%s: socket base address 0x%lx\n", 449 sc->sc_dev.dv_xname, sockbase)); 450 } 451 } 452 453 sc->sc_mem_start = 0; /* XXX */ 454 sc->sc_mem_end = 0xffffffff; /* XXX */ 455 456 /* 457 * When interrupt isn't routed correctly, give up probing cbb and do 458 * not kill pcic-compatible port. 459 */ 460 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 461 printf("%s: NOT USED because of unconfigured interrupt\n", 462 sc->sc_dev.dv_xname); 463 return; 464 } 465 466 /* 467 * When bus number isn't set correctly, give up using 32-bit CardBus 468 * mode. 469 */ 470 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 471 #if notyet 472 if (((busreg >> 8) & 0xff) == 0) { 473 printf("%s: CardBus support disabled because of unconfigured bus number\n", 474 sc->sc_dev.dv_xname); 475 flags |= PCCBB_PCMCIA_16BITONLY; 476 } 477 #endif 478 479 /* pccbb_machdep.c end */ 480 481 #if defined CBB_DEBUG 482 { 483 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 484 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 485 intrname[pa->pa_intrpin], pa->pa_intrline); 486 } 487 #endif 488 489 /* setup softc */ 490 sc->sc_pc = pc; 491 sc->sc_iot = pa->pa_iot; 492 sc->sc_memt = pa->pa_memt; 493 sc->sc_dmat = pa->pa_dmat; 494 sc->sc_tag = pa->pa_tag; 495 sc->sc_function = pa->pa_function; 496 497 sc->sc_intrline = pa->pa_intrline; 498 sc->sc_intrtag = pa->pa_intrtag; 499 sc->sc_intrpin = pa->pa_intrpin; 500 501 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 502 503 shutdownhook_establish(pccbb_shutdown, sc); 504 505 config_defer(self, pccbb_pci_callback); 506 } 507 508 509 510 511 /* 512 * static void pccbb_pci_callback(struct device *self) 513 * 514 * The actual attach routine: get memory space for YENTA register 515 * space, setup YENTA register and route interrupt. 516 * 517 * This function should be deferred because this device may obtain 518 * memory space dynamically. This function must avoid obtaining 519 * memory area which has already kept for another device. Also, 520 * this function MUST be done before ISA attach process because this 521 * function kills pcic compatible port used by ISA pcic. 522 */ 523 static void 524 pccbb_pci_callback(self) 525 struct device *self; 526 { 527 struct pccbb_softc *sc = (void *)self; 528 pci_chipset_tag_t pc = sc->sc_pc; 529 bus_space_tag_t base_memt; 530 bus_space_handle_t base_memh; 531 u_int32_t maskreg; 532 pci_intr_handle_t ih; 533 const char *intrstr = NULL; 534 bus_addr_t sockbase; 535 struct cbslot_attach_args cba; 536 struct pcmciabus_attach_args paa; 537 struct cardslot_attach_args caa; 538 struct cardslot_softc *csc; 539 540 if (0 == sc->sc_base_memh) { 541 /* The socket registers aren't mapped correctly. */ 542 #if rbus 543 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 544 (sc->sc_chipset == CB_RX5C47X 545 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 546 0, &sockbase, &sc->sc_base_memh)) { 547 return; 548 } 549 sc->sc_base_memt = sc->sc_memt; 550 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 551 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 552 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 553 PCI_SOCKBASE))); 554 #else 555 sc->sc_base_memt = sc->sc_memt; 556 #if !defined CBB_PCI_BASE 557 #define CBB_PCI_BASE 0x20000000 558 #endif 559 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 560 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 561 /* cannot allocate memory space */ 562 return; 563 } 564 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 565 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 566 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 567 sc->sc_tag, PCI_SOCKBASE))); 568 #endif 569 } 570 571 /* bus bridge initialization */ 572 pccbb_chipinit(sc); 573 574 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 575 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 576 577 /* CSC Interrupt: Card detect interrupt on */ 578 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 579 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 580 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 581 /* reset interrupt */ 582 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 583 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 584 585 /* clear data structure for child device interrupt handlers */ 586 sc->sc_pil = NULL; 587 sc->sc_pil_intr_enable = 1; 588 589 /* Map and establish the interrupt. */ 590 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 591 sc->sc_intrline, &ih)) { 592 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 593 return; 594 } 595 intrstr = pci_intr_string(pc, ih); 596 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 597 598 if (sc->sc_ih == NULL) { 599 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 600 if (intrstr != NULL) { 601 printf(" at %s", intrstr); 602 } 603 printf("\n"); 604 return; 605 } 606 607 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 608 powerhook_establish(pccbb_powerhook, sc); 609 610 { 611 u_int32_t sockstat = 612 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 613 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 614 sc->sc_flags |= CBB_CARDEXIST; 615 } 616 } 617 618 /* 619 * attach cardbus 620 */ 621 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 622 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 623 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 624 625 /* initialize cbslot_attach */ 626 cba.cba_busname = "cardbus"; 627 cba.cba_iot = sc->sc_iot; 628 cba.cba_memt = sc->sc_memt; 629 cba.cba_dmat = sc->sc_dmat; 630 cba.cba_bus = (busreg >> 8) & 0x0ff; 631 cba.cba_cc = (void *)sc; 632 cba.cba_cf = &pccbb_funcs; 633 cba.cba_intrline = sc->sc_intrline; 634 635 #if rbus 636 cba.cba_rbus_iot = sc->sc_rbus_iot; 637 cba.cba_rbus_memt = sc->sc_rbus_memt; 638 #endif 639 640 cba.cba_cacheline = PCI_CACHELINE(bhlc); 641 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 642 643 printf("%s: cacheline 0x%x lattimer 0x%x\n", 644 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 645 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 646 busreg); 647 #if defined SHOW_REGS 648 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 649 sc->sc_base_memh); 650 #endif 651 } 652 653 pccbb_pcmcia_attach_setup(sc, &paa); 654 caa.caa_cb_attach = NULL; 655 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 656 caa.caa_cb_attach = &cba; 657 } 658 caa.caa_16_attach = &paa; 659 caa.caa_ph = &sc->sc_pcmcia_h; 660 661 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 662 DPRINTF(("pccbbattach: found cardslot\n")); 663 sc->sc_csc = csc; 664 } 665 666 return; 667 } 668 669 670 671 672 673 /* 674 * static void pccbb_chipinit(struct pccbb_softc *sc) 675 * 676 * This function initialize YENTA chip registers listed below: 677 * 1) PCI command reg, 678 * 2) PCI and CardBus latency timer, 679 * 3) disable legacy (PCIC-compatible) io, 680 * 4) route PCI interrupt, 681 * 5) close all memory and io windows. 682 */ 683 static void 684 pccbb_chipinit(sc) 685 struct pccbb_softc *sc; 686 { 687 pci_chipset_tag_t pc = sc->sc_pc; 688 pcitag_t tag = sc->sc_tag; 689 pcireg_t reg; 690 691 /* 692 * Set PCI command reg. 693 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 694 */ 695 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 696 /* I believe it is harmless. */ 697 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 698 PCI_COMMAND_MASTER_ENABLE); 699 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 700 701 /* 702 * Set CardBus latency timer. 703 */ 704 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 705 if (PCI_CB_LATENCY(reg) < 0x20) { 706 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 707 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 708 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 709 } 710 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 711 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 712 713 /* 714 * Set PCI latency timer. 715 */ 716 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 717 if (PCI_LATTIMER(reg) < 0x10) { 718 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 719 reg |= (0x10 << PCI_LATTIMER_SHIFT); 720 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 721 } 722 DPRINTF(("PCI latency timer 0x%x (%x)\n", 723 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 724 725 /* Disable legacy register mapping. */ 726 switch (sc->sc_chipset) { 727 case CB_RX5C46X: /* fallthrough */ 728 #if 0 729 case CB_RX5C47X: 730 #endif 731 /* 732 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 733 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 734 * CardBus bridges have special bits on Bridge control reg (addr 735 * 0x3e on PCI config space). 736 */ 737 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 738 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 739 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 740 break; 741 742 default: 743 /* XXX I don't know proper way to kill legacy I/O. */ 744 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 745 break; 746 } 747 748 /* Route functional interrupts to PCI. */ 749 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 750 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 751 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 752 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 753 754 switch (sc->sc_chipset) { 755 case CB_TI113X: 756 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 757 /* This bit is shared, but may read as 0 on some chips, so set 758 it explicitly on both functions. */ 759 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 760 /* CSC intr enable */ 761 reg |= PCI113X_CBCTRL_PCI_CSC; 762 /* functional intr prohibit */ 763 reg &= ~PCI113X_CBCTRL_PCI_INTR; 764 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 765 break; 766 767 case CB_TOPIC95B: 768 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 769 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 770 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 771 772 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 773 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 774 sc->sc_dev.dv_xname, reg)); 775 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 776 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 777 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 778 DPRINTF(("0x%x\n", reg)); 779 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 780 break; 781 } 782 783 /* Close all memory and I/O windows. */ 784 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 785 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 786 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 787 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 788 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 789 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 790 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 791 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 792 } 793 794 795 796 797 /* 798 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 799 * struct pcmciabus_attach_args *paa) 800 * 801 * This function attaches 16-bit PCcard bus. 802 */ 803 STATIC void 804 pccbb_pcmcia_attach_setup(sc, paa) 805 struct pccbb_softc *sc; 806 struct pcmciabus_attach_args *paa; 807 { 808 struct pcic_handle *ph = &sc->sc_pcmcia_h; 809 #if rbus 810 rbus_tag_t rb; 811 #endif 812 813 /* initialize pcmcia part in pccbb_softc */ 814 ph->ph_parent = (struct device *)sc; 815 ph->sock = sc->sc_function; 816 ph->flags = 0; 817 ph->shutdown = 0; 818 ph->ih_irq = sc->sc_intrline; 819 ph->ph_bus_t = sc->sc_base_memt; 820 ph->ph_bus_h = sc->sc_base_memh; 821 ph->ph_read = pccbb_pcmcia_read; 822 ph->ph_write = pccbb_pcmcia_write; 823 sc->sc_pct = &pccbb_pcmcia_funcs; 824 825 /* 826 * We need to do a few things here: 827 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 828 * setting the IRQ numbers to 0. 829 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 830 * routing of CSC interrupts (e.g. card removal) to PCI while in 831 * PCMCIA mode. We just leave this set all the time. 832 * 3) Enable card insertion/removal interrupts in case the chip also 833 * needs that while in PCMCIA mode. 834 * 4) Clear any pending CSC interrupt. 835 */ 836 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 837 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 838 Pcic_read(ph, PCIC_CSC); 839 840 /* initialize pcmcia bus attachment */ 841 paa->paa_busname = "pcmcia"; 842 paa->pct = sc->sc_pct; 843 paa->pch = ph; 844 paa->iobase = 0; /* I don't use them */ 845 paa->iosize = 0; 846 #if rbus 847 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 848 paa->iobase = rb->rb_start + rb->rb_offset; 849 paa->iosize = rb->rb_end - rb->rb_start; 850 #endif 851 852 return; 853 } 854 855 #if 0 856 STATIC void 857 pccbb_pcmcia_attach_card(ph) 858 struct pcic_handle *ph; 859 { 860 if (ph->flags & PCIC_FLAG_CARDP) { 861 panic("pccbb_pcmcia_attach_card: already attached"); 862 } 863 864 /* call the MI attach function */ 865 pcmcia_card_attach(ph->pcmcia); 866 867 ph->flags |= PCIC_FLAG_CARDP; 868 } 869 870 STATIC void 871 pccbb_pcmcia_detach_card(ph, flags) 872 struct pcic_handle *ph; 873 int flags; 874 { 875 if (!(ph->flags & PCIC_FLAG_CARDP)) { 876 panic("pccbb_pcmcia_detach_card: already detached"); 877 } 878 879 ph->flags &= ~PCIC_FLAG_CARDP; 880 881 /* call the MI detach function */ 882 pcmcia_card_detach(ph->pcmcia, flags); 883 } 884 #endif 885 886 /* 887 * int pccbbintr(arg) 888 * void *arg; 889 * This routine handles the interrupt from Yenta PCI-CardBus bridge 890 * itself. 891 */ 892 int 893 pccbbintr(arg) 894 void *arg; 895 { 896 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 897 u_int32_t sockevent, sockstate; 898 bus_space_tag_t memt = sc->sc_base_memt; 899 bus_space_handle_t memh = sc->sc_base_memh; 900 struct pcic_handle *ph = &sc->sc_pcmcia_h; 901 902 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 903 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 904 Pcic_read(ph, PCIC_CSC); 905 906 if (sockevent == 0) { 907 /* This intr is not for me: it may be for my child devices. */ 908 if (sc->sc_pil_intr_enable) { 909 return pccbbintr_function(sc); 910 } else { 911 return 0; 912 } 913 } 914 915 if (sockevent & CB_SOCKET_EVENT_CD) { 916 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 917 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 918 /* A card should be removed. */ 919 if (sc->sc_flags & CBB_CARDEXIST) { 920 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 921 sockevent)); 922 DPRINTF((" card removed, 0x%08x\n", sockstate)); 923 sc->sc_flags &= ~CBB_CARDEXIST; 924 if (sc->sc_csc->sc_status & 925 CARDSLOT_STATUS_CARD_16) { 926 #if 0 927 struct pcic_handle *ph = 928 &sc->sc_pcmcia_h; 929 930 pcmcia_card_deactivate(ph->pcmcia); 931 pccbb_pcmcia_socket_disable(ph); 932 pccbb_pcmcia_detach_card(ph, 933 DETACH_FORCE); 934 #endif 935 cardslot_event_throw(sc->sc_csc, 936 CARDSLOT_EVENT_REMOVAL_16); 937 } else if (sc->sc_csc->sc_status & 938 CARDSLOT_STATUS_CARD_CB) { 939 /* Cardbus intr removed */ 940 cardslot_event_throw(sc->sc_csc, 941 CARDSLOT_EVENT_REMOVAL_CB); 942 } 943 } 944 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 945 /* 946 * The pccbbintr may called from powerdown hook when 947 * the system resumed, to detect the card 948 * insertion/removal during suspension. 949 */ 950 (sc->sc_flags & CBB_CARDEXIST) == 0) { 951 if (sc->sc_flags & CBB_INSERTING) { 952 callout_stop(&sc->sc_insert_ch); 953 } 954 callout_reset(&sc->sc_insert_ch, hz / 10, 955 pci113x_insert, sc); 956 sc->sc_flags |= CBB_INSERTING; 957 } 958 } 959 960 return (1); 961 } 962 963 /* 964 * static int pccbbintr_function(struct pccbb_softc *sc) 965 * 966 * This function calls each interrupt handler registered at the 967 * bridge. The interrupt handlers are called in registered order. 968 */ 969 static int 970 pccbbintr_function(sc) 971 struct pccbb_softc *sc; 972 { 973 int retval = 0, val; 974 struct pccbb_intrhand_list *pil; 975 976 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 977 val = (*pil->pil_func) (pil->pil_arg); 978 retval = retval == 1 ? 1 : 979 retval == 0 ? val : val != 0 ? val : retval; 980 } 981 982 return retval; 983 } 984 985 static void 986 pci113x_insert(arg) 987 void *arg; 988 { 989 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 990 u_int32_t sockevent, sockstate; 991 992 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 993 CB_SOCKET_EVENT); 994 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 995 CB_SOCKET_STAT); 996 997 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 998 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 999 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1000 sc->sc_flags |= CBB_CARDEXIST; 1001 /* call pccard interrupt handler here */ 1002 if (sockstate & CB_SOCKET_STAT_16BIT) { 1003 /* 16-bit card found */ 1004 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1005 cardslot_event_throw(sc->sc_csc, 1006 CARDSLOT_EVENT_INSERTION_16); 1007 } else if (sockstate & CB_SOCKET_STAT_CB) { 1008 /* cardbus card found */ 1009 /* cardbus_attach_card(sc->sc_csc); */ 1010 cardslot_event_throw(sc->sc_csc, 1011 CARDSLOT_EVENT_INSERTION_CB); 1012 } else { 1013 /* who are you? */ 1014 } 1015 } else { 1016 callout_reset(&sc->sc_insert_ch, hz / 10, 1017 pci113x_insert, sc); 1018 } 1019 } 1020 1021 #define PCCBB_PCMCIA_OFFSET 0x800 1022 static u_int8_t 1023 pccbb_pcmcia_read(ph, reg) 1024 struct pcic_handle *ph; 1025 int reg; 1026 { 1027 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1028 PCCBB_PCMCIA_OFFSET + reg); 1029 } 1030 1031 static void 1032 pccbb_pcmcia_write(ph, reg, val) 1033 struct pcic_handle *ph; 1034 int reg; 1035 u_int8_t val; 1036 { 1037 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1038 val); 1039 } 1040 1041 /* 1042 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1043 */ 1044 STATIC int 1045 pccbb_ctrl(ct, command) 1046 cardbus_chipset_tag_t ct; 1047 int command; 1048 { 1049 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1050 1051 switch (command) { 1052 case CARDBUS_CD: 1053 if (2 == pccbb_detect_card(sc)) { 1054 int retval = 0; 1055 int status = cb_detect_voltage(sc); 1056 if (PCCARD_VCC_5V & status) { 1057 retval |= CARDBUS_5V_CARD; 1058 } 1059 if (PCCARD_VCC_3V & status) { 1060 retval |= CARDBUS_3V_CARD; 1061 } 1062 if (PCCARD_VCC_XV & status) { 1063 retval |= CARDBUS_XV_CARD; 1064 } 1065 if (PCCARD_VCC_YV & status) { 1066 retval |= CARDBUS_YV_CARD; 1067 } 1068 return retval; 1069 } else { 1070 return 0; 1071 } 1072 break; 1073 case CARDBUS_RESET: 1074 return cb_reset(sc); 1075 break; 1076 case CARDBUS_IO_ENABLE: /* fallthrough */ 1077 case CARDBUS_IO_DISABLE: /* fallthrough */ 1078 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1079 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1080 case CARDBUS_BM_ENABLE: /* fallthrough */ 1081 case CARDBUS_BM_DISABLE: /* fallthrough */ 1082 return pccbb_cardenable(sc, command); 1083 break; 1084 } 1085 1086 return 0; 1087 } 1088 1089 /* 1090 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1091 * This function returns true when it succeeds and returns false when 1092 * it fails. 1093 */ 1094 STATIC int 1095 pccbb_power(ct, command) 1096 cardbus_chipset_tag_t ct; 1097 int command; 1098 { 1099 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1100 1101 u_int32_t status, sock_ctrl; 1102 bus_space_tag_t memt = sc->sc_base_memt; 1103 bus_space_handle_t memh = sc->sc_base_memh; 1104 1105 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1106 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1107 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1108 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1109 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1110 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1111 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1112 "UNKNOWN", 1113 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1114 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1115 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1116 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1117 "UNKNOWN", command)); 1118 1119 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1120 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1121 1122 switch (command & CARDBUS_VCCMASK) { 1123 case CARDBUS_VCC_UC: 1124 break; 1125 case CARDBUS_VCC_5V: 1126 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1127 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1128 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1129 } else { 1130 printf("%s: BAD voltage request: no 5 V card\n", 1131 sc->sc_dev.dv_xname); 1132 } 1133 break; 1134 case CARDBUS_VCC_3V: 1135 if (CB_SOCKET_STAT_3VCARD & status) { 1136 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1137 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1138 } else { 1139 printf("%s: BAD voltage request: no 3.3 V card\n", 1140 sc->sc_dev.dv_xname); 1141 } 1142 break; 1143 case CARDBUS_VCC_0V: 1144 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1145 break; 1146 default: 1147 return 0; /* power NEVER changed */ 1148 break; 1149 } 1150 1151 switch (command & CARDBUS_VPPMASK) { 1152 case CARDBUS_VPP_UC: 1153 break; 1154 case CARDBUS_VPP_0V: 1155 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1156 break; 1157 case CARDBUS_VPP_VCC: 1158 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1159 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1160 break; 1161 case CARDBUS_VPP_12V: 1162 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1163 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1164 break; 1165 } 1166 1167 #if 0 1168 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1169 #endif 1170 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1171 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1172 1173 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1174 /* 1175 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1176 * time is 20 ms, some PC-Card bridge requires longer duration. 1177 */ 1178 delay(200 * 1000); 1179 1180 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1181 printf 1182 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1183 sc->sc_dev.dv_xname, sock_ctrl, status); 1184 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1185 (command & CARDBUS_VCCMASK) == 1186 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1187 CARDBUS_VCCMASK) == 1188 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1189 CARDBUS_VCCMASK) == 1190 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1191 CARDBUS_VCCMASK) == 1192 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1193 CARDBUS_VCCMASK) == 1194 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1195 CARDBUS_VCCMASK) == 1196 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1197 (command & CARDBUS_VPPMASK) == 1198 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1199 CARDBUS_VPPMASK) == 1200 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1201 CARDBUS_VPPMASK) == 1202 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1203 CARDBUS_VPPMASK) == 1204 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1205 #if 0 1206 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1207 u_int32_t force = 1208 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1209 /* Reset Bad Vcc request */ 1210 force &= ~CB_SOCKET_FORCE_BADVCC; 1211 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1212 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1213 CB_SOCKET_STAT)); 1214 return 1; 1215 } 1216 #endif 1217 return 0; 1218 } 1219 return 1; /* power changed correctly */ 1220 } 1221 1222 #if defined CB_PCMCIA_POLL 1223 struct cb_poll_str { 1224 void *arg; 1225 int (*func) __P((void *)); 1226 int level; 1227 pccard_chipset_tag_t ct; 1228 int count; 1229 struct callout poll_ch; 1230 }; 1231 1232 static struct cb_poll_str cb_poll[10]; 1233 static int cb_poll_n = 0; 1234 1235 static void cb_pcmcia_poll __P((void *arg)); 1236 1237 static void 1238 cb_pcmcia_poll(arg) 1239 void *arg; 1240 { 1241 struct cb_poll_str *poll = arg; 1242 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1243 struct pccbb_softc *sc = psc->cpc_parent; 1244 int s; 1245 u_int32_t spsr; /* socket present-state reg */ 1246 1247 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1248 switch (poll->level) { 1249 case IPL_NET: 1250 s = splnet(); 1251 break; 1252 case IPL_BIO: 1253 s = splbio(); 1254 break; 1255 case IPL_TTY: /* fallthrough */ 1256 default: 1257 s = spltty(); 1258 break; 1259 } 1260 1261 spsr = 1262 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1263 CB_SOCKET_STAT); 1264 1265 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1266 if (!(spsr & 0x40)) { /* CINT low */ 1267 #else 1268 if (1) { 1269 #endif 1270 if ((*poll->func) (poll->arg) == 1) { 1271 ++poll->count; 1272 printf("intr: reported from poller, 0x%x\n", spsr); 1273 #if defined LEVEL2 1274 } else { 1275 printf("intr: miss! 0x%x\n", spsr); 1276 #endif 1277 } 1278 } 1279 splx(s); 1280 } 1281 #endif /* defined CB_PCMCIA_POLL */ 1282 1283 /* 1284 * static int pccbb_detect_card(struct pccbb_softc *sc) 1285 * return value: 0 if no card exists. 1286 * 1 if 16-bit card exists. 1287 * 2 if cardbus card exists. 1288 */ 1289 static int 1290 pccbb_detect_card(sc) 1291 struct pccbb_softc *sc; 1292 { 1293 bus_space_handle_t base_memh = sc->sc_base_memh; 1294 bus_space_tag_t base_memt = sc->sc_base_memt; 1295 u_int32_t sockstat = 1296 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1297 int retval = 0; 1298 1299 /* CD1 and CD2 asserted */ 1300 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1301 /* card must be present */ 1302 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1303 /* NOTACARD DEASSERTED */ 1304 if (CB_SOCKET_STAT_CB & sockstat) { 1305 /* CardBus mode */ 1306 retval = 2; 1307 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1308 /* 16-bit mode */ 1309 retval = 1; 1310 } 1311 } 1312 } 1313 return retval; 1314 } 1315 1316 /* 1317 * STATIC int cb_reset(struct pccbb_softc *sc) 1318 * This function resets CardBus card. 1319 */ 1320 STATIC int 1321 cb_reset(sc) 1322 struct pccbb_softc *sc; 1323 { 1324 /* 1325 * Reset Assert at least 20 ms 1326 * Some machines request longer duration. 1327 */ 1328 int reset_duration = 1329 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1330 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1331 1332 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1333 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1334 delay(reset_duration); 1335 1336 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1337 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1338 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1339 delay(reset_duration); 1340 } 1341 /* No card found on the slot. Keep Reset. */ 1342 return 1; 1343 } 1344 1345 /* 1346 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1347 * This function detect card Voltage. 1348 */ 1349 STATIC int 1350 cb_detect_voltage(sc) 1351 struct pccbb_softc *sc; 1352 { 1353 u_int32_t psr; /* socket present-state reg */ 1354 bus_space_tag_t iot = sc->sc_base_memt; 1355 bus_space_handle_t ioh = sc->sc_base_memh; 1356 int vol = PCCARD_VCC_UKN; /* set 0 */ 1357 1358 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1359 1360 if (0x400u & psr) { 1361 vol |= PCCARD_VCC_5V; 1362 } 1363 if (0x800u & psr) { 1364 vol |= PCCARD_VCC_3V; 1365 } 1366 1367 return vol; 1368 } 1369 1370 STATIC int 1371 cbbprint(aux, pcic) 1372 void *aux; 1373 const char *pcic; 1374 { 1375 /* 1376 struct cbslot_attach_args *cba = aux; 1377 1378 if (cba->cba_slot >= 0) { 1379 printf(" slot %d", cba->cba_slot); 1380 } 1381 */ 1382 return UNCONF; 1383 } 1384 1385 /* 1386 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1387 * This function enables and disables the card 1388 */ 1389 STATIC int 1390 pccbb_cardenable(sc, function) 1391 struct pccbb_softc *sc; 1392 int function; 1393 { 1394 u_int32_t command = 1395 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1396 1397 DPRINTF(("pccbb_cardenable:")); 1398 switch (function) { 1399 case CARDBUS_IO_ENABLE: 1400 command |= PCI_COMMAND_IO_ENABLE; 1401 break; 1402 case CARDBUS_IO_DISABLE: 1403 command &= ~PCI_COMMAND_IO_ENABLE; 1404 break; 1405 case CARDBUS_MEM_ENABLE: 1406 command |= PCI_COMMAND_MEM_ENABLE; 1407 break; 1408 case CARDBUS_MEM_DISABLE: 1409 command &= ~PCI_COMMAND_MEM_ENABLE; 1410 break; 1411 case CARDBUS_BM_ENABLE: 1412 command |= PCI_COMMAND_MASTER_ENABLE; 1413 break; 1414 case CARDBUS_BM_DISABLE: 1415 command &= ~PCI_COMMAND_MASTER_ENABLE; 1416 break; 1417 default: 1418 return 0; 1419 } 1420 1421 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1422 DPRINTF((" command reg 0x%x\n", command)); 1423 return 1; 1424 } 1425 1426 #if !rbus 1427 /* 1428 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1429 */ 1430 static int 1431 pccbb_io_open(ct, win, start, end) 1432 cardbus_chipset_tag_t ct; 1433 int win; 1434 u_int32_t start, end; 1435 { 1436 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1437 int basereg; 1438 int limitreg; 1439 1440 if ((win < 0) || (win > 2)) { 1441 #if defined DIAGNOSTIC 1442 printf("cardbus_io_open: window out of range %d\n", win); 1443 #endif 1444 return 0; 1445 } 1446 1447 basereg = win * 8 + 0x2c; 1448 limitreg = win * 8 + 0x30; 1449 1450 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1451 start, basereg, end, limitreg)); 1452 1453 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1454 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1455 return 1; 1456 } 1457 1458 /* 1459 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1460 */ 1461 static int 1462 pccbb_io_close(ct, win) 1463 cardbus_chipset_tag_t ct; 1464 int win; 1465 { 1466 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1467 int basereg; 1468 int limitreg; 1469 1470 if ((win < 0) || (win > 2)) { 1471 #if defined DIAGNOSTIC 1472 printf("cardbus_io_close: window out of range %d\n", win); 1473 #endif 1474 return 0; 1475 } 1476 1477 basereg = win * 8 + 0x2c; 1478 limitreg = win * 8 + 0x30; 1479 1480 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1481 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1482 return 1; 1483 } 1484 1485 /* 1486 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1487 */ 1488 static int 1489 pccbb_mem_open(ct, win, start, end) 1490 cardbus_chipset_tag_t ct; 1491 int win; 1492 u_int32_t start, end; 1493 { 1494 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1495 int basereg; 1496 int limitreg; 1497 1498 if ((win < 0) || (win > 2)) { 1499 #if defined DIAGNOSTIC 1500 printf("cardbus_mem_open: window out of range %d\n", win); 1501 #endif 1502 return 0; 1503 } 1504 1505 basereg = win * 8 + 0x1c; 1506 limitreg = win * 8 + 0x20; 1507 1508 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1509 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1510 return 1; 1511 } 1512 1513 /* 1514 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1515 */ 1516 static int 1517 pccbb_mem_close(ct, win) 1518 cardbus_chipset_tag_t ct; 1519 int win; 1520 { 1521 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1522 int basereg; 1523 int limitreg; 1524 1525 if ((win < 0) || (win > 2)) { 1526 #if defined DIAGNOSTIC 1527 printf("cardbus_mem_close: window out of range %d\n", win); 1528 #endif 1529 return 0; 1530 } 1531 1532 basereg = win * 8 + 0x1c; 1533 limitreg = win * 8 + 0x20; 1534 1535 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1536 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1537 return 1; 1538 } 1539 #endif 1540 1541 /* 1542 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1543 * int irq, 1544 * int level, 1545 * int (* func) __P((void *)), 1546 * void *arg) 1547 * 1548 * This function registers an interrupt handler at the bridge, in 1549 * order not to call the interrupt handlers of child devices when 1550 * a card-deletion interrupt occurs. 1551 * 1552 * The arguments irq and level are not used. 1553 */ 1554 static void * 1555 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1556 cardbus_chipset_tag_t ct; 1557 int irq, level; 1558 int (*func) __P((void *)); 1559 void *arg; 1560 { 1561 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1562 1563 return pccbb_intr_establish(sc, irq, level, func, arg); 1564 } 1565 1566 1567 /* 1568 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1569 * void *ih) 1570 * 1571 * This function removes an interrupt handler pointed by ih. 1572 */ 1573 static void 1574 pccbb_cb_intr_disestablish(ct, ih) 1575 cardbus_chipset_tag_t ct; 1576 void *ih; 1577 { 1578 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1579 1580 pccbb_intr_disestablish(sc, ih); 1581 } 1582 1583 1584 /* 1585 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1586 * int irq, 1587 * int level, 1588 * int (* func) __P((void *)), 1589 * void *arg) 1590 * 1591 * This function registers an interrupt handler at the bridge, in 1592 * order not to call the interrupt handlers of child devices when 1593 * a card-deletion interrupt occurs. 1594 * 1595 * The arguments irq and level are not used. 1596 */ 1597 static void * 1598 pccbb_intr_establish(sc, irq, level, func, arg) 1599 struct pccbb_softc *sc; 1600 int irq, level; 1601 int (*func) __P((void *)); 1602 void *arg; 1603 { 1604 struct pccbb_intrhand_list *pil, *newpil; 1605 1606 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1607 1608 if (sc->sc_pil == NULL) { 1609 /* initialize bridge intr routing */ 1610 1611 switch (sc->sc_chipset) { 1612 case CB_TI113X: 1613 { 1614 pcireg_t cbctrl = 1615 pci_conf_read(sc->sc_pc, sc->sc_tag, 1616 PCI_CBCTRL); 1617 /* functional intr enabled */ 1618 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1619 pci_conf_write(sc->sc_pc, sc->sc_tag, 1620 PCI_CBCTRL, cbctrl); 1621 break; 1622 } 1623 default: 1624 break; 1625 } 1626 } 1627 1628 /* 1629 * Allocate a room for interrupt handler structure. 1630 */ 1631 if (NULL == (newpil = 1632 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1633 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1634 return NULL; 1635 } 1636 1637 newpil->pil_func = func; 1638 newpil->pil_arg = arg; 1639 newpil->pil_next = NULL; 1640 1641 if (sc->sc_pil == NULL) { 1642 sc->sc_pil = newpil; 1643 } else { 1644 for (pil = sc->sc_pil; pil->pil_next != NULL; 1645 pil = pil->pil_next); 1646 pil->pil_next = newpil; 1647 } 1648 1649 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1650 1651 return newpil; 1652 } 1653 1654 /* 1655 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1656 * void *ih) 1657 * 1658 * This function removes an interrupt handler pointed by ih. 1659 */ 1660 static void 1661 pccbb_intr_disestablish(sc, ih) 1662 struct pccbb_softc *sc; 1663 void *ih; 1664 { 1665 struct pccbb_intrhand_list *pil, **pil_prev; 1666 1667 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1668 1669 pil_prev = &sc->sc_pil; 1670 1671 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1672 if (pil == ih) { 1673 *pil_prev = pil->pil_next; 1674 free(pil, M_DEVBUF); 1675 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1676 break; 1677 } 1678 pil_prev = &pil->pil_next; 1679 } 1680 1681 if (sc->sc_pil == NULL) { 1682 /* No interrupt handlers */ 1683 1684 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1685 1686 switch (sc->sc_chipset) { 1687 case CB_TI113X: 1688 { 1689 pcireg_t cbctrl = 1690 pci_conf_read(sc->sc_pc, sc->sc_tag, 1691 PCI_CBCTRL); 1692 /* functional intr disabled */ 1693 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1694 pci_conf_write(sc->sc_pc, sc->sc_tag, 1695 PCI_CBCTRL, cbctrl); 1696 break; 1697 } 1698 default: 1699 break; 1700 } 1701 } 1702 } 1703 1704 #if defined SHOW_REGS 1705 static void 1706 cb_show_regs(pc, tag, memt, memh) 1707 pci_chipset_tag_t pc; 1708 pcitag_t tag; 1709 bus_space_tag_t memt; 1710 bus_space_handle_t memh; 1711 { 1712 int i; 1713 printf("PCI config regs:"); 1714 for (i = 0; i < 0x50; i += 4) { 1715 if (i % 16 == 0) { 1716 printf("\n 0x%02x:", i); 1717 } 1718 printf(" %08x", pci_conf_read(pc, tag, i)); 1719 } 1720 for (i = 0x80; i < 0xb0; i += 4) { 1721 if (i % 16 == 0) { 1722 printf("\n 0x%02x:", i); 1723 } 1724 printf(" %08x", pci_conf_read(pc, tag, i)); 1725 } 1726 1727 if (memh == 0) { 1728 printf("\n"); 1729 return; 1730 } 1731 1732 printf("\nsocket regs:"); 1733 for (i = 0; i <= 0x10; i += 0x04) { 1734 printf(" %08x", bus_space_read_4(memt, memh, i)); 1735 } 1736 printf("\nExCA regs:"); 1737 for (i = 0; i < 0x08; ++i) { 1738 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1739 } 1740 printf("\n"); 1741 return; 1742 } 1743 #endif 1744 1745 /* 1746 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1747 * int busno, int devno, int function) 1748 * This is the function to make a tag to access config space of 1749 * a CardBus Card. It works same as pci_conf_read. 1750 */ 1751 static cardbustag_t 1752 pccbb_make_tag(cc, busno, devno, function) 1753 cardbus_chipset_tag_t cc; 1754 int busno, devno, function; 1755 { 1756 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1757 1758 return pci_make_tag(sc->sc_pc, busno, devno, function); 1759 } 1760 1761 static void 1762 pccbb_free_tag(cc, tag) 1763 cardbus_chipset_tag_t cc; 1764 cardbustag_t tag; 1765 { 1766 } 1767 1768 /* 1769 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1770 * cardbustag_t tag, int offset) 1771 * This is the function to read the config space of a CardBus Card. 1772 * It works same as pci_conf_read. 1773 */ 1774 static cardbusreg_t 1775 pccbb_conf_read(cc, tag, offset) 1776 cardbus_chipset_tag_t cc; 1777 cardbustag_t tag; 1778 int offset; /* register offset */ 1779 { 1780 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1781 1782 return pci_conf_read(sc->sc_pc, tag, offset); 1783 } 1784 1785 /* 1786 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1787 * int offs, cardbusreg_t val) 1788 * This is the function to write the config space of a CardBus Card. 1789 * It works same as pci_conf_write. 1790 */ 1791 static void 1792 pccbb_conf_write(cc, tag, reg, val) 1793 cardbus_chipset_tag_t cc; 1794 cardbustag_t tag; 1795 int reg; /* register offset */ 1796 cardbusreg_t val; 1797 { 1798 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1799 1800 pci_conf_write(sc->sc_pc, tag, reg, val); 1801 } 1802 1803 #if 0 1804 STATIC int 1805 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1806 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1807 int speed, int flags, 1808 bus_space_handle_t * iohp) 1809 #endif 1810 /* 1811 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1812 * bus_addr_t start, bus_size_t size, 1813 * bus_size_t align, 1814 * struct pcmcia_io_handle *pcihp 1815 * 1816 * This function only allocates I/O region for pccard. This function 1817 * never maps the allocated region to pccard I/O area. 1818 * 1819 * XXX: The interface of this function is not very good, I believe. 1820 */ 1821 STATIC int 1822 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1823 pcmcia_chipset_handle_t pch; 1824 bus_addr_t start; /* start address */ 1825 bus_size_t size; 1826 bus_size_t align; 1827 struct pcmcia_io_handle *pcihp; 1828 { 1829 struct pcic_handle *ph = (struct pcic_handle *)pch; 1830 bus_addr_t ioaddr; 1831 int flags = 0; 1832 bus_space_tag_t iot; 1833 bus_space_handle_t ioh; 1834 #if rbus 1835 rbus_tag_t rb; 1836 #endif 1837 if (align == 0) { 1838 align = size; /* XXX: funny??? */ 1839 } 1840 1841 /* 1842 * Allocate some arbitrary I/O space. 1843 */ 1844 1845 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1846 1847 #if rbus 1848 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1849 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1850 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1851 return 1; 1852 } 1853 #else 1854 if (start) { 1855 ioaddr = start; 1856 if (bus_space_map(iot, start, size, 0, &ioh)) { 1857 return 1; 1858 } 1859 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1860 (u_long) ioaddr, (u_long) size)); 1861 } else { 1862 flags |= PCMCIA_IO_ALLOCATED; 1863 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1864 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1865 size, align, 0, 0, &ioaddr, &ioh)) { 1866 /* No room be able to be get. */ 1867 return 1; 1868 } 1869 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1870 (u_long) ioaddr, (u_long) size)); 1871 } 1872 #endif 1873 1874 pcihp->iot = iot; 1875 pcihp->ioh = ioh; 1876 pcihp->addr = ioaddr; 1877 pcihp->size = size; 1878 pcihp->flags = flags; 1879 1880 return 0; 1881 } 1882 1883 /* 1884 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1885 * struct pcmcia_io_handle *pcihp) 1886 * 1887 * This function only frees I/O region for pccard. 1888 * 1889 * XXX: The interface of this function is not very good, I believe. 1890 */ 1891 void 1892 pccbb_pcmcia_io_free(pch, pcihp) 1893 pcmcia_chipset_handle_t pch; 1894 struct pcmcia_io_handle *pcihp; 1895 { 1896 #if !rbus 1897 bus_space_tag_t iot = pcihp->iot; 1898 #endif 1899 bus_space_handle_t ioh = pcihp->ioh; 1900 bus_size_t size = pcihp->size; 1901 1902 #if rbus 1903 struct pccbb_softc *sc = 1904 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1905 rbus_tag_t rb = sc->sc_rbus_iot; 1906 1907 rbus_space_free(rb, ioh, size, NULL); 1908 #else 1909 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1910 bus_space_free(iot, ioh, size); 1911 else 1912 bus_space_unmap(iot, ioh, size); 1913 #endif 1914 } 1915 1916 /* 1917 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1918 * bus_addr_t offset, bus_size_t size, 1919 * struct pcmcia_io_handle *pcihp, 1920 * int *windowp) 1921 * 1922 * This function maps the allocated I/O region to pccard. This function 1923 * never allocates any I/O region for pccard I/O area. I don't 1924 * understand why the original authors of pcmciabus separated alloc and 1925 * map. I believe the two must be unite. 1926 * 1927 * XXX: no wait timing control? 1928 */ 1929 int 1930 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1931 pcmcia_chipset_handle_t pch; 1932 int width; 1933 bus_addr_t offset; 1934 bus_size_t size; 1935 struct pcmcia_io_handle *pcihp; 1936 int *windowp; 1937 { 1938 struct pcic_handle *ph = (struct pcic_handle *)pch; 1939 bus_addr_t ioaddr = pcihp->addr + offset; 1940 int i, win; 1941 #if defined CBB_DEBUG 1942 static char *width_names[] = { "dynamic", "io8", "io16" }; 1943 #endif 1944 1945 /* Sanity check I/O handle. */ 1946 1947 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1948 panic("pccbb_pcmcia_io_map iot is bogus"); 1949 } 1950 1951 /* XXX Sanity check offset/size. */ 1952 1953 win = -1; 1954 for (i = 0; i < PCIC_IO_WINS; i++) { 1955 if ((ph->ioalloc & (1 << i)) == 0) { 1956 win = i; 1957 ph->ioalloc |= (1 << i); 1958 break; 1959 } 1960 } 1961 1962 if (win == -1) { 1963 return 1; 1964 } 1965 1966 *windowp = win; 1967 1968 /* XXX this is pretty gross */ 1969 1970 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1971 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1972 1973 /* XXX wtf is this doing here? */ 1974 1975 #if 0 1976 printf(" port 0x%lx", (u_long) ioaddr); 1977 if (size > 1) { 1978 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1979 } 1980 #endif 1981 1982 ph->io[win].addr = ioaddr; 1983 ph->io[win].size = size; 1984 ph->io[win].width = width; 1985 1986 /* actual dirty register-value changing in the function below. */ 1987 pccbb_pcmcia_do_io_map(ph, win); 1988 1989 return 0; 1990 } 1991 1992 /* 1993 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1994 * 1995 * This function changes register-value to map I/O region for pccard. 1996 */ 1997 static void 1998 pccbb_pcmcia_do_io_map(ph, win) 1999 struct pcic_handle *ph; 2000 int win; 2001 { 2002 static u_int8_t pcic_iowidth[3] = { 2003 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2004 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2005 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2006 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2007 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2008 }; 2009 2010 #define PCIC_SIA_START_LOW 0 2011 #define PCIC_SIA_START_HIGH 1 2012 #define PCIC_SIA_STOP_LOW 2 2013 #define PCIC_SIA_STOP_HIGH 3 2014 2015 int regbase_win = 0x8 + win * 0x04; 2016 u_int8_t ioctl, enable; 2017 2018 DPRINTF( 2019 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2020 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2021 ph->io[win].width * 8)); 2022 2023 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2024 ph->io[win].addr & 0xff); 2025 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2026 (ph->io[win].addr >> 8) & 0xff); 2027 2028 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2029 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2030 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2031 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2032 2033 ioctl = Pcic_read(ph, PCIC_IOCTL); 2034 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2035 switch (win) { 2036 case 0: 2037 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2038 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2039 PCIC_IOCTL_IO0_DATASIZE_MASK); 2040 ioctl |= pcic_iowidth[ph->io[win].width]; 2041 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2042 break; 2043 case 1: 2044 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2045 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2046 PCIC_IOCTL_IO1_DATASIZE_MASK); 2047 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2048 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2049 break; 2050 } 2051 Pcic_write(ph, PCIC_IOCTL, ioctl); 2052 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2053 #if defined CBB_DEBUG 2054 { 2055 u_int8_t start_low = 2056 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2057 u_int8_t start_high = 2058 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2059 u_int8_t stop_low = 2060 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2061 u_int8_t stop_high = 2062 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2063 printf 2064 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2065 start_low, start_high, stop_low, stop_high, ioctl, enable); 2066 } 2067 #endif 2068 } 2069 2070 /* 2071 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2072 * 2073 * This function unmaps I/O region. No return value. 2074 */ 2075 STATIC void 2076 pccbb_pcmcia_io_unmap(pch, win) 2077 pcmcia_chipset_handle_t pch; 2078 int win; 2079 { 2080 struct pcic_handle *ph = (struct pcic_handle *)pch; 2081 int reg; 2082 2083 if (win >= PCIC_IO_WINS || win < 0) { 2084 panic("pccbb_pcmcia_io_unmap: window out of range"); 2085 } 2086 2087 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2088 switch (win) { 2089 case 0: 2090 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2091 break; 2092 case 1: 2093 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2094 break; 2095 } 2096 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2097 2098 ph->ioalloc &= ~(1 << win); 2099 } 2100 2101 /* 2102 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2103 * 2104 * This function enables the card. All information is stored in 2105 * the first argument, pcmcia_chipset_handle_t. 2106 */ 2107 static void 2108 pccbb_pcmcia_wait_ready(ph) 2109 struct pcic_handle *ph; 2110 { 2111 int i; 2112 2113 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2114 Pcic_read(ph, PCIC_IF_STATUS))); 2115 2116 for (i = 0; i < 10000; i++) { 2117 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2118 return; 2119 } 2120 delay(500); 2121 #ifdef CBB_DEBUG 2122 if ((i > 5000) && (i % 100 == 99)) 2123 printf("."); 2124 #endif 2125 } 2126 2127 #ifdef DIAGNOSTIC 2128 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2129 Pcic_read(ph, PCIC_IF_STATUS)); 2130 #endif 2131 } 2132 2133 /* 2134 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2135 * 2136 * This function enables the card. All information is stored in 2137 * the first argument, pcmcia_chipset_handle_t. 2138 */ 2139 STATIC void 2140 pccbb_pcmcia_socket_enable(pch) 2141 pcmcia_chipset_handle_t pch; 2142 { 2143 struct pcic_handle *ph = (struct pcic_handle *)pch; 2144 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2145 int cardtype, win; 2146 u_int8_t power, intr; 2147 pcireg_t spsr; 2148 int voltage; 2149 2150 /* this bit is mostly stolen from pcic_attach_card */ 2151 2152 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2153 2154 /* get card Vcc info */ 2155 2156 spsr = 2157 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2158 CB_SOCKET_STAT); 2159 if (spsr & CB_SOCKET_STAT_5VCARD) { 2160 DPRINTF(("5V card\n")); 2161 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2162 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2163 DPRINTF(("3V card\n")); 2164 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2165 } else { 2166 printf("?V card, 0x%x\n", spsr); /* XXX */ 2167 return; 2168 } 2169 2170 /* assert reset bit */ 2171 intr = Pcic_read(ph, PCIC_INTR); 2172 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2173 Pcic_write(ph, PCIC_INTR, intr); 2174 2175 /* disable socket i/o: negate output enable bit */ 2176 2177 power = Pcic_read(ph, PCIC_PWRCTL); 2178 power &= ~PCIC_PWRCTL_OE; 2179 Pcic_write(ph, PCIC_PWRCTL, power); 2180 2181 /* power down the socket to reset it, clear the card reset pin */ 2182 2183 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2184 2185 /* 2186 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2187 * we are changing Vcc (Toff). 2188 */ 2189 /* delay(300*1000); too much */ 2190 2191 /* power up the socket */ 2192 pccbb_power(sc, voltage); 2193 2194 /* 2195 * wait 100ms until power raise (Tpr) and 20ms to become 2196 * stable (Tsu(Vcc)). 2197 * 2198 * some machines require some more time to be settled 2199 * (another 200ms is added here). 2200 */ 2201 /* delay((100 + 20 + 200)*1000); too much */ 2202 2203 power = Pcic_read(ph, PCIC_PWRCTL); 2204 power |= PCIC_PWRCTL_OE; 2205 Pcic_write(ph, PCIC_PWRCTL, power); 2206 2207 /* 2208 * hold RESET at least 10us. 2209 */ 2210 delay(10); 2211 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2212 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2213 2214 /* clear the reset flag */ 2215 2216 intr |= PCIC_INTR_RESET; 2217 Pcic_write(ph, PCIC_INTR, intr); 2218 2219 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2220 2221 delay(20000); 2222 2223 /* wait for the chip to finish initializing */ 2224 2225 pccbb_pcmcia_wait_ready(ph); 2226 2227 /* zero out the address windows */ 2228 2229 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2230 2231 /* set the card type */ 2232 2233 cardtype = pcmcia_card_gettype(ph->pcmcia); 2234 2235 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2236 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2237 Pcic_write(ph, PCIC_INTR, intr); 2238 2239 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2240 ph->ph_parent->dv_xname, ph->sock, 2241 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2242 2243 /* reinstall all the memory and io mappings */ 2244 2245 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2246 if (ph->memalloc & (1 << win)) { 2247 pccbb_pcmcia_do_mem_map(ph, win); 2248 } 2249 } 2250 2251 for (win = 0; win < PCIC_IO_WINS; ++win) { 2252 if (ph->ioalloc & (1 << win)) { 2253 pccbb_pcmcia_do_io_map(ph, win); 2254 } 2255 } 2256 } 2257 2258 /* 2259 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2260 * 2261 * This function disables the card. All information is stored in 2262 * the first argument, pcmcia_chipset_handle_t. 2263 */ 2264 STATIC void 2265 pccbb_pcmcia_socket_disable(pch) 2266 pcmcia_chipset_handle_t pch; 2267 { 2268 struct pcic_handle *ph = (struct pcic_handle *)pch; 2269 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2270 u_int8_t power, intr; 2271 2272 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2273 2274 /* reset signal asserting... */ 2275 2276 intr = Pcic_read(ph, PCIC_INTR); 2277 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2278 Pcic_write(ph, PCIC_INTR, intr); 2279 delay(2 * 1000); 2280 2281 /* power down the socket */ 2282 power = Pcic_read(ph, PCIC_PWRCTL); 2283 power &= ~PCIC_PWRCTL_OE; 2284 Pcic_write(ph, PCIC_PWRCTL, power); 2285 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2286 /* 2287 * wait 300ms until power fails (Tpf). 2288 */ 2289 delay(300 * 1000); 2290 } 2291 2292 /* 2293 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2294 * 2295 * This function detects whether a card is in the slot or not. 2296 * If a card is inserted, return 1. Otherwise, return 0. 2297 */ 2298 STATIC int 2299 pccbb_pcmcia_card_detect(pch) 2300 pcmcia_chipset_handle_t pch; 2301 { 2302 struct pcic_handle *ph = (struct pcic_handle *)pch; 2303 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2304 2305 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2306 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2307 } 2308 2309 #if 0 2310 STATIC int 2311 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2312 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2313 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2314 #endif 2315 /* 2316 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2317 * bus_size_t size, 2318 * struct pcmcia_mem_handle *pcmhp) 2319 * 2320 * This function only allocates memory region for pccard. This 2321 * function never maps the allocated region to pccard memory area. 2322 * 2323 * XXX: Why the argument of start address is not in? 2324 */ 2325 STATIC int 2326 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2327 pcmcia_chipset_handle_t pch; 2328 bus_size_t size; 2329 struct pcmcia_mem_handle *pcmhp; 2330 { 2331 struct pcic_handle *ph = (struct pcic_handle *)pch; 2332 bus_space_handle_t memh; 2333 bus_addr_t addr; 2334 bus_size_t sizepg; 2335 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2336 #if rbus 2337 rbus_tag_t rb; 2338 #endif 2339 2340 /* out of sc->memh, allocate as many pages as necessary */ 2341 2342 /* convert size to PCIC pages */ 2343 /* 2344 * This is not enough; when the requested region is on the page 2345 * boundaries, this may calculate wrong result. 2346 */ 2347 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2348 #if 0 2349 if (sizepg > PCIC_MAX_MEM_PAGES) { 2350 return 1; 2351 } 2352 #endif 2353 2354 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2355 return 1; 2356 } 2357 2358 addr = 0; /* XXX gcc -Wuninitialized */ 2359 2360 #if rbus 2361 rb = sc->sc_rbus_memt; 2362 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2363 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2364 &addr, &memh)) { 2365 return 1; 2366 } 2367 #else 2368 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2369 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2370 0, /* boundary */ 2371 0, /* flags */ 2372 &addr, &memh)) { 2373 return 1; 2374 } 2375 #endif 2376 2377 DPRINTF( 2378 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2379 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2380 2381 pcmhp->memt = sc->sc_memt; 2382 pcmhp->memh = memh; 2383 pcmhp->addr = addr; 2384 pcmhp->size = size; 2385 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2386 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2387 pcmhp->mhandle = 0; 2388 /* No offset??? Funny. */ 2389 2390 return 0; 2391 } 2392 2393 /* 2394 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2395 * struct pcmcia_mem_handle *pcmhp) 2396 * 2397 * This function release the memory space allocated by the function 2398 * pccbb_pcmcia_mem_alloc(). 2399 */ 2400 STATIC void 2401 pccbb_pcmcia_mem_free(pch, pcmhp) 2402 pcmcia_chipset_handle_t pch; 2403 struct pcmcia_mem_handle *pcmhp; 2404 { 2405 #if rbus 2406 struct pcic_handle *ph = (struct pcic_handle *)pch; 2407 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2408 2409 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2410 #else 2411 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2412 #endif 2413 } 2414 2415 /* 2416 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2417 * 2418 * This function release the memory space allocated by the function 2419 * pccbb_pcmcia_mem_alloc(). 2420 */ 2421 STATIC void 2422 pccbb_pcmcia_do_mem_map(ph, win) 2423 struct pcic_handle *ph; 2424 int win; 2425 { 2426 int regbase_win; 2427 bus_addr_t phys_addr; 2428 bus_addr_t phys_end; 2429 2430 #define PCIC_SMM_START_LOW 0 2431 #define PCIC_SMM_START_HIGH 1 2432 #define PCIC_SMM_STOP_LOW 2 2433 #define PCIC_SMM_STOP_HIGH 3 2434 #define PCIC_CMA_LOW 4 2435 #define PCIC_CMA_HIGH 5 2436 2437 u_int8_t start_low, start_high = 0; 2438 u_int8_t stop_low, stop_high; 2439 u_int8_t off_low, off_high; 2440 u_int8_t mem_window; 2441 int reg; 2442 2443 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2444 int mem8 = 2445 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2446 || (kind == PCMCIA_MEM_ATTR); 2447 2448 regbase_win = 0x10 + win * 0x08; 2449 2450 phys_addr = ph->mem[win].addr; 2451 phys_end = phys_addr + ph->mem[win].size; 2452 2453 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2454 phys_addr, phys_end, ph->mem[win].offset)); 2455 2456 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2457 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2458 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2459 2460 /* bit 19:12 */ 2461 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2462 /* bit 23:20 and bit 7 on */ 2463 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2464 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2465 /* bit 31:24, for 32-bit address */ 2466 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2467 2468 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2469 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2470 2471 if (((struct pccbb_softc *)ph-> 2472 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2473 Pcic_write(ph, 0x40 + win, mem_window); 2474 } 2475 2476 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2477 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2478 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2479 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2480 2481 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2482 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2483 2484 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2485 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2486 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2487 | ((kind == PCMCIA_MEM_ATTR) ? 2488 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2489 2490 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2491 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2492 2493 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2494 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2495 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2496 2497 #if defined CBB_DEBUG 2498 { 2499 int r1, r2, r3, r4, r5, r6, r7 = 0; 2500 2501 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2502 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2503 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2504 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2505 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2506 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2507 if (((struct pccbb_softc *)(ph-> 2508 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2509 r7 = Pcic_read(ph, 0x40 + win); 2510 } 2511 2512 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2513 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2514 if (((struct pccbb_softc *)(ph-> 2515 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2516 DPRINTF((" %02x", r7)); 2517 } 2518 DPRINTF(("\n")); 2519 } 2520 #endif 2521 } 2522 2523 /* 2524 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2525 * bus_addr_t card_addr, bus_size_t size, 2526 * struct pcmcia_mem_handle *pcmhp, 2527 * bus_addr_t *offsetp, int *windowp) 2528 * 2529 * This function maps memory space allocated by the function 2530 * pccbb_pcmcia_mem_alloc(). 2531 */ 2532 STATIC int 2533 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2534 pcmcia_chipset_handle_t pch; 2535 int kind; 2536 bus_addr_t card_addr; 2537 bus_size_t size; 2538 struct pcmcia_mem_handle *pcmhp; 2539 bus_addr_t *offsetp; 2540 int *windowp; 2541 { 2542 struct pcic_handle *ph = (struct pcic_handle *)pch; 2543 bus_addr_t busaddr; 2544 long card_offset; 2545 int win; 2546 2547 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2548 if ((ph->memalloc & (1 << win)) == 0) { 2549 ph->memalloc |= (1 << win); 2550 break; 2551 } 2552 } 2553 2554 if (win == PCIC_MEM_WINS) { 2555 return 1; 2556 } 2557 2558 *windowp = win; 2559 2560 /* XXX this is pretty gross */ 2561 2562 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2563 panic("pccbb_pcmcia_mem_map memt is bogus"); 2564 } 2565 2566 busaddr = pcmhp->addr; 2567 2568 /* 2569 * compute the address offset to the pcmcia address space for the 2570 * pcic. this is intentionally signed. The masks and shifts below 2571 * will cause TRT to happen in the pcic registers. Deal with making 2572 * sure the address is aligned, and return the alignment offset. 2573 */ 2574 2575 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2576 card_addr -= *offsetp; 2577 2578 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2579 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2580 (u_long) card_addr)); 2581 2582 /* 2583 * include the offset in the size, and decrement size by one, since 2584 * the hw wants start/stop 2585 */ 2586 size += *offsetp - 1; 2587 2588 card_offset = (((long)card_addr) - ((long)busaddr)); 2589 2590 ph->mem[win].addr = busaddr; 2591 ph->mem[win].size = size; 2592 ph->mem[win].offset = card_offset; 2593 ph->mem[win].kind = kind; 2594 2595 pccbb_pcmcia_do_mem_map(ph, win); 2596 2597 return 0; 2598 } 2599 2600 /* 2601 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2602 * int window) 2603 * 2604 * This function unmaps memory space which mapped by the function 2605 * pccbb_pcmcia_mem_map(). 2606 */ 2607 STATIC void 2608 pccbb_pcmcia_mem_unmap(pch, window) 2609 pcmcia_chipset_handle_t pch; 2610 int window; 2611 { 2612 struct pcic_handle *ph = (struct pcic_handle *)pch; 2613 int reg; 2614 2615 if (window >= PCIC_MEM_WINS) { 2616 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2617 } 2618 2619 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2620 reg &= ~(1 << window); 2621 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2622 2623 ph->memalloc &= ~(1 << window); 2624 } 2625 2626 #if defined PCCBB_PCMCIA_POLL 2627 struct pccbb_poll_str { 2628 void *arg; 2629 int (*func) __P((void *)); 2630 int level; 2631 struct pcic_handle *ph; 2632 int count; 2633 int num; 2634 struct callout poll_ch; 2635 }; 2636 2637 static struct pccbb_poll_str pccbb_poll[10]; 2638 static int pccbb_poll_n = 0; 2639 2640 static void pccbb_pcmcia_poll __P((void *arg)); 2641 2642 static void 2643 pccbb_pcmcia_poll(arg) 2644 void *arg; 2645 { 2646 struct pccbb_poll_str *poll = arg; 2647 struct pcic_handle *ph = poll->ph; 2648 struct pccbb_softc *sc = ph->sc; 2649 int s; 2650 u_int32_t spsr; /* socket present-state reg */ 2651 2652 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2653 switch (poll->level) { 2654 case IPL_NET: 2655 s = splnet(); 2656 break; 2657 case IPL_BIO: 2658 s = splbio(); 2659 break; 2660 case IPL_TTY: /* fallthrough */ 2661 default: 2662 s = spltty(); 2663 break; 2664 } 2665 2666 spsr = 2667 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2668 CB_SOCKET_STAT); 2669 2670 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2671 if (!(spsr & 0x40)) /* CINT low */ 2672 #else 2673 if (1) 2674 #endif 2675 { 2676 if ((*poll->func) (poll->arg) > 0) { 2677 ++poll->count; 2678 // printf("intr: reported from poller, 0x%x\n", spsr); 2679 #if defined LEVEL2 2680 } else { 2681 printf("intr: miss! 0x%x\n", spsr); 2682 #endif 2683 } 2684 } 2685 splx(s); 2686 } 2687 #endif /* defined CB_PCMCIA_POLL */ 2688 2689 /* 2690 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2691 * struct pcmcia_function *pf, 2692 * int ipl, 2693 * int (*func)(void *), 2694 * void *arg); 2695 * 2696 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2697 */ 2698 STATIC void * 2699 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2700 pcmcia_chipset_handle_t pch; 2701 struct pcmcia_function *pf; 2702 int ipl; 2703 int (*func) __P((void *)); 2704 void *arg; 2705 { 2706 struct pcic_handle *ph = (struct pcic_handle *)pch; 2707 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2708 2709 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2710 /* what should I do? */ 2711 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2712 DPRINTF( 2713 ("%s does not provide edge nor pulse interrupt\n", 2714 sc->sc_dev.dv_xname)); 2715 return NULL; 2716 } 2717 /* 2718 * XXX Noooooo! The interrupt flag must set properly!! 2719 * dumb pcmcia driver!! 2720 */ 2721 } 2722 2723 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2724 } 2725 2726 /* 2727 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2728 * void *ih) 2729 * 2730 * This function disables PC-Card interrupt. 2731 */ 2732 STATIC void 2733 pccbb_pcmcia_intr_disestablish(pch, ih) 2734 pcmcia_chipset_handle_t pch; 2735 void *ih; 2736 { 2737 struct pcic_handle *ph = (struct pcic_handle *)pch; 2738 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2739 2740 pccbb_intr_disestablish(sc, ih); 2741 } 2742 2743 #if rbus 2744 /* 2745 * static int 2746 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2747 * bus_addr_t addr, bus_size_t size, 2748 * bus_addr_t mask, bus_size_t align, 2749 * int flags, bus_addr_t *addrp; 2750 * bus_space_handle_t *bshp) 2751 * 2752 * This function allocates a portion of memory or io space for 2753 * clients. This function is called from CardBus card drivers. 2754 */ 2755 static int 2756 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2757 cardbus_chipset_tag_t ct; 2758 rbus_tag_t rb; 2759 bus_addr_t addr; 2760 bus_size_t size; 2761 bus_addr_t mask; 2762 bus_size_t align; 2763 int flags; 2764 bus_addr_t *addrp; 2765 bus_space_handle_t *bshp; 2766 { 2767 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2768 2769 DPRINTF( 2770 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2771 addr, size, mask, align)); 2772 2773 if (align == 0) { 2774 align = size; 2775 } 2776 2777 if (rb->rb_bt == sc->sc_memt) { 2778 if (align < 16) { 2779 return 1; 2780 } 2781 } else if (rb->rb_bt == sc->sc_iot) { 2782 if (align < 4) { 2783 return 1; 2784 } 2785 /* XXX: hack for avoiding ISA image */ 2786 if (mask < 0x0100) { 2787 mask = 0x3ff; 2788 addr = 0x300; 2789 } 2790 2791 } else { 2792 DPRINTF( 2793 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2794 rb->rb_bt)); 2795 return 1; 2796 /* XXX: panic here? */ 2797 } 2798 2799 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2800 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2801 return 1; 2802 } 2803 2804 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2805 2806 return 0; 2807 } 2808 2809 /* 2810 * static int 2811 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2812 * bus_space_handle_t *bshp, bus_size_t size); 2813 * 2814 * This function is called from CardBus card drivers. 2815 */ 2816 static int 2817 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2818 cardbus_chipset_tag_t ct; 2819 rbus_tag_t rb; 2820 bus_space_handle_t bsh; 2821 bus_size_t size; 2822 { 2823 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2824 bus_space_tag_t bt = rb->rb_bt; 2825 2826 pccbb_close_win(sc, bt, bsh, size); 2827 2828 if (bt == sc->sc_memt) { 2829 } else if (bt == sc->sc_iot) { 2830 } else { 2831 return 1; 2832 /* XXX: panic here? */ 2833 } 2834 2835 return rbus_space_free(rb, bsh, size, NULL); 2836 } 2837 #endif /* rbus */ 2838 2839 #if rbus 2840 2841 static int 2842 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2843 struct pccbb_softc *sc; 2844 bus_space_tag_t bst; 2845 bus_addr_t addr; 2846 bus_size_t size; 2847 bus_space_handle_t bsh; 2848 int flags; 2849 { 2850 struct pccbb_win_chain_head *head; 2851 bus_addr_t align; 2852 2853 head = &sc->sc_iowindow; 2854 align = 0x04; 2855 if (sc->sc_memt == bst) { 2856 head = &sc->sc_memwindow; 2857 align = 0x1000; 2858 DPRINTF(("using memory window, %x %x %x\n\n", 2859 sc->sc_iot, sc->sc_memt, bst)); 2860 } 2861 2862 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2863 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2864 sc->sc_dev.dv_xname, 2865 (head == &sc->sc_memwindow) ? "mem" : "io"); 2866 } 2867 pccbb_winset(align, sc, bst); 2868 2869 return 0; 2870 } 2871 2872 static int 2873 pccbb_close_win(sc, bst, bsh, size) 2874 struct pccbb_softc *sc; 2875 bus_space_tag_t bst; 2876 bus_space_handle_t bsh; 2877 bus_size_t size; 2878 { 2879 struct pccbb_win_chain_head *head; 2880 bus_addr_t align; 2881 2882 head = &sc->sc_iowindow; 2883 align = 0x04; 2884 if (sc->sc_memt == bst) { 2885 head = &sc->sc_memwindow; 2886 align = 0x1000; 2887 } 2888 2889 if (pccbb_winlist_delete(head, bsh, size)) { 2890 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2891 sc->sc_dev.dv_xname, 2892 (head == &sc->sc_memwindow) ? "mem" : "io"); 2893 } 2894 pccbb_winset(align, sc, bst); 2895 2896 return 0; 2897 } 2898 2899 static int 2900 pccbb_winlist_insert(head, start, size, bsh, flags) 2901 struct pccbb_win_chain_head *head; 2902 bus_addr_t start; 2903 bus_size_t size; 2904 bus_space_handle_t bsh; 2905 int flags; 2906 { 2907 struct pccbb_win_chain *chainp, *elem; 2908 2909 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2910 M_NOWAIT)) == NULL) 2911 return (1); /* fail */ 2912 2913 elem->wc_start = start; 2914 elem->wc_end = start + (size - 1); 2915 elem->wc_handle = bsh; 2916 elem->wc_flags = flags; 2917 2918 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2919 chainp = TAILQ_NEXT(chainp, wc_list)) { 2920 if (chainp->wc_end < start) 2921 continue; 2922 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2923 return (0); 2924 } 2925 2926 TAILQ_INSERT_TAIL(head, elem, wc_list); 2927 return (0); 2928 } 2929 2930 static int 2931 pccbb_winlist_delete(head, bsh, size) 2932 struct pccbb_win_chain_head *head; 2933 bus_space_handle_t bsh; 2934 bus_size_t size; 2935 { 2936 struct pccbb_win_chain *chainp; 2937 2938 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2939 chainp = TAILQ_NEXT(chainp, wc_list)) { 2940 if (chainp->wc_handle != bsh) 2941 continue; 2942 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2943 printf("pccbb_winlist_delete: window 0x%lx size " 2944 "inconsistent: 0x%lx, 0x%lx\n", 2945 chainp->wc_start, 2946 chainp->wc_end - chainp->wc_start, 2947 size - 1); 2948 return 1; 2949 } 2950 2951 TAILQ_REMOVE(head, chainp, wc_list); 2952 free(chainp, M_DEVBUF); 2953 2954 return 0; 2955 } 2956 2957 return 1; /* fail: no candidate to remove */ 2958 } 2959 2960 static void 2961 pccbb_winset(align, sc, bst) 2962 bus_addr_t align; 2963 struct pccbb_softc *sc; 2964 bus_space_tag_t bst; 2965 { 2966 pci_chipset_tag_t pc; 2967 pcitag_t tag; 2968 bus_addr_t mask = ~(align - 1); 2969 struct { 2970 cardbusreg_t win_start; 2971 cardbusreg_t win_limit; 2972 int win_flags; 2973 } win[2]; 2974 struct pccbb_win_chain *chainp; 2975 int offs; 2976 2977 win[0].win_start = 0xffffffff; 2978 win[0].win_limit = 0; 2979 win[1].win_start = 0xffffffff; 2980 win[1].win_limit = 0; 2981 2982 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2983 offs = 0x2c; 2984 if (sc->sc_memt == bst) { 2985 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2986 offs = 0x1c; 2987 } 2988 2989 if (chainp != NULL) { 2990 win[0].win_start = chainp->wc_start & mask; 2991 win[0].win_limit = chainp->wc_end & mask; 2992 win[0].win_flags = chainp->wc_flags; 2993 chainp = TAILQ_NEXT(chainp, wc_list); 2994 } 2995 2996 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2997 if (win[1].win_start == 0xffffffff) { 2998 /* window 1 is not used */ 2999 if ((win[0].win_flags == chainp->wc_flags) && 3000 (win[0].win_limit + align >= 3001 (chainp->wc_start & mask))) { 3002 /* concatenate */ 3003 win[0].win_limit = chainp->wc_end & mask; 3004 } else { 3005 /* make new window */ 3006 win[1].win_start = chainp->wc_start & mask; 3007 win[1].win_limit = chainp->wc_end & mask; 3008 win[1].win_flags = chainp->wc_flags; 3009 } 3010 continue; 3011 } 3012 3013 /* Both windows are engaged. */ 3014 if (win[0].win_flags == win[1].win_flags) { 3015 /* same flags */ 3016 if (win[0].win_flags == chainp->wc_flags) { 3017 if (win[1].win_start - (win[0].win_limit + 3018 align) < 3019 (chainp->wc_start & mask) - 3020 ((chainp->wc_end & mask) + align)) { 3021 /* 3022 * merge window 0 and 1, and set win1 3023 * to chainp 3024 */ 3025 win[0].win_limit = win[1].win_limit; 3026 win[1].win_start = 3027 chainp->wc_start & mask; 3028 win[1].win_limit = 3029 chainp->wc_end & mask; 3030 } else { 3031 win[1].win_limit = 3032 chainp->wc_end & mask; 3033 } 3034 } else { 3035 /* different flags */ 3036 3037 /* concatenate win0 and win1 */ 3038 win[0].win_limit = win[1].win_limit; 3039 /* allocate win[1] to new space */ 3040 win[1].win_start = chainp->wc_start & mask; 3041 win[1].win_limit = chainp->wc_end & mask; 3042 win[1].win_flags = chainp->wc_flags; 3043 } 3044 } else { 3045 /* the flags of win[0] and win[1] is different */ 3046 if (win[0].win_flags == chainp->wc_flags) { 3047 win[0].win_limit = chainp->wc_end & mask; 3048 /* 3049 * XXX this creates overlapping windows, so 3050 * what should the poor bridge do if one is 3051 * cachable, and the other is not? 3052 */ 3053 printf("%s: overlapping windows\n", 3054 sc->sc_dev.dv_xname); 3055 } else { 3056 win[1].win_limit = chainp->wc_end & mask; 3057 } 3058 } 3059 } 3060 3061 pc = sc->sc_pc; 3062 tag = sc->sc_tag; 3063 pci_conf_write(pc, tag, offs, win[0].win_start); 3064 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3065 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3066 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3067 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3068 pci_conf_read(pc, tag, offs), 3069 pci_conf_read(pc, tag, offs + 4) + align, 3070 pci_conf_read(pc, tag, offs + 8), 3071 pci_conf_read(pc, tag, offs + 12) + align)); 3072 3073 if (bst == sc->sc_memt) { 3074 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3075 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3076 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3077 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3078 } 3079 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3080 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3081 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3082 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3083 } 3084 } 3085 } 3086 3087 #endif /* rbus */ 3088 3089 static void 3090 pccbb_powerhook(why, arg) 3091 int why; 3092 void *arg; 3093 { 3094 struct pccbb_softc *sc = arg; 3095 u_int32_t reg; 3096 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3097 bus_space_handle_t base_memh = sc->sc_base_memh; 3098 3099 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3100 3101 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3102 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3103 if (sc->sc_pil_intr_enable) { 3104 (void)pccbbintr_function(sc); 3105 } 3106 sc->sc_pil_intr_enable = 0; 3107 3108 /* ToDo: deactivate or suspend child devices */ 3109 3110 } 3111 3112 if (why == PWR_RESUME) { 3113 /* CSC Interrupt: Card detect interrupt on */ 3114 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3115 /* Card detect intr is turned on. */ 3116 reg |= CB_SOCKET_MASK_CD; 3117 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3118 /* reset interrupt */ 3119 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3120 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3121 3122 /* 3123 * check for card insertion or removal during suspend period. 3124 * XXX: the code can't cope with card swap (remove then 3125 * insert). how can we detect such situation? 3126 */ 3127 (void)pccbbintr(sc); 3128 3129 sc->sc_pil_intr_enable = 1; 3130 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3131 3132 /* ToDo: activate or wakeup child devices */ 3133 } 3134 } 3135
Indexes created Fri Sep 26 20:09:58 GMT 2025