pccbb.c revision 1.4
1 /* $NetBSD: pccbb.c,v 1.4 1999/10/19 09:29:46 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998 and 1999 HAYAKAWA Koichi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by HAYAKAWA Koichi. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 #define CBB_DEBUG 34 #define SHOW_REGS 35 #define PCCBB_PCMCIA_POLL 36 */ 37 /* #define CBB_DEBUG */ 38 39 /* 40 #define CB_PCMCIA_POLL 41 #define CB_PCMCIA_POLL_ONLY 42 #define LEVEL2 43 */ 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/ioctl.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 55 #include <machine/intr.h> 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/pccbbreg.h> 63 64 #include <dev/cardbus/cardslotvar.h> 65 66 #include <dev/cardbus/cardbusvar.h> 67 68 #include <dev/pcmcia/pcmciareg.h> 69 #include <dev/pcmcia/pcmciavar.h> 70 71 #include <dev/ic/i82365reg.h> 72 #include <dev/ic/i82365var.h> 73 #include <dev/pci/pccbbvar.h> 74 75 #include "locators.h" 76 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 93 #ifdef __BROKEN_INDIRECT_CONFIG 94 int pcicbbmatch __P((struct device *, void *, void *)); 95 #else 96 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 97 #endif 98 void pccbbattach __P((struct device *, struct device *, void *)); 99 int pccbbintr __P((void *)); 100 static void pci113x_insert __P((void *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 110 STATIC int cb_reset __P((struct pccbb_softc *)); 111 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 112 STATIC int cbbprint __P((void *, const char *)); 113 114 static int cb_chipset __P((u_int32_t, char const **, int *)); 115 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc *sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 127 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 128 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 129 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 130 #endif /* !rbus */ 131 static void *pccbb_intr_establish __P((cardbus_chipset_tag_t, int irq, int level, int (* ih)(void *), void *sc)); 132 static void pccbb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 133 134 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 135 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 136 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, int)); 137 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, cardbusreg_t)); 138 static void pccbb_chipinit __P((struct pccbb_softc *)); 139 140 141 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 142 struct pcmcia_mem_handle *)); 143 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 144 struct pcmcia_mem_handle *)); 145 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 146 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 147 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 148 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 149 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 150 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 151 struct pcmcia_io_handle *)); 152 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_io_handle *, int *)); 154 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 155 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 156 struct pcmcia_function *, int, int (*) (void *), void *)); 157 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, void *)); 158 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 159 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 160 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 161 162 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 163 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 164 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 165 166 /* bus-space allocation and disallocation functions */ 167 #if rbus 168 169 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 170 bus_addr_t addr, bus_size_t size, 171 bus_addr_t mask, bus_size_t align, 172 int flags, bus_addr_t *addrp, 173 bus_space_handle_t *bshp)); 174 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 175 bus_space_handle_t, bus_size_t)); 176 177 #endif /* rbus */ 178 179 #if rbus 180 181 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 182 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, bus_space_handle_t, bus_size_t)); 183 static int pccbb_winlist_insert __P((struct pccbb_win_chain **, bus_addr_t, 184 bus_size_t, bus_space_handle_t, int)); 185 static int pccbb_winlist_delete __P((struct pccbb_win_chain **, 186 bus_space_handle_t, bus_size_t)); 187 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 188 bus_space_tag_t)); 189 void pccbb_winlist_show(struct pccbb_win_chain *); 190 191 #endif /* rbus */ 192 193 /* for config_defer */ 194 static void pccbb_pci_callback __P((struct device *)); 195 196 197 #if defined SHOW_REGS 198 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, bus_space_handle_t memh)); 199 #endif 200 201 202 203 struct cfattach cbb_pci_ca = { 204 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 205 }; 206 207 208 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 209 pccbb_pcmcia_mem_alloc, 210 pccbb_pcmcia_mem_free, 211 pccbb_pcmcia_mem_map, 212 pccbb_pcmcia_mem_unmap, 213 pccbb_pcmcia_io_alloc, 214 pccbb_pcmcia_io_free, 215 pccbb_pcmcia_io_map, 216 pccbb_pcmcia_io_unmap, 217 pccbb_pcmcia_intr_establish, 218 pccbb_pcmcia_intr_disestablish, 219 pccbb_pcmcia_socket_enable, 220 pccbb_pcmcia_socket_disable, 221 pccbb_pcmcia_card_detect 222 }; 223 224 #if rbus 225 static struct cardbus_functions pccbb_funcs = { 226 pccbb_rbus_cb_space_alloc, 227 pccbb_rbus_cb_space_free, 228 pccbb_intr_establish, 229 pccbb_intr_disestablish, 230 pccbb_ctrl, 231 pccbb_power, 232 pccbb_make_tag, 233 pccbb_free_tag, 234 pccbb_conf_read, 235 pccbb_conf_write, 236 }; 237 #else 238 static struct cardbus_functions pccbb_funcs = { 239 pccbb_ctrl, 240 pccbb_power, 241 pccbb_mem_open, 242 pccbb_mem_close, 243 pccbb_io_open, 244 pccbb_io_close, 245 pccbb_intr_establish, 246 pccbb_intr_disestablish, 247 pccbb_make_tag, 248 pccbb_conf_read, 249 pccbb_conf_write, 250 }; 251 #endif 252 253 254 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 #ifdef __BROKEN_INDIRECT_CONFIG 260 void *match; 261 #else 262 struct cfdata *match; 263 #endif 264 void *aux; 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if ((pa->pa_class & PCI_CLASS_INTERFACE_MASK) == PCI_CLASS_INTERFACE_YENTA) { 269 /* OK, It must be YENTA PCI-CardBus bridge */ 270 271 return 1; 272 } 273 274 return 0; 275 } 276 277 278 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 279 | ((prod) << PCI_PRODUCT_SHIFT)) 280 281 282 struct yenta_chipinfo { 283 pcireg_t yc_id; /* vendor tag | product tag */ 284 const char *yc_name; 285 int yc_chiptype; 286 int yc_flags; 287 } yc_chipsets[] = { 288 /* Texas Instruments chips */ 289 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), "TI1130", CB_TI113X, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), "TI1131", CB_TI113X, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 294 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), "TI1250", CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), "TI1220", CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), "TI1221", CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), "TI1225", CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), "TI1251", CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), "TI1251B", CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), "TI1211", CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), "TI1420", CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), "TI1450", CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI2030), "TI2030", CB_UNKNOWN, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), "RF5C475", 317 CB_RF5C47X, PCCBB_PCMCIA_MEM_32}, 318 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), "RF5C476", 319 CB_RF5C47X, PCCBB_PCMCIA_MEM_32}, 320 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), "RF5C477", 321 CB_RF5C47X, PCCBB_PCMCIA_MEM_32}, 322 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), "RF5C478", 323 CB_RF5C47X, PCCBB_PCMCIA_MEM_32}, 324 325 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), "RF5C465", 326 CB_RF5C46X, PCCBB_PCMCIA_MEM_32}, 327 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), "RF5C466", 328 CB_RF5C46X, PCCBB_PCMCIA_MEM_32}, 329 330 /* Toshiba products */ 331 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), "ToPIC95", 332 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 333 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), "ToPIC95B", 334 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 335 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), "ToPIC97", 336 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 337 338 /* Cirrus Logic products */ 339 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), "CL-PD683X", 340 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 341 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), "CL-PD683X", 342 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 343 344 /* sentinel, or Generic chip */ 345 {0 /* null id */, "unknown", CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 346 }; 347 348 349 350 static int 351 cb_chipset(pci_id, namep, flagp) 352 u_int32_t pci_id; 353 char const **namep; 354 int *flagp; 355 { 356 int loopend = sizeof(yc_chipsets)/sizeof(yc_chipsets[0]); 357 struct yenta_chipinfo *ycp, *ycend; 358 359 ycend = yc_chipsets + loopend; 360 361 for (ycp =yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 362 363 if (ycp == ycend) { 364 /* not found */ 365 ycp = yc_chipsets + loopend - 1; /* to point the sentinel */ 366 } 367 368 if (namep != NULL) { 369 *namep = ycp->yc_name; 370 } 371 372 if (flagp != NULL) { 373 *flagp = ycp->yc_flags; 374 } 375 376 return ycp->yc_chiptype; 377 } 378 379 380 381 382 383 void 384 pccbbattach(parent, self, aux) 385 struct device *parent; 386 struct device *self; 387 void *aux; 388 { 389 struct pccbb_softc *sc = (void *)self; 390 struct pci_attach_args *pa = aux; 391 pci_chipset_tag_t pc = pa->pa_pc; 392 pcireg_t sock_base, busreg; 393 bus_addr_t sockbase; 394 char const *name; 395 int flags; 396 397 sc->sc_chipset = cb_chipset(pa->pa_id, &name, &flags); 398 printf(" (%s), chipflags %d\n", name, flags); 399 400 #if rbus 401 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 402 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 403 #endif /* rbus */ 404 405 sc->sc_base_memh = 0; 406 407 /* 408 * MAP socket registers and ExCA registers on memory-space 409 * When no valid address is set on socket base registers (on pci 410 * config space), get it not polite way. 411 */ 412 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 413 414 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 415 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 416 /* The address must be valid. */ 417 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 418 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 419 NULL)) { 420 printf("%s: can't map socket base address 0x%x\n", sc->sc_dev.dv_xname, 421 sock_base); 422 /* I think it's funny: socket base registers must be mapped on 423 memory space, but ... */ 424 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 0, 425 &sc->sc_base_memt, &sc->sc_base_memh, 426 &sockbase, NULL)) { 427 printf("%s: can't map socket base address 0x%lx: io mode\n", 428 sc->sc_dev.dv_xname, sockbase); 429 return; 430 } 431 } else { 432 DPRINTF(("%s: socket base address 0x%lx",sc->sc_dev.dv_xname, sockbase)); 433 } 434 } 435 436 437 sc->sc_mem_start = 0; /* XXX */ 438 sc->sc_mem_end = 0xffffffff; /* XXX */ 439 440 /* 441 * When interrupt isn't routed correctly, give up probing cbb and do 442 * not kill pcic-compatible port. 443 */ 444 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 445 printf(" Do not use %s because of intr unconfig.\n", sc->sc_dev.dv_xname); 446 return; 447 } 448 449 /* 450 * When bus number isn't set correctly, give up using 32-bit CardBus 451 * mode. 452 */ 453 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 454 #if notyet 455 if (((busreg >> 8) & 0xff) == 0) { 456 printf(" CardBus on %s will not be configured, because of bus no unconfig.\n", sc->sc_dev.dv_xname); 457 flags |= PCCBB_PCMCIA_16BITONLY; 458 } 459 #endif 460 461 /* pccbb_machdep.c end */ 462 463 464 #if defined CBB_DEBUG 465 { 466 static char *intrname[5] = {"NON", "A", "B", "C", "D"}; 467 printf(" intrpin %s, intrtag %d\n", intrname[pa->pa_intrpin], 468 pa->pa_intrline); 469 } 470 #endif 471 472 473 /* setup softc */ 474 sc->sc_pc = pc; 475 sc->sc_iot = pa->pa_iot; 476 sc->sc_memt = pa->pa_memt; 477 sc->sc_dmat = pa->pa_dmat; 478 sc->sc_tag = pa->pa_tag; 479 sc->sc_function = pa->pa_function; 480 481 sc->sc_intrline = pa->pa_intrline; 482 sc->sc_intrtag = pa->pa_intrtag; 483 sc->sc_intrpin = pa->pa_intrpin; 484 485 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 486 487 /* bus bridge initialisation */ 488 pccbb_chipinit(sc); 489 490 #if __NetBSD_Version__ > 103060000 491 config_defer(self, pccbb_pci_callback); 492 #else 493 pccbb_pci_callback(self); 494 #endif 495 } 496 497 498 499 500 static void 501 pccbb_pci_callback(self) 502 struct device *self; 503 { 504 struct pccbb_softc *sc = (void *)self; 505 pci_chipset_tag_t pc = sc->sc_pc; 506 bus_space_tag_t base_memt; 507 bus_space_handle_t base_memh; 508 u_int32_t maskreg; 509 pci_intr_handle_t ih; 510 const char *intrstr = NULL; 511 bus_addr_t sockbase; 512 struct cbslot_attach_args cba; 513 struct pcmciabus_attach_args paa; 514 struct cardslot_attach_args caa; 515 struct cardslot_softc *csc; 516 517 if (0 == sc->sc_base_memh) { 518 /* The socket registers aren't mapped correctly. */ 519 #if rbus 520 if (rbus_space_alloc(sc->sc_rbus_memt, 521 0, /* address: I don't mind where it is mapped */ 522 0x1000, /* size */ 523 0x0fff, /* mask */ 524 0x1000, /* align */ 525 0, /* flags */ 526 &sockbase, &sc->sc_base_memh)) { 527 return; 528 } 529 sc->sc_base_memt = sc->sc_memt; 530 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 531 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 532 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 533 #else 534 sc->sc_base_memt = sc->sc_memt; 535 #if !defined CBB_PCI_BASE 536 #define CBB_PCI_BASE 0x20000000 537 #endif 538 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 539 0x1000, /* size */ 540 0x1000, /* alignment */ 541 0, /* boundary */ 542 0, /* flags */ 543 &sockbase, &sc->sc_base_memh)) { 544 /* cannot allocate memory space */ 545 return; 546 } 547 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 548 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n",sc->sc_dev.dv_xname, 549 sock_base, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 550 #endif 551 } 552 553 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 554 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 555 556 557 /* CSC Interrupt: Card detect interrupt on */ 558 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 559 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 560 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 561 /* reset interrupt */ 562 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 563 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 564 565 566 /* Map and establish the interrupt. */ 567 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 568 sc->sc_intrline, &ih)) { 569 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 570 return; 571 } 572 intrstr = pci_intr_string(pc, ih); 573 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 574 575 if (sc->sc_ih == NULL) { 576 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 577 if (intrstr != NULL) { 578 printf(" at %s", intrstr); 579 } 580 printf("\n"); 581 return; 582 } 583 584 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 585 586 { 587 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 588 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { /* card exist */ 589 sc->sc_flags |= CBB_CARDEXIST; 590 } 591 } 592 593 /* 594 * attach cardbus 595 */ 596 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 597 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 598 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 599 pcireg_t pci_lscp = pci_conf_read(pc, sc->sc_tag, PCI_CB_LSCP_REG); 600 601 /* initialise cbslot_attach */ 602 cba.cba_busname = "cardbus"; 603 cba.cba_iot = sc->sc_iot; 604 cba.cba_memt = sc->sc_memt; 605 cba.cba_dmat = sc->sc_dmat; 606 cba.cba_function = 0; 607 cba.cba_bus = (busreg >> 8) & 0x0ff; 608 cba.cba_cc = (void *)sc; 609 cba.cba_cf = &pccbb_funcs; 610 cba.cba_intrline = sc->sc_intrline; 611 612 #if rbus 613 cba.cba_rbus_iot = sc->sc_rbus_iot; 614 cba.cba_rbus_memt = sc->sc_rbus_memt; 615 #endif 616 617 cba.cba_cacheline = PCI_CACHELINE(bhlc); 618 cba.cba_lattimer = PCI_CB_LATENCY(pci_lscp); 619 620 printf("%s: cacheline 0x%x lattimer 0x%x\n", sc->sc_dev.dv_xname, 621 cba.cba_cacheline, cba.cba_lattimer); 622 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, 623 bhlc, pci_lscp); 624 #if defined SHOW_REGS 625 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 626 #endif 627 } 628 629 pccbb_pcmcia_attach_setup(sc, &paa); 630 caa.caa_cb_attach = NULL; 631 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 632 caa.caa_cb_attach = &cba; 633 } 634 caa.caa_16_attach = &paa; 635 caa.caa_ph = &sc->sc_pcmcia_h; 636 637 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 638 DPRINTF(("pccbbattach: found cardslot\n")); 639 sc->sc_csc = csc; 640 } 641 642 return; 643 } 644 645 646 647 static void 648 pccbb_chipinit(sc) 649 struct pccbb_softc *sc; 650 { 651 pci_chipset_tag_t pc = sc->sc_pc; 652 pcitag_t tag = sc->sc_tag; 653 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory tag */ 654 bus_space_handle_t base_memh = sc->sc_base_memh; /* socket regs memory handle */ 655 pcireg_t cbctrl; 656 657 /* 658 * Set PCI command reg. 659 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 660 */ 661 { 662 pcireg_t command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 663 664 /* I believe it is harmless. */ 665 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 666 PCI_COMMAND_MASTER_ENABLE); 667 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 668 } 669 670 /* 671 * Set CardBus latency timer 672 */ 673 { 674 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 675 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 676 pci_lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 677 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 678 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 679 } 680 DPRINTF(("CardBus latency timer 0x%x (%x)\n", PCI_CB_LATENCY(pci_lscp), 681 pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 682 } 683 684 /* 685 * Set PCI latency timer 686 */ 687 { 688 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 689 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 690 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 691 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 692 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 693 } 694 DPRINTF(("PCI latency timer 0x%x (%x)\n", PCI_LATTIMER(pci_bhlc), 695 pci_conf_read(pc, tag, PCI_BHLC_REG))); 696 } 697 698 /* disable Legacy IO */ 699 700 switch (sc->sc_chipset) { 701 case CB_RF5C46X: /* fallthrogh */ 702 case CB_RF5C47X: 703 /* 704 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 705 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 706 * CardBus bridges have special bits on Bridge control reg (addr 707 * 0x3e on PCI config space). 708 */ 709 { 710 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 711 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 712 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 713 } 714 break; 715 default: 716 /* XXX: I don't know proper way to kill Legacy IO properly. */ 717 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 718 break; 719 } 720 721 722 723 /* 724 * Interrupt routing: use PCI interrupt 725 */ 726 { 727 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 728 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 729 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 730 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 731 } 732 733 if (CB_TI113X == sc->sc_chipset) { 734 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 735 if (0 == sc->sc_function) { 736 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 737 } 738 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; /* XXX: bug in PCI113X */ 739 cbctrl |= PCI113X_CBCTRL_PCI_CSC; /* CSC intr enable */ 740 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr prohibit */ 741 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; /* prohibit ISA routing */ 742 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 743 744 /* set ExCA regs: PCI113X required to be set bit 4 at Interrupt 745 and General Register, which is IRQ Enable Register, and clear 746 bit 3:0 to zero in order to route CSC interrupt to PCI 747 interrupt pin. */ 748 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 749 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 750 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 751 #if 1 752 DPRINTF(("ExCA regs:")); 753 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 0x803))); 754 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 0x805))); 755 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt,base_memh,0x81e))); 756 #endif 757 } else if (sc->sc_chipset == CB_TI12XX) { 758 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 759 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 760 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 761 /* 762 * set ExCA regs: PCI12XX required to be set bit 4 at Interrupt 763 * and General Register, which is IRQ Enable Register, and clear 764 * bit 3:0 to zero in order to route CSC interrupt to PCI 765 * interrupt pin. 766 */ 767 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 768 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 769 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 770 } else if (sc->sc_chipset == CB_TOPIC95B) { 771 cardbusreg_t sock_ctrl, slot_ctrl; 772 773 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 774 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 775 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 776 777 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 778 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", sc->sc_dev.dv_xname, 779 slot_ctrl)); 780 slot_ctrl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 781 TOPIC_SLOT_CTRL_ID_LOCK); 782 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 783 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 784 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 785 DPRINTF(("0x%x\n", slot_ctrl)); 786 } 787 788 /* close all memory and io windows */ 789 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 790 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 791 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 792 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 793 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 794 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 795 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 796 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 797 798 return; 799 } 800 801 802 803 /* 804 * attach pccard bus 805 */ 806 STATIC void 807 pccbb_pcmcia_attach_setup(sc, paa) 808 struct pccbb_softc *sc; 809 struct pcmciabus_attach_args *paa; 810 { 811 struct pcic_handle *ph = &sc->sc_pcmcia_h; 812 813 /* initialise pcmcia part in pccbb_softc */ 814 ph->ph_parent = (struct device *)sc; 815 ph->sock = sc->sc_function; 816 ph->flags = 0; 817 ph->shutdown = 0; 818 ph->ih_irq = sc->sc_intrline; 819 ph->ph_bus_t = sc->sc_base_memt; 820 ph->ph_bus_h = sc->sc_base_memh; 821 ph->ph_read = pccbb_pcmcia_read; 822 ph->ph_write = pccbb_pcmcia_write; 823 sc->sc_pct = &pccbb_pcmcia_funcs; 824 825 Pcic_write(ph, PCIC_CSC_INTR, 0); 826 Pcic_read(ph, PCIC_CSC); 827 828 /* initialise pcmcia bus attachment */ 829 paa->paa_busname = "pcmcia"; 830 paa->pct = sc->sc_pct; 831 paa->pch = ph; 832 paa->iobase = 0; /* I don't use them */ 833 paa->iosize = 0; 834 835 return; 836 } 837 838 839 #if 0 840 STATIC void 841 pccbb_pcmcia_attach_card(ph) 842 struct pcic_handle *ph; 843 { 844 if (ph->flags & PCIC_FLAG_CARDP) { 845 panic("pccbb_pcmcia_attach_card: already attached"); 846 } 847 848 /* call the MI attach function */ 849 pcmcia_card_attach(ph->pcmcia); 850 851 ph->flags |= PCIC_FLAG_CARDP; 852 } 853 854 855 STATIC void 856 pccbb_pcmcia_detach_card(ph, flags) 857 struct pcic_handle *ph; 858 int flags; 859 { 860 if (!(ph->flags & PCIC_FLAG_CARDP)) { 861 panic("pccbb_pcmcia_detach_card: already detached"); 862 } 863 864 ph->flags &= ~PCIC_FLAG_CARDP; 865 866 /* call the MI detach function */ 867 pcmcia_card_detach(ph->pcmcia, flags); 868 } 869 #endif 870 871 872 873 874 /* 875 * int pccbbintr(arg) 876 * void *arg; 877 * This routine handles the interrupt from Yenta PCI-CardBus bridge 878 * itself. 879 */ 880 int 881 pccbbintr(arg) 882 void *arg; 883 { 884 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 885 u_int32_t sockevent; 886 bus_space_tag_t memt = sc->sc_base_memt; 887 bus_space_handle_t memh = sc->sc_base_memh; 888 u_int32_t sockstate; 889 890 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 891 if (0 == sockevent) { /* not for me */ 892 return 0; 893 } else { 894 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); /* reset bit */ 895 } 896 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 897 898 if (sockevent & CB_SOCKET_EVENT_CD) { 899 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 900 /* A card should be removed. */ 901 if (sc->sc_flags & CBB_CARDEXIST) { 902 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 903 DPRINTF((" card removed, 0x%08x\n", sockstate)); 904 sc->sc_flags &= ~CBB_CARDEXIST; 905 if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { 906 #if 0 907 struct pcic_handle *ph = &sc->sc_pcmcia_h; 908 909 pcmcia_card_deactivate(ph->pcmcia); 910 pccbb_pcmcia_socket_disable(ph); 911 pccbb_pcmcia_detach_card(ph, DETACH_FORCE); 912 #endif 913 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_16); 914 } else if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) { 915 /* Cardbus intr removed */ 916 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_CB); 917 } 918 } 919 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 920 if (sc->sc_flags & CBB_INSERTING) { 921 untimeout(pci113x_insert, sc); 922 } 923 timeout(pci113x_insert, sc, hz/10); 924 sc->sc_flags |= CBB_INSERTING; 925 } 926 } else { 927 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 928 if (sockevent & CB_SOCKET_EVENT_CSTS) { 929 DPRINTF((" cstsevent occures, 0x%08x\n", sockstate)); 930 } 931 if (sockevent & CB_SOCKET_EVENT_POWER) { 932 DPRINTF((" pwrevent occures, 0x%08x\n", sockstate)); 933 } 934 } 935 936 return 1; 937 } 938 939 940 941 static void 942 pci113x_insert(arg) 943 void *arg; 944 { 945 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 946 u_int32_t sockevent, sockstate; 947 948 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 949 CB_SOCKET_EVENT); 950 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 951 CB_SOCKET_STAT); 952 953 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 954 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 955 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 956 sc->sc_flags |= CBB_CARDEXIST; 957 /* call pccard intterupt handler here */ 958 if (sockstate & CB_SOCKET_STAT_16BIT) { 959 /* 16-bit card found */ 960 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 961 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_16); 962 } else if (sockstate & CB_SOCKET_STAT_CB) { 963 /* cardbus card fuond */ 964 /* cardbus_attach_card(sc->sc_csc); */ 965 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_CB); 966 } else { 967 /* who are you? */ 968 } 969 } else { 970 timeout(pci113x_insert, sc, hz/10); 971 } 972 } 973 974 975 976 977 #define PCCBB_PCMCIA_OFFSET 0x800 978 static u_int8_t 979 pccbb_pcmcia_read(ph, reg) 980 struct pcic_handle *ph; 981 int reg; 982 { 983 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg); 984 } 985 986 987 988 static void 989 pccbb_pcmcia_write(ph, reg, val) 990 struct pcic_handle *ph; 991 int reg; 992 u_int8_t val; 993 { 994 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, val); 995 996 return; 997 } 998 999 1000 1001 1002 /* 1003 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1004 */ 1005 STATIC int 1006 pccbb_ctrl(ct, command) 1007 cardbus_chipset_tag_t ct; 1008 int command; 1009 { 1010 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1011 1012 switch(command) { 1013 case CARDBUS_CD: 1014 if (2 == pccbb_detect_card(sc)) { 1015 int retval = 0; 1016 int status = cb_detect_voltage(sc); 1017 if (PCCARD_VCC_5V & status) { 1018 retval |= CARDBUS_5V_CARD; 1019 } 1020 if (PCCARD_VCC_3V & status) { 1021 retval |= CARDBUS_3V_CARD; 1022 } 1023 if (PCCARD_VCC_XV & status) { 1024 retval |= CARDBUS_XV_CARD; 1025 } 1026 if (PCCARD_VCC_YV & status) { 1027 retval |= CARDBUS_YV_CARD; 1028 } 1029 return retval; 1030 } else { 1031 return 0; 1032 } 1033 break; 1034 case CARDBUS_RESET: 1035 return cb_reset(sc); 1036 break; 1037 case CARDBUS_IO_ENABLE: /* fallthrough */ 1038 case CARDBUS_IO_DISABLE: /* fallthrough */ 1039 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1040 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1041 case CARDBUS_BM_ENABLE: /* fallthrough */ 1042 case CARDBUS_BM_DISABLE: /* fallthrough */ 1043 return pccbb_cardenable(sc, command); 1044 break; 1045 } 1046 1047 return 0; 1048 } 1049 1050 1051 1052 /* 1053 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1054 * This function returns true when it succeeds and returns false when 1055 * it fails. 1056 */ 1057 STATIC int 1058 pccbb_power(ct, command) 1059 cardbus_chipset_tag_t ct; 1060 int command; 1061 { 1062 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1063 1064 u_int32_t status, sock_ctrl; 1065 bus_space_tag_t memt = sc->sc_base_memt; 1066 bus_space_handle_t memh = sc->sc_base_memh; 1067 1068 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1069 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1070 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1071 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1072 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1073 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1074 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1075 "UNKNOWN", 1076 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1077 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1078 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1079 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1080 "UNKNOWN", 1081 command)); 1082 1083 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1084 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1085 1086 switch (command & CARDBUS_VCCMASK) { 1087 case CARDBUS_VCC_UC: 1088 break; 1089 case CARDBUS_VCC_5V: 1090 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1091 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1092 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1093 } else { 1094 printf("%s: BAD voltage request: no 5 V card\n", sc->sc_dev.dv_xname); 1095 } 1096 break; 1097 case CARDBUS_VCC_3V: 1098 if (CB_SOCKET_STAT_3VCARD & status) { 1099 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1100 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1101 } else { 1102 printf("%s: BAD voltage request: no 3.3 V card\n", sc->sc_dev.dv_xname); 1103 } 1104 break; 1105 case CARDBUS_VCC_0V: 1106 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1107 break; 1108 default: 1109 return 0; /* power NEVER changed */ 1110 break; 1111 } 1112 1113 switch (command & CARDBUS_VPPMASK) { 1114 case CARDBUS_VPP_UC: 1115 break; 1116 case CARDBUS_VPP_0V: 1117 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1118 break; 1119 case CARDBUS_VPP_VCC: 1120 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1121 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1122 break; 1123 case CARDBUS_VPP_12V: 1124 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1125 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1126 break; 1127 } 1128 1129 #if 0 1130 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1131 #endif 1132 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1133 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1134 1135 delay(20*1000); /* wait 20 ms: Vcc setup time */ 1136 /* XXX 1137 delay 200 ms: though the standard defines that the Vcc set-up time 1138 is 20 ms, some PC-Card bridge requires longer duration. 1139 */ 1140 delay(200*1000); 1141 1142 1143 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1144 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1145 sc->sc_dev.dv_xname, sock_ctrl ,status); 1146 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1147 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1148 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V": 1149 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V": 1150 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV": 1151 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV": 1152 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V": 1153 "UNKNOWN", 1154 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC": 1155 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ?"CARDBUS_VPP_12V": 1156 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ?"CARDBUS_VPP_VCC": 1157 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1158 "UNKNOWN", 1159 command)); 1160 #if 0 1161 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1162 u_int32_t force = bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1163 /* Reset Bad Vcc request */ 1164 force &= ~CB_SOCKET_FORCE_BADVCC; 1165 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1166 printf("new status 0x%x\n", bus_space_read_4(memt, memh,CB_SOCKET_STAT)); 1167 return 1; 1168 } 1169 #endif 1170 return 0; 1171 } 1172 return 1; /* power changed correctly */ 1173 } 1174 1175 1176 1177 1178 1179 1180 #if defined CB_PCMCIA_POLL 1181 struct cb_poll_str { 1182 void *arg; 1183 int (* func) __P((void *)); 1184 int level; 1185 pccard_chipset_tag_t ct; 1186 int count; 1187 }; 1188 1189 static struct cb_poll_str cb_poll[10]; 1190 static int cb_poll_n = 0; 1191 1192 static void cb_pcmcia_poll __P((void *arg)); 1193 1194 static void 1195 cb_pcmcia_poll(arg) 1196 void *arg; 1197 { 1198 struct cb_poll_str *poll = arg; 1199 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1200 struct pccbb_softc *sc = psc->cpc_parent; 1201 int s; 1202 u_int32_t spsr; /* socket present-state reg */ 1203 1204 timeout(cb_pcmcia_poll, arg, hz/10); 1205 switch (poll->level) { 1206 case IPL_NET: 1207 s = splnet(); 1208 break; 1209 case IPL_BIO: 1210 s = splbio(); 1211 break; 1212 case IPL_TTY: /* fallthrough */ 1213 default: 1214 s = spltty(); 1215 break; 1216 } 1217 1218 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 1219 1220 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1221 if (!(spsr & 0x40)) { /* CINT low */ 1222 #else 1223 if (1) { 1224 #endif 1225 if ((*poll->func)(poll->arg) == 1) { 1226 ++poll->count; 1227 printf("intr: reported from poller, 0x%x\n", spsr); 1228 #if defined LEVEL2 1229 } else { 1230 printf("intr: miss! 0x%x\n", spsr); 1231 #endif 1232 } 1233 } 1234 splx(s); 1235 } 1236 #endif /* defined CB_PCMCIA_POLL */ 1237 1238 1239 1240 1241 /* 1242 * static int pccbb_detect_card(struct pccbb_softc *sc) 1243 * return value: 0 if no card exists. 1244 * 1 if 16-bit card exists. 1245 * 2 if cardbus card exists. 1246 */ 1247 static int 1248 pccbb_detect_card(sc) 1249 struct pccbb_softc *sc; 1250 { 1251 bus_space_handle_t base_memh = sc->sc_base_memh; 1252 bus_space_tag_t base_memt = sc->sc_base_memt; 1253 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 1254 int retval = 0; 1255 1256 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { /* CD1 and CD2 asserted */ 1257 /* card must be present */ 1258 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { /* NOTACARD DEASSERTED */ 1259 if (CB_SOCKET_STAT_CB & sockstat) { /* CardBus mode */ 1260 retval = 2; 1261 } else if (CB_SOCKET_STAT_16BIT & sockstat) { /* 16-bit mode */ 1262 retval = 1; 1263 } 1264 } 1265 } 1266 return retval; 1267 } 1268 1269 1270 1271 1272 /* 1273 * STATIC int cb_reset(struct pccbb_softc *sc) 1274 * This function resets CardBus card. 1275 */ 1276 STATIC int 1277 cb_reset(sc) 1278 struct pccbb_softc *sc; 1279 { 1280 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1281 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1282 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1283 /* Reset Assert at least 20 ms */ 1284 delay(20*1000); 1285 1286 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1287 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1288 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1289 delay(20*1000); 1290 } 1291 /* No card found on the slot. Keep Reset. */ 1292 return 1; 1293 } 1294 1295 1296 1297 1298 /* 1299 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1300 * This function detect card Voltage. 1301 */ 1302 STATIC int 1303 cb_detect_voltage(sc) 1304 struct pccbb_softc *sc; 1305 { 1306 u_int32_t psr; /* socket present-state reg */ 1307 bus_space_tag_t iot = sc->sc_base_memt; 1308 bus_space_handle_t ioh = sc->sc_base_memh; 1309 int vol = PCCARD_VCC_UKN; /* set 0 */ 1310 1311 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1312 1313 if (0x400u & psr) { 1314 vol |= PCCARD_VCC_5V; 1315 } 1316 if (0x800u & psr) { 1317 vol |= PCCARD_VCC_3V; 1318 } 1319 1320 return vol; 1321 } 1322 1323 1324 1325 1326 1327 1328 STATIC int 1329 cbbprint(aux, pcic) 1330 void *aux; 1331 const char *pcic; 1332 { 1333 /* 1334 struct cbslot_attach_args *cba = aux; 1335 1336 if (cba->cba_slot >= 0) { 1337 printf(" slot %d", cba->cba_slot); 1338 } 1339 */ 1340 return UNCONF; 1341 } 1342 1343 1344 1345 1346 /* 1347 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1348 * This function enables and disables the card 1349 */ 1350 STATIC int 1351 pccbb_cardenable(sc, function) 1352 struct pccbb_softc *sc; 1353 int function; 1354 { 1355 u_int32_t command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1356 1357 DPRINTF(("pccbb_cardenable:")); 1358 switch (function) { 1359 case CARDBUS_IO_ENABLE: 1360 command |= PCI_COMMAND_IO_ENABLE; 1361 break; 1362 case CARDBUS_IO_DISABLE: 1363 command &= ~PCI_COMMAND_IO_ENABLE; 1364 break; 1365 case CARDBUS_MEM_ENABLE: 1366 command |= PCI_COMMAND_MEM_ENABLE; 1367 break; 1368 case CARDBUS_MEM_DISABLE: 1369 command &= ~PCI_COMMAND_MEM_ENABLE; 1370 break; 1371 case CARDBUS_BM_ENABLE: 1372 command |= PCI_COMMAND_MASTER_ENABLE; 1373 break; 1374 case CARDBUS_BM_DISABLE: 1375 command &= ~PCI_COMMAND_MASTER_ENABLE; 1376 break; 1377 default: 1378 return 0; 1379 } 1380 1381 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1382 DPRINTF((" command reg 0x%x\n", command)); 1383 return 1; 1384 } 1385 1386 1387 1388 1389 1390 1391 #if !rbus 1392 /* 1393 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1394 */ 1395 static int 1396 pccbb_io_open(ct, win, start, end) 1397 cardbus_chipset_tag_t ct; 1398 int win; 1399 u_int32_t start, end; 1400 { 1401 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1402 int basereg; 1403 int limitreg; 1404 1405 if ((win < 0) || (win > 2)) { 1406 #if defined DIAGNOSTIC 1407 printf("cardbus_io_open: window out of range %d\n", win); 1408 #endif 1409 return 0; 1410 } 1411 1412 basereg = win*8 + 0x2c; 1413 limitreg = win*8 + 0x30; 1414 1415 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1416 start, basereg, end, limitreg)); 1417 1418 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1419 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1420 return 1; 1421 } 1422 1423 /* 1424 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1425 */ 1426 static int 1427 pccbb_io_close(ct, win) 1428 cardbus_chipset_tag_t ct; 1429 int win; 1430 { 1431 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1432 int basereg; 1433 int limitreg; 1434 1435 if ((win < 0) || (win > 2)) { 1436 #if defined DIAGNOSTIC 1437 printf("cardbus_io_close: window out of range %d\n", win); 1438 #endif 1439 return 0; 1440 } 1441 1442 basereg = win*8 + 0x2c; 1443 limitreg = win*8 + 0x30; 1444 1445 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1446 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1447 return 1; 1448 } 1449 1450 /* 1451 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1452 */ 1453 static int 1454 pccbb_mem_open(ct, win, start, end) 1455 cardbus_chipset_tag_t ct; 1456 int win; 1457 u_int32_t start, end; 1458 { 1459 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1460 int basereg; 1461 int limitreg; 1462 1463 if ((win < 0) || (win > 2)) { 1464 #if defined DIAGNOSTIC 1465 printf("cardbus_mem_open: window out of range %d\n", win); 1466 #endif 1467 return 0; 1468 } 1469 1470 basereg = win*8 + 0x1c; 1471 limitreg = win*8 + 0x20; 1472 1473 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1474 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1475 return 1; 1476 } 1477 1478 1479 /* 1480 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1481 */ 1482 static int 1483 pccbb_mem_close(ct, win) 1484 cardbus_chipset_tag_t ct; 1485 int win; 1486 { 1487 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1488 int basereg; 1489 int limitreg; 1490 1491 if ((win < 0) || (win > 2)) { 1492 #if defined DIAGNOSTIC 1493 printf("cardbus_mem_close: window out of range %d\n", win); 1494 #endif 1495 return 0; 1496 } 1497 1498 basereg = win*8 + 0x1c; 1499 limitreg = win*8 + 0x20; 1500 1501 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1502 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1503 return 1; 1504 } 1505 #endif 1506 1507 1508 1509 static void * 1510 pccbb_intr_establish(ct, irq, level, func, arg) 1511 cardbus_chipset_tag_t ct; 1512 int irq, level; 1513 int (* func) __P((void *)); 1514 void *arg; 1515 { 1516 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1517 1518 switch (sc->sc_chipset) { 1519 case CB_TI113X: 1520 { 1521 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1522 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* functional intr enabled */ 1523 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1524 } 1525 break; 1526 default: 1527 break; 1528 } 1529 1530 return pci_intr_establish(sc->sc_pc, irq, level, func, arg); 1531 } 1532 1533 1534 1535 1536 static void 1537 pccbb_intr_disestablish(ct, ih) 1538 cardbus_chipset_tag_t ct; 1539 void *ih; 1540 { 1541 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1542 1543 switch (sc->sc_chipset) { 1544 case CB_TI113X: 1545 { 1546 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1547 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr disabled */ 1548 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1549 } 1550 break; 1551 default: 1552 break; 1553 } 1554 1555 pci_intr_disestablish(sc->sc_pc, ih); 1556 } 1557 1558 1559 1560 1561 1562 #if defined SHOW_REGS 1563 static void 1564 cb_show_regs(pc, tag, memt, memh) 1565 pci_chipset_tag_t pc; 1566 pcitag_t tag; 1567 bus_space_tag_t memt; 1568 bus_space_handle_t memh; 1569 { 1570 int i; 1571 printf("PCI config regs:"); 1572 for (i = 0; i < 0x50; i += 4) { 1573 if (i % 16 == 0) { 1574 printf("\n 0x%02x:", i); 1575 } 1576 printf(" %08x", pci_conf_read(pc, tag, i)); 1577 } 1578 for (i = 0x80; i < 0xb0; i += 4) { 1579 if (i % 16 == 0) { 1580 printf("\n 0x%02x:", i); 1581 } 1582 printf(" %08x", pci_conf_read(pc, tag, i)); 1583 } 1584 1585 if (memh == 0) { 1586 printf("\n"); 1587 return; 1588 } 1589 1590 printf("\nsocket regs:"); 1591 for (i = 0; i <= 0x10; i += 0x04) { 1592 printf(" %08x", bus_space_read_4(memt, memh, i)); 1593 } 1594 printf("\nExCA regs:"); 1595 for (i = 0; i < 0x08; ++i) { 1596 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1597 } 1598 printf("\n"); 1599 return; 1600 } 1601 #endif 1602 1603 1604 1605 /* 1606 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1607 * int busno, int devno, int function) 1608 * This is the function to make a tag to access config space of 1609 * a CardBus Card. It works same as pci_conf_read. 1610 */ 1611 static cardbustag_t 1612 pccbb_make_tag(cc, busno, devno, function) 1613 cardbus_chipset_tag_t cc; 1614 int busno, devno, function; 1615 { 1616 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1617 1618 return pci_make_tag(sc->sc_pc, busno, devno, function); 1619 } 1620 1621 1622 static void 1623 pccbb_free_tag(cc, tag) 1624 cardbus_chipset_tag_t cc; 1625 cardbustag_t tag; 1626 { 1627 } 1628 1629 1630 /* 1631 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1632 * cardbustag_t tag, int offset) 1633 * This is the function to read the config space of a CardBus Card. 1634 * It works same as pci_conf_read. 1635 */ 1636 static cardbusreg_t 1637 pccbb_conf_read(cc, tag, offset) 1638 cardbus_chipset_tag_t cc; 1639 cardbustag_t tag; 1640 int offset; /* register offset */ 1641 { 1642 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1643 1644 return pci_conf_read(sc->sc_pc, tag, offset); 1645 } 1646 1647 1648 1649 /* 1650 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1651 * int offs, cardbusreg_t val) 1652 * This is the function to write the config space of a CardBus Card. 1653 * It works same as pci_conf_write. 1654 */ 1655 static void 1656 pccbb_conf_write(cc, tag, reg, val) 1657 cardbus_chipset_tag_t cc; 1658 cardbustag_t tag; 1659 int reg; /* register offset */ 1660 cardbusreg_t val; 1661 { 1662 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1663 1664 pci_conf_write(sc->sc_pc, tag, reg, val); 1665 } 1666 1667 1668 1669 1670 1671 #if 0 1672 STATIC int 1673 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1674 bus_addr_t start, bus_size_t size, 1675 bus_size_t align, bus_addr_t mask, /* address line width */ 1676 int speed, int flags, /* bus width */ 1677 bus_space_handle_t *iohp) 1678 #endif 1679 1680 1681 /* 1682 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1683 * bus_addr_t start, bus_size_t size, 1684 * bus_size_t align, 1685 * struct pcmcia_io_handle *pcihp 1686 * 1687 * This function only allocates I/O region for pccard. This function 1688 * never maps the allcated region to pccard I/O area. 1689 * 1690 * XXX: The interface of this function is not very good, I believe. 1691 */ 1692 STATIC int 1693 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1694 pcmcia_chipset_handle_t pch; 1695 bus_addr_t start; /* start address */ 1696 bus_size_t size; 1697 bus_size_t align; 1698 struct pcmcia_io_handle *pcihp; 1699 { 1700 struct pcic_handle *ph = (struct pcic_handle *)pch; 1701 bus_addr_t ioaddr; 1702 int flags = 0; 1703 bus_space_tag_t iot; 1704 bus_space_handle_t ioh; 1705 #if rbus 1706 rbus_tag_t rb; 1707 #endif 1708 if (align == 0) { 1709 align = size; /* XXX: funny??? */ 1710 } 1711 1712 1713 /* 1714 * Allocate some arbitrary I/O space. 1715 */ 1716 1717 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1718 1719 #if rbus 1720 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1721 if (rbus_space_alloc(rb, start, size, 0x3ff /* XXX: I assume all card decode lower 10 bits by its hardware */, 1722 align, 0, &ioaddr, &ioh)) { 1723 return 1; 1724 } 1725 #else 1726 if (start) { 1727 ioaddr = start; 1728 if (bus_space_map(iot, start, size, 0, &ioh)) { 1729 return 1; 1730 } 1731 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1732 (u_long) ioaddr, (u_long) size)); 1733 } else { 1734 flags |= PCMCIA_IO_ALLOCATED; 1735 if (bus_space_alloc(iot, 0x700/* ph->sc->sc_iobase */, 1736 0x800/* ph->sc->sc_iobase + ph->sc->sc_iosize*/, 1737 size, align, 0, 0, &ioaddr, &ioh)) { 1738 /* No room be able to be get. */ 1739 return 1; 1740 } 1741 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1742 (u_long) ioaddr, (u_long) size)); 1743 } 1744 #endif 1745 1746 pcihp->iot = iot; 1747 pcihp->ioh = ioh; 1748 pcihp->addr = ioaddr; 1749 pcihp->size = size; 1750 pcihp->flags = flags; 1751 1752 return 0; 1753 } 1754 1755 1756 1757 1758 1759 /* 1760 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1761 * struct pcmcia_io_handle *pcihp) 1762 * 1763 * This function only frees I/O region for pccard. 1764 * 1765 * XXX: The interface of this function is not very good, I believe. 1766 */ 1767 void 1768 pccbb_pcmcia_io_free(pch, pcihp) 1769 pcmcia_chipset_handle_t pch; 1770 struct pcmcia_io_handle *pcihp; 1771 { 1772 #if !rbus 1773 bus_space_tag_t iot = pcihp->iot; 1774 #endif 1775 bus_space_handle_t ioh = pcihp->ioh; 1776 bus_size_t size = pcihp->size; 1777 1778 #if rbus 1779 struct pccbb_softc *sc = (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1780 rbus_tag_t rb = sc->sc_rbus_iot; 1781 1782 rbus_space_free(rb, ioh, size, NULL); 1783 #else 1784 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1785 bus_space_free(iot, ioh, size); 1786 else 1787 bus_space_unmap(iot, ioh, size); 1788 #endif 1789 } 1790 1791 1792 1793 /* 1794 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1795 * bus_addr_t offset, bus_size_t size, 1796 * struct pcmcia_io_handle *pcihp, 1797 * int *windowp) 1798 * 1799 * This function maps the allocated I/O region to pccard. This function 1800 * never allocates any I/O region for pccard I/O area. I don't 1801 * understand why the original authors of pcmciabus separated alloc and 1802 * map. I believe the two must be unite. 1803 * 1804 * XXX: no wait timing control? 1805 */ 1806 int 1807 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1808 pcmcia_chipset_handle_t pch; 1809 int width; 1810 bus_addr_t offset; 1811 bus_size_t size; 1812 struct pcmcia_io_handle *pcihp; 1813 int *windowp; 1814 { 1815 struct pcic_handle *ph = (struct pcic_handle *) pch; 1816 bus_addr_t ioaddr = pcihp->addr + offset; 1817 int i, win; 1818 #if defined CBB_DEBUG 1819 static char *width_names[] = { "dynamic", "io8", "io16" }; 1820 #endif 1821 1822 /* Sanity check I/O handle. */ 1823 1824 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1825 panic("pccbb_pcmcia_io_map iot is bogus"); 1826 } 1827 1828 /* XXX Sanity check offset/size. */ 1829 1830 win = -1; 1831 for (i = 0; i < PCIC_IO_WINS; i++) { 1832 if ((ph->ioalloc & (1 << i)) == 0) { 1833 win = i; 1834 ph->ioalloc |= (1 << i); 1835 break; 1836 } 1837 } 1838 1839 if (win == -1) { 1840 return 1; 1841 } 1842 1843 *windowp = win; 1844 1845 /* XXX this is pretty gross */ 1846 1847 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1848 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1849 1850 /* XXX wtf is this doing here? */ 1851 1852 #if 0 1853 printf(" port 0x%lx", (u_long) ioaddr); 1854 if (size > 1) { 1855 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1856 } 1857 #endif 1858 1859 ph->io[win].addr = ioaddr; 1860 ph->io[win].size = size; 1861 ph->io[win].width = width; 1862 1863 /* actual dirty register-value changing in the function below. */ 1864 pccbb_pcmcia_do_io_map(ph, win); 1865 1866 return 0; 1867 } 1868 1869 1870 1871 /* 1872 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1873 * 1874 * This function changes register-value to map I/O region for pccard. 1875 */ 1876 static void 1877 pccbb_pcmcia_do_io_map(ph, win) 1878 struct pcic_handle *ph; 1879 int win; 1880 { 1881 static u_int8_t pcic_iowidth[3] = { 1882 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1883 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_8BIT, 1884 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_16BIT, 1885 }; 1886 1887 #define PCIC_SIA_START_LOW 0 1888 #define PCIC_SIA_START_HIGH 1 1889 #define PCIC_SIA_STOP_LOW 2 1890 #define PCIC_SIA_STOP_HIGH 3 1891 1892 int regbase_win = 0x8 + win*0x04; 1893 u_int8_t ioctl, enable; 1894 1895 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1896 win, (long) ph->io[win].addr, (long) ph->io[win].size, 1897 ph->io[win].width * 8)); 1898 1899 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1900 ph->io[win].addr & 0xff); 1901 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1902 (ph->io[win].addr >> 8) & 0xff); 1903 1904 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1905 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1906 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1907 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1908 1909 ioctl = Pcic_read(ph, PCIC_IOCTL); 1910 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1911 switch (win) { 1912 case 0: 1913 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1914 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK); 1915 ioctl |= pcic_iowidth[ph->io[win].width]; 1916 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1917 break; 1918 case 1: 1919 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1920 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK); 1921 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1922 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1923 break; 1924 } 1925 Pcic_write(ph, PCIC_IOCTL, ioctl); 1926 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1927 #if defined CBB_DEBUG 1928 { 1929 u_int8_t start_low = Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1930 u_int8_t start_high = Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1931 u_int8_t stop_low = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1932 u_int8_t stop_high = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1933 printf(" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1934 start_low, start_high, stop_low, stop_high, ioctl, enable); 1935 } 1936 #endif 1937 } 1938 1939 1940 1941 /* 1942 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1943 * 1944 * This function unmapss I/O region. No return value. 1945 */ 1946 STATIC void 1947 pccbb_pcmcia_io_unmap(pch, win) 1948 pcmcia_chipset_handle_t pch; 1949 int win; 1950 { 1951 struct pcic_handle *ph = (struct pcic_handle *)pch; 1952 int reg; 1953 1954 if (win >= PCIC_IO_WINS || win < 0) { 1955 panic("pccbb_pcmcia_io_unmap: window out of range"); 1956 } 1957 1958 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1959 switch (win) { 1960 case 0: 1961 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1962 break; 1963 case 1: 1964 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1965 break; 1966 } 1967 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 1968 1969 ph->ioalloc &= ~(1 << win); 1970 } 1971 1972 1973 1974 1975 1976 /* 1977 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1978 * 1979 * This function enables the card. All information is stored in 1980 * the first argument, pcmcia_chipset_handle_t. 1981 */ 1982 static void 1983 pccbb_pcmcia_wait_ready(ph) 1984 struct pcic_handle *ph; 1985 { 1986 int i; 1987 1988 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 1989 Pcic_read(ph, PCIC_IF_STATUS))); 1990 1991 for (i = 0; i < 10000; i++) { 1992 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 1993 return; 1994 } 1995 delay(500); 1996 #ifdef CBB_DEBUG 1997 if ((i > 5000) && (i%100 == 99)) 1998 printf("."); 1999 #endif 2000 } 2001 2002 #ifdef DIAGNOSTIC 2003 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2004 Pcic_read(ph, PCIC_IF_STATUS)); 2005 #endif 2006 } 2007 2008 2009 2010 /* 2011 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2012 * 2013 * This function enables the card. All information is stored in 2014 * the first argument, pcmcia_chipset_handle_t. 2015 */ 2016 STATIC void 2017 pccbb_pcmcia_socket_enable(pch) 2018 pcmcia_chipset_handle_t pch; 2019 { 2020 struct pcic_handle *ph = (struct pcic_handle *)pch; 2021 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2022 int cardtype, win; 2023 u_int8_t power, intr; 2024 pcireg_t spsr; 2025 int voltage; 2026 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2027 2028 /* this bit is mostly stolen from pcic_attach_card */ 2029 2030 DPRINTF(("pccbb_pcmcia_socket_enable:\n")); 2031 2032 /* get card Vcc info */ 2033 2034 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2035 if (spsr & CB_SOCKET_STAT_5VCARD) { 2036 DPRINTF(("5V card\n")); 2037 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2038 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2039 DPRINTF(("3V card\n")); 2040 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2041 } else { 2042 printf("?V card, 0x%x\n", spsr); /* XXX */ 2043 return; 2044 } 2045 2046 /* assert reset bit */ 2047 2048 intr = Pcic_read(ph, PCIC_INTR); 2049 intr &= ~PCIC_INTR_RESET; 2050 intr |= PCIC_INTR_PCI; /* XXX */ 2051 Pcic_write(ph, PCIC_INTR, intr); 2052 2053 /* disable socket i/o: negate output enable bit */ 2054 2055 power = Pcic_read(ph, PCIC_PWRCTL); 2056 power &= ~PCIC_PWRCTL_OE; 2057 Pcic_write(ph, PCIC_PWRCTL, power); 2058 2059 /* power down the socket to reset it, clear the card reset pin */ 2060 2061 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2062 2063 /* 2064 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2065 * we are changing Vcc (Toff). 2066 */ 2067 /* delay(300*1000); too much */ 2068 2069 /* power up the socket */ 2070 pccbb_power(sc, voltage); 2071 2072 /* 2073 * wait 100ms until power raise (Tpr) and 20ms to become 2074 * stable (Tsu(Vcc)). 2075 * 2076 * some machines require some more time to be settled 2077 * (another 200ms is added here). 2078 */ 2079 /* delay((100 + 20 + 200)*1000); too much */ 2080 2081 power = Pcic_read(ph, PCIC_PWRCTL); 2082 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2083 2084 /* 2085 * hold RESET at least 10us. 2086 */ 2087 delay(10); 2088 delay(2*1000); /* XXX: TI1130 requires it. */ 2089 delay(20*1000); /* XXX: TI1130 requires it. */ 2090 2091 /* clear the reset flag */ 2092 2093 intr = Pcic_read(ph, PCIC_INTR); 2094 Pcic_write(ph, PCIC_INTR, intr | PCIC_INTR_RESET); 2095 2096 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2097 2098 delay(20000); 2099 2100 /* wait for the chip to finish initializing */ 2101 2102 pccbb_pcmcia_wait_ready(ph); 2103 2104 /* zero out the address windows */ 2105 2106 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2107 2108 /* set the card type */ 2109 2110 cardtype = pcmcia_card_gettype(ph->pcmcia); 2111 2112 intr = Pcic_read(ph, PCIC_INTR); 2113 intr &= ~PCIC_INTR_CARDTYPE_MASK; 2114 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2115 PCIC_INTR_CARDTYPE_IO : 2116 PCIC_INTR_CARDTYPE_MEM); 2117 Pcic_write(ph, PCIC_INTR, intr); 2118 2119 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2120 ph->ph_parent->dv_xname, ph->sock, 2121 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2122 2123 /* reinstall all the memory and io mappings */ 2124 2125 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2126 if (ph->memalloc & (1 << win)) { 2127 pccbb_pcmcia_do_mem_map(ph, win); 2128 } 2129 } 2130 2131 for (win = 0; win < PCIC_IO_WINS; ++win) { 2132 if (ph->ioalloc & (1 << win)) { 2133 pccbb_pcmcia_do_io_map(ph, win); 2134 } 2135 } 2136 } 2137 2138 2139 2140 /* 2141 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2142 * 2143 * This function disables the card. All information is stored in 2144 * the first argument, pcmcia_chipset_handle_t. 2145 */ 2146 STATIC void 2147 pccbb_pcmcia_socket_disable(pch) 2148 pcmcia_chipset_handle_t pch; 2149 { 2150 struct pcic_handle *ph = (struct pcic_handle *)pch; 2151 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2152 u_int8_t power, intr; 2153 2154 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2155 2156 /* reset signal asserting... */ 2157 2158 intr = Pcic_read(ph, PCIC_INTR); 2159 intr &= ~PCIC_INTR_RESET; 2160 Pcic_write(ph, PCIC_INTR, intr); 2161 delay(2*1000); 2162 2163 /* power down the socket */ 2164 power = Pcic_read(ph, PCIC_PWRCTL); 2165 power &= ~PCIC_PWRCTL_OE; 2166 Pcic_write(ph, PCIC_PWRCTL, power); 2167 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2168 2169 /* 2170 * wait 300ms until power fails (Tpf). 2171 */ 2172 delay(300 * 1000); 2173 } 2174 2175 2176 2177 /* 2178 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2179 * 2180 * This function detects whether a card is in the slot or not. 2181 * If a card is inserted, return 1. Otherwise, return 0. 2182 */ 2183 STATIC int 2184 pccbb_pcmcia_card_detect(pch) 2185 pcmcia_chipset_handle_t pch; 2186 { 2187 struct pcic_handle *ph = (struct pcic_handle *)pch; 2188 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2189 2190 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2191 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2192 } 2193 2194 2195 2196 #if 0 2197 STATIC int 2198 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2199 bus_addr_t start, bus_size_t size, 2200 bus_size_t align, 2201 int speed, int flags, /* bus width */ 2202 bus_space_tag_t *memtp 2203 bus_space_handle_t *memhp) 2204 #endif 2205 2206 2207 /* 2208 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2209 * bus_size_t size, 2210 * struct pcmcia_mem_handle *pcmhp) 2211 * 2212 * This function only allocates memory region for pccard. This 2213 * function never maps the allcated region to pccard memory area. 2214 * 2215 * XXX: Why the argument of start address is not in? 2216 */ 2217 STATIC int 2218 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2219 pcmcia_chipset_handle_t pch; 2220 bus_size_t size; 2221 struct pcmcia_mem_handle *pcmhp; 2222 { 2223 struct pcic_handle *ph = (struct pcic_handle *)pch; 2224 bus_space_handle_t memh; 2225 bus_addr_t addr; 2226 bus_size_t sizepg; 2227 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2228 #if rbus 2229 rbus_tag_t rb; 2230 #endif 2231 2232 /* out of sc->memh, allocate as many pages as necessary */ 2233 2234 /* convert size to PCIC pages */ 2235 /* 2236 This is not enough; when the requested region is on the 2237 page boundaries, this may calculate wrong result. 2238 */ 2239 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2240 #if 0 2241 if (sizepg > PCIC_MAX_MEM_PAGES) { 2242 return 1; 2243 } 2244 #endif 2245 2246 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2247 return 1; 2248 } 2249 2250 addr = 0; /* XXX gcc -Wuninitialized */ 2251 2252 #if rbus 2253 rb = sc->sc_rbus_memt; 2254 if (rbus_space_alloc(rb, 0, sizepg*PCIC_MEM_PAGESIZE, 2255 sizepg*PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 2256 0, &addr, &memh)) { 2257 return 1; 2258 } 2259 2260 #else 2261 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2262 sizepg*PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2263 0 /* boundary */, 0 /* flags */, 2264 &addr, &memh)) { 2265 return 1; 2266 } 2267 #endif 2268 2269 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2270 addr, size, sizepg*PCIC_MEM_PAGESIZE)); 2271 2272 pcmhp->memt = sc->sc_memt; 2273 pcmhp->memh = memh; 2274 pcmhp->addr = addr; 2275 pcmhp->size = size; 2276 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2277 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2278 pcmhp->mhandle = 0; 2279 /* No offset??? Funny. */ 2280 2281 return 0; 2282 } 2283 2284 2285 2286 2287 /* 2288 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2289 * struct pcmcia_mem_handle *pcmhp) 2290 * 2291 * This function release the memory space allocated by the fuction 2292 * pccbb_pcmcia_mem_alloc(). 2293 */ 2294 STATIC void 2295 pccbb_pcmcia_mem_free(pch, pcmhp) 2296 pcmcia_chipset_handle_t pch; 2297 struct pcmcia_mem_handle *pcmhp; 2298 { 2299 #if rbus 2300 struct pcic_handle *ph = (struct pcic_handle *)pch; 2301 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2302 2303 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2304 #else 2305 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2306 #endif 2307 } 2308 2309 2310 2311 2312 /* 2313 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2314 * 2315 * This function release the memory space allocated by the fuction 2316 * pccbb_pcmcia_mem_alloc(). 2317 */ 2318 STATIC void 2319 pccbb_pcmcia_do_mem_map(ph, win) 2320 struct pcic_handle *ph; 2321 int win; 2322 { 2323 int regbase_win; 2324 bus_addr_t phys_addr; 2325 bus_addr_t phys_end; 2326 2327 #define PCIC_SMM_START_LOW 0 2328 #define PCIC_SMM_START_HIGH 1 2329 #define PCIC_SMM_STOP_LOW 2 2330 #define PCIC_SMM_STOP_HIGH 3 2331 #define PCIC_CMA_LOW 4 2332 #define PCIC_CMA_HIGH 5 2333 2334 u_int8_t start_low, start_high = 0; 2335 u_int8_t stop_low, stop_high; 2336 u_int8_t off_low, off_high; 2337 u_int8_t mem_window; 2338 int reg; 2339 2340 regbase_win = 0x10 + win*0x08; 2341 2342 phys_addr = ph->mem[win].addr; 2343 phys_end = phys_addr + ph->mem[win].size; 2344 2345 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2346 phys_addr, phys_end, ph->mem[win].offset)); 2347 2348 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2349 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2350 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2351 2352 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; /* bit 19:12 */ 2353 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) /* bit 23:20 */ 2354 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2355 /* bit 31:24, for 32-bit address */ 2356 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; /* bit 31:24 */ 2357 2358 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2359 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2360 2361 if (((struct pccbb_softc *)ph->ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2362 Pcic_write(ph, 0x40 + win, mem_window); 2363 } 2364 2365 2366 #if 0 2367 /* XXX do I want 16 bit all the time? */ 2368 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 2369 #endif 2370 2371 2372 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2373 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2374 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2375 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2376 2377 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2378 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2379 2380 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2381 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2382 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2383 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2384 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2385 2386 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2387 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2388 2389 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2390 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2391 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2392 2393 #if defined CBB_DEBUG 2394 { 2395 int r1, r2, r3, r4, r5, r6, r7 = 0; 2396 2397 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2398 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2399 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2400 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2401 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2402 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2403 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2404 r7 = Pcic_read(ph, 0x40 + win); 2405 } 2406 2407 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2408 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2409 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2410 DPRINTF((" %02x",r7)); 2411 } 2412 DPRINTF(("\n")); 2413 } 2414 #endif 2415 } 2416 2417 2418 2419 2420 /* 2421 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2422 * bus_addr_t card_addr, bus_size_t size, 2423 * struct pcmcia_mem_handle *pcmhp, 2424 * bus_addr_t *offsetp, int *windowp) 2425 * 2426 * This function maps memory space allocated by the fuction 2427 * pccbb_pcmcia_mem_alloc(). 2428 */ 2429 STATIC int 2430 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2431 pcmcia_chipset_handle_t pch; 2432 int kind; 2433 bus_addr_t card_addr; 2434 bus_size_t size; 2435 struct pcmcia_mem_handle *pcmhp; 2436 bus_addr_t *offsetp; 2437 int *windowp; 2438 { 2439 struct pcic_handle *ph = (struct pcic_handle *)pch; 2440 bus_addr_t busaddr; 2441 long card_offset; 2442 int win; 2443 2444 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2445 if ((ph->memalloc & (1 << win)) == 0) { 2446 ph->memalloc |= (1 << win); 2447 break; 2448 } 2449 } 2450 2451 if (win == PCIC_MEM_WINS) { 2452 return 1; 2453 } 2454 2455 *windowp = win; 2456 2457 /* XXX this is pretty gross */ 2458 2459 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2460 panic("pccbb_pcmcia_mem_map memt is bogus"); 2461 } 2462 2463 busaddr = pcmhp->addr; 2464 2465 /* 2466 * compute the address offset to the pcmcia address space for the 2467 * pcic. this is intentionally signed. The masks and shifts below 2468 * will cause TRT to happen in the pcic registers. Deal with making 2469 * sure the address is aligned, and return the alignment offset. 2470 */ 2471 2472 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2473 card_addr -= *offsetp; 2474 2475 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2476 "%lx\n", win, (u_long)busaddr, (u_long)*offsetp, (u_long)size, 2477 (u_long)card_addr)); 2478 2479 /* 2480 * include the offset in the size, and decrement size by one, since 2481 * the hw wants start/stop 2482 */ 2483 size += *offsetp - 1; 2484 2485 card_offset = (((long) card_addr) - ((long) busaddr)); 2486 2487 ph->mem[win].addr = busaddr; 2488 ph->mem[win].size = size; 2489 ph->mem[win].offset = card_offset; 2490 ph->mem[win].kind = kind; 2491 2492 pccbb_pcmcia_do_mem_map(ph, win); 2493 2494 return 0; 2495 } 2496 2497 2498 2499 /* 2500 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2501 * int window) 2502 * 2503 * This function unmaps memory space which mapped by the fuction 2504 * pccbb_pcmcia_mem_map(). 2505 */ 2506 STATIC void 2507 pccbb_pcmcia_mem_unmap(pch, window) 2508 pcmcia_chipset_handle_t pch; 2509 int window; 2510 { 2511 struct pcic_handle *ph = (struct pcic_handle *)pch; 2512 int reg; 2513 2514 if (window >= PCIC_MEM_WINS) { 2515 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2516 } 2517 2518 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2519 reg &= ~(1 << window); 2520 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2521 2522 ph->memalloc &= ~(1 << window); 2523 } 2524 2525 2526 2527 #if defined PCCBB_PCMCIA_POLL 2528 struct pccbb_poll_str { 2529 void *arg; 2530 int (* func) __P((void *)); 2531 int level; 2532 struct pcic_handle *ph; 2533 int count; 2534 int num; 2535 }; 2536 2537 static struct pccbb_poll_str pccbb_poll[10]; 2538 static int pccbb_poll_n = 0; 2539 2540 static void pccbb_pcmcia_poll __P((void *arg)); 2541 2542 static void 2543 pccbb_pcmcia_poll(arg) 2544 void *arg; 2545 { 2546 struct pccbb_poll_str *poll = arg; 2547 struct pcic_handle *ph = poll->ph; 2548 struct pccbb_softc *sc = ph->sc; 2549 int s; 2550 u_int32_t spsr; /* socket present-state reg */ 2551 2552 timeout(pccbb_pcmcia_poll, arg, hz*2); 2553 switch (poll->level) { 2554 case IPL_NET: 2555 s = splnet(); 2556 break; 2557 case IPL_BIO: 2558 s = splbio(); 2559 break; 2560 case IPL_TTY: /* fallthrough */ 2561 default: 2562 s = spltty(); 2563 break; 2564 } 2565 2566 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2567 2568 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2569 if (!(spsr & 0x40)) /* CINT low */ 2570 #else 2571 if (1) 2572 #endif 2573 { 2574 if ((*poll->func)(poll->arg) > 0) { 2575 ++poll->count; 2576 // printf("intr: reported from poller, 0x%x\n", spsr); 2577 #if defined LEVEL2 2578 } else { 2579 printf("intr: miss! 0x%x\n", spsr); 2580 #endif 2581 } 2582 } 2583 splx(s); 2584 } 2585 #endif /* defined CB_PCMCIA_POLL */ 2586 2587 2588 2589 /* 2590 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2591 * struct pcmcia_function *pf, 2592 * int ipl, 2593 * int (*func)(void *), 2594 * void *arg); 2595 * 2596 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2597 */ 2598 STATIC void * 2599 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2600 pcmcia_chipset_handle_t pch; 2601 struct pcmcia_function *pf; 2602 int ipl; 2603 int (*func) __P((void *)); 2604 void *arg; 2605 { 2606 struct pcic_handle *ph = (struct pcic_handle *)pch; 2607 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2608 pci_intr_handle_t handle; 2609 void *ih; 2610 2611 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2612 /* what should I do? */ 2613 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2614 DPRINTF(("%s does not provide edge nor pulse interrupt\n", 2615 sc->sc_dev.dv_xname)); 2616 return NULL; 2617 } 2618 /* 2619 * XXX Noooooo! The interrupt flag must set properly!! 2620 * dumb pcmcia driver!! 2621 */ 2622 } 2623 2624 if (pci_intr_map(sc->sc_pc, sc->sc_intrtag, sc->sc_intrpin, 2625 sc->sc_intrline, &handle)) { 2626 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 2627 return NULL; 2628 } 2629 DPRINTF(("pccbb_pcmcia_intr_establish: line %d, handle %d\n", 2630 sc->sc_intrline, handle)); 2631 2632 if (NULL != (ih = pci_intr_establish(sc->sc_pc, handle, ipl, func, arg))) 2633 { 2634 u_int32_t cbctrl; 2635 2636 if ((CB_TI113X == sc->sc_chipset)) { 2637 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 2638 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* PCI functional intr req */ 2639 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 2640 } 2641 } 2642 #if defined PCCBB_PCMCIA_POLL 2643 if (pccbb_poll_n < 10) { 2644 pccbb_poll[pccbb_poll_n].arg = arg; 2645 pccbb_poll[pccbb_poll_n].func = func; 2646 pccbb_poll[pccbb_poll_n].level = ipl; 2647 pccbb_poll[pccbb_poll_n].count = 0; 2648 pccbb_poll[pccbb_poll_n].num = pccbb_poll_n; 2649 pccbb_poll[pccbb_poll_n].ph = ph; 2650 timeout(pccbb_pcmcia_poll, &pccbb_poll[pccbb_poll_n++], hz*2); 2651 printf("polling set\n"); 2652 } 2653 #endif 2654 #if defined SHOW_REGS 2655 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 2656 #endif 2657 2658 return ih; 2659 } 2660 2661 2662 2663 2664 /* 2665 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2666 * void *ih) 2667 * 2668 * This function disables PC-Card interrupt. 2669 */ 2670 STATIC void 2671 pccbb_pcmcia_intr_disestablish(pch, ih) 2672 pcmcia_chipset_handle_t pch; 2673 void *ih; 2674 { 2675 struct pcic_handle *ph = (struct pcic_handle *)pch; 2676 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2677 2678 pci_intr_disestablish(sc->sc_pc, ih); 2679 } 2680 2681 2682 2683 2684 #if rbus 2685 /* 2686 * static int 2687 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2688 * bus_addr_t addr, bus_size_t size, 2689 * bus_addr_t mask, bus_size_t align, 2690 * int flags, bus_addr_t *addrp; 2691 * bus_space_handle_t *bshp) 2692 * 2693 * This function allocates a portion of memory or io space for 2694 * clients. This function is called from CardBus card drivers. 2695 */ 2696 static int 2697 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2698 cardbus_chipset_tag_t ct; 2699 rbus_tag_t rb; 2700 bus_addr_t addr; 2701 bus_size_t size; 2702 bus_addr_t mask; 2703 bus_size_t align; 2704 int flags; 2705 bus_addr_t *addrp; 2706 bus_space_handle_t *bshp; 2707 { 2708 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2709 2710 DPRINTF(("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", addr, size, mask, align)); 2711 2712 if (align == 0) { 2713 align = size; 2714 } 2715 2716 if (rb->rb_bt == sc->sc_memt) { 2717 if (align < 16) { 2718 return 1; 2719 } 2720 } else if (rb->rb_bt == sc->sc_iot) { 2721 if (align < 4) { 2722 return 1; 2723 } 2724 } else { 2725 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2726 rb->rb_bt)); 2727 return 1; 2728 /* XXX: panic here? */ 2729 } 2730 2731 /* XXX: hack for avoiding ISA image */ 2732 if (mask < 0x3ff) { 2733 mask = 0x3ff; 2734 addr = 0x300; 2735 } 2736 2737 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2738 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2739 return 1; 2740 } 2741 2742 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2743 2744 return 0; 2745 } 2746 2747 2748 2749 2750 2751 /* 2752 * static int 2753 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2754 * bus_space_handle_t *bshp, bus_size_t size); 2755 * 2756 * This function is called from CardBus card drivers. 2757 */ 2758 static int 2759 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2760 cardbus_chipset_tag_t ct; 2761 rbus_tag_t rb; 2762 bus_space_handle_t bsh; 2763 bus_size_t size; 2764 { 2765 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2766 bus_space_tag_t bt = rb->rb_bt; 2767 2768 pccbb_close_win(sc, bt, bsh, size); 2769 2770 if (bt == sc->sc_memt) { 2771 } else if (bt == sc->sc_iot) { 2772 } else { 2773 return 1; 2774 /* XXX: panic here? */ 2775 } 2776 2777 return rbus_space_free(rb, bsh, size, NULL); 2778 } 2779 #endif /* rbus */ 2780 2781 2782 #if rbus 2783 2784 static int 2785 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2786 struct pccbb_softc *sc; 2787 bus_space_tag_t bst; 2788 bus_addr_t addr; 2789 bus_size_t size; 2790 bus_space_handle_t bsh; 2791 int flags; 2792 { 2793 struct pccbb_win_chain **top; 2794 bus_addr_t align; 2795 2796 top = &sc->sc_iowindow; 2797 align = 0x04; 2798 if (sc->sc_memt == bst) { 2799 top = &sc->sc_memwindow; 2800 align = 0x1000; 2801 DPRINTF(("using memory window, %x %x %x\n\n", 2802 sc->sc_iot, sc->sc_memt, bst)); 2803 } 2804 2805 if (pccbb_winlist_insert(top, addr, size, bsh, flags)) { 2806 printf("winlist insert fails:\n"); 2807 } 2808 pccbb_winset(align, sc, bst); 2809 2810 return 0; 2811 } 2812 2813 2814 2815 static int 2816 pccbb_close_win(sc, bst, bsh, size) 2817 struct pccbb_softc *sc; 2818 bus_space_tag_t bst; 2819 bus_space_handle_t bsh; 2820 bus_size_t size; 2821 { 2822 struct pccbb_win_chain **top; 2823 bus_addr_t align; 2824 2825 top = &sc->sc_iowindow; 2826 align = 0x04; 2827 if (sc->sc_memt == bst) { 2828 top = &sc->sc_memwindow; 2829 align = 0x1000; 2830 } 2831 2832 if (pccbb_winlist_delete(top, bsh, size)) { 2833 printf("winlist delete fails:\n"); 2834 } 2835 pccbb_winset(align, sc, bst); 2836 2837 return 0; 2838 } 2839 2840 2841 static int 2842 pccbb_winlist_insert(top, start, size, bsh, flags) 2843 struct pccbb_win_chain **top; 2844 bus_addr_t start; 2845 bus_size_t size; 2846 bus_space_handle_t bsh; 2847 int flags; 2848 { 2849 struct pccbb_win_chain *chainp = *top; 2850 struct pccbb_win_chain *before = *top; 2851 struct pccbb_win_chain *elem; 2852 2853 if (*top == NULL) { 2854 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2855 return 1; /* fail */ 2856 } 2857 2858 elem->wc_start = start; 2859 elem->wc_end = start + size - 1; 2860 elem->wc_handle = bsh; 2861 elem->wc_flags = flags; 2862 2863 *top = elem; 2864 elem->wc_next = NULL; 2865 return 0; 2866 } 2867 2868 for(; chainp && chainp->wc_start <= start; chainp = chainp->wc_next) { 2869 before = chainp; 2870 } 2871 2872 if (chainp != NULL) { 2873 if (chainp->wc_start < start + size) { 2874 printf("fatal! 0x%lx 0x%lx\n", chainp->wc_start, start+size); 2875 return 1; 2876 } 2877 } 2878 if ((before != *top) && (before->wc_end >= start)) { 2879 printf("fatal!! 0x%lx 0x%lx\n", before->wc_end, start); 2880 return 1; 2881 } 2882 2883 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2884 return 1; /* fail */ 2885 } 2886 2887 elem->wc_start = start; 2888 elem->wc_end = start + size - 1; 2889 elem->wc_handle = bsh; 2890 elem->wc_flags = flags; 2891 2892 elem->wc_next = chainp; 2893 if (chainp == *top) { 2894 *top = elem; 2895 } else { 2896 before->wc_next = elem; 2897 } 2898 return 0; 2899 } 2900 2901 2902 2903 2904 static int 2905 pccbb_winlist_delete(top, bsh, size) 2906 struct pccbb_win_chain **top; 2907 bus_space_handle_t bsh; 2908 bus_size_t size; 2909 { 2910 struct pccbb_win_chain *chainp = *top; 2911 struct pccbb_win_chain **before = top; 2912 2913 for (; chainp && chainp->wc_handle != bsh; chainp = chainp->wc_next) { 2914 before = &chainp->wc_next; 2915 } 2916 2917 if (chainp == NULL) { 2918 return 1; /* fail: no candidate to remove */ 2919 } 2920 2921 if (chainp->wc_end - chainp->wc_start != size - 1) { 2922 printf("fatal!!! 0x%lx\n", chainp->wc_start); 2923 return 1; /* fail: no candidate to remove */ 2924 } 2925 2926 *before = chainp->wc_next; 2927 free(chainp, M_DEVBUF); 2928 2929 return 0; 2930 } 2931 2932 2933 2934 static void 2935 pccbb_winset(align, sc, bst) 2936 bus_addr_t align; 2937 struct pccbb_softc *sc; 2938 bus_space_tag_t bst; 2939 { 2940 pci_chipset_tag_t pc; 2941 pcitag_t tag; 2942 bus_addr_t mask = ~(align - 1); 2943 struct { 2944 cardbusreg_t win_start; 2945 cardbusreg_t win_limit; 2946 int win_flags; 2947 } win[2]; 2948 struct pccbb_win_chain *chainp; 2949 int offs; 2950 2951 win[0].win_start = 0xffffffff; 2952 win[0].win_limit = 0; 2953 win[1].win_start = 0xffffffff; 2954 win[1].win_limit = 0; 2955 2956 chainp = sc->sc_iowindow; 2957 offs = 0x2c; 2958 if (sc->sc_memt == bst) { 2959 chainp = sc->sc_memwindow; 2960 offs = 0x1c; 2961 } 2962 2963 if (chainp) { 2964 win[0].win_start = chainp->wc_start & mask; 2965 win[0].win_limit = chainp->wc_end & mask; 2966 win[0].win_flags = chainp->wc_flags; 2967 chainp = chainp->wc_next; 2968 } 2969 2970 for(; chainp; chainp = chainp->wc_next) { 2971 if (win[1].win_start == 0xffffffff) { 2972 /* window 1 is not used */ 2973 if ((win[0].win_flags == chainp->wc_flags) && 2974 (win[0].win_limit + align >= (chainp->wc_start & mask))) { 2975 /* concatinate */ 2976 win[0].win_limit = chainp->wc_end & mask; 2977 } else { 2978 /* make new window */ 2979 win[1].win_start = chainp->wc_start & mask; 2980 win[1].win_limit = chainp->wc_end & mask; 2981 win[1].win_flags = chainp->wc_flags; 2982 } 2983 continue; 2984 } 2985 2986 /* Both windows are engagad. */ 2987 if (win[0].win_flags == win[1].win_flags) { 2988 /* same flags */ 2989 if (win[0].win_flags == chainp->wc_flags) { 2990 2991 win[1].win_limit = chainp->wc_end & mask; 2992 2993 if (win[1].win_start - (win[0].win_limit + align) 2994 < (chainp->wc_start & mask) - (win[1].win_limit + align)) { 2995 win[0].win_limit = win[1].win_limit; 2996 win[1].win_start = chainp->wc_start & mask; 2997 } 2998 } else { 2999 /* different flags */ 3000 3001 /* concatinate win0 and win1 */ 3002 win[0].win_limit = win[1].win_limit; 3003 /* allocate win[1] to new space */ 3004 win[1].win_start = chainp->wc_start & mask; 3005 win[1].win_limit = chainp->wc_end & mask; 3006 win[1].win_flags = chainp->wc_flags; 3007 } 3008 } else { 3009 /* the flags of win[0] and win[1] is different */ 3010 if (win[0].win_flags == chainp->wc_flags) { 3011 win[0].win_limit = chainp->wc_end & mask; 3012 } else { 3013 win[1].win_limit = chainp->wc_end & mask; 3014 } 3015 } 3016 } 3017 3018 pc = sc->sc_pc; 3019 tag = sc->sc_tag; 3020 pci_conf_write(pc, tag, offs, win[0].win_start); 3021 pci_conf_write(pc, tag, offs+4, win[0].win_limit); 3022 pci_conf_write(pc, tag, offs+8, win[1].win_start); 3023 pci_conf_write(pc, tag, offs+12, win[1].win_limit); 3024 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3025 pci_conf_read(pc, tag, offs), 3026 pci_conf_read(pc, tag, offs+4) + align, 3027 pci_conf_read(pc, tag, offs+8), 3028 pci_conf_read(pc, tag, offs+12) + align)); 3029 3030 if (bst == sc->sc_memt) { 3031 if (win[0].win_start & PCCBB_MEM_CACHABLE) { 3032 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3033 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3034 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3035 } 3036 if (win[1].win_start & PCCBB_MEM_CACHABLE) { 3037 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3038 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3039 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3040 } 3041 } 3042 } 3043 3044 #endif /* rbus */ 3045
Indexes created Thu Sep 25 16:09:42 GMT 2025