pccbb.c revision 1.40
1 /* $NetBSD: pccbb.c,v 1.40 2000/06/07 09:02:46 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 struct yenta_chipinfo *yc; 355 356 /* Loop over except the last default entry. */ 357 for (yc = yc_chipsets; yc < yc_chipsets + 358 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 359 if (pci_id == yc->yc_id) 360 break; 361 362 if (flagp != NULL) 363 *flagp = yc->yc_flags; 364 365 return (yc->yc_chiptype); 366 } 367 368 static void 369 pccbb_shutdown(void *arg) 370 { 371 struct pccbb_softc *sc = arg; 372 pcireg_t command; 373 374 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 375 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 376 0); 377 378 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 379 380 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 381 PCI_COMMAND_MASTER_ENABLE); 382 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 383 384 } 385 386 void 387 pccbbattach(parent, self, aux) 388 struct device *parent; 389 struct device *self; 390 void *aux; 391 { 392 struct pccbb_softc *sc = (void *)self; 393 struct pci_attach_args *pa = aux; 394 pci_chipset_tag_t pc = pa->pa_pc; 395 pcireg_t sock_base, busreg; 396 bus_addr_t sockbase; 397 char devinfo[256]; 398 int flags; 399 400 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 401 402 pci_devinfo(pa->pa_id, 0, 0, devinfo); 403 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 404 #ifdef CBB_DEBUG 405 printf(" (chipflags %x)", flags); 406 #endif 407 printf("\n"); 408 409 TAILQ_INIT(&sc->sc_memwindow); 410 TAILQ_INIT(&sc->sc_iowindow); 411 412 #if rbus 413 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 414 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 415 #endif /* rbus */ 416 417 sc->sc_base_memh = 0; 418 419 /* 420 * MAP socket registers and ExCA registers on memory-space 421 * When no valid address is set on socket base registers (on pci 422 * config space), get it not polite way. 423 */ 424 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 425 426 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 427 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 428 /* The address must be valid. */ 429 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 430 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 431 printf("%s: can't map socket base address 0x%x\n", 432 sc->sc_dev.dv_xname, sock_base); 433 /* 434 * I think it's funny: socket base registers must be 435 * mapped on memory space, but ... 436 */ 437 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 438 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 439 NULL)) { 440 printf("%s: can't map socket base address" 441 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 442 sockbase); 443 /* give up... allocate reg space via rbus. */ 444 sc->sc_base_memh = 0; 445 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 446 } 447 } else { 448 DPRINTF(("%s: socket base address 0x%lx\n", 449 sc->sc_dev.dv_xname, sockbase)); 450 } 451 } 452 453 sc->sc_mem_start = 0; /* XXX */ 454 sc->sc_mem_end = 0xffffffff; /* XXX */ 455 456 /* 457 * When interrupt isn't routed correctly, give up probing cbb and do 458 * not kill pcic-compatible port. 459 */ 460 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 461 printf("%s: NOT USED because of unconfigured interrupt\n", 462 sc->sc_dev.dv_xname); 463 return; 464 } 465 466 /* 467 * When bus number isn't set correctly, give up using 32-bit CardBus 468 * mode. 469 */ 470 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 471 #if notyet 472 if (((busreg >> 8) & 0xff) == 0) { 473 printf("%s: CardBus support disabled because of unconfigured bus number\n", 474 sc->sc_dev.dv_xname); 475 flags |= PCCBB_PCMCIA_16BITONLY; 476 } 477 #endif 478 479 /* pccbb_machdep.c end */ 480 481 #if defined CBB_DEBUG 482 { 483 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 484 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 485 intrname[pa->pa_intrpin], pa->pa_intrline); 486 } 487 #endif 488 489 /* setup softc */ 490 sc->sc_pc = pc; 491 sc->sc_iot = pa->pa_iot; 492 sc->sc_memt = pa->pa_memt; 493 sc->sc_dmat = pa->pa_dmat; 494 sc->sc_tag = pa->pa_tag; 495 sc->sc_function = pa->pa_function; 496 497 sc->sc_intrline = pa->pa_intrline; 498 sc->sc_intrtag = pa->pa_intrtag; 499 sc->sc_intrpin = pa->pa_intrpin; 500 501 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 502 503 shutdownhook_establish(pccbb_shutdown, sc); 504 505 config_defer(self, pccbb_pci_callback); 506 } 507 508 509 510 511 /* 512 * static void pccbb_pci_callback(struct device *self) 513 * 514 * The actual attach routine: get memory space for YENTA register 515 * space, setup YENTA register and route interrupt. 516 * 517 * This function should be deferred because this device may obtain 518 * memory space dynamically. This function must avoid obtaining 519 * memory area which has already kept for another device. Also, 520 * this function MUST be done before ISA attach process because this 521 * function kills pcic compatible port used by ISA pcic. 522 */ 523 static void 524 pccbb_pci_callback(self) 525 struct device *self; 526 { 527 struct pccbb_softc *sc = (void *)self; 528 pci_chipset_tag_t pc = sc->sc_pc; 529 bus_space_tag_t base_memt; 530 bus_space_handle_t base_memh; 531 u_int32_t maskreg; 532 pci_intr_handle_t ih; 533 const char *intrstr = NULL; 534 bus_addr_t sockbase; 535 struct cbslot_attach_args cba; 536 struct pcmciabus_attach_args paa; 537 struct cardslot_attach_args caa; 538 struct cardslot_softc *csc; 539 540 if (0 == sc->sc_base_memh) { 541 /* The socket registers aren't mapped correctly. */ 542 #if rbus 543 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 544 (sc->sc_chipset == CB_RX5C47X 545 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 546 0, &sockbase, &sc->sc_base_memh)) { 547 return; 548 } 549 sc->sc_base_memt = sc->sc_memt; 550 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 551 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 552 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 553 PCI_SOCKBASE))); 554 #else 555 sc->sc_base_memt = sc->sc_memt; 556 #if !defined CBB_PCI_BASE 557 #define CBB_PCI_BASE 0x20000000 558 #endif 559 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 560 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 561 /* cannot allocate memory space */ 562 return; 563 } 564 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 565 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 566 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 567 sc->sc_tag, PCI_SOCKBASE))); 568 #endif 569 } 570 571 /* bus bridge initialization */ 572 pccbb_chipinit(sc); 573 574 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 575 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 576 577 /* CSC Interrupt: Card detect interrupt on */ 578 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 579 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 580 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 581 /* reset interrupt */ 582 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 583 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 584 585 /* clear data structure for child device interrupt handlers */ 586 sc->sc_pil = NULL; 587 sc->sc_pil_intr_enable = 1; 588 589 /* Map and establish the interrupt. */ 590 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 591 sc->sc_intrline, &ih)) { 592 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 593 return; 594 } 595 intrstr = pci_intr_string(pc, ih); 596 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 597 598 if (sc->sc_ih == NULL) { 599 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 600 if (intrstr != NULL) { 601 printf(" at %s", intrstr); 602 } 603 printf("\n"); 604 return; 605 } 606 607 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 608 powerhook_establish(pccbb_powerhook, sc); 609 610 { 611 u_int32_t sockstat = 612 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 613 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 614 sc->sc_flags |= CBB_CARDEXIST; 615 } 616 } 617 618 /* 619 * attach cardbus 620 */ 621 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 622 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 623 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 624 625 /* initialize cbslot_attach */ 626 cba.cba_busname = "cardbus"; 627 cba.cba_iot = sc->sc_iot; 628 cba.cba_memt = sc->sc_memt; 629 cba.cba_dmat = sc->sc_dmat; 630 cba.cba_bus = (busreg >> 8) & 0x0ff; 631 cba.cba_cc = (void *)sc; 632 cba.cba_cf = &pccbb_funcs; 633 cba.cba_intrline = sc->sc_intrline; 634 635 #if rbus 636 cba.cba_rbus_iot = sc->sc_rbus_iot; 637 cba.cba_rbus_memt = sc->sc_rbus_memt; 638 #endif 639 640 cba.cba_cacheline = PCI_CACHELINE(bhlc); 641 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 642 643 printf("%s: cacheline 0x%x lattimer 0x%x\n", 644 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 645 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 646 busreg); 647 #if defined SHOW_REGS 648 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 649 sc->sc_base_memh); 650 #endif 651 } 652 653 pccbb_pcmcia_attach_setup(sc, &paa); 654 caa.caa_cb_attach = NULL; 655 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 656 caa.caa_cb_attach = &cba; 657 } 658 caa.caa_16_attach = &paa; 659 caa.caa_ph = &sc->sc_pcmcia_h; 660 661 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 662 DPRINTF(("pccbbattach: found cardslot\n")); 663 sc->sc_csc = csc; 664 } 665 666 return; 667 } 668 669 670 671 672 673 /* 674 * static void pccbb_chipinit(struct pccbb_softc *sc) 675 * 676 * This function initialize YENTA chip registers listed below: 677 * 1) PCI command reg, 678 * 2) PCI and CardBus latency timer, 679 * 3) disable legacy (PCIC-compatible) io, 680 * 4) route PCI interrupt, 681 * 5) close all memory and io windows. 682 */ 683 static void 684 pccbb_chipinit(sc) 685 struct pccbb_softc *sc; 686 { 687 pci_chipset_tag_t pc = sc->sc_pc; 688 pcitag_t tag = sc->sc_tag; 689 pcireg_t reg; 690 691 /* 692 * Set PCI command reg. 693 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 694 */ 695 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 696 /* I believe it is harmless. */ 697 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 698 PCI_COMMAND_MASTER_ENABLE); 699 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 700 701 /* 702 * Set CardBus latency timer. 703 */ 704 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 705 if (PCI_CB_LATENCY(reg) < 0x20) { 706 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 707 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 708 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 709 } 710 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 711 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 712 713 /* 714 * Set PCI latency timer. 715 */ 716 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 717 if (PCI_LATTIMER(reg) < 0x10) { 718 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 719 reg |= (0x10 << PCI_LATTIMER_SHIFT); 720 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 721 } 722 DPRINTF(("PCI latency timer 0x%x (%x)\n", 723 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 724 725 /* Disable legacy register mapping. */ 726 switch (sc->sc_chipset) { 727 case CB_RX5C46X: /* fallthrough */ 728 #if 0 729 case CB_RX5C47X: 730 #endif 731 /* 732 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 733 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 734 * CardBus bridges have special bits on Bridge control reg (addr 735 * 0x3e on PCI config space). 736 */ 737 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 738 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 739 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 740 break; 741 742 default: 743 /* XXX I don't know proper way to kill legacy I/O. */ 744 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 745 break; 746 } 747 748 /* Route functional interrupts to PCI. */ 749 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 750 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 751 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 752 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 753 754 switch (sc->sc_chipset) { 755 case CB_TI113X: 756 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 757 /* This bit is shared, but may read as 0 on some chips, so set 758 it explicitly on both functions. */ 759 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 760 /* CSC intr enable */ 761 reg |= PCI113X_CBCTRL_PCI_CSC; 762 /* functional intr prohibit */ 763 reg &= ~PCI113X_CBCTRL_PCI_INTR; 764 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 765 break; 766 767 case CB_TOPIC95B: 768 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 769 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 770 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 771 772 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 773 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 774 sc->sc_dev.dv_xname, reg)); 775 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 776 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 777 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 778 DPRINTF(("0x%x\n", reg)); 779 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 780 break; 781 } 782 783 /* Close all memory and I/O windows. */ 784 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 785 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 786 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 787 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 788 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 789 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 790 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 791 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 792 } 793 794 795 796 797 /* 798 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 799 * struct pcmciabus_attach_args *paa) 800 * 801 * This function attaches 16-bit PCcard bus. 802 */ 803 STATIC void 804 pccbb_pcmcia_attach_setup(sc, paa) 805 struct pccbb_softc *sc; 806 struct pcmciabus_attach_args *paa; 807 { 808 struct pcic_handle *ph = &sc->sc_pcmcia_h; 809 #if rbus 810 rbus_tag_t rb; 811 #endif 812 813 /* initialize pcmcia part in pccbb_softc */ 814 ph->ph_parent = (struct device *)sc; 815 ph->sock = sc->sc_function; 816 ph->flags = 0; 817 ph->shutdown = 0; 818 ph->ih_irq = sc->sc_intrline; 819 ph->ph_bus_t = sc->sc_base_memt; 820 ph->ph_bus_h = sc->sc_base_memh; 821 ph->ph_read = pccbb_pcmcia_read; 822 ph->ph_write = pccbb_pcmcia_write; 823 sc->sc_pct = &pccbb_pcmcia_funcs; 824 825 /* 826 * We need to do a few things here: 827 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 828 * setting the IRQ numbers to 0. 829 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 830 * routing of CSC interrupts (e.g. card removal) to PCI while in 831 * PCMCIA mode. We just leave this set all the time. 832 * 3) Enable card insertion/removal interrupts in case the chip also 833 * needs that while in PCMCIA mode. 834 * 4) Clear any pending CSC interrupt. 835 */ 836 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 837 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 838 Pcic_read(ph, PCIC_CSC); 839 840 /* initialize pcmcia bus attachment */ 841 paa->paa_busname = "pcmcia"; 842 paa->pct = sc->sc_pct; 843 paa->pch = ph; 844 paa->iobase = 0; /* I don't use them */ 845 paa->iosize = 0; 846 #if rbus 847 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 848 paa->iobase = rb->rb_start + rb->rb_offset; 849 paa->iosize = rb->rb_end - rb->rb_start; 850 #endif 851 852 return; 853 } 854 855 #if 0 856 STATIC void 857 pccbb_pcmcia_attach_card(ph) 858 struct pcic_handle *ph; 859 { 860 if (ph->flags & PCIC_FLAG_CARDP) { 861 panic("pccbb_pcmcia_attach_card: already attached"); 862 } 863 864 /* call the MI attach function */ 865 pcmcia_card_attach(ph->pcmcia); 866 867 ph->flags |= PCIC_FLAG_CARDP; 868 } 869 870 STATIC void 871 pccbb_pcmcia_detach_card(ph, flags) 872 struct pcic_handle *ph; 873 int flags; 874 { 875 if (!(ph->flags & PCIC_FLAG_CARDP)) { 876 panic("pccbb_pcmcia_detach_card: already detached"); 877 } 878 879 ph->flags &= ~PCIC_FLAG_CARDP; 880 881 /* call the MI detach function */ 882 pcmcia_card_detach(ph->pcmcia, flags); 883 } 884 #endif 885 886 /* 887 * int pccbbintr(arg) 888 * void *arg; 889 * This routine handles the interrupt from Yenta PCI-CardBus bridge 890 * itself. 891 */ 892 int 893 pccbbintr(arg) 894 void *arg; 895 { 896 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 897 u_int32_t sockevent, sockstate; 898 bus_space_tag_t memt = sc->sc_base_memt; 899 bus_space_handle_t memh = sc->sc_base_memh; 900 struct pcic_handle *ph = &sc->sc_pcmcia_h; 901 902 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 903 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 904 Pcic_read(ph, PCIC_CSC); 905 906 if (sockevent == 0) { 907 /* This intr is not for me: it may be for my child devices. */ 908 if (sc->sc_pil_intr_enable) { 909 return pccbbintr_function(sc); 910 } else { 911 return 0; 912 } 913 } 914 915 if (sockevent & CB_SOCKET_EVENT_CD) { 916 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 917 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 918 /* A card should be removed. */ 919 if (sc->sc_flags & CBB_CARDEXIST) { 920 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 921 sockevent)); 922 DPRINTF((" card removed, 0x%08x\n", sockstate)); 923 sc->sc_flags &= ~CBB_CARDEXIST; 924 if (sc->sc_csc->sc_status & 925 CARDSLOT_STATUS_CARD_16) { 926 #if 0 927 struct pcic_handle *ph = 928 &sc->sc_pcmcia_h; 929 930 pcmcia_card_deactivate(ph->pcmcia); 931 pccbb_pcmcia_socket_disable(ph); 932 pccbb_pcmcia_detach_card(ph, 933 DETACH_FORCE); 934 #endif 935 cardslot_event_throw(sc->sc_csc, 936 CARDSLOT_EVENT_REMOVAL_16); 937 } else if (sc->sc_csc->sc_status & 938 CARDSLOT_STATUS_CARD_CB) { 939 /* Cardbus intr removed */ 940 cardslot_event_throw(sc->sc_csc, 941 CARDSLOT_EVENT_REMOVAL_CB); 942 } 943 } 944 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 945 /* 946 * The pccbbintr may called from powerdown hook when 947 * the system resumed, to detect the card 948 * insertion/removal during suspension. 949 */ 950 (sc->sc_flags & CBB_CARDEXIST) == 0) { 951 if (sc->sc_flags & CBB_INSERTING) { 952 callout_stop(&sc->sc_insert_ch); 953 } 954 callout_reset(&sc->sc_insert_ch, hz / 10, 955 pci113x_insert, sc); 956 sc->sc_flags |= CBB_INSERTING; 957 } 958 } 959 960 return (1); 961 } 962 963 /* 964 * static int pccbbintr_function(struct pccbb_softc *sc) 965 * 966 * This function calls each interrupt handler registered at the 967 * bridge. The interrupt handlers are called in registered order. 968 */ 969 static int 970 pccbbintr_function(sc) 971 struct pccbb_softc *sc; 972 { 973 int retval = 0, val; 974 struct pccbb_intrhand_list *pil; 975 976 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 977 val = (*pil->pil_func) (pil->pil_arg); 978 retval = retval == 1 ? 1 : 979 retval == 0 ? val : val != 0 ? val : retval; 980 } 981 982 return retval; 983 } 984 985 static void 986 pci113x_insert(arg) 987 void *arg; 988 { 989 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 990 u_int32_t sockevent, sockstate; 991 992 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 993 CB_SOCKET_EVENT); 994 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 995 CB_SOCKET_STAT); 996 997 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 998 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 999 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1000 sc->sc_flags |= CBB_CARDEXIST; 1001 /* call pccard interrupt handler here */ 1002 if (sockstate & CB_SOCKET_STAT_16BIT) { 1003 /* 16-bit card found */ 1004 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1005 cardslot_event_throw(sc->sc_csc, 1006 CARDSLOT_EVENT_INSERTION_16); 1007 } else if (sockstate & CB_SOCKET_STAT_CB) { 1008 /* cardbus card found */ 1009 /* cardbus_attach_card(sc->sc_csc); */ 1010 cardslot_event_throw(sc->sc_csc, 1011 CARDSLOT_EVENT_INSERTION_CB); 1012 } else { 1013 /* who are you? */ 1014 } 1015 } else { 1016 callout_reset(&sc->sc_insert_ch, hz / 10, 1017 pci113x_insert, sc); 1018 } 1019 } 1020 1021 #define PCCBB_PCMCIA_OFFSET 0x800 1022 static u_int8_t 1023 pccbb_pcmcia_read(ph, reg) 1024 struct pcic_handle *ph; 1025 int reg; 1026 { 1027 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1028 PCCBB_PCMCIA_OFFSET + reg); 1029 } 1030 1031 static void 1032 pccbb_pcmcia_write(ph, reg, val) 1033 struct pcic_handle *ph; 1034 int reg; 1035 u_int8_t val; 1036 { 1037 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1038 val); 1039 } 1040 1041 /* 1042 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1043 */ 1044 STATIC int 1045 pccbb_ctrl(ct, command) 1046 cardbus_chipset_tag_t ct; 1047 int command; 1048 { 1049 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1050 1051 switch (command) { 1052 case CARDBUS_CD: 1053 if (2 == pccbb_detect_card(sc)) { 1054 int retval = 0; 1055 int status = cb_detect_voltage(sc); 1056 if (PCCARD_VCC_5V & status) { 1057 retval |= CARDBUS_5V_CARD; 1058 } 1059 if (PCCARD_VCC_3V & status) { 1060 retval |= CARDBUS_3V_CARD; 1061 } 1062 if (PCCARD_VCC_XV & status) { 1063 retval |= CARDBUS_XV_CARD; 1064 } 1065 if (PCCARD_VCC_YV & status) { 1066 retval |= CARDBUS_YV_CARD; 1067 } 1068 return retval; 1069 } else { 1070 return 0; 1071 } 1072 break; 1073 case CARDBUS_RESET: 1074 return cb_reset(sc); 1075 break; 1076 case CARDBUS_IO_ENABLE: /* fallthrough */ 1077 case CARDBUS_IO_DISABLE: /* fallthrough */ 1078 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1079 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1080 case CARDBUS_BM_ENABLE: /* fallthrough */ 1081 case CARDBUS_BM_DISABLE: /* fallthrough */ 1082 return pccbb_cardenable(sc, command); 1083 break; 1084 } 1085 1086 return 0; 1087 } 1088 1089 /* 1090 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1091 * This function returns true when it succeeds and returns false when 1092 * it fails. 1093 */ 1094 STATIC int 1095 pccbb_power(ct, command) 1096 cardbus_chipset_tag_t ct; 1097 int command; 1098 { 1099 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1100 1101 u_int32_t status, sock_ctrl; 1102 bus_space_tag_t memt = sc->sc_base_memt; 1103 bus_space_handle_t memh = sc->sc_base_memh; 1104 1105 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1106 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1107 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1108 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1109 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1110 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1111 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1112 "UNKNOWN", 1113 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1114 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1115 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1116 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1117 "UNKNOWN", command)); 1118 1119 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1120 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1121 1122 switch (command & CARDBUS_VCCMASK) { 1123 case CARDBUS_VCC_UC: 1124 break; 1125 case CARDBUS_VCC_5V: 1126 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1127 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1128 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1129 } else { 1130 printf("%s: BAD voltage request: no 5 V card\n", 1131 sc->sc_dev.dv_xname); 1132 } 1133 break; 1134 case CARDBUS_VCC_3V: 1135 if (CB_SOCKET_STAT_3VCARD & status) { 1136 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1137 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1138 } else { 1139 printf("%s: BAD voltage request: no 3.3 V card\n", 1140 sc->sc_dev.dv_xname); 1141 } 1142 break; 1143 case CARDBUS_VCC_0V: 1144 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1145 break; 1146 default: 1147 return 0; /* power NEVER changed */ 1148 break; 1149 } 1150 1151 switch (command & CARDBUS_VPPMASK) { 1152 case CARDBUS_VPP_UC: 1153 break; 1154 case CARDBUS_VPP_0V: 1155 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1156 break; 1157 case CARDBUS_VPP_VCC: 1158 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1159 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1160 break; 1161 case CARDBUS_VPP_12V: 1162 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1163 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1164 break; 1165 } 1166 1167 #if 0 1168 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1169 #endif 1170 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1171 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1172 1173 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1174 /* 1175 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1176 * time is 20 ms, some PC-Card bridge requires longer duration. 1177 */ 1178 delay(200 * 1000); 1179 1180 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1181 printf 1182 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1183 sc->sc_dev.dv_xname, sock_ctrl, status); 1184 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1185 (command & CARDBUS_VCCMASK) == 1186 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1187 CARDBUS_VCCMASK) == 1188 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1189 CARDBUS_VCCMASK) == 1190 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1191 CARDBUS_VCCMASK) == 1192 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1193 CARDBUS_VCCMASK) == 1194 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1195 CARDBUS_VCCMASK) == 1196 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1197 (command & CARDBUS_VPPMASK) == 1198 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1199 CARDBUS_VPPMASK) == 1200 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1201 CARDBUS_VPPMASK) == 1202 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1203 CARDBUS_VPPMASK) == 1204 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1205 #if 0 1206 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1207 u_int32_t force = 1208 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1209 /* Reset Bad Vcc request */ 1210 force &= ~CB_SOCKET_FORCE_BADVCC; 1211 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1212 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1213 CB_SOCKET_STAT)); 1214 return 1; 1215 } 1216 #endif 1217 return 0; 1218 } 1219 return 1; /* power changed correctly */ 1220 } 1221 1222 #if defined CB_PCMCIA_POLL 1223 struct cb_poll_str { 1224 void *arg; 1225 int (*func) __P((void *)); 1226 int level; 1227 pccard_chipset_tag_t ct; 1228 int count; 1229 struct callout poll_ch; 1230 }; 1231 1232 static struct cb_poll_str cb_poll[10]; 1233 static int cb_poll_n = 0; 1234 1235 static void cb_pcmcia_poll __P((void *arg)); 1236 1237 static void 1238 cb_pcmcia_poll(arg) 1239 void *arg; 1240 { 1241 struct cb_poll_str *poll = arg; 1242 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1243 struct pccbb_softc *sc = psc->cpc_parent; 1244 int s; 1245 u_int32_t spsr; /* socket present-state reg */ 1246 1247 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1248 switch (poll->level) { 1249 case IPL_NET: 1250 s = splnet(); 1251 break; 1252 case IPL_BIO: 1253 s = splbio(); 1254 break; 1255 case IPL_TTY: /* fallthrough */ 1256 default: 1257 s = spltty(); 1258 break; 1259 } 1260 1261 spsr = 1262 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1263 CB_SOCKET_STAT); 1264 1265 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1266 if (!(spsr & 0x40)) { /* CINT low */ 1267 #else 1268 if (1) { 1269 #endif 1270 if ((*poll->func) (poll->arg) == 1) { 1271 ++poll->count; 1272 printf("intr: reported from poller, 0x%x\n", spsr); 1273 #if defined LEVEL2 1274 } else { 1275 printf("intr: miss! 0x%x\n", spsr); 1276 #endif 1277 } 1278 } 1279 splx(s); 1280 } 1281 #endif /* defined CB_PCMCIA_POLL */ 1282 1283 /* 1284 * static int pccbb_detect_card(struct pccbb_softc *sc) 1285 * return value: 0 if no card exists. 1286 * 1 if 16-bit card exists. 1287 * 2 if cardbus card exists. 1288 */ 1289 static int 1290 pccbb_detect_card(sc) 1291 struct pccbb_softc *sc; 1292 { 1293 bus_space_handle_t base_memh = sc->sc_base_memh; 1294 bus_space_tag_t base_memt = sc->sc_base_memt; 1295 u_int32_t sockstat = 1296 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1297 int retval = 0; 1298 1299 /* CD1 and CD2 asserted */ 1300 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1301 /* card must be present */ 1302 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1303 /* NOTACARD DEASSERTED */ 1304 if (CB_SOCKET_STAT_CB & sockstat) { 1305 /* CardBus mode */ 1306 retval = 2; 1307 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1308 /* 16-bit mode */ 1309 retval = 1; 1310 } 1311 } 1312 } 1313 return retval; 1314 } 1315 1316 /* 1317 * STATIC int cb_reset(struct pccbb_softc *sc) 1318 * This function resets CardBus card. 1319 */ 1320 STATIC int 1321 cb_reset(sc) 1322 struct pccbb_softc *sc; 1323 { 1324 /* 1325 * Reset Assert at least 20 ms 1326 * Some machines request longer duration. 1327 */ 1328 int reset_duration = 1329 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1330 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1331 1332 /* Reset bit Assert (bit 6 at 0x3E) */ 1333 bcr |= CB_BCR_RESET_ENABLE; 1334 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1335 delay(reset_duration); 1336 1337 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1338 /* Reset bit Deassert (bit 6 at 0x3E) */ 1339 bcr &= ~CB_BCR_RESET_ENABLE; 1340 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1341 delay(reset_duration); 1342 } 1343 /* No card found on the slot. Keep Reset. */ 1344 return 1; 1345 } 1346 1347 /* 1348 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1349 * This function detect card Voltage. 1350 */ 1351 STATIC int 1352 cb_detect_voltage(sc) 1353 struct pccbb_softc *sc; 1354 { 1355 u_int32_t psr; /* socket present-state reg */ 1356 bus_space_tag_t iot = sc->sc_base_memt; 1357 bus_space_handle_t ioh = sc->sc_base_memh; 1358 int vol = PCCARD_VCC_UKN; /* set 0 */ 1359 1360 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1361 1362 if (0x400u & psr) { 1363 vol |= PCCARD_VCC_5V; 1364 } 1365 if (0x800u & psr) { 1366 vol |= PCCARD_VCC_3V; 1367 } 1368 1369 return vol; 1370 } 1371 1372 STATIC int 1373 cbbprint(aux, pcic) 1374 void *aux; 1375 const char *pcic; 1376 { 1377 /* 1378 struct cbslot_attach_args *cba = aux; 1379 1380 if (cba->cba_slot >= 0) { 1381 printf(" slot %d", cba->cba_slot); 1382 } 1383 */ 1384 return UNCONF; 1385 } 1386 1387 /* 1388 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1389 * This function enables and disables the card 1390 */ 1391 STATIC int 1392 pccbb_cardenable(sc, function) 1393 struct pccbb_softc *sc; 1394 int function; 1395 { 1396 u_int32_t command = 1397 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1398 1399 DPRINTF(("pccbb_cardenable:")); 1400 switch (function) { 1401 case CARDBUS_IO_ENABLE: 1402 command |= PCI_COMMAND_IO_ENABLE; 1403 break; 1404 case CARDBUS_IO_DISABLE: 1405 command &= ~PCI_COMMAND_IO_ENABLE; 1406 break; 1407 case CARDBUS_MEM_ENABLE: 1408 command |= PCI_COMMAND_MEM_ENABLE; 1409 break; 1410 case CARDBUS_MEM_DISABLE: 1411 command &= ~PCI_COMMAND_MEM_ENABLE; 1412 break; 1413 case CARDBUS_BM_ENABLE: 1414 command |= PCI_COMMAND_MASTER_ENABLE; 1415 break; 1416 case CARDBUS_BM_DISABLE: 1417 command &= ~PCI_COMMAND_MASTER_ENABLE; 1418 break; 1419 default: 1420 return 0; 1421 } 1422 1423 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1424 DPRINTF((" command reg 0x%x\n", command)); 1425 return 1; 1426 } 1427 1428 #if !rbus 1429 /* 1430 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1431 */ 1432 static int 1433 pccbb_io_open(ct, win, start, end) 1434 cardbus_chipset_tag_t ct; 1435 int win; 1436 u_int32_t start, end; 1437 { 1438 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1439 int basereg; 1440 int limitreg; 1441 1442 if ((win < 0) || (win > 2)) { 1443 #if defined DIAGNOSTIC 1444 printf("cardbus_io_open: window out of range %d\n", win); 1445 #endif 1446 return 0; 1447 } 1448 1449 basereg = win * 8 + 0x2c; 1450 limitreg = win * 8 + 0x30; 1451 1452 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1453 start, basereg, end, limitreg)); 1454 1455 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1456 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1457 return 1; 1458 } 1459 1460 /* 1461 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1462 */ 1463 static int 1464 pccbb_io_close(ct, win) 1465 cardbus_chipset_tag_t ct; 1466 int win; 1467 { 1468 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1469 int basereg; 1470 int limitreg; 1471 1472 if ((win < 0) || (win > 2)) { 1473 #if defined DIAGNOSTIC 1474 printf("cardbus_io_close: window out of range %d\n", win); 1475 #endif 1476 return 0; 1477 } 1478 1479 basereg = win * 8 + 0x2c; 1480 limitreg = win * 8 + 0x30; 1481 1482 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1483 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1484 return 1; 1485 } 1486 1487 /* 1488 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1489 */ 1490 static int 1491 pccbb_mem_open(ct, win, start, end) 1492 cardbus_chipset_tag_t ct; 1493 int win; 1494 u_int32_t start, end; 1495 { 1496 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1497 int basereg; 1498 int limitreg; 1499 1500 if ((win < 0) || (win > 2)) { 1501 #if defined DIAGNOSTIC 1502 printf("cardbus_mem_open: window out of range %d\n", win); 1503 #endif 1504 return 0; 1505 } 1506 1507 basereg = win * 8 + 0x1c; 1508 limitreg = win * 8 + 0x20; 1509 1510 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1511 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1512 return 1; 1513 } 1514 1515 /* 1516 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1517 */ 1518 static int 1519 pccbb_mem_close(ct, win) 1520 cardbus_chipset_tag_t ct; 1521 int win; 1522 { 1523 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1524 int basereg; 1525 int limitreg; 1526 1527 if ((win < 0) || (win > 2)) { 1528 #if defined DIAGNOSTIC 1529 printf("cardbus_mem_close: window out of range %d\n", win); 1530 #endif 1531 return 0; 1532 } 1533 1534 basereg = win * 8 + 0x1c; 1535 limitreg = win * 8 + 0x20; 1536 1537 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1538 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1539 return 1; 1540 } 1541 #endif 1542 1543 /* 1544 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1545 * int irq, 1546 * int level, 1547 * int (* func) __P((void *)), 1548 * void *arg) 1549 * 1550 * This function registers an interrupt handler at the bridge, in 1551 * order not to call the interrupt handlers of child devices when 1552 * a card-deletion interrupt occurs. 1553 * 1554 * The arguments irq and level are not used. 1555 */ 1556 static void * 1557 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1558 cardbus_chipset_tag_t ct; 1559 int irq, level; 1560 int (*func) __P((void *)); 1561 void *arg; 1562 { 1563 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1564 1565 return pccbb_intr_establish(sc, irq, level, func, arg); 1566 } 1567 1568 1569 /* 1570 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1571 * void *ih) 1572 * 1573 * This function removes an interrupt handler pointed by ih. 1574 */ 1575 static void 1576 pccbb_cb_intr_disestablish(ct, ih) 1577 cardbus_chipset_tag_t ct; 1578 void *ih; 1579 { 1580 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1581 1582 pccbb_intr_disestablish(sc, ih); 1583 } 1584 1585 1586 /* 1587 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1588 * int irq, 1589 * int level, 1590 * int (* func) __P((void *)), 1591 * void *arg) 1592 * 1593 * This function registers an interrupt handler at the bridge, in 1594 * order not to call the interrupt handlers of child devices when 1595 * a card-deletion interrupt occurs. 1596 * 1597 * The arguments irq and level are not used. 1598 */ 1599 static void * 1600 pccbb_intr_establish(sc, irq, level, func, arg) 1601 struct pccbb_softc *sc; 1602 int irq, level; 1603 int (*func) __P((void *)); 1604 void *arg; 1605 { 1606 struct pccbb_intrhand_list *pil, *newpil; 1607 1608 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1609 1610 if (sc->sc_pil == NULL) { 1611 /* initialize bridge intr routing */ 1612 1613 switch (sc->sc_chipset) { 1614 case CB_TI113X: 1615 { 1616 pcireg_t cbctrl = 1617 pci_conf_read(sc->sc_pc, sc->sc_tag, 1618 PCI_CBCTRL); 1619 /* functional intr enabled */ 1620 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1621 pci_conf_write(sc->sc_pc, sc->sc_tag, 1622 PCI_CBCTRL, cbctrl); 1623 break; 1624 } 1625 default: 1626 break; 1627 } 1628 } 1629 1630 /* 1631 * Allocate a room for interrupt handler structure. 1632 */ 1633 if (NULL == (newpil = 1634 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1635 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1636 return NULL; 1637 } 1638 1639 newpil->pil_func = func; 1640 newpil->pil_arg = arg; 1641 newpil->pil_next = NULL; 1642 1643 if (sc->sc_pil == NULL) { 1644 sc->sc_pil = newpil; 1645 } else { 1646 for (pil = sc->sc_pil; pil->pil_next != NULL; 1647 pil = pil->pil_next); 1648 pil->pil_next = newpil; 1649 } 1650 1651 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1652 1653 return newpil; 1654 } 1655 1656 /* 1657 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1658 * void *ih) 1659 * 1660 * This function removes an interrupt handler pointed by ih. 1661 */ 1662 static void 1663 pccbb_intr_disestablish(sc, ih) 1664 struct pccbb_softc *sc; 1665 void *ih; 1666 { 1667 struct pccbb_intrhand_list *pil, **pil_prev; 1668 1669 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1670 1671 pil_prev = &sc->sc_pil; 1672 1673 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1674 if (pil == ih) { 1675 *pil_prev = pil->pil_next; 1676 free(pil, M_DEVBUF); 1677 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1678 break; 1679 } 1680 pil_prev = &pil->pil_next; 1681 } 1682 1683 if (sc->sc_pil == NULL) { 1684 /* No interrupt handlers */ 1685 1686 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1687 1688 switch (sc->sc_chipset) { 1689 case CB_TI113X: 1690 { 1691 pcireg_t cbctrl = 1692 pci_conf_read(sc->sc_pc, sc->sc_tag, 1693 PCI_CBCTRL); 1694 /* functional intr disabled */ 1695 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1696 pci_conf_write(sc->sc_pc, sc->sc_tag, 1697 PCI_CBCTRL, cbctrl); 1698 break; 1699 } 1700 default: 1701 break; 1702 } 1703 } 1704 } 1705 1706 #if defined SHOW_REGS 1707 static void 1708 cb_show_regs(pc, tag, memt, memh) 1709 pci_chipset_tag_t pc; 1710 pcitag_t tag; 1711 bus_space_tag_t memt; 1712 bus_space_handle_t memh; 1713 { 1714 int i; 1715 printf("PCI config regs:"); 1716 for (i = 0; i < 0x50; i += 4) { 1717 if (i % 16 == 0) { 1718 printf("\n 0x%02x:", i); 1719 } 1720 printf(" %08x", pci_conf_read(pc, tag, i)); 1721 } 1722 for (i = 0x80; i < 0xb0; i += 4) { 1723 if (i % 16 == 0) { 1724 printf("\n 0x%02x:", i); 1725 } 1726 printf(" %08x", pci_conf_read(pc, tag, i)); 1727 } 1728 1729 if (memh == 0) { 1730 printf("\n"); 1731 return; 1732 } 1733 1734 printf("\nsocket regs:"); 1735 for (i = 0; i <= 0x10; i += 0x04) { 1736 printf(" %08x", bus_space_read_4(memt, memh, i)); 1737 } 1738 printf("\nExCA regs:"); 1739 for (i = 0; i < 0x08; ++i) { 1740 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1741 } 1742 printf("\n"); 1743 return; 1744 } 1745 #endif 1746 1747 /* 1748 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1749 * int busno, int devno, int function) 1750 * This is the function to make a tag to access config space of 1751 * a CardBus Card. It works same as pci_conf_read. 1752 */ 1753 static cardbustag_t 1754 pccbb_make_tag(cc, busno, devno, function) 1755 cardbus_chipset_tag_t cc; 1756 int busno, devno, function; 1757 { 1758 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1759 1760 return pci_make_tag(sc->sc_pc, busno, devno, function); 1761 } 1762 1763 static void 1764 pccbb_free_tag(cc, tag) 1765 cardbus_chipset_tag_t cc; 1766 cardbustag_t tag; 1767 { 1768 } 1769 1770 /* 1771 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1772 * cardbustag_t tag, int offset) 1773 * This is the function to read the config space of a CardBus Card. 1774 * It works same as pci_conf_read. 1775 */ 1776 static cardbusreg_t 1777 pccbb_conf_read(cc, tag, offset) 1778 cardbus_chipset_tag_t cc; 1779 cardbustag_t tag; 1780 int offset; /* register offset */ 1781 { 1782 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1783 1784 return pci_conf_read(sc->sc_pc, tag, offset); 1785 } 1786 1787 /* 1788 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1789 * int offs, cardbusreg_t val) 1790 * This is the function to write the config space of a CardBus Card. 1791 * It works same as pci_conf_write. 1792 */ 1793 static void 1794 pccbb_conf_write(cc, tag, reg, val) 1795 cardbus_chipset_tag_t cc; 1796 cardbustag_t tag; 1797 int reg; /* register offset */ 1798 cardbusreg_t val; 1799 { 1800 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1801 1802 pci_conf_write(sc->sc_pc, tag, reg, val); 1803 } 1804 1805 #if 0 1806 STATIC int 1807 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1808 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1809 int speed, int flags, 1810 bus_space_handle_t * iohp) 1811 #endif 1812 /* 1813 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1814 * bus_addr_t start, bus_size_t size, 1815 * bus_size_t align, 1816 * struct pcmcia_io_handle *pcihp 1817 * 1818 * This function only allocates I/O region for pccard. This function 1819 * never maps the allocated region to pccard I/O area. 1820 * 1821 * XXX: The interface of this function is not very good, I believe. 1822 */ 1823 STATIC int 1824 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1825 pcmcia_chipset_handle_t pch; 1826 bus_addr_t start; /* start address */ 1827 bus_size_t size; 1828 bus_size_t align; 1829 struct pcmcia_io_handle *pcihp; 1830 { 1831 struct pcic_handle *ph = (struct pcic_handle *)pch; 1832 bus_addr_t ioaddr; 1833 int flags = 0; 1834 bus_space_tag_t iot; 1835 bus_space_handle_t ioh; 1836 #if rbus 1837 rbus_tag_t rb; 1838 #endif 1839 if (align == 0) { 1840 align = size; /* XXX: funny??? */ 1841 } 1842 1843 /* 1844 * Allocate some arbitrary I/O space. 1845 */ 1846 1847 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1848 1849 #if rbus 1850 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1851 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1852 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1853 return 1; 1854 } 1855 #else 1856 if (start) { 1857 ioaddr = start; 1858 if (bus_space_map(iot, start, size, 0, &ioh)) { 1859 return 1; 1860 } 1861 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1862 (u_long) ioaddr, (u_long) size)); 1863 } else { 1864 flags |= PCMCIA_IO_ALLOCATED; 1865 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1866 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1867 size, align, 0, 0, &ioaddr, &ioh)) { 1868 /* No room be able to be get. */ 1869 return 1; 1870 } 1871 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1872 (u_long) ioaddr, (u_long) size)); 1873 } 1874 #endif 1875 1876 pcihp->iot = iot; 1877 pcihp->ioh = ioh; 1878 pcihp->addr = ioaddr; 1879 pcihp->size = size; 1880 pcihp->flags = flags; 1881 1882 return 0; 1883 } 1884 1885 /* 1886 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1887 * struct pcmcia_io_handle *pcihp) 1888 * 1889 * This function only frees I/O region for pccard. 1890 * 1891 * XXX: The interface of this function is not very good, I believe. 1892 */ 1893 void 1894 pccbb_pcmcia_io_free(pch, pcihp) 1895 pcmcia_chipset_handle_t pch; 1896 struct pcmcia_io_handle *pcihp; 1897 { 1898 #if !rbus 1899 bus_space_tag_t iot = pcihp->iot; 1900 #endif 1901 bus_space_handle_t ioh = pcihp->ioh; 1902 bus_size_t size = pcihp->size; 1903 1904 #if rbus 1905 struct pccbb_softc *sc = 1906 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1907 rbus_tag_t rb = sc->sc_rbus_iot; 1908 1909 rbus_space_free(rb, ioh, size, NULL); 1910 #else 1911 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1912 bus_space_free(iot, ioh, size); 1913 else 1914 bus_space_unmap(iot, ioh, size); 1915 #endif 1916 } 1917 1918 /* 1919 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1920 * bus_addr_t offset, bus_size_t size, 1921 * struct pcmcia_io_handle *pcihp, 1922 * int *windowp) 1923 * 1924 * This function maps the allocated I/O region to pccard. This function 1925 * never allocates any I/O region for pccard I/O area. I don't 1926 * understand why the original authors of pcmciabus separated alloc and 1927 * map. I believe the two must be unite. 1928 * 1929 * XXX: no wait timing control? 1930 */ 1931 int 1932 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1933 pcmcia_chipset_handle_t pch; 1934 int width; 1935 bus_addr_t offset; 1936 bus_size_t size; 1937 struct pcmcia_io_handle *pcihp; 1938 int *windowp; 1939 { 1940 struct pcic_handle *ph = (struct pcic_handle *)pch; 1941 bus_addr_t ioaddr = pcihp->addr + offset; 1942 int i, win; 1943 #if defined CBB_DEBUG 1944 static char *width_names[] = { "dynamic", "io8", "io16" }; 1945 #endif 1946 1947 /* Sanity check I/O handle. */ 1948 1949 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1950 panic("pccbb_pcmcia_io_map iot is bogus"); 1951 } 1952 1953 /* XXX Sanity check offset/size. */ 1954 1955 win = -1; 1956 for (i = 0; i < PCIC_IO_WINS; i++) { 1957 if ((ph->ioalloc & (1 << i)) == 0) { 1958 win = i; 1959 ph->ioalloc |= (1 << i); 1960 break; 1961 } 1962 } 1963 1964 if (win == -1) { 1965 return 1; 1966 } 1967 1968 *windowp = win; 1969 1970 /* XXX this is pretty gross */ 1971 1972 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1973 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1974 1975 /* XXX wtf is this doing here? */ 1976 1977 #if 0 1978 printf(" port 0x%lx", (u_long) ioaddr); 1979 if (size > 1) { 1980 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1981 } 1982 #endif 1983 1984 ph->io[win].addr = ioaddr; 1985 ph->io[win].size = size; 1986 ph->io[win].width = width; 1987 1988 /* actual dirty register-value changing in the function below. */ 1989 pccbb_pcmcia_do_io_map(ph, win); 1990 1991 return 0; 1992 } 1993 1994 /* 1995 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1996 * 1997 * This function changes register-value to map I/O region for pccard. 1998 */ 1999 static void 2000 pccbb_pcmcia_do_io_map(ph, win) 2001 struct pcic_handle *ph; 2002 int win; 2003 { 2004 static u_int8_t pcic_iowidth[3] = { 2005 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2006 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2007 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2008 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2009 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2010 }; 2011 2012 #define PCIC_SIA_START_LOW 0 2013 #define PCIC_SIA_START_HIGH 1 2014 #define PCIC_SIA_STOP_LOW 2 2015 #define PCIC_SIA_STOP_HIGH 3 2016 2017 int regbase_win = 0x8 + win * 0x04; 2018 u_int8_t ioctl, enable; 2019 2020 DPRINTF( 2021 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2022 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2023 ph->io[win].width * 8)); 2024 2025 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2026 ph->io[win].addr & 0xff); 2027 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2028 (ph->io[win].addr >> 8) & 0xff); 2029 2030 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2031 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2032 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2033 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2034 2035 ioctl = Pcic_read(ph, PCIC_IOCTL); 2036 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2037 switch (win) { 2038 case 0: 2039 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2040 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2041 PCIC_IOCTL_IO0_DATASIZE_MASK); 2042 ioctl |= pcic_iowidth[ph->io[win].width]; 2043 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2044 break; 2045 case 1: 2046 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2047 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2048 PCIC_IOCTL_IO1_DATASIZE_MASK); 2049 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2050 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2051 break; 2052 } 2053 Pcic_write(ph, PCIC_IOCTL, ioctl); 2054 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2055 #if defined CBB_DEBUG 2056 { 2057 u_int8_t start_low = 2058 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2059 u_int8_t start_high = 2060 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2061 u_int8_t stop_low = 2062 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2063 u_int8_t stop_high = 2064 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2065 printf 2066 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2067 start_low, start_high, stop_low, stop_high, ioctl, enable); 2068 } 2069 #endif 2070 } 2071 2072 /* 2073 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2074 * 2075 * This function unmaps I/O region. No return value. 2076 */ 2077 STATIC void 2078 pccbb_pcmcia_io_unmap(pch, win) 2079 pcmcia_chipset_handle_t pch; 2080 int win; 2081 { 2082 struct pcic_handle *ph = (struct pcic_handle *)pch; 2083 int reg; 2084 2085 if (win >= PCIC_IO_WINS || win < 0) { 2086 panic("pccbb_pcmcia_io_unmap: window out of range"); 2087 } 2088 2089 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2090 switch (win) { 2091 case 0: 2092 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2093 break; 2094 case 1: 2095 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2096 break; 2097 } 2098 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2099 2100 ph->ioalloc &= ~(1 << win); 2101 } 2102 2103 /* 2104 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2105 * 2106 * This function enables the card. All information is stored in 2107 * the first argument, pcmcia_chipset_handle_t. 2108 */ 2109 static void 2110 pccbb_pcmcia_wait_ready(ph) 2111 struct pcic_handle *ph; 2112 { 2113 int i; 2114 2115 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2116 Pcic_read(ph, PCIC_IF_STATUS))); 2117 2118 for (i = 0; i < 10000; i++) { 2119 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2120 return; 2121 } 2122 delay(500); 2123 #ifdef CBB_DEBUG 2124 if ((i > 5000) && (i % 100 == 99)) 2125 printf("."); 2126 #endif 2127 } 2128 2129 #ifdef DIAGNOSTIC 2130 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2131 Pcic_read(ph, PCIC_IF_STATUS)); 2132 #endif 2133 } 2134 2135 /* 2136 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2137 * 2138 * This function enables the card. All information is stored in 2139 * the first argument, pcmcia_chipset_handle_t. 2140 */ 2141 STATIC void 2142 pccbb_pcmcia_socket_enable(pch) 2143 pcmcia_chipset_handle_t pch; 2144 { 2145 struct pcic_handle *ph = (struct pcic_handle *)pch; 2146 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2147 int cardtype, win; 2148 u_int8_t power, intr; 2149 pcireg_t spsr; 2150 int voltage; 2151 2152 /* this bit is mostly stolen from pcic_attach_card */ 2153 2154 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2155 2156 /* get card Vcc info */ 2157 2158 spsr = 2159 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2160 CB_SOCKET_STAT); 2161 if (spsr & CB_SOCKET_STAT_5VCARD) { 2162 DPRINTF(("5V card\n")); 2163 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2164 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2165 DPRINTF(("3V card\n")); 2166 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2167 } else { 2168 printf("?V card, 0x%x\n", spsr); /* XXX */ 2169 return; 2170 } 2171 2172 /* assert reset bit */ 2173 intr = Pcic_read(ph, PCIC_INTR); 2174 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2175 Pcic_write(ph, PCIC_INTR, intr); 2176 2177 /* disable socket i/o: negate output enable bit */ 2178 2179 power = Pcic_read(ph, PCIC_PWRCTL); 2180 power &= ~PCIC_PWRCTL_OE; 2181 Pcic_write(ph, PCIC_PWRCTL, power); 2182 2183 /* power down the socket to reset it, clear the card reset pin */ 2184 2185 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2186 2187 /* 2188 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2189 * we are changing Vcc (Toff). 2190 */ 2191 /* delay(300*1000); too much */ 2192 2193 /* power up the socket */ 2194 pccbb_power(sc, voltage); 2195 2196 /* 2197 * wait 100ms until power raise (Tpr) and 20ms to become 2198 * stable (Tsu(Vcc)). 2199 * 2200 * some machines require some more time to be settled 2201 * (another 200ms is added here). 2202 */ 2203 /* delay((100 + 20 + 200)*1000); too much */ 2204 2205 power = Pcic_read(ph, PCIC_PWRCTL); 2206 power |= PCIC_PWRCTL_OE; 2207 Pcic_write(ph, PCIC_PWRCTL, power); 2208 2209 /* 2210 * hold RESET at least 10us. 2211 */ 2212 delay(10); 2213 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2214 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2215 2216 /* clear the reset flag */ 2217 2218 intr |= PCIC_INTR_RESET; 2219 Pcic_write(ph, PCIC_INTR, intr); 2220 2221 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2222 2223 delay(20000); 2224 2225 /* wait for the chip to finish initializing */ 2226 2227 pccbb_pcmcia_wait_ready(ph); 2228 2229 /* zero out the address windows */ 2230 2231 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2232 2233 /* set the card type */ 2234 2235 cardtype = pcmcia_card_gettype(ph->pcmcia); 2236 2237 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2238 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2239 Pcic_write(ph, PCIC_INTR, intr); 2240 2241 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2242 ph->ph_parent->dv_xname, ph->sock, 2243 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2244 2245 /* reinstall all the memory and io mappings */ 2246 2247 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2248 if (ph->memalloc & (1 << win)) { 2249 pccbb_pcmcia_do_mem_map(ph, win); 2250 } 2251 } 2252 2253 for (win = 0; win < PCIC_IO_WINS; ++win) { 2254 if (ph->ioalloc & (1 << win)) { 2255 pccbb_pcmcia_do_io_map(ph, win); 2256 } 2257 } 2258 } 2259 2260 /* 2261 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2262 * 2263 * This function disables the card. All information is stored in 2264 * the first argument, pcmcia_chipset_handle_t. 2265 */ 2266 STATIC void 2267 pccbb_pcmcia_socket_disable(pch) 2268 pcmcia_chipset_handle_t pch; 2269 { 2270 struct pcic_handle *ph = (struct pcic_handle *)pch; 2271 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2272 u_int8_t power, intr; 2273 2274 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2275 2276 /* reset signal asserting... */ 2277 2278 intr = Pcic_read(ph, PCIC_INTR); 2279 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2280 Pcic_write(ph, PCIC_INTR, intr); 2281 delay(2 * 1000); 2282 2283 /* power down the socket */ 2284 power = Pcic_read(ph, PCIC_PWRCTL); 2285 power &= ~PCIC_PWRCTL_OE; 2286 Pcic_write(ph, PCIC_PWRCTL, power); 2287 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2288 /* 2289 * wait 300ms until power fails (Tpf). 2290 */ 2291 delay(300 * 1000); 2292 } 2293 2294 /* 2295 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2296 * 2297 * This function detects whether a card is in the slot or not. 2298 * If a card is inserted, return 1. Otherwise, return 0. 2299 */ 2300 STATIC int 2301 pccbb_pcmcia_card_detect(pch) 2302 pcmcia_chipset_handle_t pch; 2303 { 2304 struct pcic_handle *ph = (struct pcic_handle *)pch; 2305 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2306 2307 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2308 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2309 } 2310 2311 #if 0 2312 STATIC int 2313 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2314 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2315 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2316 #endif 2317 /* 2318 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2319 * bus_size_t size, 2320 * struct pcmcia_mem_handle *pcmhp) 2321 * 2322 * This function only allocates memory region for pccard. This 2323 * function never maps the allocated region to pccard memory area. 2324 * 2325 * XXX: Why the argument of start address is not in? 2326 */ 2327 STATIC int 2328 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2329 pcmcia_chipset_handle_t pch; 2330 bus_size_t size; 2331 struct pcmcia_mem_handle *pcmhp; 2332 { 2333 struct pcic_handle *ph = (struct pcic_handle *)pch; 2334 bus_space_handle_t memh; 2335 bus_addr_t addr; 2336 bus_size_t sizepg; 2337 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2338 #if rbus 2339 rbus_tag_t rb; 2340 #endif 2341 2342 /* out of sc->memh, allocate as many pages as necessary */ 2343 2344 /* convert size to PCIC pages */ 2345 /* 2346 * This is not enough; when the requested region is on the page 2347 * boundaries, this may calculate wrong result. 2348 */ 2349 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2350 #if 0 2351 if (sizepg > PCIC_MAX_MEM_PAGES) { 2352 return 1; 2353 } 2354 #endif 2355 2356 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2357 return 1; 2358 } 2359 2360 addr = 0; /* XXX gcc -Wuninitialized */ 2361 2362 #if rbus 2363 rb = sc->sc_rbus_memt; 2364 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2365 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2366 &addr, &memh)) { 2367 return 1; 2368 } 2369 #else 2370 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2371 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2372 0, /* boundary */ 2373 0, /* flags */ 2374 &addr, &memh)) { 2375 return 1; 2376 } 2377 #endif 2378 2379 DPRINTF( 2380 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2381 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2382 2383 pcmhp->memt = sc->sc_memt; 2384 pcmhp->memh = memh; 2385 pcmhp->addr = addr; 2386 pcmhp->size = size; 2387 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2388 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2389 pcmhp->mhandle = 0; 2390 /* No offset??? Funny. */ 2391 2392 return 0; 2393 } 2394 2395 /* 2396 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2397 * struct pcmcia_mem_handle *pcmhp) 2398 * 2399 * This function release the memory space allocated by the function 2400 * pccbb_pcmcia_mem_alloc(). 2401 */ 2402 STATIC void 2403 pccbb_pcmcia_mem_free(pch, pcmhp) 2404 pcmcia_chipset_handle_t pch; 2405 struct pcmcia_mem_handle *pcmhp; 2406 { 2407 #if rbus 2408 struct pcic_handle *ph = (struct pcic_handle *)pch; 2409 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2410 2411 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2412 #else 2413 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2414 #endif 2415 } 2416 2417 /* 2418 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2419 * 2420 * This function release the memory space allocated by the function 2421 * pccbb_pcmcia_mem_alloc(). 2422 */ 2423 STATIC void 2424 pccbb_pcmcia_do_mem_map(ph, win) 2425 struct pcic_handle *ph; 2426 int win; 2427 { 2428 int regbase_win; 2429 bus_addr_t phys_addr; 2430 bus_addr_t phys_end; 2431 2432 #define PCIC_SMM_START_LOW 0 2433 #define PCIC_SMM_START_HIGH 1 2434 #define PCIC_SMM_STOP_LOW 2 2435 #define PCIC_SMM_STOP_HIGH 3 2436 #define PCIC_CMA_LOW 4 2437 #define PCIC_CMA_HIGH 5 2438 2439 u_int8_t start_low, start_high = 0; 2440 u_int8_t stop_low, stop_high; 2441 u_int8_t off_low, off_high; 2442 u_int8_t mem_window; 2443 int reg; 2444 2445 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2446 int mem8 = 2447 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2448 || (kind == PCMCIA_MEM_ATTR); 2449 2450 regbase_win = 0x10 + win * 0x08; 2451 2452 phys_addr = ph->mem[win].addr; 2453 phys_end = phys_addr + ph->mem[win].size; 2454 2455 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2456 phys_addr, phys_end, ph->mem[win].offset)); 2457 2458 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2459 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2460 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2461 2462 /* bit 19:12 */ 2463 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2464 /* bit 23:20 and bit 7 on */ 2465 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2466 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2467 /* bit 31:24, for 32-bit address */ 2468 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2469 2470 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2471 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2472 2473 if (((struct pccbb_softc *)ph-> 2474 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2475 Pcic_write(ph, 0x40 + win, mem_window); 2476 } 2477 2478 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2479 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2480 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2481 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2482 2483 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2484 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2485 2486 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2487 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2488 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2489 | ((kind == PCMCIA_MEM_ATTR) ? 2490 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2491 2492 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2493 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2494 2495 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2496 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2497 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2498 2499 #if defined CBB_DEBUG 2500 { 2501 int r1, r2, r3, r4, r5, r6, r7 = 0; 2502 2503 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2504 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2505 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2506 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2507 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2508 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2509 if (((struct pccbb_softc *)(ph-> 2510 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2511 r7 = Pcic_read(ph, 0x40 + win); 2512 } 2513 2514 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2515 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2516 if (((struct pccbb_softc *)(ph-> 2517 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2518 DPRINTF((" %02x", r7)); 2519 } 2520 DPRINTF(("\n")); 2521 } 2522 #endif 2523 } 2524 2525 /* 2526 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2527 * bus_addr_t card_addr, bus_size_t size, 2528 * struct pcmcia_mem_handle *pcmhp, 2529 * bus_addr_t *offsetp, int *windowp) 2530 * 2531 * This function maps memory space allocated by the function 2532 * pccbb_pcmcia_mem_alloc(). 2533 */ 2534 STATIC int 2535 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2536 pcmcia_chipset_handle_t pch; 2537 int kind; 2538 bus_addr_t card_addr; 2539 bus_size_t size; 2540 struct pcmcia_mem_handle *pcmhp; 2541 bus_addr_t *offsetp; 2542 int *windowp; 2543 { 2544 struct pcic_handle *ph = (struct pcic_handle *)pch; 2545 bus_addr_t busaddr; 2546 long card_offset; 2547 int win; 2548 2549 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2550 if ((ph->memalloc & (1 << win)) == 0) { 2551 ph->memalloc |= (1 << win); 2552 break; 2553 } 2554 } 2555 2556 if (win == PCIC_MEM_WINS) { 2557 return 1; 2558 } 2559 2560 *windowp = win; 2561 2562 /* XXX this is pretty gross */ 2563 2564 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2565 panic("pccbb_pcmcia_mem_map memt is bogus"); 2566 } 2567 2568 busaddr = pcmhp->addr; 2569 2570 /* 2571 * compute the address offset to the pcmcia address space for the 2572 * pcic. this is intentionally signed. The masks and shifts below 2573 * will cause TRT to happen in the pcic registers. Deal with making 2574 * sure the address is aligned, and return the alignment offset. 2575 */ 2576 2577 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2578 card_addr -= *offsetp; 2579 2580 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2581 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2582 (u_long) card_addr)); 2583 2584 /* 2585 * include the offset in the size, and decrement size by one, since 2586 * the hw wants start/stop 2587 */ 2588 size += *offsetp - 1; 2589 2590 card_offset = (((long)card_addr) - ((long)busaddr)); 2591 2592 ph->mem[win].addr = busaddr; 2593 ph->mem[win].size = size; 2594 ph->mem[win].offset = card_offset; 2595 ph->mem[win].kind = kind; 2596 2597 pccbb_pcmcia_do_mem_map(ph, win); 2598 2599 return 0; 2600 } 2601 2602 /* 2603 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2604 * int window) 2605 * 2606 * This function unmaps memory space which mapped by the function 2607 * pccbb_pcmcia_mem_map(). 2608 */ 2609 STATIC void 2610 pccbb_pcmcia_mem_unmap(pch, window) 2611 pcmcia_chipset_handle_t pch; 2612 int window; 2613 { 2614 struct pcic_handle *ph = (struct pcic_handle *)pch; 2615 int reg; 2616 2617 if (window >= PCIC_MEM_WINS) { 2618 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2619 } 2620 2621 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2622 reg &= ~(1 << window); 2623 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2624 2625 ph->memalloc &= ~(1 << window); 2626 } 2627 2628 #if defined PCCBB_PCMCIA_POLL 2629 struct pccbb_poll_str { 2630 void *arg; 2631 int (*func) __P((void *)); 2632 int level; 2633 struct pcic_handle *ph; 2634 int count; 2635 int num; 2636 struct callout poll_ch; 2637 }; 2638 2639 static struct pccbb_poll_str pccbb_poll[10]; 2640 static int pccbb_poll_n = 0; 2641 2642 static void pccbb_pcmcia_poll __P((void *arg)); 2643 2644 static void 2645 pccbb_pcmcia_poll(arg) 2646 void *arg; 2647 { 2648 struct pccbb_poll_str *poll = arg; 2649 struct pcic_handle *ph = poll->ph; 2650 struct pccbb_softc *sc = ph->sc; 2651 int s; 2652 u_int32_t spsr; /* socket present-state reg */ 2653 2654 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2655 switch (poll->level) { 2656 case IPL_NET: 2657 s = splnet(); 2658 break; 2659 case IPL_BIO: 2660 s = splbio(); 2661 break; 2662 case IPL_TTY: /* fallthrough */ 2663 default: 2664 s = spltty(); 2665 break; 2666 } 2667 2668 spsr = 2669 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2670 CB_SOCKET_STAT); 2671 2672 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2673 if (!(spsr & 0x40)) /* CINT low */ 2674 #else 2675 if (1) 2676 #endif 2677 { 2678 if ((*poll->func) (poll->arg) > 0) { 2679 ++poll->count; 2680 // printf("intr: reported from poller, 0x%x\n", spsr); 2681 #if defined LEVEL2 2682 } else { 2683 printf("intr: miss! 0x%x\n", spsr); 2684 #endif 2685 } 2686 } 2687 splx(s); 2688 } 2689 #endif /* defined CB_PCMCIA_POLL */ 2690 2691 /* 2692 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2693 * struct pcmcia_function *pf, 2694 * int ipl, 2695 * int (*func)(void *), 2696 * void *arg); 2697 * 2698 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2699 */ 2700 STATIC void * 2701 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2702 pcmcia_chipset_handle_t pch; 2703 struct pcmcia_function *pf; 2704 int ipl; 2705 int (*func) __P((void *)); 2706 void *arg; 2707 { 2708 struct pcic_handle *ph = (struct pcic_handle *)pch; 2709 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2710 2711 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2712 /* what should I do? */ 2713 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2714 DPRINTF( 2715 ("%s does not provide edge nor pulse interrupt\n", 2716 sc->sc_dev.dv_xname)); 2717 return NULL; 2718 } 2719 /* 2720 * XXX Noooooo! The interrupt flag must set properly!! 2721 * dumb pcmcia driver!! 2722 */ 2723 } 2724 2725 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2726 } 2727 2728 /* 2729 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2730 * void *ih) 2731 * 2732 * This function disables PC-Card interrupt. 2733 */ 2734 STATIC void 2735 pccbb_pcmcia_intr_disestablish(pch, ih) 2736 pcmcia_chipset_handle_t pch; 2737 void *ih; 2738 { 2739 struct pcic_handle *ph = (struct pcic_handle *)pch; 2740 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2741 2742 pccbb_intr_disestablish(sc, ih); 2743 } 2744 2745 #if rbus 2746 /* 2747 * static int 2748 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2749 * bus_addr_t addr, bus_size_t size, 2750 * bus_addr_t mask, bus_size_t align, 2751 * int flags, bus_addr_t *addrp; 2752 * bus_space_handle_t *bshp) 2753 * 2754 * This function allocates a portion of memory or io space for 2755 * clients. This function is called from CardBus card drivers. 2756 */ 2757 static int 2758 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2759 cardbus_chipset_tag_t ct; 2760 rbus_tag_t rb; 2761 bus_addr_t addr; 2762 bus_size_t size; 2763 bus_addr_t mask; 2764 bus_size_t align; 2765 int flags; 2766 bus_addr_t *addrp; 2767 bus_space_handle_t *bshp; 2768 { 2769 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2770 2771 DPRINTF( 2772 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2773 addr, size, mask, align)); 2774 2775 if (align == 0) { 2776 align = size; 2777 } 2778 2779 if (rb->rb_bt == sc->sc_memt) { 2780 if (align < 16) { 2781 return 1; 2782 } 2783 } else if (rb->rb_bt == sc->sc_iot) { 2784 if (align < 4) { 2785 return 1; 2786 } 2787 /* XXX: hack for avoiding ISA image */ 2788 if (mask < 0x0100) { 2789 mask = 0x3ff; 2790 addr = 0x300; 2791 } 2792 2793 } else { 2794 DPRINTF( 2795 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2796 rb->rb_bt)); 2797 return 1; 2798 /* XXX: panic here? */ 2799 } 2800 2801 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2802 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2803 return 1; 2804 } 2805 2806 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2807 2808 return 0; 2809 } 2810 2811 /* 2812 * static int 2813 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2814 * bus_space_handle_t *bshp, bus_size_t size); 2815 * 2816 * This function is called from CardBus card drivers. 2817 */ 2818 static int 2819 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2820 cardbus_chipset_tag_t ct; 2821 rbus_tag_t rb; 2822 bus_space_handle_t bsh; 2823 bus_size_t size; 2824 { 2825 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2826 bus_space_tag_t bt = rb->rb_bt; 2827 2828 pccbb_close_win(sc, bt, bsh, size); 2829 2830 if (bt == sc->sc_memt) { 2831 } else if (bt == sc->sc_iot) { 2832 } else { 2833 return 1; 2834 /* XXX: panic here? */ 2835 } 2836 2837 return rbus_space_free(rb, bsh, size, NULL); 2838 } 2839 #endif /* rbus */ 2840 2841 #if rbus 2842 2843 static int 2844 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2845 struct pccbb_softc *sc; 2846 bus_space_tag_t bst; 2847 bus_addr_t addr; 2848 bus_size_t size; 2849 bus_space_handle_t bsh; 2850 int flags; 2851 { 2852 struct pccbb_win_chain_head *head; 2853 bus_addr_t align; 2854 2855 head = &sc->sc_iowindow; 2856 align = 0x04; 2857 if (sc->sc_memt == bst) { 2858 head = &sc->sc_memwindow; 2859 align = 0x1000; 2860 DPRINTF(("using memory window, %x %x %x\n\n", 2861 sc->sc_iot, sc->sc_memt, bst)); 2862 } 2863 2864 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2865 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2866 sc->sc_dev.dv_xname, 2867 (head == &sc->sc_memwindow) ? "mem" : "io"); 2868 } 2869 pccbb_winset(align, sc, bst); 2870 2871 return 0; 2872 } 2873 2874 static int 2875 pccbb_close_win(sc, bst, bsh, size) 2876 struct pccbb_softc *sc; 2877 bus_space_tag_t bst; 2878 bus_space_handle_t bsh; 2879 bus_size_t size; 2880 { 2881 struct pccbb_win_chain_head *head; 2882 bus_addr_t align; 2883 2884 head = &sc->sc_iowindow; 2885 align = 0x04; 2886 if (sc->sc_memt == bst) { 2887 head = &sc->sc_memwindow; 2888 align = 0x1000; 2889 } 2890 2891 if (pccbb_winlist_delete(head, bsh, size)) { 2892 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2893 sc->sc_dev.dv_xname, 2894 (head == &sc->sc_memwindow) ? "mem" : "io"); 2895 } 2896 pccbb_winset(align, sc, bst); 2897 2898 return 0; 2899 } 2900 2901 static int 2902 pccbb_winlist_insert(head, start, size, bsh, flags) 2903 struct pccbb_win_chain_head *head; 2904 bus_addr_t start; 2905 bus_size_t size; 2906 bus_space_handle_t bsh; 2907 int flags; 2908 { 2909 struct pccbb_win_chain *chainp, *elem; 2910 2911 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2912 M_NOWAIT)) == NULL) 2913 return (1); /* fail */ 2914 2915 elem->wc_start = start; 2916 elem->wc_end = start + (size - 1); 2917 elem->wc_handle = bsh; 2918 elem->wc_flags = flags; 2919 2920 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2921 chainp = TAILQ_NEXT(chainp, wc_list)) { 2922 if (chainp->wc_end < start) 2923 continue; 2924 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2925 return (0); 2926 } 2927 2928 TAILQ_INSERT_TAIL(head, elem, wc_list); 2929 return (0); 2930 } 2931 2932 static int 2933 pccbb_winlist_delete(head, bsh, size) 2934 struct pccbb_win_chain_head *head; 2935 bus_space_handle_t bsh; 2936 bus_size_t size; 2937 { 2938 struct pccbb_win_chain *chainp; 2939 2940 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2941 chainp = TAILQ_NEXT(chainp, wc_list)) { 2942 if (chainp->wc_handle != bsh) 2943 continue; 2944 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2945 printf("pccbb_winlist_delete: window 0x%lx size " 2946 "inconsistent: 0x%lx, 0x%lx\n", 2947 chainp->wc_start, 2948 chainp->wc_end - chainp->wc_start, 2949 size - 1); 2950 return 1; 2951 } 2952 2953 TAILQ_REMOVE(head, chainp, wc_list); 2954 free(chainp, M_DEVBUF); 2955 2956 return 0; 2957 } 2958 2959 return 1; /* fail: no candidate to remove */ 2960 } 2961 2962 static void 2963 pccbb_winset(align, sc, bst) 2964 bus_addr_t align; 2965 struct pccbb_softc *sc; 2966 bus_space_tag_t bst; 2967 { 2968 pci_chipset_tag_t pc; 2969 pcitag_t tag; 2970 bus_addr_t mask = ~(align - 1); 2971 struct { 2972 cardbusreg_t win_start; 2973 cardbusreg_t win_limit; 2974 int win_flags; 2975 } win[2]; 2976 struct pccbb_win_chain *chainp; 2977 int offs; 2978 2979 win[0].win_start = 0xffffffff; 2980 win[0].win_limit = 0; 2981 win[1].win_start = 0xffffffff; 2982 win[1].win_limit = 0; 2983 2984 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2985 offs = 0x2c; 2986 if (sc->sc_memt == bst) { 2987 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2988 offs = 0x1c; 2989 } 2990 2991 if (chainp != NULL) { 2992 win[0].win_start = chainp->wc_start & mask; 2993 win[0].win_limit = chainp->wc_end & mask; 2994 win[0].win_flags = chainp->wc_flags; 2995 chainp = TAILQ_NEXT(chainp, wc_list); 2996 } 2997 2998 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2999 if (win[1].win_start == 0xffffffff) { 3000 /* window 1 is not used */ 3001 if ((win[0].win_flags == chainp->wc_flags) && 3002 (win[0].win_limit + align >= 3003 (chainp->wc_start & mask))) { 3004 /* concatenate */ 3005 win[0].win_limit = chainp->wc_end & mask; 3006 } else { 3007 /* make new window */ 3008 win[1].win_start = chainp->wc_start & mask; 3009 win[1].win_limit = chainp->wc_end & mask; 3010 win[1].win_flags = chainp->wc_flags; 3011 } 3012 continue; 3013 } 3014 3015 /* Both windows are engaged. */ 3016 if (win[0].win_flags == win[1].win_flags) { 3017 /* same flags */ 3018 if (win[0].win_flags == chainp->wc_flags) { 3019 if (win[1].win_start - (win[0].win_limit + 3020 align) < 3021 (chainp->wc_start & mask) - 3022 ((chainp->wc_end & mask) + align)) { 3023 /* 3024 * merge window 0 and 1, and set win1 3025 * to chainp 3026 */ 3027 win[0].win_limit = win[1].win_limit; 3028 win[1].win_start = 3029 chainp->wc_start & mask; 3030 win[1].win_limit = 3031 chainp->wc_end & mask; 3032 } else { 3033 win[1].win_limit = 3034 chainp->wc_end & mask; 3035 } 3036 } else { 3037 /* different flags */ 3038 3039 /* concatenate win0 and win1 */ 3040 win[0].win_limit = win[1].win_limit; 3041 /* allocate win[1] to new space */ 3042 win[1].win_start = chainp->wc_start & mask; 3043 win[1].win_limit = chainp->wc_end & mask; 3044 win[1].win_flags = chainp->wc_flags; 3045 } 3046 } else { 3047 /* the flags of win[0] and win[1] is different */ 3048 if (win[0].win_flags == chainp->wc_flags) { 3049 win[0].win_limit = chainp->wc_end & mask; 3050 /* 3051 * XXX this creates overlapping windows, so 3052 * what should the poor bridge do if one is 3053 * cachable, and the other is not? 3054 */ 3055 printf("%s: overlapping windows\n", 3056 sc->sc_dev.dv_xname); 3057 } else { 3058 win[1].win_limit = chainp->wc_end & mask; 3059 } 3060 } 3061 } 3062 3063 pc = sc->sc_pc; 3064 tag = sc->sc_tag; 3065 pci_conf_write(pc, tag, offs, win[0].win_start); 3066 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3067 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3068 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3069 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3070 pci_conf_read(pc, tag, offs), 3071 pci_conf_read(pc, tag, offs + 4) + align, 3072 pci_conf_read(pc, tag, offs + 8), 3073 pci_conf_read(pc, tag, offs + 12) + align)); 3074 3075 if (bst == sc->sc_memt) { 3076 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3077 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3078 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3079 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3080 } 3081 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3082 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3083 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3084 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3085 } 3086 } 3087 } 3088 3089 #endif /* rbus */ 3090 3091 static void 3092 pccbb_powerhook(why, arg) 3093 int why; 3094 void *arg; 3095 { 3096 struct pccbb_softc *sc = arg; 3097 u_int32_t reg; 3098 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3099 bus_space_handle_t base_memh = sc->sc_base_memh; 3100 3101 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3102 3103 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3104 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3105 if (sc->sc_pil_intr_enable) { 3106 (void)pccbbintr_function(sc); 3107 } 3108 sc->sc_pil_intr_enable = 0; 3109 3110 /* ToDo: deactivate or suspend child devices */ 3111 3112 } 3113 3114 if (why == PWR_RESUME) { 3115 /* CSC Interrupt: Card detect interrupt on */ 3116 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3117 /* Card detect intr is turned on. */ 3118 reg |= CB_SOCKET_MASK_CD; 3119 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3120 /* reset interrupt */ 3121 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3122 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3123 3124 /* 3125 * check for card insertion or removal during suspend period. 3126 * XXX: the code can't cope with card swap (remove then 3127 * insert). how can we detect such situation? 3128 */ 3129 (void)pccbbintr(sc); 3130 3131 sc->sc_pil_intr_enable = 1; 3132 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3133 3134 /* ToDo: activate or wakeup child devices */ 3135 } 3136 } 3137
Indexes created Fri Sep 26 20:09:58 GMT 2025