pccbb.c revision 1.41
1 /* $NetBSD: pccbb.c,v 1.41 2000/06/08 10:28:28 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 #ifdef __BROKEN_INDIRECT_CONFIG 93 int pcicbbmatch __P((struct device *, void *, void *)); 94 #else 95 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 96 #endif 97 void pccbbattach __P((struct device *, struct device *, void *)); 98 int pccbbintr __P((void *)); 99 static void pci113x_insert __P((void *)); 100 static int pccbbintr_function __P((struct pccbb_softc *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 STATIC int cb_reset __P((struct pccbb_softc *)); 110 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 111 STATIC int cbbprint __P((void *, const char *)); 112 113 static int cb_chipset __P((u_int32_t, int *)); 114 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 115 struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 129 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 130 u_int32_t)); 131 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 132 #endif /* !rbus */ 133 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 136 137 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 138 int level, int (*ih) (void *), void *sc)); 139 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 140 141 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 142 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 143 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 144 int)); 145 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 146 cardbusreg_t)); 147 static void pccbb_chipinit __P((struct pccbb_softc *)); 148 149 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 150 struct pcmcia_mem_handle *)); 151 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 152 struct pcmcia_mem_handle *)); 153 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 155 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 156 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 157 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 158 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 159 struct pcmcia_io_handle *)); 160 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 161 bus_size_t, struct pcmcia_io_handle *, int *)); 162 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 163 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 164 struct pcmcia_function *, int, int (*)(void *), void *)); 165 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 166 void *)); 167 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 168 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 169 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 170 171 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 172 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 173 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 174 static void pccbb_powerhook __P((int, void *)); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 182 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 191 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t)); 193 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int)); 195 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t)); 197 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t)); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback __P((struct device *)); 205 206 #if defined SHOW_REGS 207 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 208 bus_space_tag_t memt, bus_space_handle_t memh)); 209 #endif 210 211 struct cfattach cbb_pci_ca = { 212 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 213 }; 214 215 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 216 pccbb_pcmcia_mem_alloc, 217 pccbb_pcmcia_mem_free, 218 pccbb_pcmcia_mem_map, 219 pccbb_pcmcia_mem_unmap, 220 pccbb_pcmcia_io_alloc, 221 pccbb_pcmcia_io_free, 222 pccbb_pcmcia_io_map, 223 pccbb_pcmcia_io_unmap, 224 pccbb_pcmcia_intr_establish, 225 pccbb_pcmcia_intr_disestablish, 226 pccbb_pcmcia_socket_enable, 227 pccbb_pcmcia_socket_disable, 228 pccbb_pcmcia_card_detect 229 }; 230 231 #if rbus 232 static struct cardbus_functions pccbb_funcs = { 233 pccbb_rbus_cb_space_alloc, 234 pccbb_rbus_cb_space_free, 235 pccbb_cb_intr_establish, 236 pccbb_cb_intr_disestablish, 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_make_tag, 240 pccbb_free_tag, 241 pccbb_conf_read, 242 pccbb_conf_write, 243 }; 244 #else 245 static struct cardbus_functions pccbb_funcs = { 246 pccbb_ctrl, 247 pccbb_power, 248 pccbb_mem_open, 249 pccbb_mem_close, 250 pccbb_io_open, 251 pccbb_io_close, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_make_tag, 255 pccbb_conf_read, 256 pccbb_conf_write, 257 }; 258 #endif 259 260 int 261 pcicbbmatch(parent, match, aux) 262 struct device *parent; 263 #ifdef __BROKEN_INDIRECT_CONFIG 264 void *match; 265 #else 266 struct cfdata *match; 267 #endif 268 void *aux; 269 { 270 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 271 272 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 273 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 274 PCI_INTERFACE(pa->pa_class) == 0) { 275 return 1; 276 } 277 278 return 0; 279 } 280 281 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 282 | ((prod) << PCI_PRODUCT_SHIFT)) 283 284 struct yenta_chipinfo { 285 pcireg_t yc_id; /* vendor tag | product tag */ 286 int yc_chiptype; 287 int yc_flags; 288 } yc_chipsets[] = { 289 /* Texas Instruments chips */ 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 319 PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 327 PCCBB_PCMCIA_MEM_32}, 328 329 /* Toshiba products */ 330 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 331 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 333 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 335 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 337 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 338 339 /* Cirrus Logic products */ 340 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 341 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 343 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 344 345 /* sentinel, or Generic chip */ 346 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 347 }; 348 349 static int 350 cb_chipset(pci_id, flagp) 351 u_int32_t pci_id; 352 int *flagp; 353 { 354 struct yenta_chipinfo *yc; 355 356 /* Loop over except the last default entry. */ 357 for (yc = yc_chipsets; yc < yc_chipsets + 358 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 359 if (pci_id == yc->yc_id) 360 break; 361 362 if (flagp != NULL) 363 *flagp = yc->yc_flags; 364 365 return (yc->yc_chiptype); 366 } 367 368 static void 369 pccbb_shutdown(void *arg) 370 { 371 struct pccbb_softc *sc = arg; 372 pcireg_t command; 373 374 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 375 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 376 0); 377 378 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 379 380 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 381 PCI_COMMAND_MASTER_ENABLE); 382 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 383 384 } 385 386 void 387 pccbbattach(parent, self, aux) 388 struct device *parent; 389 struct device *self; 390 void *aux; 391 { 392 struct pccbb_softc *sc = (void *)self; 393 struct pci_attach_args *pa = aux; 394 pci_chipset_tag_t pc = pa->pa_pc; 395 pcireg_t sock_base, busreg; 396 bus_addr_t sockbase; 397 char devinfo[256]; 398 int flags; 399 400 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 401 402 pci_devinfo(pa->pa_id, 0, 0, devinfo); 403 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 404 #ifdef CBB_DEBUG 405 printf(" (chipflags %x)", flags); 406 #endif 407 printf("\n"); 408 409 TAILQ_INIT(&sc->sc_memwindow); 410 TAILQ_INIT(&sc->sc_iowindow); 411 412 #if rbus 413 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 414 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 415 #endif /* rbus */ 416 417 sc->sc_base_memh = 0; 418 419 /* 420 * MAP socket registers and ExCA registers on memory-space 421 * When no valid address is set on socket base registers (on pci 422 * config space), get it not polite way. 423 */ 424 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 425 426 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 427 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 428 /* The address must be valid. */ 429 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 430 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 431 printf("%s: can't map socket base address 0x%x\n", 432 sc->sc_dev.dv_xname, sock_base); 433 /* 434 * I think it's funny: socket base registers must be 435 * mapped on memory space, but ... 436 */ 437 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 438 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 439 NULL)) { 440 printf("%s: can't map socket base address" 441 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 442 sockbase); 443 /* give up... allocate reg space via rbus. */ 444 sc->sc_base_memh = 0; 445 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 446 } 447 } else { 448 DPRINTF(("%s: socket base address 0x%lx\n", 449 sc->sc_dev.dv_xname, sockbase)); 450 } 451 } 452 453 sc->sc_mem_start = 0; /* XXX */ 454 sc->sc_mem_end = 0xffffffff; /* XXX */ 455 456 /* 457 * When interrupt isn't routed correctly, give up probing cbb and do 458 * not kill pcic-compatible port. 459 */ 460 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 461 printf("%s: NOT USED because of unconfigured interrupt\n", 462 sc->sc_dev.dv_xname); 463 return; 464 } 465 466 /* 467 * When bus number isn't set correctly, give up using 32-bit CardBus 468 * mode. 469 */ 470 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 471 #if notyet 472 if (((busreg >> 8) & 0xff) == 0) { 473 printf("%s: CardBus support disabled because of unconfigured bus number\n", 474 sc->sc_dev.dv_xname); 475 flags |= PCCBB_PCMCIA_16BITONLY; 476 } 477 #endif 478 479 /* pccbb_machdep.c end */ 480 481 #if defined CBB_DEBUG 482 { 483 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 484 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 485 intrname[pa->pa_intrpin], pa->pa_intrline); 486 } 487 #endif 488 489 /* setup softc */ 490 sc->sc_pc = pc; 491 sc->sc_iot = pa->pa_iot; 492 sc->sc_memt = pa->pa_memt; 493 sc->sc_dmat = pa->pa_dmat; 494 sc->sc_tag = pa->pa_tag; 495 sc->sc_function = pa->pa_function; 496 497 sc->sc_intrline = pa->pa_intrline; 498 sc->sc_intrtag = pa->pa_intrtag; 499 sc->sc_intrpin = pa->pa_intrpin; 500 501 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 502 503 shutdownhook_establish(pccbb_shutdown, sc); 504 505 config_defer(self, pccbb_pci_callback); 506 } 507 508 509 510 511 /* 512 * static void pccbb_pci_callback(struct device *self) 513 * 514 * The actual attach routine: get memory space for YENTA register 515 * space, setup YENTA register and route interrupt. 516 * 517 * This function should be deferred because this device may obtain 518 * memory space dynamically. This function must avoid obtaining 519 * memory area which has already kept for another device. Also, 520 * this function MUST be done before ISA attach process because this 521 * function kills pcic compatible port used by ISA pcic. 522 */ 523 static void 524 pccbb_pci_callback(self) 525 struct device *self; 526 { 527 struct pccbb_softc *sc = (void *)self; 528 pci_chipset_tag_t pc = sc->sc_pc; 529 bus_space_tag_t base_memt; 530 bus_space_handle_t base_memh; 531 u_int32_t maskreg; 532 pci_intr_handle_t ih; 533 const char *intrstr = NULL; 534 bus_addr_t sockbase; 535 struct cbslot_attach_args cba; 536 struct pcmciabus_attach_args paa; 537 struct cardslot_attach_args caa; 538 struct cardslot_softc *csc; 539 540 if (0 == sc->sc_base_memh) { 541 /* The socket registers aren't mapped correctly. */ 542 #if rbus 543 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 544 (sc->sc_chipset == CB_RX5C47X 545 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 546 0, &sockbase, &sc->sc_base_memh)) { 547 return; 548 } 549 sc->sc_base_memt = sc->sc_memt; 550 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 551 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 552 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 553 PCI_SOCKBASE))); 554 #else 555 sc->sc_base_memt = sc->sc_memt; 556 #if !defined CBB_PCI_BASE 557 #define CBB_PCI_BASE 0x20000000 558 #endif 559 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 560 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 561 /* cannot allocate memory space */ 562 return; 563 } 564 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 565 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 566 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 567 sc->sc_tag, PCI_SOCKBASE))); 568 #endif 569 } 570 571 /* bus bridge initialization */ 572 pccbb_chipinit(sc); 573 574 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 575 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 576 577 /* CSC Interrupt: Card detect interrupt on */ 578 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 579 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 580 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 581 /* reset interrupt */ 582 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 583 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 584 585 /* clear data structure for child device interrupt handlers */ 586 sc->sc_pil = NULL; 587 sc->sc_pil_intr_enable = 1; 588 589 /* Map and establish the interrupt. */ 590 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 591 sc->sc_intrline, &ih)) { 592 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 593 return; 594 } 595 intrstr = pci_intr_string(pc, ih); 596 597 /* 598 * XXX pccbbintr should be called under the priority lower 599 * than any other hard interrputs. 600 */ 601 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 602 603 if (sc->sc_ih == NULL) { 604 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 605 if (intrstr != NULL) { 606 printf(" at %s", intrstr); 607 } 608 printf("\n"); 609 return; 610 } 611 612 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 613 powerhook_establish(pccbb_powerhook, sc); 614 615 { 616 u_int32_t sockstat = 617 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 618 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 619 sc->sc_flags |= CBB_CARDEXIST; 620 } 621 } 622 623 /* 624 * attach cardbus 625 */ 626 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 627 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 628 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 629 630 /* initialize cbslot_attach */ 631 cba.cba_busname = "cardbus"; 632 cba.cba_iot = sc->sc_iot; 633 cba.cba_memt = sc->sc_memt; 634 cba.cba_dmat = sc->sc_dmat; 635 cba.cba_bus = (busreg >> 8) & 0x0ff; 636 cba.cba_cc = (void *)sc; 637 cba.cba_cf = &pccbb_funcs; 638 cba.cba_intrline = sc->sc_intrline; 639 640 #if rbus 641 cba.cba_rbus_iot = sc->sc_rbus_iot; 642 cba.cba_rbus_memt = sc->sc_rbus_memt; 643 #endif 644 645 cba.cba_cacheline = PCI_CACHELINE(bhlc); 646 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 647 648 printf("%s: cacheline 0x%x lattimer 0x%x\n", 649 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 650 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 651 busreg); 652 #if defined SHOW_REGS 653 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 654 sc->sc_base_memh); 655 #endif 656 } 657 658 pccbb_pcmcia_attach_setup(sc, &paa); 659 caa.caa_cb_attach = NULL; 660 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 661 caa.caa_cb_attach = &cba; 662 } 663 caa.caa_16_attach = &paa; 664 caa.caa_ph = &sc->sc_pcmcia_h; 665 666 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 667 DPRINTF(("pccbbattach: found cardslot\n")); 668 sc->sc_csc = csc; 669 } 670 671 return; 672 } 673 674 675 676 677 678 /* 679 * static void pccbb_chipinit(struct pccbb_softc *sc) 680 * 681 * This function initialize YENTA chip registers listed below: 682 * 1) PCI command reg, 683 * 2) PCI and CardBus latency timer, 684 * 3) disable legacy (PCIC-compatible) io, 685 * 4) route PCI interrupt, 686 * 5) close all memory and io windows. 687 */ 688 static void 689 pccbb_chipinit(sc) 690 struct pccbb_softc *sc; 691 { 692 pci_chipset_tag_t pc = sc->sc_pc; 693 pcitag_t tag = sc->sc_tag; 694 pcireg_t reg; 695 696 /* 697 * Set PCI command reg. 698 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 699 */ 700 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 701 /* I believe it is harmless. */ 702 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 703 PCI_COMMAND_MASTER_ENABLE); 704 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 705 706 /* 707 * Set CardBus latency timer. 708 */ 709 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 710 if (PCI_CB_LATENCY(reg) < 0x20) { 711 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 712 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 713 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 714 } 715 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 716 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 717 718 /* 719 * Set PCI latency timer. 720 */ 721 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 722 if (PCI_LATTIMER(reg) < 0x10) { 723 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 724 reg |= (0x10 << PCI_LATTIMER_SHIFT); 725 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 726 } 727 DPRINTF(("PCI latency timer 0x%x (%x)\n", 728 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 729 730 /* Disable legacy register mapping. */ 731 switch (sc->sc_chipset) { 732 case CB_RX5C46X: /* fallthrough */ 733 #if 0 734 case CB_RX5C47X: 735 #endif 736 /* 737 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 738 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 739 * CardBus bridges have special bits on Bridge control reg (addr 740 * 0x3e on PCI config space). 741 */ 742 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 743 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 744 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 745 break; 746 747 default: 748 /* XXX I don't know proper way to kill legacy I/O. */ 749 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 750 break; 751 } 752 753 /* Route functional interrupts to PCI. */ 754 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 755 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 756 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 757 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 758 759 switch (sc->sc_chipset) { 760 case CB_TI113X: 761 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 762 /* This bit is shared, but may read as 0 on some chips, so set 763 it explicitly on both functions. */ 764 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 765 /* CSC intr enable */ 766 reg |= PCI113X_CBCTRL_PCI_CSC; 767 /* functional intr prohibit */ 768 reg &= ~PCI113X_CBCTRL_PCI_INTR; 769 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 770 break; 771 772 case CB_TOPIC95B: 773 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 774 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 775 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 776 777 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 778 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 779 sc->sc_dev.dv_xname, reg)); 780 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 781 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 782 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 783 DPRINTF(("0x%x\n", reg)); 784 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 785 break; 786 } 787 788 /* Close all memory and I/O windows. */ 789 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 790 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 791 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 792 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 793 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 794 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 795 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 796 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 797 } 798 799 800 801 802 /* 803 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 804 * struct pcmciabus_attach_args *paa) 805 * 806 * This function attaches 16-bit PCcard bus. 807 */ 808 STATIC void 809 pccbb_pcmcia_attach_setup(sc, paa) 810 struct pccbb_softc *sc; 811 struct pcmciabus_attach_args *paa; 812 { 813 struct pcic_handle *ph = &sc->sc_pcmcia_h; 814 #if rbus 815 rbus_tag_t rb; 816 #endif 817 818 /* initialize pcmcia part in pccbb_softc */ 819 ph->ph_parent = (struct device *)sc; 820 ph->sock = sc->sc_function; 821 ph->flags = 0; 822 ph->shutdown = 0; 823 ph->ih_irq = sc->sc_intrline; 824 ph->ph_bus_t = sc->sc_base_memt; 825 ph->ph_bus_h = sc->sc_base_memh; 826 ph->ph_read = pccbb_pcmcia_read; 827 ph->ph_write = pccbb_pcmcia_write; 828 sc->sc_pct = &pccbb_pcmcia_funcs; 829 830 /* 831 * We need to do a few things here: 832 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 833 * setting the IRQ numbers to 0. 834 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 835 * routing of CSC interrupts (e.g. card removal) to PCI while in 836 * PCMCIA mode. We just leave this set all the time. 837 * 3) Enable card insertion/removal interrupts in case the chip also 838 * needs that while in PCMCIA mode. 839 * 4) Clear any pending CSC interrupt. 840 */ 841 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 842 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 843 Pcic_read(ph, PCIC_CSC); 844 845 /* initialize pcmcia bus attachment */ 846 paa->paa_busname = "pcmcia"; 847 paa->pct = sc->sc_pct; 848 paa->pch = ph; 849 paa->iobase = 0; /* I don't use them */ 850 paa->iosize = 0; 851 #if rbus 852 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 853 paa->iobase = rb->rb_start + rb->rb_offset; 854 paa->iosize = rb->rb_end - rb->rb_start; 855 #endif 856 857 return; 858 } 859 860 #if 0 861 STATIC void 862 pccbb_pcmcia_attach_card(ph) 863 struct pcic_handle *ph; 864 { 865 if (ph->flags & PCIC_FLAG_CARDP) { 866 panic("pccbb_pcmcia_attach_card: already attached"); 867 } 868 869 /* call the MI attach function */ 870 pcmcia_card_attach(ph->pcmcia); 871 872 ph->flags |= PCIC_FLAG_CARDP; 873 } 874 875 STATIC void 876 pccbb_pcmcia_detach_card(ph, flags) 877 struct pcic_handle *ph; 878 int flags; 879 { 880 if (!(ph->flags & PCIC_FLAG_CARDP)) { 881 panic("pccbb_pcmcia_detach_card: already detached"); 882 } 883 884 ph->flags &= ~PCIC_FLAG_CARDP; 885 886 /* call the MI detach function */ 887 pcmcia_card_detach(ph->pcmcia, flags); 888 } 889 #endif 890 891 /* 892 * int pccbbintr(arg) 893 * void *arg; 894 * This routine handles the interrupt from Yenta PCI-CardBus bridge 895 * itself. 896 */ 897 int 898 pccbbintr(arg) 899 void *arg; 900 { 901 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 902 u_int32_t sockevent, sockstate; 903 bus_space_tag_t memt = sc->sc_base_memt; 904 bus_space_handle_t memh = sc->sc_base_memh; 905 struct pcic_handle *ph = &sc->sc_pcmcia_h; 906 907 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 908 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 909 Pcic_read(ph, PCIC_CSC); 910 911 if (sockevent == 0) { 912 /* This intr is not for me: it may be for my child devices. */ 913 if (sc->sc_pil_intr_enable) { 914 return pccbbintr_function(sc); 915 } else { 916 return 0; 917 } 918 } 919 920 if (sockevent & CB_SOCKET_EVENT_CD) { 921 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 922 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 923 /* A card should be removed. */ 924 if (sc->sc_flags & CBB_CARDEXIST) { 925 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 926 sockevent)); 927 DPRINTF((" card removed, 0x%08x\n", sockstate)); 928 sc->sc_flags &= ~CBB_CARDEXIST; 929 if (sc->sc_csc->sc_status & 930 CARDSLOT_STATUS_CARD_16) { 931 #if 0 932 struct pcic_handle *ph = 933 &sc->sc_pcmcia_h; 934 935 pcmcia_card_deactivate(ph->pcmcia); 936 pccbb_pcmcia_socket_disable(ph); 937 pccbb_pcmcia_detach_card(ph, 938 DETACH_FORCE); 939 #endif 940 cardslot_event_throw(sc->sc_csc, 941 CARDSLOT_EVENT_REMOVAL_16); 942 } else if (sc->sc_csc->sc_status & 943 CARDSLOT_STATUS_CARD_CB) { 944 /* Cardbus intr removed */ 945 cardslot_event_throw(sc->sc_csc, 946 CARDSLOT_EVENT_REMOVAL_CB); 947 } 948 } 949 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 950 /* 951 * The pccbbintr may called from powerdown hook when 952 * the system resumed, to detect the card 953 * insertion/removal during suspension. 954 */ 955 (sc->sc_flags & CBB_CARDEXIST) == 0) { 956 if (sc->sc_flags & CBB_INSERTING) { 957 callout_stop(&sc->sc_insert_ch); 958 } 959 callout_reset(&sc->sc_insert_ch, hz / 10, 960 pci113x_insert, sc); 961 sc->sc_flags |= CBB_INSERTING; 962 } 963 } 964 965 return (1); 966 } 967 968 /* 969 * static int pccbbintr_function(struct pccbb_softc *sc) 970 * 971 * This function calls each interrupt handler registered at the 972 * bridge. The interrupt handlers are called in registered order. 973 */ 974 static int 975 pccbbintr_function(sc) 976 struct pccbb_softc *sc; 977 { 978 int retval = 0, val; 979 struct pccbb_intrhand_list *pil; 980 int s, splchanged; 981 982 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 983 /* 984 * XXX priority change. gross. I use if-else 985 * sentense instead of switch-case sentense because of 986 * avoiding duplicate case value error. More than one 987 * IPL_XXX use same value. It depends on 988 * implimentation. 989 */ 990 splchanged = 1; 991 if (pil->pil_level == IPL_SERIAL) { 992 s = splserial(); 993 } else if (pil->pil_level == IPL_HIGH) { 994 s = splhigh(); 995 } else if (pil->pil_level == IPL_CLOCK) { 996 s = splclock(); 997 } else if (pil->pil_level == IPL_AUDIO) { 998 s = splaudio(); 999 } else if (pil->pil_level == IPL_IMP) { 1000 s = splimp(); 1001 } else if (pil->pil_level == IPL_TTY) { 1002 s = spltty(); 1003 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1004 s = splsoftserial(); 1005 } else if (pil->pil_level == IPL_NET) { 1006 s = splnet(); 1007 } else { 1008 splchanged = 0; 1009 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1010 } 1011 1012 val = (*pil->pil_func)(pil->pil_arg); 1013 1014 if (splchanged != 0) { 1015 splx(s); 1016 } 1017 1018 retval = retval == 1 ? 1 : 1019 retval == 0 ? val : val != 0 ? val : retval; 1020 } 1021 1022 return retval; 1023 } 1024 1025 static void 1026 pci113x_insert(arg) 1027 void *arg; 1028 { 1029 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1030 u_int32_t sockevent, sockstate; 1031 1032 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1033 CB_SOCKET_EVENT); 1034 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1035 CB_SOCKET_STAT); 1036 1037 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1038 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1039 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1040 sc->sc_flags |= CBB_CARDEXIST; 1041 /* call pccard interrupt handler here */ 1042 if (sockstate & CB_SOCKET_STAT_16BIT) { 1043 /* 16-bit card found */ 1044 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1045 cardslot_event_throw(sc->sc_csc, 1046 CARDSLOT_EVENT_INSERTION_16); 1047 } else if (sockstate & CB_SOCKET_STAT_CB) { 1048 /* cardbus card found */ 1049 /* cardbus_attach_card(sc->sc_csc); */ 1050 cardslot_event_throw(sc->sc_csc, 1051 CARDSLOT_EVENT_INSERTION_CB); 1052 } else { 1053 /* who are you? */ 1054 } 1055 } else { 1056 callout_reset(&sc->sc_insert_ch, hz / 10, 1057 pci113x_insert, sc); 1058 } 1059 } 1060 1061 #define PCCBB_PCMCIA_OFFSET 0x800 1062 static u_int8_t 1063 pccbb_pcmcia_read(ph, reg) 1064 struct pcic_handle *ph; 1065 int reg; 1066 { 1067 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1068 PCCBB_PCMCIA_OFFSET + reg); 1069 } 1070 1071 static void 1072 pccbb_pcmcia_write(ph, reg, val) 1073 struct pcic_handle *ph; 1074 int reg; 1075 u_int8_t val; 1076 { 1077 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1078 val); 1079 } 1080 1081 /* 1082 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1083 */ 1084 STATIC int 1085 pccbb_ctrl(ct, command) 1086 cardbus_chipset_tag_t ct; 1087 int command; 1088 { 1089 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1090 1091 switch (command) { 1092 case CARDBUS_CD: 1093 if (2 == pccbb_detect_card(sc)) { 1094 int retval = 0; 1095 int status = cb_detect_voltage(sc); 1096 if (PCCARD_VCC_5V & status) { 1097 retval |= CARDBUS_5V_CARD; 1098 } 1099 if (PCCARD_VCC_3V & status) { 1100 retval |= CARDBUS_3V_CARD; 1101 } 1102 if (PCCARD_VCC_XV & status) { 1103 retval |= CARDBUS_XV_CARD; 1104 } 1105 if (PCCARD_VCC_YV & status) { 1106 retval |= CARDBUS_YV_CARD; 1107 } 1108 return retval; 1109 } else { 1110 return 0; 1111 } 1112 break; 1113 case CARDBUS_RESET: 1114 return cb_reset(sc); 1115 break; 1116 case CARDBUS_IO_ENABLE: /* fallthrough */ 1117 case CARDBUS_IO_DISABLE: /* fallthrough */ 1118 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1119 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1120 case CARDBUS_BM_ENABLE: /* fallthrough */ 1121 case CARDBUS_BM_DISABLE: /* fallthrough */ 1122 return pccbb_cardenable(sc, command); 1123 break; 1124 } 1125 1126 return 0; 1127 } 1128 1129 /* 1130 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1131 * This function returns true when it succeeds and returns false when 1132 * it fails. 1133 */ 1134 STATIC int 1135 pccbb_power(ct, command) 1136 cardbus_chipset_tag_t ct; 1137 int command; 1138 { 1139 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1140 1141 u_int32_t status, sock_ctrl; 1142 bus_space_tag_t memt = sc->sc_base_memt; 1143 bus_space_handle_t memh = sc->sc_base_memh; 1144 1145 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1146 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1147 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1148 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1149 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1150 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1151 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1152 "UNKNOWN", 1153 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1154 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1155 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1156 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1157 "UNKNOWN", command)); 1158 1159 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1160 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1161 1162 switch (command & CARDBUS_VCCMASK) { 1163 case CARDBUS_VCC_UC: 1164 break; 1165 case CARDBUS_VCC_5V: 1166 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1167 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1168 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1169 } else { 1170 printf("%s: BAD voltage request: no 5 V card\n", 1171 sc->sc_dev.dv_xname); 1172 } 1173 break; 1174 case CARDBUS_VCC_3V: 1175 if (CB_SOCKET_STAT_3VCARD & status) { 1176 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1177 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1178 } else { 1179 printf("%s: BAD voltage request: no 3.3 V card\n", 1180 sc->sc_dev.dv_xname); 1181 } 1182 break; 1183 case CARDBUS_VCC_0V: 1184 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1185 break; 1186 default: 1187 return 0; /* power NEVER changed */ 1188 break; 1189 } 1190 1191 switch (command & CARDBUS_VPPMASK) { 1192 case CARDBUS_VPP_UC: 1193 break; 1194 case CARDBUS_VPP_0V: 1195 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1196 break; 1197 case CARDBUS_VPP_VCC: 1198 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1199 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1200 break; 1201 case CARDBUS_VPP_12V: 1202 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1203 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1204 break; 1205 } 1206 1207 #if 0 1208 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1209 #endif 1210 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1211 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1212 1213 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1214 /* 1215 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1216 * time is 20 ms, some PC-Card bridge requires longer duration. 1217 */ 1218 delay(200 * 1000); 1219 1220 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1221 printf 1222 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1223 sc->sc_dev.dv_xname, sock_ctrl, status); 1224 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1225 (command & CARDBUS_VCCMASK) == 1226 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1227 CARDBUS_VCCMASK) == 1228 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1229 CARDBUS_VCCMASK) == 1230 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1231 CARDBUS_VCCMASK) == 1232 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1233 CARDBUS_VCCMASK) == 1234 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1235 CARDBUS_VCCMASK) == 1236 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1237 (command & CARDBUS_VPPMASK) == 1238 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1239 CARDBUS_VPPMASK) == 1240 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1241 CARDBUS_VPPMASK) == 1242 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1243 CARDBUS_VPPMASK) == 1244 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1245 #if 0 1246 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1247 u_int32_t force = 1248 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1249 /* Reset Bad Vcc request */ 1250 force &= ~CB_SOCKET_FORCE_BADVCC; 1251 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1252 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1253 CB_SOCKET_STAT)); 1254 return 1; 1255 } 1256 #endif 1257 return 0; 1258 } 1259 return 1; /* power changed correctly */ 1260 } 1261 1262 #if defined CB_PCMCIA_POLL 1263 struct cb_poll_str { 1264 void *arg; 1265 int (*func) __P((void *)); 1266 int level; 1267 pccard_chipset_tag_t ct; 1268 int count; 1269 struct callout poll_ch; 1270 }; 1271 1272 static struct cb_poll_str cb_poll[10]; 1273 static int cb_poll_n = 0; 1274 1275 static void cb_pcmcia_poll __P((void *arg)); 1276 1277 static void 1278 cb_pcmcia_poll(arg) 1279 void *arg; 1280 { 1281 struct cb_poll_str *poll = arg; 1282 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1283 struct pccbb_softc *sc = psc->cpc_parent; 1284 int s; 1285 u_int32_t spsr; /* socket present-state reg */ 1286 1287 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1288 switch (poll->level) { 1289 case IPL_NET: 1290 s = splnet(); 1291 break; 1292 case IPL_BIO: 1293 s = splbio(); 1294 break; 1295 case IPL_TTY: /* fallthrough */ 1296 default: 1297 s = spltty(); 1298 break; 1299 } 1300 1301 spsr = 1302 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1303 CB_SOCKET_STAT); 1304 1305 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1306 if (!(spsr & 0x40)) { /* CINT low */ 1307 #else 1308 if (1) { 1309 #endif 1310 if ((*poll->func) (poll->arg) == 1) { 1311 ++poll->count; 1312 printf("intr: reported from poller, 0x%x\n", spsr); 1313 #if defined LEVEL2 1314 } else { 1315 printf("intr: miss! 0x%x\n", spsr); 1316 #endif 1317 } 1318 } 1319 splx(s); 1320 } 1321 #endif /* defined CB_PCMCIA_POLL */ 1322 1323 /* 1324 * static int pccbb_detect_card(struct pccbb_softc *sc) 1325 * return value: 0 if no card exists. 1326 * 1 if 16-bit card exists. 1327 * 2 if cardbus card exists. 1328 */ 1329 static int 1330 pccbb_detect_card(sc) 1331 struct pccbb_softc *sc; 1332 { 1333 bus_space_handle_t base_memh = sc->sc_base_memh; 1334 bus_space_tag_t base_memt = sc->sc_base_memt; 1335 u_int32_t sockstat = 1336 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1337 int retval = 0; 1338 1339 /* CD1 and CD2 asserted */ 1340 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1341 /* card must be present */ 1342 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1343 /* NOTACARD DEASSERTED */ 1344 if (CB_SOCKET_STAT_CB & sockstat) { 1345 /* CardBus mode */ 1346 retval = 2; 1347 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1348 /* 16-bit mode */ 1349 retval = 1; 1350 } 1351 } 1352 } 1353 return retval; 1354 } 1355 1356 /* 1357 * STATIC int cb_reset(struct pccbb_softc *sc) 1358 * This function resets CardBus card. 1359 */ 1360 STATIC int 1361 cb_reset(sc) 1362 struct pccbb_softc *sc; 1363 { 1364 /* 1365 * Reset Assert at least 20 ms 1366 * Some machines request longer duration. 1367 */ 1368 int reset_duration = 1369 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1370 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1371 1372 /* Reset bit Assert (bit 6 at 0x3E) */ 1373 bcr |= CB_BCR_RESET_ENABLE; 1374 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1375 delay(reset_duration); 1376 1377 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1378 /* Reset bit Deassert (bit 6 at 0x3E) */ 1379 bcr &= ~CB_BCR_RESET_ENABLE; 1380 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1381 delay(reset_duration); 1382 } 1383 /* No card found on the slot. Keep Reset. */ 1384 return 1; 1385 } 1386 1387 /* 1388 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1389 * This function detect card Voltage. 1390 */ 1391 STATIC int 1392 cb_detect_voltage(sc) 1393 struct pccbb_softc *sc; 1394 { 1395 u_int32_t psr; /* socket present-state reg */ 1396 bus_space_tag_t iot = sc->sc_base_memt; 1397 bus_space_handle_t ioh = sc->sc_base_memh; 1398 int vol = PCCARD_VCC_UKN; /* set 0 */ 1399 1400 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1401 1402 if (0x400u & psr) { 1403 vol |= PCCARD_VCC_5V; 1404 } 1405 if (0x800u & psr) { 1406 vol |= PCCARD_VCC_3V; 1407 } 1408 1409 return vol; 1410 } 1411 1412 STATIC int 1413 cbbprint(aux, pcic) 1414 void *aux; 1415 const char *pcic; 1416 { 1417 /* 1418 struct cbslot_attach_args *cba = aux; 1419 1420 if (cba->cba_slot >= 0) { 1421 printf(" slot %d", cba->cba_slot); 1422 } 1423 */ 1424 return UNCONF; 1425 } 1426 1427 /* 1428 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1429 * This function enables and disables the card 1430 */ 1431 STATIC int 1432 pccbb_cardenable(sc, function) 1433 struct pccbb_softc *sc; 1434 int function; 1435 { 1436 u_int32_t command = 1437 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1438 1439 DPRINTF(("pccbb_cardenable:")); 1440 switch (function) { 1441 case CARDBUS_IO_ENABLE: 1442 command |= PCI_COMMAND_IO_ENABLE; 1443 break; 1444 case CARDBUS_IO_DISABLE: 1445 command &= ~PCI_COMMAND_IO_ENABLE; 1446 break; 1447 case CARDBUS_MEM_ENABLE: 1448 command |= PCI_COMMAND_MEM_ENABLE; 1449 break; 1450 case CARDBUS_MEM_DISABLE: 1451 command &= ~PCI_COMMAND_MEM_ENABLE; 1452 break; 1453 case CARDBUS_BM_ENABLE: 1454 command |= PCI_COMMAND_MASTER_ENABLE; 1455 break; 1456 case CARDBUS_BM_DISABLE: 1457 command &= ~PCI_COMMAND_MASTER_ENABLE; 1458 break; 1459 default: 1460 return 0; 1461 } 1462 1463 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1464 DPRINTF((" command reg 0x%x\n", command)); 1465 return 1; 1466 } 1467 1468 #if !rbus 1469 /* 1470 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1471 */ 1472 static int 1473 pccbb_io_open(ct, win, start, end) 1474 cardbus_chipset_tag_t ct; 1475 int win; 1476 u_int32_t start, end; 1477 { 1478 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1479 int basereg; 1480 int limitreg; 1481 1482 if ((win < 0) || (win > 2)) { 1483 #if defined DIAGNOSTIC 1484 printf("cardbus_io_open: window out of range %d\n", win); 1485 #endif 1486 return 0; 1487 } 1488 1489 basereg = win * 8 + 0x2c; 1490 limitreg = win * 8 + 0x30; 1491 1492 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1493 start, basereg, end, limitreg)); 1494 1495 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1496 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1497 return 1; 1498 } 1499 1500 /* 1501 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1502 */ 1503 static int 1504 pccbb_io_close(ct, win) 1505 cardbus_chipset_tag_t ct; 1506 int win; 1507 { 1508 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1509 int basereg; 1510 int limitreg; 1511 1512 if ((win < 0) || (win > 2)) { 1513 #if defined DIAGNOSTIC 1514 printf("cardbus_io_close: window out of range %d\n", win); 1515 #endif 1516 return 0; 1517 } 1518 1519 basereg = win * 8 + 0x2c; 1520 limitreg = win * 8 + 0x30; 1521 1522 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1523 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1524 return 1; 1525 } 1526 1527 /* 1528 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1529 */ 1530 static int 1531 pccbb_mem_open(ct, win, start, end) 1532 cardbus_chipset_tag_t ct; 1533 int win; 1534 u_int32_t start, end; 1535 { 1536 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1537 int basereg; 1538 int limitreg; 1539 1540 if ((win < 0) || (win > 2)) { 1541 #if defined DIAGNOSTIC 1542 printf("cardbus_mem_open: window out of range %d\n", win); 1543 #endif 1544 return 0; 1545 } 1546 1547 basereg = win * 8 + 0x1c; 1548 limitreg = win * 8 + 0x20; 1549 1550 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1551 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1552 return 1; 1553 } 1554 1555 /* 1556 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1557 */ 1558 static int 1559 pccbb_mem_close(ct, win) 1560 cardbus_chipset_tag_t ct; 1561 int win; 1562 { 1563 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1564 int basereg; 1565 int limitreg; 1566 1567 if ((win < 0) || (win > 2)) { 1568 #if defined DIAGNOSTIC 1569 printf("cardbus_mem_close: window out of range %d\n", win); 1570 #endif 1571 return 0; 1572 } 1573 1574 basereg = win * 8 + 0x1c; 1575 limitreg = win * 8 + 0x20; 1576 1577 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1578 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1579 return 1; 1580 } 1581 #endif 1582 1583 /* 1584 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1585 * int irq, 1586 * int level, 1587 * int (* func) __P((void *)), 1588 * void *arg) 1589 * 1590 * This function registers an interrupt handler at the bridge, in 1591 * order not to call the interrupt handlers of child devices when 1592 * a card-deletion interrupt occurs. 1593 * 1594 * The arguments irq and level are not used. 1595 */ 1596 static void * 1597 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1598 cardbus_chipset_tag_t ct; 1599 int irq, level; 1600 int (*func) __P((void *)); 1601 void *arg; 1602 { 1603 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1604 1605 return pccbb_intr_establish(sc, irq, level, func, arg); 1606 } 1607 1608 1609 /* 1610 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1611 * void *ih) 1612 * 1613 * This function removes an interrupt handler pointed by ih. 1614 */ 1615 static void 1616 pccbb_cb_intr_disestablish(ct, ih) 1617 cardbus_chipset_tag_t ct; 1618 void *ih; 1619 { 1620 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1621 1622 pccbb_intr_disestablish(sc, ih); 1623 } 1624 1625 1626 /* 1627 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1628 * int irq, 1629 * int level, 1630 * int (* func) __P((void *)), 1631 * void *arg) 1632 * 1633 * This function registers an interrupt handler at the bridge, in 1634 * order not to call the interrupt handlers of child devices when 1635 * a card-deletion interrupt occurs. 1636 * 1637 * The arguments irq is not used because pccbb selects intr vector. 1638 */ 1639 static void * 1640 pccbb_intr_establish(sc, irq, level, func, arg) 1641 struct pccbb_softc *sc; 1642 int irq, level; 1643 int (*func) __P((void *)); 1644 void *arg; 1645 { 1646 struct pccbb_intrhand_list *pil, *newpil; 1647 1648 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1649 1650 if (sc->sc_pil == NULL) { 1651 /* initialize bridge intr routing */ 1652 1653 switch (sc->sc_chipset) { 1654 case CB_TI113X: 1655 { 1656 pcireg_t cbctrl = 1657 pci_conf_read(sc->sc_pc, sc->sc_tag, 1658 PCI_CBCTRL); 1659 /* functional intr enabled */ 1660 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1661 pci_conf_write(sc->sc_pc, sc->sc_tag, 1662 PCI_CBCTRL, cbctrl); 1663 break; 1664 } 1665 default: 1666 break; 1667 } 1668 } 1669 1670 /* 1671 * Allocate a room for interrupt handler structure. 1672 */ 1673 if (NULL == (newpil = 1674 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1675 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1676 return NULL; 1677 } 1678 1679 newpil->pil_func = func; 1680 newpil->pil_arg = arg; 1681 newpil->pil_level = level; 1682 newpil->pil_next = NULL; 1683 1684 if (sc->sc_pil == NULL) { 1685 sc->sc_pil = newpil; 1686 } else { 1687 for (pil = sc->sc_pil; pil->pil_next != NULL; 1688 pil = pil->pil_next); 1689 pil->pil_next = newpil; 1690 } 1691 1692 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1693 1694 return newpil; 1695 } 1696 1697 /* 1698 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1699 * void *ih) 1700 * 1701 * This function removes an interrupt handler pointed by ih. 1702 */ 1703 static void 1704 pccbb_intr_disestablish(sc, ih) 1705 struct pccbb_softc *sc; 1706 void *ih; 1707 { 1708 struct pccbb_intrhand_list *pil, **pil_prev; 1709 1710 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1711 1712 pil_prev = &sc->sc_pil; 1713 1714 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1715 if (pil == ih) { 1716 *pil_prev = pil->pil_next; 1717 free(pil, M_DEVBUF); 1718 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1719 break; 1720 } 1721 pil_prev = &pil->pil_next; 1722 } 1723 1724 if (sc->sc_pil == NULL) { 1725 /* No interrupt handlers */ 1726 1727 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1728 1729 switch (sc->sc_chipset) { 1730 case CB_TI113X: 1731 { 1732 pcireg_t cbctrl = 1733 pci_conf_read(sc->sc_pc, sc->sc_tag, 1734 PCI_CBCTRL); 1735 /* functional intr disabled */ 1736 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1737 pci_conf_write(sc->sc_pc, sc->sc_tag, 1738 PCI_CBCTRL, cbctrl); 1739 break; 1740 } 1741 default: 1742 break; 1743 } 1744 } 1745 } 1746 1747 #if defined SHOW_REGS 1748 static void 1749 cb_show_regs(pc, tag, memt, memh) 1750 pci_chipset_tag_t pc; 1751 pcitag_t tag; 1752 bus_space_tag_t memt; 1753 bus_space_handle_t memh; 1754 { 1755 int i; 1756 printf("PCI config regs:"); 1757 for (i = 0; i < 0x50; i += 4) { 1758 if (i % 16 == 0) { 1759 printf("\n 0x%02x:", i); 1760 } 1761 printf(" %08x", pci_conf_read(pc, tag, i)); 1762 } 1763 for (i = 0x80; i < 0xb0; i += 4) { 1764 if (i % 16 == 0) { 1765 printf("\n 0x%02x:", i); 1766 } 1767 printf(" %08x", pci_conf_read(pc, tag, i)); 1768 } 1769 1770 if (memh == 0) { 1771 printf("\n"); 1772 return; 1773 } 1774 1775 printf("\nsocket regs:"); 1776 for (i = 0; i <= 0x10; i += 0x04) { 1777 printf(" %08x", bus_space_read_4(memt, memh, i)); 1778 } 1779 printf("\nExCA regs:"); 1780 for (i = 0; i < 0x08; ++i) { 1781 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1782 } 1783 printf("\n"); 1784 return; 1785 } 1786 #endif 1787 1788 /* 1789 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1790 * int busno, int devno, int function) 1791 * This is the function to make a tag to access config space of 1792 * a CardBus Card. It works same as pci_conf_read. 1793 */ 1794 static cardbustag_t 1795 pccbb_make_tag(cc, busno, devno, function) 1796 cardbus_chipset_tag_t cc; 1797 int busno, devno, function; 1798 { 1799 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1800 1801 return pci_make_tag(sc->sc_pc, busno, devno, function); 1802 } 1803 1804 static void 1805 pccbb_free_tag(cc, tag) 1806 cardbus_chipset_tag_t cc; 1807 cardbustag_t tag; 1808 { 1809 } 1810 1811 /* 1812 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1813 * cardbustag_t tag, int offset) 1814 * This is the function to read the config space of a CardBus Card. 1815 * It works same as pci_conf_read. 1816 */ 1817 static cardbusreg_t 1818 pccbb_conf_read(cc, tag, offset) 1819 cardbus_chipset_tag_t cc; 1820 cardbustag_t tag; 1821 int offset; /* register offset */ 1822 { 1823 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1824 1825 return pci_conf_read(sc->sc_pc, tag, offset); 1826 } 1827 1828 /* 1829 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1830 * int offs, cardbusreg_t val) 1831 * This is the function to write the config space of a CardBus Card. 1832 * It works same as pci_conf_write. 1833 */ 1834 static void 1835 pccbb_conf_write(cc, tag, reg, val) 1836 cardbus_chipset_tag_t cc; 1837 cardbustag_t tag; 1838 int reg; /* register offset */ 1839 cardbusreg_t val; 1840 { 1841 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1842 1843 pci_conf_write(sc->sc_pc, tag, reg, val); 1844 } 1845 1846 #if 0 1847 STATIC int 1848 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1849 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1850 int speed, int flags, 1851 bus_space_handle_t * iohp) 1852 #endif 1853 /* 1854 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1855 * bus_addr_t start, bus_size_t size, 1856 * bus_size_t align, 1857 * struct pcmcia_io_handle *pcihp 1858 * 1859 * This function only allocates I/O region for pccard. This function 1860 * never maps the allocated region to pccard I/O area. 1861 * 1862 * XXX: The interface of this function is not very good, I believe. 1863 */ 1864 STATIC int 1865 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1866 pcmcia_chipset_handle_t pch; 1867 bus_addr_t start; /* start address */ 1868 bus_size_t size; 1869 bus_size_t align; 1870 struct pcmcia_io_handle *pcihp; 1871 { 1872 struct pcic_handle *ph = (struct pcic_handle *)pch; 1873 bus_addr_t ioaddr; 1874 int flags = 0; 1875 bus_space_tag_t iot; 1876 bus_space_handle_t ioh; 1877 #if rbus 1878 rbus_tag_t rb; 1879 #endif 1880 if (align == 0) { 1881 align = size; /* XXX: funny??? */ 1882 } 1883 1884 /* 1885 * Allocate some arbitrary I/O space. 1886 */ 1887 1888 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1889 1890 #if rbus 1891 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1892 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1893 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1894 return 1; 1895 } 1896 #else 1897 if (start) { 1898 ioaddr = start; 1899 if (bus_space_map(iot, start, size, 0, &ioh)) { 1900 return 1; 1901 } 1902 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1903 (u_long) ioaddr, (u_long) size)); 1904 } else { 1905 flags |= PCMCIA_IO_ALLOCATED; 1906 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1907 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1908 size, align, 0, 0, &ioaddr, &ioh)) { 1909 /* No room be able to be get. */ 1910 return 1; 1911 } 1912 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1913 (u_long) ioaddr, (u_long) size)); 1914 } 1915 #endif 1916 1917 pcihp->iot = iot; 1918 pcihp->ioh = ioh; 1919 pcihp->addr = ioaddr; 1920 pcihp->size = size; 1921 pcihp->flags = flags; 1922 1923 return 0; 1924 } 1925 1926 /* 1927 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1928 * struct pcmcia_io_handle *pcihp) 1929 * 1930 * This function only frees I/O region for pccard. 1931 * 1932 * XXX: The interface of this function is not very good, I believe. 1933 */ 1934 void 1935 pccbb_pcmcia_io_free(pch, pcihp) 1936 pcmcia_chipset_handle_t pch; 1937 struct pcmcia_io_handle *pcihp; 1938 { 1939 #if !rbus 1940 bus_space_tag_t iot = pcihp->iot; 1941 #endif 1942 bus_space_handle_t ioh = pcihp->ioh; 1943 bus_size_t size = pcihp->size; 1944 1945 #if rbus 1946 struct pccbb_softc *sc = 1947 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1948 rbus_tag_t rb = sc->sc_rbus_iot; 1949 1950 rbus_space_free(rb, ioh, size, NULL); 1951 #else 1952 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1953 bus_space_free(iot, ioh, size); 1954 else 1955 bus_space_unmap(iot, ioh, size); 1956 #endif 1957 } 1958 1959 /* 1960 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1961 * bus_addr_t offset, bus_size_t size, 1962 * struct pcmcia_io_handle *pcihp, 1963 * int *windowp) 1964 * 1965 * This function maps the allocated I/O region to pccard. This function 1966 * never allocates any I/O region for pccard I/O area. I don't 1967 * understand why the original authors of pcmciabus separated alloc and 1968 * map. I believe the two must be unite. 1969 * 1970 * XXX: no wait timing control? 1971 */ 1972 int 1973 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1974 pcmcia_chipset_handle_t pch; 1975 int width; 1976 bus_addr_t offset; 1977 bus_size_t size; 1978 struct pcmcia_io_handle *pcihp; 1979 int *windowp; 1980 { 1981 struct pcic_handle *ph = (struct pcic_handle *)pch; 1982 bus_addr_t ioaddr = pcihp->addr + offset; 1983 int i, win; 1984 #if defined CBB_DEBUG 1985 static char *width_names[] = { "dynamic", "io8", "io16" }; 1986 #endif 1987 1988 /* Sanity check I/O handle. */ 1989 1990 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1991 panic("pccbb_pcmcia_io_map iot is bogus"); 1992 } 1993 1994 /* XXX Sanity check offset/size. */ 1995 1996 win = -1; 1997 for (i = 0; i < PCIC_IO_WINS; i++) { 1998 if ((ph->ioalloc & (1 << i)) == 0) { 1999 win = i; 2000 ph->ioalloc |= (1 << i); 2001 break; 2002 } 2003 } 2004 2005 if (win == -1) { 2006 return 1; 2007 } 2008 2009 *windowp = win; 2010 2011 /* XXX this is pretty gross */ 2012 2013 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2014 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2015 2016 /* XXX wtf is this doing here? */ 2017 2018 #if 0 2019 printf(" port 0x%lx", (u_long) ioaddr); 2020 if (size > 1) { 2021 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2022 } 2023 #endif 2024 2025 ph->io[win].addr = ioaddr; 2026 ph->io[win].size = size; 2027 ph->io[win].width = width; 2028 2029 /* actual dirty register-value changing in the function below. */ 2030 pccbb_pcmcia_do_io_map(ph, win); 2031 2032 return 0; 2033 } 2034 2035 /* 2036 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2037 * 2038 * This function changes register-value to map I/O region for pccard. 2039 */ 2040 static void 2041 pccbb_pcmcia_do_io_map(ph, win) 2042 struct pcic_handle *ph; 2043 int win; 2044 { 2045 static u_int8_t pcic_iowidth[3] = { 2046 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2047 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2048 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2049 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2050 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2051 }; 2052 2053 #define PCIC_SIA_START_LOW 0 2054 #define PCIC_SIA_START_HIGH 1 2055 #define PCIC_SIA_STOP_LOW 2 2056 #define PCIC_SIA_STOP_HIGH 3 2057 2058 int regbase_win = 0x8 + win * 0x04; 2059 u_int8_t ioctl, enable; 2060 2061 DPRINTF( 2062 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2063 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2064 ph->io[win].width * 8)); 2065 2066 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2067 ph->io[win].addr & 0xff); 2068 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2069 (ph->io[win].addr >> 8) & 0xff); 2070 2071 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2072 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2073 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2074 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2075 2076 ioctl = Pcic_read(ph, PCIC_IOCTL); 2077 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2078 switch (win) { 2079 case 0: 2080 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2081 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2082 PCIC_IOCTL_IO0_DATASIZE_MASK); 2083 ioctl |= pcic_iowidth[ph->io[win].width]; 2084 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2085 break; 2086 case 1: 2087 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2088 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2089 PCIC_IOCTL_IO1_DATASIZE_MASK); 2090 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2091 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2092 break; 2093 } 2094 Pcic_write(ph, PCIC_IOCTL, ioctl); 2095 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2096 #if defined CBB_DEBUG 2097 { 2098 u_int8_t start_low = 2099 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2100 u_int8_t start_high = 2101 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2102 u_int8_t stop_low = 2103 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2104 u_int8_t stop_high = 2105 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2106 printf 2107 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2108 start_low, start_high, stop_low, stop_high, ioctl, enable); 2109 } 2110 #endif 2111 } 2112 2113 /* 2114 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2115 * 2116 * This function unmaps I/O region. No return value. 2117 */ 2118 STATIC void 2119 pccbb_pcmcia_io_unmap(pch, win) 2120 pcmcia_chipset_handle_t pch; 2121 int win; 2122 { 2123 struct pcic_handle *ph = (struct pcic_handle *)pch; 2124 int reg; 2125 2126 if (win >= PCIC_IO_WINS || win < 0) { 2127 panic("pccbb_pcmcia_io_unmap: window out of range"); 2128 } 2129 2130 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2131 switch (win) { 2132 case 0: 2133 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2134 break; 2135 case 1: 2136 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2137 break; 2138 } 2139 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2140 2141 ph->ioalloc &= ~(1 << win); 2142 } 2143 2144 /* 2145 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2146 * 2147 * This function enables the card. All information is stored in 2148 * the first argument, pcmcia_chipset_handle_t. 2149 */ 2150 static void 2151 pccbb_pcmcia_wait_ready(ph) 2152 struct pcic_handle *ph; 2153 { 2154 int i; 2155 2156 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2157 Pcic_read(ph, PCIC_IF_STATUS))); 2158 2159 for (i = 0; i < 10000; i++) { 2160 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2161 return; 2162 } 2163 delay(500); 2164 #ifdef CBB_DEBUG 2165 if ((i > 5000) && (i % 100 == 99)) 2166 printf("."); 2167 #endif 2168 } 2169 2170 #ifdef DIAGNOSTIC 2171 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2172 Pcic_read(ph, PCIC_IF_STATUS)); 2173 #endif 2174 } 2175 2176 /* 2177 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2178 * 2179 * This function enables the card. All information is stored in 2180 * the first argument, pcmcia_chipset_handle_t. 2181 */ 2182 STATIC void 2183 pccbb_pcmcia_socket_enable(pch) 2184 pcmcia_chipset_handle_t pch; 2185 { 2186 struct pcic_handle *ph = (struct pcic_handle *)pch; 2187 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2188 int cardtype, win; 2189 u_int8_t power, intr; 2190 pcireg_t spsr; 2191 int voltage; 2192 2193 /* this bit is mostly stolen from pcic_attach_card */ 2194 2195 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2196 2197 /* get card Vcc info */ 2198 2199 spsr = 2200 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2201 CB_SOCKET_STAT); 2202 if (spsr & CB_SOCKET_STAT_5VCARD) { 2203 DPRINTF(("5V card\n")); 2204 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2205 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2206 DPRINTF(("3V card\n")); 2207 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2208 } else { 2209 printf("?V card, 0x%x\n", spsr); /* XXX */ 2210 return; 2211 } 2212 2213 /* assert reset bit */ 2214 intr = Pcic_read(ph, PCIC_INTR); 2215 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2216 Pcic_write(ph, PCIC_INTR, intr); 2217 2218 /* disable socket i/o: negate output enable bit */ 2219 2220 power = Pcic_read(ph, PCIC_PWRCTL); 2221 power &= ~PCIC_PWRCTL_OE; 2222 Pcic_write(ph, PCIC_PWRCTL, power); 2223 2224 /* power down the socket to reset it, clear the card reset pin */ 2225 2226 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2227 2228 /* 2229 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2230 * we are changing Vcc (Toff). 2231 */ 2232 /* delay(300*1000); too much */ 2233 2234 /* power up the socket */ 2235 pccbb_power(sc, voltage); 2236 2237 /* 2238 * wait 100ms until power raise (Tpr) and 20ms to become 2239 * stable (Tsu(Vcc)). 2240 * 2241 * some machines require some more time to be settled 2242 * (another 200ms is added here). 2243 */ 2244 /* delay((100 + 20 + 200)*1000); too much */ 2245 2246 power = Pcic_read(ph, PCIC_PWRCTL); 2247 power |= PCIC_PWRCTL_OE; 2248 Pcic_write(ph, PCIC_PWRCTL, power); 2249 2250 /* 2251 * hold RESET at least 10us. 2252 */ 2253 delay(10); 2254 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2255 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2256 2257 /* clear the reset flag */ 2258 2259 intr |= PCIC_INTR_RESET; 2260 Pcic_write(ph, PCIC_INTR, intr); 2261 2262 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2263 2264 delay(20000); 2265 2266 /* wait for the chip to finish initializing */ 2267 2268 pccbb_pcmcia_wait_ready(ph); 2269 2270 /* zero out the address windows */ 2271 2272 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2273 2274 /* set the card type */ 2275 2276 cardtype = pcmcia_card_gettype(ph->pcmcia); 2277 2278 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2279 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2280 Pcic_write(ph, PCIC_INTR, intr); 2281 2282 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2283 ph->ph_parent->dv_xname, ph->sock, 2284 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2285 2286 /* reinstall all the memory and io mappings */ 2287 2288 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2289 if (ph->memalloc & (1 << win)) { 2290 pccbb_pcmcia_do_mem_map(ph, win); 2291 } 2292 } 2293 2294 for (win = 0; win < PCIC_IO_WINS; ++win) { 2295 if (ph->ioalloc & (1 << win)) { 2296 pccbb_pcmcia_do_io_map(ph, win); 2297 } 2298 } 2299 } 2300 2301 /* 2302 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2303 * 2304 * This function disables the card. All information is stored in 2305 * the first argument, pcmcia_chipset_handle_t. 2306 */ 2307 STATIC void 2308 pccbb_pcmcia_socket_disable(pch) 2309 pcmcia_chipset_handle_t pch; 2310 { 2311 struct pcic_handle *ph = (struct pcic_handle *)pch; 2312 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2313 u_int8_t power, intr; 2314 2315 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2316 2317 /* reset signal asserting... */ 2318 2319 intr = Pcic_read(ph, PCIC_INTR); 2320 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2321 Pcic_write(ph, PCIC_INTR, intr); 2322 delay(2 * 1000); 2323 2324 /* power down the socket */ 2325 power = Pcic_read(ph, PCIC_PWRCTL); 2326 power &= ~PCIC_PWRCTL_OE; 2327 Pcic_write(ph, PCIC_PWRCTL, power); 2328 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2329 /* 2330 * wait 300ms until power fails (Tpf). 2331 */ 2332 delay(300 * 1000); 2333 } 2334 2335 /* 2336 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2337 * 2338 * This function detects whether a card is in the slot or not. 2339 * If a card is inserted, return 1. Otherwise, return 0. 2340 */ 2341 STATIC int 2342 pccbb_pcmcia_card_detect(pch) 2343 pcmcia_chipset_handle_t pch; 2344 { 2345 struct pcic_handle *ph = (struct pcic_handle *)pch; 2346 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2347 2348 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2349 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2350 } 2351 2352 #if 0 2353 STATIC int 2354 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2355 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2356 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2357 #endif 2358 /* 2359 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2360 * bus_size_t size, 2361 * struct pcmcia_mem_handle *pcmhp) 2362 * 2363 * This function only allocates memory region for pccard. This 2364 * function never maps the allocated region to pccard memory area. 2365 * 2366 * XXX: Why the argument of start address is not in? 2367 */ 2368 STATIC int 2369 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2370 pcmcia_chipset_handle_t pch; 2371 bus_size_t size; 2372 struct pcmcia_mem_handle *pcmhp; 2373 { 2374 struct pcic_handle *ph = (struct pcic_handle *)pch; 2375 bus_space_handle_t memh; 2376 bus_addr_t addr; 2377 bus_size_t sizepg; 2378 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2379 #if rbus 2380 rbus_tag_t rb; 2381 #endif 2382 2383 /* out of sc->memh, allocate as many pages as necessary */ 2384 2385 /* convert size to PCIC pages */ 2386 /* 2387 * This is not enough; when the requested region is on the page 2388 * boundaries, this may calculate wrong result. 2389 */ 2390 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2391 #if 0 2392 if (sizepg > PCIC_MAX_MEM_PAGES) { 2393 return 1; 2394 } 2395 #endif 2396 2397 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2398 return 1; 2399 } 2400 2401 addr = 0; /* XXX gcc -Wuninitialized */ 2402 2403 #if rbus 2404 rb = sc->sc_rbus_memt; 2405 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2406 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2407 &addr, &memh)) { 2408 return 1; 2409 } 2410 #else 2411 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2412 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2413 0, /* boundary */ 2414 0, /* flags */ 2415 &addr, &memh)) { 2416 return 1; 2417 } 2418 #endif 2419 2420 DPRINTF( 2421 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2422 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2423 2424 pcmhp->memt = sc->sc_memt; 2425 pcmhp->memh = memh; 2426 pcmhp->addr = addr; 2427 pcmhp->size = size; 2428 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2429 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2430 pcmhp->mhandle = 0; 2431 /* No offset??? Funny. */ 2432 2433 return 0; 2434 } 2435 2436 /* 2437 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2438 * struct pcmcia_mem_handle *pcmhp) 2439 * 2440 * This function release the memory space allocated by the function 2441 * pccbb_pcmcia_mem_alloc(). 2442 */ 2443 STATIC void 2444 pccbb_pcmcia_mem_free(pch, pcmhp) 2445 pcmcia_chipset_handle_t pch; 2446 struct pcmcia_mem_handle *pcmhp; 2447 { 2448 #if rbus 2449 struct pcic_handle *ph = (struct pcic_handle *)pch; 2450 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2451 2452 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2453 #else 2454 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2455 #endif 2456 } 2457 2458 /* 2459 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2460 * 2461 * This function release the memory space allocated by the function 2462 * pccbb_pcmcia_mem_alloc(). 2463 */ 2464 STATIC void 2465 pccbb_pcmcia_do_mem_map(ph, win) 2466 struct pcic_handle *ph; 2467 int win; 2468 { 2469 int regbase_win; 2470 bus_addr_t phys_addr; 2471 bus_addr_t phys_end; 2472 2473 #define PCIC_SMM_START_LOW 0 2474 #define PCIC_SMM_START_HIGH 1 2475 #define PCIC_SMM_STOP_LOW 2 2476 #define PCIC_SMM_STOP_HIGH 3 2477 #define PCIC_CMA_LOW 4 2478 #define PCIC_CMA_HIGH 5 2479 2480 u_int8_t start_low, start_high = 0; 2481 u_int8_t stop_low, stop_high; 2482 u_int8_t off_low, off_high; 2483 u_int8_t mem_window; 2484 int reg; 2485 2486 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2487 int mem8 = 2488 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2489 || (kind == PCMCIA_MEM_ATTR); 2490 2491 regbase_win = 0x10 + win * 0x08; 2492 2493 phys_addr = ph->mem[win].addr; 2494 phys_end = phys_addr + ph->mem[win].size; 2495 2496 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2497 phys_addr, phys_end, ph->mem[win].offset)); 2498 2499 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2500 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2501 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2502 2503 /* bit 19:12 */ 2504 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2505 /* bit 23:20 and bit 7 on */ 2506 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2507 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2508 /* bit 31:24, for 32-bit address */ 2509 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2510 2511 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2512 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2513 2514 if (((struct pccbb_softc *)ph-> 2515 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2516 Pcic_write(ph, 0x40 + win, mem_window); 2517 } 2518 2519 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2520 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2521 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2522 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2523 2524 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2525 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2526 2527 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2528 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2529 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2530 | ((kind == PCMCIA_MEM_ATTR) ? 2531 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2532 2533 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2534 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2535 2536 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2537 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2538 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2539 2540 #if defined CBB_DEBUG 2541 { 2542 int r1, r2, r3, r4, r5, r6, r7 = 0; 2543 2544 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2545 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2546 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2547 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2548 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2549 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2550 if (((struct pccbb_softc *)(ph-> 2551 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2552 r7 = Pcic_read(ph, 0x40 + win); 2553 } 2554 2555 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2556 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2557 if (((struct pccbb_softc *)(ph-> 2558 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2559 DPRINTF((" %02x", r7)); 2560 } 2561 DPRINTF(("\n")); 2562 } 2563 #endif 2564 } 2565 2566 /* 2567 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2568 * bus_addr_t card_addr, bus_size_t size, 2569 * struct pcmcia_mem_handle *pcmhp, 2570 * bus_addr_t *offsetp, int *windowp) 2571 * 2572 * This function maps memory space allocated by the function 2573 * pccbb_pcmcia_mem_alloc(). 2574 */ 2575 STATIC int 2576 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2577 pcmcia_chipset_handle_t pch; 2578 int kind; 2579 bus_addr_t card_addr; 2580 bus_size_t size; 2581 struct pcmcia_mem_handle *pcmhp; 2582 bus_addr_t *offsetp; 2583 int *windowp; 2584 { 2585 struct pcic_handle *ph = (struct pcic_handle *)pch; 2586 bus_addr_t busaddr; 2587 long card_offset; 2588 int win; 2589 2590 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2591 if ((ph->memalloc & (1 << win)) == 0) { 2592 ph->memalloc |= (1 << win); 2593 break; 2594 } 2595 } 2596 2597 if (win == PCIC_MEM_WINS) { 2598 return 1; 2599 } 2600 2601 *windowp = win; 2602 2603 /* XXX this is pretty gross */ 2604 2605 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2606 panic("pccbb_pcmcia_mem_map memt is bogus"); 2607 } 2608 2609 busaddr = pcmhp->addr; 2610 2611 /* 2612 * compute the address offset to the pcmcia address space for the 2613 * pcic. this is intentionally signed. The masks and shifts below 2614 * will cause TRT to happen in the pcic registers. Deal with making 2615 * sure the address is aligned, and return the alignment offset. 2616 */ 2617 2618 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2619 card_addr -= *offsetp; 2620 2621 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2622 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2623 (u_long) card_addr)); 2624 2625 /* 2626 * include the offset in the size, and decrement size by one, since 2627 * the hw wants start/stop 2628 */ 2629 size += *offsetp - 1; 2630 2631 card_offset = (((long)card_addr) - ((long)busaddr)); 2632 2633 ph->mem[win].addr = busaddr; 2634 ph->mem[win].size = size; 2635 ph->mem[win].offset = card_offset; 2636 ph->mem[win].kind = kind; 2637 2638 pccbb_pcmcia_do_mem_map(ph, win); 2639 2640 return 0; 2641 } 2642 2643 /* 2644 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2645 * int window) 2646 * 2647 * This function unmaps memory space which mapped by the function 2648 * pccbb_pcmcia_mem_map(). 2649 */ 2650 STATIC void 2651 pccbb_pcmcia_mem_unmap(pch, window) 2652 pcmcia_chipset_handle_t pch; 2653 int window; 2654 { 2655 struct pcic_handle *ph = (struct pcic_handle *)pch; 2656 int reg; 2657 2658 if (window >= PCIC_MEM_WINS) { 2659 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2660 } 2661 2662 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2663 reg &= ~(1 << window); 2664 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2665 2666 ph->memalloc &= ~(1 << window); 2667 } 2668 2669 #if defined PCCBB_PCMCIA_POLL 2670 struct pccbb_poll_str { 2671 void *arg; 2672 int (*func) __P((void *)); 2673 int level; 2674 struct pcic_handle *ph; 2675 int count; 2676 int num; 2677 struct callout poll_ch; 2678 }; 2679 2680 static struct pccbb_poll_str pccbb_poll[10]; 2681 static int pccbb_poll_n = 0; 2682 2683 static void pccbb_pcmcia_poll __P((void *arg)); 2684 2685 static void 2686 pccbb_pcmcia_poll(arg) 2687 void *arg; 2688 { 2689 struct pccbb_poll_str *poll = arg; 2690 struct pcic_handle *ph = poll->ph; 2691 struct pccbb_softc *sc = ph->sc; 2692 int s; 2693 u_int32_t spsr; /* socket present-state reg */ 2694 2695 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2696 switch (poll->level) { 2697 case IPL_NET: 2698 s = splnet(); 2699 break; 2700 case IPL_BIO: 2701 s = splbio(); 2702 break; 2703 case IPL_TTY: /* fallthrough */ 2704 default: 2705 s = spltty(); 2706 break; 2707 } 2708 2709 spsr = 2710 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2711 CB_SOCKET_STAT); 2712 2713 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2714 if (!(spsr & 0x40)) /* CINT low */ 2715 #else 2716 if (1) 2717 #endif 2718 { 2719 if ((*poll->func) (poll->arg) > 0) { 2720 ++poll->count; 2721 // printf("intr: reported from poller, 0x%x\n", spsr); 2722 #if defined LEVEL2 2723 } else { 2724 printf("intr: miss! 0x%x\n", spsr); 2725 #endif 2726 } 2727 } 2728 splx(s); 2729 } 2730 #endif /* defined CB_PCMCIA_POLL */ 2731 2732 /* 2733 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2734 * struct pcmcia_function *pf, 2735 * int ipl, 2736 * int (*func)(void *), 2737 * void *arg); 2738 * 2739 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2740 */ 2741 STATIC void * 2742 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2743 pcmcia_chipset_handle_t pch; 2744 struct pcmcia_function *pf; 2745 int ipl; 2746 int (*func) __P((void *)); 2747 void *arg; 2748 { 2749 struct pcic_handle *ph = (struct pcic_handle *)pch; 2750 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2751 2752 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2753 /* what should I do? */ 2754 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2755 DPRINTF( 2756 ("%s does not provide edge nor pulse interrupt\n", 2757 sc->sc_dev.dv_xname)); 2758 return NULL; 2759 } 2760 /* 2761 * XXX Noooooo! The interrupt flag must set properly!! 2762 * dumb pcmcia driver!! 2763 */ 2764 } 2765 2766 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2767 } 2768 2769 /* 2770 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2771 * void *ih) 2772 * 2773 * This function disables PC-Card interrupt. 2774 */ 2775 STATIC void 2776 pccbb_pcmcia_intr_disestablish(pch, ih) 2777 pcmcia_chipset_handle_t pch; 2778 void *ih; 2779 { 2780 struct pcic_handle *ph = (struct pcic_handle *)pch; 2781 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2782 2783 pccbb_intr_disestablish(sc, ih); 2784 } 2785 2786 #if rbus 2787 /* 2788 * static int 2789 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2790 * bus_addr_t addr, bus_size_t size, 2791 * bus_addr_t mask, bus_size_t align, 2792 * int flags, bus_addr_t *addrp; 2793 * bus_space_handle_t *bshp) 2794 * 2795 * This function allocates a portion of memory or io space for 2796 * clients. This function is called from CardBus card drivers. 2797 */ 2798 static int 2799 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2800 cardbus_chipset_tag_t ct; 2801 rbus_tag_t rb; 2802 bus_addr_t addr; 2803 bus_size_t size; 2804 bus_addr_t mask; 2805 bus_size_t align; 2806 int flags; 2807 bus_addr_t *addrp; 2808 bus_space_handle_t *bshp; 2809 { 2810 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2811 2812 DPRINTF( 2813 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2814 addr, size, mask, align)); 2815 2816 if (align == 0) { 2817 align = size; 2818 } 2819 2820 if (rb->rb_bt == sc->sc_memt) { 2821 if (align < 16) { 2822 return 1; 2823 } 2824 } else if (rb->rb_bt == sc->sc_iot) { 2825 if (align < 4) { 2826 return 1; 2827 } 2828 /* XXX: hack for avoiding ISA image */ 2829 if (mask < 0x0100) { 2830 mask = 0x3ff; 2831 addr = 0x300; 2832 } 2833 2834 } else { 2835 DPRINTF( 2836 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2837 rb->rb_bt)); 2838 return 1; 2839 /* XXX: panic here? */ 2840 } 2841 2842 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2843 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2844 return 1; 2845 } 2846 2847 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2848 2849 return 0; 2850 } 2851 2852 /* 2853 * static int 2854 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2855 * bus_space_handle_t *bshp, bus_size_t size); 2856 * 2857 * This function is called from CardBus card drivers. 2858 */ 2859 static int 2860 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2861 cardbus_chipset_tag_t ct; 2862 rbus_tag_t rb; 2863 bus_space_handle_t bsh; 2864 bus_size_t size; 2865 { 2866 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2867 bus_space_tag_t bt = rb->rb_bt; 2868 2869 pccbb_close_win(sc, bt, bsh, size); 2870 2871 if (bt == sc->sc_memt) { 2872 } else if (bt == sc->sc_iot) { 2873 } else { 2874 return 1; 2875 /* XXX: panic here? */ 2876 } 2877 2878 return rbus_space_free(rb, bsh, size, NULL); 2879 } 2880 #endif /* rbus */ 2881 2882 #if rbus 2883 2884 static int 2885 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2886 struct pccbb_softc *sc; 2887 bus_space_tag_t bst; 2888 bus_addr_t addr; 2889 bus_size_t size; 2890 bus_space_handle_t bsh; 2891 int flags; 2892 { 2893 struct pccbb_win_chain_head *head; 2894 bus_addr_t align; 2895 2896 head = &sc->sc_iowindow; 2897 align = 0x04; 2898 if (sc->sc_memt == bst) { 2899 head = &sc->sc_memwindow; 2900 align = 0x1000; 2901 DPRINTF(("using memory window, %x %x %x\n\n", 2902 sc->sc_iot, sc->sc_memt, bst)); 2903 } 2904 2905 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2906 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2907 sc->sc_dev.dv_xname, 2908 (head == &sc->sc_memwindow) ? "mem" : "io"); 2909 } 2910 pccbb_winset(align, sc, bst); 2911 2912 return 0; 2913 } 2914 2915 static int 2916 pccbb_close_win(sc, bst, bsh, size) 2917 struct pccbb_softc *sc; 2918 bus_space_tag_t bst; 2919 bus_space_handle_t bsh; 2920 bus_size_t size; 2921 { 2922 struct pccbb_win_chain_head *head; 2923 bus_addr_t align; 2924 2925 head = &sc->sc_iowindow; 2926 align = 0x04; 2927 if (sc->sc_memt == bst) { 2928 head = &sc->sc_memwindow; 2929 align = 0x1000; 2930 } 2931 2932 if (pccbb_winlist_delete(head, bsh, size)) { 2933 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2934 sc->sc_dev.dv_xname, 2935 (head == &sc->sc_memwindow) ? "mem" : "io"); 2936 } 2937 pccbb_winset(align, sc, bst); 2938 2939 return 0; 2940 } 2941 2942 static int 2943 pccbb_winlist_insert(head, start, size, bsh, flags) 2944 struct pccbb_win_chain_head *head; 2945 bus_addr_t start; 2946 bus_size_t size; 2947 bus_space_handle_t bsh; 2948 int flags; 2949 { 2950 struct pccbb_win_chain *chainp, *elem; 2951 2952 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2953 M_NOWAIT)) == NULL) 2954 return (1); /* fail */ 2955 2956 elem->wc_start = start; 2957 elem->wc_end = start + (size - 1); 2958 elem->wc_handle = bsh; 2959 elem->wc_flags = flags; 2960 2961 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2962 chainp = TAILQ_NEXT(chainp, wc_list)) { 2963 if (chainp->wc_end < start) 2964 continue; 2965 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2966 return (0); 2967 } 2968 2969 TAILQ_INSERT_TAIL(head, elem, wc_list); 2970 return (0); 2971 } 2972 2973 static int 2974 pccbb_winlist_delete(head, bsh, size) 2975 struct pccbb_win_chain_head *head; 2976 bus_space_handle_t bsh; 2977 bus_size_t size; 2978 { 2979 struct pccbb_win_chain *chainp; 2980 2981 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2982 chainp = TAILQ_NEXT(chainp, wc_list)) { 2983 if (chainp->wc_handle != bsh) 2984 continue; 2985 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2986 printf("pccbb_winlist_delete: window 0x%lx size " 2987 "inconsistent: 0x%lx, 0x%lx\n", 2988 chainp->wc_start, 2989 chainp->wc_end - chainp->wc_start, 2990 size - 1); 2991 return 1; 2992 } 2993 2994 TAILQ_REMOVE(head, chainp, wc_list); 2995 free(chainp, M_DEVBUF); 2996 2997 return 0; 2998 } 2999 3000 return 1; /* fail: no candidate to remove */ 3001 } 3002 3003 static void 3004 pccbb_winset(align, sc, bst) 3005 bus_addr_t align; 3006 struct pccbb_softc *sc; 3007 bus_space_tag_t bst; 3008 { 3009 pci_chipset_tag_t pc; 3010 pcitag_t tag; 3011 bus_addr_t mask = ~(align - 1); 3012 struct { 3013 cardbusreg_t win_start; 3014 cardbusreg_t win_limit; 3015 int win_flags; 3016 } win[2]; 3017 struct pccbb_win_chain *chainp; 3018 int offs; 3019 3020 win[0].win_start = 0xffffffff; 3021 win[0].win_limit = 0; 3022 win[1].win_start = 0xffffffff; 3023 win[1].win_limit = 0; 3024 3025 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3026 offs = 0x2c; 3027 if (sc->sc_memt == bst) { 3028 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3029 offs = 0x1c; 3030 } 3031 3032 if (chainp != NULL) { 3033 win[0].win_start = chainp->wc_start & mask; 3034 win[0].win_limit = chainp->wc_end & mask; 3035 win[0].win_flags = chainp->wc_flags; 3036 chainp = TAILQ_NEXT(chainp, wc_list); 3037 } 3038 3039 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3040 if (win[1].win_start == 0xffffffff) { 3041 /* window 1 is not used */ 3042 if ((win[0].win_flags == chainp->wc_flags) && 3043 (win[0].win_limit + align >= 3044 (chainp->wc_start & mask))) { 3045 /* concatenate */ 3046 win[0].win_limit = chainp->wc_end & mask; 3047 } else { 3048 /* make new window */ 3049 win[1].win_start = chainp->wc_start & mask; 3050 win[1].win_limit = chainp->wc_end & mask; 3051 win[1].win_flags = chainp->wc_flags; 3052 } 3053 continue; 3054 } 3055 3056 /* Both windows are engaged. */ 3057 if (win[0].win_flags == win[1].win_flags) { 3058 /* same flags */ 3059 if (win[0].win_flags == chainp->wc_flags) { 3060 if (win[1].win_start - (win[0].win_limit + 3061 align) < 3062 (chainp->wc_start & mask) - 3063 ((chainp->wc_end & mask) + align)) { 3064 /* 3065 * merge window 0 and 1, and set win1 3066 * to chainp 3067 */ 3068 win[0].win_limit = win[1].win_limit; 3069 win[1].win_start = 3070 chainp->wc_start & mask; 3071 win[1].win_limit = 3072 chainp->wc_end & mask; 3073 } else { 3074 win[1].win_limit = 3075 chainp->wc_end & mask; 3076 } 3077 } else { 3078 /* different flags */ 3079 3080 /* concatenate win0 and win1 */ 3081 win[0].win_limit = win[1].win_limit; 3082 /* allocate win[1] to new space */ 3083 win[1].win_start = chainp->wc_start & mask; 3084 win[1].win_limit = chainp->wc_end & mask; 3085 win[1].win_flags = chainp->wc_flags; 3086 } 3087 } else { 3088 /* the flags of win[0] and win[1] is different */ 3089 if (win[0].win_flags == chainp->wc_flags) { 3090 win[0].win_limit = chainp->wc_end & mask; 3091 /* 3092 * XXX this creates overlapping windows, so 3093 * what should the poor bridge do if one is 3094 * cachable, and the other is not? 3095 */ 3096 printf("%s: overlapping windows\n", 3097 sc->sc_dev.dv_xname); 3098 } else { 3099 win[1].win_limit = chainp->wc_end & mask; 3100 } 3101 } 3102 } 3103 3104 pc = sc->sc_pc; 3105 tag = sc->sc_tag; 3106 pci_conf_write(pc, tag, offs, win[0].win_start); 3107 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3108 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3109 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3110 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3111 pci_conf_read(pc, tag, offs), 3112 pci_conf_read(pc, tag, offs + 4) + align, 3113 pci_conf_read(pc, tag, offs + 8), 3114 pci_conf_read(pc, tag, offs + 12) + align)); 3115 3116 if (bst == sc->sc_memt) { 3117 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3118 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3119 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3120 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3121 } 3122 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3123 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3124 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3125 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3126 } 3127 } 3128 } 3129 3130 #endif /* rbus */ 3131 3132 static void 3133 pccbb_powerhook(why, arg) 3134 int why; 3135 void *arg; 3136 { 3137 struct pccbb_softc *sc = arg; 3138 u_int32_t reg; 3139 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3140 bus_space_handle_t base_memh = sc->sc_base_memh; 3141 3142 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3143 3144 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3145 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3146 if (sc->sc_pil_intr_enable) { 3147 (void)pccbbintr_function(sc); 3148 } 3149 sc->sc_pil_intr_enable = 0; 3150 3151 /* ToDo: deactivate or suspend child devices */ 3152 3153 } 3154 3155 if (why == PWR_RESUME) { 3156 /* CSC Interrupt: Card detect interrupt on */ 3157 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3158 /* Card detect intr is turned on. */ 3159 reg |= CB_SOCKET_MASK_CD; 3160 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3161 /* reset interrupt */ 3162 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3163 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3164 3165 /* 3166 * check for card insertion or removal during suspend period. 3167 * XXX: the code can't cope with card swap (remove then 3168 * insert). how can we detect such situation? 3169 */ 3170 (void)pccbbintr(sc); 3171 3172 sc->sc_pil_intr_enable = 1; 3173 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3174 3175 /* ToDo: activate or wakeup child devices */ 3176 } 3177 } 3178
Indexes created Thu Sep 25 16:09:42 GMT 2025