pccbb.c revision 1.42
1 /* $NetBSD: pccbb.c,v 1.42 2000/06/16 23:41:35 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 93 void pccbbattach __P((struct device *, struct device *, void *)); 94 int pccbbintr __P((void *)); 95 static void pci113x_insert __P((void *)); 96 static int pccbbintr_function __P((struct pccbb_softc *)); 97 98 static int pccbb_detect_card __P((struct pccbb_softc *)); 99 100 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 101 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 102 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 103 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 104 105 STATIC int cb_reset __P((struct pccbb_softc *)); 106 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 107 STATIC int cbbprint __P((void *, const char *)); 108 109 static int cb_chipset __P((u_int32_t, int *)); 110 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 111 struct pcmciabus_attach_args *)); 112 #if 0 113 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 114 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 115 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 116 #endif 117 118 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 119 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 120 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 121 #if !rbus 122 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 123 u_int32_t)); 124 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 125 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 126 u_int32_t)); 127 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 128 #endif /* !rbus */ 129 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 130 int level, int (*ih) (void *), void *sc)); 131 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 132 133 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 static void pccbb_powerhook __P((int, void *)); 171 172 /* bus-space allocation and deallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 178 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t)); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 187 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t)); 189 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int)); 191 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 192 bus_space_handle_t, bus_size_t)); 193 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t)); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback __P((struct device *)); 201 202 #if defined SHOW_REGS 203 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 204 bus_space_tag_t memt, bus_space_handle_t memh)); 205 #endif 206 207 struct cfattach cbb_pci_ca = { 208 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 209 }; 210 211 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 212 pccbb_pcmcia_mem_alloc, 213 pccbb_pcmcia_mem_free, 214 pccbb_pcmcia_mem_map, 215 pccbb_pcmcia_mem_unmap, 216 pccbb_pcmcia_io_alloc, 217 pccbb_pcmcia_io_free, 218 pccbb_pcmcia_io_map, 219 pccbb_pcmcia_io_unmap, 220 pccbb_pcmcia_intr_establish, 221 pccbb_pcmcia_intr_disestablish, 222 pccbb_pcmcia_socket_enable, 223 pccbb_pcmcia_socket_disable, 224 pccbb_pcmcia_card_detect 225 }; 226 227 #if rbus 228 static struct cardbus_functions pccbb_funcs = { 229 pccbb_rbus_cb_space_alloc, 230 pccbb_rbus_cb_space_free, 231 pccbb_cb_intr_establish, 232 pccbb_cb_intr_disestablish, 233 pccbb_ctrl, 234 pccbb_power, 235 pccbb_make_tag, 236 pccbb_free_tag, 237 pccbb_conf_read, 238 pccbb_conf_write, 239 }; 240 #else 241 static struct cardbus_functions pccbb_funcs = { 242 pccbb_ctrl, 243 pccbb_power, 244 pccbb_mem_open, 245 pccbb_mem_close, 246 pccbb_io_open, 247 pccbb_io_close, 248 pccbb_cb_intr_establish, 249 pccbb_cb_intr_disestablish, 250 pccbb_make_tag, 251 pccbb_conf_read, 252 pccbb_conf_write, 253 }; 254 #endif 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 struct cfdata *match; 260 void *aux; 261 { 262 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 263 264 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 265 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 266 PCI_INTERFACE(pa->pa_class) == 0) { 267 return 1; 268 } 269 270 return 0; 271 } 272 273 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 274 | ((prod) << PCI_PRODUCT_SHIFT)) 275 276 struct yenta_chipinfo { 277 pcireg_t yc_id; /* vendor tag | product tag */ 278 int yc_chiptype; 279 int yc_flags; 280 } yc_chipsets[] = { 281 /* Texas Instruments chips */ 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 307 /* Ricoh chips */ 308 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 309 PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 311 PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 313 PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 315 PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 319 PCCBB_PCMCIA_MEM_32}, 320 321 /* Toshiba products */ 322 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 323 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 325 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 327 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 329 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 330 331 /* Cirrus Logic products */ 332 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 333 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 335 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 336 337 /* sentinel, or Generic chip */ 338 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 339 }; 340 341 static int 342 cb_chipset(pci_id, flagp) 343 u_int32_t pci_id; 344 int *flagp; 345 { 346 struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return (yc->yc_chiptype); 358 } 359 360 static void 361 pccbb_shutdown(void *arg) 362 { 363 struct pccbb_softc *sc = arg; 364 pcireg_t command; 365 366 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 367 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 368 0); 369 370 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 371 372 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 373 PCI_COMMAND_MASTER_ENABLE); 374 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 375 376 } 377 378 void 379 pccbbattach(parent, self, aux) 380 struct device *parent; 381 struct device *self; 382 void *aux; 383 { 384 struct pccbb_softc *sc = (void *)self; 385 struct pci_attach_args *pa = aux; 386 pci_chipset_tag_t pc = pa->pa_pc; 387 pcireg_t sock_base, busreg; 388 bus_addr_t sockbase; 389 char devinfo[256]; 390 int flags; 391 392 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 393 394 pci_devinfo(pa->pa_id, 0, 0, devinfo); 395 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 396 #ifdef CBB_DEBUG 397 printf(" (chipflags %x)", flags); 398 #endif 399 printf("\n"); 400 401 TAILQ_INIT(&sc->sc_memwindow); 402 TAILQ_INIT(&sc->sc_iowindow); 403 404 #if rbus 405 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 406 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 407 #endif /* rbus */ 408 409 sc->sc_base_memh = 0; 410 411 /* 412 * MAP socket registers and ExCA registers on memory-space 413 * When no valid address is set on socket base registers (on pci 414 * config space), get it not polite way. 415 */ 416 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 417 418 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 419 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 420 /* The address must be valid. */ 421 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 422 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 423 printf("%s: can't map socket base address 0x%x\n", 424 sc->sc_dev.dv_xname, sock_base); 425 /* 426 * I think it's funny: socket base registers must be 427 * mapped on memory space, but ... 428 */ 429 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 430 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 431 NULL)) { 432 printf("%s: can't map socket base address" 433 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 434 sockbase); 435 /* give up... allocate reg space via rbus. */ 436 sc->sc_base_memh = 0; 437 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 438 } 439 } else { 440 DPRINTF(("%s: socket base address 0x%lx\n", 441 sc->sc_dev.dv_xname, sockbase)); 442 } 443 } 444 445 sc->sc_mem_start = 0; /* XXX */ 446 sc->sc_mem_end = 0xffffffff; /* XXX */ 447 448 /* 449 * When interrupt isn't routed correctly, give up probing cbb and do 450 * not kill pcic-compatible port. 451 */ 452 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 453 printf("%s: NOT USED because of unconfigured interrupt\n", 454 sc->sc_dev.dv_xname); 455 return; 456 } 457 458 /* 459 * When bus number isn't set correctly, give up using 32-bit CardBus 460 * mode. 461 */ 462 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 463 #if notyet 464 if (((busreg >> 8) & 0xff) == 0) { 465 printf("%s: CardBus support disabled because of unconfigured bus number\n", 466 sc->sc_dev.dv_xname); 467 flags |= PCCBB_PCMCIA_16BITONLY; 468 } 469 #endif 470 471 /* pccbb_machdep.c end */ 472 473 #if defined CBB_DEBUG 474 { 475 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 476 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 477 intrname[pa->pa_intrpin], pa->pa_intrline); 478 } 479 #endif 480 481 /* setup softc */ 482 sc->sc_pc = pc; 483 sc->sc_iot = pa->pa_iot; 484 sc->sc_memt = pa->pa_memt; 485 sc->sc_dmat = pa->pa_dmat; 486 sc->sc_tag = pa->pa_tag; 487 sc->sc_function = pa->pa_function; 488 489 sc->sc_intrline = pa->pa_intrline; 490 sc->sc_intrtag = pa->pa_intrtag; 491 sc->sc_intrpin = pa->pa_intrpin; 492 493 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 494 495 shutdownhook_establish(pccbb_shutdown, sc); 496 497 config_defer(self, pccbb_pci_callback); 498 } 499 500 501 502 503 /* 504 * static void pccbb_pci_callback(struct device *self) 505 * 506 * The actual attach routine: get memory space for YENTA register 507 * space, setup YENTA register and route interrupt. 508 * 509 * This function should be deferred because this device may obtain 510 * memory space dynamically. This function must avoid obtaining 511 * memory area which has already kept for another device. Also, 512 * this function MUST be done before ISA attach process because this 513 * function kills pcic compatible port used by ISA pcic. 514 */ 515 static void 516 pccbb_pci_callback(self) 517 struct device *self; 518 { 519 struct pccbb_softc *sc = (void *)self; 520 pci_chipset_tag_t pc = sc->sc_pc; 521 bus_space_tag_t base_memt; 522 bus_space_handle_t base_memh; 523 u_int32_t maskreg; 524 pci_intr_handle_t ih; 525 const char *intrstr = NULL; 526 bus_addr_t sockbase; 527 struct cbslot_attach_args cba; 528 struct pcmciabus_attach_args paa; 529 struct cardslot_attach_args caa; 530 struct cardslot_softc *csc; 531 532 if (0 == sc->sc_base_memh) { 533 /* The socket registers aren't mapped correctly. */ 534 #if rbus 535 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 536 (sc->sc_chipset == CB_RX5C47X 537 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 538 0, &sockbase, &sc->sc_base_memh)) { 539 return; 540 } 541 sc->sc_base_memt = sc->sc_memt; 542 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 543 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 544 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 545 PCI_SOCKBASE))); 546 #else 547 sc->sc_base_memt = sc->sc_memt; 548 #if !defined CBB_PCI_BASE 549 #define CBB_PCI_BASE 0x20000000 550 #endif 551 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 552 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 553 /* cannot allocate memory space */ 554 return; 555 } 556 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 557 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 558 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 559 sc->sc_tag, PCI_SOCKBASE))); 560 #endif 561 } 562 563 /* bus bridge initialization */ 564 pccbb_chipinit(sc); 565 566 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 567 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 568 569 /* CSC Interrupt: Card detect interrupt on */ 570 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 571 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 572 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 573 /* reset interrupt */ 574 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 575 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 576 577 /* clear data structure for child device interrupt handlers */ 578 sc->sc_pil = NULL; 579 sc->sc_pil_intr_enable = 1; 580 581 /* Map and establish the interrupt. */ 582 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 583 sc->sc_intrline, &ih)) { 584 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 585 return; 586 } 587 intrstr = pci_intr_string(pc, ih); 588 589 /* 590 * XXX pccbbintr should be called under the priority lower 591 * than any other hard interrputs. 592 */ 593 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 594 595 if (sc->sc_ih == NULL) { 596 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 597 if (intrstr != NULL) { 598 printf(" at %s", intrstr); 599 } 600 printf("\n"); 601 return; 602 } 603 604 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 605 powerhook_establish(pccbb_powerhook, sc); 606 607 { 608 u_int32_t sockstat = 609 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 610 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 611 sc->sc_flags |= CBB_CARDEXIST; 612 } 613 } 614 615 /* 616 * attach cardbus 617 */ 618 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 619 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 620 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 621 622 /* initialize cbslot_attach */ 623 cba.cba_busname = "cardbus"; 624 cba.cba_iot = sc->sc_iot; 625 cba.cba_memt = sc->sc_memt; 626 cba.cba_dmat = sc->sc_dmat; 627 cba.cba_bus = (busreg >> 8) & 0x0ff; 628 cba.cba_cc = (void *)sc; 629 cba.cba_cf = &pccbb_funcs; 630 cba.cba_intrline = sc->sc_intrline; 631 632 #if rbus 633 cba.cba_rbus_iot = sc->sc_rbus_iot; 634 cba.cba_rbus_memt = sc->sc_rbus_memt; 635 #endif 636 637 cba.cba_cacheline = PCI_CACHELINE(bhlc); 638 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 639 640 printf("%s: cacheline 0x%x lattimer 0x%x\n", 641 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 642 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 643 busreg); 644 #if defined SHOW_REGS 645 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 646 sc->sc_base_memh); 647 #endif 648 } 649 650 pccbb_pcmcia_attach_setup(sc, &paa); 651 caa.caa_cb_attach = NULL; 652 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 653 caa.caa_cb_attach = &cba; 654 } 655 caa.caa_16_attach = &paa; 656 caa.caa_ph = &sc->sc_pcmcia_h; 657 658 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 659 DPRINTF(("pccbbattach: found cardslot\n")); 660 sc->sc_csc = csc; 661 } 662 663 return; 664 } 665 666 667 668 669 670 /* 671 * static void pccbb_chipinit(struct pccbb_softc *sc) 672 * 673 * This function initialize YENTA chip registers listed below: 674 * 1) PCI command reg, 675 * 2) PCI and CardBus latency timer, 676 * 3) disable legacy (PCIC-compatible) io, 677 * 4) route PCI interrupt, 678 * 5) close all memory and io windows. 679 */ 680 static void 681 pccbb_chipinit(sc) 682 struct pccbb_softc *sc; 683 { 684 pci_chipset_tag_t pc = sc->sc_pc; 685 pcitag_t tag = sc->sc_tag; 686 pcireg_t reg; 687 688 /* 689 * Set PCI command reg. 690 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 691 */ 692 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 693 /* I believe it is harmless. */ 694 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 695 PCI_COMMAND_MASTER_ENABLE); 696 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 697 698 /* 699 * Set CardBus latency timer. 700 */ 701 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 702 if (PCI_CB_LATENCY(reg) < 0x20) { 703 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 704 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 705 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 706 } 707 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 708 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 709 710 /* 711 * Set PCI latency timer. 712 */ 713 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 714 if (PCI_LATTIMER(reg) < 0x10) { 715 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 716 reg |= (0x10 << PCI_LATTIMER_SHIFT); 717 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 718 } 719 DPRINTF(("PCI latency timer 0x%x (%x)\n", 720 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 721 722 /* Disable legacy register mapping. */ 723 switch (sc->sc_chipset) { 724 case CB_RX5C46X: /* fallthrough */ 725 #if 0 726 case CB_RX5C47X: 727 #endif 728 /* 729 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 730 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 731 * CardBus bridges have special bits on Bridge control reg (addr 732 * 0x3e on PCI config space). 733 */ 734 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 735 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 736 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 737 break; 738 739 default: 740 /* XXX I don't know proper way to kill legacy I/O. */ 741 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 742 break; 743 } 744 745 /* Route functional interrupts to PCI. */ 746 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 747 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 748 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 749 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 750 751 switch (sc->sc_chipset) { 752 case CB_TI113X: 753 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 754 /* This bit is shared, but may read as 0 on some chips, so set 755 it explicitly on both functions. */ 756 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 757 /* CSC intr enable */ 758 reg |= PCI113X_CBCTRL_PCI_CSC; 759 /* functional intr prohibit */ 760 reg &= ~PCI113X_CBCTRL_PCI_INTR; 761 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 762 break; 763 764 case CB_TOPIC95B: 765 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 766 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 767 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 768 769 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 770 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 771 sc->sc_dev.dv_xname, reg)); 772 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 773 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 774 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 775 DPRINTF(("0x%x\n", reg)); 776 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 777 break; 778 } 779 780 /* Close all memory and I/O windows. */ 781 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 782 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 783 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 784 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 785 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 786 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 787 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 788 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 789 } 790 791 792 793 794 /* 795 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 796 * struct pcmciabus_attach_args *paa) 797 * 798 * This function attaches 16-bit PCcard bus. 799 */ 800 STATIC void 801 pccbb_pcmcia_attach_setup(sc, paa) 802 struct pccbb_softc *sc; 803 struct pcmciabus_attach_args *paa; 804 { 805 struct pcic_handle *ph = &sc->sc_pcmcia_h; 806 #if rbus 807 rbus_tag_t rb; 808 #endif 809 810 /* initialize pcmcia part in pccbb_softc */ 811 ph->ph_parent = (struct device *)sc; 812 ph->sock = sc->sc_function; 813 ph->flags = 0; 814 ph->shutdown = 0; 815 ph->ih_irq = sc->sc_intrline; 816 ph->ph_bus_t = sc->sc_base_memt; 817 ph->ph_bus_h = sc->sc_base_memh; 818 ph->ph_read = pccbb_pcmcia_read; 819 ph->ph_write = pccbb_pcmcia_write; 820 sc->sc_pct = &pccbb_pcmcia_funcs; 821 822 /* 823 * We need to do a few things here: 824 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 825 * setting the IRQ numbers to 0. 826 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 827 * routing of CSC interrupts (e.g. card removal) to PCI while in 828 * PCMCIA mode. We just leave this set all the time. 829 * 3) Enable card insertion/removal interrupts in case the chip also 830 * needs that while in PCMCIA mode. 831 * 4) Clear any pending CSC interrupt. 832 */ 833 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 834 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 835 Pcic_read(ph, PCIC_CSC); 836 837 /* initialize pcmcia bus attachment */ 838 paa->paa_busname = "pcmcia"; 839 paa->pct = sc->sc_pct; 840 paa->pch = ph; 841 paa->iobase = 0; /* I don't use them */ 842 paa->iosize = 0; 843 #if rbus 844 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 845 paa->iobase = rb->rb_start + rb->rb_offset; 846 paa->iosize = rb->rb_end - rb->rb_start; 847 #endif 848 849 return; 850 } 851 852 #if 0 853 STATIC void 854 pccbb_pcmcia_attach_card(ph) 855 struct pcic_handle *ph; 856 { 857 if (ph->flags & PCIC_FLAG_CARDP) { 858 panic("pccbb_pcmcia_attach_card: already attached"); 859 } 860 861 /* call the MI attach function */ 862 pcmcia_card_attach(ph->pcmcia); 863 864 ph->flags |= PCIC_FLAG_CARDP; 865 } 866 867 STATIC void 868 pccbb_pcmcia_detach_card(ph, flags) 869 struct pcic_handle *ph; 870 int flags; 871 { 872 if (!(ph->flags & PCIC_FLAG_CARDP)) { 873 panic("pccbb_pcmcia_detach_card: already detached"); 874 } 875 876 ph->flags &= ~PCIC_FLAG_CARDP; 877 878 /* call the MI detach function */ 879 pcmcia_card_detach(ph->pcmcia, flags); 880 } 881 #endif 882 883 /* 884 * int pccbbintr(arg) 885 * void *arg; 886 * This routine handles the interrupt from Yenta PCI-CardBus bridge 887 * itself. 888 */ 889 int 890 pccbbintr(arg) 891 void *arg; 892 { 893 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 894 u_int32_t sockevent, sockstate; 895 bus_space_tag_t memt = sc->sc_base_memt; 896 bus_space_handle_t memh = sc->sc_base_memh; 897 struct pcic_handle *ph = &sc->sc_pcmcia_h; 898 899 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 900 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 901 Pcic_read(ph, PCIC_CSC); 902 903 if (sockevent == 0) { 904 /* This intr is not for me: it may be for my child devices. */ 905 if (sc->sc_pil_intr_enable) { 906 return pccbbintr_function(sc); 907 } else { 908 return 0; 909 } 910 } 911 912 if (sockevent & CB_SOCKET_EVENT_CD) { 913 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 914 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 915 /* A card should be removed. */ 916 if (sc->sc_flags & CBB_CARDEXIST) { 917 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 918 sockevent)); 919 DPRINTF((" card removed, 0x%08x\n", sockstate)); 920 sc->sc_flags &= ~CBB_CARDEXIST; 921 if (sc->sc_csc->sc_status & 922 CARDSLOT_STATUS_CARD_16) { 923 #if 0 924 struct pcic_handle *ph = 925 &sc->sc_pcmcia_h; 926 927 pcmcia_card_deactivate(ph->pcmcia); 928 pccbb_pcmcia_socket_disable(ph); 929 pccbb_pcmcia_detach_card(ph, 930 DETACH_FORCE); 931 #endif 932 cardslot_event_throw(sc->sc_csc, 933 CARDSLOT_EVENT_REMOVAL_16); 934 } else if (sc->sc_csc->sc_status & 935 CARDSLOT_STATUS_CARD_CB) { 936 /* Cardbus intr removed */ 937 cardslot_event_throw(sc->sc_csc, 938 CARDSLOT_EVENT_REMOVAL_CB); 939 } 940 } 941 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 942 /* 943 * The pccbbintr may called from powerdown hook when 944 * the system resumed, to detect the card 945 * insertion/removal during suspension. 946 */ 947 (sc->sc_flags & CBB_CARDEXIST) == 0) { 948 if (sc->sc_flags & CBB_INSERTING) { 949 callout_stop(&sc->sc_insert_ch); 950 } 951 callout_reset(&sc->sc_insert_ch, hz / 10, 952 pci113x_insert, sc); 953 sc->sc_flags |= CBB_INSERTING; 954 } 955 } 956 957 return (1); 958 } 959 960 /* 961 * static int pccbbintr_function(struct pccbb_softc *sc) 962 * 963 * This function calls each interrupt handler registered at the 964 * bridge. The interrupt handlers are called in registered order. 965 */ 966 static int 967 pccbbintr_function(sc) 968 struct pccbb_softc *sc; 969 { 970 int retval = 0, val; 971 struct pccbb_intrhand_list *pil; 972 int s, splchanged; 973 974 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 975 /* 976 * XXX priority change. gross. I use if-else 977 * sentense instead of switch-case sentense because of 978 * avoiding duplicate case value error. More than one 979 * IPL_XXX use same value. It depends on 980 * implimentation. 981 */ 982 splchanged = 1; 983 if (pil->pil_level == IPL_SERIAL) { 984 s = splserial(); 985 } else if (pil->pil_level == IPL_HIGH) { 986 s = splhigh(); 987 } else if (pil->pil_level == IPL_CLOCK) { 988 s = splclock(); 989 } else if (pil->pil_level == IPL_AUDIO) { 990 s = splaudio(); 991 } else if (pil->pil_level == IPL_IMP) { 992 s = splimp(); 993 } else if (pil->pil_level == IPL_TTY) { 994 s = spltty(); 995 } else if (pil->pil_level == IPL_SOFTSERIAL) { 996 s = splsoftserial(); 997 } else if (pil->pil_level == IPL_NET) { 998 s = splnet(); 999 } else { 1000 splchanged = 0; 1001 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1002 } 1003 1004 val = (*pil->pil_func)(pil->pil_arg); 1005 1006 if (splchanged != 0) { 1007 splx(s); 1008 } 1009 1010 retval = retval == 1 ? 1 : 1011 retval == 0 ? val : val != 0 ? val : retval; 1012 } 1013 1014 return retval; 1015 } 1016 1017 static void 1018 pci113x_insert(arg) 1019 void *arg; 1020 { 1021 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1022 u_int32_t sockevent, sockstate; 1023 1024 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1025 CB_SOCKET_EVENT); 1026 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1027 CB_SOCKET_STAT); 1028 1029 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1030 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1031 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1032 sc->sc_flags |= CBB_CARDEXIST; 1033 /* call pccard interrupt handler here */ 1034 if (sockstate & CB_SOCKET_STAT_16BIT) { 1035 /* 16-bit card found */ 1036 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1037 cardslot_event_throw(sc->sc_csc, 1038 CARDSLOT_EVENT_INSERTION_16); 1039 } else if (sockstate & CB_SOCKET_STAT_CB) { 1040 /* cardbus card found */ 1041 /* cardbus_attach_card(sc->sc_csc); */ 1042 cardslot_event_throw(sc->sc_csc, 1043 CARDSLOT_EVENT_INSERTION_CB); 1044 } else { 1045 /* who are you? */ 1046 } 1047 } else { 1048 callout_reset(&sc->sc_insert_ch, hz / 10, 1049 pci113x_insert, sc); 1050 } 1051 } 1052 1053 #define PCCBB_PCMCIA_OFFSET 0x800 1054 static u_int8_t 1055 pccbb_pcmcia_read(ph, reg) 1056 struct pcic_handle *ph; 1057 int reg; 1058 { 1059 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1060 PCCBB_PCMCIA_OFFSET + reg); 1061 } 1062 1063 static void 1064 pccbb_pcmcia_write(ph, reg, val) 1065 struct pcic_handle *ph; 1066 int reg; 1067 u_int8_t val; 1068 { 1069 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1070 val); 1071 } 1072 1073 /* 1074 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1075 */ 1076 STATIC int 1077 pccbb_ctrl(ct, command) 1078 cardbus_chipset_tag_t ct; 1079 int command; 1080 { 1081 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1082 1083 switch (command) { 1084 case CARDBUS_CD: 1085 if (2 == pccbb_detect_card(sc)) { 1086 int retval = 0; 1087 int status = cb_detect_voltage(sc); 1088 if (PCCARD_VCC_5V & status) { 1089 retval |= CARDBUS_5V_CARD; 1090 } 1091 if (PCCARD_VCC_3V & status) { 1092 retval |= CARDBUS_3V_CARD; 1093 } 1094 if (PCCARD_VCC_XV & status) { 1095 retval |= CARDBUS_XV_CARD; 1096 } 1097 if (PCCARD_VCC_YV & status) { 1098 retval |= CARDBUS_YV_CARD; 1099 } 1100 return retval; 1101 } else { 1102 return 0; 1103 } 1104 break; 1105 case CARDBUS_RESET: 1106 return cb_reset(sc); 1107 break; 1108 case CARDBUS_IO_ENABLE: /* fallthrough */ 1109 case CARDBUS_IO_DISABLE: /* fallthrough */ 1110 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1111 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1112 case CARDBUS_BM_ENABLE: /* fallthrough */ 1113 case CARDBUS_BM_DISABLE: /* fallthrough */ 1114 return pccbb_cardenable(sc, command); 1115 break; 1116 } 1117 1118 return 0; 1119 } 1120 1121 /* 1122 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1123 * This function returns true when it succeeds and returns false when 1124 * it fails. 1125 */ 1126 STATIC int 1127 pccbb_power(ct, command) 1128 cardbus_chipset_tag_t ct; 1129 int command; 1130 { 1131 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1132 1133 u_int32_t status, sock_ctrl; 1134 bus_space_tag_t memt = sc->sc_base_memt; 1135 bus_space_handle_t memh = sc->sc_base_memh; 1136 1137 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1138 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1139 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1140 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1141 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1142 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1143 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1144 "UNKNOWN", 1145 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1146 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1147 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1148 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1149 "UNKNOWN", command)); 1150 1151 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1152 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1153 1154 switch (command & CARDBUS_VCCMASK) { 1155 case CARDBUS_VCC_UC: 1156 break; 1157 case CARDBUS_VCC_5V: 1158 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1159 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1160 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1161 } else { 1162 printf("%s: BAD voltage request: no 5 V card\n", 1163 sc->sc_dev.dv_xname); 1164 } 1165 break; 1166 case CARDBUS_VCC_3V: 1167 if (CB_SOCKET_STAT_3VCARD & status) { 1168 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1169 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1170 } else { 1171 printf("%s: BAD voltage request: no 3.3 V card\n", 1172 sc->sc_dev.dv_xname); 1173 } 1174 break; 1175 case CARDBUS_VCC_0V: 1176 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1177 break; 1178 default: 1179 return 0; /* power NEVER changed */ 1180 break; 1181 } 1182 1183 switch (command & CARDBUS_VPPMASK) { 1184 case CARDBUS_VPP_UC: 1185 break; 1186 case CARDBUS_VPP_0V: 1187 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1188 break; 1189 case CARDBUS_VPP_VCC: 1190 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1191 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1192 break; 1193 case CARDBUS_VPP_12V: 1194 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1195 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1196 break; 1197 } 1198 1199 #if 0 1200 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1201 #endif 1202 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1203 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1204 1205 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1206 /* 1207 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1208 * time is 20 ms, some PC-Card bridge requires longer duration. 1209 */ 1210 delay(200 * 1000); 1211 1212 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1213 printf 1214 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1215 sc->sc_dev.dv_xname, sock_ctrl, status); 1216 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1217 (command & CARDBUS_VCCMASK) == 1218 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1219 CARDBUS_VCCMASK) == 1220 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1221 CARDBUS_VCCMASK) == 1222 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1223 CARDBUS_VCCMASK) == 1224 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1225 CARDBUS_VCCMASK) == 1226 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1227 CARDBUS_VCCMASK) == 1228 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1229 (command & CARDBUS_VPPMASK) == 1230 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1231 CARDBUS_VPPMASK) == 1232 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1233 CARDBUS_VPPMASK) == 1234 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1235 CARDBUS_VPPMASK) == 1236 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1237 #if 0 1238 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1239 u_int32_t force = 1240 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1241 /* Reset Bad Vcc request */ 1242 force &= ~CB_SOCKET_FORCE_BADVCC; 1243 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1244 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1245 CB_SOCKET_STAT)); 1246 return 1; 1247 } 1248 #endif 1249 return 0; 1250 } 1251 return 1; /* power changed correctly */ 1252 } 1253 1254 #if defined CB_PCMCIA_POLL 1255 struct cb_poll_str { 1256 void *arg; 1257 int (*func) __P((void *)); 1258 int level; 1259 pccard_chipset_tag_t ct; 1260 int count; 1261 struct callout poll_ch; 1262 }; 1263 1264 static struct cb_poll_str cb_poll[10]; 1265 static int cb_poll_n = 0; 1266 1267 static void cb_pcmcia_poll __P((void *arg)); 1268 1269 static void 1270 cb_pcmcia_poll(arg) 1271 void *arg; 1272 { 1273 struct cb_poll_str *poll = arg; 1274 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1275 struct pccbb_softc *sc = psc->cpc_parent; 1276 int s; 1277 u_int32_t spsr; /* socket present-state reg */ 1278 1279 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1280 switch (poll->level) { 1281 case IPL_NET: 1282 s = splnet(); 1283 break; 1284 case IPL_BIO: 1285 s = splbio(); 1286 break; 1287 case IPL_TTY: /* fallthrough */ 1288 default: 1289 s = spltty(); 1290 break; 1291 } 1292 1293 spsr = 1294 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1295 CB_SOCKET_STAT); 1296 1297 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1298 if (!(spsr & 0x40)) { /* CINT low */ 1299 #else 1300 if (1) { 1301 #endif 1302 if ((*poll->func) (poll->arg) == 1) { 1303 ++poll->count; 1304 printf("intr: reported from poller, 0x%x\n", spsr); 1305 #if defined LEVEL2 1306 } else { 1307 printf("intr: miss! 0x%x\n", spsr); 1308 #endif 1309 } 1310 } 1311 splx(s); 1312 } 1313 #endif /* defined CB_PCMCIA_POLL */ 1314 1315 /* 1316 * static int pccbb_detect_card(struct pccbb_softc *sc) 1317 * return value: 0 if no card exists. 1318 * 1 if 16-bit card exists. 1319 * 2 if cardbus card exists. 1320 */ 1321 static int 1322 pccbb_detect_card(sc) 1323 struct pccbb_softc *sc; 1324 { 1325 bus_space_handle_t base_memh = sc->sc_base_memh; 1326 bus_space_tag_t base_memt = sc->sc_base_memt; 1327 u_int32_t sockstat = 1328 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1329 int retval = 0; 1330 1331 /* CD1 and CD2 asserted */ 1332 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1333 /* card must be present */ 1334 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1335 /* NOTACARD DEASSERTED */ 1336 if (CB_SOCKET_STAT_CB & sockstat) { 1337 /* CardBus mode */ 1338 retval = 2; 1339 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1340 /* 16-bit mode */ 1341 retval = 1; 1342 } 1343 } 1344 } 1345 return retval; 1346 } 1347 1348 /* 1349 * STATIC int cb_reset(struct pccbb_softc *sc) 1350 * This function resets CardBus card. 1351 */ 1352 STATIC int 1353 cb_reset(sc) 1354 struct pccbb_softc *sc; 1355 { 1356 /* 1357 * Reset Assert at least 20 ms 1358 * Some machines request longer duration. 1359 */ 1360 int reset_duration = 1361 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1362 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1363 1364 /* Reset bit Assert (bit 6 at 0x3E) */ 1365 bcr |= CB_BCR_RESET_ENABLE; 1366 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1367 delay(reset_duration); 1368 1369 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1370 /* Reset bit Deassert (bit 6 at 0x3E) */ 1371 bcr &= ~CB_BCR_RESET_ENABLE; 1372 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1373 delay(reset_duration); 1374 } 1375 /* No card found on the slot. Keep Reset. */ 1376 return 1; 1377 } 1378 1379 /* 1380 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1381 * This function detect card Voltage. 1382 */ 1383 STATIC int 1384 cb_detect_voltage(sc) 1385 struct pccbb_softc *sc; 1386 { 1387 u_int32_t psr; /* socket present-state reg */ 1388 bus_space_tag_t iot = sc->sc_base_memt; 1389 bus_space_handle_t ioh = sc->sc_base_memh; 1390 int vol = PCCARD_VCC_UKN; /* set 0 */ 1391 1392 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1393 1394 if (0x400u & psr) { 1395 vol |= PCCARD_VCC_5V; 1396 } 1397 if (0x800u & psr) { 1398 vol |= PCCARD_VCC_3V; 1399 } 1400 1401 return vol; 1402 } 1403 1404 STATIC int 1405 cbbprint(aux, pcic) 1406 void *aux; 1407 const char *pcic; 1408 { 1409 /* 1410 struct cbslot_attach_args *cba = aux; 1411 1412 if (cba->cba_slot >= 0) { 1413 printf(" slot %d", cba->cba_slot); 1414 } 1415 */ 1416 return UNCONF; 1417 } 1418 1419 /* 1420 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1421 * This function enables and disables the card 1422 */ 1423 STATIC int 1424 pccbb_cardenable(sc, function) 1425 struct pccbb_softc *sc; 1426 int function; 1427 { 1428 u_int32_t command = 1429 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1430 1431 DPRINTF(("pccbb_cardenable:")); 1432 switch (function) { 1433 case CARDBUS_IO_ENABLE: 1434 command |= PCI_COMMAND_IO_ENABLE; 1435 break; 1436 case CARDBUS_IO_DISABLE: 1437 command &= ~PCI_COMMAND_IO_ENABLE; 1438 break; 1439 case CARDBUS_MEM_ENABLE: 1440 command |= PCI_COMMAND_MEM_ENABLE; 1441 break; 1442 case CARDBUS_MEM_DISABLE: 1443 command &= ~PCI_COMMAND_MEM_ENABLE; 1444 break; 1445 case CARDBUS_BM_ENABLE: 1446 command |= PCI_COMMAND_MASTER_ENABLE; 1447 break; 1448 case CARDBUS_BM_DISABLE: 1449 command &= ~PCI_COMMAND_MASTER_ENABLE; 1450 break; 1451 default: 1452 return 0; 1453 } 1454 1455 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1456 DPRINTF((" command reg 0x%x\n", command)); 1457 return 1; 1458 } 1459 1460 #if !rbus 1461 /* 1462 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1463 */ 1464 static int 1465 pccbb_io_open(ct, win, start, end) 1466 cardbus_chipset_tag_t ct; 1467 int win; 1468 u_int32_t start, end; 1469 { 1470 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1471 int basereg; 1472 int limitreg; 1473 1474 if ((win < 0) || (win > 2)) { 1475 #if defined DIAGNOSTIC 1476 printf("cardbus_io_open: window out of range %d\n", win); 1477 #endif 1478 return 0; 1479 } 1480 1481 basereg = win * 8 + 0x2c; 1482 limitreg = win * 8 + 0x30; 1483 1484 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1485 start, basereg, end, limitreg)); 1486 1487 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1488 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1489 return 1; 1490 } 1491 1492 /* 1493 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1494 */ 1495 static int 1496 pccbb_io_close(ct, win) 1497 cardbus_chipset_tag_t ct; 1498 int win; 1499 { 1500 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1501 int basereg; 1502 int limitreg; 1503 1504 if ((win < 0) || (win > 2)) { 1505 #if defined DIAGNOSTIC 1506 printf("cardbus_io_close: window out of range %d\n", win); 1507 #endif 1508 return 0; 1509 } 1510 1511 basereg = win * 8 + 0x2c; 1512 limitreg = win * 8 + 0x30; 1513 1514 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1515 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1516 return 1; 1517 } 1518 1519 /* 1520 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1521 */ 1522 static int 1523 pccbb_mem_open(ct, win, start, end) 1524 cardbus_chipset_tag_t ct; 1525 int win; 1526 u_int32_t start, end; 1527 { 1528 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1529 int basereg; 1530 int limitreg; 1531 1532 if ((win < 0) || (win > 2)) { 1533 #if defined DIAGNOSTIC 1534 printf("cardbus_mem_open: window out of range %d\n", win); 1535 #endif 1536 return 0; 1537 } 1538 1539 basereg = win * 8 + 0x1c; 1540 limitreg = win * 8 + 0x20; 1541 1542 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1543 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1544 return 1; 1545 } 1546 1547 /* 1548 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1549 */ 1550 static int 1551 pccbb_mem_close(ct, win) 1552 cardbus_chipset_tag_t ct; 1553 int win; 1554 { 1555 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1556 int basereg; 1557 int limitreg; 1558 1559 if ((win < 0) || (win > 2)) { 1560 #if defined DIAGNOSTIC 1561 printf("cardbus_mem_close: window out of range %d\n", win); 1562 #endif 1563 return 0; 1564 } 1565 1566 basereg = win * 8 + 0x1c; 1567 limitreg = win * 8 + 0x20; 1568 1569 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1570 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1571 return 1; 1572 } 1573 #endif 1574 1575 /* 1576 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1577 * int irq, 1578 * int level, 1579 * int (* func) __P((void *)), 1580 * void *arg) 1581 * 1582 * This function registers an interrupt handler at the bridge, in 1583 * order not to call the interrupt handlers of child devices when 1584 * a card-deletion interrupt occurs. 1585 * 1586 * The arguments irq and level are not used. 1587 */ 1588 static void * 1589 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1590 cardbus_chipset_tag_t ct; 1591 int irq, level; 1592 int (*func) __P((void *)); 1593 void *arg; 1594 { 1595 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1596 1597 return pccbb_intr_establish(sc, irq, level, func, arg); 1598 } 1599 1600 1601 /* 1602 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1603 * void *ih) 1604 * 1605 * This function removes an interrupt handler pointed by ih. 1606 */ 1607 static void 1608 pccbb_cb_intr_disestablish(ct, ih) 1609 cardbus_chipset_tag_t ct; 1610 void *ih; 1611 { 1612 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1613 1614 pccbb_intr_disestablish(sc, ih); 1615 } 1616 1617 1618 /* 1619 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1620 * int irq, 1621 * int level, 1622 * int (* func) __P((void *)), 1623 * void *arg) 1624 * 1625 * This function registers an interrupt handler at the bridge, in 1626 * order not to call the interrupt handlers of child devices when 1627 * a card-deletion interrupt occurs. 1628 * 1629 * The arguments irq is not used because pccbb selects intr vector. 1630 */ 1631 static void * 1632 pccbb_intr_establish(sc, irq, level, func, arg) 1633 struct pccbb_softc *sc; 1634 int irq, level; 1635 int (*func) __P((void *)); 1636 void *arg; 1637 { 1638 struct pccbb_intrhand_list *pil, *newpil; 1639 1640 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1641 1642 if (sc->sc_pil == NULL) { 1643 /* initialize bridge intr routing */ 1644 1645 switch (sc->sc_chipset) { 1646 case CB_TI113X: 1647 { 1648 pcireg_t cbctrl = 1649 pci_conf_read(sc->sc_pc, sc->sc_tag, 1650 PCI_CBCTRL); 1651 /* functional intr enabled */ 1652 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1653 pci_conf_write(sc->sc_pc, sc->sc_tag, 1654 PCI_CBCTRL, cbctrl); 1655 break; 1656 } 1657 default: 1658 break; 1659 } 1660 } 1661 1662 /* 1663 * Allocate a room for interrupt handler structure. 1664 */ 1665 if (NULL == (newpil = 1666 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1667 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1668 return NULL; 1669 } 1670 1671 newpil->pil_func = func; 1672 newpil->pil_arg = arg; 1673 newpil->pil_level = level; 1674 newpil->pil_next = NULL; 1675 1676 if (sc->sc_pil == NULL) { 1677 sc->sc_pil = newpil; 1678 } else { 1679 for (pil = sc->sc_pil; pil->pil_next != NULL; 1680 pil = pil->pil_next); 1681 pil->pil_next = newpil; 1682 } 1683 1684 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1685 1686 return newpil; 1687 } 1688 1689 /* 1690 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1691 * void *ih) 1692 * 1693 * This function removes an interrupt handler pointed by ih. 1694 */ 1695 static void 1696 pccbb_intr_disestablish(sc, ih) 1697 struct pccbb_softc *sc; 1698 void *ih; 1699 { 1700 struct pccbb_intrhand_list *pil, **pil_prev; 1701 1702 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1703 1704 pil_prev = &sc->sc_pil; 1705 1706 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1707 if (pil == ih) { 1708 *pil_prev = pil->pil_next; 1709 free(pil, M_DEVBUF); 1710 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1711 break; 1712 } 1713 pil_prev = &pil->pil_next; 1714 } 1715 1716 if (sc->sc_pil == NULL) { 1717 /* No interrupt handlers */ 1718 1719 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1720 1721 switch (sc->sc_chipset) { 1722 case CB_TI113X: 1723 { 1724 pcireg_t cbctrl = 1725 pci_conf_read(sc->sc_pc, sc->sc_tag, 1726 PCI_CBCTRL); 1727 /* functional intr disabled */ 1728 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1729 pci_conf_write(sc->sc_pc, sc->sc_tag, 1730 PCI_CBCTRL, cbctrl); 1731 break; 1732 } 1733 default: 1734 break; 1735 } 1736 } 1737 } 1738 1739 #if defined SHOW_REGS 1740 static void 1741 cb_show_regs(pc, tag, memt, memh) 1742 pci_chipset_tag_t pc; 1743 pcitag_t tag; 1744 bus_space_tag_t memt; 1745 bus_space_handle_t memh; 1746 { 1747 int i; 1748 printf("PCI config regs:"); 1749 for (i = 0; i < 0x50; i += 4) { 1750 if (i % 16 == 0) { 1751 printf("\n 0x%02x:", i); 1752 } 1753 printf(" %08x", pci_conf_read(pc, tag, i)); 1754 } 1755 for (i = 0x80; i < 0xb0; i += 4) { 1756 if (i % 16 == 0) { 1757 printf("\n 0x%02x:", i); 1758 } 1759 printf(" %08x", pci_conf_read(pc, tag, i)); 1760 } 1761 1762 if (memh == 0) { 1763 printf("\n"); 1764 return; 1765 } 1766 1767 printf("\nsocket regs:"); 1768 for (i = 0; i <= 0x10; i += 0x04) { 1769 printf(" %08x", bus_space_read_4(memt, memh, i)); 1770 } 1771 printf("\nExCA regs:"); 1772 for (i = 0; i < 0x08; ++i) { 1773 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1774 } 1775 printf("\n"); 1776 return; 1777 } 1778 #endif 1779 1780 /* 1781 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1782 * int busno, int devno, int function) 1783 * This is the function to make a tag to access config space of 1784 * a CardBus Card. It works same as pci_conf_read. 1785 */ 1786 static cardbustag_t 1787 pccbb_make_tag(cc, busno, devno, function) 1788 cardbus_chipset_tag_t cc; 1789 int busno, devno, function; 1790 { 1791 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1792 1793 return pci_make_tag(sc->sc_pc, busno, devno, function); 1794 } 1795 1796 static void 1797 pccbb_free_tag(cc, tag) 1798 cardbus_chipset_tag_t cc; 1799 cardbustag_t tag; 1800 { 1801 } 1802 1803 /* 1804 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1805 * cardbustag_t tag, int offset) 1806 * This is the function to read the config space of a CardBus Card. 1807 * It works same as pci_conf_read. 1808 */ 1809 static cardbusreg_t 1810 pccbb_conf_read(cc, tag, offset) 1811 cardbus_chipset_tag_t cc; 1812 cardbustag_t tag; 1813 int offset; /* register offset */ 1814 { 1815 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1816 1817 return pci_conf_read(sc->sc_pc, tag, offset); 1818 } 1819 1820 /* 1821 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1822 * int offs, cardbusreg_t val) 1823 * This is the function to write the config space of a CardBus Card. 1824 * It works same as pci_conf_write. 1825 */ 1826 static void 1827 pccbb_conf_write(cc, tag, reg, val) 1828 cardbus_chipset_tag_t cc; 1829 cardbustag_t tag; 1830 int reg; /* register offset */ 1831 cardbusreg_t val; 1832 { 1833 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1834 1835 pci_conf_write(sc->sc_pc, tag, reg, val); 1836 } 1837 1838 #if 0 1839 STATIC int 1840 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1841 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1842 int speed, int flags, 1843 bus_space_handle_t * iohp) 1844 #endif 1845 /* 1846 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1847 * bus_addr_t start, bus_size_t size, 1848 * bus_size_t align, 1849 * struct pcmcia_io_handle *pcihp 1850 * 1851 * This function only allocates I/O region for pccard. This function 1852 * never maps the allocated region to pccard I/O area. 1853 * 1854 * XXX: The interface of this function is not very good, I believe. 1855 */ 1856 STATIC int 1857 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1858 pcmcia_chipset_handle_t pch; 1859 bus_addr_t start; /* start address */ 1860 bus_size_t size; 1861 bus_size_t align; 1862 struct pcmcia_io_handle *pcihp; 1863 { 1864 struct pcic_handle *ph = (struct pcic_handle *)pch; 1865 bus_addr_t ioaddr; 1866 int flags = 0; 1867 bus_space_tag_t iot; 1868 bus_space_handle_t ioh; 1869 #if rbus 1870 rbus_tag_t rb; 1871 #endif 1872 if (align == 0) { 1873 align = size; /* XXX: funny??? */ 1874 } 1875 1876 /* 1877 * Allocate some arbitrary I/O space. 1878 */ 1879 1880 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1881 1882 #if rbus 1883 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1884 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1885 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1886 return 1; 1887 } 1888 #else 1889 if (start) { 1890 ioaddr = start; 1891 if (bus_space_map(iot, start, size, 0, &ioh)) { 1892 return 1; 1893 } 1894 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1895 (u_long) ioaddr, (u_long) size)); 1896 } else { 1897 flags |= PCMCIA_IO_ALLOCATED; 1898 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1899 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1900 size, align, 0, 0, &ioaddr, &ioh)) { 1901 /* No room be able to be get. */ 1902 return 1; 1903 } 1904 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1905 (u_long) ioaddr, (u_long) size)); 1906 } 1907 #endif 1908 1909 pcihp->iot = iot; 1910 pcihp->ioh = ioh; 1911 pcihp->addr = ioaddr; 1912 pcihp->size = size; 1913 pcihp->flags = flags; 1914 1915 return 0; 1916 } 1917 1918 /* 1919 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1920 * struct pcmcia_io_handle *pcihp) 1921 * 1922 * This function only frees I/O region for pccard. 1923 * 1924 * XXX: The interface of this function is not very good, I believe. 1925 */ 1926 void 1927 pccbb_pcmcia_io_free(pch, pcihp) 1928 pcmcia_chipset_handle_t pch; 1929 struct pcmcia_io_handle *pcihp; 1930 { 1931 #if !rbus 1932 bus_space_tag_t iot = pcihp->iot; 1933 #endif 1934 bus_space_handle_t ioh = pcihp->ioh; 1935 bus_size_t size = pcihp->size; 1936 1937 #if rbus 1938 struct pccbb_softc *sc = 1939 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1940 rbus_tag_t rb = sc->sc_rbus_iot; 1941 1942 rbus_space_free(rb, ioh, size, NULL); 1943 #else 1944 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1945 bus_space_free(iot, ioh, size); 1946 else 1947 bus_space_unmap(iot, ioh, size); 1948 #endif 1949 } 1950 1951 /* 1952 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1953 * bus_addr_t offset, bus_size_t size, 1954 * struct pcmcia_io_handle *pcihp, 1955 * int *windowp) 1956 * 1957 * This function maps the allocated I/O region to pccard. This function 1958 * never allocates any I/O region for pccard I/O area. I don't 1959 * understand why the original authors of pcmciabus separated alloc and 1960 * map. I believe the two must be unite. 1961 * 1962 * XXX: no wait timing control? 1963 */ 1964 int 1965 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1966 pcmcia_chipset_handle_t pch; 1967 int width; 1968 bus_addr_t offset; 1969 bus_size_t size; 1970 struct pcmcia_io_handle *pcihp; 1971 int *windowp; 1972 { 1973 struct pcic_handle *ph = (struct pcic_handle *)pch; 1974 bus_addr_t ioaddr = pcihp->addr + offset; 1975 int i, win; 1976 #if defined CBB_DEBUG 1977 static char *width_names[] = { "dynamic", "io8", "io16" }; 1978 #endif 1979 1980 /* Sanity check I/O handle. */ 1981 1982 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1983 panic("pccbb_pcmcia_io_map iot is bogus"); 1984 } 1985 1986 /* XXX Sanity check offset/size. */ 1987 1988 win = -1; 1989 for (i = 0; i < PCIC_IO_WINS; i++) { 1990 if ((ph->ioalloc & (1 << i)) == 0) { 1991 win = i; 1992 ph->ioalloc |= (1 << i); 1993 break; 1994 } 1995 } 1996 1997 if (win == -1) { 1998 return 1; 1999 } 2000 2001 *windowp = win; 2002 2003 /* XXX this is pretty gross */ 2004 2005 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2006 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2007 2008 /* XXX wtf is this doing here? */ 2009 2010 #if 0 2011 printf(" port 0x%lx", (u_long) ioaddr); 2012 if (size > 1) { 2013 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2014 } 2015 #endif 2016 2017 ph->io[win].addr = ioaddr; 2018 ph->io[win].size = size; 2019 ph->io[win].width = width; 2020 2021 /* actual dirty register-value changing in the function below. */ 2022 pccbb_pcmcia_do_io_map(ph, win); 2023 2024 return 0; 2025 } 2026 2027 /* 2028 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2029 * 2030 * This function changes register-value to map I/O region for pccard. 2031 */ 2032 static void 2033 pccbb_pcmcia_do_io_map(ph, win) 2034 struct pcic_handle *ph; 2035 int win; 2036 { 2037 static u_int8_t pcic_iowidth[3] = { 2038 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2039 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2040 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2041 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2042 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2043 }; 2044 2045 #define PCIC_SIA_START_LOW 0 2046 #define PCIC_SIA_START_HIGH 1 2047 #define PCIC_SIA_STOP_LOW 2 2048 #define PCIC_SIA_STOP_HIGH 3 2049 2050 int regbase_win = 0x8 + win * 0x04; 2051 u_int8_t ioctl, enable; 2052 2053 DPRINTF( 2054 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2055 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2056 ph->io[win].width * 8)); 2057 2058 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2059 ph->io[win].addr & 0xff); 2060 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2061 (ph->io[win].addr >> 8) & 0xff); 2062 2063 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2064 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2065 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2066 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2067 2068 ioctl = Pcic_read(ph, PCIC_IOCTL); 2069 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2070 switch (win) { 2071 case 0: 2072 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2073 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2074 PCIC_IOCTL_IO0_DATASIZE_MASK); 2075 ioctl |= pcic_iowidth[ph->io[win].width]; 2076 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2077 break; 2078 case 1: 2079 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2080 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2081 PCIC_IOCTL_IO1_DATASIZE_MASK); 2082 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2083 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2084 break; 2085 } 2086 Pcic_write(ph, PCIC_IOCTL, ioctl); 2087 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2088 #if defined CBB_DEBUG 2089 { 2090 u_int8_t start_low = 2091 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2092 u_int8_t start_high = 2093 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2094 u_int8_t stop_low = 2095 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2096 u_int8_t stop_high = 2097 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2098 printf 2099 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2100 start_low, start_high, stop_low, stop_high, ioctl, enable); 2101 } 2102 #endif 2103 } 2104 2105 /* 2106 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2107 * 2108 * This function unmaps I/O region. No return value. 2109 */ 2110 STATIC void 2111 pccbb_pcmcia_io_unmap(pch, win) 2112 pcmcia_chipset_handle_t pch; 2113 int win; 2114 { 2115 struct pcic_handle *ph = (struct pcic_handle *)pch; 2116 int reg; 2117 2118 if (win >= PCIC_IO_WINS || win < 0) { 2119 panic("pccbb_pcmcia_io_unmap: window out of range"); 2120 } 2121 2122 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2123 switch (win) { 2124 case 0: 2125 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2126 break; 2127 case 1: 2128 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2129 break; 2130 } 2131 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2132 2133 ph->ioalloc &= ~(1 << win); 2134 } 2135 2136 /* 2137 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2138 * 2139 * This function enables the card. All information is stored in 2140 * the first argument, pcmcia_chipset_handle_t. 2141 */ 2142 static void 2143 pccbb_pcmcia_wait_ready(ph) 2144 struct pcic_handle *ph; 2145 { 2146 int i; 2147 2148 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2149 Pcic_read(ph, PCIC_IF_STATUS))); 2150 2151 for (i = 0; i < 10000; i++) { 2152 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2153 return; 2154 } 2155 delay(500); 2156 #ifdef CBB_DEBUG 2157 if ((i > 5000) && (i % 100 == 99)) 2158 printf("."); 2159 #endif 2160 } 2161 2162 #ifdef DIAGNOSTIC 2163 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2164 Pcic_read(ph, PCIC_IF_STATUS)); 2165 #endif 2166 } 2167 2168 /* 2169 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2170 * 2171 * This function enables the card. All information is stored in 2172 * the first argument, pcmcia_chipset_handle_t. 2173 */ 2174 STATIC void 2175 pccbb_pcmcia_socket_enable(pch) 2176 pcmcia_chipset_handle_t pch; 2177 { 2178 struct pcic_handle *ph = (struct pcic_handle *)pch; 2179 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2180 int cardtype, win; 2181 u_int8_t power, intr; 2182 pcireg_t spsr; 2183 int voltage; 2184 2185 /* this bit is mostly stolen from pcic_attach_card */ 2186 2187 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2188 2189 /* get card Vcc info */ 2190 2191 spsr = 2192 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2193 CB_SOCKET_STAT); 2194 if (spsr & CB_SOCKET_STAT_5VCARD) { 2195 DPRINTF(("5V card\n")); 2196 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2197 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2198 DPRINTF(("3V card\n")); 2199 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2200 } else { 2201 printf("?V card, 0x%x\n", spsr); /* XXX */ 2202 return; 2203 } 2204 2205 /* assert reset bit */ 2206 intr = Pcic_read(ph, PCIC_INTR); 2207 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2208 Pcic_write(ph, PCIC_INTR, intr); 2209 2210 /* disable socket i/o: negate output enable bit */ 2211 2212 power = Pcic_read(ph, PCIC_PWRCTL); 2213 power &= ~PCIC_PWRCTL_OE; 2214 Pcic_write(ph, PCIC_PWRCTL, power); 2215 2216 /* power down the socket to reset it, clear the card reset pin */ 2217 2218 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2219 2220 /* 2221 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2222 * we are changing Vcc (Toff). 2223 */ 2224 /* delay(300*1000); too much */ 2225 2226 /* power up the socket */ 2227 pccbb_power(sc, voltage); 2228 2229 /* 2230 * wait 100ms until power raise (Tpr) and 20ms to become 2231 * stable (Tsu(Vcc)). 2232 * 2233 * some machines require some more time to be settled 2234 * (another 200ms is added here). 2235 */ 2236 /* delay((100 + 20 + 200)*1000); too much */ 2237 2238 power = Pcic_read(ph, PCIC_PWRCTL); 2239 power |= PCIC_PWRCTL_OE; 2240 Pcic_write(ph, PCIC_PWRCTL, power); 2241 2242 /* 2243 * hold RESET at least 10us. 2244 */ 2245 delay(10); 2246 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2247 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2248 2249 /* clear the reset flag */ 2250 2251 intr |= PCIC_INTR_RESET; 2252 Pcic_write(ph, PCIC_INTR, intr); 2253 2254 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2255 2256 delay(20000); 2257 2258 /* wait for the chip to finish initializing */ 2259 2260 pccbb_pcmcia_wait_ready(ph); 2261 2262 /* zero out the address windows */ 2263 2264 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2265 2266 /* set the card type */ 2267 2268 cardtype = pcmcia_card_gettype(ph->pcmcia); 2269 2270 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2271 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2272 Pcic_write(ph, PCIC_INTR, intr); 2273 2274 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2275 ph->ph_parent->dv_xname, ph->sock, 2276 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2277 2278 /* reinstall all the memory and io mappings */ 2279 2280 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2281 if (ph->memalloc & (1 << win)) { 2282 pccbb_pcmcia_do_mem_map(ph, win); 2283 } 2284 } 2285 2286 for (win = 0; win < PCIC_IO_WINS; ++win) { 2287 if (ph->ioalloc & (1 << win)) { 2288 pccbb_pcmcia_do_io_map(ph, win); 2289 } 2290 } 2291 } 2292 2293 /* 2294 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2295 * 2296 * This function disables the card. All information is stored in 2297 * the first argument, pcmcia_chipset_handle_t. 2298 */ 2299 STATIC void 2300 pccbb_pcmcia_socket_disable(pch) 2301 pcmcia_chipset_handle_t pch; 2302 { 2303 struct pcic_handle *ph = (struct pcic_handle *)pch; 2304 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2305 u_int8_t power, intr; 2306 2307 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2308 2309 /* reset signal asserting... */ 2310 2311 intr = Pcic_read(ph, PCIC_INTR); 2312 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2313 Pcic_write(ph, PCIC_INTR, intr); 2314 delay(2 * 1000); 2315 2316 /* power down the socket */ 2317 power = Pcic_read(ph, PCIC_PWRCTL); 2318 power &= ~PCIC_PWRCTL_OE; 2319 Pcic_write(ph, PCIC_PWRCTL, power); 2320 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2321 /* 2322 * wait 300ms until power fails (Tpf). 2323 */ 2324 delay(300 * 1000); 2325 } 2326 2327 /* 2328 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2329 * 2330 * This function detects whether a card is in the slot or not. 2331 * If a card is inserted, return 1. Otherwise, return 0. 2332 */ 2333 STATIC int 2334 pccbb_pcmcia_card_detect(pch) 2335 pcmcia_chipset_handle_t pch; 2336 { 2337 struct pcic_handle *ph = (struct pcic_handle *)pch; 2338 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2339 2340 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2341 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2342 } 2343 2344 #if 0 2345 STATIC int 2346 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2347 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2348 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2349 #endif 2350 /* 2351 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2352 * bus_size_t size, 2353 * struct pcmcia_mem_handle *pcmhp) 2354 * 2355 * This function only allocates memory region for pccard. This 2356 * function never maps the allocated region to pccard memory area. 2357 * 2358 * XXX: Why the argument of start address is not in? 2359 */ 2360 STATIC int 2361 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2362 pcmcia_chipset_handle_t pch; 2363 bus_size_t size; 2364 struct pcmcia_mem_handle *pcmhp; 2365 { 2366 struct pcic_handle *ph = (struct pcic_handle *)pch; 2367 bus_space_handle_t memh; 2368 bus_addr_t addr; 2369 bus_size_t sizepg; 2370 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2371 #if rbus 2372 rbus_tag_t rb; 2373 #endif 2374 2375 /* out of sc->memh, allocate as many pages as necessary */ 2376 2377 /* convert size to PCIC pages */ 2378 /* 2379 * This is not enough; when the requested region is on the page 2380 * boundaries, this may calculate wrong result. 2381 */ 2382 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2383 #if 0 2384 if (sizepg > PCIC_MAX_MEM_PAGES) { 2385 return 1; 2386 } 2387 #endif 2388 2389 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2390 return 1; 2391 } 2392 2393 addr = 0; /* XXX gcc -Wuninitialized */ 2394 2395 #if rbus 2396 rb = sc->sc_rbus_memt; 2397 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2398 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2399 &addr, &memh)) { 2400 return 1; 2401 } 2402 #else 2403 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2404 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2405 0, /* boundary */ 2406 0, /* flags */ 2407 &addr, &memh)) { 2408 return 1; 2409 } 2410 #endif 2411 2412 DPRINTF( 2413 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2414 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2415 2416 pcmhp->memt = sc->sc_memt; 2417 pcmhp->memh = memh; 2418 pcmhp->addr = addr; 2419 pcmhp->size = size; 2420 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2421 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2422 pcmhp->mhandle = 0; 2423 /* No offset??? Funny. */ 2424 2425 return 0; 2426 } 2427 2428 /* 2429 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2430 * struct pcmcia_mem_handle *pcmhp) 2431 * 2432 * This function release the memory space allocated by the function 2433 * pccbb_pcmcia_mem_alloc(). 2434 */ 2435 STATIC void 2436 pccbb_pcmcia_mem_free(pch, pcmhp) 2437 pcmcia_chipset_handle_t pch; 2438 struct pcmcia_mem_handle *pcmhp; 2439 { 2440 #if rbus 2441 struct pcic_handle *ph = (struct pcic_handle *)pch; 2442 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2443 2444 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2445 #else 2446 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2447 #endif 2448 } 2449 2450 /* 2451 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2452 * 2453 * This function release the memory space allocated by the function 2454 * pccbb_pcmcia_mem_alloc(). 2455 */ 2456 STATIC void 2457 pccbb_pcmcia_do_mem_map(ph, win) 2458 struct pcic_handle *ph; 2459 int win; 2460 { 2461 int regbase_win; 2462 bus_addr_t phys_addr; 2463 bus_addr_t phys_end; 2464 2465 #define PCIC_SMM_START_LOW 0 2466 #define PCIC_SMM_START_HIGH 1 2467 #define PCIC_SMM_STOP_LOW 2 2468 #define PCIC_SMM_STOP_HIGH 3 2469 #define PCIC_CMA_LOW 4 2470 #define PCIC_CMA_HIGH 5 2471 2472 u_int8_t start_low, start_high = 0; 2473 u_int8_t stop_low, stop_high; 2474 u_int8_t off_low, off_high; 2475 u_int8_t mem_window; 2476 int reg; 2477 2478 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2479 int mem8 = 2480 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2481 || (kind == PCMCIA_MEM_ATTR); 2482 2483 regbase_win = 0x10 + win * 0x08; 2484 2485 phys_addr = ph->mem[win].addr; 2486 phys_end = phys_addr + ph->mem[win].size; 2487 2488 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2489 phys_addr, phys_end, ph->mem[win].offset)); 2490 2491 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2492 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2493 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2494 2495 /* bit 19:12 */ 2496 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2497 /* bit 23:20 and bit 7 on */ 2498 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2499 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2500 /* bit 31:24, for 32-bit address */ 2501 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2502 2503 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2504 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2505 2506 if (((struct pccbb_softc *)ph-> 2507 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2508 Pcic_write(ph, 0x40 + win, mem_window); 2509 } 2510 2511 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2512 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2513 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2514 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2515 2516 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2517 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2518 2519 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2520 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2521 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2522 | ((kind == PCMCIA_MEM_ATTR) ? 2523 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2524 2525 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2526 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2527 2528 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2529 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2530 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2531 2532 #if defined CBB_DEBUG 2533 { 2534 int r1, r2, r3, r4, r5, r6, r7 = 0; 2535 2536 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2537 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2538 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2539 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2540 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2541 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2542 if (((struct pccbb_softc *)(ph-> 2543 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2544 r7 = Pcic_read(ph, 0x40 + win); 2545 } 2546 2547 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2548 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2549 if (((struct pccbb_softc *)(ph-> 2550 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2551 DPRINTF((" %02x", r7)); 2552 } 2553 DPRINTF(("\n")); 2554 } 2555 #endif 2556 } 2557 2558 /* 2559 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2560 * bus_addr_t card_addr, bus_size_t size, 2561 * struct pcmcia_mem_handle *pcmhp, 2562 * bus_addr_t *offsetp, int *windowp) 2563 * 2564 * This function maps memory space allocated by the function 2565 * pccbb_pcmcia_mem_alloc(). 2566 */ 2567 STATIC int 2568 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2569 pcmcia_chipset_handle_t pch; 2570 int kind; 2571 bus_addr_t card_addr; 2572 bus_size_t size; 2573 struct pcmcia_mem_handle *pcmhp; 2574 bus_addr_t *offsetp; 2575 int *windowp; 2576 { 2577 struct pcic_handle *ph = (struct pcic_handle *)pch; 2578 bus_addr_t busaddr; 2579 long card_offset; 2580 int win; 2581 2582 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2583 if ((ph->memalloc & (1 << win)) == 0) { 2584 ph->memalloc |= (1 << win); 2585 break; 2586 } 2587 } 2588 2589 if (win == PCIC_MEM_WINS) { 2590 return 1; 2591 } 2592 2593 *windowp = win; 2594 2595 /* XXX this is pretty gross */ 2596 2597 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2598 panic("pccbb_pcmcia_mem_map memt is bogus"); 2599 } 2600 2601 busaddr = pcmhp->addr; 2602 2603 /* 2604 * compute the address offset to the pcmcia address space for the 2605 * pcic. this is intentionally signed. The masks and shifts below 2606 * will cause TRT to happen in the pcic registers. Deal with making 2607 * sure the address is aligned, and return the alignment offset. 2608 */ 2609 2610 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2611 card_addr -= *offsetp; 2612 2613 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2614 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2615 (u_long) card_addr)); 2616 2617 /* 2618 * include the offset in the size, and decrement size by one, since 2619 * the hw wants start/stop 2620 */ 2621 size += *offsetp - 1; 2622 2623 card_offset = (((long)card_addr) - ((long)busaddr)); 2624 2625 ph->mem[win].addr = busaddr; 2626 ph->mem[win].size = size; 2627 ph->mem[win].offset = card_offset; 2628 ph->mem[win].kind = kind; 2629 2630 pccbb_pcmcia_do_mem_map(ph, win); 2631 2632 return 0; 2633 } 2634 2635 /* 2636 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2637 * int window) 2638 * 2639 * This function unmaps memory space which mapped by the function 2640 * pccbb_pcmcia_mem_map(). 2641 */ 2642 STATIC void 2643 pccbb_pcmcia_mem_unmap(pch, window) 2644 pcmcia_chipset_handle_t pch; 2645 int window; 2646 { 2647 struct pcic_handle *ph = (struct pcic_handle *)pch; 2648 int reg; 2649 2650 if (window >= PCIC_MEM_WINS) { 2651 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2652 } 2653 2654 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2655 reg &= ~(1 << window); 2656 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2657 2658 ph->memalloc &= ~(1 << window); 2659 } 2660 2661 #if defined PCCBB_PCMCIA_POLL 2662 struct pccbb_poll_str { 2663 void *arg; 2664 int (*func) __P((void *)); 2665 int level; 2666 struct pcic_handle *ph; 2667 int count; 2668 int num; 2669 struct callout poll_ch; 2670 }; 2671 2672 static struct pccbb_poll_str pccbb_poll[10]; 2673 static int pccbb_poll_n = 0; 2674 2675 static void pccbb_pcmcia_poll __P((void *arg)); 2676 2677 static void 2678 pccbb_pcmcia_poll(arg) 2679 void *arg; 2680 { 2681 struct pccbb_poll_str *poll = arg; 2682 struct pcic_handle *ph = poll->ph; 2683 struct pccbb_softc *sc = ph->sc; 2684 int s; 2685 u_int32_t spsr; /* socket present-state reg */ 2686 2687 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2688 switch (poll->level) { 2689 case IPL_NET: 2690 s = splnet(); 2691 break; 2692 case IPL_BIO: 2693 s = splbio(); 2694 break; 2695 case IPL_TTY: /* fallthrough */ 2696 default: 2697 s = spltty(); 2698 break; 2699 } 2700 2701 spsr = 2702 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2703 CB_SOCKET_STAT); 2704 2705 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2706 if (!(spsr & 0x40)) /* CINT low */ 2707 #else 2708 if (1) 2709 #endif 2710 { 2711 if ((*poll->func) (poll->arg) > 0) { 2712 ++poll->count; 2713 // printf("intr: reported from poller, 0x%x\n", spsr); 2714 #if defined LEVEL2 2715 } else { 2716 printf("intr: miss! 0x%x\n", spsr); 2717 #endif 2718 } 2719 } 2720 splx(s); 2721 } 2722 #endif /* defined CB_PCMCIA_POLL */ 2723 2724 /* 2725 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2726 * struct pcmcia_function *pf, 2727 * int ipl, 2728 * int (*func)(void *), 2729 * void *arg); 2730 * 2731 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2732 */ 2733 STATIC void * 2734 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2735 pcmcia_chipset_handle_t pch; 2736 struct pcmcia_function *pf; 2737 int ipl; 2738 int (*func) __P((void *)); 2739 void *arg; 2740 { 2741 struct pcic_handle *ph = (struct pcic_handle *)pch; 2742 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2743 2744 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2745 /* what should I do? */ 2746 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2747 DPRINTF( 2748 ("%s does not provide edge nor pulse interrupt\n", 2749 sc->sc_dev.dv_xname)); 2750 return NULL; 2751 } 2752 /* 2753 * XXX Noooooo! The interrupt flag must set properly!! 2754 * dumb pcmcia driver!! 2755 */ 2756 } 2757 2758 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2759 } 2760 2761 /* 2762 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2763 * void *ih) 2764 * 2765 * This function disables PC-Card interrupt. 2766 */ 2767 STATIC void 2768 pccbb_pcmcia_intr_disestablish(pch, ih) 2769 pcmcia_chipset_handle_t pch; 2770 void *ih; 2771 { 2772 struct pcic_handle *ph = (struct pcic_handle *)pch; 2773 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2774 2775 pccbb_intr_disestablish(sc, ih); 2776 } 2777 2778 #if rbus 2779 /* 2780 * static int 2781 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2782 * bus_addr_t addr, bus_size_t size, 2783 * bus_addr_t mask, bus_size_t align, 2784 * int flags, bus_addr_t *addrp; 2785 * bus_space_handle_t *bshp) 2786 * 2787 * This function allocates a portion of memory or io space for 2788 * clients. This function is called from CardBus card drivers. 2789 */ 2790 static int 2791 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2792 cardbus_chipset_tag_t ct; 2793 rbus_tag_t rb; 2794 bus_addr_t addr; 2795 bus_size_t size; 2796 bus_addr_t mask; 2797 bus_size_t align; 2798 int flags; 2799 bus_addr_t *addrp; 2800 bus_space_handle_t *bshp; 2801 { 2802 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2803 2804 DPRINTF( 2805 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2806 addr, size, mask, align)); 2807 2808 if (align == 0) { 2809 align = size; 2810 } 2811 2812 if (rb->rb_bt == sc->sc_memt) { 2813 if (align < 16) { 2814 return 1; 2815 } 2816 } else if (rb->rb_bt == sc->sc_iot) { 2817 if (align < 4) { 2818 return 1; 2819 } 2820 /* XXX: hack for avoiding ISA image */ 2821 if (mask < 0x0100) { 2822 mask = 0x3ff; 2823 addr = 0x300; 2824 } 2825 2826 } else { 2827 DPRINTF( 2828 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2829 rb->rb_bt)); 2830 return 1; 2831 /* XXX: panic here? */ 2832 } 2833 2834 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2835 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2836 return 1; 2837 } 2838 2839 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2840 2841 return 0; 2842 } 2843 2844 /* 2845 * static int 2846 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2847 * bus_space_handle_t *bshp, bus_size_t size); 2848 * 2849 * This function is called from CardBus card drivers. 2850 */ 2851 static int 2852 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2853 cardbus_chipset_tag_t ct; 2854 rbus_tag_t rb; 2855 bus_space_handle_t bsh; 2856 bus_size_t size; 2857 { 2858 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2859 bus_space_tag_t bt = rb->rb_bt; 2860 2861 pccbb_close_win(sc, bt, bsh, size); 2862 2863 if (bt == sc->sc_memt) { 2864 } else if (bt == sc->sc_iot) { 2865 } else { 2866 return 1; 2867 /* XXX: panic here? */ 2868 } 2869 2870 return rbus_space_free(rb, bsh, size, NULL); 2871 } 2872 #endif /* rbus */ 2873 2874 #if rbus 2875 2876 static int 2877 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2878 struct pccbb_softc *sc; 2879 bus_space_tag_t bst; 2880 bus_addr_t addr; 2881 bus_size_t size; 2882 bus_space_handle_t bsh; 2883 int flags; 2884 { 2885 struct pccbb_win_chain_head *head; 2886 bus_addr_t align; 2887 2888 head = &sc->sc_iowindow; 2889 align = 0x04; 2890 if (sc->sc_memt == bst) { 2891 head = &sc->sc_memwindow; 2892 align = 0x1000; 2893 DPRINTF(("using memory window, %x %x %x\n\n", 2894 sc->sc_iot, sc->sc_memt, bst)); 2895 } 2896 2897 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2898 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2899 sc->sc_dev.dv_xname, 2900 (head == &sc->sc_memwindow) ? "mem" : "io"); 2901 } 2902 pccbb_winset(align, sc, bst); 2903 2904 return 0; 2905 } 2906 2907 static int 2908 pccbb_close_win(sc, bst, bsh, size) 2909 struct pccbb_softc *sc; 2910 bus_space_tag_t bst; 2911 bus_space_handle_t bsh; 2912 bus_size_t size; 2913 { 2914 struct pccbb_win_chain_head *head; 2915 bus_addr_t align; 2916 2917 head = &sc->sc_iowindow; 2918 align = 0x04; 2919 if (sc->sc_memt == bst) { 2920 head = &sc->sc_memwindow; 2921 align = 0x1000; 2922 } 2923 2924 if (pccbb_winlist_delete(head, bsh, size)) { 2925 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2926 sc->sc_dev.dv_xname, 2927 (head == &sc->sc_memwindow) ? "mem" : "io"); 2928 } 2929 pccbb_winset(align, sc, bst); 2930 2931 return 0; 2932 } 2933 2934 static int 2935 pccbb_winlist_insert(head, start, size, bsh, flags) 2936 struct pccbb_win_chain_head *head; 2937 bus_addr_t start; 2938 bus_size_t size; 2939 bus_space_handle_t bsh; 2940 int flags; 2941 { 2942 struct pccbb_win_chain *chainp, *elem; 2943 2944 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2945 M_NOWAIT)) == NULL) 2946 return (1); /* fail */ 2947 2948 elem->wc_start = start; 2949 elem->wc_end = start + (size - 1); 2950 elem->wc_handle = bsh; 2951 elem->wc_flags = flags; 2952 2953 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2954 chainp = TAILQ_NEXT(chainp, wc_list)) { 2955 if (chainp->wc_end < start) 2956 continue; 2957 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2958 return (0); 2959 } 2960 2961 TAILQ_INSERT_TAIL(head, elem, wc_list); 2962 return (0); 2963 } 2964 2965 static int 2966 pccbb_winlist_delete(head, bsh, size) 2967 struct pccbb_win_chain_head *head; 2968 bus_space_handle_t bsh; 2969 bus_size_t size; 2970 { 2971 struct pccbb_win_chain *chainp; 2972 2973 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2974 chainp = TAILQ_NEXT(chainp, wc_list)) { 2975 if (chainp->wc_handle != bsh) 2976 continue; 2977 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2978 printf("pccbb_winlist_delete: window 0x%lx size " 2979 "inconsistent: 0x%lx, 0x%lx\n", 2980 chainp->wc_start, 2981 chainp->wc_end - chainp->wc_start, 2982 size - 1); 2983 return 1; 2984 } 2985 2986 TAILQ_REMOVE(head, chainp, wc_list); 2987 free(chainp, M_DEVBUF); 2988 2989 return 0; 2990 } 2991 2992 return 1; /* fail: no candidate to remove */ 2993 } 2994 2995 static void 2996 pccbb_winset(align, sc, bst) 2997 bus_addr_t align; 2998 struct pccbb_softc *sc; 2999 bus_space_tag_t bst; 3000 { 3001 pci_chipset_tag_t pc; 3002 pcitag_t tag; 3003 bus_addr_t mask = ~(align - 1); 3004 struct { 3005 cardbusreg_t win_start; 3006 cardbusreg_t win_limit; 3007 int win_flags; 3008 } win[2]; 3009 struct pccbb_win_chain *chainp; 3010 int offs; 3011 3012 win[0].win_start = 0xffffffff; 3013 win[0].win_limit = 0; 3014 win[1].win_start = 0xffffffff; 3015 win[1].win_limit = 0; 3016 3017 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3018 offs = 0x2c; 3019 if (sc->sc_memt == bst) { 3020 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3021 offs = 0x1c; 3022 } 3023 3024 if (chainp != NULL) { 3025 win[0].win_start = chainp->wc_start & mask; 3026 win[0].win_limit = chainp->wc_end & mask; 3027 win[0].win_flags = chainp->wc_flags; 3028 chainp = TAILQ_NEXT(chainp, wc_list); 3029 } 3030 3031 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3032 if (win[1].win_start == 0xffffffff) { 3033 /* window 1 is not used */ 3034 if ((win[0].win_flags == chainp->wc_flags) && 3035 (win[0].win_limit + align >= 3036 (chainp->wc_start & mask))) { 3037 /* concatenate */ 3038 win[0].win_limit = chainp->wc_end & mask; 3039 } else { 3040 /* make new window */ 3041 win[1].win_start = chainp->wc_start & mask; 3042 win[1].win_limit = chainp->wc_end & mask; 3043 win[1].win_flags = chainp->wc_flags; 3044 } 3045 continue; 3046 } 3047 3048 /* Both windows are engaged. */ 3049 if (win[0].win_flags == win[1].win_flags) { 3050 /* same flags */ 3051 if (win[0].win_flags == chainp->wc_flags) { 3052 if (win[1].win_start - (win[0].win_limit + 3053 align) < 3054 (chainp->wc_start & mask) - 3055 ((chainp->wc_end & mask) + align)) { 3056 /* 3057 * merge window 0 and 1, and set win1 3058 * to chainp 3059 */ 3060 win[0].win_limit = win[1].win_limit; 3061 win[1].win_start = 3062 chainp->wc_start & mask; 3063 win[1].win_limit = 3064 chainp->wc_end & mask; 3065 } else { 3066 win[1].win_limit = 3067 chainp->wc_end & mask; 3068 } 3069 } else { 3070 /* different flags */ 3071 3072 /* concatenate win0 and win1 */ 3073 win[0].win_limit = win[1].win_limit; 3074 /* allocate win[1] to new space */ 3075 win[1].win_start = chainp->wc_start & mask; 3076 win[1].win_limit = chainp->wc_end & mask; 3077 win[1].win_flags = chainp->wc_flags; 3078 } 3079 } else { 3080 /* the flags of win[0] and win[1] is different */ 3081 if (win[0].win_flags == chainp->wc_flags) { 3082 win[0].win_limit = chainp->wc_end & mask; 3083 /* 3084 * XXX this creates overlapping windows, so 3085 * what should the poor bridge do if one is 3086 * cachable, and the other is not? 3087 */ 3088 printf("%s: overlapping windows\n", 3089 sc->sc_dev.dv_xname); 3090 } else { 3091 win[1].win_limit = chainp->wc_end & mask; 3092 } 3093 } 3094 } 3095 3096 pc = sc->sc_pc; 3097 tag = sc->sc_tag; 3098 pci_conf_write(pc, tag, offs, win[0].win_start); 3099 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3100 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3101 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3102 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3103 pci_conf_read(pc, tag, offs), 3104 pci_conf_read(pc, tag, offs + 4) + align, 3105 pci_conf_read(pc, tag, offs + 8), 3106 pci_conf_read(pc, tag, offs + 12) + align)); 3107 3108 if (bst == sc->sc_memt) { 3109 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3110 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3111 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3112 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3113 } 3114 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3115 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3116 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3117 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3118 } 3119 } 3120 } 3121 3122 #endif /* rbus */ 3123 3124 static void 3125 pccbb_powerhook(why, arg) 3126 int why; 3127 void *arg; 3128 { 3129 struct pccbb_softc *sc = arg; 3130 u_int32_t reg; 3131 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3132 bus_space_handle_t base_memh = sc->sc_base_memh; 3133 3134 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3135 3136 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3137 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3138 if (sc->sc_pil_intr_enable) { 3139 (void)pccbbintr_function(sc); 3140 } 3141 sc->sc_pil_intr_enable = 0; 3142 3143 /* ToDo: deactivate or suspend child devices */ 3144 3145 } 3146 3147 if (why == PWR_RESUME) { 3148 /* CSC Interrupt: Card detect interrupt on */ 3149 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3150 /* Card detect intr is turned on. */ 3151 reg |= CB_SOCKET_MASK_CD; 3152 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3153 /* reset interrupt */ 3154 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3155 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3156 3157 /* 3158 * check for card insertion or removal during suspend period. 3159 * XXX: the code can't cope with card swap (remove then 3160 * insert). how can we detect such situation? 3161 */ 3162 (void)pccbbintr(sc); 3163 3164 sc->sc_pil_intr_enable = 1; 3165 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3166 3167 /* ToDo: activate or wakeup child devices */ 3168 } 3169 } 3170
Indexes created Thu Oct 16 14:10:15 GMT 2025