pccbb.c revision 1.42.2.5
1 /* $NetBSD: pccbb.c,v 1.42.2.5 2001/12/24 14:23:22 he Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 93 void pccbbattach __P((struct device *, struct device *, void *)); 94 int pccbbintr __P((void *)); 95 static void pci113x_insert __P((void *)); 96 static int pccbbintr_function __P((struct pccbb_softc *)); 97 98 static int pccbb_detect_card __P((struct pccbb_softc *)); 99 100 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 101 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 102 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 103 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 104 105 STATIC int cb_reset __P((struct pccbb_softc *)); 106 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 107 STATIC int cbbprint __P((void *, const char *)); 108 109 static int cb_chipset __P((u_int32_t, int *)); 110 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 111 struct pcmciabus_attach_args *)); 112 #if 0 113 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 114 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 115 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 116 #endif 117 118 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 119 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 120 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 121 #if !rbus 122 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 123 u_int32_t)); 124 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 125 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 126 u_int32_t)); 127 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 128 #endif /* !rbus */ 129 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 130 int level, int (*ih) (void *), void *sc)); 131 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 132 133 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 static void pccbb_powerhook __P((int, void *)); 171 172 /* bus-space allocation and deallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 178 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t)); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 187 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t)); 189 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int)); 191 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 192 bus_space_handle_t, bus_size_t)); 193 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t)); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback __P((struct device *)); 201 202 #if defined SHOW_REGS 203 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 204 bus_space_tag_t memt, bus_space_handle_t memh)); 205 #endif 206 207 struct cfattach cbb_pci_ca = { 208 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 209 }; 210 211 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 212 pccbb_pcmcia_mem_alloc, 213 pccbb_pcmcia_mem_free, 214 pccbb_pcmcia_mem_map, 215 pccbb_pcmcia_mem_unmap, 216 pccbb_pcmcia_io_alloc, 217 pccbb_pcmcia_io_free, 218 pccbb_pcmcia_io_map, 219 pccbb_pcmcia_io_unmap, 220 pccbb_pcmcia_intr_establish, 221 pccbb_pcmcia_intr_disestablish, 222 pccbb_pcmcia_socket_enable, 223 pccbb_pcmcia_socket_disable, 224 pccbb_pcmcia_card_detect 225 }; 226 227 #if rbus 228 static struct cardbus_functions pccbb_funcs = { 229 pccbb_rbus_cb_space_alloc, 230 pccbb_rbus_cb_space_free, 231 pccbb_cb_intr_establish, 232 pccbb_cb_intr_disestablish, 233 pccbb_ctrl, 234 pccbb_power, 235 pccbb_make_tag, 236 pccbb_free_tag, 237 pccbb_conf_read, 238 pccbb_conf_write, 239 }; 240 #else 241 static struct cardbus_functions pccbb_funcs = { 242 pccbb_ctrl, 243 pccbb_power, 244 pccbb_mem_open, 245 pccbb_mem_close, 246 pccbb_io_open, 247 pccbb_io_close, 248 pccbb_cb_intr_establish, 249 pccbb_cb_intr_disestablish, 250 pccbb_make_tag, 251 pccbb_conf_read, 252 pccbb_conf_write, 253 }; 254 #endif 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 struct cfdata *match; 260 void *aux; 261 { 262 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 263 264 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 265 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 266 PCI_INTERFACE(pa->pa_class) == 0) { 267 return 1; 268 } 269 270 return 0; 271 } 272 273 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 274 | ((prod) << PCI_PRODUCT_SHIFT)) 275 276 struct yenta_chipinfo { 277 pcireg_t yc_id; /* vendor tag | product tag */ 278 int yc_chiptype; 279 int yc_flags; 280 } yc_chipsets[] = { 281 /* Texas Instruments chips */ 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 307 /* Ricoh chips */ 308 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 309 PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 311 PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 313 PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 315 PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 319 PCCBB_PCMCIA_MEM_32}, 320 321 /* Toshiba products */ 322 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 323 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 325 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 327 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 329 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 330 331 /* Cirrus Logic products */ 332 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 333 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 335 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 336 337 /* sentinel, or Generic chip */ 338 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 339 }; 340 341 static int 342 cb_chipset(pci_id, flagp) 343 u_int32_t pci_id; 344 int *flagp; 345 { 346 struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return (yc->yc_chiptype); 358 } 359 360 static void 361 pccbb_shutdown(void *arg) 362 { 363 struct pccbb_softc *sc = arg; 364 pcireg_t command; 365 366 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 367 368 /* 369 * turn off power 370 * 371 * XXX - do not turn off power if chipset is TI 113X because 372 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 373 */ 374 if (sc->sc_chipset != CB_TI113X) { 375 pccbb_power((cardbus_chipset_tag_t)sc, 376 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 377 } 378 379 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 380 0); 381 382 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 383 384 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 385 PCI_COMMAND_MASTER_ENABLE); 386 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 387 388 } 389 390 void 391 pccbbattach(parent, self, aux) 392 struct device *parent; 393 struct device *self; 394 void *aux; 395 { 396 struct pccbb_softc *sc = (void *)self; 397 struct pci_attach_args *pa = aux; 398 pci_chipset_tag_t pc = pa->pa_pc; 399 pcireg_t busreg, reg, sock_base; 400 bus_addr_t sockbase; 401 char devinfo[256]; 402 int flags; 403 int pwrmgt_offs; 404 405 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 406 407 pci_devinfo(pa->pa_id, 0, 0, devinfo); 408 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 409 #ifdef CBB_DEBUG 410 printf(" (chipflags %x)", flags); 411 #endif 412 printf("\n"); 413 414 TAILQ_INIT(&sc->sc_memwindow); 415 TAILQ_INIT(&sc->sc_iowindow); 416 417 #if rbus 418 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 419 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 420 #endif /* rbus */ 421 422 sc->sc_base_memh = 0; 423 424 /* power management: set D0 state */ 425 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 426 &pwrmgt_offs, 0)) { 427 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + 4); 428 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 429 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 430 reg &= ~PCI_PMCSR_STATE_MASK; 431 reg |= PCI_PMCSR_STATE_D0; 432 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 433 pci_conf_write(pc, pa->pa_tag, pwrmgt_offs + 4, reg); 434 } 435 } 436 437 /* 438 * MAP socket registers and ExCA registers on memory-space 439 * When no valid address is set on socket base registers (on pci 440 * config space), get it not polite way. 441 */ 442 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 443 444 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 445 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 446 /* The address must be valid. */ 447 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 448 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 449 printf("%s: can't map socket base address 0x%x\n", 450 sc->sc_dev.dv_xname, sock_base); 451 /* 452 * I think it's funny: socket base registers must be 453 * mapped on memory space, but ... 454 */ 455 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 456 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 457 NULL)) { 458 printf("%s: can't map socket base address" 459 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 460 sockbase); 461 /* give up... allocate reg space via rbus. */ 462 sc->sc_base_memh = 0; 463 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 464 } 465 } else { 466 DPRINTF(("%s: socket base address 0x%lx\n", 467 sc->sc_dev.dv_xname, sockbase)); 468 } 469 } 470 471 sc->sc_mem_start = 0; /* XXX */ 472 sc->sc_mem_end = 0xffffffff; /* XXX */ 473 474 /* 475 * When interrupt isn't routed correctly, give up probing cbb and do 476 * not kill pcic-compatible port. 477 */ 478 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 479 printf("%s: NOT USED because of unconfigured interrupt\n", 480 sc->sc_dev.dv_xname); 481 return; 482 } 483 484 /* 485 * When bus number isn't set correctly, give up using 32-bit CardBus 486 * mode. 487 */ 488 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 489 #if notyet 490 if (((busreg >> 8) & 0xff) == 0) { 491 printf("%s: CardBus support disabled because of unconfigured bus number\n", 492 sc->sc_dev.dv_xname); 493 flags |= PCCBB_PCMCIA_16BITONLY; 494 } 495 #endif 496 497 /* pccbb_machdep.c end */ 498 499 #if defined CBB_DEBUG 500 { 501 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 502 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 503 intrname[pa->pa_intrpin], pa->pa_intrline); 504 } 505 #endif 506 507 /* setup softc */ 508 sc->sc_pc = pc; 509 sc->sc_iot = pa->pa_iot; 510 sc->sc_memt = pa->pa_memt; 511 sc->sc_dmat = pa->pa_dmat; 512 sc->sc_tag = pa->pa_tag; 513 sc->sc_function = pa->pa_function; 514 515 sc->sc_intrline = pa->pa_intrline; 516 sc->sc_intrtag = pa->pa_intrtag; 517 sc->sc_intrpin = pa->pa_intrpin; 518 519 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 520 521 shutdownhook_establish(pccbb_shutdown, sc); 522 523 /* Disable legacy register mapping. */ 524 switch (sc->sc_chipset) { 525 case CB_RX5C46X: /* fallthrough */ 526 #if 0 527 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 528 case CB_RX5C47X: 529 #endif 530 /* 531 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 532 * cannot be disabled by substituting 0 into PCI_LEGACY 533 * register. Ricoh CardBus bridges have special bits on Bridge 534 * control reg (addr 0x3e on PCI config space). 535 */ 536 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 537 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 538 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 539 break; 540 541 default: 542 /* XXX I don't know proper way to kill legacy I/O. */ 543 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 544 break; 545 } 546 547 config_defer(self, pccbb_pci_callback); 548 } 549 550 551 552 553 /* 554 * static void pccbb_pci_callback(struct device *self) 555 * 556 * The actual attach routine: get memory space for YENTA register 557 * space, setup YENTA register and route interrupt. 558 * 559 * This function should be deferred because this device may obtain 560 * memory space dynamically. This function must avoid obtaining 561 * memory area which has already kept for another device. 562 */ 563 static void 564 pccbb_pci_callback(self) 565 struct device *self; 566 { 567 struct pccbb_softc *sc = (void *)self; 568 pci_chipset_tag_t pc = sc->sc_pc; 569 bus_space_tag_t base_memt; 570 bus_space_handle_t base_memh; 571 u_int32_t maskreg; 572 pci_intr_handle_t ih; 573 const char *intrstr = NULL; 574 bus_addr_t sockbase; 575 struct cbslot_attach_args cba; 576 struct pcmciabus_attach_args paa; 577 struct cardslot_attach_args caa; 578 struct cardslot_softc *csc; 579 580 if (0 == sc->sc_base_memh) { 581 /* The socket registers aren't mapped correctly. */ 582 #if rbus 583 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 584 (sc->sc_chipset == CB_RX5C47X 585 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 586 0, &sockbase, &sc->sc_base_memh)) { 587 return; 588 } 589 sc->sc_base_memt = sc->sc_memt; 590 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 591 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 592 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 593 PCI_SOCKBASE))); 594 #else 595 sc->sc_base_memt = sc->sc_memt; 596 #if !defined CBB_PCI_BASE 597 #define CBB_PCI_BASE 0x20000000 598 #endif 599 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 600 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 601 /* cannot allocate memory space */ 602 return; 603 } 604 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 605 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 606 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 607 sc->sc_tag, PCI_SOCKBASE))); 608 #endif 609 } 610 611 /* bus bridge initialization */ 612 pccbb_chipinit(sc); 613 614 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 615 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 616 617 /* CSC Interrupt: Card detect interrupt on */ 618 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 619 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 620 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 621 /* reset interrupt */ 622 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 623 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 624 625 /* clear data structure for child device interrupt handlers */ 626 sc->sc_pil = NULL; 627 sc->sc_pil_intr_enable = 1; 628 629 /* Map and establish the interrupt. */ 630 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 631 sc->sc_intrline, &ih)) { 632 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 633 return; 634 } 635 intrstr = pci_intr_string(pc, ih); 636 637 /* 638 * XXX pccbbintr should be called under the priority lower 639 * than any other hard interrputs. 640 */ 641 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 642 643 if (sc->sc_ih == NULL) { 644 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 645 if (intrstr != NULL) { 646 printf(" at %s", intrstr); 647 } 648 printf("\n"); 649 return; 650 } 651 652 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 653 powerhook_establish(pccbb_powerhook, sc); 654 655 { 656 u_int32_t sockstat = 657 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 658 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 659 sc->sc_flags |= CBB_CARDEXIST; 660 } 661 } 662 663 /* 664 * attach cardbus 665 */ 666 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 667 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 668 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 669 670 /* initialize cbslot_attach */ 671 cba.cba_busname = "cardbus"; 672 cba.cba_iot = sc->sc_iot; 673 cba.cba_memt = sc->sc_memt; 674 cba.cba_dmat = sc->sc_dmat; 675 cba.cba_bus = (busreg >> 8) & 0x0ff; 676 cba.cba_cc = (void *)sc; 677 cba.cba_cf = &pccbb_funcs; 678 cba.cba_intrline = sc->sc_intrline; 679 680 #if rbus 681 cba.cba_rbus_iot = sc->sc_rbus_iot; 682 cba.cba_rbus_memt = sc->sc_rbus_memt; 683 #endif 684 685 cba.cba_cacheline = PCI_CACHELINE(bhlc); 686 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 687 688 printf("%s: cacheline 0x%x lattimer 0x%x\n", 689 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 690 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 691 busreg); 692 #if defined SHOW_REGS 693 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 694 sc->sc_base_memh); 695 #endif 696 } 697 698 pccbb_pcmcia_attach_setup(sc, &paa); 699 caa.caa_cb_attach = NULL; 700 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 701 caa.caa_cb_attach = &cba; 702 } 703 caa.caa_16_attach = &paa; 704 caa.caa_ph = &sc->sc_pcmcia_h; 705 706 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 707 DPRINTF(("pccbbattach: found cardslot\n")); 708 sc->sc_csc = csc; 709 } 710 711 return; 712 } 713 714 715 716 717 718 /* 719 * static void pccbb_chipinit(struct pccbb_softc *sc) 720 * 721 * This function initialize YENTA chip registers listed below: 722 * 1) PCI command reg, 723 * 2) PCI and CardBus latency timer, 724 * 3) route PCI interrupt, 725 * 4) close all memory and io windows. 726 */ 727 static void 728 pccbb_chipinit(sc) 729 struct pccbb_softc *sc; 730 { 731 pci_chipset_tag_t pc = sc->sc_pc; 732 pcitag_t tag = sc->sc_tag; 733 pcireg_t reg; 734 735 /* 736 * Set PCI command reg. 737 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 738 */ 739 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 740 /* I believe it is harmless. */ 741 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 742 PCI_COMMAND_MASTER_ENABLE); 743 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 744 745 /* 746 * Set CardBus latency timer. 747 */ 748 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 749 if (PCI_CB_LATENCY(reg) < 0x20) { 750 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 751 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 752 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 753 } 754 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 755 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 756 757 /* 758 * Set PCI latency timer. 759 */ 760 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 761 if (PCI_LATTIMER(reg) < 0x10) { 762 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 763 reg |= (0x10 << PCI_LATTIMER_SHIFT); 764 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 765 } 766 DPRINTF(("PCI latency timer 0x%x (%x)\n", 767 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 768 769 770 /* Route functional interrupts to PCI. */ 771 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 772 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 773 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 774 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 775 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 776 777 switch (sc->sc_chipset) { 778 case CB_TI113X: 779 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 780 /* This bit is shared, but may read as 0 on some chips, so set 781 it explicitly on both functions. */ 782 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 783 /* CSC intr enable */ 784 reg |= PCI113X_CBCTRL_PCI_CSC; 785 /* functional intr prohibit | prohibit ISA routing */ 786 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 787 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 788 break; 789 790 case CB_TOPIC95B: 791 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 792 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 793 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 794 795 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 796 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 797 sc->sc_dev.dv_xname, reg)); 798 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 799 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 800 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 801 DPRINTF(("0x%x\n", reg)); 802 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 803 break; 804 } 805 806 /* Close all memory and I/O windows. */ 807 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 808 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 809 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 810 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 811 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 812 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 813 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 814 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 815 816 /* reset 16-bit pcmcia bus */ 817 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 818 0x800 + PCIC_INTR, 819 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 820 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 821 822 /* turn of power */ 823 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 824 } 825 826 827 828 829 /* 830 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 831 * struct pcmciabus_attach_args *paa) 832 * 833 * This function attaches 16-bit PCcard bus. 834 */ 835 STATIC void 836 pccbb_pcmcia_attach_setup(sc, paa) 837 struct pccbb_softc *sc; 838 struct pcmciabus_attach_args *paa; 839 { 840 struct pcic_handle *ph = &sc->sc_pcmcia_h; 841 #if rbus 842 rbus_tag_t rb; 843 #endif 844 845 /* initialize pcmcia part in pccbb_softc */ 846 ph->ph_parent = (struct device *)sc; 847 ph->sock = sc->sc_function; 848 ph->flags = 0; 849 ph->shutdown = 0; 850 ph->ih_irq = sc->sc_intrline; 851 ph->ph_bus_t = sc->sc_base_memt; 852 ph->ph_bus_h = sc->sc_base_memh; 853 ph->ph_read = pccbb_pcmcia_read; 854 ph->ph_write = pccbb_pcmcia_write; 855 sc->sc_pct = &pccbb_pcmcia_funcs; 856 857 /* 858 * We need to do a few things here: 859 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 860 * setting the IRQ numbers to 0. 861 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 862 * routing of CSC interrupts (e.g. card removal) to PCI while in 863 * PCMCIA mode. We just leave this set all the time. 864 * 3) Enable card insertion/removal interrupts in case the chip also 865 * needs that while in PCMCIA mode. 866 * 4) Clear any pending CSC interrupt. 867 */ 868 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 869 if (sc->sc_chipset == CB_TI113X) { 870 Pcic_write(ph, PCIC_CSC_INTR, 0); 871 } else { 872 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 873 Pcic_read(ph, PCIC_CSC); 874 } 875 876 /* initialize pcmcia bus attachment */ 877 paa->paa_busname = "pcmcia"; 878 paa->pct = sc->sc_pct; 879 paa->pch = ph; 880 paa->iobase = 0; /* I don't use them */ 881 paa->iosize = 0; 882 #if rbus 883 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 884 paa->iobase = rb->rb_start + rb->rb_offset; 885 paa->iosize = rb->rb_end - rb->rb_start; 886 #endif 887 888 return; 889 } 890 891 #if 0 892 STATIC void 893 pccbb_pcmcia_attach_card(ph) 894 struct pcic_handle *ph; 895 { 896 if (ph->flags & PCIC_FLAG_CARDP) { 897 panic("pccbb_pcmcia_attach_card: already attached"); 898 } 899 900 /* call the MI attach function */ 901 pcmcia_card_attach(ph->pcmcia); 902 903 ph->flags |= PCIC_FLAG_CARDP; 904 } 905 906 STATIC void 907 pccbb_pcmcia_detach_card(ph, flags) 908 struct pcic_handle *ph; 909 int flags; 910 { 911 if (!(ph->flags & PCIC_FLAG_CARDP)) { 912 panic("pccbb_pcmcia_detach_card: already detached"); 913 } 914 915 ph->flags &= ~PCIC_FLAG_CARDP; 916 917 /* call the MI detach function */ 918 pcmcia_card_detach(ph->pcmcia, flags); 919 } 920 #endif 921 922 /* 923 * int pccbbintr(arg) 924 * void *arg; 925 * This routine handles the interrupt from Yenta PCI-CardBus bridge 926 * itself. 927 */ 928 int 929 pccbbintr(arg) 930 void *arg; 931 { 932 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 933 u_int32_t sockevent, sockstate; 934 bus_space_tag_t memt = sc->sc_base_memt; 935 bus_space_handle_t memh = sc->sc_base_memh; 936 struct pcic_handle *ph = &sc->sc_pcmcia_h; 937 938 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 939 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 940 Pcic_read(ph, PCIC_CSC); 941 942 if (sockevent == 0) { 943 /* This intr is not for me: it may be for my child devices. */ 944 if (sc->sc_pil_intr_enable) { 945 return pccbbintr_function(sc); 946 } else { 947 return 0; 948 } 949 } 950 951 if (sockevent & CB_SOCKET_EVENT_CD) { 952 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 953 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 954 /* A card should be removed. */ 955 if (sc->sc_flags & CBB_CARDEXIST) { 956 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 957 sockevent)); 958 DPRINTF((" card removed, 0x%08x\n", sockstate)); 959 sc->sc_flags &= ~CBB_CARDEXIST; 960 if (sc->sc_csc->sc_status & 961 CARDSLOT_STATUS_CARD_16) { 962 #if 0 963 struct pcic_handle *ph = 964 &sc->sc_pcmcia_h; 965 966 pcmcia_card_deactivate(ph->pcmcia); 967 pccbb_pcmcia_socket_disable(ph); 968 pccbb_pcmcia_detach_card(ph, 969 DETACH_FORCE); 970 #endif 971 cardslot_event_throw(sc->sc_csc, 972 CARDSLOT_EVENT_REMOVAL_16); 973 } else if (sc->sc_csc->sc_status & 974 CARDSLOT_STATUS_CARD_CB) { 975 /* Cardbus intr removed */ 976 cardslot_event_throw(sc->sc_csc, 977 CARDSLOT_EVENT_REMOVAL_CB); 978 } 979 } 980 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 981 /* 982 * The pccbbintr may called from powerdown hook when 983 * the system resumed, to detect the card 984 * insertion/removal during suspension. 985 */ 986 (sc->sc_flags & CBB_CARDEXIST) == 0) { 987 if (sc->sc_flags & CBB_INSERTING) { 988 callout_stop(&sc->sc_insert_ch); 989 } 990 callout_reset(&sc->sc_insert_ch, hz / 10, 991 pci113x_insert, sc); 992 sc->sc_flags |= CBB_INSERTING; 993 } 994 } 995 996 return (1); 997 } 998 999 /* 1000 * static int pccbbintr_function(struct pccbb_softc *sc) 1001 * 1002 * This function calls each interrupt handler registered at the 1003 * bridge. The interrupt handlers are called in registered order. 1004 */ 1005 static int 1006 pccbbintr_function(sc) 1007 struct pccbb_softc *sc; 1008 { 1009 int retval = 0, val; 1010 struct pccbb_intrhand_list *pil; 1011 int s, splchanged; 1012 1013 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1014 /* 1015 * XXX priority change. gross. I use if-else 1016 * sentense instead of switch-case sentense because of 1017 * avoiding duplicate case value error. More than one 1018 * IPL_XXX use same value. It depends on 1019 * implimentation. 1020 */ 1021 splchanged = 1; 1022 if (pil->pil_level == IPL_SERIAL) { 1023 s = splserial(); 1024 } else if (pil->pil_level == IPL_HIGH) { 1025 s = splhigh(); 1026 } else if (pil->pil_level == IPL_CLOCK) { 1027 s = splclock(); 1028 } else if (pil->pil_level == IPL_AUDIO) { 1029 s = splaudio(); 1030 } else if (pil->pil_level == IPL_IMP) { 1031 s = splimp(); 1032 } else if (pil->pil_level == IPL_TTY) { 1033 s = spltty(); 1034 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1035 s = splsoftserial(); 1036 } else if (pil->pil_level == IPL_NET) { 1037 s = splnet(); 1038 } else { 1039 splchanged = 0; 1040 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1041 } 1042 1043 val = (*pil->pil_func)(pil->pil_arg); 1044 1045 if (splchanged != 0) { 1046 splx(s); 1047 } 1048 1049 retval = retval == 1 ? 1 : 1050 retval == 0 ? val : val != 0 ? val : retval; 1051 } 1052 1053 return retval; 1054 } 1055 1056 static void 1057 pci113x_insert(arg) 1058 void *arg; 1059 { 1060 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1061 u_int32_t sockevent, sockstate; 1062 1063 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1064 CB_SOCKET_EVENT); 1065 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1066 CB_SOCKET_STAT); 1067 1068 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1069 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1070 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1071 sc->sc_flags |= CBB_CARDEXIST; 1072 /* call pccard interrupt handler here */ 1073 if (sockstate & CB_SOCKET_STAT_16BIT) { 1074 /* 16-bit card found */ 1075 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1076 cardslot_event_throw(sc->sc_csc, 1077 CARDSLOT_EVENT_INSERTION_16); 1078 } else if (sockstate & CB_SOCKET_STAT_CB) { 1079 /* cardbus card found */ 1080 /* cardbus_attach_card(sc->sc_csc); */ 1081 cardslot_event_throw(sc->sc_csc, 1082 CARDSLOT_EVENT_INSERTION_CB); 1083 } else { 1084 /* who are you? */ 1085 } 1086 } else { 1087 callout_reset(&sc->sc_insert_ch, hz / 10, 1088 pci113x_insert, sc); 1089 } 1090 } 1091 1092 #define PCCBB_PCMCIA_OFFSET 0x800 1093 static u_int8_t 1094 pccbb_pcmcia_read(ph, reg) 1095 struct pcic_handle *ph; 1096 int reg; 1097 { 1098 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1099 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1100 1101 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1102 PCCBB_PCMCIA_OFFSET + reg); 1103 } 1104 1105 static void 1106 pccbb_pcmcia_write(ph, reg, val) 1107 struct pcic_handle *ph; 1108 int reg; 1109 u_int8_t val; 1110 { 1111 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1112 val); 1113 1114 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1115 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1116 } 1117 1118 /* 1119 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1120 */ 1121 STATIC int 1122 pccbb_ctrl(ct, command) 1123 cardbus_chipset_tag_t ct; 1124 int command; 1125 { 1126 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1127 1128 switch (command) { 1129 case CARDBUS_CD: 1130 if (2 == pccbb_detect_card(sc)) { 1131 int retval = 0; 1132 int status = cb_detect_voltage(sc); 1133 if (PCCARD_VCC_5V & status) { 1134 retval |= CARDBUS_5V_CARD; 1135 } 1136 if (PCCARD_VCC_3V & status) { 1137 retval |= CARDBUS_3V_CARD; 1138 } 1139 if (PCCARD_VCC_XV & status) { 1140 retval |= CARDBUS_XV_CARD; 1141 } 1142 if (PCCARD_VCC_YV & status) { 1143 retval |= CARDBUS_YV_CARD; 1144 } 1145 return retval; 1146 } else { 1147 return 0; 1148 } 1149 break; 1150 case CARDBUS_RESET: 1151 return cb_reset(sc); 1152 break; 1153 case CARDBUS_IO_ENABLE: /* fallthrough */ 1154 case CARDBUS_IO_DISABLE: /* fallthrough */ 1155 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1156 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1157 case CARDBUS_BM_ENABLE: /* fallthrough */ 1158 case CARDBUS_BM_DISABLE: /* fallthrough */ 1159 return pccbb_cardenable(sc, command); 1160 break; 1161 } 1162 1163 return 0; 1164 } 1165 1166 /* 1167 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1168 * This function returns true when it succeeds and returns false when 1169 * it fails. 1170 */ 1171 STATIC int 1172 pccbb_power(ct, command) 1173 cardbus_chipset_tag_t ct; 1174 int command; 1175 { 1176 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1177 1178 u_int32_t status, sock_ctrl; 1179 bus_space_tag_t memt = sc->sc_base_memt; 1180 bus_space_handle_t memh = sc->sc_base_memh; 1181 1182 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1183 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1184 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1185 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1186 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1187 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1188 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1189 "UNKNOWN", 1190 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1191 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1192 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1193 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1194 "UNKNOWN", command)); 1195 1196 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1197 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1198 1199 switch (command & CARDBUS_VCCMASK) { 1200 case CARDBUS_VCC_UC: 1201 break; 1202 case CARDBUS_VCC_5V: 1203 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1204 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1205 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1206 } else { 1207 printf("%s: BAD voltage request: no 5 V card\n", 1208 sc->sc_dev.dv_xname); 1209 } 1210 break; 1211 case CARDBUS_VCC_3V: 1212 if (CB_SOCKET_STAT_3VCARD & status) { 1213 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1214 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1215 } else { 1216 printf("%s: BAD voltage request: no 3.3 V card\n", 1217 sc->sc_dev.dv_xname); 1218 } 1219 break; 1220 case CARDBUS_VCC_0V: 1221 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1222 break; 1223 default: 1224 return 0; /* power NEVER changed */ 1225 break; 1226 } 1227 1228 switch (command & CARDBUS_VPPMASK) { 1229 case CARDBUS_VPP_UC: 1230 break; 1231 case CARDBUS_VPP_0V: 1232 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1233 break; 1234 case CARDBUS_VPP_VCC: 1235 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1236 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1237 break; 1238 case CARDBUS_VPP_12V: 1239 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1240 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1241 break; 1242 } 1243 1244 #if 0 1245 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1246 #endif 1247 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1248 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1249 1250 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1251 printf 1252 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1253 sc->sc_dev.dv_xname, sock_ctrl, status); 1254 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1255 (command & CARDBUS_VCCMASK) == 1256 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1257 CARDBUS_VCCMASK) == 1258 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1259 CARDBUS_VCCMASK) == 1260 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1261 CARDBUS_VCCMASK) == 1262 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1263 CARDBUS_VCCMASK) == 1264 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1265 CARDBUS_VCCMASK) == 1266 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1267 (command & CARDBUS_VPPMASK) == 1268 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1269 CARDBUS_VPPMASK) == 1270 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1271 CARDBUS_VPPMASK) == 1272 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1273 CARDBUS_VPPMASK) == 1274 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1275 #if 0 1276 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1277 u_int32_t force = 1278 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1279 /* Reset Bad Vcc request */ 1280 force &= ~CB_SOCKET_FORCE_BADVCC; 1281 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1282 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1283 CB_SOCKET_STAT)); 1284 return 1; 1285 } 1286 #endif 1287 return 0; 1288 } 1289 1290 /* 1291 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1292 * time is 20 ms, some PC-Card bridge requires longer duration. 1293 */ 1294 delay(300 * 1000); 1295 1296 return 1; /* power changed correctly */ 1297 } 1298 1299 #if defined CB_PCMCIA_POLL 1300 struct cb_poll_str { 1301 void *arg; 1302 int (*func) __P((void *)); 1303 int level; 1304 pccard_chipset_tag_t ct; 1305 int count; 1306 struct callout poll_ch; 1307 }; 1308 1309 static struct cb_poll_str cb_poll[10]; 1310 static int cb_poll_n = 0; 1311 1312 static void cb_pcmcia_poll __P((void *arg)); 1313 1314 static void 1315 cb_pcmcia_poll(arg) 1316 void *arg; 1317 { 1318 struct cb_poll_str *poll = arg; 1319 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1320 struct pccbb_softc *sc = psc->cpc_parent; 1321 int s; 1322 u_int32_t spsr; /* socket present-state reg */ 1323 1324 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1325 switch (poll->level) { 1326 case IPL_NET: 1327 s = splnet(); 1328 break; 1329 case IPL_BIO: 1330 s = splbio(); 1331 break; 1332 case IPL_TTY: /* fallthrough */ 1333 default: 1334 s = spltty(); 1335 break; 1336 } 1337 1338 spsr = 1339 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1340 CB_SOCKET_STAT); 1341 1342 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1343 if (!(spsr & 0x40)) { /* CINT low */ 1344 #else 1345 if (1) { 1346 #endif 1347 if ((*poll->func) (poll->arg) == 1) { 1348 ++poll->count; 1349 printf("intr: reported from poller, 0x%x\n", spsr); 1350 #if defined LEVEL2 1351 } else { 1352 printf("intr: miss! 0x%x\n", spsr); 1353 #endif 1354 } 1355 } 1356 splx(s); 1357 } 1358 #endif /* defined CB_PCMCIA_POLL */ 1359 1360 /* 1361 * static int pccbb_detect_card(struct pccbb_softc *sc) 1362 * return value: 0 if no card exists. 1363 * 1 if 16-bit card exists. 1364 * 2 if cardbus card exists. 1365 */ 1366 static int 1367 pccbb_detect_card(sc) 1368 struct pccbb_softc *sc; 1369 { 1370 bus_space_handle_t base_memh = sc->sc_base_memh; 1371 bus_space_tag_t base_memt = sc->sc_base_memt; 1372 u_int32_t sockstat = 1373 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1374 int retval = 0; 1375 1376 /* CD1 and CD2 asserted */ 1377 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1378 /* card must be present */ 1379 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1380 /* NOTACARD DEASSERTED */ 1381 if (CB_SOCKET_STAT_CB & sockstat) { 1382 /* CardBus mode */ 1383 retval = 2; 1384 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1385 /* 16-bit mode */ 1386 retval = 1; 1387 } 1388 } 1389 } 1390 return retval; 1391 } 1392 1393 /* 1394 * STATIC int cb_reset(struct pccbb_softc *sc) 1395 * This function resets CardBus card. 1396 */ 1397 STATIC int 1398 cb_reset(sc) 1399 struct pccbb_softc *sc; 1400 { 1401 /* 1402 * Reset Assert at least 20 ms 1403 * Some machines request longer duration. 1404 */ 1405 int reset_duration = 1406 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1407 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1408 1409 /* Reset bit Assert (bit 6 at 0x3E) */ 1410 bcr |= CB_BCR_RESET_ENABLE; 1411 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1412 delay(reset_duration); 1413 1414 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1415 /* Reset bit Deassert (bit 6 at 0x3E) */ 1416 bcr &= ~CB_BCR_RESET_ENABLE; 1417 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1418 delay(reset_duration); 1419 } 1420 /* No card found on the slot. Keep Reset. */ 1421 return 1; 1422 } 1423 1424 /* 1425 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1426 * This function detect card Voltage. 1427 */ 1428 STATIC int 1429 cb_detect_voltage(sc) 1430 struct pccbb_softc *sc; 1431 { 1432 u_int32_t psr; /* socket present-state reg */ 1433 bus_space_tag_t iot = sc->sc_base_memt; 1434 bus_space_handle_t ioh = sc->sc_base_memh; 1435 int vol = PCCARD_VCC_UKN; /* set 0 */ 1436 1437 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1438 1439 if (0x400u & psr) { 1440 vol |= PCCARD_VCC_5V; 1441 } 1442 if (0x800u & psr) { 1443 vol |= PCCARD_VCC_3V; 1444 } 1445 1446 return vol; 1447 } 1448 1449 STATIC int 1450 cbbprint(aux, pcic) 1451 void *aux; 1452 const char *pcic; 1453 { 1454 /* 1455 struct cbslot_attach_args *cba = aux; 1456 1457 if (cba->cba_slot >= 0) { 1458 printf(" slot %d", cba->cba_slot); 1459 } 1460 */ 1461 return UNCONF; 1462 } 1463 1464 /* 1465 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1466 * This function enables and disables the card 1467 */ 1468 STATIC int 1469 pccbb_cardenable(sc, function) 1470 struct pccbb_softc *sc; 1471 int function; 1472 { 1473 u_int32_t command = 1474 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1475 1476 DPRINTF(("pccbb_cardenable:")); 1477 switch (function) { 1478 case CARDBUS_IO_ENABLE: 1479 command |= PCI_COMMAND_IO_ENABLE; 1480 break; 1481 case CARDBUS_IO_DISABLE: 1482 command &= ~PCI_COMMAND_IO_ENABLE; 1483 break; 1484 case CARDBUS_MEM_ENABLE: 1485 command |= PCI_COMMAND_MEM_ENABLE; 1486 break; 1487 case CARDBUS_MEM_DISABLE: 1488 command &= ~PCI_COMMAND_MEM_ENABLE; 1489 break; 1490 case CARDBUS_BM_ENABLE: 1491 command |= PCI_COMMAND_MASTER_ENABLE; 1492 break; 1493 case CARDBUS_BM_DISABLE: 1494 command &= ~PCI_COMMAND_MASTER_ENABLE; 1495 break; 1496 default: 1497 return 0; 1498 } 1499 1500 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1501 DPRINTF((" command reg 0x%x\n", command)); 1502 return 1; 1503 } 1504 1505 #if !rbus 1506 /* 1507 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1508 */ 1509 static int 1510 pccbb_io_open(ct, win, start, end) 1511 cardbus_chipset_tag_t ct; 1512 int win; 1513 u_int32_t start, end; 1514 { 1515 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1516 int basereg; 1517 int limitreg; 1518 1519 if ((win < 0) || (win > 2)) { 1520 #if defined DIAGNOSTIC 1521 printf("cardbus_io_open: window out of range %d\n", win); 1522 #endif 1523 return 0; 1524 } 1525 1526 basereg = win * 8 + 0x2c; 1527 limitreg = win * 8 + 0x30; 1528 1529 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1530 start, basereg, end, limitreg)); 1531 1532 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1533 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1534 return 1; 1535 } 1536 1537 /* 1538 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1539 */ 1540 static int 1541 pccbb_io_close(ct, win) 1542 cardbus_chipset_tag_t ct; 1543 int win; 1544 { 1545 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1546 int basereg; 1547 int limitreg; 1548 1549 if ((win < 0) || (win > 2)) { 1550 #if defined DIAGNOSTIC 1551 printf("cardbus_io_close: window out of range %d\n", win); 1552 #endif 1553 return 0; 1554 } 1555 1556 basereg = win * 8 + 0x2c; 1557 limitreg = win * 8 + 0x30; 1558 1559 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1560 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1561 return 1; 1562 } 1563 1564 /* 1565 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1566 */ 1567 static int 1568 pccbb_mem_open(ct, win, start, end) 1569 cardbus_chipset_tag_t ct; 1570 int win; 1571 u_int32_t start, end; 1572 { 1573 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1574 int basereg; 1575 int limitreg; 1576 1577 if ((win < 0) || (win > 2)) { 1578 #if defined DIAGNOSTIC 1579 printf("cardbus_mem_open: window out of range %d\n", win); 1580 #endif 1581 return 0; 1582 } 1583 1584 basereg = win * 8 + 0x1c; 1585 limitreg = win * 8 + 0x20; 1586 1587 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1588 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1589 return 1; 1590 } 1591 1592 /* 1593 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1594 */ 1595 static int 1596 pccbb_mem_close(ct, win) 1597 cardbus_chipset_tag_t ct; 1598 int win; 1599 { 1600 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1601 int basereg; 1602 int limitreg; 1603 1604 if ((win < 0) || (win > 2)) { 1605 #if defined DIAGNOSTIC 1606 printf("cardbus_mem_close: window out of range %d\n", win); 1607 #endif 1608 return 0; 1609 } 1610 1611 basereg = win * 8 + 0x1c; 1612 limitreg = win * 8 + 0x20; 1613 1614 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1615 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1616 return 1; 1617 } 1618 #endif 1619 1620 /* 1621 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1622 * int irq, 1623 * int level, 1624 * int (* func) __P((void *)), 1625 * void *arg) 1626 * 1627 * This function registers an interrupt handler at the bridge, in 1628 * order not to call the interrupt handlers of child devices when 1629 * a card-deletion interrupt occurs. 1630 * 1631 * The arguments irq and level are not used. 1632 */ 1633 static void * 1634 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1635 cardbus_chipset_tag_t ct; 1636 int irq, level; 1637 int (*func) __P((void *)); 1638 void *arg; 1639 { 1640 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1641 1642 return pccbb_intr_establish(sc, irq, level, func, arg); 1643 } 1644 1645 1646 /* 1647 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1648 * void *ih) 1649 * 1650 * This function removes an interrupt handler pointed by ih. 1651 */ 1652 static void 1653 pccbb_cb_intr_disestablish(ct, ih) 1654 cardbus_chipset_tag_t ct; 1655 void *ih; 1656 { 1657 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1658 1659 pccbb_intr_disestablish(sc, ih); 1660 } 1661 1662 1663 /* 1664 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1665 * int irq, 1666 * int level, 1667 * int (* func) __P((void *)), 1668 * void *arg) 1669 * 1670 * This function registers an interrupt handler at the bridge, in 1671 * order not to call the interrupt handlers of child devices when 1672 * a card-deletion interrupt occurs. 1673 * 1674 * The arguments irq is not used because pccbb selects intr vector. 1675 */ 1676 static void * 1677 pccbb_intr_establish(sc, irq, level, func, arg) 1678 struct pccbb_softc *sc; 1679 int irq, level; 1680 int (*func) __P((void *)); 1681 void *arg; 1682 { 1683 struct pccbb_intrhand_list *pil, *newpil; 1684 pcireg_t reg; 1685 1686 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1687 1688 if (sc->sc_pil == NULL) { 1689 /* initialize bridge intr routing */ 1690 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1691 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1692 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1693 1694 switch (sc->sc_chipset) { 1695 case CB_TI113X: 1696 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1697 /* functional intr enabled */ 1698 reg |= PCI113X_CBCTRL_PCI_INTR; 1699 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1700 break; 1701 default: 1702 break; 1703 } 1704 } 1705 1706 /* 1707 * Allocate a room for interrupt handler structure. 1708 */ 1709 if (NULL == (newpil = 1710 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1711 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1712 return NULL; 1713 } 1714 1715 newpil->pil_func = func; 1716 newpil->pil_arg = arg; 1717 newpil->pil_level = level; 1718 newpil->pil_next = NULL; 1719 1720 if (sc->sc_pil == NULL) { 1721 sc->sc_pil = newpil; 1722 } else { 1723 for (pil = sc->sc_pil; pil->pil_next != NULL; 1724 pil = pil->pil_next); 1725 pil->pil_next = newpil; 1726 } 1727 1728 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1729 1730 return newpil; 1731 } 1732 1733 /* 1734 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1735 * void *ih) 1736 * 1737 * This function removes an interrupt handler pointed by ih. 1738 */ 1739 static void 1740 pccbb_intr_disestablish(sc, ih) 1741 struct pccbb_softc *sc; 1742 void *ih; 1743 { 1744 struct pccbb_intrhand_list *pil, **pil_prev; 1745 pcireg_t reg; 1746 1747 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1748 1749 pil_prev = &sc->sc_pil; 1750 1751 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1752 if (pil == ih) { 1753 *pil_prev = pil->pil_next; 1754 free(pil, M_DEVBUF); 1755 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1756 break; 1757 } 1758 pil_prev = &pil->pil_next; 1759 } 1760 1761 if (sc->sc_pil == NULL) { 1762 /* No interrupt handlers */ 1763 1764 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1765 1766 /* stop routing PCI intr */ 1767 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1768 reg |= CB_BCR_INTR_IREQ_ENABLE; 1769 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1770 1771 switch (sc->sc_chipset) { 1772 case CB_TI113X: 1773 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1774 /* functional intr disabled */ 1775 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1776 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1777 break; 1778 default: 1779 break; 1780 } 1781 } 1782 } 1783 1784 #if defined SHOW_REGS 1785 static void 1786 cb_show_regs(pc, tag, memt, memh) 1787 pci_chipset_tag_t pc; 1788 pcitag_t tag; 1789 bus_space_tag_t memt; 1790 bus_space_handle_t memh; 1791 { 1792 int i; 1793 printf("PCI config regs:"); 1794 for (i = 0; i < 0x50; i += 4) { 1795 if (i % 16 == 0) { 1796 printf("\n 0x%02x:", i); 1797 } 1798 printf(" %08x", pci_conf_read(pc, tag, i)); 1799 } 1800 for (i = 0x80; i < 0xb0; i += 4) { 1801 if (i % 16 == 0) { 1802 printf("\n 0x%02x:", i); 1803 } 1804 printf(" %08x", pci_conf_read(pc, tag, i)); 1805 } 1806 1807 if (memh == 0) { 1808 printf("\n"); 1809 return; 1810 } 1811 1812 printf("\nsocket regs:"); 1813 for (i = 0; i <= 0x10; i += 0x04) { 1814 printf(" %08x", bus_space_read_4(memt, memh, i)); 1815 } 1816 printf("\nExCA regs:"); 1817 for (i = 0; i < 0x08; ++i) { 1818 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1819 } 1820 printf("\n"); 1821 return; 1822 } 1823 #endif 1824 1825 /* 1826 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1827 * int busno, int devno, int function) 1828 * This is the function to make a tag to access config space of 1829 * a CardBus Card. It works same as pci_conf_read. 1830 */ 1831 static cardbustag_t 1832 pccbb_make_tag(cc, busno, devno, function) 1833 cardbus_chipset_tag_t cc; 1834 int busno, devno, function; 1835 { 1836 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1837 1838 return pci_make_tag(sc->sc_pc, busno, devno, function); 1839 } 1840 1841 static void 1842 pccbb_free_tag(cc, tag) 1843 cardbus_chipset_tag_t cc; 1844 cardbustag_t tag; 1845 { 1846 } 1847 1848 /* 1849 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1850 * cardbustag_t tag, int offset) 1851 * This is the function to read the config space of a CardBus Card. 1852 * It works same as pci_conf_read. 1853 */ 1854 static cardbusreg_t 1855 pccbb_conf_read(cc, tag, offset) 1856 cardbus_chipset_tag_t cc; 1857 cardbustag_t tag; 1858 int offset; /* register offset */ 1859 { 1860 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1861 1862 return pci_conf_read(sc->sc_pc, tag, offset); 1863 } 1864 1865 /* 1866 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1867 * int offs, cardbusreg_t val) 1868 * This is the function to write the config space of a CardBus Card. 1869 * It works same as pci_conf_write. 1870 */ 1871 static void 1872 pccbb_conf_write(cc, tag, reg, val) 1873 cardbus_chipset_tag_t cc; 1874 cardbustag_t tag; 1875 int reg; /* register offset */ 1876 cardbusreg_t val; 1877 { 1878 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1879 1880 pci_conf_write(sc->sc_pc, tag, reg, val); 1881 } 1882 1883 #if 0 1884 STATIC int 1885 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1886 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1887 int speed, int flags, 1888 bus_space_handle_t * iohp) 1889 #endif 1890 /* 1891 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1892 * bus_addr_t start, bus_size_t size, 1893 * bus_size_t align, 1894 * struct pcmcia_io_handle *pcihp 1895 * 1896 * This function only allocates I/O region for pccard. This function 1897 * never maps the allocated region to pccard I/O area. 1898 * 1899 * XXX: The interface of this function is not very good, I believe. 1900 */ 1901 STATIC int 1902 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1903 pcmcia_chipset_handle_t pch; 1904 bus_addr_t start; /* start address */ 1905 bus_size_t size; 1906 bus_size_t align; 1907 struct pcmcia_io_handle *pcihp; 1908 { 1909 struct pcic_handle *ph = (struct pcic_handle *)pch; 1910 bus_addr_t ioaddr; 1911 int flags = 0; 1912 bus_space_tag_t iot; 1913 bus_space_handle_t ioh; 1914 #if rbus 1915 rbus_tag_t rb; 1916 #endif 1917 if (align == 0) { 1918 align = size; /* XXX: funny??? */ 1919 } 1920 1921 /* 1922 * Allocate some arbitrary I/O space. 1923 */ 1924 1925 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1926 1927 #if rbus 1928 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1929 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1930 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1931 return 1; 1932 } 1933 #else 1934 if (start) { 1935 ioaddr = start; 1936 if (bus_space_map(iot, start, size, 0, &ioh)) { 1937 return 1; 1938 } 1939 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1940 (u_long) ioaddr, (u_long) size)); 1941 } else { 1942 flags |= PCMCIA_IO_ALLOCATED; 1943 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1944 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1945 size, align, 0, 0, &ioaddr, &ioh)) { 1946 /* No room be able to be get. */ 1947 return 1; 1948 } 1949 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1950 (u_long) ioaddr, (u_long) size)); 1951 } 1952 #endif 1953 1954 pcihp->iot = iot; 1955 pcihp->ioh = ioh; 1956 pcihp->addr = ioaddr; 1957 pcihp->size = size; 1958 pcihp->flags = flags; 1959 1960 return 0; 1961 } 1962 1963 /* 1964 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1965 * struct pcmcia_io_handle *pcihp) 1966 * 1967 * This function only frees I/O region for pccard. 1968 * 1969 * XXX: The interface of this function is not very good, I believe. 1970 */ 1971 void 1972 pccbb_pcmcia_io_free(pch, pcihp) 1973 pcmcia_chipset_handle_t pch; 1974 struct pcmcia_io_handle *pcihp; 1975 { 1976 #if !rbus 1977 bus_space_tag_t iot = pcihp->iot; 1978 #endif 1979 bus_space_handle_t ioh = pcihp->ioh; 1980 bus_size_t size = pcihp->size; 1981 1982 #if rbus 1983 struct pccbb_softc *sc = 1984 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1985 rbus_tag_t rb = sc->sc_rbus_iot; 1986 1987 rbus_space_free(rb, ioh, size, NULL); 1988 #else 1989 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1990 bus_space_free(iot, ioh, size); 1991 else 1992 bus_space_unmap(iot, ioh, size); 1993 #endif 1994 } 1995 1996 /* 1997 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1998 * bus_addr_t offset, bus_size_t size, 1999 * struct pcmcia_io_handle *pcihp, 2000 * int *windowp) 2001 * 2002 * This function maps the allocated I/O region to pccard. This function 2003 * never allocates any I/O region for pccard I/O area. I don't 2004 * understand why the original authors of pcmciabus separated alloc and 2005 * map. I believe the two must be unite. 2006 * 2007 * XXX: no wait timing control? 2008 */ 2009 int 2010 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2011 pcmcia_chipset_handle_t pch; 2012 int width; 2013 bus_addr_t offset; 2014 bus_size_t size; 2015 struct pcmcia_io_handle *pcihp; 2016 int *windowp; 2017 { 2018 struct pcic_handle *ph = (struct pcic_handle *)pch; 2019 bus_addr_t ioaddr = pcihp->addr + offset; 2020 int i, win; 2021 #if defined CBB_DEBUG 2022 static char *width_names[] = { "dynamic", "io8", "io16" }; 2023 #endif 2024 2025 /* Sanity check I/O handle. */ 2026 2027 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2028 panic("pccbb_pcmcia_io_map iot is bogus"); 2029 } 2030 2031 /* XXX Sanity check offset/size. */ 2032 2033 win = -1; 2034 for (i = 0; i < PCIC_IO_WINS; i++) { 2035 if ((ph->ioalloc & (1 << i)) == 0) { 2036 win = i; 2037 ph->ioalloc |= (1 << i); 2038 break; 2039 } 2040 } 2041 2042 if (win == -1) { 2043 return 1; 2044 } 2045 2046 *windowp = win; 2047 2048 /* XXX this is pretty gross */ 2049 2050 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2051 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2052 2053 /* XXX wtf is this doing here? */ 2054 2055 #if 0 2056 printf(" port 0x%lx", (u_long) ioaddr); 2057 if (size > 1) { 2058 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2059 } 2060 #endif 2061 2062 ph->io[win].addr = ioaddr; 2063 ph->io[win].size = size; 2064 ph->io[win].width = width; 2065 2066 /* actual dirty register-value changing in the function below. */ 2067 pccbb_pcmcia_do_io_map(ph, win); 2068 2069 return 0; 2070 } 2071 2072 /* 2073 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2074 * 2075 * This function changes register-value to map I/O region for pccard. 2076 */ 2077 static void 2078 pccbb_pcmcia_do_io_map(ph, win) 2079 struct pcic_handle *ph; 2080 int win; 2081 { 2082 static u_int8_t pcic_iowidth[3] = { 2083 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2084 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2085 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2086 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2087 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2088 }; 2089 2090 #define PCIC_SIA_START_LOW 0 2091 #define PCIC_SIA_START_HIGH 1 2092 #define PCIC_SIA_STOP_LOW 2 2093 #define PCIC_SIA_STOP_HIGH 3 2094 2095 int regbase_win = 0x8 + win * 0x04; 2096 u_int8_t ioctl, enable; 2097 2098 DPRINTF( 2099 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2100 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2101 ph->io[win].width * 8)); 2102 2103 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2104 ph->io[win].addr & 0xff); 2105 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2106 (ph->io[win].addr >> 8) & 0xff); 2107 2108 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2109 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2110 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2111 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2112 2113 ioctl = Pcic_read(ph, PCIC_IOCTL); 2114 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2115 switch (win) { 2116 case 0: 2117 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2118 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2119 PCIC_IOCTL_IO0_DATASIZE_MASK); 2120 ioctl |= pcic_iowidth[ph->io[win].width]; 2121 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2122 break; 2123 case 1: 2124 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2125 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2126 PCIC_IOCTL_IO1_DATASIZE_MASK); 2127 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2128 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2129 break; 2130 } 2131 Pcic_write(ph, PCIC_IOCTL, ioctl); 2132 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2133 #if defined CBB_DEBUG 2134 { 2135 u_int8_t start_low = 2136 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2137 u_int8_t start_high = 2138 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2139 u_int8_t stop_low = 2140 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2141 u_int8_t stop_high = 2142 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2143 printf 2144 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2145 start_low, start_high, stop_low, stop_high, ioctl, enable); 2146 } 2147 #endif 2148 } 2149 2150 /* 2151 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2152 * 2153 * This function unmaps I/O region. No return value. 2154 */ 2155 STATIC void 2156 pccbb_pcmcia_io_unmap(pch, win) 2157 pcmcia_chipset_handle_t pch; 2158 int win; 2159 { 2160 struct pcic_handle *ph = (struct pcic_handle *)pch; 2161 int reg; 2162 2163 if (win >= PCIC_IO_WINS || win < 0) { 2164 panic("pccbb_pcmcia_io_unmap: window out of range"); 2165 } 2166 2167 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2168 switch (win) { 2169 case 0: 2170 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2171 break; 2172 case 1: 2173 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2174 break; 2175 } 2176 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2177 2178 ph->ioalloc &= ~(1 << win); 2179 } 2180 2181 /* 2182 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2183 * 2184 * This function enables the card. All information is stored in 2185 * the first argument, pcmcia_chipset_handle_t. 2186 */ 2187 static void 2188 pccbb_pcmcia_wait_ready(ph) 2189 struct pcic_handle *ph; 2190 { 2191 int i; 2192 2193 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2194 Pcic_read(ph, PCIC_IF_STATUS))); 2195 2196 for (i = 0; i < 10000; i++) { 2197 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2198 return; 2199 } 2200 delay(500); 2201 #ifdef CBB_DEBUG 2202 if ((i > 5000) && (i % 100 == 99)) 2203 printf("."); 2204 #endif 2205 } 2206 2207 #ifdef DIAGNOSTIC 2208 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2209 Pcic_read(ph, PCIC_IF_STATUS)); 2210 #endif 2211 } 2212 2213 /* 2214 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2215 * 2216 * This function enables the card. All information is stored in 2217 * the first argument, pcmcia_chipset_handle_t. 2218 */ 2219 STATIC void 2220 pccbb_pcmcia_socket_enable(pch) 2221 pcmcia_chipset_handle_t pch; 2222 { 2223 struct pcic_handle *ph = (struct pcic_handle *)pch; 2224 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2225 int cardtype, win; 2226 u_int8_t power, intr; 2227 pcireg_t spsr; 2228 int voltage; 2229 2230 /* this bit is mostly stolen from pcic_attach_card */ 2231 2232 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2233 2234 /* get card Vcc info */ 2235 2236 spsr = 2237 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2238 CB_SOCKET_STAT); 2239 if (spsr & CB_SOCKET_STAT_5VCARD) { 2240 DPRINTF(("5V card\n")); 2241 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2242 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2243 DPRINTF(("3V card\n")); 2244 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2245 } else { 2246 printf("?V card, 0x%x\n", spsr); /* XXX */ 2247 return; 2248 } 2249 2250 /* disable socket i/o: negate output enable bit */ 2251 2252 power = 0; 2253 Pcic_write(ph, PCIC_PWRCTL, power); 2254 2255 /* power down the socket to reset it, clear the card reset pin */ 2256 2257 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2258 2259 /* 2260 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2261 * we are changing Vcc (Toff). 2262 */ 2263 /* delay(300*1000); too much */ 2264 2265 /* assert reset bit */ 2266 intr = Pcic_read(ph, PCIC_INTR); 2267 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2268 Pcic_write(ph, PCIC_INTR, intr); 2269 2270 /* power up the socket and output enable */ 2271 power = Pcic_read(ph, PCIC_PWRCTL); 2272 power |= PCIC_PWRCTL_OE; 2273 Pcic_write(ph, PCIC_PWRCTL, power); 2274 pccbb_power(sc, voltage); 2275 2276 /* 2277 * hold RESET at least 10us. 2278 */ 2279 delay(10); 2280 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2281 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2282 2283 /* clear the reset flag */ 2284 2285 intr |= PCIC_INTR_RESET; 2286 Pcic_write(ph, PCIC_INTR, intr); 2287 2288 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2289 2290 delay(20000); 2291 2292 /* wait for the chip to finish initializing */ 2293 2294 pccbb_pcmcia_wait_ready(ph); 2295 2296 /* zero out the address windows */ 2297 2298 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2299 2300 /* set the card type */ 2301 2302 cardtype = pcmcia_card_gettype(ph->pcmcia); 2303 2304 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2305 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2306 Pcic_write(ph, PCIC_INTR, intr); 2307 2308 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2309 ph->ph_parent->dv_xname, ph->sock, 2310 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2311 2312 /* reinstall all the memory and io mappings */ 2313 2314 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2315 if (ph->memalloc & (1 << win)) { 2316 pccbb_pcmcia_do_mem_map(ph, win); 2317 } 2318 } 2319 2320 for (win = 0; win < PCIC_IO_WINS; ++win) { 2321 if (ph->ioalloc & (1 << win)) { 2322 pccbb_pcmcia_do_io_map(ph, win); 2323 } 2324 } 2325 } 2326 2327 /* 2328 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2329 * 2330 * This function disables the card. All information is stored in 2331 * the first argument, pcmcia_chipset_handle_t. 2332 */ 2333 STATIC void 2334 pccbb_pcmcia_socket_disable(pch) 2335 pcmcia_chipset_handle_t pch; 2336 { 2337 struct pcic_handle *ph = (struct pcic_handle *)pch; 2338 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2339 u_int8_t power, intr; 2340 2341 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2342 2343 /* reset signal asserting... */ 2344 2345 intr = Pcic_read(ph, PCIC_INTR); 2346 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2347 Pcic_write(ph, PCIC_INTR, intr); 2348 delay(2 * 1000); 2349 2350 /* power down the socket */ 2351 power = Pcic_read(ph, PCIC_PWRCTL); 2352 power &= ~PCIC_PWRCTL_OE; 2353 Pcic_write(ph, PCIC_PWRCTL, power); 2354 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2355 /* 2356 * wait 300ms until power fails (Tpf). 2357 */ 2358 delay(300 * 1000); 2359 } 2360 2361 /* 2362 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2363 * 2364 * This function detects whether a card is in the slot or not. 2365 * If a card is inserted, return 1. Otherwise, return 0. 2366 */ 2367 STATIC int 2368 pccbb_pcmcia_card_detect(pch) 2369 pcmcia_chipset_handle_t pch; 2370 { 2371 struct pcic_handle *ph = (struct pcic_handle *)pch; 2372 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2373 2374 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2375 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2376 } 2377 2378 #if 0 2379 STATIC int 2380 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2381 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2382 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2383 #endif 2384 /* 2385 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2386 * bus_size_t size, 2387 * struct pcmcia_mem_handle *pcmhp) 2388 * 2389 * This function only allocates memory region for pccard. This 2390 * function never maps the allocated region to pccard memory area. 2391 * 2392 * XXX: Why the argument of start address is not in? 2393 */ 2394 STATIC int 2395 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2396 pcmcia_chipset_handle_t pch; 2397 bus_size_t size; 2398 struct pcmcia_mem_handle *pcmhp; 2399 { 2400 struct pcic_handle *ph = (struct pcic_handle *)pch; 2401 bus_space_handle_t memh; 2402 bus_addr_t addr; 2403 bus_size_t sizepg; 2404 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2405 #if rbus 2406 rbus_tag_t rb; 2407 #endif 2408 2409 /* out of sc->memh, allocate as many pages as necessary */ 2410 2411 /* convert size to PCIC pages */ 2412 /* 2413 * This is not enough; when the requested region is on the page 2414 * boundaries, this may calculate wrong result. 2415 */ 2416 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2417 #if 0 2418 if (sizepg > PCIC_MAX_MEM_PAGES) { 2419 return 1; 2420 } 2421 #endif 2422 2423 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2424 return 1; 2425 } 2426 2427 addr = 0; /* XXX gcc -Wuninitialized */ 2428 2429 #if rbus 2430 rb = sc->sc_rbus_memt; 2431 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2432 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2433 &addr, &memh)) { 2434 return 1; 2435 } 2436 #else 2437 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2438 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2439 0, /* boundary */ 2440 0, /* flags */ 2441 &addr, &memh)) { 2442 return 1; 2443 } 2444 #endif 2445 2446 DPRINTF( 2447 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2448 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2449 2450 pcmhp->memt = sc->sc_memt; 2451 pcmhp->memh = memh; 2452 pcmhp->addr = addr; 2453 pcmhp->size = size; 2454 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2455 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2456 pcmhp->mhandle = 0; 2457 /* No offset??? Funny. */ 2458 2459 return 0; 2460 } 2461 2462 /* 2463 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2464 * struct pcmcia_mem_handle *pcmhp) 2465 * 2466 * This function release the memory space allocated by the function 2467 * pccbb_pcmcia_mem_alloc(). 2468 */ 2469 STATIC void 2470 pccbb_pcmcia_mem_free(pch, pcmhp) 2471 pcmcia_chipset_handle_t pch; 2472 struct pcmcia_mem_handle *pcmhp; 2473 { 2474 #if rbus 2475 struct pcic_handle *ph = (struct pcic_handle *)pch; 2476 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2477 2478 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2479 #else 2480 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2481 #endif 2482 } 2483 2484 /* 2485 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2486 * 2487 * This function release the memory space allocated by the function 2488 * pccbb_pcmcia_mem_alloc(). 2489 */ 2490 STATIC void 2491 pccbb_pcmcia_do_mem_map(ph, win) 2492 struct pcic_handle *ph; 2493 int win; 2494 { 2495 int regbase_win; 2496 bus_addr_t phys_addr; 2497 bus_addr_t phys_end; 2498 2499 #define PCIC_SMM_START_LOW 0 2500 #define PCIC_SMM_START_HIGH 1 2501 #define PCIC_SMM_STOP_LOW 2 2502 #define PCIC_SMM_STOP_HIGH 3 2503 #define PCIC_CMA_LOW 4 2504 #define PCIC_CMA_HIGH 5 2505 2506 u_int8_t start_low, start_high = 0; 2507 u_int8_t stop_low, stop_high; 2508 u_int8_t off_low, off_high; 2509 u_int8_t mem_window; 2510 int reg; 2511 2512 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2513 int mem8 = 2514 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2515 || (kind == PCMCIA_MEM_ATTR); 2516 2517 regbase_win = 0x10 + win * 0x08; 2518 2519 phys_addr = ph->mem[win].addr; 2520 phys_end = phys_addr + ph->mem[win].size; 2521 2522 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2523 phys_addr, phys_end, ph->mem[win].offset)); 2524 2525 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2526 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2527 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2528 2529 /* bit 19:12 */ 2530 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2531 /* bit 23:20 and bit 7 on */ 2532 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2533 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2534 /* bit 31:24, for 32-bit address */ 2535 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2536 2537 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2538 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2539 2540 if (((struct pccbb_softc *)ph-> 2541 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2542 Pcic_write(ph, 0x40 + win, mem_window); 2543 } 2544 2545 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2546 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2547 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2548 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2549 2550 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2551 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2552 2553 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2554 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2555 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2556 | ((kind == PCMCIA_MEM_ATTR) ? 2557 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2558 2559 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2560 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2561 2562 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2563 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2564 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2565 2566 #if defined CBB_DEBUG 2567 { 2568 int r1, r2, r3, r4, r5, r6, r7 = 0; 2569 2570 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2571 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2572 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2573 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2574 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2575 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2576 if (((struct pccbb_softc *)(ph-> 2577 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2578 r7 = Pcic_read(ph, 0x40 + win); 2579 } 2580 2581 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2582 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2583 if (((struct pccbb_softc *)(ph-> 2584 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2585 DPRINTF((" %02x", r7)); 2586 } 2587 DPRINTF(("\n")); 2588 } 2589 #endif 2590 } 2591 2592 /* 2593 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2594 * bus_addr_t card_addr, bus_size_t size, 2595 * struct pcmcia_mem_handle *pcmhp, 2596 * bus_addr_t *offsetp, int *windowp) 2597 * 2598 * This function maps memory space allocated by the function 2599 * pccbb_pcmcia_mem_alloc(). 2600 */ 2601 STATIC int 2602 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2603 pcmcia_chipset_handle_t pch; 2604 int kind; 2605 bus_addr_t card_addr; 2606 bus_size_t size; 2607 struct pcmcia_mem_handle *pcmhp; 2608 bus_addr_t *offsetp; 2609 int *windowp; 2610 { 2611 struct pcic_handle *ph = (struct pcic_handle *)pch; 2612 bus_addr_t busaddr; 2613 long card_offset; 2614 int win; 2615 2616 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2617 if ((ph->memalloc & (1 << win)) == 0) { 2618 ph->memalloc |= (1 << win); 2619 break; 2620 } 2621 } 2622 2623 if (win == PCIC_MEM_WINS) { 2624 return 1; 2625 } 2626 2627 *windowp = win; 2628 2629 /* XXX this is pretty gross */ 2630 2631 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2632 panic("pccbb_pcmcia_mem_map memt is bogus"); 2633 } 2634 2635 busaddr = pcmhp->addr; 2636 2637 /* 2638 * compute the address offset to the pcmcia address space for the 2639 * pcic. this is intentionally signed. The masks and shifts below 2640 * will cause TRT to happen in the pcic registers. Deal with making 2641 * sure the address is aligned, and return the alignment offset. 2642 */ 2643 2644 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2645 card_addr -= *offsetp; 2646 2647 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2648 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2649 (u_long) card_addr)); 2650 2651 /* 2652 * include the offset in the size, and decrement size by one, since 2653 * the hw wants start/stop 2654 */ 2655 size += *offsetp - 1; 2656 2657 card_offset = (((long)card_addr) - ((long)busaddr)); 2658 2659 ph->mem[win].addr = busaddr; 2660 ph->mem[win].size = size; 2661 ph->mem[win].offset = card_offset; 2662 ph->mem[win].kind = kind; 2663 2664 pccbb_pcmcia_do_mem_map(ph, win); 2665 2666 return 0; 2667 } 2668 2669 /* 2670 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2671 * int window) 2672 * 2673 * This function unmaps memory space which mapped by the function 2674 * pccbb_pcmcia_mem_map(). 2675 */ 2676 STATIC void 2677 pccbb_pcmcia_mem_unmap(pch, window) 2678 pcmcia_chipset_handle_t pch; 2679 int window; 2680 { 2681 struct pcic_handle *ph = (struct pcic_handle *)pch; 2682 int reg; 2683 2684 if (window >= PCIC_MEM_WINS) { 2685 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2686 } 2687 2688 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2689 reg &= ~(1 << window); 2690 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2691 2692 ph->memalloc &= ~(1 << window); 2693 } 2694 2695 #if defined PCCBB_PCMCIA_POLL 2696 struct pccbb_poll_str { 2697 void *arg; 2698 int (*func) __P((void *)); 2699 int level; 2700 struct pcic_handle *ph; 2701 int count; 2702 int num; 2703 struct callout poll_ch; 2704 }; 2705 2706 static struct pccbb_poll_str pccbb_poll[10]; 2707 static int pccbb_poll_n = 0; 2708 2709 static void pccbb_pcmcia_poll __P((void *arg)); 2710 2711 static void 2712 pccbb_pcmcia_poll(arg) 2713 void *arg; 2714 { 2715 struct pccbb_poll_str *poll = arg; 2716 struct pcic_handle *ph = poll->ph; 2717 struct pccbb_softc *sc = ph->sc; 2718 int s; 2719 u_int32_t spsr; /* socket present-state reg */ 2720 2721 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2722 switch (poll->level) { 2723 case IPL_NET: 2724 s = splnet(); 2725 break; 2726 case IPL_BIO: 2727 s = splbio(); 2728 break; 2729 case IPL_TTY: /* fallthrough */ 2730 default: 2731 s = spltty(); 2732 break; 2733 } 2734 2735 spsr = 2736 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2737 CB_SOCKET_STAT); 2738 2739 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2740 if (!(spsr & 0x40)) /* CINT low */ 2741 #else 2742 if (1) 2743 #endif 2744 { 2745 if ((*poll->func) (poll->arg) > 0) { 2746 ++poll->count; 2747 // printf("intr: reported from poller, 0x%x\n", spsr); 2748 #if defined LEVEL2 2749 } else { 2750 printf("intr: miss! 0x%x\n", spsr); 2751 #endif 2752 } 2753 } 2754 splx(s); 2755 } 2756 #endif /* defined CB_PCMCIA_POLL */ 2757 2758 /* 2759 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2760 * struct pcmcia_function *pf, 2761 * int ipl, 2762 * int (*func)(void *), 2763 * void *arg); 2764 * 2765 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2766 */ 2767 STATIC void * 2768 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2769 pcmcia_chipset_handle_t pch; 2770 struct pcmcia_function *pf; 2771 int ipl; 2772 int (*func) __P((void *)); 2773 void *arg; 2774 { 2775 struct pcic_handle *ph = (struct pcic_handle *)pch; 2776 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2777 2778 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2779 /* what should I do? */ 2780 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2781 DPRINTF( 2782 ("%s does not provide edge nor pulse interrupt\n", 2783 sc->sc_dev.dv_xname)); 2784 return NULL; 2785 } 2786 /* 2787 * XXX Noooooo! The interrupt flag must set properly!! 2788 * dumb pcmcia driver!! 2789 */ 2790 } 2791 2792 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2793 } 2794 2795 /* 2796 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2797 * void *ih) 2798 * 2799 * This function disables PC-Card interrupt. 2800 */ 2801 STATIC void 2802 pccbb_pcmcia_intr_disestablish(pch, ih) 2803 pcmcia_chipset_handle_t pch; 2804 void *ih; 2805 { 2806 struct pcic_handle *ph = (struct pcic_handle *)pch; 2807 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2808 2809 pccbb_intr_disestablish(sc, ih); 2810 } 2811 2812 #if rbus 2813 /* 2814 * static int 2815 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2816 * bus_addr_t addr, bus_size_t size, 2817 * bus_addr_t mask, bus_size_t align, 2818 * int flags, bus_addr_t *addrp; 2819 * bus_space_handle_t *bshp) 2820 * 2821 * This function allocates a portion of memory or io space for 2822 * clients. This function is called from CardBus card drivers. 2823 */ 2824 static int 2825 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2826 cardbus_chipset_tag_t ct; 2827 rbus_tag_t rb; 2828 bus_addr_t addr; 2829 bus_size_t size; 2830 bus_addr_t mask; 2831 bus_size_t align; 2832 int flags; 2833 bus_addr_t *addrp; 2834 bus_space_handle_t *bshp; 2835 { 2836 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2837 2838 DPRINTF( 2839 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2840 addr, size, mask, align)); 2841 2842 if (align == 0) { 2843 align = size; 2844 } 2845 2846 if (rb->rb_bt == sc->sc_memt) { 2847 if (align < 16) { 2848 return 1; 2849 } 2850 } else if (rb->rb_bt == sc->sc_iot) { 2851 if (align < 4) { 2852 return 1; 2853 } 2854 /* XXX: hack for avoiding ISA image */ 2855 if (mask < 0x0100) { 2856 mask = 0x3ff; 2857 addr = 0x300; 2858 } 2859 2860 } else { 2861 DPRINTF( 2862 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2863 rb->rb_bt)); 2864 return 1; 2865 /* XXX: panic here? */ 2866 } 2867 2868 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2869 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2870 return 1; 2871 } 2872 2873 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2874 2875 return 0; 2876 } 2877 2878 /* 2879 * static int 2880 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2881 * bus_space_handle_t *bshp, bus_size_t size); 2882 * 2883 * This function is called from CardBus card drivers. 2884 */ 2885 static int 2886 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2887 cardbus_chipset_tag_t ct; 2888 rbus_tag_t rb; 2889 bus_space_handle_t bsh; 2890 bus_size_t size; 2891 { 2892 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2893 bus_space_tag_t bt = rb->rb_bt; 2894 2895 pccbb_close_win(sc, bt, bsh, size); 2896 2897 if (bt == sc->sc_memt) { 2898 } else if (bt == sc->sc_iot) { 2899 } else { 2900 return 1; 2901 /* XXX: panic here? */ 2902 } 2903 2904 return rbus_space_free(rb, bsh, size, NULL); 2905 } 2906 #endif /* rbus */ 2907 2908 #if rbus 2909 2910 static int 2911 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2912 struct pccbb_softc *sc; 2913 bus_space_tag_t bst; 2914 bus_addr_t addr; 2915 bus_size_t size; 2916 bus_space_handle_t bsh; 2917 int flags; 2918 { 2919 struct pccbb_win_chain_head *head; 2920 bus_addr_t align; 2921 2922 head = &sc->sc_iowindow; 2923 align = 0x04; 2924 if (sc->sc_memt == bst) { 2925 head = &sc->sc_memwindow; 2926 align = 0x1000; 2927 DPRINTF(("using memory window, %x %x %x\n\n", 2928 sc->sc_iot, sc->sc_memt, bst)); 2929 } 2930 2931 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2932 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2933 sc->sc_dev.dv_xname, 2934 (head == &sc->sc_memwindow) ? "mem" : "io"); 2935 } 2936 pccbb_winset(align, sc, bst); 2937 2938 return 0; 2939 } 2940 2941 static int 2942 pccbb_close_win(sc, bst, bsh, size) 2943 struct pccbb_softc *sc; 2944 bus_space_tag_t bst; 2945 bus_space_handle_t bsh; 2946 bus_size_t size; 2947 { 2948 struct pccbb_win_chain_head *head; 2949 bus_addr_t align; 2950 2951 head = &sc->sc_iowindow; 2952 align = 0x04; 2953 if (sc->sc_memt == bst) { 2954 head = &sc->sc_memwindow; 2955 align = 0x1000; 2956 } 2957 2958 if (pccbb_winlist_delete(head, bsh, size)) { 2959 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2960 sc->sc_dev.dv_xname, 2961 (head == &sc->sc_memwindow) ? "mem" : "io"); 2962 } 2963 pccbb_winset(align, sc, bst); 2964 2965 return 0; 2966 } 2967 2968 static int 2969 pccbb_winlist_insert(head, start, size, bsh, flags) 2970 struct pccbb_win_chain_head *head; 2971 bus_addr_t start; 2972 bus_size_t size; 2973 bus_space_handle_t bsh; 2974 int flags; 2975 { 2976 struct pccbb_win_chain *chainp, *elem; 2977 2978 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2979 M_NOWAIT)) == NULL) 2980 return (1); /* fail */ 2981 2982 elem->wc_start = start; 2983 elem->wc_end = start + (size - 1); 2984 elem->wc_handle = bsh; 2985 elem->wc_flags = flags; 2986 2987 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2988 chainp = TAILQ_NEXT(chainp, wc_list)) { 2989 if (chainp->wc_end < start) 2990 continue; 2991 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2992 return (0); 2993 } 2994 2995 TAILQ_INSERT_TAIL(head, elem, wc_list); 2996 return (0); 2997 } 2998 2999 static int 3000 pccbb_winlist_delete(head, bsh, size) 3001 struct pccbb_win_chain_head *head; 3002 bus_space_handle_t bsh; 3003 bus_size_t size; 3004 { 3005 struct pccbb_win_chain *chainp; 3006 3007 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3008 chainp = TAILQ_NEXT(chainp, wc_list)) { 3009 if (chainp->wc_handle != bsh) 3010 continue; 3011 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3012 printf("pccbb_winlist_delete: window 0x%lx size " 3013 "inconsistent: 0x%lx, 0x%lx\n", 3014 chainp->wc_start, 3015 chainp->wc_end - chainp->wc_start, 3016 size - 1); 3017 return 1; 3018 } 3019 3020 TAILQ_REMOVE(head, chainp, wc_list); 3021 free(chainp, M_DEVBUF); 3022 3023 return 0; 3024 } 3025 3026 return 1; /* fail: no candidate to remove */ 3027 } 3028 3029 static void 3030 pccbb_winset(align, sc, bst) 3031 bus_addr_t align; 3032 struct pccbb_softc *sc; 3033 bus_space_tag_t bst; 3034 { 3035 pci_chipset_tag_t pc; 3036 pcitag_t tag; 3037 bus_addr_t mask = ~(align - 1); 3038 struct { 3039 cardbusreg_t win_start; 3040 cardbusreg_t win_limit; 3041 int win_flags; 3042 } win[2]; 3043 struct pccbb_win_chain *chainp; 3044 int offs; 3045 3046 win[0].win_start = 0xffffffff; 3047 win[0].win_limit = 0; 3048 win[1].win_start = 0xffffffff; 3049 win[1].win_limit = 0; 3050 3051 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3052 offs = 0x2c; 3053 if (sc->sc_memt == bst) { 3054 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3055 offs = 0x1c; 3056 } 3057 3058 if (chainp != NULL) { 3059 win[0].win_start = chainp->wc_start & mask; 3060 win[0].win_limit = chainp->wc_end & mask; 3061 win[0].win_flags = chainp->wc_flags; 3062 chainp = TAILQ_NEXT(chainp, wc_list); 3063 } 3064 3065 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3066 if (win[1].win_start == 0xffffffff) { 3067 /* window 1 is not used */ 3068 if ((win[0].win_flags == chainp->wc_flags) && 3069 (win[0].win_limit + align >= 3070 (chainp->wc_start & mask))) { 3071 /* concatenate */ 3072 win[0].win_limit = chainp->wc_end & mask; 3073 } else { 3074 /* make new window */ 3075 win[1].win_start = chainp->wc_start & mask; 3076 win[1].win_limit = chainp->wc_end & mask; 3077 win[1].win_flags = chainp->wc_flags; 3078 } 3079 continue; 3080 } 3081 3082 /* Both windows are engaged. */ 3083 if (win[0].win_flags == win[1].win_flags) { 3084 /* same flags */ 3085 if (win[0].win_flags == chainp->wc_flags) { 3086 if (win[1].win_start - (win[0].win_limit + 3087 align) < 3088 (chainp->wc_start & mask) - 3089 ((chainp->wc_end & mask) + align)) { 3090 /* 3091 * merge window 0 and 1, and set win1 3092 * to chainp 3093 */ 3094 win[0].win_limit = win[1].win_limit; 3095 win[1].win_start = 3096 chainp->wc_start & mask; 3097 win[1].win_limit = 3098 chainp->wc_end & mask; 3099 } else { 3100 win[1].win_limit = 3101 chainp->wc_end & mask; 3102 } 3103 } else { 3104 /* different flags */ 3105 3106 /* concatenate win0 and win1 */ 3107 win[0].win_limit = win[1].win_limit; 3108 /* allocate win[1] to new space */ 3109 win[1].win_start = chainp->wc_start & mask; 3110 win[1].win_limit = chainp->wc_end & mask; 3111 win[1].win_flags = chainp->wc_flags; 3112 } 3113 } else { 3114 /* the flags of win[0] and win[1] is different */ 3115 if (win[0].win_flags == chainp->wc_flags) { 3116 win[0].win_limit = chainp->wc_end & mask; 3117 /* 3118 * XXX this creates overlapping windows, so 3119 * what should the poor bridge do if one is 3120 * cachable, and the other is not? 3121 */ 3122 printf("%s: overlapping windows\n", 3123 sc->sc_dev.dv_xname); 3124 } else { 3125 win[1].win_limit = chainp->wc_end & mask; 3126 } 3127 } 3128 } 3129 3130 pc = sc->sc_pc; 3131 tag = sc->sc_tag; 3132 pci_conf_write(pc, tag, offs, win[0].win_start); 3133 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3134 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3135 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3136 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3137 pci_conf_read(pc, tag, offs), 3138 pci_conf_read(pc, tag, offs + 4) + align, 3139 pci_conf_read(pc, tag, offs + 8), 3140 pci_conf_read(pc, tag, offs + 12) + align)); 3141 3142 if (bst == sc->sc_memt) { 3143 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3144 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3145 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3146 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3147 } 3148 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3149 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3150 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3151 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3152 } 3153 } 3154 } 3155 3156 #endif /* rbus */ 3157 3158 static void 3159 pccbb_powerhook(why, arg) 3160 int why; 3161 void *arg; 3162 { 3163 struct pccbb_softc *sc = arg; 3164 u_int32_t reg; 3165 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3166 bus_space_handle_t base_memh = sc->sc_base_memh; 3167 3168 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3169 3170 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3171 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3172 if (sc->sc_pil_intr_enable) { 3173 (void)pccbbintr_function(sc); 3174 } 3175 sc->sc_pil_intr_enable = 0; 3176 3177 /* ToDo: deactivate or suspend child devices */ 3178 3179 } 3180 3181 if (why == PWR_RESUME) { 3182 /* CSC Interrupt: Card detect interrupt on */ 3183 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3184 /* Card detect intr is turned on. */ 3185 reg |= CB_SOCKET_MASK_CD; 3186 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3187 /* reset interrupt */ 3188 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3189 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3190 3191 /* 3192 * check for card insertion or removal during suspend period. 3193 * XXX: the code can't cope with card swap (remove then 3194 * insert). how can we detect such situation? 3195 */ 3196 (void)pccbbintr(sc); 3197 3198 sc->sc_pil_intr_enable = 1; 3199 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3200 3201 /* ToDo: activate or wakeup child devices */ 3202 } 3203 } 3204
Indexes created Thu Oct 16 14:10:15 GMT 2025