pccbb.c revision 1.44
1 /* $NetBSD: pccbb.c,v 1.44 2000/07/09 22:06:02 jhawk Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 93 void pccbbattach __P((struct device *, struct device *, void *)); 94 int pccbbintr __P((void *)); 95 static void pci113x_insert __P((void *)); 96 static int pccbbintr_function __P((struct pccbb_softc *)); 97 98 static int pccbb_detect_card __P((struct pccbb_softc *)); 99 100 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 101 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 102 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 103 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 104 105 STATIC int cb_reset __P((struct pccbb_softc *)); 106 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 107 STATIC int cbbprint __P((void *, const char *)); 108 109 static int cb_chipset __P((u_int32_t, int *)); 110 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 111 struct pcmciabus_attach_args *)); 112 #if 0 113 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 114 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 115 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 116 #endif 117 118 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 119 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 120 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 121 #if !rbus 122 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 123 u_int32_t)); 124 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 125 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 126 u_int32_t)); 127 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 128 #endif /* !rbus */ 129 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 130 int level, int (*ih) (void *), void *sc)); 131 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 132 133 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 static void pccbb_powerhook __P((int, void *)); 171 172 /* bus-space allocation and deallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 178 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t)); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 187 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t)); 189 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int)); 191 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 192 bus_space_handle_t, bus_size_t)); 193 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t)); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback __P((struct device *)); 201 202 #if defined SHOW_REGS 203 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 204 bus_space_tag_t memt, bus_space_handle_t memh)); 205 #endif 206 207 struct cfattach cbb_pci_ca = { 208 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 209 }; 210 211 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 212 pccbb_pcmcia_mem_alloc, 213 pccbb_pcmcia_mem_free, 214 pccbb_pcmcia_mem_map, 215 pccbb_pcmcia_mem_unmap, 216 pccbb_pcmcia_io_alloc, 217 pccbb_pcmcia_io_free, 218 pccbb_pcmcia_io_map, 219 pccbb_pcmcia_io_unmap, 220 pccbb_pcmcia_intr_establish, 221 pccbb_pcmcia_intr_disestablish, 222 pccbb_pcmcia_socket_enable, 223 pccbb_pcmcia_socket_disable, 224 pccbb_pcmcia_card_detect 225 }; 226 227 #if rbus 228 static struct cardbus_functions pccbb_funcs = { 229 pccbb_rbus_cb_space_alloc, 230 pccbb_rbus_cb_space_free, 231 pccbb_cb_intr_establish, 232 pccbb_cb_intr_disestablish, 233 pccbb_ctrl, 234 pccbb_power, 235 pccbb_make_tag, 236 pccbb_free_tag, 237 pccbb_conf_read, 238 pccbb_conf_write, 239 }; 240 #else 241 static struct cardbus_functions pccbb_funcs = { 242 pccbb_ctrl, 243 pccbb_power, 244 pccbb_mem_open, 245 pccbb_mem_close, 246 pccbb_io_open, 247 pccbb_io_close, 248 pccbb_cb_intr_establish, 249 pccbb_cb_intr_disestablish, 250 pccbb_make_tag, 251 pccbb_conf_read, 252 pccbb_conf_write, 253 }; 254 #endif 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 struct cfdata *match; 260 void *aux; 261 { 262 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 263 264 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 265 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 266 PCI_INTERFACE(pa->pa_class) == 0) { 267 return 1; 268 } 269 270 return 0; 271 } 272 273 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 274 | ((prod) << PCI_PRODUCT_SHIFT)) 275 276 struct yenta_chipinfo { 277 pcireg_t yc_id; /* vendor tag | product tag */ 278 int yc_chiptype; 279 int yc_flags; 280 } yc_chipsets[] = { 281 /* Texas Instruments chips */ 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 307 /* Ricoh chips */ 308 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 309 PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 311 PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 313 PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 315 PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 319 PCCBB_PCMCIA_MEM_32}, 320 321 /* Toshiba products */ 322 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 323 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 325 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 327 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 329 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 330 331 /* Cirrus Logic products */ 332 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 333 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 335 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 336 337 /* sentinel, or Generic chip */ 338 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 339 }; 340 341 static int 342 cb_chipset(pci_id, flagp) 343 u_int32_t pci_id; 344 int *flagp; 345 { 346 struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return (yc->yc_chiptype); 358 } 359 360 static void 361 pccbb_shutdown(void *arg) 362 { 363 struct pccbb_softc *sc = arg; 364 pcireg_t command; 365 366 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 367 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 368 0); 369 370 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 371 372 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 373 PCI_COMMAND_MASTER_ENABLE); 374 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 375 376 } 377 378 void 379 pccbbattach(parent, self, aux) 380 struct device *parent; 381 struct device *self; 382 void *aux; 383 { 384 struct pccbb_softc *sc = (void *)self; 385 struct pci_attach_args *pa = aux; 386 pci_chipset_tag_t pc = pa->pa_pc; 387 pcireg_t busreg, reg, sock_base; 388 bus_addr_t sockbase; 389 char devinfo[256]; 390 int flags; 391 392 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 393 394 pci_devinfo(pa->pa_id, 0, 0, devinfo); 395 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 396 #ifdef CBB_DEBUG 397 printf(" (chipflags %x)", flags); 398 #endif 399 printf("\n"); 400 401 TAILQ_INIT(&sc->sc_memwindow); 402 TAILQ_INIT(&sc->sc_iowindow); 403 404 #if rbus 405 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 406 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 407 #endif /* rbus */ 408 409 sc->sc_base_memh = 0; 410 411 /* 412 * MAP socket registers and ExCA registers on memory-space 413 * When no valid address is set on socket base registers (on pci 414 * config space), get it not polite way. 415 */ 416 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 417 418 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 419 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 420 /* The address must be valid. */ 421 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 422 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 423 printf("%s: can't map socket base address 0x%x\n", 424 sc->sc_dev.dv_xname, sock_base); 425 /* 426 * I think it's funny: socket base registers must be 427 * mapped on memory space, but ... 428 */ 429 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 430 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 431 NULL)) { 432 printf("%s: can't map socket base address" 433 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 434 sockbase); 435 /* give up... allocate reg space via rbus. */ 436 sc->sc_base_memh = 0; 437 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 438 } 439 } else { 440 DPRINTF(("%s: socket base address 0x%lx\n", 441 sc->sc_dev.dv_xname, sockbase)); 442 } 443 } 444 445 sc->sc_mem_start = 0; /* XXX */ 446 sc->sc_mem_end = 0xffffffff; /* XXX */ 447 448 /* 449 * When interrupt isn't routed correctly, give up probing cbb and do 450 * not kill pcic-compatible port. 451 */ 452 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 453 printf("%s: NOT USED because of unconfigured interrupt\n", 454 sc->sc_dev.dv_xname); 455 return; 456 } 457 458 /* 459 * When bus number isn't set correctly, give up using 32-bit CardBus 460 * mode. 461 */ 462 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 463 #if notyet 464 if (((busreg >> 8) & 0xff) == 0) { 465 printf("%s: CardBus support disabled because of unconfigured bus number\n", 466 sc->sc_dev.dv_xname); 467 flags |= PCCBB_PCMCIA_16BITONLY; 468 } 469 #endif 470 471 /* pccbb_machdep.c end */ 472 473 #if defined CBB_DEBUG 474 { 475 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 476 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 477 intrname[pa->pa_intrpin], pa->pa_intrline); 478 } 479 #endif 480 481 /* setup softc */ 482 sc->sc_pc = pc; 483 sc->sc_iot = pa->pa_iot; 484 sc->sc_memt = pa->pa_memt; 485 sc->sc_dmat = pa->pa_dmat; 486 sc->sc_tag = pa->pa_tag; 487 sc->sc_function = pa->pa_function; 488 489 sc->sc_intrline = pa->pa_intrline; 490 sc->sc_intrtag = pa->pa_intrtag; 491 sc->sc_intrpin = pa->pa_intrpin; 492 493 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 494 495 shutdownhook_establish(pccbb_shutdown, sc); 496 497 /* Disable legacy register mapping. */ 498 switch (sc->sc_chipset) { 499 case CB_RX5C46X: /* fallthrough */ 500 #if 0 501 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 502 case CB_RX5C47X: 503 #endif 504 /* 505 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 506 * cannot be disabled by substituting 0 into PCI_LEGACY 507 * register. Ricoh CardBus bridges have special bits on Bridge 508 * control reg (addr 0x3e on PCI config space). 509 */ 510 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 511 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 512 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 513 break; 514 515 default: 516 /* XXX I don't know proper way to kill legacy I/O. */ 517 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 518 break; 519 } 520 521 config_defer(self, pccbb_pci_callback); 522 } 523 524 525 526 527 /* 528 * static void pccbb_pci_callback(struct device *self) 529 * 530 * The actual attach routine: get memory space for YENTA register 531 * space, setup YENTA register and route interrupt. 532 * 533 * This function should be deferred because this device may obtain 534 * memory space dynamically. This function must avoid obtaining 535 * memory area which has already kept for another device. 536 */ 537 static void 538 pccbb_pci_callback(self) 539 struct device *self; 540 { 541 struct pccbb_softc *sc = (void *)self; 542 pci_chipset_tag_t pc = sc->sc_pc; 543 bus_space_tag_t base_memt; 544 bus_space_handle_t base_memh; 545 u_int32_t maskreg; 546 pci_intr_handle_t ih; 547 const char *intrstr = NULL; 548 bus_addr_t sockbase; 549 struct cbslot_attach_args cba; 550 struct pcmciabus_attach_args paa; 551 struct cardslot_attach_args caa; 552 struct cardslot_softc *csc; 553 554 if (0 == sc->sc_base_memh) { 555 /* The socket registers aren't mapped correctly. */ 556 #if rbus 557 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 558 (sc->sc_chipset == CB_RX5C47X 559 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 560 0, &sockbase, &sc->sc_base_memh)) { 561 return; 562 } 563 sc->sc_base_memt = sc->sc_memt; 564 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 565 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 566 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 567 PCI_SOCKBASE))); 568 #else 569 sc->sc_base_memt = sc->sc_memt; 570 #if !defined CBB_PCI_BASE 571 #define CBB_PCI_BASE 0x20000000 572 #endif 573 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 574 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 575 /* cannot allocate memory space */ 576 return; 577 } 578 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 579 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 580 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 581 sc->sc_tag, PCI_SOCKBASE))); 582 #endif 583 } 584 585 /* bus bridge initialization */ 586 pccbb_chipinit(sc); 587 588 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 589 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 590 591 /* CSC Interrupt: Card detect interrupt on */ 592 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 593 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 594 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 595 /* reset interrupt */ 596 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 597 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 598 599 /* clear data structure for child device interrupt handlers */ 600 sc->sc_pil = NULL; 601 sc->sc_pil_intr_enable = 1; 602 603 /* Map and establish the interrupt. */ 604 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 605 sc->sc_intrline, &ih)) { 606 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 607 return; 608 } 609 intrstr = pci_intr_string(pc, ih); 610 611 /* 612 * XXX pccbbintr should be called under the priority lower 613 * than any other hard interrputs. 614 */ 615 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 616 617 if (sc->sc_ih == NULL) { 618 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 619 if (intrstr != NULL) { 620 printf(" at %s", intrstr); 621 } 622 printf("\n"); 623 return; 624 } 625 626 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 627 powerhook_establish(pccbb_powerhook, sc); 628 629 { 630 u_int32_t sockstat = 631 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 632 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 633 sc->sc_flags |= CBB_CARDEXIST; 634 } 635 } 636 637 /* 638 * attach cardbus 639 */ 640 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 641 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 642 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 643 644 /* initialize cbslot_attach */ 645 cba.cba_busname = "cardbus"; 646 cba.cba_iot = sc->sc_iot; 647 cba.cba_memt = sc->sc_memt; 648 cba.cba_dmat = sc->sc_dmat; 649 cba.cba_bus = (busreg >> 8) & 0x0ff; 650 cba.cba_cc = (void *)sc; 651 cba.cba_cf = &pccbb_funcs; 652 cba.cba_intrline = sc->sc_intrline; 653 654 #if rbus 655 cba.cba_rbus_iot = sc->sc_rbus_iot; 656 cba.cba_rbus_memt = sc->sc_rbus_memt; 657 #endif 658 659 cba.cba_cacheline = PCI_CACHELINE(bhlc); 660 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 661 662 printf("%s: cacheline 0x%x lattimer 0x%x\n", 663 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 664 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 665 busreg); 666 #if defined SHOW_REGS 667 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 668 sc->sc_base_memh); 669 #endif 670 } 671 672 pccbb_pcmcia_attach_setup(sc, &paa); 673 caa.caa_cb_attach = NULL; 674 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 675 caa.caa_cb_attach = &cba; 676 } 677 caa.caa_16_attach = &paa; 678 caa.caa_ph = &sc->sc_pcmcia_h; 679 680 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 681 DPRINTF(("pccbbattach: found cardslot\n")); 682 sc->sc_csc = csc; 683 } 684 685 return; 686 } 687 688 689 690 691 692 /* 693 * static void pccbb_chipinit(struct pccbb_softc *sc) 694 * 695 * This function initialize YENTA chip registers listed below: 696 * 1) PCI command reg, 697 * 2) PCI and CardBus latency timer, 698 * 3) route PCI interrupt, 699 * 4) close all memory and io windows. 700 */ 701 static void 702 pccbb_chipinit(sc) 703 struct pccbb_softc *sc; 704 { 705 pci_chipset_tag_t pc = sc->sc_pc; 706 pcitag_t tag = sc->sc_tag; 707 pcireg_t reg; 708 709 /* 710 * Set PCI command reg. 711 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 712 */ 713 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 714 /* I believe it is harmless. */ 715 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 716 PCI_COMMAND_MASTER_ENABLE); 717 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 718 719 /* 720 * Set CardBus latency timer. 721 */ 722 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 723 if (PCI_CB_LATENCY(reg) < 0x20) { 724 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 725 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 726 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 727 } 728 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 729 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 730 731 /* 732 * Set PCI latency timer. 733 */ 734 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 735 if (PCI_LATTIMER(reg) < 0x10) { 736 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 737 reg |= (0x10 << PCI_LATTIMER_SHIFT); 738 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 739 } 740 DPRINTF(("PCI latency timer 0x%x (%x)\n", 741 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 742 743 744 /* Route functional interrupts to PCI. */ 745 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 746 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 747 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 748 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 749 750 switch (sc->sc_chipset) { 751 case CB_TI113X: 752 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 753 /* This bit is shared, but may read as 0 on some chips, so set 754 it explicitly on both functions. */ 755 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 756 /* CSC intr enable */ 757 reg |= PCI113X_CBCTRL_PCI_CSC; 758 /* functional intr prohibit */ 759 reg &= ~PCI113X_CBCTRL_PCI_INTR; 760 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 761 break; 762 763 case CB_TOPIC95B: 764 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 765 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 766 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 767 768 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 769 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 770 sc->sc_dev.dv_xname, reg)); 771 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 772 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 773 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 774 DPRINTF(("0x%x\n", reg)); 775 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 776 break; 777 } 778 779 /* Close all memory and I/O windows. */ 780 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 781 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 782 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 783 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 784 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 785 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 786 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 787 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 788 } 789 790 791 792 793 /* 794 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 795 * struct pcmciabus_attach_args *paa) 796 * 797 * This function attaches 16-bit PCcard bus. 798 */ 799 STATIC void 800 pccbb_pcmcia_attach_setup(sc, paa) 801 struct pccbb_softc *sc; 802 struct pcmciabus_attach_args *paa; 803 { 804 struct pcic_handle *ph = &sc->sc_pcmcia_h; 805 #if rbus 806 rbus_tag_t rb; 807 #endif 808 809 /* initialize pcmcia part in pccbb_softc */ 810 ph->ph_parent = (struct device *)sc; 811 ph->sock = sc->sc_function; 812 ph->flags = 0; 813 ph->shutdown = 0; 814 ph->ih_irq = sc->sc_intrline; 815 ph->ph_bus_t = sc->sc_base_memt; 816 ph->ph_bus_h = sc->sc_base_memh; 817 ph->ph_read = pccbb_pcmcia_read; 818 ph->ph_write = pccbb_pcmcia_write; 819 sc->sc_pct = &pccbb_pcmcia_funcs; 820 821 /* 822 * We need to do a few things here: 823 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 824 * setting the IRQ numbers to 0. 825 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 826 * routing of CSC interrupts (e.g. card removal) to PCI while in 827 * PCMCIA mode. We just leave this set all the time. 828 * 3) Enable card insertion/removal interrupts in case the chip also 829 * needs that while in PCMCIA mode. 830 * 4) Clear any pending CSC interrupt. 831 */ 832 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 833 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 834 Pcic_read(ph, PCIC_CSC); 835 836 /* initialize pcmcia bus attachment */ 837 paa->paa_busname = "pcmcia"; 838 paa->pct = sc->sc_pct; 839 paa->pch = ph; 840 paa->iobase = 0; /* I don't use them */ 841 paa->iosize = 0; 842 #if rbus 843 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 844 paa->iobase = rb->rb_start + rb->rb_offset; 845 paa->iosize = rb->rb_end - rb->rb_start; 846 #endif 847 848 return; 849 } 850 851 #if 0 852 STATIC void 853 pccbb_pcmcia_attach_card(ph) 854 struct pcic_handle *ph; 855 { 856 if (ph->flags & PCIC_FLAG_CARDP) { 857 panic("pccbb_pcmcia_attach_card: already attached"); 858 } 859 860 /* call the MI attach function */ 861 pcmcia_card_attach(ph->pcmcia); 862 863 ph->flags |= PCIC_FLAG_CARDP; 864 } 865 866 STATIC void 867 pccbb_pcmcia_detach_card(ph, flags) 868 struct pcic_handle *ph; 869 int flags; 870 { 871 if (!(ph->flags & PCIC_FLAG_CARDP)) { 872 panic("pccbb_pcmcia_detach_card: already detached"); 873 } 874 875 ph->flags &= ~PCIC_FLAG_CARDP; 876 877 /* call the MI detach function */ 878 pcmcia_card_detach(ph->pcmcia, flags); 879 } 880 #endif 881 882 /* 883 * int pccbbintr(arg) 884 * void *arg; 885 * This routine handles the interrupt from Yenta PCI-CardBus bridge 886 * itself. 887 */ 888 int 889 pccbbintr(arg) 890 void *arg; 891 { 892 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 893 u_int32_t sockevent, sockstate; 894 bus_space_tag_t memt = sc->sc_base_memt; 895 bus_space_handle_t memh = sc->sc_base_memh; 896 struct pcic_handle *ph = &sc->sc_pcmcia_h; 897 898 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 899 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 900 Pcic_read(ph, PCIC_CSC); 901 902 if (sockevent == 0) { 903 /* This intr is not for me: it may be for my child devices. */ 904 if (sc->sc_pil_intr_enable) { 905 return pccbbintr_function(sc); 906 } else { 907 return 0; 908 } 909 } 910 911 if (sockevent & CB_SOCKET_EVENT_CD) { 912 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 913 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 914 /* A card should be removed. */ 915 if (sc->sc_flags & CBB_CARDEXIST) { 916 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 917 sockevent)); 918 DPRINTF((" card removed, 0x%08x\n", sockstate)); 919 sc->sc_flags &= ~CBB_CARDEXIST; 920 if (sc->sc_csc->sc_status & 921 CARDSLOT_STATUS_CARD_16) { 922 #if 0 923 struct pcic_handle *ph = 924 &sc->sc_pcmcia_h; 925 926 pcmcia_card_deactivate(ph->pcmcia); 927 pccbb_pcmcia_socket_disable(ph); 928 pccbb_pcmcia_detach_card(ph, 929 DETACH_FORCE); 930 #endif 931 cardslot_event_throw(sc->sc_csc, 932 CARDSLOT_EVENT_REMOVAL_16); 933 } else if (sc->sc_csc->sc_status & 934 CARDSLOT_STATUS_CARD_CB) { 935 /* Cardbus intr removed */ 936 cardslot_event_throw(sc->sc_csc, 937 CARDSLOT_EVENT_REMOVAL_CB); 938 } 939 } 940 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 941 /* 942 * The pccbbintr may called from powerdown hook when 943 * the system resumed, to detect the card 944 * insertion/removal during suspension. 945 */ 946 (sc->sc_flags & CBB_CARDEXIST) == 0) { 947 if (sc->sc_flags & CBB_INSERTING) { 948 callout_stop(&sc->sc_insert_ch); 949 } 950 callout_reset(&sc->sc_insert_ch, hz / 10, 951 pci113x_insert, sc); 952 sc->sc_flags |= CBB_INSERTING; 953 } 954 } 955 956 return (1); 957 } 958 959 /* 960 * static int pccbbintr_function(struct pccbb_softc *sc) 961 * 962 * This function calls each interrupt handler registered at the 963 * bridge. The interrupt handlers are called in registered order. 964 */ 965 static int 966 pccbbintr_function(sc) 967 struct pccbb_softc *sc; 968 { 969 int retval = 0, val; 970 struct pccbb_intrhand_list *pil; 971 int s, splchanged; 972 973 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 974 /* 975 * XXX priority change. gross. I use if-else 976 * sentense instead of switch-case sentense because of 977 * avoiding duplicate case value error. More than one 978 * IPL_XXX use same value. It depends on 979 * implimentation. 980 */ 981 splchanged = 1; 982 if (pil->pil_level == IPL_SERIAL) { 983 s = splserial(); 984 } else if (pil->pil_level == IPL_HIGH) { 985 s = splhigh(); 986 } else if (pil->pil_level == IPL_CLOCK) { 987 s = splclock(); 988 } else if (pil->pil_level == IPL_AUDIO) { 989 s = splaudio(); 990 } else if (pil->pil_level == IPL_IMP) { 991 s = splimp(); 992 } else if (pil->pil_level == IPL_TTY) { 993 s = spltty(); 994 } else if (pil->pil_level == IPL_SOFTSERIAL) { 995 s = splsoftserial(); 996 } else if (pil->pil_level == IPL_NET) { 997 s = splnet(); 998 } else { 999 splchanged = 0; 1000 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1001 } 1002 1003 val = (*pil->pil_func)(pil->pil_arg); 1004 1005 if (splchanged != 0) { 1006 splx(s); 1007 } 1008 1009 retval = retval == 1 ? 1 : 1010 retval == 0 ? val : val != 0 ? val : retval; 1011 } 1012 1013 return retval; 1014 } 1015 1016 static void 1017 pci113x_insert(arg) 1018 void *arg; 1019 { 1020 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1021 u_int32_t sockevent, sockstate; 1022 1023 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1024 CB_SOCKET_EVENT); 1025 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1026 CB_SOCKET_STAT); 1027 1028 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1029 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1030 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1031 sc->sc_flags |= CBB_CARDEXIST; 1032 /* call pccard interrupt handler here */ 1033 if (sockstate & CB_SOCKET_STAT_16BIT) { 1034 /* 16-bit card found */ 1035 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1036 cardslot_event_throw(sc->sc_csc, 1037 CARDSLOT_EVENT_INSERTION_16); 1038 } else if (sockstate & CB_SOCKET_STAT_CB) { 1039 /* cardbus card found */ 1040 /* cardbus_attach_card(sc->sc_csc); */ 1041 cardslot_event_throw(sc->sc_csc, 1042 CARDSLOT_EVENT_INSERTION_CB); 1043 } else { 1044 /* who are you? */ 1045 } 1046 } else { 1047 callout_reset(&sc->sc_insert_ch, hz / 10, 1048 pci113x_insert, sc); 1049 } 1050 } 1051 1052 #define PCCBB_PCMCIA_OFFSET 0x800 1053 static u_int8_t 1054 pccbb_pcmcia_read(ph, reg) 1055 struct pcic_handle *ph; 1056 int reg; 1057 { 1058 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1059 PCCBB_PCMCIA_OFFSET + reg); 1060 } 1061 1062 static void 1063 pccbb_pcmcia_write(ph, reg, val) 1064 struct pcic_handle *ph; 1065 int reg; 1066 u_int8_t val; 1067 { 1068 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1069 val); 1070 } 1071 1072 /* 1073 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1074 */ 1075 STATIC int 1076 pccbb_ctrl(ct, command) 1077 cardbus_chipset_tag_t ct; 1078 int command; 1079 { 1080 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1081 1082 switch (command) { 1083 case CARDBUS_CD: 1084 if (2 == pccbb_detect_card(sc)) { 1085 int retval = 0; 1086 int status = cb_detect_voltage(sc); 1087 if (PCCARD_VCC_5V & status) { 1088 retval |= CARDBUS_5V_CARD; 1089 } 1090 if (PCCARD_VCC_3V & status) { 1091 retval |= CARDBUS_3V_CARD; 1092 } 1093 if (PCCARD_VCC_XV & status) { 1094 retval |= CARDBUS_XV_CARD; 1095 } 1096 if (PCCARD_VCC_YV & status) { 1097 retval |= CARDBUS_YV_CARD; 1098 } 1099 return retval; 1100 } else { 1101 return 0; 1102 } 1103 break; 1104 case CARDBUS_RESET: 1105 return cb_reset(sc); 1106 break; 1107 case CARDBUS_IO_ENABLE: /* fallthrough */ 1108 case CARDBUS_IO_DISABLE: /* fallthrough */ 1109 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1110 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1111 case CARDBUS_BM_ENABLE: /* fallthrough */ 1112 case CARDBUS_BM_DISABLE: /* fallthrough */ 1113 return pccbb_cardenable(sc, command); 1114 break; 1115 } 1116 1117 return 0; 1118 } 1119 1120 /* 1121 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1122 * This function returns true when it succeeds and returns false when 1123 * it fails. 1124 */ 1125 STATIC int 1126 pccbb_power(ct, command) 1127 cardbus_chipset_tag_t ct; 1128 int command; 1129 { 1130 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1131 1132 u_int32_t status, sock_ctrl; 1133 bus_space_tag_t memt = sc->sc_base_memt; 1134 bus_space_handle_t memh = sc->sc_base_memh; 1135 1136 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1137 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1138 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1139 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1140 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1141 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1142 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1143 "UNKNOWN", 1144 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1145 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1146 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1147 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1148 "UNKNOWN", command)); 1149 1150 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1151 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1152 1153 switch (command & CARDBUS_VCCMASK) { 1154 case CARDBUS_VCC_UC: 1155 break; 1156 case CARDBUS_VCC_5V: 1157 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1158 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1159 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1160 } else { 1161 printf("%s: BAD voltage request: no 5 V card\n", 1162 sc->sc_dev.dv_xname); 1163 } 1164 break; 1165 case CARDBUS_VCC_3V: 1166 if (CB_SOCKET_STAT_3VCARD & status) { 1167 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1168 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1169 } else { 1170 printf("%s: BAD voltage request: no 3.3 V card\n", 1171 sc->sc_dev.dv_xname); 1172 } 1173 break; 1174 case CARDBUS_VCC_0V: 1175 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1176 break; 1177 default: 1178 return 0; /* power NEVER changed */ 1179 break; 1180 } 1181 1182 switch (command & CARDBUS_VPPMASK) { 1183 case CARDBUS_VPP_UC: 1184 break; 1185 case CARDBUS_VPP_0V: 1186 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1187 break; 1188 case CARDBUS_VPP_VCC: 1189 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1190 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1191 break; 1192 case CARDBUS_VPP_12V: 1193 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1194 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1195 break; 1196 } 1197 1198 #if 0 1199 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1200 #endif 1201 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1202 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1203 1204 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1205 /* 1206 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1207 * time is 20 ms, some PC-Card bridge requires longer duration. 1208 */ 1209 delay(200 * 1000); 1210 1211 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1212 printf 1213 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1214 sc->sc_dev.dv_xname, sock_ctrl, status); 1215 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1216 (command & CARDBUS_VCCMASK) == 1217 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1218 CARDBUS_VCCMASK) == 1219 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1220 CARDBUS_VCCMASK) == 1221 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1222 CARDBUS_VCCMASK) == 1223 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1224 CARDBUS_VCCMASK) == 1225 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1226 CARDBUS_VCCMASK) == 1227 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1228 (command & CARDBUS_VPPMASK) == 1229 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1230 CARDBUS_VPPMASK) == 1231 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1232 CARDBUS_VPPMASK) == 1233 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1234 CARDBUS_VPPMASK) == 1235 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1236 #if 0 1237 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1238 u_int32_t force = 1239 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1240 /* Reset Bad Vcc request */ 1241 force &= ~CB_SOCKET_FORCE_BADVCC; 1242 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1243 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1244 CB_SOCKET_STAT)); 1245 return 1; 1246 } 1247 #endif 1248 return 0; 1249 } 1250 return 1; /* power changed correctly */ 1251 } 1252 1253 #if defined CB_PCMCIA_POLL 1254 struct cb_poll_str { 1255 void *arg; 1256 int (*func) __P((void *)); 1257 int level; 1258 pccard_chipset_tag_t ct; 1259 int count; 1260 struct callout poll_ch; 1261 }; 1262 1263 static struct cb_poll_str cb_poll[10]; 1264 static int cb_poll_n = 0; 1265 1266 static void cb_pcmcia_poll __P((void *arg)); 1267 1268 static void 1269 cb_pcmcia_poll(arg) 1270 void *arg; 1271 { 1272 struct cb_poll_str *poll = arg; 1273 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1274 struct pccbb_softc *sc = psc->cpc_parent; 1275 int s; 1276 u_int32_t spsr; /* socket present-state reg */ 1277 1278 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1279 switch (poll->level) { 1280 case IPL_NET: 1281 s = splnet(); 1282 break; 1283 case IPL_BIO: 1284 s = splbio(); 1285 break; 1286 case IPL_TTY: /* fallthrough */ 1287 default: 1288 s = spltty(); 1289 break; 1290 } 1291 1292 spsr = 1293 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1294 CB_SOCKET_STAT); 1295 1296 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1297 if (!(spsr & 0x40)) { /* CINT low */ 1298 #else 1299 if (1) { 1300 #endif 1301 if ((*poll->func) (poll->arg) == 1) { 1302 ++poll->count; 1303 printf("intr: reported from poller, 0x%x\n", spsr); 1304 #if defined LEVEL2 1305 } else { 1306 printf("intr: miss! 0x%x\n", spsr); 1307 #endif 1308 } 1309 } 1310 splx(s); 1311 } 1312 #endif /* defined CB_PCMCIA_POLL */ 1313 1314 /* 1315 * static int pccbb_detect_card(struct pccbb_softc *sc) 1316 * return value: 0 if no card exists. 1317 * 1 if 16-bit card exists. 1318 * 2 if cardbus card exists. 1319 */ 1320 static int 1321 pccbb_detect_card(sc) 1322 struct pccbb_softc *sc; 1323 { 1324 bus_space_handle_t base_memh = sc->sc_base_memh; 1325 bus_space_tag_t base_memt = sc->sc_base_memt; 1326 u_int32_t sockstat = 1327 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1328 int retval = 0; 1329 1330 /* CD1 and CD2 asserted */ 1331 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1332 /* card must be present */ 1333 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1334 /* NOTACARD DEASSERTED */ 1335 if (CB_SOCKET_STAT_CB & sockstat) { 1336 /* CardBus mode */ 1337 retval = 2; 1338 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1339 /* 16-bit mode */ 1340 retval = 1; 1341 } 1342 } 1343 } 1344 return retval; 1345 } 1346 1347 /* 1348 * STATIC int cb_reset(struct pccbb_softc *sc) 1349 * This function resets CardBus card. 1350 */ 1351 STATIC int 1352 cb_reset(sc) 1353 struct pccbb_softc *sc; 1354 { 1355 /* 1356 * Reset Assert at least 20 ms 1357 * Some machines request longer duration. 1358 */ 1359 int reset_duration = 1360 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1361 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1362 1363 /* Reset bit Assert (bit 6 at 0x3E) */ 1364 bcr |= CB_BCR_RESET_ENABLE; 1365 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1366 delay(reset_duration); 1367 1368 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1369 /* Reset bit Deassert (bit 6 at 0x3E) */ 1370 bcr &= ~CB_BCR_RESET_ENABLE; 1371 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1372 delay(reset_duration); 1373 } 1374 /* No card found on the slot. Keep Reset. */ 1375 return 1; 1376 } 1377 1378 /* 1379 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1380 * This function detect card Voltage. 1381 */ 1382 STATIC int 1383 cb_detect_voltage(sc) 1384 struct pccbb_softc *sc; 1385 { 1386 u_int32_t psr; /* socket present-state reg */ 1387 bus_space_tag_t iot = sc->sc_base_memt; 1388 bus_space_handle_t ioh = sc->sc_base_memh; 1389 int vol = PCCARD_VCC_UKN; /* set 0 */ 1390 1391 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1392 1393 if (0x400u & psr) { 1394 vol |= PCCARD_VCC_5V; 1395 } 1396 if (0x800u & psr) { 1397 vol |= PCCARD_VCC_3V; 1398 } 1399 1400 return vol; 1401 } 1402 1403 STATIC int 1404 cbbprint(aux, pcic) 1405 void *aux; 1406 const char *pcic; 1407 { 1408 /* 1409 struct cbslot_attach_args *cba = aux; 1410 1411 if (cba->cba_slot >= 0) { 1412 printf(" slot %d", cba->cba_slot); 1413 } 1414 */ 1415 return UNCONF; 1416 } 1417 1418 /* 1419 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1420 * This function enables and disables the card 1421 */ 1422 STATIC int 1423 pccbb_cardenable(sc, function) 1424 struct pccbb_softc *sc; 1425 int function; 1426 { 1427 u_int32_t command = 1428 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1429 1430 DPRINTF(("pccbb_cardenable:")); 1431 switch (function) { 1432 case CARDBUS_IO_ENABLE: 1433 command |= PCI_COMMAND_IO_ENABLE; 1434 break; 1435 case CARDBUS_IO_DISABLE: 1436 command &= ~PCI_COMMAND_IO_ENABLE; 1437 break; 1438 case CARDBUS_MEM_ENABLE: 1439 command |= PCI_COMMAND_MEM_ENABLE; 1440 break; 1441 case CARDBUS_MEM_DISABLE: 1442 command &= ~PCI_COMMAND_MEM_ENABLE; 1443 break; 1444 case CARDBUS_BM_ENABLE: 1445 command |= PCI_COMMAND_MASTER_ENABLE; 1446 break; 1447 case CARDBUS_BM_DISABLE: 1448 command &= ~PCI_COMMAND_MASTER_ENABLE; 1449 break; 1450 default: 1451 return 0; 1452 } 1453 1454 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1455 DPRINTF((" command reg 0x%x\n", command)); 1456 return 1; 1457 } 1458 1459 #if !rbus 1460 /* 1461 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1462 */ 1463 static int 1464 pccbb_io_open(ct, win, start, end) 1465 cardbus_chipset_tag_t ct; 1466 int win; 1467 u_int32_t start, end; 1468 { 1469 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1470 int basereg; 1471 int limitreg; 1472 1473 if ((win < 0) || (win > 2)) { 1474 #if defined DIAGNOSTIC 1475 printf("cardbus_io_open: window out of range %d\n", win); 1476 #endif 1477 return 0; 1478 } 1479 1480 basereg = win * 8 + 0x2c; 1481 limitreg = win * 8 + 0x30; 1482 1483 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1484 start, basereg, end, limitreg)); 1485 1486 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1487 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1488 return 1; 1489 } 1490 1491 /* 1492 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1493 */ 1494 static int 1495 pccbb_io_close(ct, win) 1496 cardbus_chipset_tag_t ct; 1497 int win; 1498 { 1499 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1500 int basereg; 1501 int limitreg; 1502 1503 if ((win < 0) || (win > 2)) { 1504 #if defined DIAGNOSTIC 1505 printf("cardbus_io_close: window out of range %d\n", win); 1506 #endif 1507 return 0; 1508 } 1509 1510 basereg = win * 8 + 0x2c; 1511 limitreg = win * 8 + 0x30; 1512 1513 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1514 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1515 return 1; 1516 } 1517 1518 /* 1519 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1520 */ 1521 static int 1522 pccbb_mem_open(ct, win, start, end) 1523 cardbus_chipset_tag_t ct; 1524 int win; 1525 u_int32_t start, end; 1526 { 1527 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1528 int basereg; 1529 int limitreg; 1530 1531 if ((win < 0) || (win > 2)) { 1532 #if defined DIAGNOSTIC 1533 printf("cardbus_mem_open: window out of range %d\n", win); 1534 #endif 1535 return 0; 1536 } 1537 1538 basereg = win * 8 + 0x1c; 1539 limitreg = win * 8 + 0x20; 1540 1541 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1542 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1543 return 1; 1544 } 1545 1546 /* 1547 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1548 */ 1549 static int 1550 pccbb_mem_close(ct, win) 1551 cardbus_chipset_tag_t ct; 1552 int win; 1553 { 1554 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1555 int basereg; 1556 int limitreg; 1557 1558 if ((win < 0) || (win > 2)) { 1559 #if defined DIAGNOSTIC 1560 printf("cardbus_mem_close: window out of range %d\n", win); 1561 #endif 1562 return 0; 1563 } 1564 1565 basereg = win * 8 + 0x1c; 1566 limitreg = win * 8 + 0x20; 1567 1568 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1569 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1570 return 1; 1571 } 1572 #endif 1573 1574 /* 1575 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1576 * int irq, 1577 * int level, 1578 * int (* func) __P((void *)), 1579 * void *arg) 1580 * 1581 * This function registers an interrupt handler at the bridge, in 1582 * order not to call the interrupt handlers of child devices when 1583 * a card-deletion interrupt occurs. 1584 * 1585 * The arguments irq and level are not used. 1586 */ 1587 static void * 1588 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1589 cardbus_chipset_tag_t ct; 1590 int irq, level; 1591 int (*func) __P((void *)); 1592 void *arg; 1593 { 1594 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1595 1596 return pccbb_intr_establish(sc, irq, level, func, arg); 1597 } 1598 1599 1600 /* 1601 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1602 * void *ih) 1603 * 1604 * This function removes an interrupt handler pointed by ih. 1605 */ 1606 static void 1607 pccbb_cb_intr_disestablish(ct, ih) 1608 cardbus_chipset_tag_t ct; 1609 void *ih; 1610 { 1611 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1612 1613 pccbb_intr_disestablish(sc, ih); 1614 } 1615 1616 1617 /* 1618 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1619 * int irq, 1620 * int level, 1621 * int (* func) __P((void *)), 1622 * void *arg) 1623 * 1624 * This function registers an interrupt handler at the bridge, in 1625 * order not to call the interrupt handlers of child devices when 1626 * a card-deletion interrupt occurs. 1627 * 1628 * The arguments irq is not used because pccbb selects intr vector. 1629 */ 1630 static void * 1631 pccbb_intr_establish(sc, irq, level, func, arg) 1632 struct pccbb_softc *sc; 1633 int irq, level; 1634 int (*func) __P((void *)); 1635 void *arg; 1636 { 1637 struct pccbb_intrhand_list *pil, *newpil; 1638 1639 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1640 1641 if (sc->sc_pil == NULL) { 1642 /* initialize bridge intr routing */ 1643 1644 switch (sc->sc_chipset) { 1645 case CB_TI113X: 1646 { 1647 pcireg_t cbctrl = 1648 pci_conf_read(sc->sc_pc, sc->sc_tag, 1649 PCI_CBCTRL); 1650 /* functional intr enabled */ 1651 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1652 pci_conf_write(sc->sc_pc, sc->sc_tag, 1653 PCI_CBCTRL, cbctrl); 1654 break; 1655 } 1656 default: 1657 break; 1658 } 1659 } 1660 1661 /* 1662 * Allocate a room for interrupt handler structure. 1663 */ 1664 if (NULL == (newpil = 1665 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1666 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1667 return NULL; 1668 } 1669 1670 newpil->pil_func = func; 1671 newpil->pil_arg = arg; 1672 newpil->pil_level = level; 1673 newpil->pil_next = NULL; 1674 1675 if (sc->sc_pil == NULL) { 1676 sc->sc_pil = newpil; 1677 } else { 1678 for (pil = sc->sc_pil; pil->pil_next != NULL; 1679 pil = pil->pil_next); 1680 pil->pil_next = newpil; 1681 } 1682 1683 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1684 1685 return newpil; 1686 } 1687 1688 /* 1689 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1690 * void *ih) 1691 * 1692 * This function removes an interrupt handler pointed by ih. 1693 */ 1694 static void 1695 pccbb_intr_disestablish(sc, ih) 1696 struct pccbb_softc *sc; 1697 void *ih; 1698 { 1699 struct pccbb_intrhand_list *pil, **pil_prev; 1700 1701 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1702 1703 pil_prev = &sc->sc_pil; 1704 1705 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1706 if (pil == ih) { 1707 *pil_prev = pil->pil_next; 1708 free(pil, M_DEVBUF); 1709 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1710 break; 1711 } 1712 pil_prev = &pil->pil_next; 1713 } 1714 1715 if (sc->sc_pil == NULL) { 1716 /* No interrupt handlers */ 1717 1718 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1719 1720 switch (sc->sc_chipset) { 1721 case CB_TI113X: 1722 { 1723 pcireg_t cbctrl = 1724 pci_conf_read(sc->sc_pc, sc->sc_tag, 1725 PCI_CBCTRL); 1726 /* functional intr disabled */ 1727 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1728 pci_conf_write(sc->sc_pc, sc->sc_tag, 1729 PCI_CBCTRL, cbctrl); 1730 break; 1731 } 1732 default: 1733 break; 1734 } 1735 } 1736 } 1737 1738 #if defined SHOW_REGS 1739 static void 1740 cb_show_regs(pc, tag, memt, memh) 1741 pci_chipset_tag_t pc; 1742 pcitag_t tag; 1743 bus_space_tag_t memt; 1744 bus_space_handle_t memh; 1745 { 1746 int i; 1747 printf("PCI config regs:"); 1748 for (i = 0; i < 0x50; i += 4) { 1749 if (i % 16 == 0) { 1750 printf("\n 0x%02x:", i); 1751 } 1752 printf(" %08x", pci_conf_read(pc, tag, i)); 1753 } 1754 for (i = 0x80; i < 0xb0; i += 4) { 1755 if (i % 16 == 0) { 1756 printf("\n 0x%02x:", i); 1757 } 1758 printf(" %08x", pci_conf_read(pc, tag, i)); 1759 } 1760 1761 if (memh == 0) { 1762 printf("\n"); 1763 return; 1764 } 1765 1766 printf("\nsocket regs:"); 1767 for (i = 0; i <= 0x10; i += 0x04) { 1768 printf(" %08x", bus_space_read_4(memt, memh, i)); 1769 } 1770 printf("\nExCA regs:"); 1771 for (i = 0; i < 0x08; ++i) { 1772 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1773 } 1774 printf("\n"); 1775 return; 1776 } 1777 #endif 1778 1779 /* 1780 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1781 * int busno, int devno, int function) 1782 * This is the function to make a tag to access config space of 1783 * a CardBus Card. It works same as pci_conf_read. 1784 */ 1785 static cardbustag_t 1786 pccbb_make_tag(cc, busno, devno, function) 1787 cardbus_chipset_tag_t cc; 1788 int busno, devno, function; 1789 { 1790 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1791 1792 return pci_make_tag(sc->sc_pc, busno, devno, function); 1793 } 1794 1795 static void 1796 pccbb_free_tag(cc, tag) 1797 cardbus_chipset_tag_t cc; 1798 cardbustag_t tag; 1799 { 1800 } 1801 1802 /* 1803 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1804 * cardbustag_t tag, int offset) 1805 * This is the function to read the config space of a CardBus Card. 1806 * It works same as pci_conf_read. 1807 */ 1808 static cardbusreg_t 1809 pccbb_conf_read(cc, tag, offset) 1810 cardbus_chipset_tag_t cc; 1811 cardbustag_t tag; 1812 int offset; /* register offset */ 1813 { 1814 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1815 1816 return pci_conf_read(sc->sc_pc, tag, offset); 1817 } 1818 1819 /* 1820 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1821 * int offs, cardbusreg_t val) 1822 * This is the function to write the config space of a CardBus Card. 1823 * It works same as pci_conf_write. 1824 */ 1825 static void 1826 pccbb_conf_write(cc, tag, reg, val) 1827 cardbus_chipset_tag_t cc; 1828 cardbustag_t tag; 1829 int reg; /* register offset */ 1830 cardbusreg_t val; 1831 { 1832 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1833 1834 pci_conf_write(sc->sc_pc, tag, reg, val); 1835 } 1836 1837 #if 0 1838 STATIC int 1839 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1840 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1841 int speed, int flags, 1842 bus_space_handle_t * iohp) 1843 #endif 1844 /* 1845 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1846 * bus_addr_t start, bus_size_t size, 1847 * bus_size_t align, 1848 * struct pcmcia_io_handle *pcihp 1849 * 1850 * This function only allocates I/O region for pccard. This function 1851 * never maps the allocated region to pccard I/O area. 1852 * 1853 * XXX: The interface of this function is not very good, I believe. 1854 */ 1855 STATIC int 1856 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1857 pcmcia_chipset_handle_t pch; 1858 bus_addr_t start; /* start address */ 1859 bus_size_t size; 1860 bus_size_t align; 1861 struct pcmcia_io_handle *pcihp; 1862 { 1863 struct pcic_handle *ph = (struct pcic_handle *)pch; 1864 bus_addr_t ioaddr; 1865 int flags = 0; 1866 bus_space_tag_t iot; 1867 bus_space_handle_t ioh; 1868 #if rbus 1869 rbus_tag_t rb; 1870 #endif 1871 if (align == 0) { 1872 align = size; /* XXX: funny??? */ 1873 } 1874 1875 /* 1876 * Allocate some arbitrary I/O space. 1877 */ 1878 1879 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1880 1881 #if rbus 1882 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1883 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1884 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1885 return 1; 1886 } 1887 #else 1888 if (start) { 1889 ioaddr = start; 1890 if (bus_space_map(iot, start, size, 0, &ioh)) { 1891 return 1; 1892 } 1893 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1894 (u_long) ioaddr, (u_long) size)); 1895 } else { 1896 flags |= PCMCIA_IO_ALLOCATED; 1897 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1898 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1899 size, align, 0, 0, &ioaddr, &ioh)) { 1900 /* No room be able to be get. */ 1901 return 1; 1902 } 1903 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1904 (u_long) ioaddr, (u_long) size)); 1905 } 1906 #endif 1907 1908 pcihp->iot = iot; 1909 pcihp->ioh = ioh; 1910 pcihp->addr = ioaddr; 1911 pcihp->size = size; 1912 pcihp->flags = flags; 1913 1914 return 0; 1915 } 1916 1917 /* 1918 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1919 * struct pcmcia_io_handle *pcihp) 1920 * 1921 * This function only frees I/O region for pccard. 1922 * 1923 * XXX: The interface of this function is not very good, I believe. 1924 */ 1925 void 1926 pccbb_pcmcia_io_free(pch, pcihp) 1927 pcmcia_chipset_handle_t pch; 1928 struct pcmcia_io_handle *pcihp; 1929 { 1930 #if !rbus 1931 bus_space_tag_t iot = pcihp->iot; 1932 #endif 1933 bus_space_handle_t ioh = pcihp->ioh; 1934 bus_size_t size = pcihp->size; 1935 1936 #if rbus 1937 struct pccbb_softc *sc = 1938 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1939 rbus_tag_t rb = sc->sc_rbus_iot; 1940 1941 rbus_space_free(rb, ioh, size, NULL); 1942 #else 1943 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1944 bus_space_free(iot, ioh, size); 1945 else 1946 bus_space_unmap(iot, ioh, size); 1947 #endif 1948 } 1949 1950 /* 1951 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1952 * bus_addr_t offset, bus_size_t size, 1953 * struct pcmcia_io_handle *pcihp, 1954 * int *windowp) 1955 * 1956 * This function maps the allocated I/O region to pccard. This function 1957 * never allocates any I/O region for pccard I/O area. I don't 1958 * understand why the original authors of pcmciabus separated alloc and 1959 * map. I believe the two must be unite. 1960 * 1961 * XXX: no wait timing control? 1962 */ 1963 int 1964 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1965 pcmcia_chipset_handle_t pch; 1966 int width; 1967 bus_addr_t offset; 1968 bus_size_t size; 1969 struct pcmcia_io_handle *pcihp; 1970 int *windowp; 1971 { 1972 struct pcic_handle *ph = (struct pcic_handle *)pch; 1973 bus_addr_t ioaddr = pcihp->addr + offset; 1974 int i, win; 1975 #if defined CBB_DEBUG 1976 static char *width_names[] = { "dynamic", "io8", "io16" }; 1977 #endif 1978 1979 /* Sanity check I/O handle. */ 1980 1981 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1982 panic("pccbb_pcmcia_io_map iot is bogus"); 1983 } 1984 1985 /* XXX Sanity check offset/size. */ 1986 1987 win = -1; 1988 for (i = 0; i < PCIC_IO_WINS; i++) { 1989 if ((ph->ioalloc & (1 << i)) == 0) { 1990 win = i; 1991 ph->ioalloc |= (1 << i); 1992 break; 1993 } 1994 } 1995 1996 if (win == -1) { 1997 return 1; 1998 } 1999 2000 *windowp = win; 2001 2002 /* XXX this is pretty gross */ 2003 2004 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2005 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2006 2007 /* XXX wtf is this doing here? */ 2008 2009 #if 0 2010 printf(" port 0x%lx", (u_long) ioaddr); 2011 if (size > 1) { 2012 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2013 } 2014 #endif 2015 2016 ph->io[win].addr = ioaddr; 2017 ph->io[win].size = size; 2018 ph->io[win].width = width; 2019 2020 /* actual dirty register-value changing in the function below. */ 2021 pccbb_pcmcia_do_io_map(ph, win); 2022 2023 return 0; 2024 } 2025 2026 /* 2027 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2028 * 2029 * This function changes register-value to map I/O region for pccard. 2030 */ 2031 static void 2032 pccbb_pcmcia_do_io_map(ph, win) 2033 struct pcic_handle *ph; 2034 int win; 2035 { 2036 static u_int8_t pcic_iowidth[3] = { 2037 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2038 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2039 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2040 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2041 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2042 }; 2043 2044 #define PCIC_SIA_START_LOW 0 2045 #define PCIC_SIA_START_HIGH 1 2046 #define PCIC_SIA_STOP_LOW 2 2047 #define PCIC_SIA_STOP_HIGH 3 2048 2049 int regbase_win = 0x8 + win * 0x04; 2050 u_int8_t ioctl, enable; 2051 2052 DPRINTF( 2053 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2054 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2055 ph->io[win].width * 8)); 2056 2057 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2058 ph->io[win].addr & 0xff); 2059 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2060 (ph->io[win].addr >> 8) & 0xff); 2061 2062 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2063 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2064 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2065 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2066 2067 ioctl = Pcic_read(ph, PCIC_IOCTL); 2068 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2069 switch (win) { 2070 case 0: 2071 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2072 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2073 PCIC_IOCTL_IO0_DATASIZE_MASK); 2074 ioctl |= pcic_iowidth[ph->io[win].width]; 2075 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2076 break; 2077 case 1: 2078 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2079 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2080 PCIC_IOCTL_IO1_DATASIZE_MASK); 2081 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2082 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2083 break; 2084 } 2085 Pcic_write(ph, PCIC_IOCTL, ioctl); 2086 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2087 #if defined CBB_DEBUG 2088 { 2089 u_int8_t start_low = 2090 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2091 u_int8_t start_high = 2092 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2093 u_int8_t stop_low = 2094 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2095 u_int8_t stop_high = 2096 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2097 printf 2098 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2099 start_low, start_high, stop_low, stop_high, ioctl, enable); 2100 } 2101 #endif 2102 } 2103 2104 /* 2105 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2106 * 2107 * This function unmaps I/O region. No return value. 2108 */ 2109 STATIC void 2110 pccbb_pcmcia_io_unmap(pch, win) 2111 pcmcia_chipset_handle_t pch; 2112 int win; 2113 { 2114 struct pcic_handle *ph = (struct pcic_handle *)pch; 2115 int reg; 2116 2117 if (win >= PCIC_IO_WINS || win < 0) { 2118 panic("pccbb_pcmcia_io_unmap: window out of range"); 2119 } 2120 2121 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2122 switch (win) { 2123 case 0: 2124 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2125 break; 2126 case 1: 2127 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2128 break; 2129 } 2130 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2131 2132 ph->ioalloc &= ~(1 << win); 2133 } 2134 2135 /* 2136 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2137 * 2138 * This function enables the card. All information is stored in 2139 * the first argument, pcmcia_chipset_handle_t. 2140 */ 2141 static void 2142 pccbb_pcmcia_wait_ready(ph) 2143 struct pcic_handle *ph; 2144 { 2145 int i; 2146 2147 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2148 Pcic_read(ph, PCIC_IF_STATUS))); 2149 2150 for (i = 0; i < 10000; i++) { 2151 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2152 return; 2153 } 2154 delay(500); 2155 #ifdef CBB_DEBUG 2156 if ((i > 5000) && (i % 100 == 99)) 2157 printf("."); 2158 #endif 2159 } 2160 2161 #ifdef DIAGNOSTIC 2162 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2163 Pcic_read(ph, PCIC_IF_STATUS)); 2164 #endif 2165 } 2166 2167 /* 2168 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2169 * 2170 * This function enables the card. All information is stored in 2171 * the first argument, pcmcia_chipset_handle_t. 2172 */ 2173 STATIC void 2174 pccbb_pcmcia_socket_enable(pch) 2175 pcmcia_chipset_handle_t pch; 2176 { 2177 struct pcic_handle *ph = (struct pcic_handle *)pch; 2178 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2179 int cardtype, win; 2180 u_int8_t power, intr; 2181 pcireg_t spsr; 2182 int voltage; 2183 2184 /* this bit is mostly stolen from pcic_attach_card */ 2185 2186 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2187 2188 /* get card Vcc info */ 2189 2190 spsr = 2191 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2192 CB_SOCKET_STAT); 2193 if (spsr & CB_SOCKET_STAT_5VCARD) { 2194 DPRINTF(("5V card\n")); 2195 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2196 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2197 DPRINTF(("3V card\n")); 2198 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2199 } else { 2200 printf("?V card, 0x%x\n", spsr); /* XXX */ 2201 return; 2202 } 2203 2204 /* assert reset bit */ 2205 intr = Pcic_read(ph, PCIC_INTR); 2206 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2207 Pcic_write(ph, PCIC_INTR, intr); 2208 2209 /* disable socket i/o: negate output enable bit */ 2210 2211 power = Pcic_read(ph, PCIC_PWRCTL); 2212 power &= ~PCIC_PWRCTL_OE; 2213 Pcic_write(ph, PCIC_PWRCTL, power); 2214 2215 /* power down the socket to reset it, clear the card reset pin */ 2216 2217 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2218 2219 /* 2220 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2221 * we are changing Vcc (Toff). 2222 */ 2223 /* delay(300*1000); too much */ 2224 2225 /* power up the socket */ 2226 pccbb_power(sc, voltage); 2227 2228 /* 2229 * wait 100ms until power raise (Tpr) and 20ms to become 2230 * stable (Tsu(Vcc)). 2231 * 2232 * some machines require some more time to be settled 2233 * (another 200ms is added here). 2234 */ 2235 /* delay((100 + 20 + 200)*1000); too much */ 2236 2237 power = Pcic_read(ph, PCIC_PWRCTL); 2238 power |= PCIC_PWRCTL_OE; 2239 Pcic_write(ph, PCIC_PWRCTL, power); 2240 2241 /* 2242 * hold RESET at least 10us. 2243 */ 2244 delay(10); 2245 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2246 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2247 2248 /* clear the reset flag */ 2249 2250 intr |= PCIC_INTR_RESET; 2251 Pcic_write(ph, PCIC_INTR, intr); 2252 2253 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2254 2255 delay(20000); 2256 2257 /* wait for the chip to finish initializing */ 2258 2259 pccbb_pcmcia_wait_ready(ph); 2260 2261 /* zero out the address windows */ 2262 2263 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2264 2265 /* set the card type */ 2266 2267 cardtype = pcmcia_card_gettype(ph->pcmcia); 2268 2269 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2270 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2271 Pcic_write(ph, PCIC_INTR, intr); 2272 2273 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2274 ph->ph_parent->dv_xname, ph->sock, 2275 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2276 2277 /* reinstall all the memory and io mappings */ 2278 2279 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2280 if (ph->memalloc & (1 << win)) { 2281 pccbb_pcmcia_do_mem_map(ph, win); 2282 } 2283 } 2284 2285 for (win = 0; win < PCIC_IO_WINS; ++win) { 2286 if (ph->ioalloc & (1 << win)) { 2287 pccbb_pcmcia_do_io_map(ph, win); 2288 } 2289 } 2290 } 2291 2292 /* 2293 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2294 * 2295 * This function disables the card. All information is stored in 2296 * the first argument, pcmcia_chipset_handle_t. 2297 */ 2298 STATIC void 2299 pccbb_pcmcia_socket_disable(pch) 2300 pcmcia_chipset_handle_t pch; 2301 { 2302 struct pcic_handle *ph = (struct pcic_handle *)pch; 2303 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2304 u_int8_t power, intr; 2305 2306 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2307 2308 /* reset signal asserting... */ 2309 2310 intr = Pcic_read(ph, PCIC_INTR); 2311 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2312 Pcic_write(ph, PCIC_INTR, intr); 2313 delay(2 * 1000); 2314 2315 /* power down the socket */ 2316 power = Pcic_read(ph, PCIC_PWRCTL); 2317 power &= ~PCIC_PWRCTL_OE; 2318 Pcic_write(ph, PCIC_PWRCTL, power); 2319 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2320 /* 2321 * wait 300ms until power fails (Tpf). 2322 */ 2323 delay(300 * 1000); 2324 } 2325 2326 /* 2327 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2328 * 2329 * This function detects whether a card is in the slot or not. 2330 * If a card is inserted, return 1. Otherwise, return 0. 2331 */ 2332 STATIC int 2333 pccbb_pcmcia_card_detect(pch) 2334 pcmcia_chipset_handle_t pch; 2335 { 2336 struct pcic_handle *ph = (struct pcic_handle *)pch; 2337 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2338 2339 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2340 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2341 } 2342 2343 #if 0 2344 STATIC int 2345 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2346 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2347 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2348 #endif 2349 /* 2350 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2351 * bus_size_t size, 2352 * struct pcmcia_mem_handle *pcmhp) 2353 * 2354 * This function only allocates memory region for pccard. This 2355 * function never maps the allocated region to pccard memory area. 2356 * 2357 * XXX: Why the argument of start address is not in? 2358 */ 2359 STATIC int 2360 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2361 pcmcia_chipset_handle_t pch; 2362 bus_size_t size; 2363 struct pcmcia_mem_handle *pcmhp; 2364 { 2365 struct pcic_handle *ph = (struct pcic_handle *)pch; 2366 bus_space_handle_t memh; 2367 bus_addr_t addr; 2368 bus_size_t sizepg; 2369 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2370 #if rbus 2371 rbus_tag_t rb; 2372 #endif 2373 2374 /* out of sc->memh, allocate as many pages as necessary */ 2375 2376 /* convert size to PCIC pages */ 2377 /* 2378 * This is not enough; when the requested region is on the page 2379 * boundaries, this may calculate wrong result. 2380 */ 2381 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2382 #if 0 2383 if (sizepg > PCIC_MAX_MEM_PAGES) { 2384 return 1; 2385 } 2386 #endif 2387 2388 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2389 return 1; 2390 } 2391 2392 addr = 0; /* XXX gcc -Wuninitialized */ 2393 2394 #if rbus 2395 rb = sc->sc_rbus_memt; 2396 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2397 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2398 &addr, &memh)) { 2399 return 1; 2400 } 2401 #else 2402 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2403 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2404 0, /* boundary */ 2405 0, /* flags */ 2406 &addr, &memh)) { 2407 return 1; 2408 } 2409 #endif 2410 2411 DPRINTF( 2412 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2413 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2414 2415 pcmhp->memt = sc->sc_memt; 2416 pcmhp->memh = memh; 2417 pcmhp->addr = addr; 2418 pcmhp->size = size; 2419 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2420 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2421 pcmhp->mhandle = 0; 2422 /* No offset??? Funny. */ 2423 2424 return 0; 2425 } 2426 2427 /* 2428 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2429 * struct pcmcia_mem_handle *pcmhp) 2430 * 2431 * This function release the memory space allocated by the function 2432 * pccbb_pcmcia_mem_alloc(). 2433 */ 2434 STATIC void 2435 pccbb_pcmcia_mem_free(pch, pcmhp) 2436 pcmcia_chipset_handle_t pch; 2437 struct pcmcia_mem_handle *pcmhp; 2438 { 2439 #if rbus 2440 struct pcic_handle *ph = (struct pcic_handle *)pch; 2441 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2442 2443 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2444 #else 2445 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2446 #endif 2447 } 2448 2449 /* 2450 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2451 * 2452 * This function release the memory space allocated by the function 2453 * pccbb_pcmcia_mem_alloc(). 2454 */ 2455 STATIC void 2456 pccbb_pcmcia_do_mem_map(ph, win) 2457 struct pcic_handle *ph; 2458 int win; 2459 { 2460 int regbase_win; 2461 bus_addr_t phys_addr; 2462 bus_addr_t phys_end; 2463 2464 #define PCIC_SMM_START_LOW 0 2465 #define PCIC_SMM_START_HIGH 1 2466 #define PCIC_SMM_STOP_LOW 2 2467 #define PCIC_SMM_STOP_HIGH 3 2468 #define PCIC_CMA_LOW 4 2469 #define PCIC_CMA_HIGH 5 2470 2471 u_int8_t start_low, start_high = 0; 2472 u_int8_t stop_low, stop_high; 2473 u_int8_t off_low, off_high; 2474 u_int8_t mem_window; 2475 int reg; 2476 2477 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2478 int mem8 = 2479 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2480 || (kind == PCMCIA_MEM_ATTR); 2481 2482 regbase_win = 0x10 + win * 0x08; 2483 2484 phys_addr = ph->mem[win].addr; 2485 phys_end = phys_addr + ph->mem[win].size; 2486 2487 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2488 phys_addr, phys_end, ph->mem[win].offset)); 2489 2490 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2491 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2492 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2493 2494 /* bit 19:12 */ 2495 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2496 /* bit 23:20 and bit 7 on */ 2497 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2498 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2499 /* bit 31:24, for 32-bit address */ 2500 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2501 2502 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2503 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2504 2505 if (((struct pccbb_softc *)ph-> 2506 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2507 Pcic_write(ph, 0x40 + win, mem_window); 2508 } 2509 2510 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2511 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2512 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2513 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2514 2515 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2516 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2517 2518 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2519 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2520 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2521 | ((kind == PCMCIA_MEM_ATTR) ? 2522 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2523 2524 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2525 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2526 2527 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2528 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2529 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2530 2531 #if defined CBB_DEBUG 2532 { 2533 int r1, r2, r3, r4, r5, r6, r7 = 0; 2534 2535 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2536 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2537 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2538 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2539 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2540 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2541 if (((struct pccbb_softc *)(ph-> 2542 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2543 r7 = Pcic_read(ph, 0x40 + win); 2544 } 2545 2546 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2547 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2548 if (((struct pccbb_softc *)(ph-> 2549 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2550 DPRINTF((" %02x", r7)); 2551 } 2552 DPRINTF(("\n")); 2553 } 2554 #endif 2555 } 2556 2557 /* 2558 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2559 * bus_addr_t card_addr, bus_size_t size, 2560 * struct pcmcia_mem_handle *pcmhp, 2561 * bus_addr_t *offsetp, int *windowp) 2562 * 2563 * This function maps memory space allocated by the function 2564 * pccbb_pcmcia_mem_alloc(). 2565 */ 2566 STATIC int 2567 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2568 pcmcia_chipset_handle_t pch; 2569 int kind; 2570 bus_addr_t card_addr; 2571 bus_size_t size; 2572 struct pcmcia_mem_handle *pcmhp; 2573 bus_addr_t *offsetp; 2574 int *windowp; 2575 { 2576 struct pcic_handle *ph = (struct pcic_handle *)pch; 2577 bus_addr_t busaddr; 2578 long card_offset; 2579 int win; 2580 2581 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2582 if ((ph->memalloc & (1 << win)) == 0) { 2583 ph->memalloc |= (1 << win); 2584 break; 2585 } 2586 } 2587 2588 if (win == PCIC_MEM_WINS) { 2589 return 1; 2590 } 2591 2592 *windowp = win; 2593 2594 /* XXX this is pretty gross */ 2595 2596 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2597 panic("pccbb_pcmcia_mem_map memt is bogus"); 2598 } 2599 2600 busaddr = pcmhp->addr; 2601 2602 /* 2603 * compute the address offset to the pcmcia address space for the 2604 * pcic. this is intentionally signed. The masks and shifts below 2605 * will cause TRT to happen in the pcic registers. Deal with making 2606 * sure the address is aligned, and return the alignment offset. 2607 */ 2608 2609 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2610 card_addr -= *offsetp; 2611 2612 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2613 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2614 (u_long) card_addr)); 2615 2616 /* 2617 * include the offset in the size, and decrement size by one, since 2618 * the hw wants start/stop 2619 */ 2620 size += *offsetp - 1; 2621 2622 card_offset = (((long)card_addr) - ((long)busaddr)); 2623 2624 ph->mem[win].addr = busaddr; 2625 ph->mem[win].size = size; 2626 ph->mem[win].offset = card_offset; 2627 ph->mem[win].kind = kind; 2628 2629 pccbb_pcmcia_do_mem_map(ph, win); 2630 2631 return 0; 2632 } 2633 2634 /* 2635 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2636 * int window) 2637 * 2638 * This function unmaps memory space which mapped by the function 2639 * pccbb_pcmcia_mem_map(). 2640 */ 2641 STATIC void 2642 pccbb_pcmcia_mem_unmap(pch, window) 2643 pcmcia_chipset_handle_t pch; 2644 int window; 2645 { 2646 struct pcic_handle *ph = (struct pcic_handle *)pch; 2647 int reg; 2648 2649 if (window >= PCIC_MEM_WINS) { 2650 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2651 } 2652 2653 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2654 reg &= ~(1 << window); 2655 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2656 2657 ph->memalloc &= ~(1 << window); 2658 } 2659 2660 #if defined PCCBB_PCMCIA_POLL 2661 struct pccbb_poll_str { 2662 void *arg; 2663 int (*func) __P((void *)); 2664 int level; 2665 struct pcic_handle *ph; 2666 int count; 2667 int num; 2668 struct callout poll_ch; 2669 }; 2670 2671 static struct pccbb_poll_str pccbb_poll[10]; 2672 static int pccbb_poll_n = 0; 2673 2674 static void pccbb_pcmcia_poll __P((void *arg)); 2675 2676 static void 2677 pccbb_pcmcia_poll(arg) 2678 void *arg; 2679 { 2680 struct pccbb_poll_str *poll = arg; 2681 struct pcic_handle *ph = poll->ph; 2682 struct pccbb_softc *sc = ph->sc; 2683 int s; 2684 u_int32_t spsr; /* socket present-state reg */ 2685 2686 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2687 switch (poll->level) { 2688 case IPL_NET: 2689 s = splnet(); 2690 break; 2691 case IPL_BIO: 2692 s = splbio(); 2693 break; 2694 case IPL_TTY: /* fallthrough */ 2695 default: 2696 s = spltty(); 2697 break; 2698 } 2699 2700 spsr = 2701 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2702 CB_SOCKET_STAT); 2703 2704 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2705 if (!(spsr & 0x40)) /* CINT low */ 2706 #else 2707 if (1) 2708 #endif 2709 { 2710 if ((*poll->func) (poll->arg) > 0) { 2711 ++poll->count; 2712 // printf("intr: reported from poller, 0x%x\n", spsr); 2713 #if defined LEVEL2 2714 } else { 2715 printf("intr: miss! 0x%x\n", spsr); 2716 #endif 2717 } 2718 } 2719 splx(s); 2720 } 2721 #endif /* defined CB_PCMCIA_POLL */ 2722 2723 /* 2724 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2725 * struct pcmcia_function *pf, 2726 * int ipl, 2727 * int (*func)(void *), 2728 * void *arg); 2729 * 2730 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2731 */ 2732 STATIC void * 2733 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2734 pcmcia_chipset_handle_t pch; 2735 struct pcmcia_function *pf; 2736 int ipl; 2737 int (*func) __P((void *)); 2738 void *arg; 2739 { 2740 struct pcic_handle *ph = (struct pcic_handle *)pch; 2741 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2742 2743 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2744 /* what should I do? */ 2745 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2746 DPRINTF( 2747 ("%s does not provide edge nor pulse interrupt\n", 2748 sc->sc_dev.dv_xname)); 2749 return NULL; 2750 } 2751 /* 2752 * XXX Noooooo! The interrupt flag must set properly!! 2753 * dumb pcmcia driver!! 2754 */ 2755 } 2756 2757 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2758 } 2759 2760 /* 2761 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2762 * void *ih) 2763 * 2764 * This function disables PC-Card interrupt. 2765 */ 2766 STATIC void 2767 pccbb_pcmcia_intr_disestablish(pch, ih) 2768 pcmcia_chipset_handle_t pch; 2769 void *ih; 2770 { 2771 struct pcic_handle *ph = (struct pcic_handle *)pch; 2772 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2773 2774 pccbb_intr_disestablish(sc, ih); 2775 } 2776 2777 #if rbus 2778 /* 2779 * static int 2780 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2781 * bus_addr_t addr, bus_size_t size, 2782 * bus_addr_t mask, bus_size_t align, 2783 * int flags, bus_addr_t *addrp; 2784 * bus_space_handle_t *bshp) 2785 * 2786 * This function allocates a portion of memory or io space for 2787 * clients. This function is called from CardBus card drivers. 2788 */ 2789 static int 2790 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2791 cardbus_chipset_tag_t ct; 2792 rbus_tag_t rb; 2793 bus_addr_t addr; 2794 bus_size_t size; 2795 bus_addr_t mask; 2796 bus_size_t align; 2797 int flags; 2798 bus_addr_t *addrp; 2799 bus_space_handle_t *bshp; 2800 { 2801 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2802 2803 DPRINTF( 2804 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2805 addr, size, mask, align)); 2806 2807 if (align == 0) { 2808 align = size; 2809 } 2810 2811 if (rb->rb_bt == sc->sc_memt) { 2812 if (align < 16) { 2813 return 1; 2814 } 2815 } else if (rb->rb_bt == sc->sc_iot) { 2816 if (align < 4) { 2817 return 1; 2818 } 2819 /* XXX: hack for avoiding ISA image */ 2820 if (mask < 0x0100) { 2821 mask = 0x3ff; 2822 addr = 0x300; 2823 } 2824 2825 } else { 2826 DPRINTF( 2827 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2828 rb->rb_bt)); 2829 return 1; 2830 /* XXX: panic here? */ 2831 } 2832 2833 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2834 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2835 return 1; 2836 } 2837 2838 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2839 2840 return 0; 2841 } 2842 2843 /* 2844 * static int 2845 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2846 * bus_space_handle_t *bshp, bus_size_t size); 2847 * 2848 * This function is called from CardBus card drivers. 2849 */ 2850 static int 2851 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2852 cardbus_chipset_tag_t ct; 2853 rbus_tag_t rb; 2854 bus_space_handle_t bsh; 2855 bus_size_t size; 2856 { 2857 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2858 bus_space_tag_t bt = rb->rb_bt; 2859 2860 pccbb_close_win(sc, bt, bsh, size); 2861 2862 if (bt == sc->sc_memt) { 2863 } else if (bt == sc->sc_iot) { 2864 } else { 2865 return 1; 2866 /* XXX: panic here? */ 2867 } 2868 2869 return rbus_space_free(rb, bsh, size, NULL); 2870 } 2871 #endif /* rbus */ 2872 2873 #if rbus 2874 2875 static int 2876 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2877 struct pccbb_softc *sc; 2878 bus_space_tag_t bst; 2879 bus_addr_t addr; 2880 bus_size_t size; 2881 bus_space_handle_t bsh; 2882 int flags; 2883 { 2884 struct pccbb_win_chain_head *head; 2885 bus_addr_t align; 2886 2887 head = &sc->sc_iowindow; 2888 align = 0x04; 2889 if (sc->sc_memt == bst) { 2890 head = &sc->sc_memwindow; 2891 align = 0x1000; 2892 DPRINTF(("using memory window, %x %x %x\n\n", 2893 sc->sc_iot, sc->sc_memt, bst)); 2894 } 2895 2896 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2897 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2898 sc->sc_dev.dv_xname, 2899 (head == &sc->sc_memwindow) ? "mem" : "io"); 2900 } 2901 pccbb_winset(align, sc, bst); 2902 2903 return 0; 2904 } 2905 2906 static int 2907 pccbb_close_win(sc, bst, bsh, size) 2908 struct pccbb_softc *sc; 2909 bus_space_tag_t bst; 2910 bus_space_handle_t bsh; 2911 bus_size_t size; 2912 { 2913 struct pccbb_win_chain_head *head; 2914 bus_addr_t align; 2915 2916 head = &sc->sc_iowindow; 2917 align = 0x04; 2918 if (sc->sc_memt == bst) { 2919 head = &sc->sc_memwindow; 2920 align = 0x1000; 2921 } 2922 2923 if (pccbb_winlist_delete(head, bsh, size)) { 2924 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2925 sc->sc_dev.dv_xname, 2926 (head == &sc->sc_memwindow) ? "mem" : "io"); 2927 } 2928 pccbb_winset(align, sc, bst); 2929 2930 return 0; 2931 } 2932 2933 static int 2934 pccbb_winlist_insert(head, start, size, bsh, flags) 2935 struct pccbb_win_chain_head *head; 2936 bus_addr_t start; 2937 bus_size_t size; 2938 bus_space_handle_t bsh; 2939 int flags; 2940 { 2941 struct pccbb_win_chain *chainp, *elem; 2942 2943 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2944 M_NOWAIT)) == NULL) 2945 return (1); /* fail */ 2946 2947 elem->wc_start = start; 2948 elem->wc_end = start + (size - 1); 2949 elem->wc_handle = bsh; 2950 elem->wc_flags = flags; 2951 2952 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2953 chainp = TAILQ_NEXT(chainp, wc_list)) { 2954 if (chainp->wc_end < start) 2955 continue; 2956 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2957 return (0); 2958 } 2959 2960 TAILQ_INSERT_TAIL(head, elem, wc_list); 2961 return (0); 2962 } 2963 2964 static int 2965 pccbb_winlist_delete(head, bsh, size) 2966 struct pccbb_win_chain_head *head; 2967 bus_space_handle_t bsh; 2968 bus_size_t size; 2969 { 2970 struct pccbb_win_chain *chainp; 2971 2972 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2973 chainp = TAILQ_NEXT(chainp, wc_list)) { 2974 if (chainp->wc_handle != bsh) 2975 continue; 2976 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2977 printf("pccbb_winlist_delete: window 0x%lx size " 2978 "inconsistent: 0x%lx, 0x%lx\n", 2979 chainp->wc_start, 2980 chainp->wc_end - chainp->wc_start, 2981 size - 1); 2982 return 1; 2983 } 2984 2985 TAILQ_REMOVE(head, chainp, wc_list); 2986 free(chainp, M_DEVBUF); 2987 2988 return 0; 2989 } 2990 2991 return 1; /* fail: no candidate to remove */ 2992 } 2993 2994 static void 2995 pccbb_winset(align, sc, bst) 2996 bus_addr_t align; 2997 struct pccbb_softc *sc; 2998 bus_space_tag_t bst; 2999 { 3000 pci_chipset_tag_t pc; 3001 pcitag_t tag; 3002 bus_addr_t mask = ~(align - 1); 3003 struct { 3004 cardbusreg_t win_start; 3005 cardbusreg_t win_limit; 3006 int win_flags; 3007 } win[2]; 3008 struct pccbb_win_chain *chainp; 3009 int offs; 3010 3011 win[0].win_start = 0xffffffff; 3012 win[0].win_limit = 0; 3013 win[1].win_start = 0xffffffff; 3014 win[1].win_limit = 0; 3015 3016 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3017 offs = 0x2c; 3018 if (sc->sc_memt == bst) { 3019 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3020 offs = 0x1c; 3021 } 3022 3023 if (chainp != NULL) { 3024 win[0].win_start = chainp->wc_start & mask; 3025 win[0].win_limit = chainp->wc_end & mask; 3026 win[0].win_flags = chainp->wc_flags; 3027 chainp = TAILQ_NEXT(chainp, wc_list); 3028 } 3029 3030 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3031 if (win[1].win_start == 0xffffffff) { 3032 /* window 1 is not used */ 3033 if ((win[0].win_flags == chainp->wc_flags) && 3034 (win[0].win_limit + align >= 3035 (chainp->wc_start & mask))) { 3036 /* concatenate */ 3037 win[0].win_limit = chainp->wc_end & mask; 3038 } else { 3039 /* make new window */ 3040 win[1].win_start = chainp->wc_start & mask; 3041 win[1].win_limit = chainp->wc_end & mask; 3042 win[1].win_flags = chainp->wc_flags; 3043 } 3044 continue; 3045 } 3046 3047 /* Both windows are engaged. */ 3048 if (win[0].win_flags == win[1].win_flags) { 3049 /* same flags */ 3050 if (win[0].win_flags == chainp->wc_flags) { 3051 if (win[1].win_start - (win[0].win_limit + 3052 align) < 3053 (chainp->wc_start & mask) - 3054 ((chainp->wc_end & mask) + align)) { 3055 /* 3056 * merge window 0 and 1, and set win1 3057 * to chainp 3058 */ 3059 win[0].win_limit = win[1].win_limit; 3060 win[1].win_start = 3061 chainp->wc_start & mask; 3062 win[1].win_limit = 3063 chainp->wc_end & mask; 3064 } else { 3065 win[1].win_limit = 3066 chainp->wc_end & mask; 3067 } 3068 } else { 3069 /* different flags */ 3070 3071 /* concatenate win0 and win1 */ 3072 win[0].win_limit = win[1].win_limit; 3073 /* allocate win[1] to new space */ 3074 win[1].win_start = chainp->wc_start & mask; 3075 win[1].win_limit = chainp->wc_end & mask; 3076 win[1].win_flags = chainp->wc_flags; 3077 } 3078 } else { 3079 /* the flags of win[0] and win[1] is different */ 3080 if (win[0].win_flags == chainp->wc_flags) { 3081 win[0].win_limit = chainp->wc_end & mask; 3082 /* 3083 * XXX this creates overlapping windows, so 3084 * what should the poor bridge do if one is 3085 * cachable, and the other is not? 3086 */ 3087 printf("%s: overlapping windows\n", 3088 sc->sc_dev.dv_xname); 3089 } else { 3090 win[1].win_limit = chainp->wc_end & mask; 3091 } 3092 } 3093 } 3094 3095 pc = sc->sc_pc; 3096 tag = sc->sc_tag; 3097 pci_conf_write(pc, tag, offs, win[0].win_start); 3098 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3099 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3100 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3101 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3102 pci_conf_read(pc, tag, offs), 3103 pci_conf_read(pc, tag, offs + 4) + align, 3104 pci_conf_read(pc, tag, offs + 8), 3105 pci_conf_read(pc, tag, offs + 12) + align)); 3106 3107 if (bst == sc->sc_memt) { 3108 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3109 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3110 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3111 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3112 } 3113 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3114 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3115 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3116 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3117 } 3118 } 3119 } 3120 3121 #endif /* rbus */ 3122 3123 static void 3124 pccbb_powerhook(why, arg) 3125 int why; 3126 void *arg; 3127 { 3128 struct pccbb_softc *sc = arg; 3129 u_int32_t reg; 3130 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3131 bus_space_handle_t base_memh = sc->sc_base_memh; 3132 3133 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3134 3135 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3136 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3137 if (sc->sc_pil_intr_enable) { 3138 (void)pccbbintr_function(sc); 3139 } 3140 sc->sc_pil_intr_enable = 0; 3141 3142 /* ToDo: deactivate or suspend child devices */ 3143 3144 } 3145 3146 if (why == PWR_RESUME) { 3147 /* CSC Interrupt: Card detect interrupt on */ 3148 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3149 /* Card detect intr is turned on. */ 3150 reg |= CB_SOCKET_MASK_CD; 3151 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3152 /* reset interrupt */ 3153 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3154 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3155 3156 /* 3157 * check for card insertion or removal during suspend period. 3158 * XXX: the code can't cope with card swap (remove then 3159 * insert). how can we detect such situation? 3160 */ 3161 (void)pccbbintr(sc); 3162 3163 sc->sc_pil_intr_enable = 1; 3164 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3165 3166 /* ToDo: activate or wakeup child devices */ 3167 } 3168 } 3169
Indexes created Sat Sep 27 14:09:57 GMT 2025