pccbb.c revision 1.45
1 /* $NetBSD: pccbb.c,v 1.45 2000/08/28 09:26:38 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 93 void pccbbattach __P((struct device *, struct device *, void *)); 94 int pccbbintr __P((void *)); 95 static void pci113x_insert __P((void *)); 96 static int pccbbintr_function __P((struct pccbb_softc *)); 97 98 static int pccbb_detect_card __P((struct pccbb_softc *)); 99 100 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 101 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 102 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 103 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 104 105 STATIC int cb_reset __P((struct pccbb_softc *)); 106 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 107 STATIC int cbbprint __P((void *, const char *)); 108 109 static int cb_chipset __P((u_int32_t, int *)); 110 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 111 struct pcmciabus_attach_args *)); 112 #if 0 113 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 114 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 115 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 116 #endif 117 118 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 119 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 120 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 121 #if !rbus 122 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 123 u_int32_t)); 124 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 125 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 126 u_int32_t)); 127 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 128 #endif /* !rbus */ 129 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 130 int level, int (*ih) (void *), void *sc)); 131 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 132 133 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 static void pccbb_powerhook __P((int, void *)); 171 172 /* bus-space allocation and deallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 178 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t)); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 187 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t)); 189 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int)); 191 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 192 bus_space_handle_t, bus_size_t)); 193 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t)); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback __P((struct device *)); 201 202 #if defined SHOW_REGS 203 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 204 bus_space_tag_t memt, bus_space_handle_t memh)); 205 #endif 206 207 struct cfattach cbb_pci_ca = { 208 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 209 }; 210 211 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 212 pccbb_pcmcia_mem_alloc, 213 pccbb_pcmcia_mem_free, 214 pccbb_pcmcia_mem_map, 215 pccbb_pcmcia_mem_unmap, 216 pccbb_pcmcia_io_alloc, 217 pccbb_pcmcia_io_free, 218 pccbb_pcmcia_io_map, 219 pccbb_pcmcia_io_unmap, 220 pccbb_pcmcia_intr_establish, 221 pccbb_pcmcia_intr_disestablish, 222 pccbb_pcmcia_socket_enable, 223 pccbb_pcmcia_socket_disable, 224 pccbb_pcmcia_card_detect 225 }; 226 227 #if rbus 228 static struct cardbus_functions pccbb_funcs = { 229 pccbb_rbus_cb_space_alloc, 230 pccbb_rbus_cb_space_free, 231 pccbb_cb_intr_establish, 232 pccbb_cb_intr_disestablish, 233 pccbb_ctrl, 234 pccbb_power, 235 pccbb_make_tag, 236 pccbb_free_tag, 237 pccbb_conf_read, 238 pccbb_conf_write, 239 }; 240 #else 241 static struct cardbus_functions pccbb_funcs = { 242 pccbb_ctrl, 243 pccbb_power, 244 pccbb_mem_open, 245 pccbb_mem_close, 246 pccbb_io_open, 247 pccbb_io_close, 248 pccbb_cb_intr_establish, 249 pccbb_cb_intr_disestablish, 250 pccbb_make_tag, 251 pccbb_conf_read, 252 pccbb_conf_write, 253 }; 254 #endif 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 struct cfdata *match; 260 void *aux; 261 { 262 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 263 264 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 265 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 266 PCI_INTERFACE(pa->pa_class) == 0) { 267 return 1; 268 } 269 270 return 0; 271 } 272 273 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 274 | ((prod) << PCI_PRODUCT_SHIFT)) 275 276 struct yenta_chipinfo { 277 pcireg_t yc_id; /* vendor tag | product tag */ 278 int yc_chiptype; 279 int yc_flags; 280 } yc_chipsets[] = { 281 /* Texas Instruments chips */ 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 307 /* Ricoh chips */ 308 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 309 PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 311 PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 313 PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 315 PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 319 PCCBB_PCMCIA_MEM_32}, 320 321 /* Toshiba products */ 322 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 323 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 325 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 327 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 329 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 330 331 /* Cirrus Logic products */ 332 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 333 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 335 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 336 337 /* sentinel, or Generic chip */ 338 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 339 }; 340 341 static int 342 cb_chipset(pci_id, flagp) 343 u_int32_t pci_id; 344 int *flagp; 345 { 346 struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return (yc->yc_chiptype); 358 } 359 360 static void 361 pccbb_shutdown(void *arg) 362 { 363 struct pccbb_softc *sc = arg; 364 pcireg_t command; 365 366 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 367 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 368 0); 369 370 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 371 372 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 373 PCI_COMMAND_MASTER_ENABLE); 374 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 375 376 } 377 378 void 379 pccbbattach(parent, self, aux) 380 struct device *parent; 381 struct device *self; 382 void *aux; 383 { 384 struct pccbb_softc *sc = (void *)self; 385 struct pci_attach_args *pa = aux; 386 pci_chipset_tag_t pc = pa->pa_pc; 387 pcireg_t busreg, reg, sock_base; 388 bus_addr_t sockbase; 389 char devinfo[256]; 390 int flags; 391 392 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 393 394 pci_devinfo(pa->pa_id, 0, 0, devinfo); 395 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 396 #ifdef CBB_DEBUG 397 printf(" (chipflags %x)", flags); 398 #endif 399 printf("\n"); 400 401 TAILQ_INIT(&sc->sc_memwindow); 402 TAILQ_INIT(&sc->sc_iowindow); 403 404 #if rbus 405 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 406 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 407 #endif /* rbus */ 408 409 sc->sc_base_memh = 0; 410 411 /* 412 * MAP socket registers and ExCA registers on memory-space 413 * When no valid address is set on socket base registers (on pci 414 * config space), get it not polite way. 415 */ 416 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 417 418 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 419 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 420 /* The address must be valid. */ 421 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 422 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 423 printf("%s: can't map socket base address 0x%x\n", 424 sc->sc_dev.dv_xname, sock_base); 425 /* 426 * I think it's funny: socket base registers must be 427 * mapped on memory space, but ... 428 */ 429 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 430 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 431 NULL)) { 432 printf("%s: can't map socket base address" 433 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 434 sockbase); 435 /* give up... allocate reg space via rbus. */ 436 sc->sc_base_memh = 0; 437 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 438 } 439 } else { 440 DPRINTF(("%s: socket base address 0x%lx\n", 441 sc->sc_dev.dv_xname, sockbase)); 442 } 443 } 444 445 sc->sc_mem_start = 0; /* XXX */ 446 sc->sc_mem_end = 0xffffffff; /* XXX */ 447 448 /* 449 * When interrupt isn't routed correctly, give up probing cbb and do 450 * not kill pcic-compatible port. 451 */ 452 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 453 printf("%s: NOT USED because of unconfigured interrupt\n", 454 sc->sc_dev.dv_xname); 455 return; 456 } 457 458 /* 459 * When bus number isn't set correctly, give up using 32-bit CardBus 460 * mode. 461 */ 462 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 463 #if notyet 464 if (((busreg >> 8) & 0xff) == 0) { 465 printf("%s: CardBus support disabled because of unconfigured bus number\n", 466 sc->sc_dev.dv_xname); 467 flags |= PCCBB_PCMCIA_16BITONLY; 468 } 469 #endif 470 471 /* pccbb_machdep.c end */ 472 473 #if defined CBB_DEBUG 474 { 475 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 476 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 477 intrname[pa->pa_intrpin], pa->pa_intrline); 478 } 479 #endif 480 481 /* setup softc */ 482 sc->sc_pc = pc; 483 sc->sc_iot = pa->pa_iot; 484 sc->sc_memt = pa->pa_memt; 485 sc->sc_dmat = pa->pa_dmat; 486 sc->sc_tag = pa->pa_tag; 487 sc->sc_function = pa->pa_function; 488 489 sc->sc_intrline = pa->pa_intrline; 490 sc->sc_intrtag = pa->pa_intrtag; 491 sc->sc_intrpin = pa->pa_intrpin; 492 493 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 494 495 shutdownhook_establish(pccbb_shutdown, sc); 496 497 /* Disable legacy register mapping. */ 498 switch (sc->sc_chipset) { 499 case CB_RX5C46X: /* fallthrough */ 500 #if 0 501 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 502 case CB_RX5C47X: 503 #endif 504 /* 505 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 506 * cannot be disabled by substituting 0 into PCI_LEGACY 507 * register. Ricoh CardBus bridges have special bits on Bridge 508 * control reg (addr 0x3e on PCI config space). 509 */ 510 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 511 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 512 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 513 break; 514 515 default: 516 /* XXX I don't know proper way to kill legacy I/O. */ 517 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 518 break; 519 } 520 521 config_defer(self, pccbb_pci_callback); 522 } 523 524 525 526 527 /* 528 * static void pccbb_pci_callback(struct device *self) 529 * 530 * The actual attach routine: get memory space for YENTA register 531 * space, setup YENTA register and route interrupt. 532 * 533 * This function should be deferred because this device may obtain 534 * memory space dynamically. This function must avoid obtaining 535 * memory area which has already kept for another device. 536 */ 537 static void 538 pccbb_pci_callback(self) 539 struct device *self; 540 { 541 struct pccbb_softc *sc = (void *)self; 542 pci_chipset_tag_t pc = sc->sc_pc; 543 bus_space_tag_t base_memt; 544 bus_space_handle_t base_memh; 545 u_int32_t maskreg; 546 pci_intr_handle_t ih; 547 const char *intrstr = NULL; 548 bus_addr_t sockbase; 549 struct cbslot_attach_args cba; 550 struct pcmciabus_attach_args paa; 551 struct cardslot_attach_args caa; 552 struct cardslot_softc *csc; 553 554 if (0 == sc->sc_base_memh) { 555 /* The socket registers aren't mapped correctly. */ 556 #if rbus 557 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 558 (sc->sc_chipset == CB_RX5C47X 559 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 560 0, &sockbase, &sc->sc_base_memh)) { 561 return; 562 } 563 sc->sc_base_memt = sc->sc_memt; 564 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 565 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 566 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 567 PCI_SOCKBASE))); 568 #else 569 sc->sc_base_memt = sc->sc_memt; 570 #if !defined CBB_PCI_BASE 571 #define CBB_PCI_BASE 0x20000000 572 #endif 573 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 574 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 575 /* cannot allocate memory space */ 576 return; 577 } 578 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 579 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 580 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 581 sc->sc_tag, PCI_SOCKBASE))); 582 #endif 583 } 584 585 /* bus bridge initialization */ 586 pccbb_chipinit(sc); 587 588 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 589 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 590 591 /* CSC Interrupt: Card detect interrupt on */ 592 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 593 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 594 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 595 /* reset interrupt */ 596 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 597 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 598 599 /* clear data structure for child device interrupt handlers */ 600 sc->sc_pil = NULL; 601 sc->sc_pil_intr_enable = 1; 602 603 /* Map and establish the interrupt. */ 604 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 605 sc->sc_intrline, &ih)) { 606 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 607 return; 608 } 609 intrstr = pci_intr_string(pc, ih); 610 611 /* 612 * XXX pccbbintr should be called under the priority lower 613 * than any other hard interrputs. 614 */ 615 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 616 617 if (sc->sc_ih == NULL) { 618 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 619 if (intrstr != NULL) { 620 printf(" at %s", intrstr); 621 } 622 printf("\n"); 623 return; 624 } 625 626 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 627 powerhook_establish(pccbb_powerhook, sc); 628 629 { 630 u_int32_t sockstat = 631 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 632 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 633 sc->sc_flags |= CBB_CARDEXIST; 634 } 635 } 636 637 /* 638 * attach cardbus 639 */ 640 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 641 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 642 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 643 644 /* initialize cbslot_attach */ 645 cba.cba_busname = "cardbus"; 646 cba.cba_iot = sc->sc_iot; 647 cba.cba_memt = sc->sc_memt; 648 cba.cba_dmat = sc->sc_dmat; 649 cba.cba_bus = (busreg >> 8) & 0x0ff; 650 cba.cba_cc = (void *)sc; 651 cba.cba_cf = &pccbb_funcs; 652 cba.cba_intrline = sc->sc_intrline; 653 654 #if rbus 655 cba.cba_rbus_iot = sc->sc_rbus_iot; 656 cba.cba_rbus_memt = sc->sc_rbus_memt; 657 #endif 658 659 cba.cba_cacheline = PCI_CACHELINE(bhlc); 660 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 661 662 printf("%s: cacheline 0x%x lattimer 0x%x\n", 663 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 664 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 665 busreg); 666 #if defined SHOW_REGS 667 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 668 sc->sc_base_memh); 669 #endif 670 } 671 672 pccbb_pcmcia_attach_setup(sc, &paa); 673 caa.caa_cb_attach = NULL; 674 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 675 caa.caa_cb_attach = &cba; 676 } 677 caa.caa_16_attach = &paa; 678 caa.caa_ph = &sc->sc_pcmcia_h; 679 680 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 681 DPRINTF(("pccbbattach: found cardslot\n")); 682 sc->sc_csc = csc; 683 } 684 685 return; 686 } 687 688 689 690 691 692 /* 693 * static void pccbb_chipinit(struct pccbb_softc *sc) 694 * 695 * This function initialize YENTA chip registers listed below: 696 * 1) PCI command reg, 697 * 2) PCI and CardBus latency timer, 698 * 3) route PCI interrupt, 699 * 4) close all memory and io windows. 700 */ 701 static void 702 pccbb_chipinit(sc) 703 struct pccbb_softc *sc; 704 { 705 pci_chipset_tag_t pc = sc->sc_pc; 706 pcitag_t tag = sc->sc_tag; 707 pcireg_t reg; 708 709 /* 710 * Set PCI command reg. 711 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 712 */ 713 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 714 /* I believe it is harmless. */ 715 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 716 PCI_COMMAND_MASTER_ENABLE); 717 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 718 719 /* 720 * Set CardBus latency timer. 721 */ 722 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 723 if (PCI_CB_LATENCY(reg) < 0x20) { 724 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 725 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 726 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 727 } 728 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 729 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 730 731 /* 732 * Set PCI latency timer. 733 */ 734 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 735 if (PCI_LATTIMER(reg) < 0x10) { 736 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 737 reg |= (0x10 << PCI_LATTIMER_SHIFT); 738 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 739 } 740 DPRINTF(("PCI latency timer 0x%x (%x)\n", 741 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 742 743 744 /* Route functional interrupts to PCI. */ 745 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 746 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 747 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 748 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 749 750 switch (sc->sc_chipset) { 751 case CB_TI113X: 752 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 753 /* This bit is shared, but may read as 0 on some chips, so set 754 it explicitly on both functions. */ 755 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 756 /* CSC intr enable */ 757 reg |= PCI113X_CBCTRL_PCI_CSC; 758 /* functional intr prohibit | prohibit ISA routing */ 759 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 760 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 761 break; 762 763 case CB_TOPIC95B: 764 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 765 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 766 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 767 768 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 769 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 770 sc->sc_dev.dv_xname, reg)); 771 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 772 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 773 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 774 DPRINTF(("0x%x\n", reg)); 775 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 776 break; 777 } 778 779 /* Close all memory and I/O windows. */ 780 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 781 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 782 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 783 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 784 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 785 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 786 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 787 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 788 } 789 790 791 792 793 /* 794 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 795 * struct pcmciabus_attach_args *paa) 796 * 797 * This function attaches 16-bit PCcard bus. 798 */ 799 STATIC void 800 pccbb_pcmcia_attach_setup(sc, paa) 801 struct pccbb_softc *sc; 802 struct pcmciabus_attach_args *paa; 803 { 804 struct pcic_handle *ph = &sc->sc_pcmcia_h; 805 #if rbus 806 rbus_tag_t rb; 807 #endif 808 809 /* initialize pcmcia part in pccbb_softc */ 810 ph->ph_parent = (struct device *)sc; 811 ph->sock = sc->sc_function; 812 ph->flags = 0; 813 ph->shutdown = 0; 814 ph->ih_irq = sc->sc_intrline; 815 ph->ph_bus_t = sc->sc_base_memt; 816 ph->ph_bus_h = sc->sc_base_memh; 817 ph->ph_read = pccbb_pcmcia_read; 818 ph->ph_write = pccbb_pcmcia_write; 819 sc->sc_pct = &pccbb_pcmcia_funcs; 820 821 /* 822 * We need to do a few things here: 823 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 824 * setting the IRQ numbers to 0. 825 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 826 * routing of CSC interrupts (e.g. card removal) to PCI while in 827 * PCMCIA mode. We just leave this set all the time. 828 * 3) Enable card insertion/removal interrupts in case the chip also 829 * needs that while in PCMCIA mode. 830 * 4) Clear any pending CSC interrupt. 831 */ 832 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 833 if (sc->sc_chipset == CB_TI113X) { 834 Pcic_write(ph, PCIC_CSC_INTR, 0); 835 } else { 836 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 837 Pcic_read(ph, PCIC_CSC); 838 } 839 840 /* initialize pcmcia bus attachment */ 841 paa->paa_busname = "pcmcia"; 842 paa->pct = sc->sc_pct; 843 paa->pch = ph; 844 paa->iobase = 0; /* I don't use them */ 845 paa->iosize = 0; 846 #if rbus 847 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 848 paa->iobase = rb->rb_start + rb->rb_offset; 849 paa->iosize = rb->rb_end - rb->rb_start; 850 #endif 851 852 return; 853 } 854 855 #if 0 856 STATIC void 857 pccbb_pcmcia_attach_card(ph) 858 struct pcic_handle *ph; 859 { 860 if (ph->flags & PCIC_FLAG_CARDP) { 861 panic("pccbb_pcmcia_attach_card: already attached"); 862 } 863 864 /* call the MI attach function */ 865 pcmcia_card_attach(ph->pcmcia); 866 867 ph->flags |= PCIC_FLAG_CARDP; 868 } 869 870 STATIC void 871 pccbb_pcmcia_detach_card(ph, flags) 872 struct pcic_handle *ph; 873 int flags; 874 { 875 if (!(ph->flags & PCIC_FLAG_CARDP)) { 876 panic("pccbb_pcmcia_detach_card: already detached"); 877 } 878 879 ph->flags &= ~PCIC_FLAG_CARDP; 880 881 /* call the MI detach function */ 882 pcmcia_card_detach(ph->pcmcia, flags); 883 } 884 #endif 885 886 /* 887 * int pccbbintr(arg) 888 * void *arg; 889 * This routine handles the interrupt from Yenta PCI-CardBus bridge 890 * itself. 891 */ 892 int 893 pccbbintr(arg) 894 void *arg; 895 { 896 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 897 u_int32_t sockevent, sockstate; 898 bus_space_tag_t memt = sc->sc_base_memt; 899 bus_space_handle_t memh = sc->sc_base_memh; 900 struct pcic_handle *ph = &sc->sc_pcmcia_h; 901 902 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 903 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 904 Pcic_read(ph, PCIC_CSC); 905 906 if (sockevent == 0) { 907 /* This intr is not for me: it may be for my child devices. */ 908 if (sc->sc_pil_intr_enable) { 909 return pccbbintr_function(sc); 910 } else { 911 return 0; 912 } 913 } 914 915 if (sockevent & CB_SOCKET_EVENT_CD) { 916 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 917 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 918 /* A card should be removed. */ 919 if (sc->sc_flags & CBB_CARDEXIST) { 920 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 921 sockevent)); 922 DPRINTF((" card removed, 0x%08x\n", sockstate)); 923 sc->sc_flags &= ~CBB_CARDEXIST; 924 if (sc->sc_csc->sc_status & 925 CARDSLOT_STATUS_CARD_16) { 926 #if 0 927 struct pcic_handle *ph = 928 &sc->sc_pcmcia_h; 929 930 pcmcia_card_deactivate(ph->pcmcia); 931 pccbb_pcmcia_socket_disable(ph); 932 pccbb_pcmcia_detach_card(ph, 933 DETACH_FORCE); 934 #endif 935 cardslot_event_throw(sc->sc_csc, 936 CARDSLOT_EVENT_REMOVAL_16); 937 } else if (sc->sc_csc->sc_status & 938 CARDSLOT_STATUS_CARD_CB) { 939 /* Cardbus intr removed */ 940 cardslot_event_throw(sc->sc_csc, 941 CARDSLOT_EVENT_REMOVAL_CB); 942 } 943 } 944 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 945 /* 946 * The pccbbintr may called from powerdown hook when 947 * the system resumed, to detect the card 948 * insertion/removal during suspension. 949 */ 950 (sc->sc_flags & CBB_CARDEXIST) == 0) { 951 if (sc->sc_flags & CBB_INSERTING) { 952 callout_stop(&sc->sc_insert_ch); 953 } 954 callout_reset(&sc->sc_insert_ch, hz / 10, 955 pci113x_insert, sc); 956 sc->sc_flags |= CBB_INSERTING; 957 } 958 } 959 960 return (1); 961 } 962 963 /* 964 * static int pccbbintr_function(struct pccbb_softc *sc) 965 * 966 * This function calls each interrupt handler registered at the 967 * bridge. The interrupt handlers are called in registered order. 968 */ 969 static int 970 pccbbintr_function(sc) 971 struct pccbb_softc *sc; 972 { 973 int retval = 0, val; 974 struct pccbb_intrhand_list *pil; 975 int s, splchanged; 976 977 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 978 /* 979 * XXX priority change. gross. I use if-else 980 * sentense instead of switch-case sentense because of 981 * avoiding duplicate case value error. More than one 982 * IPL_XXX use same value. It depends on 983 * implimentation. 984 */ 985 splchanged = 1; 986 if (pil->pil_level == IPL_SERIAL) { 987 s = splserial(); 988 } else if (pil->pil_level == IPL_HIGH) { 989 s = splhigh(); 990 } else if (pil->pil_level == IPL_CLOCK) { 991 s = splclock(); 992 } else if (pil->pil_level == IPL_AUDIO) { 993 s = splaudio(); 994 } else if (pil->pil_level == IPL_IMP) { 995 s = splimp(); 996 } else if (pil->pil_level == IPL_TTY) { 997 s = spltty(); 998 } else if (pil->pil_level == IPL_SOFTSERIAL) { 999 s = splsoftserial(); 1000 } else if (pil->pil_level == IPL_NET) { 1001 s = splnet(); 1002 } else { 1003 splchanged = 0; 1004 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1005 } 1006 1007 val = (*pil->pil_func)(pil->pil_arg); 1008 1009 if (splchanged != 0) { 1010 splx(s); 1011 } 1012 1013 retval = retval == 1 ? 1 : 1014 retval == 0 ? val : val != 0 ? val : retval; 1015 } 1016 1017 return retval; 1018 } 1019 1020 static void 1021 pci113x_insert(arg) 1022 void *arg; 1023 { 1024 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1025 u_int32_t sockevent, sockstate; 1026 1027 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1028 CB_SOCKET_EVENT); 1029 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1030 CB_SOCKET_STAT); 1031 1032 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1033 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1034 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1035 sc->sc_flags |= CBB_CARDEXIST; 1036 /* call pccard interrupt handler here */ 1037 if (sockstate & CB_SOCKET_STAT_16BIT) { 1038 /* 16-bit card found */ 1039 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1040 cardslot_event_throw(sc->sc_csc, 1041 CARDSLOT_EVENT_INSERTION_16); 1042 } else if (sockstate & CB_SOCKET_STAT_CB) { 1043 /* cardbus card found */ 1044 /* cardbus_attach_card(sc->sc_csc); */ 1045 cardslot_event_throw(sc->sc_csc, 1046 CARDSLOT_EVENT_INSERTION_CB); 1047 } else { 1048 /* who are you? */ 1049 } 1050 } else { 1051 callout_reset(&sc->sc_insert_ch, hz / 10, 1052 pci113x_insert, sc); 1053 } 1054 } 1055 1056 #define PCCBB_PCMCIA_OFFSET 0x800 1057 static u_int8_t 1058 pccbb_pcmcia_read(ph, reg) 1059 struct pcic_handle *ph; 1060 int reg; 1061 { 1062 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1063 PCCBB_PCMCIA_OFFSET + reg); 1064 } 1065 1066 static void 1067 pccbb_pcmcia_write(ph, reg, val) 1068 struct pcic_handle *ph; 1069 int reg; 1070 u_int8_t val; 1071 { 1072 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1073 val); 1074 } 1075 1076 /* 1077 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1078 */ 1079 STATIC int 1080 pccbb_ctrl(ct, command) 1081 cardbus_chipset_tag_t ct; 1082 int command; 1083 { 1084 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1085 1086 switch (command) { 1087 case CARDBUS_CD: 1088 if (2 == pccbb_detect_card(sc)) { 1089 int retval = 0; 1090 int status = cb_detect_voltage(sc); 1091 if (PCCARD_VCC_5V & status) { 1092 retval |= CARDBUS_5V_CARD; 1093 } 1094 if (PCCARD_VCC_3V & status) { 1095 retval |= CARDBUS_3V_CARD; 1096 } 1097 if (PCCARD_VCC_XV & status) { 1098 retval |= CARDBUS_XV_CARD; 1099 } 1100 if (PCCARD_VCC_YV & status) { 1101 retval |= CARDBUS_YV_CARD; 1102 } 1103 return retval; 1104 } else { 1105 return 0; 1106 } 1107 break; 1108 case CARDBUS_RESET: 1109 return cb_reset(sc); 1110 break; 1111 case CARDBUS_IO_ENABLE: /* fallthrough */ 1112 case CARDBUS_IO_DISABLE: /* fallthrough */ 1113 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1114 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1115 case CARDBUS_BM_ENABLE: /* fallthrough */ 1116 case CARDBUS_BM_DISABLE: /* fallthrough */ 1117 return pccbb_cardenable(sc, command); 1118 break; 1119 } 1120 1121 return 0; 1122 } 1123 1124 /* 1125 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1126 * This function returns true when it succeeds and returns false when 1127 * it fails. 1128 */ 1129 STATIC int 1130 pccbb_power(ct, command) 1131 cardbus_chipset_tag_t ct; 1132 int command; 1133 { 1134 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1135 1136 u_int32_t status, sock_ctrl; 1137 bus_space_tag_t memt = sc->sc_base_memt; 1138 bus_space_handle_t memh = sc->sc_base_memh; 1139 1140 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1141 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1142 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1143 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1144 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1145 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1146 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1147 "UNKNOWN", 1148 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1149 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1150 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1151 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1152 "UNKNOWN", command)); 1153 1154 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1155 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1156 1157 switch (command & CARDBUS_VCCMASK) { 1158 case CARDBUS_VCC_UC: 1159 break; 1160 case CARDBUS_VCC_5V: 1161 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1162 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1163 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1164 } else { 1165 printf("%s: BAD voltage request: no 5 V card\n", 1166 sc->sc_dev.dv_xname); 1167 } 1168 break; 1169 case CARDBUS_VCC_3V: 1170 if (CB_SOCKET_STAT_3VCARD & status) { 1171 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1172 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1173 } else { 1174 printf("%s: BAD voltage request: no 3.3 V card\n", 1175 sc->sc_dev.dv_xname); 1176 } 1177 break; 1178 case CARDBUS_VCC_0V: 1179 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1180 break; 1181 default: 1182 return 0; /* power NEVER changed */ 1183 break; 1184 } 1185 1186 switch (command & CARDBUS_VPPMASK) { 1187 case CARDBUS_VPP_UC: 1188 break; 1189 case CARDBUS_VPP_0V: 1190 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1191 break; 1192 case CARDBUS_VPP_VCC: 1193 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1194 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1195 break; 1196 case CARDBUS_VPP_12V: 1197 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1198 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1199 break; 1200 } 1201 1202 #if 0 1203 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1204 #endif 1205 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1206 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1207 1208 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1209 /* 1210 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1211 * time is 20 ms, some PC-Card bridge requires longer duration. 1212 */ 1213 delay(200 * 1000); 1214 1215 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1216 printf 1217 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1218 sc->sc_dev.dv_xname, sock_ctrl, status); 1219 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1220 (command & CARDBUS_VCCMASK) == 1221 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1222 CARDBUS_VCCMASK) == 1223 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1224 CARDBUS_VCCMASK) == 1225 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1226 CARDBUS_VCCMASK) == 1227 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1228 CARDBUS_VCCMASK) == 1229 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1230 CARDBUS_VCCMASK) == 1231 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1232 (command & CARDBUS_VPPMASK) == 1233 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1234 CARDBUS_VPPMASK) == 1235 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1236 CARDBUS_VPPMASK) == 1237 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1238 CARDBUS_VPPMASK) == 1239 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1240 #if 0 1241 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1242 u_int32_t force = 1243 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1244 /* Reset Bad Vcc request */ 1245 force &= ~CB_SOCKET_FORCE_BADVCC; 1246 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1247 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1248 CB_SOCKET_STAT)); 1249 return 1; 1250 } 1251 #endif 1252 return 0; 1253 } 1254 return 1; /* power changed correctly */ 1255 } 1256 1257 #if defined CB_PCMCIA_POLL 1258 struct cb_poll_str { 1259 void *arg; 1260 int (*func) __P((void *)); 1261 int level; 1262 pccard_chipset_tag_t ct; 1263 int count; 1264 struct callout poll_ch; 1265 }; 1266 1267 static struct cb_poll_str cb_poll[10]; 1268 static int cb_poll_n = 0; 1269 1270 static void cb_pcmcia_poll __P((void *arg)); 1271 1272 static void 1273 cb_pcmcia_poll(arg) 1274 void *arg; 1275 { 1276 struct cb_poll_str *poll = arg; 1277 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1278 struct pccbb_softc *sc = psc->cpc_parent; 1279 int s; 1280 u_int32_t spsr; /* socket present-state reg */ 1281 1282 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1283 switch (poll->level) { 1284 case IPL_NET: 1285 s = splnet(); 1286 break; 1287 case IPL_BIO: 1288 s = splbio(); 1289 break; 1290 case IPL_TTY: /* fallthrough */ 1291 default: 1292 s = spltty(); 1293 break; 1294 } 1295 1296 spsr = 1297 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1298 CB_SOCKET_STAT); 1299 1300 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1301 if (!(spsr & 0x40)) { /* CINT low */ 1302 #else 1303 if (1) { 1304 #endif 1305 if ((*poll->func) (poll->arg) == 1) { 1306 ++poll->count; 1307 printf("intr: reported from poller, 0x%x\n", spsr); 1308 #if defined LEVEL2 1309 } else { 1310 printf("intr: miss! 0x%x\n", spsr); 1311 #endif 1312 } 1313 } 1314 splx(s); 1315 } 1316 #endif /* defined CB_PCMCIA_POLL */ 1317 1318 /* 1319 * static int pccbb_detect_card(struct pccbb_softc *sc) 1320 * return value: 0 if no card exists. 1321 * 1 if 16-bit card exists. 1322 * 2 if cardbus card exists. 1323 */ 1324 static int 1325 pccbb_detect_card(sc) 1326 struct pccbb_softc *sc; 1327 { 1328 bus_space_handle_t base_memh = sc->sc_base_memh; 1329 bus_space_tag_t base_memt = sc->sc_base_memt; 1330 u_int32_t sockstat = 1331 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1332 int retval = 0; 1333 1334 /* CD1 and CD2 asserted */ 1335 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1336 /* card must be present */ 1337 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1338 /* NOTACARD DEASSERTED */ 1339 if (CB_SOCKET_STAT_CB & sockstat) { 1340 /* CardBus mode */ 1341 retval = 2; 1342 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1343 /* 16-bit mode */ 1344 retval = 1; 1345 } 1346 } 1347 } 1348 return retval; 1349 } 1350 1351 /* 1352 * STATIC int cb_reset(struct pccbb_softc *sc) 1353 * This function resets CardBus card. 1354 */ 1355 STATIC int 1356 cb_reset(sc) 1357 struct pccbb_softc *sc; 1358 { 1359 /* 1360 * Reset Assert at least 20 ms 1361 * Some machines request longer duration. 1362 */ 1363 int reset_duration = 1364 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1365 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1366 1367 /* Reset bit Assert (bit 6 at 0x3E) */ 1368 bcr |= CB_BCR_RESET_ENABLE; 1369 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1370 delay(reset_duration); 1371 1372 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1373 /* Reset bit Deassert (bit 6 at 0x3E) */ 1374 bcr &= ~CB_BCR_RESET_ENABLE; 1375 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1376 delay(reset_duration); 1377 } 1378 /* No card found on the slot. Keep Reset. */ 1379 return 1; 1380 } 1381 1382 /* 1383 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1384 * This function detect card Voltage. 1385 */ 1386 STATIC int 1387 cb_detect_voltage(sc) 1388 struct pccbb_softc *sc; 1389 { 1390 u_int32_t psr; /* socket present-state reg */ 1391 bus_space_tag_t iot = sc->sc_base_memt; 1392 bus_space_handle_t ioh = sc->sc_base_memh; 1393 int vol = PCCARD_VCC_UKN; /* set 0 */ 1394 1395 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1396 1397 if (0x400u & psr) { 1398 vol |= PCCARD_VCC_5V; 1399 } 1400 if (0x800u & psr) { 1401 vol |= PCCARD_VCC_3V; 1402 } 1403 1404 return vol; 1405 } 1406 1407 STATIC int 1408 cbbprint(aux, pcic) 1409 void *aux; 1410 const char *pcic; 1411 { 1412 /* 1413 struct cbslot_attach_args *cba = aux; 1414 1415 if (cba->cba_slot >= 0) { 1416 printf(" slot %d", cba->cba_slot); 1417 } 1418 */ 1419 return UNCONF; 1420 } 1421 1422 /* 1423 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1424 * This function enables and disables the card 1425 */ 1426 STATIC int 1427 pccbb_cardenable(sc, function) 1428 struct pccbb_softc *sc; 1429 int function; 1430 { 1431 u_int32_t command = 1432 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1433 1434 DPRINTF(("pccbb_cardenable:")); 1435 switch (function) { 1436 case CARDBUS_IO_ENABLE: 1437 command |= PCI_COMMAND_IO_ENABLE; 1438 break; 1439 case CARDBUS_IO_DISABLE: 1440 command &= ~PCI_COMMAND_IO_ENABLE; 1441 break; 1442 case CARDBUS_MEM_ENABLE: 1443 command |= PCI_COMMAND_MEM_ENABLE; 1444 break; 1445 case CARDBUS_MEM_DISABLE: 1446 command &= ~PCI_COMMAND_MEM_ENABLE; 1447 break; 1448 case CARDBUS_BM_ENABLE: 1449 command |= PCI_COMMAND_MASTER_ENABLE; 1450 break; 1451 case CARDBUS_BM_DISABLE: 1452 command &= ~PCI_COMMAND_MASTER_ENABLE; 1453 break; 1454 default: 1455 return 0; 1456 } 1457 1458 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1459 DPRINTF((" command reg 0x%x\n", command)); 1460 return 1; 1461 } 1462 1463 #if !rbus 1464 /* 1465 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1466 */ 1467 static int 1468 pccbb_io_open(ct, win, start, end) 1469 cardbus_chipset_tag_t ct; 1470 int win; 1471 u_int32_t start, end; 1472 { 1473 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1474 int basereg; 1475 int limitreg; 1476 1477 if ((win < 0) || (win > 2)) { 1478 #if defined DIAGNOSTIC 1479 printf("cardbus_io_open: window out of range %d\n", win); 1480 #endif 1481 return 0; 1482 } 1483 1484 basereg = win * 8 + 0x2c; 1485 limitreg = win * 8 + 0x30; 1486 1487 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1488 start, basereg, end, limitreg)); 1489 1490 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1491 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1492 return 1; 1493 } 1494 1495 /* 1496 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1497 */ 1498 static int 1499 pccbb_io_close(ct, win) 1500 cardbus_chipset_tag_t ct; 1501 int win; 1502 { 1503 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1504 int basereg; 1505 int limitreg; 1506 1507 if ((win < 0) || (win > 2)) { 1508 #if defined DIAGNOSTIC 1509 printf("cardbus_io_close: window out of range %d\n", win); 1510 #endif 1511 return 0; 1512 } 1513 1514 basereg = win * 8 + 0x2c; 1515 limitreg = win * 8 + 0x30; 1516 1517 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1518 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1519 return 1; 1520 } 1521 1522 /* 1523 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1524 */ 1525 static int 1526 pccbb_mem_open(ct, win, start, end) 1527 cardbus_chipset_tag_t ct; 1528 int win; 1529 u_int32_t start, end; 1530 { 1531 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1532 int basereg; 1533 int limitreg; 1534 1535 if ((win < 0) || (win > 2)) { 1536 #if defined DIAGNOSTIC 1537 printf("cardbus_mem_open: window out of range %d\n", win); 1538 #endif 1539 return 0; 1540 } 1541 1542 basereg = win * 8 + 0x1c; 1543 limitreg = win * 8 + 0x20; 1544 1545 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1546 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1547 return 1; 1548 } 1549 1550 /* 1551 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1552 */ 1553 static int 1554 pccbb_mem_close(ct, win) 1555 cardbus_chipset_tag_t ct; 1556 int win; 1557 { 1558 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1559 int basereg; 1560 int limitreg; 1561 1562 if ((win < 0) || (win > 2)) { 1563 #if defined DIAGNOSTIC 1564 printf("cardbus_mem_close: window out of range %d\n", win); 1565 #endif 1566 return 0; 1567 } 1568 1569 basereg = win * 8 + 0x1c; 1570 limitreg = win * 8 + 0x20; 1571 1572 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1573 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1574 return 1; 1575 } 1576 #endif 1577 1578 /* 1579 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1580 * int irq, 1581 * int level, 1582 * int (* func) __P((void *)), 1583 * void *arg) 1584 * 1585 * This function registers an interrupt handler at the bridge, in 1586 * order not to call the interrupt handlers of child devices when 1587 * a card-deletion interrupt occurs. 1588 * 1589 * The arguments irq and level are not used. 1590 */ 1591 static void * 1592 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1593 cardbus_chipset_tag_t ct; 1594 int irq, level; 1595 int (*func) __P((void *)); 1596 void *arg; 1597 { 1598 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1599 1600 return pccbb_intr_establish(sc, irq, level, func, arg); 1601 } 1602 1603 1604 /* 1605 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1606 * void *ih) 1607 * 1608 * This function removes an interrupt handler pointed by ih. 1609 */ 1610 static void 1611 pccbb_cb_intr_disestablish(ct, ih) 1612 cardbus_chipset_tag_t ct; 1613 void *ih; 1614 { 1615 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1616 1617 pccbb_intr_disestablish(sc, ih); 1618 } 1619 1620 1621 /* 1622 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1623 * int irq, 1624 * int level, 1625 * int (* func) __P((void *)), 1626 * void *arg) 1627 * 1628 * This function registers an interrupt handler at the bridge, in 1629 * order not to call the interrupt handlers of child devices when 1630 * a card-deletion interrupt occurs. 1631 * 1632 * The arguments irq is not used because pccbb selects intr vector. 1633 */ 1634 static void * 1635 pccbb_intr_establish(sc, irq, level, func, arg) 1636 struct pccbb_softc *sc; 1637 int irq, level; 1638 int (*func) __P((void *)); 1639 void *arg; 1640 { 1641 struct pccbb_intrhand_list *pil, *newpil; 1642 1643 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1644 1645 if (sc->sc_pil == NULL) { 1646 /* initialize bridge intr routing */ 1647 1648 switch (sc->sc_chipset) { 1649 case CB_TI113X: 1650 { 1651 pcireg_t cbctrl = 1652 pci_conf_read(sc->sc_pc, sc->sc_tag, 1653 PCI_CBCTRL); 1654 /* functional intr enabled */ 1655 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1656 pci_conf_write(sc->sc_pc, sc->sc_tag, 1657 PCI_CBCTRL, cbctrl); 1658 break; 1659 } 1660 default: 1661 break; 1662 } 1663 } 1664 1665 /* 1666 * Allocate a room for interrupt handler structure. 1667 */ 1668 if (NULL == (newpil = 1669 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1670 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1671 return NULL; 1672 } 1673 1674 newpil->pil_func = func; 1675 newpil->pil_arg = arg; 1676 newpil->pil_level = level; 1677 newpil->pil_next = NULL; 1678 1679 if (sc->sc_pil == NULL) { 1680 sc->sc_pil = newpil; 1681 } else { 1682 for (pil = sc->sc_pil; pil->pil_next != NULL; 1683 pil = pil->pil_next); 1684 pil->pil_next = newpil; 1685 } 1686 1687 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1688 1689 return newpil; 1690 } 1691 1692 /* 1693 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1694 * void *ih) 1695 * 1696 * This function removes an interrupt handler pointed by ih. 1697 */ 1698 static void 1699 pccbb_intr_disestablish(sc, ih) 1700 struct pccbb_softc *sc; 1701 void *ih; 1702 { 1703 struct pccbb_intrhand_list *pil, **pil_prev; 1704 1705 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1706 1707 pil_prev = &sc->sc_pil; 1708 1709 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1710 if (pil == ih) { 1711 *pil_prev = pil->pil_next; 1712 free(pil, M_DEVBUF); 1713 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1714 break; 1715 } 1716 pil_prev = &pil->pil_next; 1717 } 1718 1719 if (sc->sc_pil == NULL) { 1720 /* No interrupt handlers */ 1721 1722 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1723 1724 switch (sc->sc_chipset) { 1725 case CB_TI113X: 1726 { 1727 pcireg_t cbctrl = 1728 pci_conf_read(sc->sc_pc, sc->sc_tag, 1729 PCI_CBCTRL); 1730 /* functional intr disabled */ 1731 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1732 pci_conf_write(sc->sc_pc, sc->sc_tag, 1733 PCI_CBCTRL, cbctrl); 1734 break; 1735 } 1736 default: 1737 break; 1738 } 1739 } 1740 } 1741 1742 #if defined SHOW_REGS 1743 static void 1744 cb_show_regs(pc, tag, memt, memh) 1745 pci_chipset_tag_t pc; 1746 pcitag_t tag; 1747 bus_space_tag_t memt; 1748 bus_space_handle_t memh; 1749 { 1750 int i; 1751 printf("PCI config regs:"); 1752 for (i = 0; i < 0x50; i += 4) { 1753 if (i % 16 == 0) { 1754 printf("\n 0x%02x:", i); 1755 } 1756 printf(" %08x", pci_conf_read(pc, tag, i)); 1757 } 1758 for (i = 0x80; i < 0xb0; i += 4) { 1759 if (i % 16 == 0) { 1760 printf("\n 0x%02x:", i); 1761 } 1762 printf(" %08x", pci_conf_read(pc, tag, i)); 1763 } 1764 1765 if (memh == 0) { 1766 printf("\n"); 1767 return; 1768 } 1769 1770 printf("\nsocket regs:"); 1771 for (i = 0; i <= 0x10; i += 0x04) { 1772 printf(" %08x", bus_space_read_4(memt, memh, i)); 1773 } 1774 printf("\nExCA regs:"); 1775 for (i = 0; i < 0x08; ++i) { 1776 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1777 } 1778 printf("\n"); 1779 return; 1780 } 1781 #endif 1782 1783 /* 1784 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1785 * int busno, int devno, int function) 1786 * This is the function to make a tag to access config space of 1787 * a CardBus Card. It works same as pci_conf_read. 1788 */ 1789 static cardbustag_t 1790 pccbb_make_tag(cc, busno, devno, function) 1791 cardbus_chipset_tag_t cc; 1792 int busno, devno, function; 1793 { 1794 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1795 1796 return pci_make_tag(sc->sc_pc, busno, devno, function); 1797 } 1798 1799 static void 1800 pccbb_free_tag(cc, tag) 1801 cardbus_chipset_tag_t cc; 1802 cardbustag_t tag; 1803 { 1804 } 1805 1806 /* 1807 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1808 * cardbustag_t tag, int offset) 1809 * This is the function to read the config space of a CardBus Card. 1810 * It works same as pci_conf_read. 1811 */ 1812 static cardbusreg_t 1813 pccbb_conf_read(cc, tag, offset) 1814 cardbus_chipset_tag_t cc; 1815 cardbustag_t tag; 1816 int offset; /* register offset */ 1817 { 1818 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1819 1820 return pci_conf_read(sc->sc_pc, tag, offset); 1821 } 1822 1823 /* 1824 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1825 * int offs, cardbusreg_t val) 1826 * This is the function to write the config space of a CardBus Card. 1827 * It works same as pci_conf_write. 1828 */ 1829 static void 1830 pccbb_conf_write(cc, tag, reg, val) 1831 cardbus_chipset_tag_t cc; 1832 cardbustag_t tag; 1833 int reg; /* register offset */ 1834 cardbusreg_t val; 1835 { 1836 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1837 1838 pci_conf_write(sc->sc_pc, tag, reg, val); 1839 } 1840 1841 #if 0 1842 STATIC int 1843 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1844 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1845 int speed, int flags, 1846 bus_space_handle_t * iohp) 1847 #endif 1848 /* 1849 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1850 * bus_addr_t start, bus_size_t size, 1851 * bus_size_t align, 1852 * struct pcmcia_io_handle *pcihp 1853 * 1854 * This function only allocates I/O region for pccard. This function 1855 * never maps the allocated region to pccard I/O area. 1856 * 1857 * XXX: The interface of this function is not very good, I believe. 1858 */ 1859 STATIC int 1860 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1861 pcmcia_chipset_handle_t pch; 1862 bus_addr_t start; /* start address */ 1863 bus_size_t size; 1864 bus_size_t align; 1865 struct pcmcia_io_handle *pcihp; 1866 { 1867 struct pcic_handle *ph = (struct pcic_handle *)pch; 1868 bus_addr_t ioaddr; 1869 int flags = 0; 1870 bus_space_tag_t iot; 1871 bus_space_handle_t ioh; 1872 #if rbus 1873 rbus_tag_t rb; 1874 #endif 1875 if (align == 0) { 1876 align = size; /* XXX: funny??? */ 1877 } 1878 1879 /* 1880 * Allocate some arbitrary I/O space. 1881 */ 1882 1883 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1884 1885 #if rbus 1886 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1887 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1888 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1889 return 1; 1890 } 1891 #else 1892 if (start) { 1893 ioaddr = start; 1894 if (bus_space_map(iot, start, size, 0, &ioh)) { 1895 return 1; 1896 } 1897 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1898 (u_long) ioaddr, (u_long) size)); 1899 } else { 1900 flags |= PCMCIA_IO_ALLOCATED; 1901 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1902 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1903 size, align, 0, 0, &ioaddr, &ioh)) { 1904 /* No room be able to be get. */ 1905 return 1; 1906 } 1907 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1908 (u_long) ioaddr, (u_long) size)); 1909 } 1910 #endif 1911 1912 pcihp->iot = iot; 1913 pcihp->ioh = ioh; 1914 pcihp->addr = ioaddr; 1915 pcihp->size = size; 1916 pcihp->flags = flags; 1917 1918 return 0; 1919 } 1920 1921 /* 1922 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1923 * struct pcmcia_io_handle *pcihp) 1924 * 1925 * This function only frees I/O region for pccard. 1926 * 1927 * XXX: The interface of this function is not very good, I believe. 1928 */ 1929 void 1930 pccbb_pcmcia_io_free(pch, pcihp) 1931 pcmcia_chipset_handle_t pch; 1932 struct pcmcia_io_handle *pcihp; 1933 { 1934 #if !rbus 1935 bus_space_tag_t iot = pcihp->iot; 1936 #endif 1937 bus_space_handle_t ioh = pcihp->ioh; 1938 bus_size_t size = pcihp->size; 1939 1940 #if rbus 1941 struct pccbb_softc *sc = 1942 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1943 rbus_tag_t rb = sc->sc_rbus_iot; 1944 1945 rbus_space_free(rb, ioh, size, NULL); 1946 #else 1947 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1948 bus_space_free(iot, ioh, size); 1949 else 1950 bus_space_unmap(iot, ioh, size); 1951 #endif 1952 } 1953 1954 /* 1955 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1956 * bus_addr_t offset, bus_size_t size, 1957 * struct pcmcia_io_handle *pcihp, 1958 * int *windowp) 1959 * 1960 * This function maps the allocated I/O region to pccard. This function 1961 * never allocates any I/O region for pccard I/O area. I don't 1962 * understand why the original authors of pcmciabus separated alloc and 1963 * map. I believe the two must be unite. 1964 * 1965 * XXX: no wait timing control? 1966 */ 1967 int 1968 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1969 pcmcia_chipset_handle_t pch; 1970 int width; 1971 bus_addr_t offset; 1972 bus_size_t size; 1973 struct pcmcia_io_handle *pcihp; 1974 int *windowp; 1975 { 1976 struct pcic_handle *ph = (struct pcic_handle *)pch; 1977 bus_addr_t ioaddr = pcihp->addr + offset; 1978 int i, win; 1979 #if defined CBB_DEBUG 1980 static char *width_names[] = { "dynamic", "io8", "io16" }; 1981 #endif 1982 1983 /* Sanity check I/O handle. */ 1984 1985 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1986 panic("pccbb_pcmcia_io_map iot is bogus"); 1987 } 1988 1989 /* XXX Sanity check offset/size. */ 1990 1991 win = -1; 1992 for (i = 0; i < PCIC_IO_WINS; i++) { 1993 if ((ph->ioalloc & (1 << i)) == 0) { 1994 win = i; 1995 ph->ioalloc |= (1 << i); 1996 break; 1997 } 1998 } 1999 2000 if (win == -1) { 2001 return 1; 2002 } 2003 2004 *windowp = win; 2005 2006 /* XXX this is pretty gross */ 2007 2008 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2009 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2010 2011 /* XXX wtf is this doing here? */ 2012 2013 #if 0 2014 printf(" port 0x%lx", (u_long) ioaddr); 2015 if (size > 1) { 2016 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2017 } 2018 #endif 2019 2020 ph->io[win].addr = ioaddr; 2021 ph->io[win].size = size; 2022 ph->io[win].width = width; 2023 2024 /* actual dirty register-value changing in the function below. */ 2025 pccbb_pcmcia_do_io_map(ph, win); 2026 2027 return 0; 2028 } 2029 2030 /* 2031 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2032 * 2033 * This function changes register-value to map I/O region for pccard. 2034 */ 2035 static void 2036 pccbb_pcmcia_do_io_map(ph, win) 2037 struct pcic_handle *ph; 2038 int win; 2039 { 2040 static u_int8_t pcic_iowidth[3] = { 2041 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2042 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2043 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2044 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2045 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2046 }; 2047 2048 #define PCIC_SIA_START_LOW 0 2049 #define PCIC_SIA_START_HIGH 1 2050 #define PCIC_SIA_STOP_LOW 2 2051 #define PCIC_SIA_STOP_HIGH 3 2052 2053 int regbase_win = 0x8 + win * 0x04; 2054 u_int8_t ioctl, enable; 2055 2056 DPRINTF( 2057 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2058 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2059 ph->io[win].width * 8)); 2060 2061 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2062 ph->io[win].addr & 0xff); 2063 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2064 (ph->io[win].addr >> 8) & 0xff); 2065 2066 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2067 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2068 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2069 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2070 2071 ioctl = Pcic_read(ph, PCIC_IOCTL); 2072 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2073 switch (win) { 2074 case 0: 2075 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2076 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2077 PCIC_IOCTL_IO0_DATASIZE_MASK); 2078 ioctl |= pcic_iowidth[ph->io[win].width]; 2079 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2080 break; 2081 case 1: 2082 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2083 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2084 PCIC_IOCTL_IO1_DATASIZE_MASK); 2085 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2086 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2087 break; 2088 } 2089 Pcic_write(ph, PCIC_IOCTL, ioctl); 2090 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2091 #if defined CBB_DEBUG 2092 { 2093 u_int8_t start_low = 2094 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2095 u_int8_t start_high = 2096 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2097 u_int8_t stop_low = 2098 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2099 u_int8_t stop_high = 2100 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2101 printf 2102 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2103 start_low, start_high, stop_low, stop_high, ioctl, enable); 2104 } 2105 #endif 2106 } 2107 2108 /* 2109 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2110 * 2111 * This function unmaps I/O region. No return value. 2112 */ 2113 STATIC void 2114 pccbb_pcmcia_io_unmap(pch, win) 2115 pcmcia_chipset_handle_t pch; 2116 int win; 2117 { 2118 struct pcic_handle *ph = (struct pcic_handle *)pch; 2119 int reg; 2120 2121 if (win >= PCIC_IO_WINS || win < 0) { 2122 panic("pccbb_pcmcia_io_unmap: window out of range"); 2123 } 2124 2125 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2126 switch (win) { 2127 case 0: 2128 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2129 break; 2130 case 1: 2131 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2132 break; 2133 } 2134 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2135 2136 ph->ioalloc &= ~(1 << win); 2137 } 2138 2139 /* 2140 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2141 * 2142 * This function enables the card. All information is stored in 2143 * the first argument, pcmcia_chipset_handle_t. 2144 */ 2145 static void 2146 pccbb_pcmcia_wait_ready(ph) 2147 struct pcic_handle *ph; 2148 { 2149 int i; 2150 2151 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2152 Pcic_read(ph, PCIC_IF_STATUS))); 2153 2154 for (i = 0; i < 10000; i++) { 2155 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2156 return; 2157 } 2158 delay(500); 2159 #ifdef CBB_DEBUG 2160 if ((i > 5000) && (i % 100 == 99)) 2161 printf("."); 2162 #endif 2163 } 2164 2165 #ifdef DIAGNOSTIC 2166 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2167 Pcic_read(ph, PCIC_IF_STATUS)); 2168 #endif 2169 } 2170 2171 /* 2172 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2173 * 2174 * This function enables the card. All information is stored in 2175 * the first argument, pcmcia_chipset_handle_t. 2176 */ 2177 STATIC void 2178 pccbb_pcmcia_socket_enable(pch) 2179 pcmcia_chipset_handle_t pch; 2180 { 2181 struct pcic_handle *ph = (struct pcic_handle *)pch; 2182 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2183 int cardtype, win; 2184 u_int8_t power, intr; 2185 pcireg_t spsr; 2186 int voltage; 2187 2188 /* this bit is mostly stolen from pcic_attach_card */ 2189 2190 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2191 2192 /* get card Vcc info */ 2193 2194 spsr = 2195 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2196 CB_SOCKET_STAT); 2197 if (spsr & CB_SOCKET_STAT_5VCARD) { 2198 DPRINTF(("5V card\n")); 2199 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2200 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2201 DPRINTF(("3V card\n")); 2202 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2203 } else { 2204 printf("?V card, 0x%x\n", spsr); /* XXX */ 2205 return; 2206 } 2207 2208 /* assert reset bit */ 2209 intr = Pcic_read(ph, PCIC_INTR); 2210 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2211 Pcic_write(ph, PCIC_INTR, intr); 2212 2213 /* disable socket i/o: negate output enable bit */ 2214 2215 power = Pcic_read(ph, PCIC_PWRCTL); 2216 power &= ~PCIC_PWRCTL_OE; 2217 Pcic_write(ph, PCIC_PWRCTL, power); 2218 2219 /* power down the socket to reset it, clear the card reset pin */ 2220 2221 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2222 2223 /* 2224 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2225 * we are changing Vcc (Toff). 2226 */ 2227 /* delay(300*1000); too much */ 2228 2229 /* power up the socket */ 2230 pccbb_power(sc, voltage); 2231 2232 /* 2233 * wait 100ms until power raise (Tpr) and 20ms to become 2234 * stable (Tsu(Vcc)). 2235 * 2236 * some machines require some more time to be settled 2237 * (another 200ms is added here). 2238 */ 2239 /* delay((100 + 20 + 200)*1000); too much */ 2240 2241 power = Pcic_read(ph, PCIC_PWRCTL); 2242 power |= PCIC_PWRCTL_OE; 2243 Pcic_write(ph, PCIC_PWRCTL, power); 2244 2245 /* 2246 * hold RESET at least 10us. 2247 */ 2248 delay(10); 2249 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2250 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2251 2252 /* clear the reset flag */ 2253 2254 intr |= PCIC_INTR_RESET; 2255 Pcic_write(ph, PCIC_INTR, intr); 2256 2257 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2258 2259 delay(20000); 2260 2261 /* wait for the chip to finish initializing */ 2262 2263 pccbb_pcmcia_wait_ready(ph); 2264 2265 /* zero out the address windows */ 2266 2267 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2268 2269 /* set the card type */ 2270 2271 cardtype = pcmcia_card_gettype(ph->pcmcia); 2272 2273 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2274 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2275 Pcic_write(ph, PCIC_INTR, intr); 2276 2277 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2278 ph->ph_parent->dv_xname, ph->sock, 2279 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2280 2281 /* reinstall all the memory and io mappings */ 2282 2283 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2284 if (ph->memalloc & (1 << win)) { 2285 pccbb_pcmcia_do_mem_map(ph, win); 2286 } 2287 } 2288 2289 for (win = 0; win < PCIC_IO_WINS; ++win) { 2290 if (ph->ioalloc & (1 << win)) { 2291 pccbb_pcmcia_do_io_map(ph, win); 2292 } 2293 } 2294 } 2295 2296 /* 2297 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2298 * 2299 * This function disables the card. All information is stored in 2300 * the first argument, pcmcia_chipset_handle_t. 2301 */ 2302 STATIC void 2303 pccbb_pcmcia_socket_disable(pch) 2304 pcmcia_chipset_handle_t pch; 2305 { 2306 struct pcic_handle *ph = (struct pcic_handle *)pch; 2307 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2308 u_int8_t power, intr; 2309 2310 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2311 2312 /* reset signal asserting... */ 2313 2314 intr = Pcic_read(ph, PCIC_INTR); 2315 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2316 Pcic_write(ph, PCIC_INTR, intr); 2317 delay(2 * 1000); 2318 2319 /* power down the socket */ 2320 power = Pcic_read(ph, PCIC_PWRCTL); 2321 power &= ~PCIC_PWRCTL_OE; 2322 Pcic_write(ph, PCIC_PWRCTL, power); 2323 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2324 /* 2325 * wait 300ms until power fails (Tpf). 2326 */ 2327 delay(300 * 1000); 2328 } 2329 2330 /* 2331 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2332 * 2333 * This function detects whether a card is in the slot or not. 2334 * If a card is inserted, return 1. Otherwise, return 0. 2335 */ 2336 STATIC int 2337 pccbb_pcmcia_card_detect(pch) 2338 pcmcia_chipset_handle_t pch; 2339 { 2340 struct pcic_handle *ph = (struct pcic_handle *)pch; 2341 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2342 2343 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2344 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2345 } 2346 2347 #if 0 2348 STATIC int 2349 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2350 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2351 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2352 #endif 2353 /* 2354 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2355 * bus_size_t size, 2356 * struct pcmcia_mem_handle *pcmhp) 2357 * 2358 * This function only allocates memory region for pccard. This 2359 * function never maps the allocated region to pccard memory area. 2360 * 2361 * XXX: Why the argument of start address is not in? 2362 */ 2363 STATIC int 2364 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2365 pcmcia_chipset_handle_t pch; 2366 bus_size_t size; 2367 struct pcmcia_mem_handle *pcmhp; 2368 { 2369 struct pcic_handle *ph = (struct pcic_handle *)pch; 2370 bus_space_handle_t memh; 2371 bus_addr_t addr; 2372 bus_size_t sizepg; 2373 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2374 #if rbus 2375 rbus_tag_t rb; 2376 #endif 2377 2378 /* out of sc->memh, allocate as many pages as necessary */ 2379 2380 /* convert size to PCIC pages */ 2381 /* 2382 * This is not enough; when the requested region is on the page 2383 * boundaries, this may calculate wrong result. 2384 */ 2385 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2386 #if 0 2387 if (sizepg > PCIC_MAX_MEM_PAGES) { 2388 return 1; 2389 } 2390 #endif 2391 2392 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2393 return 1; 2394 } 2395 2396 addr = 0; /* XXX gcc -Wuninitialized */ 2397 2398 #if rbus 2399 rb = sc->sc_rbus_memt; 2400 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2401 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2402 &addr, &memh)) { 2403 return 1; 2404 } 2405 #else 2406 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2407 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2408 0, /* boundary */ 2409 0, /* flags */ 2410 &addr, &memh)) { 2411 return 1; 2412 } 2413 #endif 2414 2415 DPRINTF( 2416 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2417 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2418 2419 pcmhp->memt = sc->sc_memt; 2420 pcmhp->memh = memh; 2421 pcmhp->addr = addr; 2422 pcmhp->size = size; 2423 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2424 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2425 pcmhp->mhandle = 0; 2426 /* No offset??? Funny. */ 2427 2428 return 0; 2429 } 2430 2431 /* 2432 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2433 * struct pcmcia_mem_handle *pcmhp) 2434 * 2435 * This function release the memory space allocated by the function 2436 * pccbb_pcmcia_mem_alloc(). 2437 */ 2438 STATIC void 2439 pccbb_pcmcia_mem_free(pch, pcmhp) 2440 pcmcia_chipset_handle_t pch; 2441 struct pcmcia_mem_handle *pcmhp; 2442 { 2443 #if rbus 2444 struct pcic_handle *ph = (struct pcic_handle *)pch; 2445 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2446 2447 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2448 #else 2449 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2450 #endif 2451 } 2452 2453 /* 2454 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2455 * 2456 * This function release the memory space allocated by the function 2457 * pccbb_pcmcia_mem_alloc(). 2458 */ 2459 STATIC void 2460 pccbb_pcmcia_do_mem_map(ph, win) 2461 struct pcic_handle *ph; 2462 int win; 2463 { 2464 int regbase_win; 2465 bus_addr_t phys_addr; 2466 bus_addr_t phys_end; 2467 2468 #define PCIC_SMM_START_LOW 0 2469 #define PCIC_SMM_START_HIGH 1 2470 #define PCIC_SMM_STOP_LOW 2 2471 #define PCIC_SMM_STOP_HIGH 3 2472 #define PCIC_CMA_LOW 4 2473 #define PCIC_CMA_HIGH 5 2474 2475 u_int8_t start_low, start_high = 0; 2476 u_int8_t stop_low, stop_high; 2477 u_int8_t off_low, off_high; 2478 u_int8_t mem_window; 2479 int reg; 2480 2481 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2482 int mem8 = 2483 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2484 || (kind == PCMCIA_MEM_ATTR); 2485 2486 regbase_win = 0x10 + win * 0x08; 2487 2488 phys_addr = ph->mem[win].addr; 2489 phys_end = phys_addr + ph->mem[win].size; 2490 2491 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2492 phys_addr, phys_end, ph->mem[win].offset)); 2493 2494 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2495 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2496 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2497 2498 /* bit 19:12 */ 2499 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2500 /* bit 23:20 and bit 7 on */ 2501 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2502 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2503 /* bit 31:24, for 32-bit address */ 2504 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2505 2506 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2507 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2508 2509 if (((struct pccbb_softc *)ph-> 2510 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2511 Pcic_write(ph, 0x40 + win, mem_window); 2512 } 2513 2514 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2515 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2516 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2517 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2518 2519 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2520 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2521 2522 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2523 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2524 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2525 | ((kind == PCMCIA_MEM_ATTR) ? 2526 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2527 2528 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2529 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2530 2531 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2532 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2533 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2534 2535 #if defined CBB_DEBUG 2536 { 2537 int r1, r2, r3, r4, r5, r6, r7 = 0; 2538 2539 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2540 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2541 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2542 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2543 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2544 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2545 if (((struct pccbb_softc *)(ph-> 2546 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2547 r7 = Pcic_read(ph, 0x40 + win); 2548 } 2549 2550 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2551 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2552 if (((struct pccbb_softc *)(ph-> 2553 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2554 DPRINTF((" %02x", r7)); 2555 } 2556 DPRINTF(("\n")); 2557 } 2558 #endif 2559 } 2560 2561 /* 2562 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2563 * bus_addr_t card_addr, bus_size_t size, 2564 * struct pcmcia_mem_handle *pcmhp, 2565 * bus_addr_t *offsetp, int *windowp) 2566 * 2567 * This function maps memory space allocated by the function 2568 * pccbb_pcmcia_mem_alloc(). 2569 */ 2570 STATIC int 2571 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2572 pcmcia_chipset_handle_t pch; 2573 int kind; 2574 bus_addr_t card_addr; 2575 bus_size_t size; 2576 struct pcmcia_mem_handle *pcmhp; 2577 bus_addr_t *offsetp; 2578 int *windowp; 2579 { 2580 struct pcic_handle *ph = (struct pcic_handle *)pch; 2581 bus_addr_t busaddr; 2582 long card_offset; 2583 int win; 2584 2585 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2586 if ((ph->memalloc & (1 << win)) == 0) { 2587 ph->memalloc |= (1 << win); 2588 break; 2589 } 2590 } 2591 2592 if (win == PCIC_MEM_WINS) { 2593 return 1; 2594 } 2595 2596 *windowp = win; 2597 2598 /* XXX this is pretty gross */ 2599 2600 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2601 panic("pccbb_pcmcia_mem_map memt is bogus"); 2602 } 2603 2604 busaddr = pcmhp->addr; 2605 2606 /* 2607 * compute the address offset to the pcmcia address space for the 2608 * pcic. this is intentionally signed. The masks and shifts below 2609 * will cause TRT to happen in the pcic registers. Deal with making 2610 * sure the address is aligned, and return the alignment offset. 2611 */ 2612 2613 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2614 card_addr -= *offsetp; 2615 2616 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2617 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2618 (u_long) card_addr)); 2619 2620 /* 2621 * include the offset in the size, and decrement size by one, since 2622 * the hw wants start/stop 2623 */ 2624 size += *offsetp - 1; 2625 2626 card_offset = (((long)card_addr) - ((long)busaddr)); 2627 2628 ph->mem[win].addr = busaddr; 2629 ph->mem[win].size = size; 2630 ph->mem[win].offset = card_offset; 2631 ph->mem[win].kind = kind; 2632 2633 pccbb_pcmcia_do_mem_map(ph, win); 2634 2635 return 0; 2636 } 2637 2638 /* 2639 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2640 * int window) 2641 * 2642 * This function unmaps memory space which mapped by the function 2643 * pccbb_pcmcia_mem_map(). 2644 */ 2645 STATIC void 2646 pccbb_pcmcia_mem_unmap(pch, window) 2647 pcmcia_chipset_handle_t pch; 2648 int window; 2649 { 2650 struct pcic_handle *ph = (struct pcic_handle *)pch; 2651 int reg; 2652 2653 if (window >= PCIC_MEM_WINS) { 2654 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2655 } 2656 2657 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2658 reg &= ~(1 << window); 2659 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2660 2661 ph->memalloc &= ~(1 << window); 2662 } 2663 2664 #if defined PCCBB_PCMCIA_POLL 2665 struct pccbb_poll_str { 2666 void *arg; 2667 int (*func) __P((void *)); 2668 int level; 2669 struct pcic_handle *ph; 2670 int count; 2671 int num; 2672 struct callout poll_ch; 2673 }; 2674 2675 static struct pccbb_poll_str pccbb_poll[10]; 2676 static int pccbb_poll_n = 0; 2677 2678 static void pccbb_pcmcia_poll __P((void *arg)); 2679 2680 static void 2681 pccbb_pcmcia_poll(arg) 2682 void *arg; 2683 { 2684 struct pccbb_poll_str *poll = arg; 2685 struct pcic_handle *ph = poll->ph; 2686 struct pccbb_softc *sc = ph->sc; 2687 int s; 2688 u_int32_t spsr; /* socket present-state reg */ 2689 2690 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2691 switch (poll->level) { 2692 case IPL_NET: 2693 s = splnet(); 2694 break; 2695 case IPL_BIO: 2696 s = splbio(); 2697 break; 2698 case IPL_TTY: /* fallthrough */ 2699 default: 2700 s = spltty(); 2701 break; 2702 } 2703 2704 spsr = 2705 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2706 CB_SOCKET_STAT); 2707 2708 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2709 if (!(spsr & 0x40)) /* CINT low */ 2710 #else 2711 if (1) 2712 #endif 2713 { 2714 if ((*poll->func) (poll->arg) > 0) { 2715 ++poll->count; 2716 // printf("intr: reported from poller, 0x%x\n", spsr); 2717 #if defined LEVEL2 2718 } else { 2719 printf("intr: miss! 0x%x\n", spsr); 2720 #endif 2721 } 2722 } 2723 splx(s); 2724 } 2725 #endif /* defined CB_PCMCIA_POLL */ 2726 2727 /* 2728 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2729 * struct pcmcia_function *pf, 2730 * int ipl, 2731 * int (*func)(void *), 2732 * void *arg); 2733 * 2734 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2735 */ 2736 STATIC void * 2737 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2738 pcmcia_chipset_handle_t pch; 2739 struct pcmcia_function *pf; 2740 int ipl; 2741 int (*func) __P((void *)); 2742 void *arg; 2743 { 2744 struct pcic_handle *ph = (struct pcic_handle *)pch; 2745 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2746 2747 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2748 /* what should I do? */ 2749 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2750 DPRINTF( 2751 ("%s does not provide edge nor pulse interrupt\n", 2752 sc->sc_dev.dv_xname)); 2753 return NULL; 2754 } 2755 /* 2756 * XXX Noooooo! The interrupt flag must set properly!! 2757 * dumb pcmcia driver!! 2758 */ 2759 } 2760 2761 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2762 } 2763 2764 /* 2765 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2766 * void *ih) 2767 * 2768 * This function disables PC-Card interrupt. 2769 */ 2770 STATIC void 2771 pccbb_pcmcia_intr_disestablish(pch, ih) 2772 pcmcia_chipset_handle_t pch; 2773 void *ih; 2774 { 2775 struct pcic_handle *ph = (struct pcic_handle *)pch; 2776 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2777 2778 pccbb_intr_disestablish(sc, ih); 2779 } 2780 2781 #if rbus 2782 /* 2783 * static int 2784 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2785 * bus_addr_t addr, bus_size_t size, 2786 * bus_addr_t mask, bus_size_t align, 2787 * int flags, bus_addr_t *addrp; 2788 * bus_space_handle_t *bshp) 2789 * 2790 * This function allocates a portion of memory or io space for 2791 * clients. This function is called from CardBus card drivers. 2792 */ 2793 static int 2794 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2795 cardbus_chipset_tag_t ct; 2796 rbus_tag_t rb; 2797 bus_addr_t addr; 2798 bus_size_t size; 2799 bus_addr_t mask; 2800 bus_size_t align; 2801 int flags; 2802 bus_addr_t *addrp; 2803 bus_space_handle_t *bshp; 2804 { 2805 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2806 2807 DPRINTF( 2808 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2809 addr, size, mask, align)); 2810 2811 if (align == 0) { 2812 align = size; 2813 } 2814 2815 if (rb->rb_bt == sc->sc_memt) { 2816 if (align < 16) { 2817 return 1; 2818 } 2819 } else if (rb->rb_bt == sc->sc_iot) { 2820 if (align < 4) { 2821 return 1; 2822 } 2823 /* XXX: hack for avoiding ISA image */ 2824 if (mask < 0x0100) { 2825 mask = 0x3ff; 2826 addr = 0x300; 2827 } 2828 2829 } else { 2830 DPRINTF( 2831 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2832 rb->rb_bt)); 2833 return 1; 2834 /* XXX: panic here? */ 2835 } 2836 2837 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2838 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2839 return 1; 2840 } 2841 2842 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2843 2844 return 0; 2845 } 2846 2847 /* 2848 * static int 2849 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2850 * bus_space_handle_t *bshp, bus_size_t size); 2851 * 2852 * This function is called from CardBus card drivers. 2853 */ 2854 static int 2855 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2856 cardbus_chipset_tag_t ct; 2857 rbus_tag_t rb; 2858 bus_space_handle_t bsh; 2859 bus_size_t size; 2860 { 2861 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2862 bus_space_tag_t bt = rb->rb_bt; 2863 2864 pccbb_close_win(sc, bt, bsh, size); 2865 2866 if (bt == sc->sc_memt) { 2867 } else if (bt == sc->sc_iot) { 2868 } else { 2869 return 1; 2870 /* XXX: panic here? */ 2871 } 2872 2873 return rbus_space_free(rb, bsh, size, NULL); 2874 } 2875 #endif /* rbus */ 2876 2877 #if rbus 2878 2879 static int 2880 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2881 struct pccbb_softc *sc; 2882 bus_space_tag_t bst; 2883 bus_addr_t addr; 2884 bus_size_t size; 2885 bus_space_handle_t bsh; 2886 int flags; 2887 { 2888 struct pccbb_win_chain_head *head; 2889 bus_addr_t align; 2890 2891 head = &sc->sc_iowindow; 2892 align = 0x04; 2893 if (sc->sc_memt == bst) { 2894 head = &sc->sc_memwindow; 2895 align = 0x1000; 2896 DPRINTF(("using memory window, %x %x %x\n\n", 2897 sc->sc_iot, sc->sc_memt, bst)); 2898 } 2899 2900 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2901 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2902 sc->sc_dev.dv_xname, 2903 (head == &sc->sc_memwindow) ? "mem" : "io"); 2904 } 2905 pccbb_winset(align, sc, bst); 2906 2907 return 0; 2908 } 2909 2910 static int 2911 pccbb_close_win(sc, bst, bsh, size) 2912 struct pccbb_softc *sc; 2913 bus_space_tag_t bst; 2914 bus_space_handle_t bsh; 2915 bus_size_t size; 2916 { 2917 struct pccbb_win_chain_head *head; 2918 bus_addr_t align; 2919 2920 head = &sc->sc_iowindow; 2921 align = 0x04; 2922 if (sc->sc_memt == bst) { 2923 head = &sc->sc_memwindow; 2924 align = 0x1000; 2925 } 2926 2927 if (pccbb_winlist_delete(head, bsh, size)) { 2928 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2929 sc->sc_dev.dv_xname, 2930 (head == &sc->sc_memwindow) ? "mem" : "io"); 2931 } 2932 pccbb_winset(align, sc, bst); 2933 2934 return 0; 2935 } 2936 2937 static int 2938 pccbb_winlist_insert(head, start, size, bsh, flags) 2939 struct pccbb_win_chain_head *head; 2940 bus_addr_t start; 2941 bus_size_t size; 2942 bus_space_handle_t bsh; 2943 int flags; 2944 { 2945 struct pccbb_win_chain *chainp, *elem; 2946 2947 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2948 M_NOWAIT)) == NULL) 2949 return (1); /* fail */ 2950 2951 elem->wc_start = start; 2952 elem->wc_end = start + (size - 1); 2953 elem->wc_handle = bsh; 2954 elem->wc_flags = flags; 2955 2956 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2957 chainp = TAILQ_NEXT(chainp, wc_list)) { 2958 if (chainp->wc_end < start) 2959 continue; 2960 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2961 return (0); 2962 } 2963 2964 TAILQ_INSERT_TAIL(head, elem, wc_list); 2965 return (0); 2966 } 2967 2968 static int 2969 pccbb_winlist_delete(head, bsh, size) 2970 struct pccbb_win_chain_head *head; 2971 bus_space_handle_t bsh; 2972 bus_size_t size; 2973 { 2974 struct pccbb_win_chain *chainp; 2975 2976 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2977 chainp = TAILQ_NEXT(chainp, wc_list)) { 2978 if (chainp->wc_handle != bsh) 2979 continue; 2980 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2981 printf("pccbb_winlist_delete: window 0x%lx size " 2982 "inconsistent: 0x%lx, 0x%lx\n", 2983 chainp->wc_start, 2984 chainp->wc_end - chainp->wc_start, 2985 size - 1); 2986 return 1; 2987 } 2988 2989 TAILQ_REMOVE(head, chainp, wc_list); 2990 free(chainp, M_DEVBUF); 2991 2992 return 0; 2993 } 2994 2995 return 1; /* fail: no candidate to remove */ 2996 } 2997 2998 static void 2999 pccbb_winset(align, sc, bst) 3000 bus_addr_t align; 3001 struct pccbb_softc *sc; 3002 bus_space_tag_t bst; 3003 { 3004 pci_chipset_tag_t pc; 3005 pcitag_t tag; 3006 bus_addr_t mask = ~(align - 1); 3007 struct { 3008 cardbusreg_t win_start; 3009 cardbusreg_t win_limit; 3010 int win_flags; 3011 } win[2]; 3012 struct pccbb_win_chain *chainp; 3013 int offs; 3014 3015 win[0].win_start = 0xffffffff; 3016 win[0].win_limit = 0; 3017 win[1].win_start = 0xffffffff; 3018 win[1].win_limit = 0; 3019 3020 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3021 offs = 0x2c; 3022 if (sc->sc_memt == bst) { 3023 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3024 offs = 0x1c; 3025 } 3026 3027 if (chainp != NULL) { 3028 win[0].win_start = chainp->wc_start & mask; 3029 win[0].win_limit = chainp->wc_end & mask; 3030 win[0].win_flags = chainp->wc_flags; 3031 chainp = TAILQ_NEXT(chainp, wc_list); 3032 } 3033 3034 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3035 if (win[1].win_start == 0xffffffff) { 3036 /* window 1 is not used */ 3037 if ((win[0].win_flags == chainp->wc_flags) && 3038 (win[0].win_limit + align >= 3039 (chainp->wc_start & mask))) { 3040 /* concatenate */ 3041 win[0].win_limit = chainp->wc_end & mask; 3042 } else { 3043 /* make new window */ 3044 win[1].win_start = chainp->wc_start & mask; 3045 win[1].win_limit = chainp->wc_end & mask; 3046 win[1].win_flags = chainp->wc_flags; 3047 } 3048 continue; 3049 } 3050 3051 /* Both windows are engaged. */ 3052 if (win[0].win_flags == win[1].win_flags) { 3053 /* same flags */ 3054 if (win[0].win_flags == chainp->wc_flags) { 3055 if (win[1].win_start - (win[0].win_limit + 3056 align) < 3057 (chainp->wc_start & mask) - 3058 ((chainp->wc_end & mask) + align)) { 3059 /* 3060 * merge window 0 and 1, and set win1 3061 * to chainp 3062 */ 3063 win[0].win_limit = win[1].win_limit; 3064 win[1].win_start = 3065 chainp->wc_start & mask; 3066 win[1].win_limit = 3067 chainp->wc_end & mask; 3068 } else { 3069 win[1].win_limit = 3070 chainp->wc_end & mask; 3071 } 3072 } else { 3073 /* different flags */ 3074 3075 /* concatenate win0 and win1 */ 3076 win[0].win_limit = win[1].win_limit; 3077 /* allocate win[1] to new space */ 3078 win[1].win_start = chainp->wc_start & mask; 3079 win[1].win_limit = chainp->wc_end & mask; 3080 win[1].win_flags = chainp->wc_flags; 3081 } 3082 } else { 3083 /* the flags of win[0] and win[1] is different */ 3084 if (win[0].win_flags == chainp->wc_flags) { 3085 win[0].win_limit = chainp->wc_end & mask; 3086 /* 3087 * XXX this creates overlapping windows, so 3088 * what should the poor bridge do if one is 3089 * cachable, and the other is not? 3090 */ 3091 printf("%s: overlapping windows\n", 3092 sc->sc_dev.dv_xname); 3093 } else { 3094 win[1].win_limit = chainp->wc_end & mask; 3095 } 3096 } 3097 } 3098 3099 pc = sc->sc_pc; 3100 tag = sc->sc_tag; 3101 pci_conf_write(pc, tag, offs, win[0].win_start); 3102 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3103 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3104 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3105 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3106 pci_conf_read(pc, tag, offs), 3107 pci_conf_read(pc, tag, offs + 4) + align, 3108 pci_conf_read(pc, tag, offs + 8), 3109 pci_conf_read(pc, tag, offs + 12) + align)); 3110 3111 if (bst == sc->sc_memt) { 3112 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3113 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3114 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3115 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3116 } 3117 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3118 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3119 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3120 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3121 } 3122 } 3123 } 3124 3125 #endif /* rbus */ 3126 3127 static void 3128 pccbb_powerhook(why, arg) 3129 int why; 3130 void *arg; 3131 { 3132 struct pccbb_softc *sc = arg; 3133 u_int32_t reg; 3134 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3135 bus_space_handle_t base_memh = sc->sc_base_memh; 3136 3137 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3138 3139 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3140 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3141 if (sc->sc_pil_intr_enable) { 3142 (void)pccbbintr_function(sc); 3143 } 3144 sc->sc_pil_intr_enable = 0; 3145 3146 /* ToDo: deactivate or suspend child devices */ 3147 3148 } 3149 3150 if (why == PWR_RESUME) { 3151 /* CSC Interrupt: Card detect interrupt on */ 3152 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3153 /* Card detect intr is turned on. */ 3154 reg |= CB_SOCKET_MASK_CD; 3155 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3156 /* reset interrupt */ 3157 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3158 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3159 3160 /* 3161 * check for card insertion or removal during suspend period. 3162 * XXX: the code can't cope with card swap (remove then 3163 * insert). how can we detect such situation? 3164 */ 3165 (void)pccbbintr(sc); 3166 3167 sc->sc_pil_intr_enable = 1; 3168 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3169 3170 /* ToDo: activate or wakeup child devices */ 3171 } 3172 } 3173
Indexes created Fri Sep 26 08:10:20 GMT 2025