pccbb.c revision 1.46
1 /* $NetBSD: pccbb.c,v 1.46 2000/10/25 09:15:58 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 93 void pccbbattach __P((struct device *, struct device *, void *)); 94 int pccbbintr __P((void *)); 95 static void pci113x_insert __P((void *)); 96 static int pccbbintr_function __P((struct pccbb_softc *)); 97 98 static int pccbb_detect_card __P((struct pccbb_softc *)); 99 100 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 101 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 102 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 103 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 104 105 STATIC int cb_reset __P((struct pccbb_softc *)); 106 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 107 STATIC int cbbprint __P((void *, const char *)); 108 109 static int cb_chipset __P((u_int32_t, int *)); 110 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 111 struct pcmciabus_attach_args *)); 112 #if 0 113 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 114 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 115 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 116 #endif 117 118 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 119 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 120 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 121 #if !rbus 122 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 123 u_int32_t)); 124 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 125 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 126 u_int32_t)); 127 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 128 #endif /* !rbus */ 129 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 130 int level, int (*ih) (void *), void *sc)); 131 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 132 133 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 static void pccbb_powerhook __P((int, void *)); 171 172 /* bus-space allocation and deallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 178 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t)); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 187 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t)); 189 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int)); 191 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 192 bus_space_handle_t, bus_size_t)); 193 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t)); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback __P((struct device *)); 201 202 #if defined SHOW_REGS 203 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 204 bus_space_tag_t memt, bus_space_handle_t memh)); 205 #endif 206 207 struct cfattach cbb_pci_ca = { 208 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 209 }; 210 211 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 212 pccbb_pcmcia_mem_alloc, 213 pccbb_pcmcia_mem_free, 214 pccbb_pcmcia_mem_map, 215 pccbb_pcmcia_mem_unmap, 216 pccbb_pcmcia_io_alloc, 217 pccbb_pcmcia_io_free, 218 pccbb_pcmcia_io_map, 219 pccbb_pcmcia_io_unmap, 220 pccbb_pcmcia_intr_establish, 221 pccbb_pcmcia_intr_disestablish, 222 pccbb_pcmcia_socket_enable, 223 pccbb_pcmcia_socket_disable, 224 pccbb_pcmcia_card_detect 225 }; 226 227 #if rbus 228 static struct cardbus_functions pccbb_funcs = { 229 pccbb_rbus_cb_space_alloc, 230 pccbb_rbus_cb_space_free, 231 pccbb_cb_intr_establish, 232 pccbb_cb_intr_disestablish, 233 pccbb_ctrl, 234 pccbb_power, 235 pccbb_make_tag, 236 pccbb_free_tag, 237 pccbb_conf_read, 238 pccbb_conf_write, 239 }; 240 #else 241 static struct cardbus_functions pccbb_funcs = { 242 pccbb_ctrl, 243 pccbb_power, 244 pccbb_mem_open, 245 pccbb_mem_close, 246 pccbb_io_open, 247 pccbb_io_close, 248 pccbb_cb_intr_establish, 249 pccbb_cb_intr_disestablish, 250 pccbb_make_tag, 251 pccbb_conf_read, 252 pccbb_conf_write, 253 }; 254 #endif 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 struct cfdata *match; 260 void *aux; 261 { 262 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 263 264 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 265 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 266 PCI_INTERFACE(pa->pa_class) == 0) { 267 return 1; 268 } 269 270 return 0; 271 } 272 273 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 274 | ((prod) << PCI_PRODUCT_SHIFT)) 275 276 struct yenta_chipinfo { 277 pcireg_t yc_id; /* vendor tag | product tag */ 278 int yc_chiptype; 279 int yc_flags; 280 } yc_chipsets[] = { 281 /* Texas Instruments chips */ 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 307 /* Ricoh chips */ 308 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 309 PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 311 PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 313 PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 315 PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 319 PCCBB_PCMCIA_MEM_32}, 320 321 /* Toshiba products */ 322 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 323 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 325 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 327 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 329 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 330 331 /* Cirrus Logic products */ 332 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 333 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 335 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 336 337 /* sentinel, or Generic chip */ 338 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 339 }; 340 341 static int 342 cb_chipset(pci_id, flagp) 343 u_int32_t pci_id; 344 int *flagp; 345 { 346 struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return (yc->yc_chiptype); 358 } 359 360 static void 361 pccbb_shutdown(void *arg) 362 { 363 struct pccbb_softc *sc = arg; 364 pcireg_t command; 365 366 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 367 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 368 0); 369 370 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 371 372 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 373 PCI_COMMAND_MASTER_ENABLE); 374 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 375 376 } 377 378 void 379 pccbbattach(parent, self, aux) 380 struct device *parent; 381 struct device *self; 382 void *aux; 383 { 384 struct pccbb_softc *sc = (void *)self; 385 struct pci_attach_args *pa = aux; 386 pci_chipset_tag_t pc = pa->pa_pc; 387 pcireg_t busreg, reg, sock_base; 388 bus_addr_t sockbase; 389 char devinfo[256]; 390 int flags; 391 392 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 393 394 pci_devinfo(pa->pa_id, 0, 0, devinfo); 395 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 396 #ifdef CBB_DEBUG 397 printf(" (chipflags %x)", flags); 398 #endif 399 printf("\n"); 400 401 TAILQ_INIT(&sc->sc_memwindow); 402 TAILQ_INIT(&sc->sc_iowindow); 403 404 #if rbus 405 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 406 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 407 #endif /* rbus */ 408 409 sc->sc_base_memh = 0; 410 411 /* 412 * MAP socket registers and ExCA registers on memory-space 413 * When no valid address is set on socket base registers (on pci 414 * config space), get it not polite way. 415 */ 416 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 417 418 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 419 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 420 /* The address must be valid. */ 421 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 422 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 423 printf("%s: can't map socket base address 0x%x\n", 424 sc->sc_dev.dv_xname, sock_base); 425 /* 426 * I think it's funny: socket base registers must be 427 * mapped on memory space, but ... 428 */ 429 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 430 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 431 NULL)) { 432 printf("%s: can't map socket base address" 433 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 434 sockbase); 435 /* give up... allocate reg space via rbus. */ 436 sc->sc_base_memh = 0; 437 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 438 } 439 } else { 440 DPRINTF(("%s: socket base address 0x%lx\n", 441 sc->sc_dev.dv_xname, sockbase)); 442 } 443 } 444 445 sc->sc_mem_start = 0; /* XXX */ 446 sc->sc_mem_end = 0xffffffff; /* XXX */ 447 448 /* 449 * When interrupt isn't routed correctly, give up probing cbb and do 450 * not kill pcic-compatible port. 451 */ 452 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 453 printf("%s: NOT USED because of unconfigured interrupt\n", 454 sc->sc_dev.dv_xname); 455 return; 456 } 457 458 /* 459 * When bus number isn't set correctly, give up using 32-bit CardBus 460 * mode. 461 */ 462 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 463 #if notyet 464 if (((busreg >> 8) & 0xff) == 0) { 465 printf("%s: CardBus support disabled because of unconfigured bus number\n", 466 sc->sc_dev.dv_xname); 467 flags |= PCCBB_PCMCIA_16BITONLY; 468 } 469 #endif 470 471 /* pccbb_machdep.c end */ 472 473 #if defined CBB_DEBUG 474 { 475 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 476 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 477 intrname[pa->pa_intrpin], pa->pa_intrline); 478 } 479 #endif 480 481 /* setup softc */ 482 sc->sc_pc = pc; 483 sc->sc_iot = pa->pa_iot; 484 sc->sc_memt = pa->pa_memt; 485 sc->sc_dmat = pa->pa_dmat; 486 sc->sc_tag = pa->pa_tag; 487 sc->sc_function = pa->pa_function; 488 489 sc->sc_intrline = pa->pa_intrline; 490 sc->sc_intrtag = pa->pa_intrtag; 491 sc->sc_intrpin = pa->pa_intrpin; 492 493 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 494 495 shutdownhook_establish(pccbb_shutdown, sc); 496 497 /* Disable legacy register mapping. */ 498 switch (sc->sc_chipset) { 499 case CB_RX5C46X: /* fallthrough */ 500 #if 0 501 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 502 case CB_RX5C47X: 503 #endif 504 /* 505 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 506 * cannot be disabled by substituting 0 into PCI_LEGACY 507 * register. Ricoh CardBus bridges have special bits on Bridge 508 * control reg (addr 0x3e on PCI config space). 509 */ 510 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 511 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 512 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 513 break; 514 515 default: 516 /* XXX I don't know proper way to kill legacy I/O. */ 517 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 518 break; 519 } 520 521 config_defer(self, pccbb_pci_callback); 522 } 523 524 525 526 527 /* 528 * static void pccbb_pci_callback(struct device *self) 529 * 530 * The actual attach routine: get memory space for YENTA register 531 * space, setup YENTA register and route interrupt. 532 * 533 * This function should be deferred because this device may obtain 534 * memory space dynamically. This function must avoid obtaining 535 * memory area which has already kept for another device. 536 */ 537 static void 538 pccbb_pci_callback(self) 539 struct device *self; 540 { 541 struct pccbb_softc *sc = (void *)self; 542 pci_chipset_tag_t pc = sc->sc_pc; 543 bus_space_tag_t base_memt; 544 bus_space_handle_t base_memh; 545 u_int32_t maskreg; 546 pci_intr_handle_t ih; 547 const char *intrstr = NULL; 548 bus_addr_t sockbase; 549 struct cbslot_attach_args cba; 550 struct pcmciabus_attach_args paa; 551 struct cardslot_attach_args caa; 552 struct cardslot_softc *csc; 553 554 if (0 == sc->sc_base_memh) { 555 /* The socket registers aren't mapped correctly. */ 556 #if rbus 557 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 558 (sc->sc_chipset == CB_RX5C47X 559 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 560 0, &sockbase, &sc->sc_base_memh)) { 561 return; 562 } 563 sc->sc_base_memt = sc->sc_memt; 564 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 565 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 566 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 567 PCI_SOCKBASE))); 568 #else 569 sc->sc_base_memt = sc->sc_memt; 570 #if !defined CBB_PCI_BASE 571 #define CBB_PCI_BASE 0x20000000 572 #endif 573 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 574 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 575 /* cannot allocate memory space */ 576 return; 577 } 578 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 579 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 580 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 581 sc->sc_tag, PCI_SOCKBASE))); 582 #endif 583 } 584 585 /* bus bridge initialization */ 586 pccbb_chipinit(sc); 587 588 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 589 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 590 591 /* CSC Interrupt: Card detect interrupt on */ 592 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 593 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 594 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 595 /* reset interrupt */ 596 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 597 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 598 599 /* clear data structure for child device interrupt handlers */ 600 sc->sc_pil = NULL; 601 sc->sc_pil_intr_enable = 1; 602 603 /* Map and establish the interrupt. */ 604 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 605 sc->sc_intrline, &ih)) { 606 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 607 return; 608 } 609 intrstr = pci_intr_string(pc, ih); 610 611 /* 612 * XXX pccbbintr should be called under the priority lower 613 * than any other hard interrputs. 614 */ 615 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 616 617 if (sc->sc_ih == NULL) { 618 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 619 if (intrstr != NULL) { 620 printf(" at %s", intrstr); 621 } 622 printf("\n"); 623 return; 624 } 625 626 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 627 powerhook_establish(pccbb_powerhook, sc); 628 629 { 630 u_int32_t sockstat = 631 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 632 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 633 sc->sc_flags |= CBB_CARDEXIST; 634 } 635 } 636 637 /* 638 * attach cardbus 639 */ 640 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 641 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 642 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 643 644 /* initialize cbslot_attach */ 645 cba.cba_busname = "cardbus"; 646 cba.cba_iot = sc->sc_iot; 647 cba.cba_memt = sc->sc_memt; 648 cba.cba_dmat = sc->sc_dmat; 649 cba.cba_bus = (busreg >> 8) & 0x0ff; 650 cba.cba_cc = (void *)sc; 651 cba.cba_cf = &pccbb_funcs; 652 cba.cba_intrline = sc->sc_intrline; 653 654 #if rbus 655 cba.cba_rbus_iot = sc->sc_rbus_iot; 656 cba.cba_rbus_memt = sc->sc_rbus_memt; 657 #endif 658 659 cba.cba_cacheline = PCI_CACHELINE(bhlc); 660 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 661 662 printf("%s: cacheline 0x%x lattimer 0x%x\n", 663 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 664 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 665 busreg); 666 #if defined SHOW_REGS 667 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 668 sc->sc_base_memh); 669 #endif 670 } 671 672 pccbb_pcmcia_attach_setup(sc, &paa); 673 caa.caa_cb_attach = NULL; 674 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 675 caa.caa_cb_attach = &cba; 676 } 677 caa.caa_16_attach = &paa; 678 caa.caa_ph = &sc->sc_pcmcia_h; 679 680 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 681 DPRINTF(("pccbbattach: found cardslot\n")); 682 sc->sc_csc = csc; 683 } 684 685 return; 686 } 687 688 689 690 691 692 /* 693 * static void pccbb_chipinit(struct pccbb_softc *sc) 694 * 695 * This function initialize YENTA chip registers listed below: 696 * 1) PCI command reg, 697 * 2) PCI and CardBus latency timer, 698 * 3) route PCI interrupt, 699 * 4) close all memory and io windows. 700 */ 701 static void 702 pccbb_chipinit(sc) 703 struct pccbb_softc *sc; 704 { 705 pci_chipset_tag_t pc = sc->sc_pc; 706 pcitag_t tag = sc->sc_tag; 707 pcireg_t reg; 708 709 /* 710 * Set PCI command reg. 711 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 712 */ 713 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 714 /* I believe it is harmless. */ 715 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 716 PCI_COMMAND_MASTER_ENABLE); 717 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 718 719 /* 720 * Set CardBus latency timer. 721 */ 722 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 723 if (PCI_CB_LATENCY(reg) < 0x20) { 724 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 725 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 726 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 727 } 728 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 729 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 730 731 /* 732 * Set PCI latency timer. 733 */ 734 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 735 if (PCI_LATTIMER(reg) < 0x10) { 736 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 737 reg |= (0x10 << PCI_LATTIMER_SHIFT); 738 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 739 } 740 DPRINTF(("PCI latency timer 0x%x (%x)\n", 741 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 742 743 744 /* Route functional interrupts to PCI. */ 745 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 746 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 747 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 748 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 749 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 750 751 switch (sc->sc_chipset) { 752 case CB_TI113X: 753 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 754 /* This bit is shared, but may read as 0 on some chips, so set 755 it explicitly on both functions. */ 756 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 757 /* CSC intr enable */ 758 reg |= PCI113X_CBCTRL_PCI_CSC; 759 /* functional intr prohibit | prohibit ISA routing */ 760 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 761 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 762 break; 763 764 case CB_TOPIC95B: 765 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 766 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 767 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 768 769 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 770 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 771 sc->sc_dev.dv_xname, reg)); 772 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 773 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 774 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 775 DPRINTF(("0x%x\n", reg)); 776 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 777 break; 778 } 779 780 /* Close all memory and I/O windows. */ 781 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 782 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 783 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 784 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 785 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 786 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 787 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 788 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 789 790 /* reset 16-bit pcmcia bus */ 791 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 792 0x800 + PCIC_INTR, 793 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 794 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 795 796 /* turn of power */ 797 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 798 } 799 800 801 802 803 /* 804 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 805 * struct pcmciabus_attach_args *paa) 806 * 807 * This function attaches 16-bit PCcard bus. 808 */ 809 STATIC void 810 pccbb_pcmcia_attach_setup(sc, paa) 811 struct pccbb_softc *sc; 812 struct pcmciabus_attach_args *paa; 813 { 814 struct pcic_handle *ph = &sc->sc_pcmcia_h; 815 #if rbus 816 rbus_tag_t rb; 817 #endif 818 819 /* initialize pcmcia part in pccbb_softc */ 820 ph->ph_parent = (struct device *)sc; 821 ph->sock = sc->sc_function; 822 ph->flags = 0; 823 ph->shutdown = 0; 824 ph->ih_irq = sc->sc_intrline; 825 ph->ph_bus_t = sc->sc_base_memt; 826 ph->ph_bus_h = sc->sc_base_memh; 827 ph->ph_read = pccbb_pcmcia_read; 828 ph->ph_write = pccbb_pcmcia_write; 829 sc->sc_pct = &pccbb_pcmcia_funcs; 830 831 /* 832 * We need to do a few things here: 833 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 834 * setting the IRQ numbers to 0. 835 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 836 * routing of CSC interrupts (e.g. card removal) to PCI while in 837 * PCMCIA mode. We just leave this set all the time. 838 * 3) Enable card insertion/removal interrupts in case the chip also 839 * needs that while in PCMCIA mode. 840 * 4) Clear any pending CSC interrupt. 841 */ 842 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 843 if (sc->sc_chipset == CB_TI113X) { 844 Pcic_write(ph, PCIC_CSC_INTR, 0); 845 } else { 846 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 847 Pcic_read(ph, PCIC_CSC); 848 } 849 850 /* initialize pcmcia bus attachment */ 851 paa->paa_busname = "pcmcia"; 852 paa->pct = sc->sc_pct; 853 paa->pch = ph; 854 paa->iobase = 0; /* I don't use them */ 855 paa->iosize = 0; 856 #if rbus 857 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 858 paa->iobase = rb->rb_start + rb->rb_offset; 859 paa->iosize = rb->rb_end - rb->rb_start; 860 #endif 861 862 return; 863 } 864 865 #if 0 866 STATIC void 867 pccbb_pcmcia_attach_card(ph) 868 struct pcic_handle *ph; 869 { 870 if (ph->flags & PCIC_FLAG_CARDP) { 871 panic("pccbb_pcmcia_attach_card: already attached"); 872 } 873 874 /* call the MI attach function */ 875 pcmcia_card_attach(ph->pcmcia); 876 877 ph->flags |= PCIC_FLAG_CARDP; 878 } 879 880 STATIC void 881 pccbb_pcmcia_detach_card(ph, flags) 882 struct pcic_handle *ph; 883 int flags; 884 { 885 if (!(ph->flags & PCIC_FLAG_CARDP)) { 886 panic("pccbb_pcmcia_detach_card: already detached"); 887 } 888 889 ph->flags &= ~PCIC_FLAG_CARDP; 890 891 /* call the MI detach function */ 892 pcmcia_card_detach(ph->pcmcia, flags); 893 } 894 #endif 895 896 /* 897 * int pccbbintr(arg) 898 * void *arg; 899 * This routine handles the interrupt from Yenta PCI-CardBus bridge 900 * itself. 901 */ 902 int 903 pccbbintr(arg) 904 void *arg; 905 { 906 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 907 u_int32_t sockevent, sockstate; 908 bus_space_tag_t memt = sc->sc_base_memt; 909 bus_space_handle_t memh = sc->sc_base_memh; 910 struct pcic_handle *ph = &sc->sc_pcmcia_h; 911 912 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 913 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 914 Pcic_read(ph, PCIC_CSC); 915 916 if (sockevent == 0) { 917 /* This intr is not for me: it may be for my child devices. */ 918 if (sc->sc_pil_intr_enable) { 919 return pccbbintr_function(sc); 920 } else { 921 return 0; 922 } 923 } 924 925 if (sockevent & CB_SOCKET_EVENT_CD) { 926 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 927 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 928 /* A card should be removed. */ 929 if (sc->sc_flags & CBB_CARDEXIST) { 930 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 931 sockevent)); 932 DPRINTF((" card removed, 0x%08x\n", sockstate)); 933 sc->sc_flags &= ~CBB_CARDEXIST; 934 if (sc->sc_csc->sc_status & 935 CARDSLOT_STATUS_CARD_16) { 936 #if 0 937 struct pcic_handle *ph = 938 &sc->sc_pcmcia_h; 939 940 pcmcia_card_deactivate(ph->pcmcia); 941 pccbb_pcmcia_socket_disable(ph); 942 pccbb_pcmcia_detach_card(ph, 943 DETACH_FORCE); 944 #endif 945 cardslot_event_throw(sc->sc_csc, 946 CARDSLOT_EVENT_REMOVAL_16); 947 } else if (sc->sc_csc->sc_status & 948 CARDSLOT_STATUS_CARD_CB) { 949 /* Cardbus intr removed */ 950 cardslot_event_throw(sc->sc_csc, 951 CARDSLOT_EVENT_REMOVAL_CB); 952 } 953 } 954 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 955 /* 956 * The pccbbintr may called from powerdown hook when 957 * the system resumed, to detect the card 958 * insertion/removal during suspension. 959 */ 960 (sc->sc_flags & CBB_CARDEXIST) == 0) { 961 if (sc->sc_flags & CBB_INSERTING) { 962 callout_stop(&sc->sc_insert_ch); 963 } 964 callout_reset(&sc->sc_insert_ch, hz / 10, 965 pci113x_insert, sc); 966 sc->sc_flags |= CBB_INSERTING; 967 } 968 } 969 970 return (1); 971 } 972 973 /* 974 * static int pccbbintr_function(struct pccbb_softc *sc) 975 * 976 * This function calls each interrupt handler registered at the 977 * bridge. The interrupt handlers are called in registered order. 978 */ 979 static int 980 pccbbintr_function(sc) 981 struct pccbb_softc *sc; 982 { 983 int retval = 0, val; 984 struct pccbb_intrhand_list *pil; 985 int s, splchanged; 986 987 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 988 /* 989 * XXX priority change. gross. I use if-else 990 * sentense instead of switch-case sentense because of 991 * avoiding duplicate case value error. More than one 992 * IPL_XXX use same value. It depends on 993 * implimentation. 994 */ 995 splchanged = 1; 996 if (pil->pil_level == IPL_SERIAL) { 997 s = splserial(); 998 } else if (pil->pil_level == IPL_HIGH) { 999 s = splhigh(); 1000 } else if (pil->pil_level == IPL_CLOCK) { 1001 s = splclock(); 1002 } else if (pil->pil_level == IPL_AUDIO) { 1003 s = splaudio(); 1004 } else if (pil->pil_level == IPL_IMP) { 1005 s = splimp(); 1006 } else if (pil->pil_level == IPL_TTY) { 1007 s = spltty(); 1008 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1009 s = splsoftserial(); 1010 } else if (pil->pil_level == IPL_NET) { 1011 s = splnet(); 1012 } else { 1013 splchanged = 0; 1014 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1015 } 1016 1017 val = (*pil->pil_func)(pil->pil_arg); 1018 1019 if (splchanged != 0) { 1020 splx(s); 1021 } 1022 1023 retval = retval == 1 ? 1 : 1024 retval == 0 ? val : val != 0 ? val : retval; 1025 } 1026 1027 return retval; 1028 } 1029 1030 static void 1031 pci113x_insert(arg) 1032 void *arg; 1033 { 1034 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1035 u_int32_t sockevent, sockstate; 1036 1037 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1038 CB_SOCKET_EVENT); 1039 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1040 CB_SOCKET_STAT); 1041 1042 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1043 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1044 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1045 sc->sc_flags |= CBB_CARDEXIST; 1046 /* call pccard interrupt handler here */ 1047 if (sockstate & CB_SOCKET_STAT_16BIT) { 1048 /* 16-bit card found */ 1049 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1050 cardslot_event_throw(sc->sc_csc, 1051 CARDSLOT_EVENT_INSERTION_16); 1052 } else if (sockstate & CB_SOCKET_STAT_CB) { 1053 /* cardbus card found */ 1054 /* cardbus_attach_card(sc->sc_csc); */ 1055 cardslot_event_throw(sc->sc_csc, 1056 CARDSLOT_EVENT_INSERTION_CB); 1057 } else { 1058 /* who are you? */ 1059 } 1060 } else { 1061 callout_reset(&sc->sc_insert_ch, hz / 10, 1062 pci113x_insert, sc); 1063 } 1064 } 1065 1066 #define PCCBB_PCMCIA_OFFSET 0x800 1067 static u_int8_t 1068 pccbb_pcmcia_read(ph, reg) 1069 struct pcic_handle *ph; 1070 int reg; 1071 { 1072 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1073 PCCBB_PCMCIA_OFFSET + reg); 1074 } 1075 1076 static void 1077 pccbb_pcmcia_write(ph, reg, val) 1078 struct pcic_handle *ph; 1079 int reg; 1080 u_int8_t val; 1081 { 1082 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1083 val); 1084 } 1085 1086 /* 1087 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1088 */ 1089 STATIC int 1090 pccbb_ctrl(ct, command) 1091 cardbus_chipset_tag_t ct; 1092 int command; 1093 { 1094 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1095 1096 switch (command) { 1097 case CARDBUS_CD: 1098 if (2 == pccbb_detect_card(sc)) { 1099 int retval = 0; 1100 int status = cb_detect_voltage(sc); 1101 if (PCCARD_VCC_5V & status) { 1102 retval |= CARDBUS_5V_CARD; 1103 } 1104 if (PCCARD_VCC_3V & status) { 1105 retval |= CARDBUS_3V_CARD; 1106 } 1107 if (PCCARD_VCC_XV & status) { 1108 retval |= CARDBUS_XV_CARD; 1109 } 1110 if (PCCARD_VCC_YV & status) { 1111 retval |= CARDBUS_YV_CARD; 1112 } 1113 return retval; 1114 } else { 1115 return 0; 1116 } 1117 break; 1118 case CARDBUS_RESET: 1119 return cb_reset(sc); 1120 break; 1121 case CARDBUS_IO_ENABLE: /* fallthrough */ 1122 case CARDBUS_IO_DISABLE: /* fallthrough */ 1123 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1124 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1125 case CARDBUS_BM_ENABLE: /* fallthrough */ 1126 case CARDBUS_BM_DISABLE: /* fallthrough */ 1127 return pccbb_cardenable(sc, command); 1128 break; 1129 } 1130 1131 return 0; 1132 } 1133 1134 /* 1135 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1136 * This function returns true when it succeeds and returns false when 1137 * it fails. 1138 */ 1139 STATIC int 1140 pccbb_power(ct, command) 1141 cardbus_chipset_tag_t ct; 1142 int command; 1143 { 1144 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1145 1146 u_int32_t status, sock_ctrl; 1147 bus_space_tag_t memt = sc->sc_base_memt; 1148 bus_space_handle_t memh = sc->sc_base_memh; 1149 1150 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1151 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1152 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1153 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1154 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1155 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1156 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1157 "UNKNOWN", 1158 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1159 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1160 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1161 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1162 "UNKNOWN", command)); 1163 1164 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1165 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1166 1167 switch (command & CARDBUS_VCCMASK) { 1168 case CARDBUS_VCC_UC: 1169 break; 1170 case CARDBUS_VCC_5V: 1171 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1172 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1173 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1174 } else { 1175 printf("%s: BAD voltage request: no 5 V card\n", 1176 sc->sc_dev.dv_xname); 1177 } 1178 break; 1179 case CARDBUS_VCC_3V: 1180 if (CB_SOCKET_STAT_3VCARD & status) { 1181 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1182 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1183 } else { 1184 printf("%s: BAD voltage request: no 3.3 V card\n", 1185 sc->sc_dev.dv_xname); 1186 } 1187 break; 1188 case CARDBUS_VCC_0V: 1189 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1190 break; 1191 default: 1192 return 0; /* power NEVER changed */ 1193 break; 1194 } 1195 1196 switch (command & CARDBUS_VPPMASK) { 1197 case CARDBUS_VPP_UC: 1198 break; 1199 case CARDBUS_VPP_0V: 1200 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1201 break; 1202 case CARDBUS_VPP_VCC: 1203 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1204 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1205 break; 1206 case CARDBUS_VPP_12V: 1207 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1208 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1209 break; 1210 } 1211 1212 #if 0 1213 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1214 #endif 1215 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1216 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1217 1218 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1219 /* 1220 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1221 * time is 20 ms, some PC-Card bridge requires longer duration. 1222 */ 1223 delay(200 * 1000); 1224 1225 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1226 printf 1227 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1228 sc->sc_dev.dv_xname, sock_ctrl, status); 1229 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1230 (command & CARDBUS_VCCMASK) == 1231 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1232 CARDBUS_VCCMASK) == 1233 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1234 CARDBUS_VCCMASK) == 1235 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1236 CARDBUS_VCCMASK) == 1237 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1238 CARDBUS_VCCMASK) == 1239 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1240 CARDBUS_VCCMASK) == 1241 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1242 (command & CARDBUS_VPPMASK) == 1243 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1244 CARDBUS_VPPMASK) == 1245 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1246 CARDBUS_VPPMASK) == 1247 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1248 CARDBUS_VPPMASK) == 1249 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1250 #if 0 1251 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1252 u_int32_t force = 1253 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1254 /* Reset Bad Vcc request */ 1255 force &= ~CB_SOCKET_FORCE_BADVCC; 1256 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1257 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1258 CB_SOCKET_STAT)); 1259 return 1; 1260 } 1261 #endif 1262 return 0; 1263 } 1264 return 1; /* power changed correctly */ 1265 } 1266 1267 #if defined CB_PCMCIA_POLL 1268 struct cb_poll_str { 1269 void *arg; 1270 int (*func) __P((void *)); 1271 int level; 1272 pccard_chipset_tag_t ct; 1273 int count; 1274 struct callout poll_ch; 1275 }; 1276 1277 static struct cb_poll_str cb_poll[10]; 1278 static int cb_poll_n = 0; 1279 1280 static void cb_pcmcia_poll __P((void *arg)); 1281 1282 static void 1283 cb_pcmcia_poll(arg) 1284 void *arg; 1285 { 1286 struct cb_poll_str *poll = arg; 1287 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1288 struct pccbb_softc *sc = psc->cpc_parent; 1289 int s; 1290 u_int32_t spsr; /* socket present-state reg */ 1291 1292 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1293 switch (poll->level) { 1294 case IPL_NET: 1295 s = splnet(); 1296 break; 1297 case IPL_BIO: 1298 s = splbio(); 1299 break; 1300 case IPL_TTY: /* fallthrough */ 1301 default: 1302 s = spltty(); 1303 break; 1304 } 1305 1306 spsr = 1307 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1308 CB_SOCKET_STAT); 1309 1310 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1311 if (!(spsr & 0x40)) { /* CINT low */ 1312 #else 1313 if (1) { 1314 #endif 1315 if ((*poll->func) (poll->arg) == 1) { 1316 ++poll->count; 1317 printf("intr: reported from poller, 0x%x\n", spsr); 1318 #if defined LEVEL2 1319 } else { 1320 printf("intr: miss! 0x%x\n", spsr); 1321 #endif 1322 } 1323 } 1324 splx(s); 1325 } 1326 #endif /* defined CB_PCMCIA_POLL */ 1327 1328 /* 1329 * static int pccbb_detect_card(struct pccbb_softc *sc) 1330 * return value: 0 if no card exists. 1331 * 1 if 16-bit card exists. 1332 * 2 if cardbus card exists. 1333 */ 1334 static int 1335 pccbb_detect_card(sc) 1336 struct pccbb_softc *sc; 1337 { 1338 bus_space_handle_t base_memh = sc->sc_base_memh; 1339 bus_space_tag_t base_memt = sc->sc_base_memt; 1340 u_int32_t sockstat = 1341 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1342 int retval = 0; 1343 1344 /* CD1 and CD2 asserted */ 1345 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1346 /* card must be present */ 1347 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1348 /* NOTACARD DEASSERTED */ 1349 if (CB_SOCKET_STAT_CB & sockstat) { 1350 /* CardBus mode */ 1351 retval = 2; 1352 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1353 /* 16-bit mode */ 1354 retval = 1; 1355 } 1356 } 1357 } 1358 return retval; 1359 } 1360 1361 /* 1362 * STATIC int cb_reset(struct pccbb_softc *sc) 1363 * This function resets CardBus card. 1364 */ 1365 STATIC int 1366 cb_reset(sc) 1367 struct pccbb_softc *sc; 1368 { 1369 /* 1370 * Reset Assert at least 20 ms 1371 * Some machines request longer duration. 1372 */ 1373 int reset_duration = 1374 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1375 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1376 1377 /* Reset bit Assert (bit 6 at 0x3E) */ 1378 bcr |= CB_BCR_RESET_ENABLE; 1379 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1380 delay(reset_duration); 1381 1382 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1383 /* Reset bit Deassert (bit 6 at 0x3E) */ 1384 bcr &= ~CB_BCR_RESET_ENABLE; 1385 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1386 delay(reset_duration); 1387 } 1388 /* No card found on the slot. Keep Reset. */ 1389 return 1; 1390 } 1391 1392 /* 1393 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1394 * This function detect card Voltage. 1395 */ 1396 STATIC int 1397 cb_detect_voltage(sc) 1398 struct pccbb_softc *sc; 1399 { 1400 u_int32_t psr; /* socket present-state reg */ 1401 bus_space_tag_t iot = sc->sc_base_memt; 1402 bus_space_handle_t ioh = sc->sc_base_memh; 1403 int vol = PCCARD_VCC_UKN; /* set 0 */ 1404 1405 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1406 1407 if (0x400u & psr) { 1408 vol |= PCCARD_VCC_5V; 1409 } 1410 if (0x800u & psr) { 1411 vol |= PCCARD_VCC_3V; 1412 } 1413 1414 return vol; 1415 } 1416 1417 STATIC int 1418 cbbprint(aux, pcic) 1419 void *aux; 1420 const char *pcic; 1421 { 1422 /* 1423 struct cbslot_attach_args *cba = aux; 1424 1425 if (cba->cba_slot >= 0) { 1426 printf(" slot %d", cba->cba_slot); 1427 } 1428 */ 1429 return UNCONF; 1430 } 1431 1432 /* 1433 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1434 * This function enables and disables the card 1435 */ 1436 STATIC int 1437 pccbb_cardenable(sc, function) 1438 struct pccbb_softc *sc; 1439 int function; 1440 { 1441 u_int32_t command = 1442 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1443 1444 DPRINTF(("pccbb_cardenable:")); 1445 switch (function) { 1446 case CARDBUS_IO_ENABLE: 1447 command |= PCI_COMMAND_IO_ENABLE; 1448 break; 1449 case CARDBUS_IO_DISABLE: 1450 command &= ~PCI_COMMAND_IO_ENABLE; 1451 break; 1452 case CARDBUS_MEM_ENABLE: 1453 command |= PCI_COMMAND_MEM_ENABLE; 1454 break; 1455 case CARDBUS_MEM_DISABLE: 1456 command &= ~PCI_COMMAND_MEM_ENABLE; 1457 break; 1458 case CARDBUS_BM_ENABLE: 1459 command |= PCI_COMMAND_MASTER_ENABLE; 1460 break; 1461 case CARDBUS_BM_DISABLE: 1462 command &= ~PCI_COMMAND_MASTER_ENABLE; 1463 break; 1464 default: 1465 return 0; 1466 } 1467 1468 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1469 DPRINTF((" command reg 0x%x\n", command)); 1470 return 1; 1471 } 1472 1473 #if !rbus 1474 /* 1475 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1476 */ 1477 static int 1478 pccbb_io_open(ct, win, start, end) 1479 cardbus_chipset_tag_t ct; 1480 int win; 1481 u_int32_t start, end; 1482 { 1483 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1484 int basereg; 1485 int limitreg; 1486 1487 if ((win < 0) || (win > 2)) { 1488 #if defined DIAGNOSTIC 1489 printf("cardbus_io_open: window out of range %d\n", win); 1490 #endif 1491 return 0; 1492 } 1493 1494 basereg = win * 8 + 0x2c; 1495 limitreg = win * 8 + 0x30; 1496 1497 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1498 start, basereg, end, limitreg)); 1499 1500 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1501 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1502 return 1; 1503 } 1504 1505 /* 1506 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1507 */ 1508 static int 1509 pccbb_io_close(ct, win) 1510 cardbus_chipset_tag_t ct; 1511 int win; 1512 { 1513 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1514 int basereg; 1515 int limitreg; 1516 1517 if ((win < 0) || (win > 2)) { 1518 #if defined DIAGNOSTIC 1519 printf("cardbus_io_close: window out of range %d\n", win); 1520 #endif 1521 return 0; 1522 } 1523 1524 basereg = win * 8 + 0x2c; 1525 limitreg = win * 8 + 0x30; 1526 1527 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1528 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1529 return 1; 1530 } 1531 1532 /* 1533 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1534 */ 1535 static int 1536 pccbb_mem_open(ct, win, start, end) 1537 cardbus_chipset_tag_t ct; 1538 int win; 1539 u_int32_t start, end; 1540 { 1541 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1542 int basereg; 1543 int limitreg; 1544 1545 if ((win < 0) || (win > 2)) { 1546 #if defined DIAGNOSTIC 1547 printf("cardbus_mem_open: window out of range %d\n", win); 1548 #endif 1549 return 0; 1550 } 1551 1552 basereg = win * 8 + 0x1c; 1553 limitreg = win * 8 + 0x20; 1554 1555 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1556 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1557 return 1; 1558 } 1559 1560 /* 1561 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1562 */ 1563 static int 1564 pccbb_mem_close(ct, win) 1565 cardbus_chipset_tag_t ct; 1566 int win; 1567 { 1568 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1569 int basereg; 1570 int limitreg; 1571 1572 if ((win < 0) || (win > 2)) { 1573 #if defined DIAGNOSTIC 1574 printf("cardbus_mem_close: window out of range %d\n", win); 1575 #endif 1576 return 0; 1577 } 1578 1579 basereg = win * 8 + 0x1c; 1580 limitreg = win * 8 + 0x20; 1581 1582 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1583 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1584 return 1; 1585 } 1586 #endif 1587 1588 /* 1589 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1590 * int irq, 1591 * int level, 1592 * int (* func) __P((void *)), 1593 * void *arg) 1594 * 1595 * This function registers an interrupt handler at the bridge, in 1596 * order not to call the interrupt handlers of child devices when 1597 * a card-deletion interrupt occurs. 1598 * 1599 * The arguments irq and level are not used. 1600 */ 1601 static void * 1602 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1603 cardbus_chipset_tag_t ct; 1604 int irq, level; 1605 int (*func) __P((void *)); 1606 void *arg; 1607 { 1608 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1609 1610 return pccbb_intr_establish(sc, irq, level, func, arg); 1611 } 1612 1613 1614 /* 1615 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1616 * void *ih) 1617 * 1618 * This function removes an interrupt handler pointed by ih. 1619 */ 1620 static void 1621 pccbb_cb_intr_disestablish(ct, ih) 1622 cardbus_chipset_tag_t ct; 1623 void *ih; 1624 { 1625 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1626 1627 pccbb_intr_disestablish(sc, ih); 1628 } 1629 1630 1631 /* 1632 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1633 * int irq, 1634 * int level, 1635 * int (* func) __P((void *)), 1636 * void *arg) 1637 * 1638 * This function registers an interrupt handler at the bridge, in 1639 * order not to call the interrupt handlers of child devices when 1640 * a card-deletion interrupt occurs. 1641 * 1642 * The arguments irq is not used because pccbb selects intr vector. 1643 */ 1644 static void * 1645 pccbb_intr_establish(sc, irq, level, func, arg) 1646 struct pccbb_softc *sc; 1647 int irq, level; 1648 int (*func) __P((void *)); 1649 void *arg; 1650 { 1651 struct pccbb_intrhand_list *pil, *newpil; 1652 1653 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1654 1655 if (sc->sc_pil == NULL) { 1656 /* initialize bridge intr routing */ 1657 1658 switch (sc->sc_chipset) { 1659 case CB_TI113X: 1660 { 1661 pcireg_t cbctrl = 1662 pci_conf_read(sc->sc_pc, sc->sc_tag, 1663 PCI_CBCTRL); 1664 /* functional intr enabled */ 1665 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1666 pci_conf_write(sc->sc_pc, sc->sc_tag, 1667 PCI_CBCTRL, cbctrl); 1668 break; 1669 } 1670 default: 1671 break; 1672 } 1673 } 1674 1675 /* 1676 * Allocate a room for interrupt handler structure. 1677 */ 1678 if (NULL == (newpil = 1679 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1680 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1681 return NULL; 1682 } 1683 1684 newpil->pil_func = func; 1685 newpil->pil_arg = arg; 1686 newpil->pil_level = level; 1687 newpil->pil_next = NULL; 1688 1689 if (sc->sc_pil == NULL) { 1690 sc->sc_pil = newpil; 1691 } else { 1692 for (pil = sc->sc_pil; pil->pil_next != NULL; 1693 pil = pil->pil_next); 1694 pil->pil_next = newpil; 1695 } 1696 1697 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1698 1699 return newpil; 1700 } 1701 1702 /* 1703 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1704 * void *ih) 1705 * 1706 * This function removes an interrupt handler pointed by ih. 1707 */ 1708 static void 1709 pccbb_intr_disestablish(sc, ih) 1710 struct pccbb_softc *sc; 1711 void *ih; 1712 { 1713 struct pccbb_intrhand_list *pil, **pil_prev; 1714 1715 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1716 1717 pil_prev = &sc->sc_pil; 1718 1719 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1720 if (pil == ih) { 1721 *pil_prev = pil->pil_next; 1722 free(pil, M_DEVBUF); 1723 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1724 break; 1725 } 1726 pil_prev = &pil->pil_next; 1727 } 1728 1729 if (sc->sc_pil == NULL) { 1730 /* No interrupt handlers */ 1731 1732 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1733 1734 switch (sc->sc_chipset) { 1735 case CB_TI113X: 1736 { 1737 pcireg_t cbctrl = 1738 pci_conf_read(sc->sc_pc, sc->sc_tag, 1739 PCI_CBCTRL); 1740 /* functional intr disabled */ 1741 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1742 pci_conf_write(sc->sc_pc, sc->sc_tag, 1743 PCI_CBCTRL, cbctrl); 1744 break; 1745 } 1746 default: 1747 break; 1748 } 1749 } 1750 } 1751 1752 #if defined SHOW_REGS 1753 static void 1754 cb_show_regs(pc, tag, memt, memh) 1755 pci_chipset_tag_t pc; 1756 pcitag_t tag; 1757 bus_space_tag_t memt; 1758 bus_space_handle_t memh; 1759 { 1760 int i; 1761 printf("PCI config regs:"); 1762 for (i = 0; i < 0x50; i += 4) { 1763 if (i % 16 == 0) { 1764 printf("\n 0x%02x:", i); 1765 } 1766 printf(" %08x", pci_conf_read(pc, tag, i)); 1767 } 1768 for (i = 0x80; i < 0xb0; i += 4) { 1769 if (i % 16 == 0) { 1770 printf("\n 0x%02x:", i); 1771 } 1772 printf(" %08x", pci_conf_read(pc, tag, i)); 1773 } 1774 1775 if (memh == 0) { 1776 printf("\n"); 1777 return; 1778 } 1779 1780 printf("\nsocket regs:"); 1781 for (i = 0; i <= 0x10; i += 0x04) { 1782 printf(" %08x", bus_space_read_4(memt, memh, i)); 1783 } 1784 printf("\nExCA regs:"); 1785 for (i = 0; i < 0x08; ++i) { 1786 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1787 } 1788 printf("\n"); 1789 return; 1790 } 1791 #endif 1792 1793 /* 1794 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1795 * int busno, int devno, int function) 1796 * This is the function to make a tag to access config space of 1797 * a CardBus Card. It works same as pci_conf_read. 1798 */ 1799 static cardbustag_t 1800 pccbb_make_tag(cc, busno, devno, function) 1801 cardbus_chipset_tag_t cc; 1802 int busno, devno, function; 1803 { 1804 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1805 1806 return pci_make_tag(sc->sc_pc, busno, devno, function); 1807 } 1808 1809 static void 1810 pccbb_free_tag(cc, tag) 1811 cardbus_chipset_tag_t cc; 1812 cardbustag_t tag; 1813 { 1814 } 1815 1816 /* 1817 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1818 * cardbustag_t tag, int offset) 1819 * This is the function to read the config space of a CardBus Card. 1820 * It works same as pci_conf_read. 1821 */ 1822 static cardbusreg_t 1823 pccbb_conf_read(cc, tag, offset) 1824 cardbus_chipset_tag_t cc; 1825 cardbustag_t tag; 1826 int offset; /* register offset */ 1827 { 1828 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1829 1830 return pci_conf_read(sc->sc_pc, tag, offset); 1831 } 1832 1833 /* 1834 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1835 * int offs, cardbusreg_t val) 1836 * This is the function to write the config space of a CardBus Card. 1837 * It works same as pci_conf_write. 1838 */ 1839 static void 1840 pccbb_conf_write(cc, tag, reg, val) 1841 cardbus_chipset_tag_t cc; 1842 cardbustag_t tag; 1843 int reg; /* register offset */ 1844 cardbusreg_t val; 1845 { 1846 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1847 1848 pci_conf_write(sc->sc_pc, tag, reg, val); 1849 } 1850 1851 #if 0 1852 STATIC int 1853 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1854 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1855 int speed, int flags, 1856 bus_space_handle_t * iohp) 1857 #endif 1858 /* 1859 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1860 * bus_addr_t start, bus_size_t size, 1861 * bus_size_t align, 1862 * struct pcmcia_io_handle *pcihp 1863 * 1864 * This function only allocates I/O region for pccard. This function 1865 * never maps the allocated region to pccard I/O area. 1866 * 1867 * XXX: The interface of this function is not very good, I believe. 1868 */ 1869 STATIC int 1870 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1871 pcmcia_chipset_handle_t pch; 1872 bus_addr_t start; /* start address */ 1873 bus_size_t size; 1874 bus_size_t align; 1875 struct pcmcia_io_handle *pcihp; 1876 { 1877 struct pcic_handle *ph = (struct pcic_handle *)pch; 1878 bus_addr_t ioaddr; 1879 int flags = 0; 1880 bus_space_tag_t iot; 1881 bus_space_handle_t ioh; 1882 #if rbus 1883 rbus_tag_t rb; 1884 #endif 1885 if (align == 0) { 1886 align = size; /* XXX: funny??? */ 1887 } 1888 1889 /* 1890 * Allocate some arbitrary I/O space. 1891 */ 1892 1893 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1894 1895 #if rbus 1896 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1897 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1898 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1899 return 1; 1900 } 1901 #else 1902 if (start) { 1903 ioaddr = start; 1904 if (bus_space_map(iot, start, size, 0, &ioh)) { 1905 return 1; 1906 } 1907 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1908 (u_long) ioaddr, (u_long) size)); 1909 } else { 1910 flags |= PCMCIA_IO_ALLOCATED; 1911 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1912 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1913 size, align, 0, 0, &ioaddr, &ioh)) { 1914 /* No room be able to be get. */ 1915 return 1; 1916 } 1917 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1918 (u_long) ioaddr, (u_long) size)); 1919 } 1920 #endif 1921 1922 pcihp->iot = iot; 1923 pcihp->ioh = ioh; 1924 pcihp->addr = ioaddr; 1925 pcihp->size = size; 1926 pcihp->flags = flags; 1927 1928 return 0; 1929 } 1930 1931 /* 1932 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1933 * struct pcmcia_io_handle *pcihp) 1934 * 1935 * This function only frees I/O region for pccard. 1936 * 1937 * XXX: The interface of this function is not very good, I believe. 1938 */ 1939 void 1940 pccbb_pcmcia_io_free(pch, pcihp) 1941 pcmcia_chipset_handle_t pch; 1942 struct pcmcia_io_handle *pcihp; 1943 { 1944 #if !rbus 1945 bus_space_tag_t iot = pcihp->iot; 1946 #endif 1947 bus_space_handle_t ioh = pcihp->ioh; 1948 bus_size_t size = pcihp->size; 1949 1950 #if rbus 1951 struct pccbb_softc *sc = 1952 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1953 rbus_tag_t rb = sc->sc_rbus_iot; 1954 1955 rbus_space_free(rb, ioh, size, NULL); 1956 #else 1957 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1958 bus_space_free(iot, ioh, size); 1959 else 1960 bus_space_unmap(iot, ioh, size); 1961 #endif 1962 } 1963 1964 /* 1965 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1966 * bus_addr_t offset, bus_size_t size, 1967 * struct pcmcia_io_handle *pcihp, 1968 * int *windowp) 1969 * 1970 * This function maps the allocated I/O region to pccard. This function 1971 * never allocates any I/O region for pccard I/O area. I don't 1972 * understand why the original authors of pcmciabus separated alloc and 1973 * map. I believe the two must be unite. 1974 * 1975 * XXX: no wait timing control? 1976 */ 1977 int 1978 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1979 pcmcia_chipset_handle_t pch; 1980 int width; 1981 bus_addr_t offset; 1982 bus_size_t size; 1983 struct pcmcia_io_handle *pcihp; 1984 int *windowp; 1985 { 1986 struct pcic_handle *ph = (struct pcic_handle *)pch; 1987 bus_addr_t ioaddr = pcihp->addr + offset; 1988 int i, win; 1989 #if defined CBB_DEBUG 1990 static char *width_names[] = { "dynamic", "io8", "io16" }; 1991 #endif 1992 1993 /* Sanity check I/O handle. */ 1994 1995 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1996 panic("pccbb_pcmcia_io_map iot is bogus"); 1997 } 1998 1999 /* XXX Sanity check offset/size. */ 2000 2001 win = -1; 2002 for (i = 0; i < PCIC_IO_WINS; i++) { 2003 if ((ph->ioalloc & (1 << i)) == 0) { 2004 win = i; 2005 ph->ioalloc |= (1 << i); 2006 break; 2007 } 2008 } 2009 2010 if (win == -1) { 2011 return 1; 2012 } 2013 2014 *windowp = win; 2015 2016 /* XXX this is pretty gross */ 2017 2018 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2019 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2020 2021 /* XXX wtf is this doing here? */ 2022 2023 #if 0 2024 printf(" port 0x%lx", (u_long) ioaddr); 2025 if (size > 1) { 2026 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2027 } 2028 #endif 2029 2030 ph->io[win].addr = ioaddr; 2031 ph->io[win].size = size; 2032 ph->io[win].width = width; 2033 2034 /* actual dirty register-value changing in the function below. */ 2035 pccbb_pcmcia_do_io_map(ph, win); 2036 2037 return 0; 2038 } 2039 2040 /* 2041 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2042 * 2043 * This function changes register-value to map I/O region for pccard. 2044 */ 2045 static void 2046 pccbb_pcmcia_do_io_map(ph, win) 2047 struct pcic_handle *ph; 2048 int win; 2049 { 2050 static u_int8_t pcic_iowidth[3] = { 2051 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2052 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2053 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2054 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2055 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2056 }; 2057 2058 #define PCIC_SIA_START_LOW 0 2059 #define PCIC_SIA_START_HIGH 1 2060 #define PCIC_SIA_STOP_LOW 2 2061 #define PCIC_SIA_STOP_HIGH 3 2062 2063 int regbase_win = 0x8 + win * 0x04; 2064 u_int8_t ioctl, enable; 2065 2066 DPRINTF( 2067 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2068 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2069 ph->io[win].width * 8)); 2070 2071 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2072 ph->io[win].addr & 0xff); 2073 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2074 (ph->io[win].addr >> 8) & 0xff); 2075 2076 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2077 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2078 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2079 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2080 2081 ioctl = Pcic_read(ph, PCIC_IOCTL); 2082 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2083 switch (win) { 2084 case 0: 2085 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2086 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2087 PCIC_IOCTL_IO0_DATASIZE_MASK); 2088 ioctl |= pcic_iowidth[ph->io[win].width]; 2089 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2090 break; 2091 case 1: 2092 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2093 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2094 PCIC_IOCTL_IO1_DATASIZE_MASK); 2095 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2096 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2097 break; 2098 } 2099 Pcic_write(ph, PCIC_IOCTL, ioctl); 2100 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2101 #if defined CBB_DEBUG 2102 { 2103 u_int8_t start_low = 2104 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2105 u_int8_t start_high = 2106 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2107 u_int8_t stop_low = 2108 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2109 u_int8_t stop_high = 2110 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2111 printf 2112 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2113 start_low, start_high, stop_low, stop_high, ioctl, enable); 2114 } 2115 #endif 2116 } 2117 2118 /* 2119 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2120 * 2121 * This function unmaps I/O region. No return value. 2122 */ 2123 STATIC void 2124 pccbb_pcmcia_io_unmap(pch, win) 2125 pcmcia_chipset_handle_t pch; 2126 int win; 2127 { 2128 struct pcic_handle *ph = (struct pcic_handle *)pch; 2129 int reg; 2130 2131 if (win >= PCIC_IO_WINS || win < 0) { 2132 panic("pccbb_pcmcia_io_unmap: window out of range"); 2133 } 2134 2135 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2136 switch (win) { 2137 case 0: 2138 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2139 break; 2140 case 1: 2141 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2142 break; 2143 } 2144 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2145 2146 ph->ioalloc &= ~(1 << win); 2147 } 2148 2149 /* 2150 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2151 * 2152 * This function enables the card. All information is stored in 2153 * the first argument, pcmcia_chipset_handle_t. 2154 */ 2155 static void 2156 pccbb_pcmcia_wait_ready(ph) 2157 struct pcic_handle *ph; 2158 { 2159 int i; 2160 2161 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2162 Pcic_read(ph, PCIC_IF_STATUS))); 2163 2164 for (i = 0; i < 10000; i++) { 2165 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2166 return; 2167 } 2168 delay(500); 2169 #ifdef CBB_DEBUG 2170 if ((i > 5000) && (i % 100 == 99)) 2171 printf("."); 2172 #endif 2173 } 2174 2175 #ifdef DIAGNOSTIC 2176 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2177 Pcic_read(ph, PCIC_IF_STATUS)); 2178 #endif 2179 } 2180 2181 /* 2182 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2183 * 2184 * This function enables the card. All information is stored in 2185 * the first argument, pcmcia_chipset_handle_t. 2186 */ 2187 STATIC void 2188 pccbb_pcmcia_socket_enable(pch) 2189 pcmcia_chipset_handle_t pch; 2190 { 2191 struct pcic_handle *ph = (struct pcic_handle *)pch; 2192 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2193 int cardtype, win; 2194 u_int8_t power, intr; 2195 pcireg_t spsr; 2196 int voltage; 2197 2198 /* this bit is mostly stolen from pcic_attach_card */ 2199 2200 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2201 2202 /* get card Vcc info */ 2203 2204 spsr = 2205 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2206 CB_SOCKET_STAT); 2207 if (spsr & CB_SOCKET_STAT_5VCARD) { 2208 DPRINTF(("5V card\n")); 2209 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2210 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2211 DPRINTF(("3V card\n")); 2212 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2213 } else { 2214 printf("?V card, 0x%x\n", spsr); /* XXX */ 2215 return; 2216 } 2217 2218 /* assert reset bit */ 2219 intr = Pcic_read(ph, PCIC_INTR); 2220 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2221 Pcic_write(ph, PCIC_INTR, intr); 2222 2223 /* disable socket i/o: negate output enable bit */ 2224 2225 power = Pcic_read(ph, PCIC_PWRCTL); 2226 power &= ~PCIC_PWRCTL_OE; 2227 Pcic_write(ph, PCIC_PWRCTL, power); 2228 2229 /* power down the socket to reset it, clear the card reset pin */ 2230 2231 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2232 2233 /* 2234 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2235 * we are changing Vcc (Toff). 2236 */ 2237 /* delay(300*1000); too much */ 2238 2239 /* power up the socket */ 2240 pccbb_power(sc, voltage); 2241 2242 /* 2243 * wait 100ms until power raise (Tpr) and 20ms to become 2244 * stable (Tsu(Vcc)). 2245 * 2246 * some machines require some more time to be settled 2247 * (another 200ms is added here). 2248 */ 2249 /* delay((100 + 20 + 200)*1000); too much */ 2250 2251 power = Pcic_read(ph, PCIC_PWRCTL); 2252 power |= PCIC_PWRCTL_OE; 2253 Pcic_write(ph, PCIC_PWRCTL, power); 2254 2255 /* 2256 * hold RESET at least 10us. 2257 */ 2258 delay(10); 2259 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2260 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2261 2262 /* clear the reset flag */ 2263 2264 intr |= PCIC_INTR_RESET; 2265 Pcic_write(ph, PCIC_INTR, intr); 2266 2267 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2268 2269 delay(20000); 2270 2271 /* wait for the chip to finish initializing */ 2272 2273 pccbb_pcmcia_wait_ready(ph); 2274 2275 /* zero out the address windows */ 2276 2277 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2278 2279 /* set the card type */ 2280 2281 cardtype = pcmcia_card_gettype(ph->pcmcia); 2282 2283 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2284 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2285 Pcic_write(ph, PCIC_INTR, intr); 2286 2287 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2288 ph->ph_parent->dv_xname, ph->sock, 2289 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2290 2291 /* reinstall all the memory and io mappings */ 2292 2293 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2294 if (ph->memalloc & (1 << win)) { 2295 pccbb_pcmcia_do_mem_map(ph, win); 2296 } 2297 } 2298 2299 for (win = 0; win < PCIC_IO_WINS; ++win) { 2300 if (ph->ioalloc & (1 << win)) { 2301 pccbb_pcmcia_do_io_map(ph, win); 2302 } 2303 } 2304 } 2305 2306 /* 2307 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2308 * 2309 * This function disables the card. All information is stored in 2310 * the first argument, pcmcia_chipset_handle_t. 2311 */ 2312 STATIC void 2313 pccbb_pcmcia_socket_disable(pch) 2314 pcmcia_chipset_handle_t pch; 2315 { 2316 struct pcic_handle *ph = (struct pcic_handle *)pch; 2317 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2318 u_int8_t power, intr; 2319 2320 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2321 2322 /* reset signal asserting... */ 2323 2324 intr = Pcic_read(ph, PCIC_INTR); 2325 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2326 Pcic_write(ph, PCIC_INTR, intr); 2327 delay(2 * 1000); 2328 2329 /* power down the socket */ 2330 power = Pcic_read(ph, PCIC_PWRCTL); 2331 power &= ~PCIC_PWRCTL_OE; 2332 Pcic_write(ph, PCIC_PWRCTL, power); 2333 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2334 /* 2335 * wait 300ms until power fails (Tpf). 2336 */ 2337 delay(300 * 1000); 2338 } 2339 2340 /* 2341 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2342 * 2343 * This function detects whether a card is in the slot or not. 2344 * If a card is inserted, return 1. Otherwise, return 0. 2345 */ 2346 STATIC int 2347 pccbb_pcmcia_card_detect(pch) 2348 pcmcia_chipset_handle_t pch; 2349 { 2350 struct pcic_handle *ph = (struct pcic_handle *)pch; 2351 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2352 2353 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2354 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2355 } 2356 2357 #if 0 2358 STATIC int 2359 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2360 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2361 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2362 #endif 2363 /* 2364 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2365 * bus_size_t size, 2366 * struct pcmcia_mem_handle *pcmhp) 2367 * 2368 * This function only allocates memory region for pccard. This 2369 * function never maps the allocated region to pccard memory area. 2370 * 2371 * XXX: Why the argument of start address is not in? 2372 */ 2373 STATIC int 2374 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2375 pcmcia_chipset_handle_t pch; 2376 bus_size_t size; 2377 struct pcmcia_mem_handle *pcmhp; 2378 { 2379 struct pcic_handle *ph = (struct pcic_handle *)pch; 2380 bus_space_handle_t memh; 2381 bus_addr_t addr; 2382 bus_size_t sizepg; 2383 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2384 #if rbus 2385 rbus_tag_t rb; 2386 #endif 2387 2388 /* out of sc->memh, allocate as many pages as necessary */ 2389 2390 /* convert size to PCIC pages */ 2391 /* 2392 * This is not enough; when the requested region is on the page 2393 * boundaries, this may calculate wrong result. 2394 */ 2395 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2396 #if 0 2397 if (sizepg > PCIC_MAX_MEM_PAGES) { 2398 return 1; 2399 } 2400 #endif 2401 2402 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2403 return 1; 2404 } 2405 2406 addr = 0; /* XXX gcc -Wuninitialized */ 2407 2408 #if rbus 2409 rb = sc->sc_rbus_memt; 2410 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2411 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2412 &addr, &memh)) { 2413 return 1; 2414 } 2415 #else 2416 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2417 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2418 0, /* boundary */ 2419 0, /* flags */ 2420 &addr, &memh)) { 2421 return 1; 2422 } 2423 #endif 2424 2425 DPRINTF( 2426 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2427 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2428 2429 pcmhp->memt = sc->sc_memt; 2430 pcmhp->memh = memh; 2431 pcmhp->addr = addr; 2432 pcmhp->size = size; 2433 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2434 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2435 pcmhp->mhandle = 0; 2436 /* No offset??? Funny. */ 2437 2438 return 0; 2439 } 2440 2441 /* 2442 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2443 * struct pcmcia_mem_handle *pcmhp) 2444 * 2445 * This function release the memory space allocated by the function 2446 * pccbb_pcmcia_mem_alloc(). 2447 */ 2448 STATIC void 2449 pccbb_pcmcia_mem_free(pch, pcmhp) 2450 pcmcia_chipset_handle_t pch; 2451 struct pcmcia_mem_handle *pcmhp; 2452 { 2453 #if rbus 2454 struct pcic_handle *ph = (struct pcic_handle *)pch; 2455 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2456 2457 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2458 #else 2459 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2460 #endif 2461 } 2462 2463 /* 2464 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2465 * 2466 * This function release the memory space allocated by the function 2467 * pccbb_pcmcia_mem_alloc(). 2468 */ 2469 STATIC void 2470 pccbb_pcmcia_do_mem_map(ph, win) 2471 struct pcic_handle *ph; 2472 int win; 2473 { 2474 int regbase_win; 2475 bus_addr_t phys_addr; 2476 bus_addr_t phys_end; 2477 2478 #define PCIC_SMM_START_LOW 0 2479 #define PCIC_SMM_START_HIGH 1 2480 #define PCIC_SMM_STOP_LOW 2 2481 #define PCIC_SMM_STOP_HIGH 3 2482 #define PCIC_CMA_LOW 4 2483 #define PCIC_CMA_HIGH 5 2484 2485 u_int8_t start_low, start_high = 0; 2486 u_int8_t stop_low, stop_high; 2487 u_int8_t off_low, off_high; 2488 u_int8_t mem_window; 2489 int reg; 2490 2491 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2492 int mem8 = 2493 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2494 || (kind == PCMCIA_MEM_ATTR); 2495 2496 regbase_win = 0x10 + win * 0x08; 2497 2498 phys_addr = ph->mem[win].addr; 2499 phys_end = phys_addr + ph->mem[win].size; 2500 2501 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2502 phys_addr, phys_end, ph->mem[win].offset)); 2503 2504 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2505 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2506 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2507 2508 /* bit 19:12 */ 2509 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2510 /* bit 23:20 and bit 7 on */ 2511 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2512 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2513 /* bit 31:24, for 32-bit address */ 2514 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2515 2516 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2517 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2518 2519 if (((struct pccbb_softc *)ph-> 2520 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2521 Pcic_write(ph, 0x40 + win, mem_window); 2522 } 2523 2524 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2525 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2526 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2527 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2528 2529 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2530 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2531 2532 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2533 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2534 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2535 | ((kind == PCMCIA_MEM_ATTR) ? 2536 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2537 2538 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2539 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2540 2541 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2542 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2543 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2544 2545 #if defined CBB_DEBUG 2546 { 2547 int r1, r2, r3, r4, r5, r6, r7 = 0; 2548 2549 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2550 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2551 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2552 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2553 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2554 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2555 if (((struct pccbb_softc *)(ph-> 2556 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2557 r7 = Pcic_read(ph, 0x40 + win); 2558 } 2559 2560 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2561 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2562 if (((struct pccbb_softc *)(ph-> 2563 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2564 DPRINTF((" %02x", r7)); 2565 } 2566 DPRINTF(("\n")); 2567 } 2568 #endif 2569 } 2570 2571 /* 2572 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2573 * bus_addr_t card_addr, bus_size_t size, 2574 * struct pcmcia_mem_handle *pcmhp, 2575 * bus_addr_t *offsetp, int *windowp) 2576 * 2577 * This function maps memory space allocated by the function 2578 * pccbb_pcmcia_mem_alloc(). 2579 */ 2580 STATIC int 2581 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2582 pcmcia_chipset_handle_t pch; 2583 int kind; 2584 bus_addr_t card_addr; 2585 bus_size_t size; 2586 struct pcmcia_mem_handle *pcmhp; 2587 bus_addr_t *offsetp; 2588 int *windowp; 2589 { 2590 struct pcic_handle *ph = (struct pcic_handle *)pch; 2591 bus_addr_t busaddr; 2592 long card_offset; 2593 int win; 2594 2595 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2596 if ((ph->memalloc & (1 << win)) == 0) { 2597 ph->memalloc |= (1 << win); 2598 break; 2599 } 2600 } 2601 2602 if (win == PCIC_MEM_WINS) { 2603 return 1; 2604 } 2605 2606 *windowp = win; 2607 2608 /* XXX this is pretty gross */ 2609 2610 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2611 panic("pccbb_pcmcia_mem_map memt is bogus"); 2612 } 2613 2614 busaddr = pcmhp->addr; 2615 2616 /* 2617 * compute the address offset to the pcmcia address space for the 2618 * pcic. this is intentionally signed. The masks and shifts below 2619 * will cause TRT to happen in the pcic registers. Deal with making 2620 * sure the address is aligned, and return the alignment offset. 2621 */ 2622 2623 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2624 card_addr -= *offsetp; 2625 2626 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2627 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2628 (u_long) card_addr)); 2629 2630 /* 2631 * include the offset in the size, and decrement size by one, since 2632 * the hw wants start/stop 2633 */ 2634 size += *offsetp - 1; 2635 2636 card_offset = (((long)card_addr) - ((long)busaddr)); 2637 2638 ph->mem[win].addr = busaddr; 2639 ph->mem[win].size = size; 2640 ph->mem[win].offset = card_offset; 2641 ph->mem[win].kind = kind; 2642 2643 pccbb_pcmcia_do_mem_map(ph, win); 2644 2645 return 0; 2646 } 2647 2648 /* 2649 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2650 * int window) 2651 * 2652 * This function unmaps memory space which mapped by the function 2653 * pccbb_pcmcia_mem_map(). 2654 */ 2655 STATIC void 2656 pccbb_pcmcia_mem_unmap(pch, window) 2657 pcmcia_chipset_handle_t pch; 2658 int window; 2659 { 2660 struct pcic_handle *ph = (struct pcic_handle *)pch; 2661 int reg; 2662 2663 if (window >= PCIC_MEM_WINS) { 2664 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2665 } 2666 2667 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2668 reg &= ~(1 << window); 2669 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2670 2671 ph->memalloc &= ~(1 << window); 2672 } 2673 2674 #if defined PCCBB_PCMCIA_POLL 2675 struct pccbb_poll_str { 2676 void *arg; 2677 int (*func) __P((void *)); 2678 int level; 2679 struct pcic_handle *ph; 2680 int count; 2681 int num; 2682 struct callout poll_ch; 2683 }; 2684 2685 static struct pccbb_poll_str pccbb_poll[10]; 2686 static int pccbb_poll_n = 0; 2687 2688 static void pccbb_pcmcia_poll __P((void *arg)); 2689 2690 static void 2691 pccbb_pcmcia_poll(arg) 2692 void *arg; 2693 { 2694 struct pccbb_poll_str *poll = arg; 2695 struct pcic_handle *ph = poll->ph; 2696 struct pccbb_softc *sc = ph->sc; 2697 int s; 2698 u_int32_t spsr; /* socket present-state reg */ 2699 2700 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2701 switch (poll->level) { 2702 case IPL_NET: 2703 s = splnet(); 2704 break; 2705 case IPL_BIO: 2706 s = splbio(); 2707 break; 2708 case IPL_TTY: /* fallthrough */ 2709 default: 2710 s = spltty(); 2711 break; 2712 } 2713 2714 spsr = 2715 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2716 CB_SOCKET_STAT); 2717 2718 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2719 if (!(spsr & 0x40)) /* CINT low */ 2720 #else 2721 if (1) 2722 #endif 2723 { 2724 if ((*poll->func) (poll->arg) > 0) { 2725 ++poll->count; 2726 // printf("intr: reported from poller, 0x%x\n", spsr); 2727 #if defined LEVEL2 2728 } else { 2729 printf("intr: miss! 0x%x\n", spsr); 2730 #endif 2731 } 2732 } 2733 splx(s); 2734 } 2735 #endif /* defined CB_PCMCIA_POLL */ 2736 2737 /* 2738 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2739 * struct pcmcia_function *pf, 2740 * int ipl, 2741 * int (*func)(void *), 2742 * void *arg); 2743 * 2744 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2745 */ 2746 STATIC void * 2747 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2748 pcmcia_chipset_handle_t pch; 2749 struct pcmcia_function *pf; 2750 int ipl; 2751 int (*func) __P((void *)); 2752 void *arg; 2753 { 2754 struct pcic_handle *ph = (struct pcic_handle *)pch; 2755 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2756 2757 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2758 /* what should I do? */ 2759 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2760 DPRINTF( 2761 ("%s does not provide edge nor pulse interrupt\n", 2762 sc->sc_dev.dv_xname)); 2763 return NULL; 2764 } 2765 /* 2766 * XXX Noooooo! The interrupt flag must set properly!! 2767 * dumb pcmcia driver!! 2768 */ 2769 } 2770 2771 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2772 } 2773 2774 /* 2775 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2776 * void *ih) 2777 * 2778 * This function disables PC-Card interrupt. 2779 */ 2780 STATIC void 2781 pccbb_pcmcia_intr_disestablish(pch, ih) 2782 pcmcia_chipset_handle_t pch; 2783 void *ih; 2784 { 2785 struct pcic_handle *ph = (struct pcic_handle *)pch; 2786 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2787 2788 pccbb_intr_disestablish(sc, ih); 2789 } 2790 2791 #if rbus 2792 /* 2793 * static int 2794 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2795 * bus_addr_t addr, bus_size_t size, 2796 * bus_addr_t mask, bus_size_t align, 2797 * int flags, bus_addr_t *addrp; 2798 * bus_space_handle_t *bshp) 2799 * 2800 * This function allocates a portion of memory or io space for 2801 * clients. This function is called from CardBus card drivers. 2802 */ 2803 static int 2804 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2805 cardbus_chipset_tag_t ct; 2806 rbus_tag_t rb; 2807 bus_addr_t addr; 2808 bus_size_t size; 2809 bus_addr_t mask; 2810 bus_size_t align; 2811 int flags; 2812 bus_addr_t *addrp; 2813 bus_space_handle_t *bshp; 2814 { 2815 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2816 2817 DPRINTF( 2818 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2819 addr, size, mask, align)); 2820 2821 if (align == 0) { 2822 align = size; 2823 } 2824 2825 if (rb->rb_bt == sc->sc_memt) { 2826 if (align < 16) { 2827 return 1; 2828 } 2829 } else if (rb->rb_bt == sc->sc_iot) { 2830 if (align < 4) { 2831 return 1; 2832 } 2833 /* XXX: hack for avoiding ISA image */ 2834 if (mask < 0x0100) { 2835 mask = 0x3ff; 2836 addr = 0x300; 2837 } 2838 2839 } else { 2840 DPRINTF( 2841 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2842 rb->rb_bt)); 2843 return 1; 2844 /* XXX: panic here? */ 2845 } 2846 2847 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2848 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2849 return 1; 2850 } 2851 2852 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2853 2854 return 0; 2855 } 2856 2857 /* 2858 * static int 2859 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2860 * bus_space_handle_t *bshp, bus_size_t size); 2861 * 2862 * This function is called from CardBus card drivers. 2863 */ 2864 static int 2865 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2866 cardbus_chipset_tag_t ct; 2867 rbus_tag_t rb; 2868 bus_space_handle_t bsh; 2869 bus_size_t size; 2870 { 2871 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2872 bus_space_tag_t bt = rb->rb_bt; 2873 2874 pccbb_close_win(sc, bt, bsh, size); 2875 2876 if (bt == sc->sc_memt) { 2877 } else if (bt == sc->sc_iot) { 2878 } else { 2879 return 1; 2880 /* XXX: panic here? */ 2881 } 2882 2883 return rbus_space_free(rb, bsh, size, NULL); 2884 } 2885 #endif /* rbus */ 2886 2887 #if rbus 2888 2889 static int 2890 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2891 struct pccbb_softc *sc; 2892 bus_space_tag_t bst; 2893 bus_addr_t addr; 2894 bus_size_t size; 2895 bus_space_handle_t bsh; 2896 int flags; 2897 { 2898 struct pccbb_win_chain_head *head; 2899 bus_addr_t align; 2900 2901 head = &sc->sc_iowindow; 2902 align = 0x04; 2903 if (sc->sc_memt == bst) { 2904 head = &sc->sc_memwindow; 2905 align = 0x1000; 2906 DPRINTF(("using memory window, %x %x %x\n\n", 2907 sc->sc_iot, sc->sc_memt, bst)); 2908 } 2909 2910 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2911 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2912 sc->sc_dev.dv_xname, 2913 (head == &sc->sc_memwindow) ? "mem" : "io"); 2914 } 2915 pccbb_winset(align, sc, bst); 2916 2917 return 0; 2918 } 2919 2920 static int 2921 pccbb_close_win(sc, bst, bsh, size) 2922 struct pccbb_softc *sc; 2923 bus_space_tag_t bst; 2924 bus_space_handle_t bsh; 2925 bus_size_t size; 2926 { 2927 struct pccbb_win_chain_head *head; 2928 bus_addr_t align; 2929 2930 head = &sc->sc_iowindow; 2931 align = 0x04; 2932 if (sc->sc_memt == bst) { 2933 head = &sc->sc_memwindow; 2934 align = 0x1000; 2935 } 2936 2937 if (pccbb_winlist_delete(head, bsh, size)) { 2938 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2939 sc->sc_dev.dv_xname, 2940 (head == &sc->sc_memwindow) ? "mem" : "io"); 2941 } 2942 pccbb_winset(align, sc, bst); 2943 2944 return 0; 2945 } 2946 2947 static int 2948 pccbb_winlist_insert(head, start, size, bsh, flags) 2949 struct pccbb_win_chain_head *head; 2950 bus_addr_t start; 2951 bus_size_t size; 2952 bus_space_handle_t bsh; 2953 int flags; 2954 { 2955 struct pccbb_win_chain *chainp, *elem; 2956 2957 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2958 M_NOWAIT)) == NULL) 2959 return (1); /* fail */ 2960 2961 elem->wc_start = start; 2962 elem->wc_end = start + (size - 1); 2963 elem->wc_handle = bsh; 2964 elem->wc_flags = flags; 2965 2966 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2967 chainp = TAILQ_NEXT(chainp, wc_list)) { 2968 if (chainp->wc_end < start) 2969 continue; 2970 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2971 return (0); 2972 } 2973 2974 TAILQ_INSERT_TAIL(head, elem, wc_list); 2975 return (0); 2976 } 2977 2978 static int 2979 pccbb_winlist_delete(head, bsh, size) 2980 struct pccbb_win_chain_head *head; 2981 bus_space_handle_t bsh; 2982 bus_size_t size; 2983 { 2984 struct pccbb_win_chain *chainp; 2985 2986 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2987 chainp = TAILQ_NEXT(chainp, wc_list)) { 2988 if (chainp->wc_handle != bsh) 2989 continue; 2990 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2991 printf("pccbb_winlist_delete: window 0x%lx size " 2992 "inconsistent: 0x%lx, 0x%lx\n", 2993 chainp->wc_start, 2994 chainp->wc_end - chainp->wc_start, 2995 size - 1); 2996 return 1; 2997 } 2998 2999 TAILQ_REMOVE(head, chainp, wc_list); 3000 free(chainp, M_DEVBUF); 3001 3002 return 0; 3003 } 3004 3005 return 1; /* fail: no candidate to remove */ 3006 } 3007 3008 static void 3009 pccbb_winset(align, sc, bst) 3010 bus_addr_t align; 3011 struct pccbb_softc *sc; 3012 bus_space_tag_t bst; 3013 { 3014 pci_chipset_tag_t pc; 3015 pcitag_t tag; 3016 bus_addr_t mask = ~(align - 1); 3017 struct { 3018 cardbusreg_t win_start; 3019 cardbusreg_t win_limit; 3020 int win_flags; 3021 } win[2]; 3022 struct pccbb_win_chain *chainp; 3023 int offs; 3024 3025 win[0].win_start = 0xffffffff; 3026 win[0].win_limit = 0; 3027 win[1].win_start = 0xffffffff; 3028 win[1].win_limit = 0; 3029 3030 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3031 offs = 0x2c; 3032 if (sc->sc_memt == bst) { 3033 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3034 offs = 0x1c; 3035 } 3036 3037 if (chainp != NULL) { 3038 win[0].win_start = chainp->wc_start & mask; 3039 win[0].win_limit = chainp->wc_end & mask; 3040 win[0].win_flags = chainp->wc_flags; 3041 chainp = TAILQ_NEXT(chainp, wc_list); 3042 } 3043 3044 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3045 if (win[1].win_start == 0xffffffff) { 3046 /* window 1 is not used */ 3047 if ((win[0].win_flags == chainp->wc_flags) && 3048 (win[0].win_limit + align >= 3049 (chainp->wc_start & mask))) { 3050 /* concatenate */ 3051 win[0].win_limit = chainp->wc_end & mask; 3052 } else { 3053 /* make new window */ 3054 win[1].win_start = chainp->wc_start & mask; 3055 win[1].win_limit = chainp->wc_end & mask; 3056 win[1].win_flags = chainp->wc_flags; 3057 } 3058 continue; 3059 } 3060 3061 /* Both windows are engaged. */ 3062 if (win[0].win_flags == win[1].win_flags) { 3063 /* same flags */ 3064 if (win[0].win_flags == chainp->wc_flags) { 3065 if (win[1].win_start - (win[0].win_limit + 3066 align) < 3067 (chainp->wc_start & mask) - 3068 ((chainp->wc_end & mask) + align)) { 3069 /* 3070 * merge window 0 and 1, and set win1 3071 * to chainp 3072 */ 3073 win[0].win_limit = win[1].win_limit; 3074 win[1].win_start = 3075 chainp->wc_start & mask; 3076 win[1].win_limit = 3077 chainp->wc_end & mask; 3078 } else { 3079 win[1].win_limit = 3080 chainp->wc_end & mask; 3081 } 3082 } else { 3083 /* different flags */ 3084 3085 /* concatenate win0 and win1 */ 3086 win[0].win_limit = win[1].win_limit; 3087 /* allocate win[1] to new space */ 3088 win[1].win_start = chainp->wc_start & mask; 3089 win[1].win_limit = chainp->wc_end & mask; 3090 win[1].win_flags = chainp->wc_flags; 3091 } 3092 } else { 3093 /* the flags of win[0] and win[1] is different */ 3094 if (win[0].win_flags == chainp->wc_flags) { 3095 win[0].win_limit = chainp->wc_end & mask; 3096 /* 3097 * XXX this creates overlapping windows, so 3098 * what should the poor bridge do if one is 3099 * cachable, and the other is not? 3100 */ 3101 printf("%s: overlapping windows\n", 3102 sc->sc_dev.dv_xname); 3103 } else { 3104 win[1].win_limit = chainp->wc_end & mask; 3105 } 3106 } 3107 } 3108 3109 pc = sc->sc_pc; 3110 tag = sc->sc_tag; 3111 pci_conf_write(pc, tag, offs, win[0].win_start); 3112 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3113 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3114 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3115 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3116 pci_conf_read(pc, tag, offs), 3117 pci_conf_read(pc, tag, offs + 4) + align, 3118 pci_conf_read(pc, tag, offs + 8), 3119 pci_conf_read(pc, tag, offs + 12) + align)); 3120 3121 if (bst == sc->sc_memt) { 3122 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3123 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3124 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3125 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3126 } 3127 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3128 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3129 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3130 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3131 } 3132 } 3133 } 3134 3135 #endif /* rbus */ 3136 3137 static void 3138 pccbb_powerhook(why, arg) 3139 int why; 3140 void *arg; 3141 { 3142 struct pccbb_softc *sc = arg; 3143 u_int32_t reg; 3144 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3145 bus_space_handle_t base_memh = sc->sc_base_memh; 3146 3147 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3148 3149 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3150 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3151 if (sc->sc_pil_intr_enable) { 3152 (void)pccbbintr_function(sc); 3153 } 3154 sc->sc_pil_intr_enable = 0; 3155 3156 /* ToDo: deactivate or suspend child devices */ 3157 3158 } 3159 3160 if (why == PWR_RESUME) { 3161 /* CSC Interrupt: Card detect interrupt on */ 3162 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3163 /* Card detect intr is turned on. */ 3164 reg |= CB_SOCKET_MASK_CD; 3165 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3166 /* reset interrupt */ 3167 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3168 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3169 3170 /* 3171 * check for card insertion or removal during suspend period. 3172 * XXX: the code can't cope with card swap (remove then 3173 * insert). how can we detect such situation? 3174 */ 3175 (void)pccbbintr(sc); 3176 3177 sc->sc_pil_intr_enable = 1; 3178 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3179 3180 /* ToDo: activate or wakeup child devices */ 3181 } 3182 } 3183
Indexes created Fri Sep 26 08:10:20 GMT 2025