pccbb.c revision 1.47
1 /* $NetBSD: pccbb.c,v 1.47 2000/11/27 09:04:32 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 93 void pccbbattach __P((struct device *, struct device *, void *)); 94 int pccbbintr __P((void *)); 95 static void pci113x_insert __P((void *)); 96 static int pccbbintr_function __P((struct pccbb_softc *)); 97 98 static int pccbb_detect_card __P((struct pccbb_softc *)); 99 100 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 101 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 102 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 103 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 104 105 STATIC int cb_reset __P((struct pccbb_softc *)); 106 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 107 STATIC int cbbprint __P((void *, const char *)); 108 109 static int cb_chipset __P((u_int32_t, int *)); 110 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 111 struct pcmciabus_attach_args *)); 112 #if 0 113 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 114 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 115 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 116 #endif 117 118 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 119 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 120 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 121 #if !rbus 122 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 123 u_int32_t)); 124 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 125 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 126 u_int32_t)); 127 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 128 #endif /* !rbus */ 129 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 130 int level, int (*ih) (void *), void *sc)); 131 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 132 133 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 static void pccbb_powerhook __P((int, void *)); 171 172 /* bus-space allocation and deallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 178 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t)); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 187 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t)); 189 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int)); 191 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 192 bus_space_handle_t, bus_size_t)); 193 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t)); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback __P((struct device *)); 201 202 #if defined SHOW_REGS 203 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 204 bus_space_tag_t memt, bus_space_handle_t memh)); 205 #endif 206 207 struct cfattach cbb_pci_ca = { 208 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 209 }; 210 211 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 212 pccbb_pcmcia_mem_alloc, 213 pccbb_pcmcia_mem_free, 214 pccbb_pcmcia_mem_map, 215 pccbb_pcmcia_mem_unmap, 216 pccbb_pcmcia_io_alloc, 217 pccbb_pcmcia_io_free, 218 pccbb_pcmcia_io_map, 219 pccbb_pcmcia_io_unmap, 220 pccbb_pcmcia_intr_establish, 221 pccbb_pcmcia_intr_disestablish, 222 pccbb_pcmcia_socket_enable, 223 pccbb_pcmcia_socket_disable, 224 pccbb_pcmcia_card_detect 225 }; 226 227 #if rbus 228 static struct cardbus_functions pccbb_funcs = { 229 pccbb_rbus_cb_space_alloc, 230 pccbb_rbus_cb_space_free, 231 pccbb_cb_intr_establish, 232 pccbb_cb_intr_disestablish, 233 pccbb_ctrl, 234 pccbb_power, 235 pccbb_make_tag, 236 pccbb_free_tag, 237 pccbb_conf_read, 238 pccbb_conf_write, 239 }; 240 #else 241 static struct cardbus_functions pccbb_funcs = { 242 pccbb_ctrl, 243 pccbb_power, 244 pccbb_mem_open, 245 pccbb_mem_close, 246 pccbb_io_open, 247 pccbb_io_close, 248 pccbb_cb_intr_establish, 249 pccbb_cb_intr_disestablish, 250 pccbb_make_tag, 251 pccbb_conf_read, 252 pccbb_conf_write, 253 }; 254 #endif 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 struct cfdata *match; 260 void *aux; 261 { 262 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 263 264 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 265 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 266 PCI_INTERFACE(pa->pa_class) == 0) { 267 return 1; 268 } 269 270 return 0; 271 } 272 273 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 274 | ((prod) << PCI_PRODUCT_SHIFT)) 275 276 struct yenta_chipinfo { 277 pcireg_t yc_id; /* vendor tag | product tag */ 278 int yc_chiptype; 279 int yc_flags; 280 } yc_chipsets[] = { 281 /* Texas Instruments chips */ 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 307 /* Ricoh chips */ 308 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 309 PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 311 PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 313 PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 315 PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 319 PCCBB_PCMCIA_MEM_32}, 320 321 /* Toshiba products */ 322 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 323 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 325 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 327 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 329 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 330 331 /* Cirrus Logic products */ 332 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 333 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 335 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 336 337 /* sentinel, or Generic chip */ 338 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 339 }; 340 341 static int 342 cb_chipset(pci_id, flagp) 343 u_int32_t pci_id; 344 int *flagp; 345 { 346 struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return (yc->yc_chiptype); 358 } 359 360 static void 361 pccbb_shutdown(void *arg) 362 { 363 struct pccbb_softc *sc = arg; 364 pcireg_t command; 365 366 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 367 368 /* turn off power */ 369 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 370 371 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 372 0); 373 374 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 375 376 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 377 PCI_COMMAND_MASTER_ENABLE); 378 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 379 380 } 381 382 void 383 pccbbattach(parent, self, aux) 384 struct device *parent; 385 struct device *self; 386 void *aux; 387 { 388 struct pccbb_softc *sc = (void *)self; 389 struct pci_attach_args *pa = aux; 390 pci_chipset_tag_t pc = pa->pa_pc; 391 pcireg_t busreg, reg, sock_base; 392 bus_addr_t sockbase; 393 char devinfo[256]; 394 int flags; 395 396 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 397 398 pci_devinfo(pa->pa_id, 0, 0, devinfo); 399 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 400 #ifdef CBB_DEBUG 401 printf(" (chipflags %x)", flags); 402 #endif 403 printf("\n"); 404 405 TAILQ_INIT(&sc->sc_memwindow); 406 TAILQ_INIT(&sc->sc_iowindow); 407 408 #if rbus 409 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 410 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 411 #endif /* rbus */ 412 413 sc->sc_base_memh = 0; 414 415 /* 416 * MAP socket registers and ExCA registers on memory-space 417 * When no valid address is set on socket base registers (on pci 418 * config space), get it not polite way. 419 */ 420 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 421 422 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 423 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 424 /* The address must be valid. */ 425 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 426 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 427 printf("%s: can't map socket base address 0x%x\n", 428 sc->sc_dev.dv_xname, sock_base); 429 /* 430 * I think it's funny: socket base registers must be 431 * mapped on memory space, but ... 432 */ 433 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 434 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 435 NULL)) { 436 printf("%s: can't map socket base address" 437 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 438 sockbase); 439 /* give up... allocate reg space via rbus. */ 440 sc->sc_base_memh = 0; 441 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 442 } 443 } else { 444 DPRINTF(("%s: socket base address 0x%lx\n", 445 sc->sc_dev.dv_xname, sockbase)); 446 } 447 } 448 449 sc->sc_mem_start = 0; /* XXX */ 450 sc->sc_mem_end = 0xffffffff; /* XXX */ 451 452 /* 453 * When interrupt isn't routed correctly, give up probing cbb and do 454 * not kill pcic-compatible port. 455 */ 456 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 457 printf("%s: NOT USED because of unconfigured interrupt\n", 458 sc->sc_dev.dv_xname); 459 return; 460 } 461 462 /* 463 * When bus number isn't set correctly, give up using 32-bit CardBus 464 * mode. 465 */ 466 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 467 #if notyet 468 if (((busreg >> 8) & 0xff) == 0) { 469 printf("%s: CardBus support disabled because of unconfigured bus number\n", 470 sc->sc_dev.dv_xname); 471 flags |= PCCBB_PCMCIA_16BITONLY; 472 } 473 #endif 474 475 /* pccbb_machdep.c end */ 476 477 #if defined CBB_DEBUG 478 { 479 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 480 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 481 intrname[pa->pa_intrpin], pa->pa_intrline); 482 } 483 #endif 484 485 /* setup softc */ 486 sc->sc_pc = pc; 487 sc->sc_iot = pa->pa_iot; 488 sc->sc_memt = pa->pa_memt; 489 sc->sc_dmat = pa->pa_dmat; 490 sc->sc_tag = pa->pa_tag; 491 sc->sc_function = pa->pa_function; 492 493 sc->sc_intrline = pa->pa_intrline; 494 sc->sc_intrtag = pa->pa_intrtag; 495 sc->sc_intrpin = pa->pa_intrpin; 496 497 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 498 499 shutdownhook_establish(pccbb_shutdown, sc); 500 501 /* Disable legacy register mapping. */ 502 switch (sc->sc_chipset) { 503 case CB_RX5C46X: /* fallthrough */ 504 #if 0 505 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 506 case CB_RX5C47X: 507 #endif 508 /* 509 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 510 * cannot be disabled by substituting 0 into PCI_LEGACY 511 * register. Ricoh CardBus bridges have special bits on Bridge 512 * control reg (addr 0x3e on PCI config space). 513 */ 514 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 515 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 516 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 517 break; 518 519 default: 520 /* XXX I don't know proper way to kill legacy I/O. */ 521 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 522 break; 523 } 524 525 config_defer(self, pccbb_pci_callback); 526 } 527 528 529 530 531 /* 532 * static void pccbb_pci_callback(struct device *self) 533 * 534 * The actual attach routine: get memory space for YENTA register 535 * space, setup YENTA register and route interrupt. 536 * 537 * This function should be deferred because this device may obtain 538 * memory space dynamically. This function must avoid obtaining 539 * memory area which has already kept for another device. 540 */ 541 static void 542 pccbb_pci_callback(self) 543 struct device *self; 544 { 545 struct pccbb_softc *sc = (void *)self; 546 pci_chipset_tag_t pc = sc->sc_pc; 547 bus_space_tag_t base_memt; 548 bus_space_handle_t base_memh; 549 u_int32_t maskreg; 550 pci_intr_handle_t ih; 551 const char *intrstr = NULL; 552 bus_addr_t sockbase; 553 struct cbslot_attach_args cba; 554 struct pcmciabus_attach_args paa; 555 struct cardslot_attach_args caa; 556 struct cardslot_softc *csc; 557 558 if (0 == sc->sc_base_memh) { 559 /* The socket registers aren't mapped correctly. */ 560 #if rbus 561 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 562 (sc->sc_chipset == CB_RX5C47X 563 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 564 0, &sockbase, &sc->sc_base_memh)) { 565 return; 566 } 567 sc->sc_base_memt = sc->sc_memt; 568 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 569 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 570 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 571 PCI_SOCKBASE))); 572 #else 573 sc->sc_base_memt = sc->sc_memt; 574 #if !defined CBB_PCI_BASE 575 #define CBB_PCI_BASE 0x20000000 576 #endif 577 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 578 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 579 /* cannot allocate memory space */ 580 return; 581 } 582 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 583 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 584 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 585 sc->sc_tag, PCI_SOCKBASE))); 586 #endif 587 } 588 589 /* bus bridge initialization */ 590 pccbb_chipinit(sc); 591 592 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 593 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 594 595 /* CSC Interrupt: Card detect interrupt on */ 596 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 597 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 598 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 599 /* reset interrupt */ 600 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 601 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 602 603 /* clear data structure for child device interrupt handlers */ 604 sc->sc_pil = NULL; 605 sc->sc_pil_intr_enable = 1; 606 607 /* Map and establish the interrupt. */ 608 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 609 sc->sc_intrline, &ih)) { 610 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 611 return; 612 } 613 intrstr = pci_intr_string(pc, ih); 614 615 /* 616 * XXX pccbbintr should be called under the priority lower 617 * than any other hard interrputs. 618 */ 619 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 620 621 if (sc->sc_ih == NULL) { 622 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 623 if (intrstr != NULL) { 624 printf(" at %s", intrstr); 625 } 626 printf("\n"); 627 return; 628 } 629 630 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 631 powerhook_establish(pccbb_powerhook, sc); 632 633 { 634 u_int32_t sockstat = 635 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 636 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 637 sc->sc_flags |= CBB_CARDEXIST; 638 } 639 } 640 641 /* 642 * attach cardbus 643 */ 644 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 645 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 646 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 647 648 /* initialize cbslot_attach */ 649 cba.cba_busname = "cardbus"; 650 cba.cba_iot = sc->sc_iot; 651 cba.cba_memt = sc->sc_memt; 652 cba.cba_dmat = sc->sc_dmat; 653 cba.cba_bus = (busreg >> 8) & 0x0ff; 654 cba.cba_cc = (void *)sc; 655 cba.cba_cf = &pccbb_funcs; 656 cba.cba_intrline = sc->sc_intrline; 657 658 #if rbus 659 cba.cba_rbus_iot = sc->sc_rbus_iot; 660 cba.cba_rbus_memt = sc->sc_rbus_memt; 661 #endif 662 663 cba.cba_cacheline = PCI_CACHELINE(bhlc); 664 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 665 666 printf("%s: cacheline 0x%x lattimer 0x%x\n", 667 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 668 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 669 busreg); 670 #if defined SHOW_REGS 671 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 672 sc->sc_base_memh); 673 #endif 674 } 675 676 pccbb_pcmcia_attach_setup(sc, &paa); 677 caa.caa_cb_attach = NULL; 678 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 679 caa.caa_cb_attach = &cba; 680 } 681 caa.caa_16_attach = &paa; 682 caa.caa_ph = &sc->sc_pcmcia_h; 683 684 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 685 DPRINTF(("pccbbattach: found cardslot\n")); 686 sc->sc_csc = csc; 687 } 688 689 return; 690 } 691 692 693 694 695 696 /* 697 * static void pccbb_chipinit(struct pccbb_softc *sc) 698 * 699 * This function initialize YENTA chip registers listed below: 700 * 1) PCI command reg, 701 * 2) PCI and CardBus latency timer, 702 * 3) route PCI interrupt, 703 * 4) close all memory and io windows. 704 */ 705 static void 706 pccbb_chipinit(sc) 707 struct pccbb_softc *sc; 708 { 709 pci_chipset_tag_t pc = sc->sc_pc; 710 pcitag_t tag = sc->sc_tag; 711 pcireg_t reg; 712 713 /* 714 * Set PCI command reg. 715 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 716 */ 717 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 718 /* I believe it is harmless. */ 719 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 720 PCI_COMMAND_MASTER_ENABLE); 721 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 722 723 /* 724 * Set CardBus latency timer. 725 */ 726 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 727 if (PCI_CB_LATENCY(reg) < 0x20) { 728 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 729 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 730 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 731 } 732 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 733 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 734 735 /* 736 * Set PCI latency timer. 737 */ 738 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 739 if (PCI_LATTIMER(reg) < 0x10) { 740 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 741 reg |= (0x10 << PCI_LATTIMER_SHIFT); 742 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 743 } 744 DPRINTF(("PCI latency timer 0x%x (%x)\n", 745 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 746 747 748 /* Route functional interrupts to PCI. */ 749 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 750 reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 751 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 752 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 753 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 754 755 switch (sc->sc_chipset) { 756 case CB_TI113X: 757 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 758 /* This bit is shared, but may read as 0 on some chips, so set 759 it explicitly on both functions. */ 760 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 761 /* CSC intr enable */ 762 reg |= PCI113X_CBCTRL_PCI_CSC; 763 /* functional intr prohibit | prohibit ISA routing */ 764 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 765 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 766 break; 767 768 case CB_TOPIC95B: 769 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 770 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 771 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 772 773 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 774 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 775 sc->sc_dev.dv_xname, reg)); 776 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 777 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 778 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 779 DPRINTF(("0x%x\n", reg)); 780 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 781 break; 782 } 783 784 /* Close all memory and I/O windows. */ 785 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 786 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 787 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 788 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 789 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 790 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 791 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 792 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 793 794 /* reset 16-bit pcmcia bus */ 795 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 796 0x800 + PCIC_INTR, 797 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 798 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 799 800 /* turn of power */ 801 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 802 } 803 804 805 806 807 /* 808 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 809 * struct pcmciabus_attach_args *paa) 810 * 811 * This function attaches 16-bit PCcard bus. 812 */ 813 STATIC void 814 pccbb_pcmcia_attach_setup(sc, paa) 815 struct pccbb_softc *sc; 816 struct pcmciabus_attach_args *paa; 817 { 818 struct pcic_handle *ph = &sc->sc_pcmcia_h; 819 #if rbus 820 rbus_tag_t rb; 821 #endif 822 823 /* initialize pcmcia part in pccbb_softc */ 824 ph->ph_parent = (struct device *)sc; 825 ph->sock = sc->sc_function; 826 ph->flags = 0; 827 ph->shutdown = 0; 828 ph->ih_irq = sc->sc_intrline; 829 ph->ph_bus_t = sc->sc_base_memt; 830 ph->ph_bus_h = sc->sc_base_memh; 831 ph->ph_read = pccbb_pcmcia_read; 832 ph->ph_write = pccbb_pcmcia_write; 833 sc->sc_pct = &pccbb_pcmcia_funcs; 834 835 /* 836 * We need to do a few things here: 837 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 838 * setting the IRQ numbers to 0. 839 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 840 * routing of CSC interrupts (e.g. card removal) to PCI while in 841 * PCMCIA mode. We just leave this set all the time. 842 * 3) Enable card insertion/removal interrupts in case the chip also 843 * needs that while in PCMCIA mode. 844 * 4) Clear any pending CSC interrupt. 845 */ 846 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 847 if (sc->sc_chipset == CB_TI113X) { 848 Pcic_write(ph, PCIC_CSC_INTR, 0); 849 } else { 850 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 851 Pcic_read(ph, PCIC_CSC); 852 } 853 854 /* initialize pcmcia bus attachment */ 855 paa->paa_busname = "pcmcia"; 856 paa->pct = sc->sc_pct; 857 paa->pch = ph; 858 paa->iobase = 0; /* I don't use them */ 859 paa->iosize = 0; 860 #if rbus 861 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 862 paa->iobase = rb->rb_start + rb->rb_offset; 863 paa->iosize = rb->rb_end - rb->rb_start; 864 #endif 865 866 return; 867 } 868 869 #if 0 870 STATIC void 871 pccbb_pcmcia_attach_card(ph) 872 struct pcic_handle *ph; 873 { 874 if (ph->flags & PCIC_FLAG_CARDP) { 875 panic("pccbb_pcmcia_attach_card: already attached"); 876 } 877 878 /* call the MI attach function */ 879 pcmcia_card_attach(ph->pcmcia); 880 881 ph->flags |= PCIC_FLAG_CARDP; 882 } 883 884 STATIC void 885 pccbb_pcmcia_detach_card(ph, flags) 886 struct pcic_handle *ph; 887 int flags; 888 { 889 if (!(ph->flags & PCIC_FLAG_CARDP)) { 890 panic("pccbb_pcmcia_detach_card: already detached"); 891 } 892 893 ph->flags &= ~PCIC_FLAG_CARDP; 894 895 /* call the MI detach function */ 896 pcmcia_card_detach(ph->pcmcia, flags); 897 } 898 #endif 899 900 /* 901 * int pccbbintr(arg) 902 * void *arg; 903 * This routine handles the interrupt from Yenta PCI-CardBus bridge 904 * itself. 905 */ 906 int 907 pccbbintr(arg) 908 void *arg; 909 { 910 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 911 u_int32_t sockevent, sockstate; 912 bus_space_tag_t memt = sc->sc_base_memt; 913 bus_space_handle_t memh = sc->sc_base_memh; 914 struct pcic_handle *ph = &sc->sc_pcmcia_h; 915 916 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 917 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 918 Pcic_read(ph, PCIC_CSC); 919 920 if (sockevent == 0) { 921 /* This intr is not for me: it may be for my child devices. */ 922 if (sc->sc_pil_intr_enable) { 923 return pccbbintr_function(sc); 924 } else { 925 return 0; 926 } 927 } 928 929 if (sockevent & CB_SOCKET_EVENT_CD) { 930 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 931 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 932 /* A card should be removed. */ 933 if (sc->sc_flags & CBB_CARDEXIST) { 934 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 935 sockevent)); 936 DPRINTF((" card removed, 0x%08x\n", sockstate)); 937 sc->sc_flags &= ~CBB_CARDEXIST; 938 if (sc->sc_csc->sc_status & 939 CARDSLOT_STATUS_CARD_16) { 940 #if 0 941 struct pcic_handle *ph = 942 &sc->sc_pcmcia_h; 943 944 pcmcia_card_deactivate(ph->pcmcia); 945 pccbb_pcmcia_socket_disable(ph); 946 pccbb_pcmcia_detach_card(ph, 947 DETACH_FORCE); 948 #endif 949 cardslot_event_throw(sc->sc_csc, 950 CARDSLOT_EVENT_REMOVAL_16); 951 } else if (sc->sc_csc->sc_status & 952 CARDSLOT_STATUS_CARD_CB) { 953 /* Cardbus intr removed */ 954 cardslot_event_throw(sc->sc_csc, 955 CARDSLOT_EVENT_REMOVAL_CB); 956 } 957 } 958 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 959 /* 960 * The pccbbintr may called from powerdown hook when 961 * the system resumed, to detect the card 962 * insertion/removal during suspension. 963 */ 964 (sc->sc_flags & CBB_CARDEXIST) == 0) { 965 if (sc->sc_flags & CBB_INSERTING) { 966 callout_stop(&sc->sc_insert_ch); 967 } 968 callout_reset(&sc->sc_insert_ch, hz / 10, 969 pci113x_insert, sc); 970 sc->sc_flags |= CBB_INSERTING; 971 } 972 } 973 974 return (1); 975 } 976 977 /* 978 * static int pccbbintr_function(struct pccbb_softc *sc) 979 * 980 * This function calls each interrupt handler registered at the 981 * bridge. The interrupt handlers are called in registered order. 982 */ 983 static int 984 pccbbintr_function(sc) 985 struct pccbb_softc *sc; 986 { 987 int retval = 0, val; 988 struct pccbb_intrhand_list *pil; 989 int s, splchanged; 990 991 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 992 /* 993 * XXX priority change. gross. I use if-else 994 * sentense instead of switch-case sentense because of 995 * avoiding duplicate case value error. More than one 996 * IPL_XXX use same value. It depends on 997 * implimentation. 998 */ 999 splchanged = 1; 1000 if (pil->pil_level == IPL_SERIAL) { 1001 s = splserial(); 1002 } else if (pil->pil_level == IPL_HIGH) { 1003 s = splhigh(); 1004 } else if (pil->pil_level == IPL_CLOCK) { 1005 s = splclock(); 1006 } else if (pil->pil_level == IPL_AUDIO) { 1007 s = splaudio(); 1008 } else if (pil->pil_level == IPL_IMP) { 1009 s = splimp(); 1010 } else if (pil->pil_level == IPL_TTY) { 1011 s = spltty(); 1012 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1013 s = splsoftserial(); 1014 } else if (pil->pil_level == IPL_NET) { 1015 s = splnet(); 1016 } else { 1017 splchanged = 0; 1018 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1019 } 1020 1021 val = (*pil->pil_func)(pil->pil_arg); 1022 1023 if (splchanged != 0) { 1024 splx(s); 1025 } 1026 1027 retval = retval == 1 ? 1 : 1028 retval == 0 ? val : val != 0 ? val : retval; 1029 } 1030 1031 return retval; 1032 } 1033 1034 static void 1035 pci113x_insert(arg) 1036 void *arg; 1037 { 1038 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1039 u_int32_t sockevent, sockstate; 1040 1041 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1042 CB_SOCKET_EVENT); 1043 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1044 CB_SOCKET_STAT); 1045 1046 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1047 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1048 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1049 sc->sc_flags |= CBB_CARDEXIST; 1050 /* call pccard interrupt handler here */ 1051 if (sockstate & CB_SOCKET_STAT_16BIT) { 1052 /* 16-bit card found */ 1053 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1054 cardslot_event_throw(sc->sc_csc, 1055 CARDSLOT_EVENT_INSERTION_16); 1056 } else if (sockstate & CB_SOCKET_STAT_CB) { 1057 /* cardbus card found */ 1058 /* cardbus_attach_card(sc->sc_csc); */ 1059 cardslot_event_throw(sc->sc_csc, 1060 CARDSLOT_EVENT_INSERTION_CB); 1061 } else { 1062 /* who are you? */ 1063 } 1064 } else { 1065 callout_reset(&sc->sc_insert_ch, hz / 10, 1066 pci113x_insert, sc); 1067 } 1068 } 1069 1070 #define PCCBB_PCMCIA_OFFSET 0x800 1071 static u_int8_t 1072 pccbb_pcmcia_read(ph, reg) 1073 struct pcic_handle *ph; 1074 int reg; 1075 { 1076 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1077 PCCBB_PCMCIA_OFFSET + reg); 1078 } 1079 1080 static void 1081 pccbb_pcmcia_write(ph, reg, val) 1082 struct pcic_handle *ph; 1083 int reg; 1084 u_int8_t val; 1085 { 1086 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1087 val); 1088 } 1089 1090 /* 1091 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1092 */ 1093 STATIC int 1094 pccbb_ctrl(ct, command) 1095 cardbus_chipset_tag_t ct; 1096 int command; 1097 { 1098 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1099 1100 switch (command) { 1101 case CARDBUS_CD: 1102 if (2 == pccbb_detect_card(sc)) { 1103 int retval = 0; 1104 int status = cb_detect_voltage(sc); 1105 if (PCCARD_VCC_5V & status) { 1106 retval |= CARDBUS_5V_CARD; 1107 } 1108 if (PCCARD_VCC_3V & status) { 1109 retval |= CARDBUS_3V_CARD; 1110 } 1111 if (PCCARD_VCC_XV & status) { 1112 retval |= CARDBUS_XV_CARD; 1113 } 1114 if (PCCARD_VCC_YV & status) { 1115 retval |= CARDBUS_YV_CARD; 1116 } 1117 return retval; 1118 } else { 1119 return 0; 1120 } 1121 break; 1122 case CARDBUS_RESET: 1123 return cb_reset(sc); 1124 break; 1125 case CARDBUS_IO_ENABLE: /* fallthrough */ 1126 case CARDBUS_IO_DISABLE: /* fallthrough */ 1127 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1128 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1129 case CARDBUS_BM_ENABLE: /* fallthrough */ 1130 case CARDBUS_BM_DISABLE: /* fallthrough */ 1131 return pccbb_cardenable(sc, command); 1132 break; 1133 } 1134 1135 return 0; 1136 } 1137 1138 /* 1139 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1140 * This function returns true when it succeeds and returns false when 1141 * it fails. 1142 */ 1143 STATIC int 1144 pccbb_power(ct, command) 1145 cardbus_chipset_tag_t ct; 1146 int command; 1147 { 1148 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1149 1150 u_int32_t status, sock_ctrl; 1151 bus_space_tag_t memt = sc->sc_base_memt; 1152 bus_space_handle_t memh = sc->sc_base_memh; 1153 1154 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1155 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1156 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1157 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1158 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1159 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1160 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1161 "UNKNOWN", 1162 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1163 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1164 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1165 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1166 "UNKNOWN", command)); 1167 1168 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1169 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1170 1171 switch (command & CARDBUS_VCCMASK) { 1172 case CARDBUS_VCC_UC: 1173 break; 1174 case CARDBUS_VCC_5V: 1175 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1176 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1177 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1178 } else { 1179 printf("%s: BAD voltage request: no 5 V card\n", 1180 sc->sc_dev.dv_xname); 1181 } 1182 break; 1183 case CARDBUS_VCC_3V: 1184 if (CB_SOCKET_STAT_3VCARD & status) { 1185 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1186 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1187 } else { 1188 printf("%s: BAD voltage request: no 3.3 V card\n", 1189 sc->sc_dev.dv_xname); 1190 } 1191 break; 1192 case CARDBUS_VCC_0V: 1193 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1194 break; 1195 default: 1196 return 0; /* power NEVER changed */ 1197 break; 1198 } 1199 1200 switch (command & CARDBUS_VPPMASK) { 1201 case CARDBUS_VPP_UC: 1202 break; 1203 case CARDBUS_VPP_0V: 1204 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1205 break; 1206 case CARDBUS_VPP_VCC: 1207 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1208 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1209 break; 1210 case CARDBUS_VPP_12V: 1211 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1212 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1213 break; 1214 } 1215 1216 #if 0 1217 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1218 #endif 1219 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1220 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1221 1222 delay(20 * 1000); /* wait 20 ms: Vcc setup time */ 1223 /* 1224 * XXX delay 200 ms: though the standard defines that the Vcc set-up 1225 * time is 20 ms, some PC-Card bridge requires longer duration. 1226 */ 1227 delay(200 * 1000); 1228 1229 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1230 printf 1231 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1232 sc->sc_dev.dv_xname, sock_ctrl, status); 1233 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1234 (command & CARDBUS_VCCMASK) == 1235 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1236 CARDBUS_VCCMASK) == 1237 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1238 CARDBUS_VCCMASK) == 1239 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1240 CARDBUS_VCCMASK) == 1241 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1242 CARDBUS_VCCMASK) == 1243 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1244 CARDBUS_VCCMASK) == 1245 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1246 (command & CARDBUS_VPPMASK) == 1247 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1248 CARDBUS_VPPMASK) == 1249 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1250 CARDBUS_VPPMASK) == 1251 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1252 CARDBUS_VPPMASK) == 1253 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1254 #if 0 1255 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1256 u_int32_t force = 1257 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1258 /* Reset Bad Vcc request */ 1259 force &= ~CB_SOCKET_FORCE_BADVCC; 1260 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1261 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1262 CB_SOCKET_STAT)); 1263 return 1; 1264 } 1265 #endif 1266 return 0; 1267 } 1268 return 1; /* power changed correctly */ 1269 } 1270 1271 #if defined CB_PCMCIA_POLL 1272 struct cb_poll_str { 1273 void *arg; 1274 int (*func) __P((void *)); 1275 int level; 1276 pccard_chipset_tag_t ct; 1277 int count; 1278 struct callout poll_ch; 1279 }; 1280 1281 static struct cb_poll_str cb_poll[10]; 1282 static int cb_poll_n = 0; 1283 1284 static void cb_pcmcia_poll __P((void *arg)); 1285 1286 static void 1287 cb_pcmcia_poll(arg) 1288 void *arg; 1289 { 1290 struct cb_poll_str *poll = arg; 1291 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1292 struct pccbb_softc *sc = psc->cpc_parent; 1293 int s; 1294 u_int32_t spsr; /* socket present-state reg */ 1295 1296 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1297 switch (poll->level) { 1298 case IPL_NET: 1299 s = splnet(); 1300 break; 1301 case IPL_BIO: 1302 s = splbio(); 1303 break; 1304 case IPL_TTY: /* fallthrough */ 1305 default: 1306 s = spltty(); 1307 break; 1308 } 1309 1310 spsr = 1311 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1312 CB_SOCKET_STAT); 1313 1314 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1315 if (!(spsr & 0x40)) { /* CINT low */ 1316 #else 1317 if (1) { 1318 #endif 1319 if ((*poll->func) (poll->arg) == 1) { 1320 ++poll->count; 1321 printf("intr: reported from poller, 0x%x\n", spsr); 1322 #if defined LEVEL2 1323 } else { 1324 printf("intr: miss! 0x%x\n", spsr); 1325 #endif 1326 } 1327 } 1328 splx(s); 1329 } 1330 #endif /* defined CB_PCMCIA_POLL */ 1331 1332 /* 1333 * static int pccbb_detect_card(struct pccbb_softc *sc) 1334 * return value: 0 if no card exists. 1335 * 1 if 16-bit card exists. 1336 * 2 if cardbus card exists. 1337 */ 1338 static int 1339 pccbb_detect_card(sc) 1340 struct pccbb_softc *sc; 1341 { 1342 bus_space_handle_t base_memh = sc->sc_base_memh; 1343 bus_space_tag_t base_memt = sc->sc_base_memt; 1344 u_int32_t sockstat = 1345 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1346 int retval = 0; 1347 1348 /* CD1 and CD2 asserted */ 1349 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1350 /* card must be present */ 1351 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1352 /* NOTACARD DEASSERTED */ 1353 if (CB_SOCKET_STAT_CB & sockstat) { 1354 /* CardBus mode */ 1355 retval = 2; 1356 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1357 /* 16-bit mode */ 1358 retval = 1; 1359 } 1360 } 1361 } 1362 return retval; 1363 } 1364 1365 /* 1366 * STATIC int cb_reset(struct pccbb_softc *sc) 1367 * This function resets CardBus card. 1368 */ 1369 STATIC int 1370 cb_reset(sc) 1371 struct pccbb_softc *sc; 1372 { 1373 /* 1374 * Reset Assert at least 20 ms 1375 * Some machines request longer duration. 1376 */ 1377 int reset_duration = 1378 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1379 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1380 1381 /* Reset bit Assert (bit 6 at 0x3E) */ 1382 bcr |= CB_BCR_RESET_ENABLE; 1383 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1384 delay(reset_duration); 1385 1386 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1387 /* Reset bit Deassert (bit 6 at 0x3E) */ 1388 bcr &= ~CB_BCR_RESET_ENABLE; 1389 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1390 delay(reset_duration); 1391 } 1392 /* No card found on the slot. Keep Reset. */ 1393 return 1; 1394 } 1395 1396 /* 1397 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1398 * This function detect card Voltage. 1399 */ 1400 STATIC int 1401 cb_detect_voltage(sc) 1402 struct pccbb_softc *sc; 1403 { 1404 u_int32_t psr; /* socket present-state reg */ 1405 bus_space_tag_t iot = sc->sc_base_memt; 1406 bus_space_handle_t ioh = sc->sc_base_memh; 1407 int vol = PCCARD_VCC_UKN; /* set 0 */ 1408 1409 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1410 1411 if (0x400u & psr) { 1412 vol |= PCCARD_VCC_5V; 1413 } 1414 if (0x800u & psr) { 1415 vol |= PCCARD_VCC_3V; 1416 } 1417 1418 return vol; 1419 } 1420 1421 STATIC int 1422 cbbprint(aux, pcic) 1423 void *aux; 1424 const char *pcic; 1425 { 1426 /* 1427 struct cbslot_attach_args *cba = aux; 1428 1429 if (cba->cba_slot >= 0) { 1430 printf(" slot %d", cba->cba_slot); 1431 } 1432 */ 1433 return UNCONF; 1434 } 1435 1436 /* 1437 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1438 * This function enables and disables the card 1439 */ 1440 STATIC int 1441 pccbb_cardenable(sc, function) 1442 struct pccbb_softc *sc; 1443 int function; 1444 { 1445 u_int32_t command = 1446 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1447 1448 DPRINTF(("pccbb_cardenable:")); 1449 switch (function) { 1450 case CARDBUS_IO_ENABLE: 1451 command |= PCI_COMMAND_IO_ENABLE; 1452 break; 1453 case CARDBUS_IO_DISABLE: 1454 command &= ~PCI_COMMAND_IO_ENABLE; 1455 break; 1456 case CARDBUS_MEM_ENABLE: 1457 command |= PCI_COMMAND_MEM_ENABLE; 1458 break; 1459 case CARDBUS_MEM_DISABLE: 1460 command &= ~PCI_COMMAND_MEM_ENABLE; 1461 break; 1462 case CARDBUS_BM_ENABLE: 1463 command |= PCI_COMMAND_MASTER_ENABLE; 1464 break; 1465 case CARDBUS_BM_DISABLE: 1466 command &= ~PCI_COMMAND_MASTER_ENABLE; 1467 break; 1468 default: 1469 return 0; 1470 } 1471 1472 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1473 DPRINTF((" command reg 0x%x\n", command)); 1474 return 1; 1475 } 1476 1477 #if !rbus 1478 /* 1479 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1480 */ 1481 static int 1482 pccbb_io_open(ct, win, start, end) 1483 cardbus_chipset_tag_t ct; 1484 int win; 1485 u_int32_t start, end; 1486 { 1487 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1488 int basereg; 1489 int limitreg; 1490 1491 if ((win < 0) || (win > 2)) { 1492 #if defined DIAGNOSTIC 1493 printf("cardbus_io_open: window out of range %d\n", win); 1494 #endif 1495 return 0; 1496 } 1497 1498 basereg = win * 8 + 0x2c; 1499 limitreg = win * 8 + 0x30; 1500 1501 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1502 start, basereg, end, limitreg)); 1503 1504 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1505 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1506 return 1; 1507 } 1508 1509 /* 1510 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1511 */ 1512 static int 1513 pccbb_io_close(ct, win) 1514 cardbus_chipset_tag_t ct; 1515 int win; 1516 { 1517 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1518 int basereg; 1519 int limitreg; 1520 1521 if ((win < 0) || (win > 2)) { 1522 #if defined DIAGNOSTIC 1523 printf("cardbus_io_close: window out of range %d\n", win); 1524 #endif 1525 return 0; 1526 } 1527 1528 basereg = win * 8 + 0x2c; 1529 limitreg = win * 8 + 0x30; 1530 1531 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1532 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1533 return 1; 1534 } 1535 1536 /* 1537 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1538 */ 1539 static int 1540 pccbb_mem_open(ct, win, start, end) 1541 cardbus_chipset_tag_t ct; 1542 int win; 1543 u_int32_t start, end; 1544 { 1545 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1546 int basereg; 1547 int limitreg; 1548 1549 if ((win < 0) || (win > 2)) { 1550 #if defined DIAGNOSTIC 1551 printf("cardbus_mem_open: window out of range %d\n", win); 1552 #endif 1553 return 0; 1554 } 1555 1556 basereg = win * 8 + 0x1c; 1557 limitreg = win * 8 + 0x20; 1558 1559 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1560 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1561 return 1; 1562 } 1563 1564 /* 1565 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1566 */ 1567 static int 1568 pccbb_mem_close(ct, win) 1569 cardbus_chipset_tag_t ct; 1570 int win; 1571 { 1572 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1573 int basereg; 1574 int limitreg; 1575 1576 if ((win < 0) || (win > 2)) { 1577 #if defined DIAGNOSTIC 1578 printf("cardbus_mem_close: window out of range %d\n", win); 1579 #endif 1580 return 0; 1581 } 1582 1583 basereg = win * 8 + 0x1c; 1584 limitreg = win * 8 + 0x20; 1585 1586 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1587 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1588 return 1; 1589 } 1590 #endif 1591 1592 /* 1593 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1594 * int irq, 1595 * int level, 1596 * int (* func) __P((void *)), 1597 * void *arg) 1598 * 1599 * This function registers an interrupt handler at the bridge, in 1600 * order not to call the interrupt handlers of child devices when 1601 * a card-deletion interrupt occurs. 1602 * 1603 * The arguments irq and level are not used. 1604 */ 1605 static void * 1606 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1607 cardbus_chipset_tag_t ct; 1608 int irq, level; 1609 int (*func) __P((void *)); 1610 void *arg; 1611 { 1612 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1613 1614 return pccbb_intr_establish(sc, irq, level, func, arg); 1615 } 1616 1617 1618 /* 1619 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1620 * void *ih) 1621 * 1622 * This function removes an interrupt handler pointed by ih. 1623 */ 1624 static void 1625 pccbb_cb_intr_disestablish(ct, ih) 1626 cardbus_chipset_tag_t ct; 1627 void *ih; 1628 { 1629 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1630 1631 pccbb_intr_disestablish(sc, ih); 1632 } 1633 1634 1635 /* 1636 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1637 * int irq, 1638 * int level, 1639 * int (* func) __P((void *)), 1640 * void *arg) 1641 * 1642 * This function registers an interrupt handler at the bridge, in 1643 * order not to call the interrupt handlers of child devices when 1644 * a card-deletion interrupt occurs. 1645 * 1646 * The arguments irq is not used because pccbb selects intr vector. 1647 */ 1648 static void * 1649 pccbb_intr_establish(sc, irq, level, func, arg) 1650 struct pccbb_softc *sc; 1651 int irq, level; 1652 int (*func) __P((void *)); 1653 void *arg; 1654 { 1655 struct pccbb_intrhand_list *pil, *newpil; 1656 1657 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1658 1659 if (sc->sc_pil == NULL) { 1660 /* initialize bridge intr routing */ 1661 1662 switch (sc->sc_chipset) { 1663 case CB_TI113X: 1664 { 1665 pcireg_t cbctrl = 1666 pci_conf_read(sc->sc_pc, sc->sc_tag, 1667 PCI_CBCTRL); 1668 /* functional intr enabled */ 1669 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1670 pci_conf_write(sc->sc_pc, sc->sc_tag, 1671 PCI_CBCTRL, cbctrl); 1672 break; 1673 } 1674 default: 1675 break; 1676 } 1677 } 1678 1679 /* 1680 * Allocate a room for interrupt handler structure. 1681 */ 1682 if (NULL == (newpil = 1683 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1684 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1685 return NULL; 1686 } 1687 1688 newpil->pil_func = func; 1689 newpil->pil_arg = arg; 1690 newpil->pil_level = level; 1691 newpil->pil_next = NULL; 1692 1693 if (sc->sc_pil == NULL) { 1694 sc->sc_pil = newpil; 1695 } else { 1696 for (pil = sc->sc_pil; pil->pil_next != NULL; 1697 pil = pil->pil_next); 1698 pil->pil_next = newpil; 1699 } 1700 1701 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1702 1703 return newpil; 1704 } 1705 1706 /* 1707 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1708 * void *ih) 1709 * 1710 * This function removes an interrupt handler pointed by ih. 1711 */ 1712 static void 1713 pccbb_intr_disestablish(sc, ih) 1714 struct pccbb_softc *sc; 1715 void *ih; 1716 { 1717 struct pccbb_intrhand_list *pil, **pil_prev; 1718 1719 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1720 1721 pil_prev = &sc->sc_pil; 1722 1723 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1724 if (pil == ih) { 1725 *pil_prev = pil->pil_next; 1726 free(pil, M_DEVBUF); 1727 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1728 break; 1729 } 1730 pil_prev = &pil->pil_next; 1731 } 1732 1733 if (sc->sc_pil == NULL) { 1734 /* No interrupt handlers */ 1735 1736 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1737 1738 switch (sc->sc_chipset) { 1739 case CB_TI113X: 1740 { 1741 pcireg_t cbctrl = 1742 pci_conf_read(sc->sc_pc, sc->sc_tag, 1743 PCI_CBCTRL); 1744 /* functional intr disabled */ 1745 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; 1746 pci_conf_write(sc->sc_pc, sc->sc_tag, 1747 PCI_CBCTRL, cbctrl); 1748 break; 1749 } 1750 default: 1751 break; 1752 } 1753 } 1754 } 1755 1756 #if defined SHOW_REGS 1757 static void 1758 cb_show_regs(pc, tag, memt, memh) 1759 pci_chipset_tag_t pc; 1760 pcitag_t tag; 1761 bus_space_tag_t memt; 1762 bus_space_handle_t memh; 1763 { 1764 int i; 1765 printf("PCI config regs:"); 1766 for (i = 0; i < 0x50; i += 4) { 1767 if (i % 16 == 0) { 1768 printf("\n 0x%02x:", i); 1769 } 1770 printf(" %08x", pci_conf_read(pc, tag, i)); 1771 } 1772 for (i = 0x80; i < 0xb0; i += 4) { 1773 if (i % 16 == 0) { 1774 printf("\n 0x%02x:", i); 1775 } 1776 printf(" %08x", pci_conf_read(pc, tag, i)); 1777 } 1778 1779 if (memh == 0) { 1780 printf("\n"); 1781 return; 1782 } 1783 1784 printf("\nsocket regs:"); 1785 for (i = 0; i <= 0x10; i += 0x04) { 1786 printf(" %08x", bus_space_read_4(memt, memh, i)); 1787 } 1788 printf("\nExCA regs:"); 1789 for (i = 0; i < 0x08; ++i) { 1790 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1791 } 1792 printf("\n"); 1793 return; 1794 } 1795 #endif 1796 1797 /* 1798 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1799 * int busno, int devno, int function) 1800 * This is the function to make a tag to access config space of 1801 * a CardBus Card. It works same as pci_conf_read. 1802 */ 1803 static cardbustag_t 1804 pccbb_make_tag(cc, busno, devno, function) 1805 cardbus_chipset_tag_t cc; 1806 int busno, devno, function; 1807 { 1808 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1809 1810 return pci_make_tag(sc->sc_pc, busno, devno, function); 1811 } 1812 1813 static void 1814 pccbb_free_tag(cc, tag) 1815 cardbus_chipset_tag_t cc; 1816 cardbustag_t tag; 1817 { 1818 } 1819 1820 /* 1821 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1822 * cardbustag_t tag, int offset) 1823 * This is the function to read the config space of a CardBus Card. 1824 * It works same as pci_conf_read. 1825 */ 1826 static cardbusreg_t 1827 pccbb_conf_read(cc, tag, offset) 1828 cardbus_chipset_tag_t cc; 1829 cardbustag_t tag; 1830 int offset; /* register offset */ 1831 { 1832 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1833 1834 return pci_conf_read(sc->sc_pc, tag, offset); 1835 } 1836 1837 /* 1838 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1839 * int offs, cardbusreg_t val) 1840 * This is the function to write the config space of a CardBus Card. 1841 * It works same as pci_conf_write. 1842 */ 1843 static void 1844 pccbb_conf_write(cc, tag, reg, val) 1845 cardbus_chipset_tag_t cc; 1846 cardbustag_t tag; 1847 int reg; /* register offset */ 1848 cardbusreg_t val; 1849 { 1850 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1851 1852 pci_conf_write(sc->sc_pc, tag, reg, val); 1853 } 1854 1855 #if 0 1856 STATIC int 1857 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1858 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1859 int speed, int flags, 1860 bus_space_handle_t * iohp) 1861 #endif 1862 /* 1863 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1864 * bus_addr_t start, bus_size_t size, 1865 * bus_size_t align, 1866 * struct pcmcia_io_handle *pcihp 1867 * 1868 * This function only allocates I/O region for pccard. This function 1869 * never maps the allocated region to pccard I/O area. 1870 * 1871 * XXX: The interface of this function is not very good, I believe. 1872 */ 1873 STATIC int 1874 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1875 pcmcia_chipset_handle_t pch; 1876 bus_addr_t start; /* start address */ 1877 bus_size_t size; 1878 bus_size_t align; 1879 struct pcmcia_io_handle *pcihp; 1880 { 1881 struct pcic_handle *ph = (struct pcic_handle *)pch; 1882 bus_addr_t ioaddr; 1883 int flags = 0; 1884 bus_space_tag_t iot; 1885 bus_space_handle_t ioh; 1886 #if rbus 1887 rbus_tag_t rb; 1888 #endif 1889 if (align == 0) { 1890 align = size; /* XXX: funny??? */ 1891 } 1892 1893 /* 1894 * Allocate some arbitrary I/O space. 1895 */ 1896 1897 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1898 1899 #if rbus 1900 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1901 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1902 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1903 return 1; 1904 } 1905 #else 1906 if (start) { 1907 ioaddr = start; 1908 if (bus_space_map(iot, start, size, 0, &ioh)) { 1909 return 1; 1910 } 1911 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1912 (u_long) ioaddr, (u_long) size)); 1913 } else { 1914 flags |= PCMCIA_IO_ALLOCATED; 1915 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1916 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1917 size, align, 0, 0, &ioaddr, &ioh)) { 1918 /* No room be able to be get. */ 1919 return 1; 1920 } 1921 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1922 (u_long) ioaddr, (u_long) size)); 1923 } 1924 #endif 1925 1926 pcihp->iot = iot; 1927 pcihp->ioh = ioh; 1928 pcihp->addr = ioaddr; 1929 pcihp->size = size; 1930 pcihp->flags = flags; 1931 1932 return 0; 1933 } 1934 1935 /* 1936 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1937 * struct pcmcia_io_handle *pcihp) 1938 * 1939 * This function only frees I/O region for pccard. 1940 * 1941 * XXX: The interface of this function is not very good, I believe. 1942 */ 1943 void 1944 pccbb_pcmcia_io_free(pch, pcihp) 1945 pcmcia_chipset_handle_t pch; 1946 struct pcmcia_io_handle *pcihp; 1947 { 1948 #if !rbus 1949 bus_space_tag_t iot = pcihp->iot; 1950 #endif 1951 bus_space_handle_t ioh = pcihp->ioh; 1952 bus_size_t size = pcihp->size; 1953 1954 #if rbus 1955 struct pccbb_softc *sc = 1956 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1957 rbus_tag_t rb = sc->sc_rbus_iot; 1958 1959 rbus_space_free(rb, ioh, size, NULL); 1960 #else 1961 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1962 bus_space_free(iot, ioh, size); 1963 else 1964 bus_space_unmap(iot, ioh, size); 1965 #endif 1966 } 1967 1968 /* 1969 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1970 * bus_addr_t offset, bus_size_t size, 1971 * struct pcmcia_io_handle *pcihp, 1972 * int *windowp) 1973 * 1974 * This function maps the allocated I/O region to pccard. This function 1975 * never allocates any I/O region for pccard I/O area. I don't 1976 * understand why the original authors of pcmciabus separated alloc and 1977 * map. I believe the two must be unite. 1978 * 1979 * XXX: no wait timing control? 1980 */ 1981 int 1982 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1983 pcmcia_chipset_handle_t pch; 1984 int width; 1985 bus_addr_t offset; 1986 bus_size_t size; 1987 struct pcmcia_io_handle *pcihp; 1988 int *windowp; 1989 { 1990 struct pcic_handle *ph = (struct pcic_handle *)pch; 1991 bus_addr_t ioaddr = pcihp->addr + offset; 1992 int i, win; 1993 #if defined CBB_DEBUG 1994 static char *width_names[] = { "dynamic", "io8", "io16" }; 1995 #endif 1996 1997 /* Sanity check I/O handle. */ 1998 1999 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2000 panic("pccbb_pcmcia_io_map iot is bogus"); 2001 } 2002 2003 /* XXX Sanity check offset/size. */ 2004 2005 win = -1; 2006 for (i = 0; i < PCIC_IO_WINS; i++) { 2007 if ((ph->ioalloc & (1 << i)) == 0) { 2008 win = i; 2009 ph->ioalloc |= (1 << i); 2010 break; 2011 } 2012 } 2013 2014 if (win == -1) { 2015 return 1; 2016 } 2017 2018 *windowp = win; 2019 2020 /* XXX this is pretty gross */ 2021 2022 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2023 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2024 2025 /* XXX wtf is this doing here? */ 2026 2027 #if 0 2028 printf(" port 0x%lx", (u_long) ioaddr); 2029 if (size > 1) { 2030 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2031 } 2032 #endif 2033 2034 ph->io[win].addr = ioaddr; 2035 ph->io[win].size = size; 2036 ph->io[win].width = width; 2037 2038 /* actual dirty register-value changing in the function below. */ 2039 pccbb_pcmcia_do_io_map(ph, win); 2040 2041 return 0; 2042 } 2043 2044 /* 2045 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2046 * 2047 * This function changes register-value to map I/O region for pccard. 2048 */ 2049 static void 2050 pccbb_pcmcia_do_io_map(ph, win) 2051 struct pcic_handle *ph; 2052 int win; 2053 { 2054 static u_int8_t pcic_iowidth[3] = { 2055 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2056 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2057 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2058 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2059 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2060 }; 2061 2062 #define PCIC_SIA_START_LOW 0 2063 #define PCIC_SIA_START_HIGH 1 2064 #define PCIC_SIA_STOP_LOW 2 2065 #define PCIC_SIA_STOP_HIGH 3 2066 2067 int regbase_win = 0x8 + win * 0x04; 2068 u_int8_t ioctl, enable; 2069 2070 DPRINTF( 2071 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2072 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2073 ph->io[win].width * 8)); 2074 2075 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2076 ph->io[win].addr & 0xff); 2077 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2078 (ph->io[win].addr >> 8) & 0xff); 2079 2080 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2081 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2082 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2083 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2084 2085 ioctl = Pcic_read(ph, PCIC_IOCTL); 2086 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2087 switch (win) { 2088 case 0: 2089 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2090 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2091 PCIC_IOCTL_IO0_DATASIZE_MASK); 2092 ioctl |= pcic_iowidth[ph->io[win].width]; 2093 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2094 break; 2095 case 1: 2096 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2097 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2098 PCIC_IOCTL_IO1_DATASIZE_MASK); 2099 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2100 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2101 break; 2102 } 2103 Pcic_write(ph, PCIC_IOCTL, ioctl); 2104 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2105 #if defined CBB_DEBUG 2106 { 2107 u_int8_t start_low = 2108 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2109 u_int8_t start_high = 2110 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2111 u_int8_t stop_low = 2112 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2113 u_int8_t stop_high = 2114 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2115 printf 2116 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2117 start_low, start_high, stop_low, stop_high, ioctl, enable); 2118 } 2119 #endif 2120 } 2121 2122 /* 2123 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2124 * 2125 * This function unmaps I/O region. No return value. 2126 */ 2127 STATIC void 2128 pccbb_pcmcia_io_unmap(pch, win) 2129 pcmcia_chipset_handle_t pch; 2130 int win; 2131 { 2132 struct pcic_handle *ph = (struct pcic_handle *)pch; 2133 int reg; 2134 2135 if (win >= PCIC_IO_WINS || win < 0) { 2136 panic("pccbb_pcmcia_io_unmap: window out of range"); 2137 } 2138 2139 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2140 switch (win) { 2141 case 0: 2142 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2143 break; 2144 case 1: 2145 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2146 break; 2147 } 2148 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2149 2150 ph->ioalloc &= ~(1 << win); 2151 } 2152 2153 /* 2154 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2155 * 2156 * This function enables the card. All information is stored in 2157 * the first argument, pcmcia_chipset_handle_t. 2158 */ 2159 static void 2160 pccbb_pcmcia_wait_ready(ph) 2161 struct pcic_handle *ph; 2162 { 2163 int i; 2164 2165 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2166 Pcic_read(ph, PCIC_IF_STATUS))); 2167 2168 for (i = 0; i < 10000; i++) { 2169 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2170 return; 2171 } 2172 delay(500); 2173 #ifdef CBB_DEBUG 2174 if ((i > 5000) && (i % 100 == 99)) 2175 printf("."); 2176 #endif 2177 } 2178 2179 #ifdef DIAGNOSTIC 2180 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2181 Pcic_read(ph, PCIC_IF_STATUS)); 2182 #endif 2183 } 2184 2185 /* 2186 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2187 * 2188 * This function enables the card. All information is stored in 2189 * the first argument, pcmcia_chipset_handle_t. 2190 */ 2191 STATIC void 2192 pccbb_pcmcia_socket_enable(pch) 2193 pcmcia_chipset_handle_t pch; 2194 { 2195 struct pcic_handle *ph = (struct pcic_handle *)pch; 2196 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2197 int cardtype, win; 2198 u_int8_t power, intr; 2199 pcireg_t spsr; 2200 int voltage; 2201 2202 /* this bit is mostly stolen from pcic_attach_card */ 2203 2204 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2205 2206 /* get card Vcc info */ 2207 2208 spsr = 2209 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2210 CB_SOCKET_STAT); 2211 if (spsr & CB_SOCKET_STAT_5VCARD) { 2212 DPRINTF(("5V card\n")); 2213 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2214 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2215 DPRINTF(("3V card\n")); 2216 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2217 } else { 2218 printf("?V card, 0x%x\n", spsr); /* XXX */ 2219 return; 2220 } 2221 2222 /* assert reset bit */ 2223 intr = Pcic_read(ph, PCIC_INTR); 2224 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2225 Pcic_write(ph, PCIC_INTR, intr); 2226 2227 /* disable socket i/o: negate output enable bit */ 2228 2229 power = Pcic_read(ph, PCIC_PWRCTL); 2230 power &= ~PCIC_PWRCTL_OE; 2231 Pcic_write(ph, PCIC_PWRCTL, power); 2232 2233 /* power down the socket to reset it, clear the card reset pin */ 2234 2235 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2236 2237 /* 2238 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2239 * we are changing Vcc (Toff). 2240 */ 2241 /* delay(300*1000); too much */ 2242 2243 /* power up the socket */ 2244 pccbb_power(sc, voltage); 2245 2246 /* 2247 * wait 100ms until power raise (Tpr) and 20ms to become 2248 * stable (Tsu(Vcc)). 2249 * 2250 * some machines require some more time to be settled 2251 * (another 200ms is added here). 2252 */ 2253 /* delay((100 + 20 + 200)*1000); too much */ 2254 2255 power = Pcic_read(ph, PCIC_PWRCTL); 2256 power |= PCIC_PWRCTL_OE; 2257 Pcic_write(ph, PCIC_PWRCTL, power); 2258 2259 /* 2260 * hold RESET at least 10us. 2261 */ 2262 delay(10); 2263 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2264 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2265 2266 /* clear the reset flag */ 2267 2268 intr |= PCIC_INTR_RESET; 2269 Pcic_write(ph, PCIC_INTR, intr); 2270 2271 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2272 2273 delay(20000); 2274 2275 /* wait for the chip to finish initializing */ 2276 2277 pccbb_pcmcia_wait_ready(ph); 2278 2279 /* zero out the address windows */ 2280 2281 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2282 2283 /* set the card type */ 2284 2285 cardtype = pcmcia_card_gettype(ph->pcmcia); 2286 2287 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2288 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2289 Pcic_write(ph, PCIC_INTR, intr); 2290 2291 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2292 ph->ph_parent->dv_xname, ph->sock, 2293 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2294 2295 /* reinstall all the memory and io mappings */ 2296 2297 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2298 if (ph->memalloc & (1 << win)) { 2299 pccbb_pcmcia_do_mem_map(ph, win); 2300 } 2301 } 2302 2303 for (win = 0; win < PCIC_IO_WINS; ++win) { 2304 if (ph->ioalloc & (1 << win)) { 2305 pccbb_pcmcia_do_io_map(ph, win); 2306 } 2307 } 2308 } 2309 2310 /* 2311 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2312 * 2313 * This function disables the card. All information is stored in 2314 * the first argument, pcmcia_chipset_handle_t. 2315 */ 2316 STATIC void 2317 pccbb_pcmcia_socket_disable(pch) 2318 pcmcia_chipset_handle_t pch; 2319 { 2320 struct pcic_handle *ph = (struct pcic_handle *)pch; 2321 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2322 u_int8_t power, intr; 2323 2324 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2325 2326 /* reset signal asserting... */ 2327 2328 intr = Pcic_read(ph, PCIC_INTR); 2329 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2330 Pcic_write(ph, PCIC_INTR, intr); 2331 delay(2 * 1000); 2332 2333 /* power down the socket */ 2334 power = Pcic_read(ph, PCIC_PWRCTL); 2335 power &= ~PCIC_PWRCTL_OE; 2336 Pcic_write(ph, PCIC_PWRCTL, power); 2337 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2338 /* 2339 * wait 300ms until power fails (Tpf). 2340 */ 2341 delay(300 * 1000); 2342 } 2343 2344 /* 2345 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2346 * 2347 * This function detects whether a card is in the slot or not. 2348 * If a card is inserted, return 1. Otherwise, return 0. 2349 */ 2350 STATIC int 2351 pccbb_pcmcia_card_detect(pch) 2352 pcmcia_chipset_handle_t pch; 2353 { 2354 struct pcic_handle *ph = (struct pcic_handle *)pch; 2355 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2356 2357 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2358 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2359 } 2360 2361 #if 0 2362 STATIC int 2363 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2364 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2365 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2366 #endif 2367 /* 2368 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2369 * bus_size_t size, 2370 * struct pcmcia_mem_handle *pcmhp) 2371 * 2372 * This function only allocates memory region for pccard. This 2373 * function never maps the allocated region to pccard memory area. 2374 * 2375 * XXX: Why the argument of start address is not in? 2376 */ 2377 STATIC int 2378 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2379 pcmcia_chipset_handle_t pch; 2380 bus_size_t size; 2381 struct pcmcia_mem_handle *pcmhp; 2382 { 2383 struct pcic_handle *ph = (struct pcic_handle *)pch; 2384 bus_space_handle_t memh; 2385 bus_addr_t addr; 2386 bus_size_t sizepg; 2387 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2388 #if rbus 2389 rbus_tag_t rb; 2390 #endif 2391 2392 /* out of sc->memh, allocate as many pages as necessary */ 2393 2394 /* convert size to PCIC pages */ 2395 /* 2396 * This is not enough; when the requested region is on the page 2397 * boundaries, this may calculate wrong result. 2398 */ 2399 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2400 #if 0 2401 if (sizepg > PCIC_MAX_MEM_PAGES) { 2402 return 1; 2403 } 2404 #endif 2405 2406 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2407 return 1; 2408 } 2409 2410 addr = 0; /* XXX gcc -Wuninitialized */ 2411 2412 #if rbus 2413 rb = sc->sc_rbus_memt; 2414 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2415 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2416 &addr, &memh)) { 2417 return 1; 2418 } 2419 #else 2420 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2421 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2422 0, /* boundary */ 2423 0, /* flags */ 2424 &addr, &memh)) { 2425 return 1; 2426 } 2427 #endif 2428 2429 DPRINTF( 2430 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2431 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2432 2433 pcmhp->memt = sc->sc_memt; 2434 pcmhp->memh = memh; 2435 pcmhp->addr = addr; 2436 pcmhp->size = size; 2437 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2438 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2439 pcmhp->mhandle = 0; 2440 /* No offset??? Funny. */ 2441 2442 return 0; 2443 } 2444 2445 /* 2446 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2447 * struct pcmcia_mem_handle *pcmhp) 2448 * 2449 * This function release the memory space allocated by the function 2450 * pccbb_pcmcia_mem_alloc(). 2451 */ 2452 STATIC void 2453 pccbb_pcmcia_mem_free(pch, pcmhp) 2454 pcmcia_chipset_handle_t pch; 2455 struct pcmcia_mem_handle *pcmhp; 2456 { 2457 #if rbus 2458 struct pcic_handle *ph = (struct pcic_handle *)pch; 2459 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2460 2461 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2462 #else 2463 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2464 #endif 2465 } 2466 2467 /* 2468 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2469 * 2470 * This function release the memory space allocated by the function 2471 * pccbb_pcmcia_mem_alloc(). 2472 */ 2473 STATIC void 2474 pccbb_pcmcia_do_mem_map(ph, win) 2475 struct pcic_handle *ph; 2476 int win; 2477 { 2478 int regbase_win; 2479 bus_addr_t phys_addr; 2480 bus_addr_t phys_end; 2481 2482 #define PCIC_SMM_START_LOW 0 2483 #define PCIC_SMM_START_HIGH 1 2484 #define PCIC_SMM_STOP_LOW 2 2485 #define PCIC_SMM_STOP_HIGH 3 2486 #define PCIC_CMA_LOW 4 2487 #define PCIC_CMA_HIGH 5 2488 2489 u_int8_t start_low, start_high = 0; 2490 u_int8_t stop_low, stop_high; 2491 u_int8_t off_low, off_high; 2492 u_int8_t mem_window; 2493 int reg; 2494 2495 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2496 int mem8 = 2497 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2498 || (kind == PCMCIA_MEM_ATTR); 2499 2500 regbase_win = 0x10 + win * 0x08; 2501 2502 phys_addr = ph->mem[win].addr; 2503 phys_end = phys_addr + ph->mem[win].size; 2504 2505 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2506 phys_addr, phys_end, ph->mem[win].offset)); 2507 2508 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2509 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2510 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2511 2512 /* bit 19:12 */ 2513 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2514 /* bit 23:20 and bit 7 on */ 2515 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2516 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2517 /* bit 31:24, for 32-bit address */ 2518 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2519 2520 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2521 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2522 2523 if (((struct pccbb_softc *)ph-> 2524 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2525 Pcic_write(ph, 0x40 + win, mem_window); 2526 } 2527 2528 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2529 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2530 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2531 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2532 2533 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2534 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2535 2536 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2537 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2538 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2539 | ((kind == PCMCIA_MEM_ATTR) ? 2540 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2541 2542 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2543 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2544 2545 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2546 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2547 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2548 2549 #if defined CBB_DEBUG 2550 { 2551 int r1, r2, r3, r4, r5, r6, r7 = 0; 2552 2553 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2554 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2555 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2556 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2557 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2558 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2559 if (((struct pccbb_softc *)(ph-> 2560 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2561 r7 = Pcic_read(ph, 0x40 + win); 2562 } 2563 2564 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2565 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2566 if (((struct pccbb_softc *)(ph-> 2567 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2568 DPRINTF((" %02x", r7)); 2569 } 2570 DPRINTF(("\n")); 2571 } 2572 #endif 2573 } 2574 2575 /* 2576 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2577 * bus_addr_t card_addr, bus_size_t size, 2578 * struct pcmcia_mem_handle *pcmhp, 2579 * bus_addr_t *offsetp, int *windowp) 2580 * 2581 * This function maps memory space allocated by the function 2582 * pccbb_pcmcia_mem_alloc(). 2583 */ 2584 STATIC int 2585 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2586 pcmcia_chipset_handle_t pch; 2587 int kind; 2588 bus_addr_t card_addr; 2589 bus_size_t size; 2590 struct pcmcia_mem_handle *pcmhp; 2591 bus_addr_t *offsetp; 2592 int *windowp; 2593 { 2594 struct pcic_handle *ph = (struct pcic_handle *)pch; 2595 bus_addr_t busaddr; 2596 long card_offset; 2597 int win; 2598 2599 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2600 if ((ph->memalloc & (1 << win)) == 0) { 2601 ph->memalloc |= (1 << win); 2602 break; 2603 } 2604 } 2605 2606 if (win == PCIC_MEM_WINS) { 2607 return 1; 2608 } 2609 2610 *windowp = win; 2611 2612 /* XXX this is pretty gross */ 2613 2614 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2615 panic("pccbb_pcmcia_mem_map memt is bogus"); 2616 } 2617 2618 busaddr = pcmhp->addr; 2619 2620 /* 2621 * compute the address offset to the pcmcia address space for the 2622 * pcic. this is intentionally signed. The masks and shifts below 2623 * will cause TRT to happen in the pcic registers. Deal with making 2624 * sure the address is aligned, and return the alignment offset. 2625 */ 2626 2627 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2628 card_addr -= *offsetp; 2629 2630 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2631 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2632 (u_long) card_addr)); 2633 2634 /* 2635 * include the offset in the size, and decrement size by one, since 2636 * the hw wants start/stop 2637 */ 2638 size += *offsetp - 1; 2639 2640 card_offset = (((long)card_addr) - ((long)busaddr)); 2641 2642 ph->mem[win].addr = busaddr; 2643 ph->mem[win].size = size; 2644 ph->mem[win].offset = card_offset; 2645 ph->mem[win].kind = kind; 2646 2647 pccbb_pcmcia_do_mem_map(ph, win); 2648 2649 return 0; 2650 } 2651 2652 /* 2653 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2654 * int window) 2655 * 2656 * This function unmaps memory space which mapped by the function 2657 * pccbb_pcmcia_mem_map(). 2658 */ 2659 STATIC void 2660 pccbb_pcmcia_mem_unmap(pch, window) 2661 pcmcia_chipset_handle_t pch; 2662 int window; 2663 { 2664 struct pcic_handle *ph = (struct pcic_handle *)pch; 2665 int reg; 2666 2667 if (window >= PCIC_MEM_WINS) { 2668 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2669 } 2670 2671 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2672 reg &= ~(1 << window); 2673 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2674 2675 ph->memalloc &= ~(1 << window); 2676 } 2677 2678 #if defined PCCBB_PCMCIA_POLL 2679 struct pccbb_poll_str { 2680 void *arg; 2681 int (*func) __P((void *)); 2682 int level; 2683 struct pcic_handle *ph; 2684 int count; 2685 int num; 2686 struct callout poll_ch; 2687 }; 2688 2689 static struct pccbb_poll_str pccbb_poll[10]; 2690 static int pccbb_poll_n = 0; 2691 2692 static void pccbb_pcmcia_poll __P((void *arg)); 2693 2694 static void 2695 pccbb_pcmcia_poll(arg) 2696 void *arg; 2697 { 2698 struct pccbb_poll_str *poll = arg; 2699 struct pcic_handle *ph = poll->ph; 2700 struct pccbb_softc *sc = ph->sc; 2701 int s; 2702 u_int32_t spsr; /* socket present-state reg */ 2703 2704 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2705 switch (poll->level) { 2706 case IPL_NET: 2707 s = splnet(); 2708 break; 2709 case IPL_BIO: 2710 s = splbio(); 2711 break; 2712 case IPL_TTY: /* fallthrough */ 2713 default: 2714 s = spltty(); 2715 break; 2716 } 2717 2718 spsr = 2719 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2720 CB_SOCKET_STAT); 2721 2722 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2723 if (!(spsr & 0x40)) /* CINT low */ 2724 #else 2725 if (1) 2726 #endif 2727 { 2728 if ((*poll->func) (poll->arg) > 0) { 2729 ++poll->count; 2730 // printf("intr: reported from poller, 0x%x\n", spsr); 2731 #if defined LEVEL2 2732 } else { 2733 printf("intr: miss! 0x%x\n", spsr); 2734 #endif 2735 } 2736 } 2737 splx(s); 2738 } 2739 #endif /* defined CB_PCMCIA_POLL */ 2740 2741 /* 2742 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2743 * struct pcmcia_function *pf, 2744 * int ipl, 2745 * int (*func)(void *), 2746 * void *arg); 2747 * 2748 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2749 */ 2750 STATIC void * 2751 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2752 pcmcia_chipset_handle_t pch; 2753 struct pcmcia_function *pf; 2754 int ipl; 2755 int (*func) __P((void *)); 2756 void *arg; 2757 { 2758 struct pcic_handle *ph = (struct pcic_handle *)pch; 2759 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2760 2761 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2762 /* what should I do? */ 2763 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2764 DPRINTF( 2765 ("%s does not provide edge nor pulse interrupt\n", 2766 sc->sc_dev.dv_xname)); 2767 return NULL; 2768 } 2769 /* 2770 * XXX Noooooo! The interrupt flag must set properly!! 2771 * dumb pcmcia driver!! 2772 */ 2773 } 2774 2775 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2776 } 2777 2778 /* 2779 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2780 * void *ih) 2781 * 2782 * This function disables PC-Card interrupt. 2783 */ 2784 STATIC void 2785 pccbb_pcmcia_intr_disestablish(pch, ih) 2786 pcmcia_chipset_handle_t pch; 2787 void *ih; 2788 { 2789 struct pcic_handle *ph = (struct pcic_handle *)pch; 2790 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2791 2792 pccbb_intr_disestablish(sc, ih); 2793 } 2794 2795 #if rbus 2796 /* 2797 * static int 2798 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2799 * bus_addr_t addr, bus_size_t size, 2800 * bus_addr_t mask, bus_size_t align, 2801 * int flags, bus_addr_t *addrp; 2802 * bus_space_handle_t *bshp) 2803 * 2804 * This function allocates a portion of memory or io space for 2805 * clients. This function is called from CardBus card drivers. 2806 */ 2807 static int 2808 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2809 cardbus_chipset_tag_t ct; 2810 rbus_tag_t rb; 2811 bus_addr_t addr; 2812 bus_size_t size; 2813 bus_addr_t mask; 2814 bus_size_t align; 2815 int flags; 2816 bus_addr_t *addrp; 2817 bus_space_handle_t *bshp; 2818 { 2819 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2820 2821 DPRINTF( 2822 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2823 addr, size, mask, align)); 2824 2825 if (align == 0) { 2826 align = size; 2827 } 2828 2829 if (rb->rb_bt == sc->sc_memt) { 2830 if (align < 16) { 2831 return 1; 2832 } 2833 } else if (rb->rb_bt == sc->sc_iot) { 2834 if (align < 4) { 2835 return 1; 2836 } 2837 /* XXX: hack for avoiding ISA image */ 2838 if (mask < 0x0100) { 2839 mask = 0x3ff; 2840 addr = 0x300; 2841 } 2842 2843 } else { 2844 DPRINTF( 2845 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2846 rb->rb_bt)); 2847 return 1; 2848 /* XXX: panic here? */ 2849 } 2850 2851 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2852 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2853 return 1; 2854 } 2855 2856 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2857 2858 return 0; 2859 } 2860 2861 /* 2862 * static int 2863 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2864 * bus_space_handle_t *bshp, bus_size_t size); 2865 * 2866 * This function is called from CardBus card drivers. 2867 */ 2868 static int 2869 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2870 cardbus_chipset_tag_t ct; 2871 rbus_tag_t rb; 2872 bus_space_handle_t bsh; 2873 bus_size_t size; 2874 { 2875 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2876 bus_space_tag_t bt = rb->rb_bt; 2877 2878 pccbb_close_win(sc, bt, bsh, size); 2879 2880 if (bt == sc->sc_memt) { 2881 } else if (bt == sc->sc_iot) { 2882 } else { 2883 return 1; 2884 /* XXX: panic here? */ 2885 } 2886 2887 return rbus_space_free(rb, bsh, size, NULL); 2888 } 2889 #endif /* rbus */ 2890 2891 #if rbus 2892 2893 static int 2894 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2895 struct pccbb_softc *sc; 2896 bus_space_tag_t bst; 2897 bus_addr_t addr; 2898 bus_size_t size; 2899 bus_space_handle_t bsh; 2900 int flags; 2901 { 2902 struct pccbb_win_chain_head *head; 2903 bus_addr_t align; 2904 2905 head = &sc->sc_iowindow; 2906 align = 0x04; 2907 if (sc->sc_memt == bst) { 2908 head = &sc->sc_memwindow; 2909 align = 0x1000; 2910 DPRINTF(("using memory window, %x %x %x\n\n", 2911 sc->sc_iot, sc->sc_memt, bst)); 2912 } 2913 2914 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2915 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2916 sc->sc_dev.dv_xname, 2917 (head == &sc->sc_memwindow) ? "mem" : "io"); 2918 } 2919 pccbb_winset(align, sc, bst); 2920 2921 return 0; 2922 } 2923 2924 static int 2925 pccbb_close_win(sc, bst, bsh, size) 2926 struct pccbb_softc *sc; 2927 bus_space_tag_t bst; 2928 bus_space_handle_t bsh; 2929 bus_size_t size; 2930 { 2931 struct pccbb_win_chain_head *head; 2932 bus_addr_t align; 2933 2934 head = &sc->sc_iowindow; 2935 align = 0x04; 2936 if (sc->sc_memt == bst) { 2937 head = &sc->sc_memwindow; 2938 align = 0x1000; 2939 } 2940 2941 if (pccbb_winlist_delete(head, bsh, size)) { 2942 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2943 sc->sc_dev.dv_xname, 2944 (head == &sc->sc_memwindow) ? "mem" : "io"); 2945 } 2946 pccbb_winset(align, sc, bst); 2947 2948 return 0; 2949 } 2950 2951 static int 2952 pccbb_winlist_insert(head, start, size, bsh, flags) 2953 struct pccbb_win_chain_head *head; 2954 bus_addr_t start; 2955 bus_size_t size; 2956 bus_space_handle_t bsh; 2957 int flags; 2958 { 2959 struct pccbb_win_chain *chainp, *elem; 2960 2961 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2962 M_NOWAIT)) == NULL) 2963 return (1); /* fail */ 2964 2965 elem->wc_start = start; 2966 elem->wc_end = start + (size - 1); 2967 elem->wc_handle = bsh; 2968 elem->wc_flags = flags; 2969 2970 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2971 chainp = TAILQ_NEXT(chainp, wc_list)) { 2972 if (chainp->wc_end < start) 2973 continue; 2974 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2975 return (0); 2976 } 2977 2978 TAILQ_INSERT_TAIL(head, elem, wc_list); 2979 return (0); 2980 } 2981 2982 static int 2983 pccbb_winlist_delete(head, bsh, size) 2984 struct pccbb_win_chain_head *head; 2985 bus_space_handle_t bsh; 2986 bus_size_t size; 2987 { 2988 struct pccbb_win_chain *chainp; 2989 2990 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2991 chainp = TAILQ_NEXT(chainp, wc_list)) { 2992 if (chainp->wc_handle != bsh) 2993 continue; 2994 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2995 printf("pccbb_winlist_delete: window 0x%lx size " 2996 "inconsistent: 0x%lx, 0x%lx\n", 2997 chainp->wc_start, 2998 chainp->wc_end - chainp->wc_start, 2999 size - 1); 3000 return 1; 3001 } 3002 3003 TAILQ_REMOVE(head, chainp, wc_list); 3004 free(chainp, M_DEVBUF); 3005 3006 return 0; 3007 } 3008 3009 return 1; /* fail: no candidate to remove */ 3010 } 3011 3012 static void 3013 pccbb_winset(align, sc, bst) 3014 bus_addr_t align; 3015 struct pccbb_softc *sc; 3016 bus_space_tag_t bst; 3017 { 3018 pci_chipset_tag_t pc; 3019 pcitag_t tag; 3020 bus_addr_t mask = ~(align - 1); 3021 struct { 3022 cardbusreg_t win_start; 3023 cardbusreg_t win_limit; 3024 int win_flags; 3025 } win[2]; 3026 struct pccbb_win_chain *chainp; 3027 int offs; 3028 3029 win[0].win_start = 0xffffffff; 3030 win[0].win_limit = 0; 3031 win[1].win_start = 0xffffffff; 3032 win[1].win_limit = 0; 3033 3034 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3035 offs = 0x2c; 3036 if (sc->sc_memt == bst) { 3037 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3038 offs = 0x1c; 3039 } 3040 3041 if (chainp != NULL) { 3042 win[0].win_start = chainp->wc_start & mask; 3043 win[0].win_limit = chainp->wc_end & mask; 3044 win[0].win_flags = chainp->wc_flags; 3045 chainp = TAILQ_NEXT(chainp, wc_list); 3046 } 3047 3048 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3049 if (win[1].win_start == 0xffffffff) { 3050 /* window 1 is not used */ 3051 if ((win[0].win_flags == chainp->wc_flags) && 3052 (win[0].win_limit + align >= 3053 (chainp->wc_start & mask))) { 3054 /* concatenate */ 3055 win[0].win_limit = chainp->wc_end & mask; 3056 } else { 3057 /* make new window */ 3058 win[1].win_start = chainp->wc_start & mask; 3059 win[1].win_limit = chainp->wc_end & mask; 3060 win[1].win_flags = chainp->wc_flags; 3061 } 3062 continue; 3063 } 3064 3065 /* Both windows are engaged. */ 3066 if (win[0].win_flags == win[1].win_flags) { 3067 /* same flags */ 3068 if (win[0].win_flags == chainp->wc_flags) { 3069 if (win[1].win_start - (win[0].win_limit + 3070 align) < 3071 (chainp->wc_start & mask) - 3072 ((chainp->wc_end & mask) + align)) { 3073 /* 3074 * merge window 0 and 1, and set win1 3075 * to chainp 3076 */ 3077 win[0].win_limit = win[1].win_limit; 3078 win[1].win_start = 3079 chainp->wc_start & mask; 3080 win[1].win_limit = 3081 chainp->wc_end & mask; 3082 } else { 3083 win[1].win_limit = 3084 chainp->wc_end & mask; 3085 } 3086 } else { 3087 /* different flags */ 3088 3089 /* concatenate win0 and win1 */ 3090 win[0].win_limit = win[1].win_limit; 3091 /* allocate win[1] to new space */ 3092 win[1].win_start = chainp->wc_start & mask; 3093 win[1].win_limit = chainp->wc_end & mask; 3094 win[1].win_flags = chainp->wc_flags; 3095 } 3096 } else { 3097 /* the flags of win[0] and win[1] is different */ 3098 if (win[0].win_flags == chainp->wc_flags) { 3099 win[0].win_limit = chainp->wc_end & mask; 3100 /* 3101 * XXX this creates overlapping windows, so 3102 * what should the poor bridge do if one is 3103 * cachable, and the other is not? 3104 */ 3105 printf("%s: overlapping windows\n", 3106 sc->sc_dev.dv_xname); 3107 } else { 3108 win[1].win_limit = chainp->wc_end & mask; 3109 } 3110 } 3111 } 3112 3113 pc = sc->sc_pc; 3114 tag = sc->sc_tag; 3115 pci_conf_write(pc, tag, offs, win[0].win_start); 3116 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3117 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3118 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3119 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3120 pci_conf_read(pc, tag, offs), 3121 pci_conf_read(pc, tag, offs + 4) + align, 3122 pci_conf_read(pc, tag, offs + 8), 3123 pci_conf_read(pc, tag, offs + 12) + align)); 3124 3125 if (bst == sc->sc_memt) { 3126 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3127 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3128 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3129 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3130 } 3131 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3132 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3133 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3134 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3135 } 3136 } 3137 } 3138 3139 #endif /* rbus */ 3140 3141 static void 3142 pccbb_powerhook(why, arg) 3143 int why; 3144 void *arg; 3145 { 3146 struct pccbb_softc *sc = arg; 3147 u_int32_t reg; 3148 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3149 bus_space_handle_t base_memh = sc->sc_base_memh; 3150 3151 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3152 3153 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3154 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3155 if (sc->sc_pil_intr_enable) { 3156 (void)pccbbintr_function(sc); 3157 } 3158 sc->sc_pil_intr_enable = 0; 3159 3160 /* ToDo: deactivate or suspend child devices */ 3161 3162 } 3163 3164 if (why == PWR_RESUME) { 3165 /* CSC Interrupt: Card detect interrupt on */ 3166 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3167 /* Card detect intr is turned on. */ 3168 reg |= CB_SOCKET_MASK_CD; 3169 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3170 /* reset interrupt */ 3171 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3172 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3173 3174 /* 3175 * check for card insertion or removal during suspend period. 3176 * XXX: the code can't cope with card swap (remove then 3177 * insert). how can we detect such situation? 3178 */ 3179 (void)pccbbintr(sc); 3180 3181 sc->sc_pil_intr_enable = 1; 3182 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3183 3184 /* ToDo: activate or wakeup child devices */ 3185 } 3186 } 3187
Indexes created Fri Sep 26 08:10:20 GMT 2025