pccbb.c revision 1.48
1 /* $NetBSD: pccbb.c,v 1.48 2000/11/28 09:11:36 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 93 void pccbbattach __P((struct device *, struct device *, void *)); 94 int pccbbintr __P((void *)); 95 static void pci113x_insert __P((void *)); 96 static int pccbbintr_function __P((struct pccbb_softc *)); 97 98 static int pccbb_detect_card __P((struct pccbb_softc *)); 99 100 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 101 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 102 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 103 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 104 105 STATIC int cb_reset __P((struct pccbb_softc *)); 106 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 107 STATIC int cbbprint __P((void *, const char *)); 108 109 static int cb_chipset __P((u_int32_t, int *)); 110 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 111 struct pcmciabus_attach_args *)); 112 #if 0 113 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 114 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 115 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 116 #endif 117 118 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 119 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 120 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 121 #if !rbus 122 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 123 u_int32_t)); 124 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 125 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 126 u_int32_t)); 127 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 128 #endif /* !rbus */ 129 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 130 int level, int (*ih) (void *), void *sc)); 131 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 132 133 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 static void pccbb_powerhook __P((int, void *)); 171 172 /* bus-space allocation and deallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 178 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t)); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 187 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t)); 189 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int)); 191 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 192 bus_space_handle_t, bus_size_t)); 193 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t)); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback __P((struct device *)); 201 202 #if defined SHOW_REGS 203 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 204 bus_space_tag_t memt, bus_space_handle_t memh)); 205 #endif 206 207 struct cfattach cbb_pci_ca = { 208 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 209 }; 210 211 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 212 pccbb_pcmcia_mem_alloc, 213 pccbb_pcmcia_mem_free, 214 pccbb_pcmcia_mem_map, 215 pccbb_pcmcia_mem_unmap, 216 pccbb_pcmcia_io_alloc, 217 pccbb_pcmcia_io_free, 218 pccbb_pcmcia_io_map, 219 pccbb_pcmcia_io_unmap, 220 pccbb_pcmcia_intr_establish, 221 pccbb_pcmcia_intr_disestablish, 222 pccbb_pcmcia_socket_enable, 223 pccbb_pcmcia_socket_disable, 224 pccbb_pcmcia_card_detect 225 }; 226 227 #if rbus 228 static struct cardbus_functions pccbb_funcs = { 229 pccbb_rbus_cb_space_alloc, 230 pccbb_rbus_cb_space_free, 231 pccbb_cb_intr_establish, 232 pccbb_cb_intr_disestablish, 233 pccbb_ctrl, 234 pccbb_power, 235 pccbb_make_tag, 236 pccbb_free_tag, 237 pccbb_conf_read, 238 pccbb_conf_write, 239 }; 240 #else 241 static struct cardbus_functions pccbb_funcs = { 242 pccbb_ctrl, 243 pccbb_power, 244 pccbb_mem_open, 245 pccbb_mem_close, 246 pccbb_io_open, 247 pccbb_io_close, 248 pccbb_cb_intr_establish, 249 pccbb_cb_intr_disestablish, 250 pccbb_make_tag, 251 pccbb_conf_read, 252 pccbb_conf_write, 253 }; 254 #endif 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 struct cfdata *match; 260 void *aux; 261 { 262 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 263 264 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 265 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 266 PCI_INTERFACE(pa->pa_class) == 0) { 267 return 1; 268 } 269 270 return 0; 271 } 272 273 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 274 | ((prod) << PCI_PRODUCT_SHIFT)) 275 276 struct yenta_chipinfo { 277 pcireg_t yc_id; /* vendor tag | product tag */ 278 int yc_chiptype; 279 int yc_flags; 280 } yc_chipsets[] = { 281 /* Texas Instruments chips */ 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 307 /* Ricoh chips */ 308 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 309 PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 311 PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 313 PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 315 PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 319 PCCBB_PCMCIA_MEM_32}, 320 321 /* Toshiba products */ 322 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 323 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 325 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 327 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 329 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 330 331 /* Cirrus Logic products */ 332 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 333 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 335 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 336 337 /* sentinel, or Generic chip */ 338 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 339 }; 340 341 static int 342 cb_chipset(pci_id, flagp) 343 u_int32_t pci_id; 344 int *flagp; 345 { 346 struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return (yc->yc_chiptype); 358 } 359 360 static void 361 pccbb_shutdown(void *arg) 362 { 363 struct pccbb_softc *sc = arg; 364 pcireg_t command; 365 366 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 367 368 /* turn off power */ 369 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 370 371 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 372 0); 373 374 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 375 376 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 377 PCI_COMMAND_MASTER_ENABLE); 378 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 379 380 } 381 382 void 383 pccbbattach(parent, self, aux) 384 struct device *parent; 385 struct device *self; 386 void *aux; 387 { 388 struct pccbb_softc *sc = (void *)self; 389 struct pci_attach_args *pa = aux; 390 pci_chipset_tag_t pc = pa->pa_pc; 391 pcireg_t busreg, reg, sock_base; 392 bus_addr_t sockbase; 393 char devinfo[256]; 394 int flags; 395 396 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 397 398 pci_devinfo(pa->pa_id, 0, 0, devinfo); 399 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 400 #ifdef CBB_DEBUG 401 printf(" (chipflags %x)", flags); 402 #endif 403 printf("\n"); 404 405 TAILQ_INIT(&sc->sc_memwindow); 406 TAILQ_INIT(&sc->sc_iowindow); 407 408 #if rbus 409 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 410 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 411 #endif /* rbus */ 412 413 sc->sc_base_memh = 0; 414 415 /* 416 * MAP socket registers and ExCA registers on memory-space 417 * When no valid address is set on socket base registers (on pci 418 * config space), get it not polite way. 419 */ 420 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 421 422 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 423 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 424 /* The address must be valid. */ 425 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 426 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 427 printf("%s: can't map socket base address 0x%x\n", 428 sc->sc_dev.dv_xname, sock_base); 429 /* 430 * I think it's funny: socket base registers must be 431 * mapped on memory space, but ... 432 */ 433 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 434 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 435 NULL)) { 436 printf("%s: can't map socket base address" 437 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 438 sockbase); 439 /* give up... allocate reg space via rbus. */ 440 sc->sc_base_memh = 0; 441 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 442 } 443 } else { 444 DPRINTF(("%s: socket base address 0x%lx\n", 445 sc->sc_dev.dv_xname, sockbase)); 446 } 447 } 448 449 sc->sc_mem_start = 0; /* XXX */ 450 sc->sc_mem_end = 0xffffffff; /* XXX */ 451 452 /* 453 * When interrupt isn't routed correctly, give up probing cbb and do 454 * not kill pcic-compatible port. 455 */ 456 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 457 printf("%s: NOT USED because of unconfigured interrupt\n", 458 sc->sc_dev.dv_xname); 459 return; 460 } 461 462 /* 463 * When bus number isn't set correctly, give up using 32-bit CardBus 464 * mode. 465 */ 466 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 467 #if notyet 468 if (((busreg >> 8) & 0xff) == 0) { 469 printf("%s: CardBus support disabled because of unconfigured bus number\n", 470 sc->sc_dev.dv_xname); 471 flags |= PCCBB_PCMCIA_16BITONLY; 472 } 473 #endif 474 475 /* pccbb_machdep.c end */ 476 477 #if defined CBB_DEBUG 478 { 479 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 480 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 481 intrname[pa->pa_intrpin], pa->pa_intrline); 482 } 483 #endif 484 485 /* setup softc */ 486 sc->sc_pc = pc; 487 sc->sc_iot = pa->pa_iot; 488 sc->sc_memt = pa->pa_memt; 489 sc->sc_dmat = pa->pa_dmat; 490 sc->sc_tag = pa->pa_tag; 491 sc->sc_function = pa->pa_function; 492 493 sc->sc_intrline = pa->pa_intrline; 494 sc->sc_intrtag = pa->pa_intrtag; 495 sc->sc_intrpin = pa->pa_intrpin; 496 497 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 498 499 shutdownhook_establish(pccbb_shutdown, sc); 500 501 /* Disable legacy register mapping. */ 502 switch (sc->sc_chipset) { 503 case CB_RX5C46X: /* fallthrough */ 504 #if 0 505 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 506 case CB_RX5C47X: 507 #endif 508 /* 509 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 510 * cannot be disabled by substituting 0 into PCI_LEGACY 511 * register. Ricoh CardBus bridges have special bits on Bridge 512 * control reg (addr 0x3e on PCI config space). 513 */ 514 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 515 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 516 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 517 break; 518 519 default: 520 /* XXX I don't know proper way to kill legacy I/O. */ 521 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 522 break; 523 } 524 525 config_defer(self, pccbb_pci_callback); 526 } 527 528 529 530 531 /* 532 * static void pccbb_pci_callback(struct device *self) 533 * 534 * The actual attach routine: get memory space for YENTA register 535 * space, setup YENTA register and route interrupt. 536 * 537 * This function should be deferred because this device may obtain 538 * memory space dynamically. This function must avoid obtaining 539 * memory area which has already kept for another device. 540 */ 541 static void 542 pccbb_pci_callback(self) 543 struct device *self; 544 { 545 struct pccbb_softc *sc = (void *)self; 546 pci_chipset_tag_t pc = sc->sc_pc; 547 bus_space_tag_t base_memt; 548 bus_space_handle_t base_memh; 549 u_int32_t maskreg; 550 pci_intr_handle_t ih; 551 const char *intrstr = NULL; 552 bus_addr_t sockbase; 553 struct cbslot_attach_args cba; 554 struct pcmciabus_attach_args paa; 555 struct cardslot_attach_args caa; 556 struct cardslot_softc *csc; 557 558 if (0 == sc->sc_base_memh) { 559 /* The socket registers aren't mapped correctly. */ 560 #if rbus 561 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 562 (sc->sc_chipset == CB_RX5C47X 563 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 564 0, &sockbase, &sc->sc_base_memh)) { 565 return; 566 } 567 sc->sc_base_memt = sc->sc_memt; 568 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 569 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 570 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 571 PCI_SOCKBASE))); 572 #else 573 sc->sc_base_memt = sc->sc_memt; 574 #if !defined CBB_PCI_BASE 575 #define CBB_PCI_BASE 0x20000000 576 #endif 577 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 578 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 579 /* cannot allocate memory space */ 580 return; 581 } 582 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 583 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 584 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 585 sc->sc_tag, PCI_SOCKBASE))); 586 #endif 587 } 588 589 /* bus bridge initialization */ 590 pccbb_chipinit(sc); 591 592 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 593 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 594 595 /* CSC Interrupt: Card detect interrupt on */ 596 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 597 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 598 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 599 /* reset interrupt */ 600 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 601 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 602 603 /* clear data structure for child device interrupt handlers */ 604 sc->sc_pil = NULL; 605 sc->sc_pil_intr_enable = 1; 606 607 /* Map and establish the interrupt. */ 608 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 609 sc->sc_intrline, &ih)) { 610 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 611 return; 612 } 613 intrstr = pci_intr_string(pc, ih); 614 615 /* 616 * XXX pccbbintr should be called under the priority lower 617 * than any other hard interrputs. 618 */ 619 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 620 621 if (sc->sc_ih == NULL) { 622 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 623 if (intrstr != NULL) { 624 printf(" at %s", intrstr); 625 } 626 printf("\n"); 627 return; 628 } 629 630 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 631 powerhook_establish(pccbb_powerhook, sc); 632 633 { 634 u_int32_t sockstat = 635 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 636 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 637 sc->sc_flags |= CBB_CARDEXIST; 638 } 639 } 640 641 /* 642 * attach cardbus 643 */ 644 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 645 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 646 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 647 648 /* initialize cbslot_attach */ 649 cba.cba_busname = "cardbus"; 650 cba.cba_iot = sc->sc_iot; 651 cba.cba_memt = sc->sc_memt; 652 cba.cba_dmat = sc->sc_dmat; 653 cba.cba_bus = (busreg >> 8) & 0x0ff; 654 cba.cba_cc = (void *)sc; 655 cba.cba_cf = &pccbb_funcs; 656 cba.cba_intrline = sc->sc_intrline; 657 658 #if rbus 659 cba.cba_rbus_iot = sc->sc_rbus_iot; 660 cba.cba_rbus_memt = sc->sc_rbus_memt; 661 #endif 662 663 cba.cba_cacheline = PCI_CACHELINE(bhlc); 664 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 665 666 printf("%s: cacheline 0x%x lattimer 0x%x\n", 667 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 668 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 669 busreg); 670 #if defined SHOW_REGS 671 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 672 sc->sc_base_memh); 673 #endif 674 } 675 676 pccbb_pcmcia_attach_setup(sc, &paa); 677 caa.caa_cb_attach = NULL; 678 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 679 caa.caa_cb_attach = &cba; 680 } 681 caa.caa_16_attach = &paa; 682 caa.caa_ph = &sc->sc_pcmcia_h; 683 684 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 685 DPRINTF(("pccbbattach: found cardslot\n")); 686 sc->sc_csc = csc; 687 } 688 689 return; 690 } 691 692 693 694 695 696 /* 697 * static void pccbb_chipinit(struct pccbb_softc *sc) 698 * 699 * This function initialize YENTA chip registers listed below: 700 * 1) PCI command reg, 701 * 2) PCI and CardBus latency timer, 702 * 3) route PCI interrupt, 703 * 4) close all memory and io windows. 704 */ 705 static void 706 pccbb_chipinit(sc) 707 struct pccbb_softc *sc; 708 { 709 pci_chipset_tag_t pc = sc->sc_pc; 710 pcitag_t tag = sc->sc_tag; 711 pcireg_t reg; 712 713 /* 714 * Set PCI command reg. 715 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 716 */ 717 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 718 /* I believe it is harmless. */ 719 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 720 PCI_COMMAND_MASTER_ENABLE); 721 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 722 723 /* 724 * Set CardBus latency timer. 725 */ 726 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 727 if (PCI_CB_LATENCY(reg) < 0x20) { 728 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 729 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 730 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 731 } 732 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 733 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 734 735 /* 736 * Set PCI latency timer. 737 */ 738 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 739 if (PCI_LATTIMER(reg) < 0x10) { 740 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 741 reg |= (0x10 << PCI_LATTIMER_SHIFT); 742 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 743 } 744 DPRINTF(("PCI latency timer 0x%x (%x)\n", 745 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 746 747 748 /* Route functional interrupts to PCI. */ 749 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 750 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 751 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 752 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 753 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 754 755 switch (sc->sc_chipset) { 756 case CB_TI113X: 757 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 758 /* This bit is shared, but may read as 0 on some chips, so set 759 it explicitly on both functions. */ 760 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 761 /* CSC intr enable */ 762 reg |= PCI113X_CBCTRL_PCI_CSC; 763 /* functional intr prohibit | prohibit ISA routing */ 764 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 765 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 766 break; 767 768 case CB_TOPIC95B: 769 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 770 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 771 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 772 773 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 774 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 775 sc->sc_dev.dv_xname, reg)); 776 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 777 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 778 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 779 DPRINTF(("0x%x\n", reg)); 780 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 781 break; 782 } 783 784 /* Close all memory and I/O windows. */ 785 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 786 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 787 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 788 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 789 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 790 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 791 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 792 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 793 794 /* reset 16-bit pcmcia bus */ 795 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 796 0x800 + PCIC_INTR, 797 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 798 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 799 800 /* turn of power */ 801 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 802 } 803 804 805 806 807 /* 808 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 809 * struct pcmciabus_attach_args *paa) 810 * 811 * This function attaches 16-bit PCcard bus. 812 */ 813 STATIC void 814 pccbb_pcmcia_attach_setup(sc, paa) 815 struct pccbb_softc *sc; 816 struct pcmciabus_attach_args *paa; 817 { 818 struct pcic_handle *ph = &sc->sc_pcmcia_h; 819 #if rbus 820 rbus_tag_t rb; 821 #endif 822 823 /* initialize pcmcia part in pccbb_softc */ 824 ph->ph_parent = (struct device *)sc; 825 ph->sock = sc->sc_function; 826 ph->flags = 0; 827 ph->shutdown = 0; 828 ph->ih_irq = sc->sc_intrline; 829 ph->ph_bus_t = sc->sc_base_memt; 830 ph->ph_bus_h = sc->sc_base_memh; 831 ph->ph_read = pccbb_pcmcia_read; 832 ph->ph_write = pccbb_pcmcia_write; 833 sc->sc_pct = &pccbb_pcmcia_funcs; 834 835 /* 836 * We need to do a few things here: 837 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 838 * setting the IRQ numbers to 0. 839 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 840 * routing of CSC interrupts (e.g. card removal) to PCI while in 841 * PCMCIA mode. We just leave this set all the time. 842 * 3) Enable card insertion/removal interrupts in case the chip also 843 * needs that while in PCMCIA mode. 844 * 4) Clear any pending CSC interrupt. 845 */ 846 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 847 if (sc->sc_chipset == CB_TI113X) { 848 Pcic_write(ph, PCIC_CSC_INTR, 0); 849 } else { 850 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 851 Pcic_read(ph, PCIC_CSC); 852 } 853 854 /* initialize pcmcia bus attachment */ 855 paa->paa_busname = "pcmcia"; 856 paa->pct = sc->sc_pct; 857 paa->pch = ph; 858 paa->iobase = 0; /* I don't use them */ 859 paa->iosize = 0; 860 #if rbus 861 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 862 paa->iobase = rb->rb_start + rb->rb_offset; 863 paa->iosize = rb->rb_end - rb->rb_start; 864 #endif 865 866 return; 867 } 868 869 #if 0 870 STATIC void 871 pccbb_pcmcia_attach_card(ph) 872 struct pcic_handle *ph; 873 { 874 if (ph->flags & PCIC_FLAG_CARDP) { 875 panic("pccbb_pcmcia_attach_card: already attached"); 876 } 877 878 /* call the MI attach function */ 879 pcmcia_card_attach(ph->pcmcia); 880 881 ph->flags |= PCIC_FLAG_CARDP; 882 } 883 884 STATIC void 885 pccbb_pcmcia_detach_card(ph, flags) 886 struct pcic_handle *ph; 887 int flags; 888 { 889 if (!(ph->flags & PCIC_FLAG_CARDP)) { 890 panic("pccbb_pcmcia_detach_card: already detached"); 891 } 892 893 ph->flags &= ~PCIC_FLAG_CARDP; 894 895 /* call the MI detach function */ 896 pcmcia_card_detach(ph->pcmcia, flags); 897 } 898 #endif 899 900 /* 901 * int pccbbintr(arg) 902 * void *arg; 903 * This routine handles the interrupt from Yenta PCI-CardBus bridge 904 * itself. 905 */ 906 int 907 pccbbintr(arg) 908 void *arg; 909 { 910 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 911 u_int32_t sockevent, sockstate; 912 bus_space_tag_t memt = sc->sc_base_memt; 913 bus_space_handle_t memh = sc->sc_base_memh; 914 struct pcic_handle *ph = &sc->sc_pcmcia_h; 915 916 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 917 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 918 Pcic_read(ph, PCIC_CSC); 919 920 if (sockevent == 0) { 921 /* This intr is not for me: it may be for my child devices. */ 922 if (sc->sc_pil_intr_enable) { 923 return pccbbintr_function(sc); 924 } else { 925 return 0; 926 } 927 } 928 929 if (sockevent & CB_SOCKET_EVENT_CD) { 930 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 931 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 932 /* A card should be removed. */ 933 if (sc->sc_flags & CBB_CARDEXIST) { 934 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 935 sockevent)); 936 DPRINTF((" card removed, 0x%08x\n", sockstate)); 937 sc->sc_flags &= ~CBB_CARDEXIST; 938 if (sc->sc_csc->sc_status & 939 CARDSLOT_STATUS_CARD_16) { 940 #if 0 941 struct pcic_handle *ph = 942 &sc->sc_pcmcia_h; 943 944 pcmcia_card_deactivate(ph->pcmcia); 945 pccbb_pcmcia_socket_disable(ph); 946 pccbb_pcmcia_detach_card(ph, 947 DETACH_FORCE); 948 #endif 949 cardslot_event_throw(sc->sc_csc, 950 CARDSLOT_EVENT_REMOVAL_16); 951 } else if (sc->sc_csc->sc_status & 952 CARDSLOT_STATUS_CARD_CB) { 953 /* Cardbus intr removed */ 954 cardslot_event_throw(sc->sc_csc, 955 CARDSLOT_EVENT_REMOVAL_CB); 956 } 957 } 958 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 959 /* 960 * The pccbbintr may called from powerdown hook when 961 * the system resumed, to detect the card 962 * insertion/removal during suspension. 963 */ 964 (sc->sc_flags & CBB_CARDEXIST) == 0) { 965 if (sc->sc_flags & CBB_INSERTING) { 966 callout_stop(&sc->sc_insert_ch); 967 } 968 callout_reset(&sc->sc_insert_ch, hz / 10, 969 pci113x_insert, sc); 970 sc->sc_flags |= CBB_INSERTING; 971 } 972 } 973 974 return (1); 975 } 976 977 /* 978 * static int pccbbintr_function(struct pccbb_softc *sc) 979 * 980 * This function calls each interrupt handler registered at the 981 * bridge. The interrupt handlers are called in registered order. 982 */ 983 static int 984 pccbbintr_function(sc) 985 struct pccbb_softc *sc; 986 { 987 int retval = 0, val; 988 struct pccbb_intrhand_list *pil; 989 int s, splchanged; 990 991 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 992 /* 993 * XXX priority change. gross. I use if-else 994 * sentense instead of switch-case sentense because of 995 * avoiding duplicate case value error. More than one 996 * IPL_XXX use same value. It depends on 997 * implimentation. 998 */ 999 splchanged = 1; 1000 if (pil->pil_level == IPL_SERIAL) { 1001 s = splserial(); 1002 } else if (pil->pil_level == IPL_HIGH) { 1003 s = splhigh(); 1004 } else if (pil->pil_level == IPL_CLOCK) { 1005 s = splclock(); 1006 } else if (pil->pil_level == IPL_AUDIO) { 1007 s = splaudio(); 1008 } else if (pil->pil_level == IPL_IMP) { 1009 s = splimp(); 1010 } else if (pil->pil_level == IPL_TTY) { 1011 s = spltty(); 1012 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1013 s = splsoftserial(); 1014 } else if (pil->pil_level == IPL_NET) { 1015 s = splnet(); 1016 } else { 1017 splchanged = 0; 1018 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1019 } 1020 1021 val = (*pil->pil_func)(pil->pil_arg); 1022 1023 if (splchanged != 0) { 1024 splx(s); 1025 } 1026 1027 retval = retval == 1 ? 1 : 1028 retval == 0 ? val : val != 0 ? val : retval; 1029 } 1030 1031 return retval; 1032 } 1033 1034 static void 1035 pci113x_insert(arg) 1036 void *arg; 1037 { 1038 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1039 u_int32_t sockevent, sockstate; 1040 1041 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1042 CB_SOCKET_EVENT); 1043 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1044 CB_SOCKET_STAT); 1045 1046 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1047 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1048 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1049 sc->sc_flags |= CBB_CARDEXIST; 1050 /* call pccard interrupt handler here */ 1051 if (sockstate & CB_SOCKET_STAT_16BIT) { 1052 /* 16-bit card found */ 1053 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1054 cardslot_event_throw(sc->sc_csc, 1055 CARDSLOT_EVENT_INSERTION_16); 1056 } else if (sockstate & CB_SOCKET_STAT_CB) { 1057 /* cardbus card found */ 1058 /* cardbus_attach_card(sc->sc_csc); */ 1059 cardslot_event_throw(sc->sc_csc, 1060 CARDSLOT_EVENT_INSERTION_CB); 1061 } else { 1062 /* who are you? */ 1063 } 1064 } else { 1065 callout_reset(&sc->sc_insert_ch, hz / 10, 1066 pci113x_insert, sc); 1067 } 1068 } 1069 1070 #define PCCBB_PCMCIA_OFFSET 0x800 1071 static u_int8_t 1072 pccbb_pcmcia_read(ph, reg) 1073 struct pcic_handle *ph; 1074 int reg; 1075 { 1076 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1077 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1078 1079 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1080 PCCBB_PCMCIA_OFFSET + reg); 1081 } 1082 1083 static void 1084 pccbb_pcmcia_write(ph, reg, val) 1085 struct pcic_handle *ph; 1086 int reg; 1087 u_int8_t val; 1088 { 1089 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1090 val); 1091 1092 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1093 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1094 } 1095 1096 /* 1097 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1098 */ 1099 STATIC int 1100 pccbb_ctrl(ct, command) 1101 cardbus_chipset_tag_t ct; 1102 int command; 1103 { 1104 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1105 1106 switch (command) { 1107 case CARDBUS_CD: 1108 if (2 == pccbb_detect_card(sc)) { 1109 int retval = 0; 1110 int status = cb_detect_voltage(sc); 1111 if (PCCARD_VCC_5V & status) { 1112 retval |= CARDBUS_5V_CARD; 1113 } 1114 if (PCCARD_VCC_3V & status) { 1115 retval |= CARDBUS_3V_CARD; 1116 } 1117 if (PCCARD_VCC_XV & status) { 1118 retval |= CARDBUS_XV_CARD; 1119 } 1120 if (PCCARD_VCC_YV & status) { 1121 retval |= CARDBUS_YV_CARD; 1122 } 1123 return retval; 1124 } else { 1125 return 0; 1126 } 1127 break; 1128 case CARDBUS_RESET: 1129 return cb_reset(sc); 1130 break; 1131 case CARDBUS_IO_ENABLE: /* fallthrough */ 1132 case CARDBUS_IO_DISABLE: /* fallthrough */ 1133 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1134 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1135 case CARDBUS_BM_ENABLE: /* fallthrough */ 1136 case CARDBUS_BM_DISABLE: /* fallthrough */ 1137 return pccbb_cardenable(sc, command); 1138 break; 1139 } 1140 1141 return 0; 1142 } 1143 1144 /* 1145 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1146 * This function returns true when it succeeds and returns false when 1147 * it fails. 1148 */ 1149 STATIC int 1150 pccbb_power(ct, command) 1151 cardbus_chipset_tag_t ct; 1152 int command; 1153 { 1154 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1155 1156 u_int32_t status, sock_ctrl; 1157 bus_space_tag_t memt = sc->sc_base_memt; 1158 bus_space_handle_t memh = sc->sc_base_memh; 1159 1160 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1161 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1162 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1163 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1164 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1165 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1166 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1167 "UNKNOWN", 1168 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1169 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1170 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1171 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1172 "UNKNOWN", command)); 1173 1174 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1175 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1176 1177 switch (command & CARDBUS_VCCMASK) { 1178 case CARDBUS_VCC_UC: 1179 break; 1180 case CARDBUS_VCC_5V: 1181 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1182 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1183 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1184 } else { 1185 printf("%s: BAD voltage request: no 5 V card\n", 1186 sc->sc_dev.dv_xname); 1187 } 1188 break; 1189 case CARDBUS_VCC_3V: 1190 if (CB_SOCKET_STAT_3VCARD & status) { 1191 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1192 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1193 } else { 1194 printf("%s: BAD voltage request: no 3.3 V card\n", 1195 sc->sc_dev.dv_xname); 1196 } 1197 break; 1198 case CARDBUS_VCC_0V: 1199 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1200 break; 1201 default: 1202 return 0; /* power NEVER changed */ 1203 break; 1204 } 1205 1206 switch (command & CARDBUS_VPPMASK) { 1207 case CARDBUS_VPP_UC: 1208 break; 1209 case CARDBUS_VPP_0V: 1210 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1211 break; 1212 case CARDBUS_VPP_VCC: 1213 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1214 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1215 break; 1216 case CARDBUS_VPP_12V: 1217 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1218 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1219 break; 1220 } 1221 1222 #if 0 1223 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1224 #endif 1225 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1226 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1227 1228 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1229 printf 1230 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1231 sc->sc_dev.dv_xname, sock_ctrl, status); 1232 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1233 (command & CARDBUS_VCCMASK) == 1234 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1235 CARDBUS_VCCMASK) == 1236 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1237 CARDBUS_VCCMASK) == 1238 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1239 CARDBUS_VCCMASK) == 1240 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1241 CARDBUS_VCCMASK) == 1242 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1243 CARDBUS_VCCMASK) == 1244 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1245 (command & CARDBUS_VPPMASK) == 1246 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1247 CARDBUS_VPPMASK) == 1248 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1249 CARDBUS_VPPMASK) == 1250 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1251 CARDBUS_VPPMASK) == 1252 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1253 #if 0 1254 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1255 u_int32_t force = 1256 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1257 /* Reset Bad Vcc request */ 1258 force &= ~CB_SOCKET_FORCE_BADVCC; 1259 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1260 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1261 CB_SOCKET_STAT)); 1262 return 1; 1263 } 1264 #endif 1265 return 0; 1266 } 1267 1268 /* 1269 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1270 * time is 20 ms, some PC-Card bridge requires longer duration. 1271 */ 1272 delay(300 * 1000); 1273 1274 return 1; /* power changed correctly */ 1275 } 1276 1277 #if defined CB_PCMCIA_POLL 1278 struct cb_poll_str { 1279 void *arg; 1280 int (*func) __P((void *)); 1281 int level; 1282 pccard_chipset_tag_t ct; 1283 int count; 1284 struct callout poll_ch; 1285 }; 1286 1287 static struct cb_poll_str cb_poll[10]; 1288 static int cb_poll_n = 0; 1289 1290 static void cb_pcmcia_poll __P((void *arg)); 1291 1292 static void 1293 cb_pcmcia_poll(arg) 1294 void *arg; 1295 { 1296 struct cb_poll_str *poll = arg; 1297 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1298 struct pccbb_softc *sc = psc->cpc_parent; 1299 int s; 1300 u_int32_t spsr; /* socket present-state reg */ 1301 1302 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1303 switch (poll->level) { 1304 case IPL_NET: 1305 s = splnet(); 1306 break; 1307 case IPL_BIO: 1308 s = splbio(); 1309 break; 1310 case IPL_TTY: /* fallthrough */ 1311 default: 1312 s = spltty(); 1313 break; 1314 } 1315 1316 spsr = 1317 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1318 CB_SOCKET_STAT); 1319 1320 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1321 if (!(spsr & 0x40)) { /* CINT low */ 1322 #else 1323 if (1) { 1324 #endif 1325 if ((*poll->func) (poll->arg) == 1) { 1326 ++poll->count; 1327 printf("intr: reported from poller, 0x%x\n", spsr); 1328 #if defined LEVEL2 1329 } else { 1330 printf("intr: miss! 0x%x\n", spsr); 1331 #endif 1332 } 1333 } 1334 splx(s); 1335 } 1336 #endif /* defined CB_PCMCIA_POLL */ 1337 1338 /* 1339 * static int pccbb_detect_card(struct pccbb_softc *sc) 1340 * return value: 0 if no card exists. 1341 * 1 if 16-bit card exists. 1342 * 2 if cardbus card exists. 1343 */ 1344 static int 1345 pccbb_detect_card(sc) 1346 struct pccbb_softc *sc; 1347 { 1348 bus_space_handle_t base_memh = sc->sc_base_memh; 1349 bus_space_tag_t base_memt = sc->sc_base_memt; 1350 u_int32_t sockstat = 1351 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1352 int retval = 0; 1353 1354 /* CD1 and CD2 asserted */ 1355 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1356 /* card must be present */ 1357 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1358 /* NOTACARD DEASSERTED */ 1359 if (CB_SOCKET_STAT_CB & sockstat) { 1360 /* CardBus mode */ 1361 retval = 2; 1362 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1363 /* 16-bit mode */ 1364 retval = 1; 1365 } 1366 } 1367 } 1368 return retval; 1369 } 1370 1371 /* 1372 * STATIC int cb_reset(struct pccbb_softc *sc) 1373 * This function resets CardBus card. 1374 */ 1375 STATIC int 1376 cb_reset(sc) 1377 struct pccbb_softc *sc; 1378 { 1379 /* 1380 * Reset Assert at least 20 ms 1381 * Some machines request longer duration. 1382 */ 1383 int reset_duration = 1384 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1385 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1386 1387 /* Reset bit Assert (bit 6 at 0x3E) */ 1388 bcr |= CB_BCR_RESET_ENABLE; 1389 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1390 delay(reset_duration); 1391 1392 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1393 /* Reset bit Deassert (bit 6 at 0x3E) */ 1394 bcr &= ~CB_BCR_RESET_ENABLE; 1395 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1396 delay(reset_duration); 1397 } 1398 /* No card found on the slot. Keep Reset. */ 1399 return 1; 1400 } 1401 1402 /* 1403 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1404 * This function detect card Voltage. 1405 */ 1406 STATIC int 1407 cb_detect_voltage(sc) 1408 struct pccbb_softc *sc; 1409 { 1410 u_int32_t psr; /* socket present-state reg */ 1411 bus_space_tag_t iot = sc->sc_base_memt; 1412 bus_space_handle_t ioh = sc->sc_base_memh; 1413 int vol = PCCARD_VCC_UKN; /* set 0 */ 1414 1415 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1416 1417 if (0x400u & psr) { 1418 vol |= PCCARD_VCC_5V; 1419 } 1420 if (0x800u & psr) { 1421 vol |= PCCARD_VCC_3V; 1422 } 1423 1424 return vol; 1425 } 1426 1427 STATIC int 1428 cbbprint(aux, pcic) 1429 void *aux; 1430 const char *pcic; 1431 { 1432 /* 1433 struct cbslot_attach_args *cba = aux; 1434 1435 if (cba->cba_slot >= 0) { 1436 printf(" slot %d", cba->cba_slot); 1437 } 1438 */ 1439 return UNCONF; 1440 } 1441 1442 /* 1443 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1444 * This function enables and disables the card 1445 */ 1446 STATIC int 1447 pccbb_cardenable(sc, function) 1448 struct pccbb_softc *sc; 1449 int function; 1450 { 1451 u_int32_t command = 1452 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1453 1454 DPRINTF(("pccbb_cardenable:")); 1455 switch (function) { 1456 case CARDBUS_IO_ENABLE: 1457 command |= PCI_COMMAND_IO_ENABLE; 1458 break; 1459 case CARDBUS_IO_DISABLE: 1460 command &= ~PCI_COMMAND_IO_ENABLE; 1461 break; 1462 case CARDBUS_MEM_ENABLE: 1463 command |= PCI_COMMAND_MEM_ENABLE; 1464 break; 1465 case CARDBUS_MEM_DISABLE: 1466 command &= ~PCI_COMMAND_MEM_ENABLE; 1467 break; 1468 case CARDBUS_BM_ENABLE: 1469 command |= PCI_COMMAND_MASTER_ENABLE; 1470 break; 1471 case CARDBUS_BM_DISABLE: 1472 command &= ~PCI_COMMAND_MASTER_ENABLE; 1473 break; 1474 default: 1475 return 0; 1476 } 1477 1478 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1479 DPRINTF((" command reg 0x%x\n", command)); 1480 return 1; 1481 } 1482 1483 #if !rbus 1484 /* 1485 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1486 */ 1487 static int 1488 pccbb_io_open(ct, win, start, end) 1489 cardbus_chipset_tag_t ct; 1490 int win; 1491 u_int32_t start, end; 1492 { 1493 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1494 int basereg; 1495 int limitreg; 1496 1497 if ((win < 0) || (win > 2)) { 1498 #if defined DIAGNOSTIC 1499 printf("cardbus_io_open: window out of range %d\n", win); 1500 #endif 1501 return 0; 1502 } 1503 1504 basereg = win * 8 + 0x2c; 1505 limitreg = win * 8 + 0x30; 1506 1507 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1508 start, basereg, end, limitreg)); 1509 1510 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1511 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1512 return 1; 1513 } 1514 1515 /* 1516 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1517 */ 1518 static int 1519 pccbb_io_close(ct, win) 1520 cardbus_chipset_tag_t ct; 1521 int win; 1522 { 1523 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1524 int basereg; 1525 int limitreg; 1526 1527 if ((win < 0) || (win > 2)) { 1528 #if defined DIAGNOSTIC 1529 printf("cardbus_io_close: window out of range %d\n", win); 1530 #endif 1531 return 0; 1532 } 1533 1534 basereg = win * 8 + 0x2c; 1535 limitreg = win * 8 + 0x30; 1536 1537 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1538 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1539 return 1; 1540 } 1541 1542 /* 1543 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1544 */ 1545 static int 1546 pccbb_mem_open(ct, win, start, end) 1547 cardbus_chipset_tag_t ct; 1548 int win; 1549 u_int32_t start, end; 1550 { 1551 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1552 int basereg; 1553 int limitreg; 1554 1555 if ((win < 0) || (win > 2)) { 1556 #if defined DIAGNOSTIC 1557 printf("cardbus_mem_open: window out of range %d\n", win); 1558 #endif 1559 return 0; 1560 } 1561 1562 basereg = win * 8 + 0x1c; 1563 limitreg = win * 8 + 0x20; 1564 1565 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1566 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1567 return 1; 1568 } 1569 1570 /* 1571 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1572 */ 1573 static int 1574 pccbb_mem_close(ct, win) 1575 cardbus_chipset_tag_t ct; 1576 int win; 1577 { 1578 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1579 int basereg; 1580 int limitreg; 1581 1582 if ((win < 0) || (win > 2)) { 1583 #if defined DIAGNOSTIC 1584 printf("cardbus_mem_close: window out of range %d\n", win); 1585 #endif 1586 return 0; 1587 } 1588 1589 basereg = win * 8 + 0x1c; 1590 limitreg = win * 8 + 0x20; 1591 1592 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1593 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1594 return 1; 1595 } 1596 #endif 1597 1598 /* 1599 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1600 * int irq, 1601 * int level, 1602 * int (* func) __P((void *)), 1603 * void *arg) 1604 * 1605 * This function registers an interrupt handler at the bridge, in 1606 * order not to call the interrupt handlers of child devices when 1607 * a card-deletion interrupt occurs. 1608 * 1609 * The arguments irq and level are not used. 1610 */ 1611 static void * 1612 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1613 cardbus_chipset_tag_t ct; 1614 int irq, level; 1615 int (*func) __P((void *)); 1616 void *arg; 1617 { 1618 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1619 1620 return pccbb_intr_establish(sc, irq, level, func, arg); 1621 } 1622 1623 1624 /* 1625 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1626 * void *ih) 1627 * 1628 * This function removes an interrupt handler pointed by ih. 1629 */ 1630 static void 1631 pccbb_cb_intr_disestablish(ct, ih) 1632 cardbus_chipset_tag_t ct; 1633 void *ih; 1634 { 1635 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1636 1637 pccbb_intr_disestablish(sc, ih); 1638 } 1639 1640 1641 /* 1642 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1643 * int irq, 1644 * int level, 1645 * int (* func) __P((void *)), 1646 * void *arg) 1647 * 1648 * This function registers an interrupt handler at the bridge, in 1649 * order not to call the interrupt handlers of child devices when 1650 * a card-deletion interrupt occurs. 1651 * 1652 * The arguments irq is not used because pccbb selects intr vector. 1653 */ 1654 static void * 1655 pccbb_intr_establish(sc, irq, level, func, arg) 1656 struct pccbb_softc *sc; 1657 int irq, level; 1658 int (*func) __P((void *)); 1659 void *arg; 1660 { 1661 struct pccbb_intrhand_list *pil, *newpil; 1662 pcireg_t reg; 1663 1664 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1665 1666 if (sc->sc_pil == NULL) { 1667 /* initialize bridge intr routing */ 1668 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1669 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1670 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1671 1672 switch (sc->sc_chipset) { 1673 case CB_TI113X: 1674 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1675 /* functional intr enabled */ 1676 reg |= PCI113X_CBCTRL_PCI_INTR; 1677 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1678 break; 1679 default: 1680 break; 1681 } 1682 } 1683 1684 /* 1685 * Allocate a room for interrupt handler structure. 1686 */ 1687 if (NULL == (newpil = 1688 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1689 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1690 return NULL; 1691 } 1692 1693 newpil->pil_func = func; 1694 newpil->pil_arg = arg; 1695 newpil->pil_level = level; 1696 newpil->pil_next = NULL; 1697 1698 if (sc->sc_pil == NULL) { 1699 sc->sc_pil = newpil; 1700 } else { 1701 for (pil = sc->sc_pil; pil->pil_next != NULL; 1702 pil = pil->pil_next); 1703 pil->pil_next = newpil; 1704 } 1705 1706 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1707 1708 return newpil; 1709 } 1710 1711 /* 1712 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1713 * void *ih) 1714 * 1715 * This function removes an interrupt handler pointed by ih. 1716 */ 1717 static void 1718 pccbb_intr_disestablish(sc, ih) 1719 struct pccbb_softc *sc; 1720 void *ih; 1721 { 1722 struct pccbb_intrhand_list *pil, **pil_prev; 1723 pcireg_t reg; 1724 1725 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1726 1727 pil_prev = &sc->sc_pil; 1728 1729 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1730 if (pil == ih) { 1731 *pil_prev = pil->pil_next; 1732 free(pil, M_DEVBUF); 1733 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1734 break; 1735 } 1736 pil_prev = &pil->pil_next; 1737 } 1738 1739 if (sc->sc_pil == NULL) { 1740 /* No interrupt handlers */ 1741 1742 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1743 1744 /* stop routing PCI intr */ 1745 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1746 reg |= CB_BCR_INTR_IREQ_ENABLE; 1747 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1748 1749 switch (sc->sc_chipset) { 1750 case CB_TI113X: 1751 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1752 /* functional intr disabled */ 1753 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1754 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1755 break; 1756 default: 1757 break; 1758 } 1759 } 1760 } 1761 1762 #if defined SHOW_REGS 1763 static void 1764 cb_show_regs(pc, tag, memt, memh) 1765 pci_chipset_tag_t pc; 1766 pcitag_t tag; 1767 bus_space_tag_t memt; 1768 bus_space_handle_t memh; 1769 { 1770 int i; 1771 printf("PCI config regs:"); 1772 for (i = 0; i < 0x50; i += 4) { 1773 if (i % 16 == 0) { 1774 printf("\n 0x%02x:", i); 1775 } 1776 printf(" %08x", pci_conf_read(pc, tag, i)); 1777 } 1778 for (i = 0x80; i < 0xb0; i += 4) { 1779 if (i % 16 == 0) { 1780 printf("\n 0x%02x:", i); 1781 } 1782 printf(" %08x", pci_conf_read(pc, tag, i)); 1783 } 1784 1785 if (memh == 0) { 1786 printf("\n"); 1787 return; 1788 } 1789 1790 printf("\nsocket regs:"); 1791 for (i = 0; i <= 0x10; i += 0x04) { 1792 printf(" %08x", bus_space_read_4(memt, memh, i)); 1793 } 1794 printf("\nExCA regs:"); 1795 for (i = 0; i < 0x08; ++i) { 1796 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1797 } 1798 printf("\n"); 1799 return; 1800 } 1801 #endif 1802 1803 /* 1804 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1805 * int busno, int devno, int function) 1806 * This is the function to make a tag to access config space of 1807 * a CardBus Card. It works same as pci_conf_read. 1808 */ 1809 static cardbustag_t 1810 pccbb_make_tag(cc, busno, devno, function) 1811 cardbus_chipset_tag_t cc; 1812 int busno, devno, function; 1813 { 1814 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1815 1816 return pci_make_tag(sc->sc_pc, busno, devno, function); 1817 } 1818 1819 static void 1820 pccbb_free_tag(cc, tag) 1821 cardbus_chipset_tag_t cc; 1822 cardbustag_t tag; 1823 { 1824 } 1825 1826 /* 1827 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1828 * cardbustag_t tag, int offset) 1829 * This is the function to read the config space of a CardBus Card. 1830 * It works same as pci_conf_read. 1831 */ 1832 static cardbusreg_t 1833 pccbb_conf_read(cc, tag, offset) 1834 cardbus_chipset_tag_t cc; 1835 cardbustag_t tag; 1836 int offset; /* register offset */ 1837 { 1838 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1839 1840 return pci_conf_read(sc->sc_pc, tag, offset); 1841 } 1842 1843 /* 1844 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1845 * int offs, cardbusreg_t val) 1846 * This is the function to write the config space of a CardBus Card. 1847 * It works same as pci_conf_write. 1848 */ 1849 static void 1850 pccbb_conf_write(cc, tag, reg, val) 1851 cardbus_chipset_tag_t cc; 1852 cardbustag_t tag; 1853 int reg; /* register offset */ 1854 cardbusreg_t val; 1855 { 1856 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1857 1858 pci_conf_write(sc->sc_pc, tag, reg, val); 1859 } 1860 1861 #if 0 1862 STATIC int 1863 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1864 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1865 int speed, int flags, 1866 bus_space_handle_t * iohp) 1867 #endif 1868 /* 1869 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1870 * bus_addr_t start, bus_size_t size, 1871 * bus_size_t align, 1872 * struct pcmcia_io_handle *pcihp 1873 * 1874 * This function only allocates I/O region for pccard. This function 1875 * never maps the allocated region to pccard I/O area. 1876 * 1877 * XXX: The interface of this function is not very good, I believe. 1878 */ 1879 STATIC int 1880 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1881 pcmcia_chipset_handle_t pch; 1882 bus_addr_t start; /* start address */ 1883 bus_size_t size; 1884 bus_size_t align; 1885 struct pcmcia_io_handle *pcihp; 1886 { 1887 struct pcic_handle *ph = (struct pcic_handle *)pch; 1888 bus_addr_t ioaddr; 1889 int flags = 0; 1890 bus_space_tag_t iot; 1891 bus_space_handle_t ioh; 1892 #if rbus 1893 rbus_tag_t rb; 1894 #endif 1895 if (align == 0) { 1896 align = size; /* XXX: funny??? */ 1897 } 1898 1899 /* 1900 * Allocate some arbitrary I/O space. 1901 */ 1902 1903 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1904 1905 #if rbus 1906 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1907 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1908 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1909 return 1; 1910 } 1911 #else 1912 if (start) { 1913 ioaddr = start; 1914 if (bus_space_map(iot, start, size, 0, &ioh)) { 1915 return 1; 1916 } 1917 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1918 (u_long) ioaddr, (u_long) size)); 1919 } else { 1920 flags |= PCMCIA_IO_ALLOCATED; 1921 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1922 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1923 size, align, 0, 0, &ioaddr, &ioh)) { 1924 /* No room be able to be get. */ 1925 return 1; 1926 } 1927 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1928 (u_long) ioaddr, (u_long) size)); 1929 } 1930 #endif 1931 1932 pcihp->iot = iot; 1933 pcihp->ioh = ioh; 1934 pcihp->addr = ioaddr; 1935 pcihp->size = size; 1936 pcihp->flags = flags; 1937 1938 return 0; 1939 } 1940 1941 /* 1942 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1943 * struct pcmcia_io_handle *pcihp) 1944 * 1945 * This function only frees I/O region for pccard. 1946 * 1947 * XXX: The interface of this function is not very good, I believe. 1948 */ 1949 void 1950 pccbb_pcmcia_io_free(pch, pcihp) 1951 pcmcia_chipset_handle_t pch; 1952 struct pcmcia_io_handle *pcihp; 1953 { 1954 #if !rbus 1955 bus_space_tag_t iot = pcihp->iot; 1956 #endif 1957 bus_space_handle_t ioh = pcihp->ioh; 1958 bus_size_t size = pcihp->size; 1959 1960 #if rbus 1961 struct pccbb_softc *sc = 1962 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1963 rbus_tag_t rb = sc->sc_rbus_iot; 1964 1965 rbus_space_free(rb, ioh, size, NULL); 1966 #else 1967 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1968 bus_space_free(iot, ioh, size); 1969 else 1970 bus_space_unmap(iot, ioh, size); 1971 #endif 1972 } 1973 1974 /* 1975 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1976 * bus_addr_t offset, bus_size_t size, 1977 * struct pcmcia_io_handle *pcihp, 1978 * int *windowp) 1979 * 1980 * This function maps the allocated I/O region to pccard. This function 1981 * never allocates any I/O region for pccard I/O area. I don't 1982 * understand why the original authors of pcmciabus separated alloc and 1983 * map. I believe the two must be unite. 1984 * 1985 * XXX: no wait timing control? 1986 */ 1987 int 1988 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1989 pcmcia_chipset_handle_t pch; 1990 int width; 1991 bus_addr_t offset; 1992 bus_size_t size; 1993 struct pcmcia_io_handle *pcihp; 1994 int *windowp; 1995 { 1996 struct pcic_handle *ph = (struct pcic_handle *)pch; 1997 bus_addr_t ioaddr = pcihp->addr + offset; 1998 int i, win; 1999 #if defined CBB_DEBUG 2000 static char *width_names[] = { "dynamic", "io8", "io16" }; 2001 #endif 2002 2003 /* Sanity check I/O handle. */ 2004 2005 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2006 panic("pccbb_pcmcia_io_map iot is bogus"); 2007 } 2008 2009 /* XXX Sanity check offset/size. */ 2010 2011 win = -1; 2012 for (i = 0; i < PCIC_IO_WINS; i++) { 2013 if ((ph->ioalloc & (1 << i)) == 0) { 2014 win = i; 2015 ph->ioalloc |= (1 << i); 2016 break; 2017 } 2018 } 2019 2020 if (win == -1) { 2021 return 1; 2022 } 2023 2024 *windowp = win; 2025 2026 /* XXX this is pretty gross */ 2027 2028 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2029 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2030 2031 /* XXX wtf is this doing here? */ 2032 2033 #if 0 2034 printf(" port 0x%lx", (u_long) ioaddr); 2035 if (size > 1) { 2036 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2037 } 2038 #endif 2039 2040 ph->io[win].addr = ioaddr; 2041 ph->io[win].size = size; 2042 ph->io[win].width = width; 2043 2044 /* actual dirty register-value changing in the function below. */ 2045 pccbb_pcmcia_do_io_map(ph, win); 2046 2047 return 0; 2048 } 2049 2050 /* 2051 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2052 * 2053 * This function changes register-value to map I/O region for pccard. 2054 */ 2055 static void 2056 pccbb_pcmcia_do_io_map(ph, win) 2057 struct pcic_handle *ph; 2058 int win; 2059 { 2060 static u_int8_t pcic_iowidth[3] = { 2061 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2062 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2063 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2064 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2065 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2066 }; 2067 2068 #define PCIC_SIA_START_LOW 0 2069 #define PCIC_SIA_START_HIGH 1 2070 #define PCIC_SIA_STOP_LOW 2 2071 #define PCIC_SIA_STOP_HIGH 3 2072 2073 int regbase_win = 0x8 + win * 0x04; 2074 u_int8_t ioctl, enable; 2075 2076 DPRINTF( 2077 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2078 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2079 ph->io[win].width * 8)); 2080 2081 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2082 ph->io[win].addr & 0xff); 2083 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2084 (ph->io[win].addr >> 8) & 0xff); 2085 2086 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2087 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2088 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2089 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2090 2091 ioctl = Pcic_read(ph, PCIC_IOCTL); 2092 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2093 switch (win) { 2094 case 0: 2095 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2096 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2097 PCIC_IOCTL_IO0_DATASIZE_MASK); 2098 ioctl |= pcic_iowidth[ph->io[win].width]; 2099 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2100 break; 2101 case 1: 2102 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2103 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2104 PCIC_IOCTL_IO1_DATASIZE_MASK); 2105 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2106 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2107 break; 2108 } 2109 Pcic_write(ph, PCIC_IOCTL, ioctl); 2110 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2111 #if defined CBB_DEBUG 2112 { 2113 u_int8_t start_low = 2114 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2115 u_int8_t start_high = 2116 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2117 u_int8_t stop_low = 2118 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2119 u_int8_t stop_high = 2120 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2121 printf 2122 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2123 start_low, start_high, stop_low, stop_high, ioctl, enable); 2124 } 2125 #endif 2126 } 2127 2128 /* 2129 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2130 * 2131 * This function unmaps I/O region. No return value. 2132 */ 2133 STATIC void 2134 pccbb_pcmcia_io_unmap(pch, win) 2135 pcmcia_chipset_handle_t pch; 2136 int win; 2137 { 2138 struct pcic_handle *ph = (struct pcic_handle *)pch; 2139 int reg; 2140 2141 if (win >= PCIC_IO_WINS || win < 0) { 2142 panic("pccbb_pcmcia_io_unmap: window out of range"); 2143 } 2144 2145 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2146 switch (win) { 2147 case 0: 2148 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2149 break; 2150 case 1: 2151 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2152 break; 2153 } 2154 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2155 2156 ph->ioalloc &= ~(1 << win); 2157 } 2158 2159 /* 2160 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2161 * 2162 * This function enables the card. All information is stored in 2163 * the first argument, pcmcia_chipset_handle_t. 2164 */ 2165 static void 2166 pccbb_pcmcia_wait_ready(ph) 2167 struct pcic_handle *ph; 2168 { 2169 int i; 2170 2171 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2172 Pcic_read(ph, PCIC_IF_STATUS))); 2173 2174 for (i = 0; i < 10000; i++) { 2175 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2176 return; 2177 } 2178 delay(500); 2179 #ifdef CBB_DEBUG 2180 if ((i > 5000) && (i % 100 == 99)) 2181 printf("."); 2182 #endif 2183 } 2184 2185 #ifdef DIAGNOSTIC 2186 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2187 Pcic_read(ph, PCIC_IF_STATUS)); 2188 #endif 2189 } 2190 2191 /* 2192 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2193 * 2194 * This function enables the card. All information is stored in 2195 * the first argument, pcmcia_chipset_handle_t. 2196 */ 2197 STATIC void 2198 pccbb_pcmcia_socket_enable(pch) 2199 pcmcia_chipset_handle_t pch; 2200 { 2201 struct pcic_handle *ph = (struct pcic_handle *)pch; 2202 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2203 int cardtype, win; 2204 u_int8_t power, intr; 2205 pcireg_t spsr; 2206 int voltage; 2207 2208 /* this bit is mostly stolen from pcic_attach_card */ 2209 2210 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2211 2212 /* get card Vcc info */ 2213 2214 spsr = 2215 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2216 CB_SOCKET_STAT); 2217 if (spsr & CB_SOCKET_STAT_5VCARD) { 2218 DPRINTF(("5V card\n")); 2219 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2220 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2221 DPRINTF(("3V card\n")); 2222 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2223 } else { 2224 printf("?V card, 0x%x\n", spsr); /* XXX */ 2225 return; 2226 } 2227 2228 /* disable socket i/o: negate output enable bit */ 2229 2230 power = 0; 2231 Pcic_write(ph, PCIC_PWRCTL, power); 2232 2233 /* power down the socket to reset it, clear the card reset pin */ 2234 2235 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2236 2237 /* 2238 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2239 * we are changing Vcc (Toff). 2240 */ 2241 /* delay(300*1000); too much */ 2242 2243 /* assert reset bit */ 2244 intr = Pcic_read(ph, PCIC_INTR); 2245 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2246 Pcic_write(ph, PCIC_INTR, intr); 2247 2248 /* power up the socket and output enable */ 2249 power = Pcic_read(ph, PCIC_PWRCTL); 2250 power |= PCIC_PWRCTL_OE; 2251 Pcic_write(ph, PCIC_PWRCTL, power); 2252 pccbb_power(sc, voltage); 2253 2254 /* 2255 * hold RESET at least 10us. 2256 */ 2257 delay(10); 2258 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2259 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2260 2261 /* clear the reset flag */ 2262 2263 intr |= PCIC_INTR_RESET; 2264 Pcic_write(ph, PCIC_INTR, intr); 2265 2266 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2267 2268 delay(20000); 2269 2270 /* wait for the chip to finish initializing */ 2271 2272 pccbb_pcmcia_wait_ready(ph); 2273 2274 /* zero out the address windows */ 2275 2276 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2277 2278 /* set the card type */ 2279 2280 cardtype = pcmcia_card_gettype(ph->pcmcia); 2281 2282 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2283 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2284 Pcic_write(ph, PCIC_INTR, intr); 2285 2286 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2287 ph->ph_parent->dv_xname, ph->sock, 2288 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2289 2290 /* reinstall all the memory and io mappings */ 2291 2292 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2293 if (ph->memalloc & (1 << win)) { 2294 pccbb_pcmcia_do_mem_map(ph, win); 2295 } 2296 } 2297 2298 for (win = 0; win < PCIC_IO_WINS; ++win) { 2299 if (ph->ioalloc & (1 << win)) { 2300 pccbb_pcmcia_do_io_map(ph, win); 2301 } 2302 } 2303 } 2304 2305 /* 2306 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2307 * 2308 * This function disables the card. All information is stored in 2309 * the first argument, pcmcia_chipset_handle_t. 2310 */ 2311 STATIC void 2312 pccbb_pcmcia_socket_disable(pch) 2313 pcmcia_chipset_handle_t pch; 2314 { 2315 struct pcic_handle *ph = (struct pcic_handle *)pch; 2316 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2317 u_int8_t power, intr; 2318 2319 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2320 2321 /* reset signal asserting... */ 2322 2323 intr = Pcic_read(ph, PCIC_INTR); 2324 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2325 Pcic_write(ph, PCIC_INTR, intr); 2326 delay(2 * 1000); 2327 2328 /* power down the socket */ 2329 power = Pcic_read(ph, PCIC_PWRCTL); 2330 power &= ~PCIC_PWRCTL_OE; 2331 Pcic_write(ph, PCIC_PWRCTL, power); 2332 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2333 /* 2334 * wait 300ms until power fails (Tpf). 2335 */ 2336 delay(300 * 1000); 2337 } 2338 2339 /* 2340 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2341 * 2342 * This function detects whether a card is in the slot or not. 2343 * If a card is inserted, return 1. Otherwise, return 0. 2344 */ 2345 STATIC int 2346 pccbb_pcmcia_card_detect(pch) 2347 pcmcia_chipset_handle_t pch; 2348 { 2349 struct pcic_handle *ph = (struct pcic_handle *)pch; 2350 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2351 2352 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2353 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2354 } 2355 2356 #if 0 2357 STATIC int 2358 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2359 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2360 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2361 #endif 2362 /* 2363 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2364 * bus_size_t size, 2365 * struct pcmcia_mem_handle *pcmhp) 2366 * 2367 * This function only allocates memory region for pccard. This 2368 * function never maps the allocated region to pccard memory area. 2369 * 2370 * XXX: Why the argument of start address is not in? 2371 */ 2372 STATIC int 2373 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2374 pcmcia_chipset_handle_t pch; 2375 bus_size_t size; 2376 struct pcmcia_mem_handle *pcmhp; 2377 { 2378 struct pcic_handle *ph = (struct pcic_handle *)pch; 2379 bus_space_handle_t memh; 2380 bus_addr_t addr; 2381 bus_size_t sizepg; 2382 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2383 #if rbus 2384 rbus_tag_t rb; 2385 #endif 2386 2387 /* out of sc->memh, allocate as many pages as necessary */ 2388 2389 /* convert size to PCIC pages */ 2390 /* 2391 * This is not enough; when the requested region is on the page 2392 * boundaries, this may calculate wrong result. 2393 */ 2394 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2395 #if 0 2396 if (sizepg > PCIC_MAX_MEM_PAGES) { 2397 return 1; 2398 } 2399 #endif 2400 2401 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2402 return 1; 2403 } 2404 2405 addr = 0; /* XXX gcc -Wuninitialized */ 2406 2407 #if rbus 2408 rb = sc->sc_rbus_memt; 2409 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2410 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2411 &addr, &memh)) { 2412 return 1; 2413 } 2414 #else 2415 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2416 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2417 0, /* boundary */ 2418 0, /* flags */ 2419 &addr, &memh)) { 2420 return 1; 2421 } 2422 #endif 2423 2424 DPRINTF( 2425 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2426 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2427 2428 pcmhp->memt = sc->sc_memt; 2429 pcmhp->memh = memh; 2430 pcmhp->addr = addr; 2431 pcmhp->size = size; 2432 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2433 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2434 pcmhp->mhandle = 0; 2435 /* No offset??? Funny. */ 2436 2437 return 0; 2438 } 2439 2440 /* 2441 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2442 * struct pcmcia_mem_handle *pcmhp) 2443 * 2444 * This function release the memory space allocated by the function 2445 * pccbb_pcmcia_mem_alloc(). 2446 */ 2447 STATIC void 2448 pccbb_pcmcia_mem_free(pch, pcmhp) 2449 pcmcia_chipset_handle_t pch; 2450 struct pcmcia_mem_handle *pcmhp; 2451 { 2452 #if rbus 2453 struct pcic_handle *ph = (struct pcic_handle *)pch; 2454 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2455 2456 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2457 #else 2458 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2459 #endif 2460 } 2461 2462 /* 2463 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2464 * 2465 * This function release the memory space allocated by the function 2466 * pccbb_pcmcia_mem_alloc(). 2467 */ 2468 STATIC void 2469 pccbb_pcmcia_do_mem_map(ph, win) 2470 struct pcic_handle *ph; 2471 int win; 2472 { 2473 int regbase_win; 2474 bus_addr_t phys_addr; 2475 bus_addr_t phys_end; 2476 2477 #define PCIC_SMM_START_LOW 0 2478 #define PCIC_SMM_START_HIGH 1 2479 #define PCIC_SMM_STOP_LOW 2 2480 #define PCIC_SMM_STOP_HIGH 3 2481 #define PCIC_CMA_LOW 4 2482 #define PCIC_CMA_HIGH 5 2483 2484 u_int8_t start_low, start_high = 0; 2485 u_int8_t stop_low, stop_high; 2486 u_int8_t off_low, off_high; 2487 u_int8_t mem_window; 2488 int reg; 2489 2490 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2491 int mem8 = 2492 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2493 || (kind == PCMCIA_MEM_ATTR); 2494 2495 regbase_win = 0x10 + win * 0x08; 2496 2497 phys_addr = ph->mem[win].addr; 2498 phys_end = phys_addr + ph->mem[win].size; 2499 2500 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2501 phys_addr, phys_end, ph->mem[win].offset)); 2502 2503 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2504 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2505 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2506 2507 /* bit 19:12 */ 2508 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2509 /* bit 23:20 and bit 7 on */ 2510 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2511 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2512 /* bit 31:24, for 32-bit address */ 2513 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2514 2515 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2516 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2517 2518 if (((struct pccbb_softc *)ph-> 2519 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2520 Pcic_write(ph, 0x40 + win, mem_window); 2521 } 2522 2523 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2524 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2525 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2526 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2527 2528 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2529 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2530 2531 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2532 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2533 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2534 | ((kind == PCMCIA_MEM_ATTR) ? 2535 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2536 2537 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2538 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2539 2540 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2541 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2542 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2543 2544 #if defined CBB_DEBUG 2545 { 2546 int r1, r2, r3, r4, r5, r6, r7 = 0; 2547 2548 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2549 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2550 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2551 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2552 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2553 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2554 if (((struct pccbb_softc *)(ph-> 2555 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2556 r7 = Pcic_read(ph, 0x40 + win); 2557 } 2558 2559 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2560 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2561 if (((struct pccbb_softc *)(ph-> 2562 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2563 DPRINTF((" %02x", r7)); 2564 } 2565 DPRINTF(("\n")); 2566 } 2567 #endif 2568 } 2569 2570 /* 2571 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2572 * bus_addr_t card_addr, bus_size_t size, 2573 * struct pcmcia_mem_handle *pcmhp, 2574 * bus_addr_t *offsetp, int *windowp) 2575 * 2576 * This function maps memory space allocated by the function 2577 * pccbb_pcmcia_mem_alloc(). 2578 */ 2579 STATIC int 2580 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2581 pcmcia_chipset_handle_t pch; 2582 int kind; 2583 bus_addr_t card_addr; 2584 bus_size_t size; 2585 struct pcmcia_mem_handle *pcmhp; 2586 bus_addr_t *offsetp; 2587 int *windowp; 2588 { 2589 struct pcic_handle *ph = (struct pcic_handle *)pch; 2590 bus_addr_t busaddr; 2591 long card_offset; 2592 int win; 2593 2594 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2595 if ((ph->memalloc & (1 << win)) == 0) { 2596 ph->memalloc |= (1 << win); 2597 break; 2598 } 2599 } 2600 2601 if (win == PCIC_MEM_WINS) { 2602 return 1; 2603 } 2604 2605 *windowp = win; 2606 2607 /* XXX this is pretty gross */ 2608 2609 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2610 panic("pccbb_pcmcia_mem_map memt is bogus"); 2611 } 2612 2613 busaddr = pcmhp->addr; 2614 2615 /* 2616 * compute the address offset to the pcmcia address space for the 2617 * pcic. this is intentionally signed. The masks and shifts below 2618 * will cause TRT to happen in the pcic registers. Deal with making 2619 * sure the address is aligned, and return the alignment offset. 2620 */ 2621 2622 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2623 card_addr -= *offsetp; 2624 2625 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2626 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2627 (u_long) card_addr)); 2628 2629 /* 2630 * include the offset in the size, and decrement size by one, since 2631 * the hw wants start/stop 2632 */ 2633 size += *offsetp - 1; 2634 2635 card_offset = (((long)card_addr) - ((long)busaddr)); 2636 2637 ph->mem[win].addr = busaddr; 2638 ph->mem[win].size = size; 2639 ph->mem[win].offset = card_offset; 2640 ph->mem[win].kind = kind; 2641 2642 pccbb_pcmcia_do_mem_map(ph, win); 2643 2644 return 0; 2645 } 2646 2647 /* 2648 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2649 * int window) 2650 * 2651 * This function unmaps memory space which mapped by the function 2652 * pccbb_pcmcia_mem_map(). 2653 */ 2654 STATIC void 2655 pccbb_pcmcia_mem_unmap(pch, window) 2656 pcmcia_chipset_handle_t pch; 2657 int window; 2658 { 2659 struct pcic_handle *ph = (struct pcic_handle *)pch; 2660 int reg; 2661 2662 if (window >= PCIC_MEM_WINS) { 2663 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2664 } 2665 2666 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2667 reg &= ~(1 << window); 2668 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2669 2670 ph->memalloc &= ~(1 << window); 2671 } 2672 2673 #if defined PCCBB_PCMCIA_POLL 2674 struct pccbb_poll_str { 2675 void *arg; 2676 int (*func) __P((void *)); 2677 int level; 2678 struct pcic_handle *ph; 2679 int count; 2680 int num; 2681 struct callout poll_ch; 2682 }; 2683 2684 static struct pccbb_poll_str pccbb_poll[10]; 2685 static int pccbb_poll_n = 0; 2686 2687 static void pccbb_pcmcia_poll __P((void *arg)); 2688 2689 static void 2690 pccbb_pcmcia_poll(arg) 2691 void *arg; 2692 { 2693 struct pccbb_poll_str *poll = arg; 2694 struct pcic_handle *ph = poll->ph; 2695 struct pccbb_softc *sc = ph->sc; 2696 int s; 2697 u_int32_t spsr; /* socket present-state reg */ 2698 2699 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2700 switch (poll->level) { 2701 case IPL_NET: 2702 s = splnet(); 2703 break; 2704 case IPL_BIO: 2705 s = splbio(); 2706 break; 2707 case IPL_TTY: /* fallthrough */ 2708 default: 2709 s = spltty(); 2710 break; 2711 } 2712 2713 spsr = 2714 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2715 CB_SOCKET_STAT); 2716 2717 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2718 if (!(spsr & 0x40)) /* CINT low */ 2719 #else 2720 if (1) 2721 #endif 2722 { 2723 if ((*poll->func) (poll->arg) > 0) { 2724 ++poll->count; 2725 // printf("intr: reported from poller, 0x%x\n", spsr); 2726 #if defined LEVEL2 2727 } else { 2728 printf("intr: miss! 0x%x\n", spsr); 2729 #endif 2730 } 2731 } 2732 splx(s); 2733 } 2734 #endif /* defined CB_PCMCIA_POLL */ 2735 2736 /* 2737 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2738 * struct pcmcia_function *pf, 2739 * int ipl, 2740 * int (*func)(void *), 2741 * void *arg); 2742 * 2743 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2744 */ 2745 STATIC void * 2746 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2747 pcmcia_chipset_handle_t pch; 2748 struct pcmcia_function *pf; 2749 int ipl; 2750 int (*func) __P((void *)); 2751 void *arg; 2752 { 2753 struct pcic_handle *ph = (struct pcic_handle *)pch; 2754 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2755 2756 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2757 /* what should I do? */ 2758 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2759 DPRINTF( 2760 ("%s does not provide edge nor pulse interrupt\n", 2761 sc->sc_dev.dv_xname)); 2762 return NULL; 2763 } 2764 /* 2765 * XXX Noooooo! The interrupt flag must set properly!! 2766 * dumb pcmcia driver!! 2767 */ 2768 } 2769 2770 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2771 } 2772 2773 /* 2774 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2775 * void *ih) 2776 * 2777 * This function disables PC-Card interrupt. 2778 */ 2779 STATIC void 2780 pccbb_pcmcia_intr_disestablish(pch, ih) 2781 pcmcia_chipset_handle_t pch; 2782 void *ih; 2783 { 2784 struct pcic_handle *ph = (struct pcic_handle *)pch; 2785 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2786 2787 pccbb_intr_disestablish(sc, ih); 2788 } 2789 2790 #if rbus 2791 /* 2792 * static int 2793 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2794 * bus_addr_t addr, bus_size_t size, 2795 * bus_addr_t mask, bus_size_t align, 2796 * int flags, bus_addr_t *addrp; 2797 * bus_space_handle_t *bshp) 2798 * 2799 * This function allocates a portion of memory or io space for 2800 * clients. This function is called from CardBus card drivers. 2801 */ 2802 static int 2803 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2804 cardbus_chipset_tag_t ct; 2805 rbus_tag_t rb; 2806 bus_addr_t addr; 2807 bus_size_t size; 2808 bus_addr_t mask; 2809 bus_size_t align; 2810 int flags; 2811 bus_addr_t *addrp; 2812 bus_space_handle_t *bshp; 2813 { 2814 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2815 2816 DPRINTF( 2817 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2818 addr, size, mask, align)); 2819 2820 if (align == 0) { 2821 align = size; 2822 } 2823 2824 if (rb->rb_bt == sc->sc_memt) { 2825 if (align < 16) { 2826 return 1; 2827 } 2828 } else if (rb->rb_bt == sc->sc_iot) { 2829 if (align < 4) { 2830 return 1; 2831 } 2832 /* XXX: hack for avoiding ISA image */ 2833 if (mask < 0x0100) { 2834 mask = 0x3ff; 2835 addr = 0x300; 2836 } 2837 2838 } else { 2839 DPRINTF( 2840 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2841 rb->rb_bt)); 2842 return 1; 2843 /* XXX: panic here? */ 2844 } 2845 2846 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2847 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2848 return 1; 2849 } 2850 2851 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2852 2853 return 0; 2854 } 2855 2856 /* 2857 * static int 2858 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2859 * bus_space_handle_t *bshp, bus_size_t size); 2860 * 2861 * This function is called from CardBus card drivers. 2862 */ 2863 static int 2864 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2865 cardbus_chipset_tag_t ct; 2866 rbus_tag_t rb; 2867 bus_space_handle_t bsh; 2868 bus_size_t size; 2869 { 2870 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2871 bus_space_tag_t bt = rb->rb_bt; 2872 2873 pccbb_close_win(sc, bt, bsh, size); 2874 2875 if (bt == sc->sc_memt) { 2876 } else if (bt == sc->sc_iot) { 2877 } else { 2878 return 1; 2879 /* XXX: panic here? */ 2880 } 2881 2882 return rbus_space_free(rb, bsh, size, NULL); 2883 } 2884 #endif /* rbus */ 2885 2886 #if rbus 2887 2888 static int 2889 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2890 struct pccbb_softc *sc; 2891 bus_space_tag_t bst; 2892 bus_addr_t addr; 2893 bus_size_t size; 2894 bus_space_handle_t bsh; 2895 int flags; 2896 { 2897 struct pccbb_win_chain_head *head; 2898 bus_addr_t align; 2899 2900 head = &sc->sc_iowindow; 2901 align = 0x04; 2902 if (sc->sc_memt == bst) { 2903 head = &sc->sc_memwindow; 2904 align = 0x1000; 2905 DPRINTF(("using memory window, %x %x %x\n\n", 2906 sc->sc_iot, sc->sc_memt, bst)); 2907 } 2908 2909 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2910 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2911 sc->sc_dev.dv_xname, 2912 (head == &sc->sc_memwindow) ? "mem" : "io"); 2913 } 2914 pccbb_winset(align, sc, bst); 2915 2916 return 0; 2917 } 2918 2919 static int 2920 pccbb_close_win(sc, bst, bsh, size) 2921 struct pccbb_softc *sc; 2922 bus_space_tag_t bst; 2923 bus_space_handle_t bsh; 2924 bus_size_t size; 2925 { 2926 struct pccbb_win_chain_head *head; 2927 bus_addr_t align; 2928 2929 head = &sc->sc_iowindow; 2930 align = 0x04; 2931 if (sc->sc_memt == bst) { 2932 head = &sc->sc_memwindow; 2933 align = 0x1000; 2934 } 2935 2936 if (pccbb_winlist_delete(head, bsh, size)) { 2937 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2938 sc->sc_dev.dv_xname, 2939 (head == &sc->sc_memwindow) ? "mem" : "io"); 2940 } 2941 pccbb_winset(align, sc, bst); 2942 2943 return 0; 2944 } 2945 2946 static int 2947 pccbb_winlist_insert(head, start, size, bsh, flags) 2948 struct pccbb_win_chain_head *head; 2949 bus_addr_t start; 2950 bus_size_t size; 2951 bus_space_handle_t bsh; 2952 int flags; 2953 { 2954 struct pccbb_win_chain *chainp, *elem; 2955 2956 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2957 M_NOWAIT)) == NULL) 2958 return (1); /* fail */ 2959 2960 elem->wc_start = start; 2961 elem->wc_end = start + (size - 1); 2962 elem->wc_handle = bsh; 2963 elem->wc_flags = flags; 2964 2965 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2966 chainp = TAILQ_NEXT(chainp, wc_list)) { 2967 if (chainp->wc_end < start) 2968 continue; 2969 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2970 return (0); 2971 } 2972 2973 TAILQ_INSERT_TAIL(head, elem, wc_list); 2974 return (0); 2975 } 2976 2977 static int 2978 pccbb_winlist_delete(head, bsh, size) 2979 struct pccbb_win_chain_head *head; 2980 bus_space_handle_t bsh; 2981 bus_size_t size; 2982 { 2983 struct pccbb_win_chain *chainp; 2984 2985 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2986 chainp = TAILQ_NEXT(chainp, wc_list)) { 2987 if (chainp->wc_handle != bsh) 2988 continue; 2989 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2990 printf("pccbb_winlist_delete: window 0x%lx size " 2991 "inconsistent: 0x%lx, 0x%lx\n", 2992 chainp->wc_start, 2993 chainp->wc_end - chainp->wc_start, 2994 size - 1); 2995 return 1; 2996 } 2997 2998 TAILQ_REMOVE(head, chainp, wc_list); 2999 free(chainp, M_DEVBUF); 3000 3001 return 0; 3002 } 3003 3004 return 1; /* fail: no candidate to remove */ 3005 } 3006 3007 static void 3008 pccbb_winset(align, sc, bst) 3009 bus_addr_t align; 3010 struct pccbb_softc *sc; 3011 bus_space_tag_t bst; 3012 { 3013 pci_chipset_tag_t pc; 3014 pcitag_t tag; 3015 bus_addr_t mask = ~(align - 1); 3016 struct { 3017 cardbusreg_t win_start; 3018 cardbusreg_t win_limit; 3019 int win_flags; 3020 } win[2]; 3021 struct pccbb_win_chain *chainp; 3022 int offs; 3023 3024 win[0].win_start = 0xffffffff; 3025 win[0].win_limit = 0; 3026 win[1].win_start = 0xffffffff; 3027 win[1].win_limit = 0; 3028 3029 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3030 offs = 0x2c; 3031 if (sc->sc_memt == bst) { 3032 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3033 offs = 0x1c; 3034 } 3035 3036 if (chainp != NULL) { 3037 win[0].win_start = chainp->wc_start & mask; 3038 win[0].win_limit = chainp->wc_end & mask; 3039 win[0].win_flags = chainp->wc_flags; 3040 chainp = TAILQ_NEXT(chainp, wc_list); 3041 } 3042 3043 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3044 if (win[1].win_start == 0xffffffff) { 3045 /* window 1 is not used */ 3046 if ((win[0].win_flags == chainp->wc_flags) && 3047 (win[0].win_limit + align >= 3048 (chainp->wc_start & mask))) { 3049 /* concatenate */ 3050 win[0].win_limit = chainp->wc_end & mask; 3051 } else { 3052 /* make new window */ 3053 win[1].win_start = chainp->wc_start & mask; 3054 win[1].win_limit = chainp->wc_end & mask; 3055 win[1].win_flags = chainp->wc_flags; 3056 } 3057 continue; 3058 } 3059 3060 /* Both windows are engaged. */ 3061 if (win[0].win_flags == win[1].win_flags) { 3062 /* same flags */ 3063 if (win[0].win_flags == chainp->wc_flags) { 3064 if (win[1].win_start - (win[0].win_limit + 3065 align) < 3066 (chainp->wc_start & mask) - 3067 ((chainp->wc_end & mask) + align)) { 3068 /* 3069 * merge window 0 and 1, and set win1 3070 * to chainp 3071 */ 3072 win[0].win_limit = win[1].win_limit; 3073 win[1].win_start = 3074 chainp->wc_start & mask; 3075 win[1].win_limit = 3076 chainp->wc_end & mask; 3077 } else { 3078 win[1].win_limit = 3079 chainp->wc_end & mask; 3080 } 3081 } else { 3082 /* different flags */ 3083 3084 /* concatenate win0 and win1 */ 3085 win[0].win_limit = win[1].win_limit; 3086 /* allocate win[1] to new space */ 3087 win[1].win_start = chainp->wc_start & mask; 3088 win[1].win_limit = chainp->wc_end & mask; 3089 win[1].win_flags = chainp->wc_flags; 3090 } 3091 } else { 3092 /* the flags of win[0] and win[1] is different */ 3093 if (win[0].win_flags == chainp->wc_flags) { 3094 win[0].win_limit = chainp->wc_end & mask; 3095 /* 3096 * XXX this creates overlapping windows, so 3097 * what should the poor bridge do if one is 3098 * cachable, and the other is not? 3099 */ 3100 printf("%s: overlapping windows\n", 3101 sc->sc_dev.dv_xname); 3102 } else { 3103 win[1].win_limit = chainp->wc_end & mask; 3104 } 3105 } 3106 } 3107 3108 pc = sc->sc_pc; 3109 tag = sc->sc_tag; 3110 pci_conf_write(pc, tag, offs, win[0].win_start); 3111 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3112 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3113 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3114 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3115 pci_conf_read(pc, tag, offs), 3116 pci_conf_read(pc, tag, offs + 4) + align, 3117 pci_conf_read(pc, tag, offs + 8), 3118 pci_conf_read(pc, tag, offs + 12) + align)); 3119 3120 if (bst == sc->sc_memt) { 3121 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3122 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3123 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3124 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3125 } 3126 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3127 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3128 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3129 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3130 } 3131 } 3132 } 3133 3134 #endif /* rbus */ 3135 3136 static void 3137 pccbb_powerhook(why, arg) 3138 int why; 3139 void *arg; 3140 { 3141 struct pccbb_softc *sc = arg; 3142 u_int32_t reg; 3143 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3144 bus_space_handle_t base_memh = sc->sc_base_memh; 3145 3146 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3147 3148 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3149 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3150 if (sc->sc_pil_intr_enable) { 3151 (void)pccbbintr_function(sc); 3152 } 3153 sc->sc_pil_intr_enable = 0; 3154 3155 /* ToDo: deactivate or suspend child devices */ 3156 3157 } 3158 3159 if (why == PWR_RESUME) { 3160 /* CSC Interrupt: Card detect interrupt on */ 3161 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3162 /* Card detect intr is turned on. */ 3163 reg |= CB_SOCKET_MASK_CD; 3164 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3165 /* reset interrupt */ 3166 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3167 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3168 3169 /* 3170 * check for card insertion or removal during suspend period. 3171 * XXX: the code can't cope with card swap (remove then 3172 * insert). how can we detect such situation? 3173 */ 3174 (void)pccbbintr(sc); 3175 3176 sc->sc_pil_intr_enable = 1; 3177 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3178 3179 /* ToDo: activate or wakeup child devices */ 3180 } 3181 } 3182
Indexes created Sat Sep 27 22:09:54 GMT 2025