pccbb.c revision 1.49
1 /* $NetBSD: pccbb.c,v 1.49 2000/12/08 10:24:14 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 93 void pccbbattach __P((struct device *, struct device *, void *)); 94 int pccbbintr __P((void *)); 95 static void pci113x_insert __P((void *)); 96 static int pccbbintr_function __P((struct pccbb_softc *)); 97 98 static int pccbb_detect_card __P((struct pccbb_softc *)); 99 100 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 101 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 102 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 103 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 104 105 STATIC int cb_reset __P((struct pccbb_softc *)); 106 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 107 STATIC int cbbprint __P((void *, const char *)); 108 109 static int cb_chipset __P((u_int32_t, int *)); 110 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 111 struct pcmciabus_attach_args *)); 112 #if 0 113 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 114 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 115 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 116 #endif 117 118 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 119 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 120 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 121 #if !rbus 122 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 123 u_int32_t)); 124 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 125 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 126 u_int32_t)); 127 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 128 #endif /* !rbus */ 129 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 130 int level, int (*ih) (void *), void *sc)); 131 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 132 133 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 static void pccbb_powerhook __P((int, void *)); 171 172 /* bus-space allocation and deallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 178 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t)); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 187 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t)); 189 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int)); 191 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 192 bus_space_handle_t, bus_size_t)); 193 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t)); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback __P((struct device *)); 201 202 #if defined SHOW_REGS 203 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 204 bus_space_tag_t memt, bus_space_handle_t memh)); 205 #endif 206 207 struct cfattach cbb_pci_ca = { 208 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 209 }; 210 211 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 212 pccbb_pcmcia_mem_alloc, 213 pccbb_pcmcia_mem_free, 214 pccbb_pcmcia_mem_map, 215 pccbb_pcmcia_mem_unmap, 216 pccbb_pcmcia_io_alloc, 217 pccbb_pcmcia_io_free, 218 pccbb_pcmcia_io_map, 219 pccbb_pcmcia_io_unmap, 220 pccbb_pcmcia_intr_establish, 221 pccbb_pcmcia_intr_disestablish, 222 pccbb_pcmcia_socket_enable, 223 pccbb_pcmcia_socket_disable, 224 pccbb_pcmcia_card_detect 225 }; 226 227 #if rbus 228 static struct cardbus_functions pccbb_funcs = { 229 pccbb_rbus_cb_space_alloc, 230 pccbb_rbus_cb_space_free, 231 pccbb_cb_intr_establish, 232 pccbb_cb_intr_disestablish, 233 pccbb_ctrl, 234 pccbb_power, 235 pccbb_make_tag, 236 pccbb_free_tag, 237 pccbb_conf_read, 238 pccbb_conf_write, 239 }; 240 #else 241 static struct cardbus_functions pccbb_funcs = { 242 pccbb_ctrl, 243 pccbb_power, 244 pccbb_mem_open, 245 pccbb_mem_close, 246 pccbb_io_open, 247 pccbb_io_close, 248 pccbb_cb_intr_establish, 249 pccbb_cb_intr_disestablish, 250 pccbb_make_tag, 251 pccbb_conf_read, 252 pccbb_conf_write, 253 }; 254 #endif 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 struct cfdata *match; 260 void *aux; 261 { 262 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 263 264 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 265 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 266 PCI_INTERFACE(pa->pa_class) == 0) { 267 return 1; 268 } 269 270 return 0; 271 } 272 273 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 274 | ((prod) << PCI_PRODUCT_SHIFT)) 275 276 struct yenta_chipinfo { 277 pcireg_t yc_id; /* vendor tag | product tag */ 278 int yc_chiptype; 279 int yc_flags; 280 } yc_chipsets[] = { 281 /* Texas Instruments chips */ 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 307 /* Ricoh chips */ 308 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 309 PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 311 PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 313 PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 315 PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 319 PCCBB_PCMCIA_MEM_32}, 320 321 /* Toshiba products */ 322 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 323 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 325 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 327 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 329 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 330 331 /* Cirrus Logic products */ 332 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 333 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 335 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 336 337 /* sentinel, or Generic chip */ 338 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 339 }; 340 341 static int 342 cb_chipset(pci_id, flagp) 343 u_int32_t pci_id; 344 int *flagp; 345 { 346 struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return (yc->yc_chiptype); 358 } 359 360 static void 361 pccbb_shutdown(void *arg) 362 { 363 struct pccbb_softc *sc = arg; 364 pcireg_t command; 365 366 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 367 368 /* 369 * turn off power 370 * 371 * XXX - do not turn off power if chipset is TI 113X because 372 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 373 */ 374 if (sc->sc_chipset != CB_TI113X) { 375 pccbb_power((cardbus_chipset_tag_t)sc, 376 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 377 } 378 379 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 380 0); 381 382 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 383 384 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 385 PCI_COMMAND_MASTER_ENABLE); 386 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 387 388 } 389 390 void 391 pccbbattach(parent, self, aux) 392 struct device *parent; 393 struct device *self; 394 void *aux; 395 { 396 struct pccbb_softc *sc = (void *)self; 397 struct pci_attach_args *pa = aux; 398 pci_chipset_tag_t pc = pa->pa_pc; 399 pcireg_t busreg, reg, sock_base; 400 bus_addr_t sockbase; 401 char devinfo[256]; 402 int flags; 403 404 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 405 406 pci_devinfo(pa->pa_id, 0, 0, devinfo); 407 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 408 #ifdef CBB_DEBUG 409 printf(" (chipflags %x)", flags); 410 #endif 411 printf("\n"); 412 413 TAILQ_INIT(&sc->sc_memwindow); 414 TAILQ_INIT(&sc->sc_iowindow); 415 416 #if rbus 417 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 418 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 419 #endif /* rbus */ 420 421 sc->sc_base_memh = 0; 422 423 /* 424 * MAP socket registers and ExCA registers on memory-space 425 * When no valid address is set on socket base registers (on pci 426 * config space), get it not polite way. 427 */ 428 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 429 430 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 431 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 432 /* The address must be valid. */ 433 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 434 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 435 printf("%s: can't map socket base address 0x%x\n", 436 sc->sc_dev.dv_xname, sock_base); 437 /* 438 * I think it's funny: socket base registers must be 439 * mapped on memory space, but ... 440 */ 441 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 442 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 443 NULL)) { 444 printf("%s: can't map socket base address" 445 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 446 sockbase); 447 /* give up... allocate reg space via rbus. */ 448 sc->sc_base_memh = 0; 449 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 450 } 451 } else { 452 DPRINTF(("%s: socket base address 0x%lx\n", 453 sc->sc_dev.dv_xname, sockbase)); 454 } 455 } 456 457 sc->sc_mem_start = 0; /* XXX */ 458 sc->sc_mem_end = 0xffffffff; /* XXX */ 459 460 /* 461 * When interrupt isn't routed correctly, give up probing cbb and do 462 * not kill pcic-compatible port. 463 */ 464 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 465 printf("%s: NOT USED because of unconfigured interrupt\n", 466 sc->sc_dev.dv_xname); 467 return; 468 } 469 470 /* 471 * When bus number isn't set correctly, give up using 32-bit CardBus 472 * mode. 473 */ 474 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 475 #if notyet 476 if (((busreg >> 8) & 0xff) == 0) { 477 printf("%s: CardBus support disabled because of unconfigured bus number\n", 478 sc->sc_dev.dv_xname); 479 flags |= PCCBB_PCMCIA_16BITONLY; 480 } 481 #endif 482 483 /* pccbb_machdep.c end */ 484 485 #if defined CBB_DEBUG 486 { 487 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 488 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 489 intrname[pa->pa_intrpin], pa->pa_intrline); 490 } 491 #endif 492 493 /* setup softc */ 494 sc->sc_pc = pc; 495 sc->sc_iot = pa->pa_iot; 496 sc->sc_memt = pa->pa_memt; 497 sc->sc_dmat = pa->pa_dmat; 498 sc->sc_tag = pa->pa_tag; 499 sc->sc_function = pa->pa_function; 500 501 sc->sc_intrline = pa->pa_intrline; 502 sc->sc_intrtag = pa->pa_intrtag; 503 sc->sc_intrpin = pa->pa_intrpin; 504 505 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 506 507 shutdownhook_establish(pccbb_shutdown, sc); 508 509 /* Disable legacy register mapping. */ 510 switch (sc->sc_chipset) { 511 case CB_RX5C46X: /* fallthrough */ 512 #if 0 513 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 514 case CB_RX5C47X: 515 #endif 516 /* 517 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 518 * cannot be disabled by substituting 0 into PCI_LEGACY 519 * register. Ricoh CardBus bridges have special bits on Bridge 520 * control reg (addr 0x3e on PCI config space). 521 */ 522 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 523 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 524 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 525 break; 526 527 default: 528 /* XXX I don't know proper way to kill legacy I/O. */ 529 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 530 break; 531 } 532 533 config_defer(self, pccbb_pci_callback); 534 } 535 536 537 538 539 /* 540 * static void pccbb_pci_callback(struct device *self) 541 * 542 * The actual attach routine: get memory space for YENTA register 543 * space, setup YENTA register and route interrupt. 544 * 545 * This function should be deferred because this device may obtain 546 * memory space dynamically. This function must avoid obtaining 547 * memory area which has already kept for another device. 548 */ 549 static void 550 pccbb_pci_callback(self) 551 struct device *self; 552 { 553 struct pccbb_softc *sc = (void *)self; 554 pci_chipset_tag_t pc = sc->sc_pc; 555 bus_space_tag_t base_memt; 556 bus_space_handle_t base_memh; 557 u_int32_t maskreg; 558 pci_intr_handle_t ih; 559 const char *intrstr = NULL; 560 bus_addr_t sockbase; 561 struct cbslot_attach_args cba; 562 struct pcmciabus_attach_args paa; 563 struct cardslot_attach_args caa; 564 struct cardslot_softc *csc; 565 566 if (0 == sc->sc_base_memh) { 567 /* The socket registers aren't mapped correctly. */ 568 #if rbus 569 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 570 (sc->sc_chipset == CB_RX5C47X 571 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 572 0, &sockbase, &sc->sc_base_memh)) { 573 return; 574 } 575 sc->sc_base_memt = sc->sc_memt; 576 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 577 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 578 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 579 PCI_SOCKBASE))); 580 #else 581 sc->sc_base_memt = sc->sc_memt; 582 #if !defined CBB_PCI_BASE 583 #define CBB_PCI_BASE 0x20000000 584 #endif 585 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 586 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 587 /* cannot allocate memory space */ 588 return; 589 } 590 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 591 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 592 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 593 sc->sc_tag, PCI_SOCKBASE))); 594 #endif 595 } 596 597 /* bus bridge initialization */ 598 pccbb_chipinit(sc); 599 600 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 601 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 602 603 /* CSC Interrupt: Card detect interrupt on */ 604 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 605 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 606 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 607 /* reset interrupt */ 608 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 609 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 610 611 /* clear data structure for child device interrupt handlers */ 612 sc->sc_pil = NULL; 613 sc->sc_pil_intr_enable = 1; 614 615 /* Map and establish the interrupt. */ 616 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 617 sc->sc_intrline, &ih)) { 618 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 619 return; 620 } 621 intrstr = pci_intr_string(pc, ih); 622 623 /* 624 * XXX pccbbintr should be called under the priority lower 625 * than any other hard interrputs. 626 */ 627 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 628 629 if (sc->sc_ih == NULL) { 630 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 631 if (intrstr != NULL) { 632 printf(" at %s", intrstr); 633 } 634 printf("\n"); 635 return; 636 } 637 638 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 639 powerhook_establish(pccbb_powerhook, sc); 640 641 { 642 u_int32_t sockstat = 643 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 644 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 645 sc->sc_flags |= CBB_CARDEXIST; 646 } 647 } 648 649 /* 650 * attach cardbus 651 */ 652 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 653 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 654 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 655 656 /* initialize cbslot_attach */ 657 cba.cba_busname = "cardbus"; 658 cba.cba_iot = sc->sc_iot; 659 cba.cba_memt = sc->sc_memt; 660 cba.cba_dmat = sc->sc_dmat; 661 cba.cba_bus = (busreg >> 8) & 0x0ff; 662 cba.cba_cc = (void *)sc; 663 cba.cba_cf = &pccbb_funcs; 664 cba.cba_intrline = sc->sc_intrline; 665 666 #if rbus 667 cba.cba_rbus_iot = sc->sc_rbus_iot; 668 cba.cba_rbus_memt = sc->sc_rbus_memt; 669 #endif 670 671 cba.cba_cacheline = PCI_CACHELINE(bhlc); 672 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 673 674 printf("%s: cacheline 0x%x lattimer 0x%x\n", 675 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 676 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 677 busreg); 678 #if defined SHOW_REGS 679 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 680 sc->sc_base_memh); 681 #endif 682 } 683 684 pccbb_pcmcia_attach_setup(sc, &paa); 685 caa.caa_cb_attach = NULL; 686 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 687 caa.caa_cb_attach = &cba; 688 } 689 caa.caa_16_attach = &paa; 690 caa.caa_ph = &sc->sc_pcmcia_h; 691 692 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 693 DPRINTF(("pccbbattach: found cardslot\n")); 694 sc->sc_csc = csc; 695 } 696 697 return; 698 } 699 700 701 702 703 704 /* 705 * static void pccbb_chipinit(struct pccbb_softc *sc) 706 * 707 * This function initialize YENTA chip registers listed below: 708 * 1) PCI command reg, 709 * 2) PCI and CardBus latency timer, 710 * 3) route PCI interrupt, 711 * 4) close all memory and io windows. 712 */ 713 static void 714 pccbb_chipinit(sc) 715 struct pccbb_softc *sc; 716 { 717 pci_chipset_tag_t pc = sc->sc_pc; 718 pcitag_t tag = sc->sc_tag; 719 pcireg_t reg; 720 721 /* 722 * Set PCI command reg. 723 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 724 */ 725 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 726 /* I believe it is harmless. */ 727 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 728 PCI_COMMAND_MASTER_ENABLE); 729 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 730 731 /* 732 * Set CardBus latency timer. 733 */ 734 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 735 if (PCI_CB_LATENCY(reg) < 0x20) { 736 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 737 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 738 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 739 } 740 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 741 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 742 743 /* 744 * Set PCI latency timer. 745 */ 746 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 747 if (PCI_LATTIMER(reg) < 0x10) { 748 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 749 reg |= (0x10 << PCI_LATTIMER_SHIFT); 750 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 751 } 752 DPRINTF(("PCI latency timer 0x%x (%x)\n", 753 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 754 755 756 /* Route functional interrupts to PCI. */ 757 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 758 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 759 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 760 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 761 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 762 763 switch (sc->sc_chipset) { 764 case CB_TI113X: 765 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 766 /* This bit is shared, but may read as 0 on some chips, so set 767 it explicitly on both functions. */ 768 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 769 /* CSC intr enable */ 770 reg |= PCI113X_CBCTRL_PCI_CSC; 771 /* functional intr prohibit | prohibit ISA routing */ 772 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 773 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 774 break; 775 776 case CB_TOPIC95B: 777 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 778 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 779 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 780 781 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 782 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 783 sc->sc_dev.dv_xname, reg)); 784 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 785 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 786 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 787 DPRINTF(("0x%x\n", reg)); 788 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 789 break; 790 } 791 792 /* Close all memory and I/O windows. */ 793 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 794 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 795 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 796 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 797 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 798 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 799 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 800 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 801 802 /* reset 16-bit pcmcia bus */ 803 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 804 0x800 + PCIC_INTR, 805 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 806 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 807 808 /* turn of power */ 809 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 810 } 811 812 813 814 815 /* 816 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 817 * struct pcmciabus_attach_args *paa) 818 * 819 * This function attaches 16-bit PCcard bus. 820 */ 821 STATIC void 822 pccbb_pcmcia_attach_setup(sc, paa) 823 struct pccbb_softc *sc; 824 struct pcmciabus_attach_args *paa; 825 { 826 struct pcic_handle *ph = &sc->sc_pcmcia_h; 827 #if rbus 828 rbus_tag_t rb; 829 #endif 830 831 /* initialize pcmcia part in pccbb_softc */ 832 ph->ph_parent = (struct device *)sc; 833 ph->sock = sc->sc_function; 834 ph->flags = 0; 835 ph->shutdown = 0; 836 ph->ih_irq = sc->sc_intrline; 837 ph->ph_bus_t = sc->sc_base_memt; 838 ph->ph_bus_h = sc->sc_base_memh; 839 ph->ph_read = pccbb_pcmcia_read; 840 ph->ph_write = pccbb_pcmcia_write; 841 sc->sc_pct = &pccbb_pcmcia_funcs; 842 843 /* 844 * We need to do a few things here: 845 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 846 * setting the IRQ numbers to 0. 847 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 848 * routing of CSC interrupts (e.g. card removal) to PCI while in 849 * PCMCIA mode. We just leave this set all the time. 850 * 3) Enable card insertion/removal interrupts in case the chip also 851 * needs that while in PCMCIA mode. 852 * 4) Clear any pending CSC interrupt. 853 */ 854 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 855 if (sc->sc_chipset == CB_TI113X) { 856 Pcic_write(ph, PCIC_CSC_INTR, 0); 857 } else { 858 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 859 Pcic_read(ph, PCIC_CSC); 860 } 861 862 /* initialize pcmcia bus attachment */ 863 paa->paa_busname = "pcmcia"; 864 paa->pct = sc->sc_pct; 865 paa->pch = ph; 866 paa->iobase = 0; /* I don't use them */ 867 paa->iosize = 0; 868 #if rbus 869 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 870 paa->iobase = rb->rb_start + rb->rb_offset; 871 paa->iosize = rb->rb_end - rb->rb_start; 872 #endif 873 874 return; 875 } 876 877 #if 0 878 STATIC void 879 pccbb_pcmcia_attach_card(ph) 880 struct pcic_handle *ph; 881 { 882 if (ph->flags & PCIC_FLAG_CARDP) { 883 panic("pccbb_pcmcia_attach_card: already attached"); 884 } 885 886 /* call the MI attach function */ 887 pcmcia_card_attach(ph->pcmcia); 888 889 ph->flags |= PCIC_FLAG_CARDP; 890 } 891 892 STATIC void 893 pccbb_pcmcia_detach_card(ph, flags) 894 struct pcic_handle *ph; 895 int flags; 896 { 897 if (!(ph->flags & PCIC_FLAG_CARDP)) { 898 panic("pccbb_pcmcia_detach_card: already detached"); 899 } 900 901 ph->flags &= ~PCIC_FLAG_CARDP; 902 903 /* call the MI detach function */ 904 pcmcia_card_detach(ph->pcmcia, flags); 905 } 906 #endif 907 908 /* 909 * int pccbbintr(arg) 910 * void *arg; 911 * This routine handles the interrupt from Yenta PCI-CardBus bridge 912 * itself. 913 */ 914 int 915 pccbbintr(arg) 916 void *arg; 917 { 918 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 919 u_int32_t sockevent, sockstate; 920 bus_space_tag_t memt = sc->sc_base_memt; 921 bus_space_handle_t memh = sc->sc_base_memh; 922 struct pcic_handle *ph = &sc->sc_pcmcia_h; 923 924 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 925 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 926 Pcic_read(ph, PCIC_CSC); 927 928 if (sockevent == 0) { 929 /* This intr is not for me: it may be for my child devices. */ 930 if (sc->sc_pil_intr_enable) { 931 return pccbbintr_function(sc); 932 } else { 933 return 0; 934 } 935 } 936 937 if (sockevent & CB_SOCKET_EVENT_CD) { 938 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 939 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 940 /* A card should be removed. */ 941 if (sc->sc_flags & CBB_CARDEXIST) { 942 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 943 sockevent)); 944 DPRINTF((" card removed, 0x%08x\n", sockstate)); 945 sc->sc_flags &= ~CBB_CARDEXIST; 946 if (sc->sc_csc->sc_status & 947 CARDSLOT_STATUS_CARD_16) { 948 #if 0 949 struct pcic_handle *ph = 950 &sc->sc_pcmcia_h; 951 952 pcmcia_card_deactivate(ph->pcmcia); 953 pccbb_pcmcia_socket_disable(ph); 954 pccbb_pcmcia_detach_card(ph, 955 DETACH_FORCE); 956 #endif 957 cardslot_event_throw(sc->sc_csc, 958 CARDSLOT_EVENT_REMOVAL_16); 959 } else if (sc->sc_csc->sc_status & 960 CARDSLOT_STATUS_CARD_CB) { 961 /* Cardbus intr removed */ 962 cardslot_event_throw(sc->sc_csc, 963 CARDSLOT_EVENT_REMOVAL_CB); 964 } 965 } 966 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 967 /* 968 * The pccbbintr may called from powerdown hook when 969 * the system resumed, to detect the card 970 * insertion/removal during suspension. 971 */ 972 (sc->sc_flags & CBB_CARDEXIST) == 0) { 973 if (sc->sc_flags & CBB_INSERTING) { 974 callout_stop(&sc->sc_insert_ch); 975 } 976 callout_reset(&sc->sc_insert_ch, hz / 10, 977 pci113x_insert, sc); 978 sc->sc_flags |= CBB_INSERTING; 979 } 980 } 981 982 return (1); 983 } 984 985 /* 986 * static int pccbbintr_function(struct pccbb_softc *sc) 987 * 988 * This function calls each interrupt handler registered at the 989 * bridge. The interrupt handlers are called in registered order. 990 */ 991 static int 992 pccbbintr_function(sc) 993 struct pccbb_softc *sc; 994 { 995 int retval = 0, val; 996 struct pccbb_intrhand_list *pil; 997 int s, splchanged; 998 999 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1000 /* 1001 * XXX priority change. gross. I use if-else 1002 * sentense instead of switch-case sentense because of 1003 * avoiding duplicate case value error. More than one 1004 * IPL_XXX use same value. It depends on 1005 * implimentation. 1006 */ 1007 splchanged = 1; 1008 if (pil->pil_level == IPL_SERIAL) { 1009 s = splserial(); 1010 } else if (pil->pil_level == IPL_HIGH) { 1011 s = splhigh(); 1012 } else if (pil->pil_level == IPL_CLOCK) { 1013 s = splclock(); 1014 } else if (pil->pil_level == IPL_AUDIO) { 1015 s = splaudio(); 1016 } else if (pil->pil_level == IPL_IMP) { 1017 s = splimp(); 1018 } else if (pil->pil_level == IPL_TTY) { 1019 s = spltty(); 1020 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1021 s = splsoftserial(); 1022 } else if (pil->pil_level == IPL_NET) { 1023 s = splnet(); 1024 } else { 1025 splchanged = 0; 1026 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1027 } 1028 1029 val = (*pil->pil_func)(pil->pil_arg); 1030 1031 if (splchanged != 0) { 1032 splx(s); 1033 } 1034 1035 retval = retval == 1 ? 1 : 1036 retval == 0 ? val : val != 0 ? val : retval; 1037 } 1038 1039 return retval; 1040 } 1041 1042 static void 1043 pci113x_insert(arg) 1044 void *arg; 1045 { 1046 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1047 u_int32_t sockevent, sockstate; 1048 1049 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1050 CB_SOCKET_EVENT); 1051 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1052 CB_SOCKET_STAT); 1053 1054 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1055 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1056 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1057 sc->sc_flags |= CBB_CARDEXIST; 1058 /* call pccard interrupt handler here */ 1059 if (sockstate & CB_SOCKET_STAT_16BIT) { 1060 /* 16-bit card found */ 1061 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1062 cardslot_event_throw(sc->sc_csc, 1063 CARDSLOT_EVENT_INSERTION_16); 1064 } else if (sockstate & CB_SOCKET_STAT_CB) { 1065 /* cardbus card found */ 1066 /* cardbus_attach_card(sc->sc_csc); */ 1067 cardslot_event_throw(sc->sc_csc, 1068 CARDSLOT_EVENT_INSERTION_CB); 1069 } else { 1070 /* who are you? */ 1071 } 1072 } else { 1073 callout_reset(&sc->sc_insert_ch, hz / 10, 1074 pci113x_insert, sc); 1075 } 1076 } 1077 1078 #define PCCBB_PCMCIA_OFFSET 0x800 1079 static u_int8_t 1080 pccbb_pcmcia_read(ph, reg) 1081 struct pcic_handle *ph; 1082 int reg; 1083 { 1084 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1085 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1086 1087 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1088 PCCBB_PCMCIA_OFFSET + reg); 1089 } 1090 1091 static void 1092 pccbb_pcmcia_write(ph, reg, val) 1093 struct pcic_handle *ph; 1094 int reg; 1095 u_int8_t val; 1096 { 1097 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1098 val); 1099 1100 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1101 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1102 } 1103 1104 /* 1105 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1106 */ 1107 STATIC int 1108 pccbb_ctrl(ct, command) 1109 cardbus_chipset_tag_t ct; 1110 int command; 1111 { 1112 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1113 1114 switch (command) { 1115 case CARDBUS_CD: 1116 if (2 == pccbb_detect_card(sc)) { 1117 int retval = 0; 1118 int status = cb_detect_voltage(sc); 1119 if (PCCARD_VCC_5V & status) { 1120 retval |= CARDBUS_5V_CARD; 1121 } 1122 if (PCCARD_VCC_3V & status) { 1123 retval |= CARDBUS_3V_CARD; 1124 } 1125 if (PCCARD_VCC_XV & status) { 1126 retval |= CARDBUS_XV_CARD; 1127 } 1128 if (PCCARD_VCC_YV & status) { 1129 retval |= CARDBUS_YV_CARD; 1130 } 1131 return retval; 1132 } else { 1133 return 0; 1134 } 1135 break; 1136 case CARDBUS_RESET: 1137 return cb_reset(sc); 1138 break; 1139 case CARDBUS_IO_ENABLE: /* fallthrough */ 1140 case CARDBUS_IO_DISABLE: /* fallthrough */ 1141 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1142 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1143 case CARDBUS_BM_ENABLE: /* fallthrough */ 1144 case CARDBUS_BM_DISABLE: /* fallthrough */ 1145 return pccbb_cardenable(sc, command); 1146 break; 1147 } 1148 1149 return 0; 1150 } 1151 1152 /* 1153 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1154 * This function returns true when it succeeds and returns false when 1155 * it fails. 1156 */ 1157 STATIC int 1158 pccbb_power(ct, command) 1159 cardbus_chipset_tag_t ct; 1160 int command; 1161 { 1162 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1163 1164 u_int32_t status, sock_ctrl; 1165 bus_space_tag_t memt = sc->sc_base_memt; 1166 bus_space_handle_t memh = sc->sc_base_memh; 1167 1168 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1169 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1170 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1171 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1172 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1173 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1174 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1175 "UNKNOWN", 1176 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1177 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1178 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1179 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1180 "UNKNOWN", command)); 1181 1182 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1183 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1184 1185 switch (command & CARDBUS_VCCMASK) { 1186 case CARDBUS_VCC_UC: 1187 break; 1188 case CARDBUS_VCC_5V: 1189 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1190 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1191 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1192 } else { 1193 printf("%s: BAD voltage request: no 5 V card\n", 1194 sc->sc_dev.dv_xname); 1195 } 1196 break; 1197 case CARDBUS_VCC_3V: 1198 if (CB_SOCKET_STAT_3VCARD & status) { 1199 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1200 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1201 } else { 1202 printf("%s: BAD voltage request: no 3.3 V card\n", 1203 sc->sc_dev.dv_xname); 1204 } 1205 break; 1206 case CARDBUS_VCC_0V: 1207 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1208 break; 1209 default: 1210 return 0; /* power NEVER changed */ 1211 break; 1212 } 1213 1214 switch (command & CARDBUS_VPPMASK) { 1215 case CARDBUS_VPP_UC: 1216 break; 1217 case CARDBUS_VPP_0V: 1218 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1219 break; 1220 case CARDBUS_VPP_VCC: 1221 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1222 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1223 break; 1224 case CARDBUS_VPP_12V: 1225 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1226 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1227 break; 1228 } 1229 1230 #if 0 1231 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1232 #endif 1233 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1234 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1235 1236 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1237 printf 1238 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1239 sc->sc_dev.dv_xname, sock_ctrl, status); 1240 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1241 (command & CARDBUS_VCCMASK) == 1242 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1243 CARDBUS_VCCMASK) == 1244 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1245 CARDBUS_VCCMASK) == 1246 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1247 CARDBUS_VCCMASK) == 1248 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1249 CARDBUS_VCCMASK) == 1250 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1251 CARDBUS_VCCMASK) == 1252 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1253 (command & CARDBUS_VPPMASK) == 1254 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1255 CARDBUS_VPPMASK) == 1256 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1257 CARDBUS_VPPMASK) == 1258 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1259 CARDBUS_VPPMASK) == 1260 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1261 #if 0 1262 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1263 u_int32_t force = 1264 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1265 /* Reset Bad Vcc request */ 1266 force &= ~CB_SOCKET_FORCE_BADVCC; 1267 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1268 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1269 CB_SOCKET_STAT)); 1270 return 1; 1271 } 1272 #endif 1273 return 0; 1274 } 1275 1276 /* 1277 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1278 * time is 20 ms, some PC-Card bridge requires longer duration. 1279 */ 1280 delay(300 * 1000); 1281 1282 return 1; /* power changed correctly */ 1283 } 1284 1285 #if defined CB_PCMCIA_POLL 1286 struct cb_poll_str { 1287 void *arg; 1288 int (*func) __P((void *)); 1289 int level; 1290 pccard_chipset_tag_t ct; 1291 int count; 1292 struct callout poll_ch; 1293 }; 1294 1295 static struct cb_poll_str cb_poll[10]; 1296 static int cb_poll_n = 0; 1297 1298 static void cb_pcmcia_poll __P((void *arg)); 1299 1300 static void 1301 cb_pcmcia_poll(arg) 1302 void *arg; 1303 { 1304 struct cb_poll_str *poll = arg; 1305 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1306 struct pccbb_softc *sc = psc->cpc_parent; 1307 int s; 1308 u_int32_t spsr; /* socket present-state reg */ 1309 1310 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1311 switch (poll->level) { 1312 case IPL_NET: 1313 s = splnet(); 1314 break; 1315 case IPL_BIO: 1316 s = splbio(); 1317 break; 1318 case IPL_TTY: /* fallthrough */ 1319 default: 1320 s = spltty(); 1321 break; 1322 } 1323 1324 spsr = 1325 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1326 CB_SOCKET_STAT); 1327 1328 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1329 if (!(spsr & 0x40)) { /* CINT low */ 1330 #else 1331 if (1) { 1332 #endif 1333 if ((*poll->func) (poll->arg) == 1) { 1334 ++poll->count; 1335 printf("intr: reported from poller, 0x%x\n", spsr); 1336 #if defined LEVEL2 1337 } else { 1338 printf("intr: miss! 0x%x\n", spsr); 1339 #endif 1340 } 1341 } 1342 splx(s); 1343 } 1344 #endif /* defined CB_PCMCIA_POLL */ 1345 1346 /* 1347 * static int pccbb_detect_card(struct pccbb_softc *sc) 1348 * return value: 0 if no card exists. 1349 * 1 if 16-bit card exists. 1350 * 2 if cardbus card exists. 1351 */ 1352 static int 1353 pccbb_detect_card(sc) 1354 struct pccbb_softc *sc; 1355 { 1356 bus_space_handle_t base_memh = sc->sc_base_memh; 1357 bus_space_tag_t base_memt = sc->sc_base_memt; 1358 u_int32_t sockstat = 1359 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1360 int retval = 0; 1361 1362 /* CD1 and CD2 asserted */ 1363 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1364 /* card must be present */ 1365 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1366 /* NOTACARD DEASSERTED */ 1367 if (CB_SOCKET_STAT_CB & sockstat) { 1368 /* CardBus mode */ 1369 retval = 2; 1370 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1371 /* 16-bit mode */ 1372 retval = 1; 1373 } 1374 } 1375 } 1376 return retval; 1377 } 1378 1379 /* 1380 * STATIC int cb_reset(struct pccbb_softc *sc) 1381 * This function resets CardBus card. 1382 */ 1383 STATIC int 1384 cb_reset(sc) 1385 struct pccbb_softc *sc; 1386 { 1387 /* 1388 * Reset Assert at least 20 ms 1389 * Some machines request longer duration. 1390 */ 1391 int reset_duration = 1392 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1393 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1394 1395 /* Reset bit Assert (bit 6 at 0x3E) */ 1396 bcr |= CB_BCR_RESET_ENABLE; 1397 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1398 delay(reset_duration); 1399 1400 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1401 /* Reset bit Deassert (bit 6 at 0x3E) */ 1402 bcr &= ~CB_BCR_RESET_ENABLE; 1403 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1404 delay(reset_duration); 1405 } 1406 /* No card found on the slot. Keep Reset. */ 1407 return 1; 1408 } 1409 1410 /* 1411 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1412 * This function detect card Voltage. 1413 */ 1414 STATIC int 1415 cb_detect_voltage(sc) 1416 struct pccbb_softc *sc; 1417 { 1418 u_int32_t psr; /* socket present-state reg */ 1419 bus_space_tag_t iot = sc->sc_base_memt; 1420 bus_space_handle_t ioh = sc->sc_base_memh; 1421 int vol = PCCARD_VCC_UKN; /* set 0 */ 1422 1423 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1424 1425 if (0x400u & psr) { 1426 vol |= PCCARD_VCC_5V; 1427 } 1428 if (0x800u & psr) { 1429 vol |= PCCARD_VCC_3V; 1430 } 1431 1432 return vol; 1433 } 1434 1435 STATIC int 1436 cbbprint(aux, pcic) 1437 void *aux; 1438 const char *pcic; 1439 { 1440 /* 1441 struct cbslot_attach_args *cba = aux; 1442 1443 if (cba->cba_slot >= 0) { 1444 printf(" slot %d", cba->cba_slot); 1445 } 1446 */ 1447 return UNCONF; 1448 } 1449 1450 /* 1451 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1452 * This function enables and disables the card 1453 */ 1454 STATIC int 1455 pccbb_cardenable(sc, function) 1456 struct pccbb_softc *sc; 1457 int function; 1458 { 1459 u_int32_t command = 1460 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1461 1462 DPRINTF(("pccbb_cardenable:")); 1463 switch (function) { 1464 case CARDBUS_IO_ENABLE: 1465 command |= PCI_COMMAND_IO_ENABLE; 1466 break; 1467 case CARDBUS_IO_DISABLE: 1468 command &= ~PCI_COMMAND_IO_ENABLE; 1469 break; 1470 case CARDBUS_MEM_ENABLE: 1471 command |= PCI_COMMAND_MEM_ENABLE; 1472 break; 1473 case CARDBUS_MEM_DISABLE: 1474 command &= ~PCI_COMMAND_MEM_ENABLE; 1475 break; 1476 case CARDBUS_BM_ENABLE: 1477 command |= PCI_COMMAND_MASTER_ENABLE; 1478 break; 1479 case CARDBUS_BM_DISABLE: 1480 command &= ~PCI_COMMAND_MASTER_ENABLE; 1481 break; 1482 default: 1483 return 0; 1484 } 1485 1486 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1487 DPRINTF((" command reg 0x%x\n", command)); 1488 return 1; 1489 } 1490 1491 #if !rbus 1492 /* 1493 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1494 */ 1495 static int 1496 pccbb_io_open(ct, win, start, end) 1497 cardbus_chipset_tag_t ct; 1498 int win; 1499 u_int32_t start, end; 1500 { 1501 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1502 int basereg; 1503 int limitreg; 1504 1505 if ((win < 0) || (win > 2)) { 1506 #if defined DIAGNOSTIC 1507 printf("cardbus_io_open: window out of range %d\n", win); 1508 #endif 1509 return 0; 1510 } 1511 1512 basereg = win * 8 + 0x2c; 1513 limitreg = win * 8 + 0x30; 1514 1515 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1516 start, basereg, end, limitreg)); 1517 1518 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1519 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1520 return 1; 1521 } 1522 1523 /* 1524 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1525 */ 1526 static int 1527 pccbb_io_close(ct, win) 1528 cardbus_chipset_tag_t ct; 1529 int win; 1530 { 1531 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1532 int basereg; 1533 int limitreg; 1534 1535 if ((win < 0) || (win > 2)) { 1536 #if defined DIAGNOSTIC 1537 printf("cardbus_io_close: window out of range %d\n", win); 1538 #endif 1539 return 0; 1540 } 1541 1542 basereg = win * 8 + 0x2c; 1543 limitreg = win * 8 + 0x30; 1544 1545 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1546 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1547 return 1; 1548 } 1549 1550 /* 1551 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1552 */ 1553 static int 1554 pccbb_mem_open(ct, win, start, end) 1555 cardbus_chipset_tag_t ct; 1556 int win; 1557 u_int32_t start, end; 1558 { 1559 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1560 int basereg; 1561 int limitreg; 1562 1563 if ((win < 0) || (win > 2)) { 1564 #if defined DIAGNOSTIC 1565 printf("cardbus_mem_open: window out of range %d\n", win); 1566 #endif 1567 return 0; 1568 } 1569 1570 basereg = win * 8 + 0x1c; 1571 limitreg = win * 8 + 0x20; 1572 1573 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1574 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1575 return 1; 1576 } 1577 1578 /* 1579 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1580 */ 1581 static int 1582 pccbb_mem_close(ct, win) 1583 cardbus_chipset_tag_t ct; 1584 int win; 1585 { 1586 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1587 int basereg; 1588 int limitreg; 1589 1590 if ((win < 0) || (win > 2)) { 1591 #if defined DIAGNOSTIC 1592 printf("cardbus_mem_close: window out of range %d\n", win); 1593 #endif 1594 return 0; 1595 } 1596 1597 basereg = win * 8 + 0x1c; 1598 limitreg = win * 8 + 0x20; 1599 1600 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1601 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1602 return 1; 1603 } 1604 #endif 1605 1606 /* 1607 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1608 * int irq, 1609 * int level, 1610 * int (* func) __P((void *)), 1611 * void *arg) 1612 * 1613 * This function registers an interrupt handler at the bridge, in 1614 * order not to call the interrupt handlers of child devices when 1615 * a card-deletion interrupt occurs. 1616 * 1617 * The arguments irq and level are not used. 1618 */ 1619 static void * 1620 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1621 cardbus_chipset_tag_t ct; 1622 int irq, level; 1623 int (*func) __P((void *)); 1624 void *arg; 1625 { 1626 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1627 1628 return pccbb_intr_establish(sc, irq, level, func, arg); 1629 } 1630 1631 1632 /* 1633 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1634 * void *ih) 1635 * 1636 * This function removes an interrupt handler pointed by ih. 1637 */ 1638 static void 1639 pccbb_cb_intr_disestablish(ct, ih) 1640 cardbus_chipset_tag_t ct; 1641 void *ih; 1642 { 1643 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1644 1645 pccbb_intr_disestablish(sc, ih); 1646 } 1647 1648 1649 /* 1650 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1651 * int irq, 1652 * int level, 1653 * int (* func) __P((void *)), 1654 * void *arg) 1655 * 1656 * This function registers an interrupt handler at the bridge, in 1657 * order not to call the interrupt handlers of child devices when 1658 * a card-deletion interrupt occurs. 1659 * 1660 * The arguments irq is not used because pccbb selects intr vector. 1661 */ 1662 static void * 1663 pccbb_intr_establish(sc, irq, level, func, arg) 1664 struct pccbb_softc *sc; 1665 int irq, level; 1666 int (*func) __P((void *)); 1667 void *arg; 1668 { 1669 struct pccbb_intrhand_list *pil, *newpil; 1670 pcireg_t reg; 1671 1672 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1673 1674 if (sc->sc_pil == NULL) { 1675 /* initialize bridge intr routing */ 1676 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1677 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1678 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1679 1680 switch (sc->sc_chipset) { 1681 case CB_TI113X: 1682 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1683 /* functional intr enabled */ 1684 reg |= PCI113X_CBCTRL_PCI_INTR; 1685 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1686 break; 1687 default: 1688 break; 1689 } 1690 } 1691 1692 /* 1693 * Allocate a room for interrupt handler structure. 1694 */ 1695 if (NULL == (newpil = 1696 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1697 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1698 return NULL; 1699 } 1700 1701 newpil->pil_func = func; 1702 newpil->pil_arg = arg; 1703 newpil->pil_level = level; 1704 newpil->pil_next = NULL; 1705 1706 if (sc->sc_pil == NULL) { 1707 sc->sc_pil = newpil; 1708 } else { 1709 for (pil = sc->sc_pil; pil->pil_next != NULL; 1710 pil = pil->pil_next); 1711 pil->pil_next = newpil; 1712 } 1713 1714 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1715 1716 return newpil; 1717 } 1718 1719 /* 1720 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1721 * void *ih) 1722 * 1723 * This function removes an interrupt handler pointed by ih. 1724 */ 1725 static void 1726 pccbb_intr_disestablish(sc, ih) 1727 struct pccbb_softc *sc; 1728 void *ih; 1729 { 1730 struct pccbb_intrhand_list *pil, **pil_prev; 1731 pcireg_t reg; 1732 1733 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1734 1735 pil_prev = &sc->sc_pil; 1736 1737 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1738 if (pil == ih) { 1739 *pil_prev = pil->pil_next; 1740 free(pil, M_DEVBUF); 1741 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1742 break; 1743 } 1744 pil_prev = &pil->pil_next; 1745 } 1746 1747 if (sc->sc_pil == NULL) { 1748 /* No interrupt handlers */ 1749 1750 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1751 1752 /* stop routing PCI intr */ 1753 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1754 reg |= CB_BCR_INTR_IREQ_ENABLE; 1755 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1756 1757 switch (sc->sc_chipset) { 1758 case CB_TI113X: 1759 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1760 /* functional intr disabled */ 1761 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1762 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1763 break; 1764 default: 1765 break; 1766 } 1767 } 1768 } 1769 1770 #if defined SHOW_REGS 1771 static void 1772 cb_show_regs(pc, tag, memt, memh) 1773 pci_chipset_tag_t pc; 1774 pcitag_t tag; 1775 bus_space_tag_t memt; 1776 bus_space_handle_t memh; 1777 { 1778 int i; 1779 printf("PCI config regs:"); 1780 for (i = 0; i < 0x50; i += 4) { 1781 if (i % 16 == 0) { 1782 printf("\n 0x%02x:", i); 1783 } 1784 printf(" %08x", pci_conf_read(pc, tag, i)); 1785 } 1786 for (i = 0x80; i < 0xb0; i += 4) { 1787 if (i % 16 == 0) { 1788 printf("\n 0x%02x:", i); 1789 } 1790 printf(" %08x", pci_conf_read(pc, tag, i)); 1791 } 1792 1793 if (memh == 0) { 1794 printf("\n"); 1795 return; 1796 } 1797 1798 printf("\nsocket regs:"); 1799 for (i = 0; i <= 0x10; i += 0x04) { 1800 printf(" %08x", bus_space_read_4(memt, memh, i)); 1801 } 1802 printf("\nExCA regs:"); 1803 for (i = 0; i < 0x08; ++i) { 1804 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1805 } 1806 printf("\n"); 1807 return; 1808 } 1809 #endif 1810 1811 /* 1812 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1813 * int busno, int devno, int function) 1814 * This is the function to make a tag to access config space of 1815 * a CardBus Card. It works same as pci_conf_read. 1816 */ 1817 static cardbustag_t 1818 pccbb_make_tag(cc, busno, devno, function) 1819 cardbus_chipset_tag_t cc; 1820 int busno, devno, function; 1821 { 1822 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1823 1824 return pci_make_tag(sc->sc_pc, busno, devno, function); 1825 } 1826 1827 static void 1828 pccbb_free_tag(cc, tag) 1829 cardbus_chipset_tag_t cc; 1830 cardbustag_t tag; 1831 { 1832 } 1833 1834 /* 1835 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1836 * cardbustag_t tag, int offset) 1837 * This is the function to read the config space of a CardBus Card. 1838 * It works same as pci_conf_read. 1839 */ 1840 static cardbusreg_t 1841 pccbb_conf_read(cc, tag, offset) 1842 cardbus_chipset_tag_t cc; 1843 cardbustag_t tag; 1844 int offset; /* register offset */ 1845 { 1846 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1847 1848 return pci_conf_read(sc->sc_pc, tag, offset); 1849 } 1850 1851 /* 1852 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1853 * int offs, cardbusreg_t val) 1854 * This is the function to write the config space of a CardBus Card. 1855 * It works same as pci_conf_write. 1856 */ 1857 static void 1858 pccbb_conf_write(cc, tag, reg, val) 1859 cardbus_chipset_tag_t cc; 1860 cardbustag_t tag; 1861 int reg; /* register offset */ 1862 cardbusreg_t val; 1863 { 1864 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1865 1866 pci_conf_write(sc->sc_pc, tag, reg, val); 1867 } 1868 1869 #if 0 1870 STATIC int 1871 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1872 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1873 int speed, int flags, 1874 bus_space_handle_t * iohp) 1875 #endif 1876 /* 1877 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1878 * bus_addr_t start, bus_size_t size, 1879 * bus_size_t align, 1880 * struct pcmcia_io_handle *pcihp 1881 * 1882 * This function only allocates I/O region for pccard. This function 1883 * never maps the allocated region to pccard I/O area. 1884 * 1885 * XXX: The interface of this function is not very good, I believe. 1886 */ 1887 STATIC int 1888 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1889 pcmcia_chipset_handle_t pch; 1890 bus_addr_t start; /* start address */ 1891 bus_size_t size; 1892 bus_size_t align; 1893 struct pcmcia_io_handle *pcihp; 1894 { 1895 struct pcic_handle *ph = (struct pcic_handle *)pch; 1896 bus_addr_t ioaddr; 1897 int flags = 0; 1898 bus_space_tag_t iot; 1899 bus_space_handle_t ioh; 1900 #if rbus 1901 rbus_tag_t rb; 1902 #endif 1903 if (align == 0) { 1904 align = size; /* XXX: funny??? */ 1905 } 1906 1907 /* 1908 * Allocate some arbitrary I/O space. 1909 */ 1910 1911 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1912 1913 #if rbus 1914 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1915 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1916 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1917 return 1; 1918 } 1919 #else 1920 if (start) { 1921 ioaddr = start; 1922 if (bus_space_map(iot, start, size, 0, &ioh)) { 1923 return 1; 1924 } 1925 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1926 (u_long) ioaddr, (u_long) size)); 1927 } else { 1928 flags |= PCMCIA_IO_ALLOCATED; 1929 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1930 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1931 size, align, 0, 0, &ioaddr, &ioh)) { 1932 /* No room be able to be get. */ 1933 return 1; 1934 } 1935 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1936 (u_long) ioaddr, (u_long) size)); 1937 } 1938 #endif 1939 1940 pcihp->iot = iot; 1941 pcihp->ioh = ioh; 1942 pcihp->addr = ioaddr; 1943 pcihp->size = size; 1944 pcihp->flags = flags; 1945 1946 return 0; 1947 } 1948 1949 /* 1950 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1951 * struct pcmcia_io_handle *pcihp) 1952 * 1953 * This function only frees I/O region for pccard. 1954 * 1955 * XXX: The interface of this function is not very good, I believe. 1956 */ 1957 void 1958 pccbb_pcmcia_io_free(pch, pcihp) 1959 pcmcia_chipset_handle_t pch; 1960 struct pcmcia_io_handle *pcihp; 1961 { 1962 #if !rbus 1963 bus_space_tag_t iot = pcihp->iot; 1964 #endif 1965 bus_space_handle_t ioh = pcihp->ioh; 1966 bus_size_t size = pcihp->size; 1967 1968 #if rbus 1969 struct pccbb_softc *sc = 1970 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1971 rbus_tag_t rb = sc->sc_rbus_iot; 1972 1973 rbus_space_free(rb, ioh, size, NULL); 1974 #else 1975 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1976 bus_space_free(iot, ioh, size); 1977 else 1978 bus_space_unmap(iot, ioh, size); 1979 #endif 1980 } 1981 1982 /* 1983 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1984 * bus_addr_t offset, bus_size_t size, 1985 * struct pcmcia_io_handle *pcihp, 1986 * int *windowp) 1987 * 1988 * This function maps the allocated I/O region to pccard. This function 1989 * never allocates any I/O region for pccard I/O area. I don't 1990 * understand why the original authors of pcmciabus separated alloc and 1991 * map. I believe the two must be unite. 1992 * 1993 * XXX: no wait timing control? 1994 */ 1995 int 1996 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1997 pcmcia_chipset_handle_t pch; 1998 int width; 1999 bus_addr_t offset; 2000 bus_size_t size; 2001 struct pcmcia_io_handle *pcihp; 2002 int *windowp; 2003 { 2004 struct pcic_handle *ph = (struct pcic_handle *)pch; 2005 bus_addr_t ioaddr = pcihp->addr + offset; 2006 int i, win; 2007 #if defined CBB_DEBUG 2008 static char *width_names[] = { "dynamic", "io8", "io16" }; 2009 #endif 2010 2011 /* Sanity check I/O handle. */ 2012 2013 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2014 panic("pccbb_pcmcia_io_map iot is bogus"); 2015 } 2016 2017 /* XXX Sanity check offset/size. */ 2018 2019 win = -1; 2020 for (i = 0; i < PCIC_IO_WINS; i++) { 2021 if ((ph->ioalloc & (1 << i)) == 0) { 2022 win = i; 2023 ph->ioalloc |= (1 << i); 2024 break; 2025 } 2026 } 2027 2028 if (win == -1) { 2029 return 1; 2030 } 2031 2032 *windowp = win; 2033 2034 /* XXX this is pretty gross */ 2035 2036 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2037 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2038 2039 /* XXX wtf is this doing here? */ 2040 2041 #if 0 2042 printf(" port 0x%lx", (u_long) ioaddr); 2043 if (size > 1) { 2044 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2045 } 2046 #endif 2047 2048 ph->io[win].addr = ioaddr; 2049 ph->io[win].size = size; 2050 ph->io[win].width = width; 2051 2052 /* actual dirty register-value changing in the function below. */ 2053 pccbb_pcmcia_do_io_map(ph, win); 2054 2055 return 0; 2056 } 2057 2058 /* 2059 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2060 * 2061 * This function changes register-value to map I/O region for pccard. 2062 */ 2063 static void 2064 pccbb_pcmcia_do_io_map(ph, win) 2065 struct pcic_handle *ph; 2066 int win; 2067 { 2068 static u_int8_t pcic_iowidth[3] = { 2069 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2070 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2071 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2072 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2073 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2074 }; 2075 2076 #define PCIC_SIA_START_LOW 0 2077 #define PCIC_SIA_START_HIGH 1 2078 #define PCIC_SIA_STOP_LOW 2 2079 #define PCIC_SIA_STOP_HIGH 3 2080 2081 int regbase_win = 0x8 + win * 0x04; 2082 u_int8_t ioctl, enable; 2083 2084 DPRINTF( 2085 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2086 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2087 ph->io[win].width * 8)); 2088 2089 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2090 ph->io[win].addr & 0xff); 2091 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2092 (ph->io[win].addr >> 8) & 0xff); 2093 2094 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2095 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2096 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2097 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2098 2099 ioctl = Pcic_read(ph, PCIC_IOCTL); 2100 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2101 switch (win) { 2102 case 0: 2103 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2104 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2105 PCIC_IOCTL_IO0_DATASIZE_MASK); 2106 ioctl |= pcic_iowidth[ph->io[win].width]; 2107 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2108 break; 2109 case 1: 2110 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2111 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2112 PCIC_IOCTL_IO1_DATASIZE_MASK); 2113 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2114 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2115 break; 2116 } 2117 Pcic_write(ph, PCIC_IOCTL, ioctl); 2118 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2119 #if defined CBB_DEBUG 2120 { 2121 u_int8_t start_low = 2122 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2123 u_int8_t start_high = 2124 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2125 u_int8_t stop_low = 2126 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2127 u_int8_t stop_high = 2128 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2129 printf 2130 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2131 start_low, start_high, stop_low, stop_high, ioctl, enable); 2132 } 2133 #endif 2134 } 2135 2136 /* 2137 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2138 * 2139 * This function unmaps I/O region. No return value. 2140 */ 2141 STATIC void 2142 pccbb_pcmcia_io_unmap(pch, win) 2143 pcmcia_chipset_handle_t pch; 2144 int win; 2145 { 2146 struct pcic_handle *ph = (struct pcic_handle *)pch; 2147 int reg; 2148 2149 if (win >= PCIC_IO_WINS || win < 0) { 2150 panic("pccbb_pcmcia_io_unmap: window out of range"); 2151 } 2152 2153 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2154 switch (win) { 2155 case 0: 2156 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2157 break; 2158 case 1: 2159 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2160 break; 2161 } 2162 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2163 2164 ph->ioalloc &= ~(1 << win); 2165 } 2166 2167 /* 2168 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2169 * 2170 * This function enables the card. All information is stored in 2171 * the first argument, pcmcia_chipset_handle_t. 2172 */ 2173 static void 2174 pccbb_pcmcia_wait_ready(ph) 2175 struct pcic_handle *ph; 2176 { 2177 int i; 2178 2179 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2180 Pcic_read(ph, PCIC_IF_STATUS))); 2181 2182 for (i = 0; i < 10000; i++) { 2183 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2184 return; 2185 } 2186 delay(500); 2187 #ifdef CBB_DEBUG 2188 if ((i > 5000) && (i % 100 == 99)) 2189 printf("."); 2190 #endif 2191 } 2192 2193 #ifdef DIAGNOSTIC 2194 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2195 Pcic_read(ph, PCIC_IF_STATUS)); 2196 #endif 2197 } 2198 2199 /* 2200 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2201 * 2202 * This function enables the card. All information is stored in 2203 * the first argument, pcmcia_chipset_handle_t. 2204 */ 2205 STATIC void 2206 pccbb_pcmcia_socket_enable(pch) 2207 pcmcia_chipset_handle_t pch; 2208 { 2209 struct pcic_handle *ph = (struct pcic_handle *)pch; 2210 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2211 int cardtype, win; 2212 u_int8_t power, intr; 2213 pcireg_t spsr; 2214 int voltage; 2215 2216 /* this bit is mostly stolen from pcic_attach_card */ 2217 2218 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2219 2220 /* get card Vcc info */ 2221 2222 spsr = 2223 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2224 CB_SOCKET_STAT); 2225 if (spsr & CB_SOCKET_STAT_5VCARD) { 2226 DPRINTF(("5V card\n")); 2227 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2228 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2229 DPRINTF(("3V card\n")); 2230 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2231 } else { 2232 printf("?V card, 0x%x\n", spsr); /* XXX */ 2233 return; 2234 } 2235 2236 /* disable socket i/o: negate output enable bit */ 2237 2238 power = 0; 2239 Pcic_write(ph, PCIC_PWRCTL, power); 2240 2241 /* power down the socket to reset it, clear the card reset pin */ 2242 2243 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2244 2245 /* 2246 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2247 * we are changing Vcc (Toff). 2248 */ 2249 /* delay(300*1000); too much */ 2250 2251 /* assert reset bit */ 2252 intr = Pcic_read(ph, PCIC_INTR); 2253 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2254 Pcic_write(ph, PCIC_INTR, intr); 2255 2256 /* power up the socket and output enable */ 2257 power = Pcic_read(ph, PCIC_PWRCTL); 2258 power |= PCIC_PWRCTL_OE; 2259 Pcic_write(ph, PCIC_PWRCTL, power); 2260 pccbb_power(sc, voltage); 2261 2262 /* 2263 * hold RESET at least 10us. 2264 */ 2265 delay(10); 2266 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2267 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2268 2269 /* clear the reset flag */ 2270 2271 intr |= PCIC_INTR_RESET; 2272 Pcic_write(ph, PCIC_INTR, intr); 2273 2274 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2275 2276 delay(20000); 2277 2278 /* wait for the chip to finish initializing */ 2279 2280 pccbb_pcmcia_wait_ready(ph); 2281 2282 /* zero out the address windows */ 2283 2284 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2285 2286 /* set the card type */ 2287 2288 cardtype = pcmcia_card_gettype(ph->pcmcia); 2289 2290 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2291 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2292 Pcic_write(ph, PCIC_INTR, intr); 2293 2294 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2295 ph->ph_parent->dv_xname, ph->sock, 2296 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2297 2298 /* reinstall all the memory and io mappings */ 2299 2300 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2301 if (ph->memalloc & (1 << win)) { 2302 pccbb_pcmcia_do_mem_map(ph, win); 2303 } 2304 } 2305 2306 for (win = 0; win < PCIC_IO_WINS; ++win) { 2307 if (ph->ioalloc & (1 << win)) { 2308 pccbb_pcmcia_do_io_map(ph, win); 2309 } 2310 } 2311 } 2312 2313 /* 2314 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2315 * 2316 * This function disables the card. All information is stored in 2317 * the first argument, pcmcia_chipset_handle_t. 2318 */ 2319 STATIC void 2320 pccbb_pcmcia_socket_disable(pch) 2321 pcmcia_chipset_handle_t pch; 2322 { 2323 struct pcic_handle *ph = (struct pcic_handle *)pch; 2324 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2325 u_int8_t power, intr; 2326 2327 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2328 2329 /* reset signal asserting... */ 2330 2331 intr = Pcic_read(ph, PCIC_INTR); 2332 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2333 Pcic_write(ph, PCIC_INTR, intr); 2334 delay(2 * 1000); 2335 2336 /* power down the socket */ 2337 power = Pcic_read(ph, PCIC_PWRCTL); 2338 power &= ~PCIC_PWRCTL_OE; 2339 Pcic_write(ph, PCIC_PWRCTL, power); 2340 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2341 /* 2342 * wait 300ms until power fails (Tpf). 2343 */ 2344 delay(300 * 1000); 2345 } 2346 2347 /* 2348 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2349 * 2350 * This function detects whether a card is in the slot or not. 2351 * If a card is inserted, return 1. Otherwise, return 0. 2352 */ 2353 STATIC int 2354 pccbb_pcmcia_card_detect(pch) 2355 pcmcia_chipset_handle_t pch; 2356 { 2357 struct pcic_handle *ph = (struct pcic_handle *)pch; 2358 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2359 2360 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2361 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2362 } 2363 2364 #if 0 2365 STATIC int 2366 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2367 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2368 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2369 #endif 2370 /* 2371 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2372 * bus_size_t size, 2373 * struct pcmcia_mem_handle *pcmhp) 2374 * 2375 * This function only allocates memory region for pccard. This 2376 * function never maps the allocated region to pccard memory area. 2377 * 2378 * XXX: Why the argument of start address is not in? 2379 */ 2380 STATIC int 2381 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2382 pcmcia_chipset_handle_t pch; 2383 bus_size_t size; 2384 struct pcmcia_mem_handle *pcmhp; 2385 { 2386 struct pcic_handle *ph = (struct pcic_handle *)pch; 2387 bus_space_handle_t memh; 2388 bus_addr_t addr; 2389 bus_size_t sizepg; 2390 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2391 #if rbus 2392 rbus_tag_t rb; 2393 #endif 2394 2395 /* out of sc->memh, allocate as many pages as necessary */ 2396 2397 /* convert size to PCIC pages */ 2398 /* 2399 * This is not enough; when the requested region is on the page 2400 * boundaries, this may calculate wrong result. 2401 */ 2402 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2403 #if 0 2404 if (sizepg > PCIC_MAX_MEM_PAGES) { 2405 return 1; 2406 } 2407 #endif 2408 2409 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2410 return 1; 2411 } 2412 2413 addr = 0; /* XXX gcc -Wuninitialized */ 2414 2415 #if rbus 2416 rb = sc->sc_rbus_memt; 2417 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2418 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2419 &addr, &memh)) { 2420 return 1; 2421 } 2422 #else 2423 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2424 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2425 0, /* boundary */ 2426 0, /* flags */ 2427 &addr, &memh)) { 2428 return 1; 2429 } 2430 #endif 2431 2432 DPRINTF( 2433 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2434 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2435 2436 pcmhp->memt = sc->sc_memt; 2437 pcmhp->memh = memh; 2438 pcmhp->addr = addr; 2439 pcmhp->size = size; 2440 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2441 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2442 pcmhp->mhandle = 0; 2443 /* No offset??? Funny. */ 2444 2445 return 0; 2446 } 2447 2448 /* 2449 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2450 * struct pcmcia_mem_handle *pcmhp) 2451 * 2452 * This function release the memory space allocated by the function 2453 * pccbb_pcmcia_mem_alloc(). 2454 */ 2455 STATIC void 2456 pccbb_pcmcia_mem_free(pch, pcmhp) 2457 pcmcia_chipset_handle_t pch; 2458 struct pcmcia_mem_handle *pcmhp; 2459 { 2460 #if rbus 2461 struct pcic_handle *ph = (struct pcic_handle *)pch; 2462 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2463 2464 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2465 #else 2466 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2467 #endif 2468 } 2469 2470 /* 2471 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2472 * 2473 * This function release the memory space allocated by the function 2474 * pccbb_pcmcia_mem_alloc(). 2475 */ 2476 STATIC void 2477 pccbb_pcmcia_do_mem_map(ph, win) 2478 struct pcic_handle *ph; 2479 int win; 2480 { 2481 int regbase_win; 2482 bus_addr_t phys_addr; 2483 bus_addr_t phys_end; 2484 2485 #define PCIC_SMM_START_LOW 0 2486 #define PCIC_SMM_START_HIGH 1 2487 #define PCIC_SMM_STOP_LOW 2 2488 #define PCIC_SMM_STOP_HIGH 3 2489 #define PCIC_CMA_LOW 4 2490 #define PCIC_CMA_HIGH 5 2491 2492 u_int8_t start_low, start_high = 0; 2493 u_int8_t stop_low, stop_high; 2494 u_int8_t off_low, off_high; 2495 u_int8_t mem_window; 2496 int reg; 2497 2498 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2499 int mem8 = 2500 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2501 || (kind == PCMCIA_MEM_ATTR); 2502 2503 regbase_win = 0x10 + win * 0x08; 2504 2505 phys_addr = ph->mem[win].addr; 2506 phys_end = phys_addr + ph->mem[win].size; 2507 2508 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2509 phys_addr, phys_end, ph->mem[win].offset)); 2510 2511 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2512 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2513 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2514 2515 /* bit 19:12 */ 2516 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2517 /* bit 23:20 and bit 7 on */ 2518 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2519 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2520 /* bit 31:24, for 32-bit address */ 2521 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2522 2523 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2524 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2525 2526 if (((struct pccbb_softc *)ph-> 2527 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2528 Pcic_write(ph, 0x40 + win, mem_window); 2529 } 2530 2531 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2532 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2533 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2534 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2535 2536 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2537 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2538 2539 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2540 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2541 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2542 | ((kind == PCMCIA_MEM_ATTR) ? 2543 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2544 2545 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2546 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2547 2548 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2549 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2550 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2551 2552 #if defined CBB_DEBUG 2553 { 2554 int r1, r2, r3, r4, r5, r6, r7 = 0; 2555 2556 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2557 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2558 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2559 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2560 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2561 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2562 if (((struct pccbb_softc *)(ph-> 2563 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2564 r7 = Pcic_read(ph, 0x40 + win); 2565 } 2566 2567 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2568 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2569 if (((struct pccbb_softc *)(ph-> 2570 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2571 DPRINTF((" %02x", r7)); 2572 } 2573 DPRINTF(("\n")); 2574 } 2575 #endif 2576 } 2577 2578 /* 2579 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2580 * bus_addr_t card_addr, bus_size_t size, 2581 * struct pcmcia_mem_handle *pcmhp, 2582 * bus_addr_t *offsetp, int *windowp) 2583 * 2584 * This function maps memory space allocated by the function 2585 * pccbb_pcmcia_mem_alloc(). 2586 */ 2587 STATIC int 2588 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2589 pcmcia_chipset_handle_t pch; 2590 int kind; 2591 bus_addr_t card_addr; 2592 bus_size_t size; 2593 struct pcmcia_mem_handle *pcmhp; 2594 bus_addr_t *offsetp; 2595 int *windowp; 2596 { 2597 struct pcic_handle *ph = (struct pcic_handle *)pch; 2598 bus_addr_t busaddr; 2599 long card_offset; 2600 int win; 2601 2602 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2603 if ((ph->memalloc & (1 << win)) == 0) { 2604 ph->memalloc |= (1 << win); 2605 break; 2606 } 2607 } 2608 2609 if (win == PCIC_MEM_WINS) { 2610 return 1; 2611 } 2612 2613 *windowp = win; 2614 2615 /* XXX this is pretty gross */ 2616 2617 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2618 panic("pccbb_pcmcia_mem_map memt is bogus"); 2619 } 2620 2621 busaddr = pcmhp->addr; 2622 2623 /* 2624 * compute the address offset to the pcmcia address space for the 2625 * pcic. this is intentionally signed. The masks and shifts below 2626 * will cause TRT to happen in the pcic registers. Deal with making 2627 * sure the address is aligned, and return the alignment offset. 2628 */ 2629 2630 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2631 card_addr -= *offsetp; 2632 2633 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2634 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2635 (u_long) card_addr)); 2636 2637 /* 2638 * include the offset in the size, and decrement size by one, since 2639 * the hw wants start/stop 2640 */ 2641 size += *offsetp - 1; 2642 2643 card_offset = (((long)card_addr) - ((long)busaddr)); 2644 2645 ph->mem[win].addr = busaddr; 2646 ph->mem[win].size = size; 2647 ph->mem[win].offset = card_offset; 2648 ph->mem[win].kind = kind; 2649 2650 pccbb_pcmcia_do_mem_map(ph, win); 2651 2652 return 0; 2653 } 2654 2655 /* 2656 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2657 * int window) 2658 * 2659 * This function unmaps memory space which mapped by the function 2660 * pccbb_pcmcia_mem_map(). 2661 */ 2662 STATIC void 2663 pccbb_pcmcia_mem_unmap(pch, window) 2664 pcmcia_chipset_handle_t pch; 2665 int window; 2666 { 2667 struct pcic_handle *ph = (struct pcic_handle *)pch; 2668 int reg; 2669 2670 if (window >= PCIC_MEM_WINS) { 2671 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2672 } 2673 2674 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2675 reg &= ~(1 << window); 2676 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2677 2678 ph->memalloc &= ~(1 << window); 2679 } 2680 2681 #if defined PCCBB_PCMCIA_POLL 2682 struct pccbb_poll_str { 2683 void *arg; 2684 int (*func) __P((void *)); 2685 int level; 2686 struct pcic_handle *ph; 2687 int count; 2688 int num; 2689 struct callout poll_ch; 2690 }; 2691 2692 static struct pccbb_poll_str pccbb_poll[10]; 2693 static int pccbb_poll_n = 0; 2694 2695 static void pccbb_pcmcia_poll __P((void *arg)); 2696 2697 static void 2698 pccbb_pcmcia_poll(arg) 2699 void *arg; 2700 { 2701 struct pccbb_poll_str *poll = arg; 2702 struct pcic_handle *ph = poll->ph; 2703 struct pccbb_softc *sc = ph->sc; 2704 int s; 2705 u_int32_t spsr; /* socket present-state reg */ 2706 2707 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2708 switch (poll->level) { 2709 case IPL_NET: 2710 s = splnet(); 2711 break; 2712 case IPL_BIO: 2713 s = splbio(); 2714 break; 2715 case IPL_TTY: /* fallthrough */ 2716 default: 2717 s = spltty(); 2718 break; 2719 } 2720 2721 spsr = 2722 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2723 CB_SOCKET_STAT); 2724 2725 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2726 if (!(spsr & 0x40)) /* CINT low */ 2727 #else 2728 if (1) 2729 #endif 2730 { 2731 if ((*poll->func) (poll->arg) > 0) { 2732 ++poll->count; 2733 // printf("intr: reported from poller, 0x%x\n", spsr); 2734 #if defined LEVEL2 2735 } else { 2736 printf("intr: miss! 0x%x\n", spsr); 2737 #endif 2738 } 2739 } 2740 splx(s); 2741 } 2742 #endif /* defined CB_PCMCIA_POLL */ 2743 2744 /* 2745 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2746 * struct pcmcia_function *pf, 2747 * int ipl, 2748 * int (*func)(void *), 2749 * void *arg); 2750 * 2751 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2752 */ 2753 STATIC void * 2754 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2755 pcmcia_chipset_handle_t pch; 2756 struct pcmcia_function *pf; 2757 int ipl; 2758 int (*func) __P((void *)); 2759 void *arg; 2760 { 2761 struct pcic_handle *ph = (struct pcic_handle *)pch; 2762 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2763 2764 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2765 /* what should I do? */ 2766 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2767 DPRINTF( 2768 ("%s does not provide edge nor pulse interrupt\n", 2769 sc->sc_dev.dv_xname)); 2770 return NULL; 2771 } 2772 /* 2773 * XXX Noooooo! The interrupt flag must set properly!! 2774 * dumb pcmcia driver!! 2775 */ 2776 } 2777 2778 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2779 } 2780 2781 /* 2782 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2783 * void *ih) 2784 * 2785 * This function disables PC-Card interrupt. 2786 */ 2787 STATIC void 2788 pccbb_pcmcia_intr_disestablish(pch, ih) 2789 pcmcia_chipset_handle_t pch; 2790 void *ih; 2791 { 2792 struct pcic_handle *ph = (struct pcic_handle *)pch; 2793 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2794 2795 pccbb_intr_disestablish(sc, ih); 2796 } 2797 2798 #if rbus 2799 /* 2800 * static int 2801 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2802 * bus_addr_t addr, bus_size_t size, 2803 * bus_addr_t mask, bus_size_t align, 2804 * int flags, bus_addr_t *addrp; 2805 * bus_space_handle_t *bshp) 2806 * 2807 * This function allocates a portion of memory or io space for 2808 * clients. This function is called from CardBus card drivers. 2809 */ 2810 static int 2811 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2812 cardbus_chipset_tag_t ct; 2813 rbus_tag_t rb; 2814 bus_addr_t addr; 2815 bus_size_t size; 2816 bus_addr_t mask; 2817 bus_size_t align; 2818 int flags; 2819 bus_addr_t *addrp; 2820 bus_space_handle_t *bshp; 2821 { 2822 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2823 2824 DPRINTF( 2825 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2826 addr, size, mask, align)); 2827 2828 if (align == 0) { 2829 align = size; 2830 } 2831 2832 if (rb->rb_bt == sc->sc_memt) { 2833 if (align < 16) { 2834 return 1; 2835 } 2836 } else if (rb->rb_bt == sc->sc_iot) { 2837 if (align < 4) { 2838 return 1; 2839 } 2840 /* XXX: hack for avoiding ISA image */ 2841 if (mask < 0x0100) { 2842 mask = 0x3ff; 2843 addr = 0x300; 2844 } 2845 2846 } else { 2847 DPRINTF( 2848 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2849 rb->rb_bt)); 2850 return 1; 2851 /* XXX: panic here? */ 2852 } 2853 2854 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2855 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2856 return 1; 2857 } 2858 2859 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2860 2861 return 0; 2862 } 2863 2864 /* 2865 * static int 2866 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2867 * bus_space_handle_t *bshp, bus_size_t size); 2868 * 2869 * This function is called from CardBus card drivers. 2870 */ 2871 static int 2872 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2873 cardbus_chipset_tag_t ct; 2874 rbus_tag_t rb; 2875 bus_space_handle_t bsh; 2876 bus_size_t size; 2877 { 2878 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2879 bus_space_tag_t bt = rb->rb_bt; 2880 2881 pccbb_close_win(sc, bt, bsh, size); 2882 2883 if (bt == sc->sc_memt) { 2884 } else if (bt == sc->sc_iot) { 2885 } else { 2886 return 1; 2887 /* XXX: panic here? */ 2888 } 2889 2890 return rbus_space_free(rb, bsh, size, NULL); 2891 } 2892 #endif /* rbus */ 2893 2894 #if rbus 2895 2896 static int 2897 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2898 struct pccbb_softc *sc; 2899 bus_space_tag_t bst; 2900 bus_addr_t addr; 2901 bus_size_t size; 2902 bus_space_handle_t bsh; 2903 int flags; 2904 { 2905 struct pccbb_win_chain_head *head; 2906 bus_addr_t align; 2907 2908 head = &sc->sc_iowindow; 2909 align = 0x04; 2910 if (sc->sc_memt == bst) { 2911 head = &sc->sc_memwindow; 2912 align = 0x1000; 2913 DPRINTF(("using memory window, %x %x %x\n\n", 2914 sc->sc_iot, sc->sc_memt, bst)); 2915 } 2916 2917 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2918 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2919 sc->sc_dev.dv_xname, 2920 (head == &sc->sc_memwindow) ? "mem" : "io"); 2921 } 2922 pccbb_winset(align, sc, bst); 2923 2924 return 0; 2925 } 2926 2927 static int 2928 pccbb_close_win(sc, bst, bsh, size) 2929 struct pccbb_softc *sc; 2930 bus_space_tag_t bst; 2931 bus_space_handle_t bsh; 2932 bus_size_t size; 2933 { 2934 struct pccbb_win_chain_head *head; 2935 bus_addr_t align; 2936 2937 head = &sc->sc_iowindow; 2938 align = 0x04; 2939 if (sc->sc_memt == bst) { 2940 head = &sc->sc_memwindow; 2941 align = 0x1000; 2942 } 2943 2944 if (pccbb_winlist_delete(head, bsh, size)) { 2945 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2946 sc->sc_dev.dv_xname, 2947 (head == &sc->sc_memwindow) ? "mem" : "io"); 2948 } 2949 pccbb_winset(align, sc, bst); 2950 2951 return 0; 2952 } 2953 2954 static int 2955 pccbb_winlist_insert(head, start, size, bsh, flags) 2956 struct pccbb_win_chain_head *head; 2957 bus_addr_t start; 2958 bus_size_t size; 2959 bus_space_handle_t bsh; 2960 int flags; 2961 { 2962 struct pccbb_win_chain *chainp, *elem; 2963 2964 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2965 M_NOWAIT)) == NULL) 2966 return (1); /* fail */ 2967 2968 elem->wc_start = start; 2969 elem->wc_end = start + (size - 1); 2970 elem->wc_handle = bsh; 2971 elem->wc_flags = flags; 2972 2973 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2974 chainp = TAILQ_NEXT(chainp, wc_list)) { 2975 if (chainp->wc_end < start) 2976 continue; 2977 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2978 return (0); 2979 } 2980 2981 TAILQ_INSERT_TAIL(head, elem, wc_list); 2982 return (0); 2983 } 2984 2985 static int 2986 pccbb_winlist_delete(head, bsh, size) 2987 struct pccbb_win_chain_head *head; 2988 bus_space_handle_t bsh; 2989 bus_size_t size; 2990 { 2991 struct pccbb_win_chain *chainp; 2992 2993 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2994 chainp = TAILQ_NEXT(chainp, wc_list)) { 2995 if (chainp->wc_handle != bsh) 2996 continue; 2997 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2998 printf("pccbb_winlist_delete: window 0x%lx size " 2999 "inconsistent: 0x%lx, 0x%lx\n", 3000 chainp->wc_start, 3001 chainp->wc_end - chainp->wc_start, 3002 size - 1); 3003 return 1; 3004 } 3005 3006 TAILQ_REMOVE(head, chainp, wc_list); 3007 free(chainp, M_DEVBUF); 3008 3009 return 0; 3010 } 3011 3012 return 1; /* fail: no candidate to remove */ 3013 } 3014 3015 static void 3016 pccbb_winset(align, sc, bst) 3017 bus_addr_t align; 3018 struct pccbb_softc *sc; 3019 bus_space_tag_t bst; 3020 { 3021 pci_chipset_tag_t pc; 3022 pcitag_t tag; 3023 bus_addr_t mask = ~(align - 1); 3024 struct { 3025 cardbusreg_t win_start; 3026 cardbusreg_t win_limit; 3027 int win_flags; 3028 } win[2]; 3029 struct pccbb_win_chain *chainp; 3030 int offs; 3031 3032 win[0].win_start = 0xffffffff; 3033 win[0].win_limit = 0; 3034 win[1].win_start = 0xffffffff; 3035 win[1].win_limit = 0; 3036 3037 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3038 offs = 0x2c; 3039 if (sc->sc_memt == bst) { 3040 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3041 offs = 0x1c; 3042 } 3043 3044 if (chainp != NULL) { 3045 win[0].win_start = chainp->wc_start & mask; 3046 win[0].win_limit = chainp->wc_end & mask; 3047 win[0].win_flags = chainp->wc_flags; 3048 chainp = TAILQ_NEXT(chainp, wc_list); 3049 } 3050 3051 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3052 if (win[1].win_start == 0xffffffff) { 3053 /* window 1 is not used */ 3054 if ((win[0].win_flags == chainp->wc_flags) && 3055 (win[0].win_limit + align >= 3056 (chainp->wc_start & mask))) { 3057 /* concatenate */ 3058 win[0].win_limit = chainp->wc_end & mask; 3059 } else { 3060 /* make new window */ 3061 win[1].win_start = chainp->wc_start & mask; 3062 win[1].win_limit = chainp->wc_end & mask; 3063 win[1].win_flags = chainp->wc_flags; 3064 } 3065 continue; 3066 } 3067 3068 /* Both windows are engaged. */ 3069 if (win[0].win_flags == win[1].win_flags) { 3070 /* same flags */ 3071 if (win[0].win_flags == chainp->wc_flags) { 3072 if (win[1].win_start - (win[0].win_limit + 3073 align) < 3074 (chainp->wc_start & mask) - 3075 ((chainp->wc_end & mask) + align)) { 3076 /* 3077 * merge window 0 and 1, and set win1 3078 * to chainp 3079 */ 3080 win[0].win_limit = win[1].win_limit; 3081 win[1].win_start = 3082 chainp->wc_start & mask; 3083 win[1].win_limit = 3084 chainp->wc_end & mask; 3085 } else { 3086 win[1].win_limit = 3087 chainp->wc_end & mask; 3088 } 3089 } else { 3090 /* different flags */ 3091 3092 /* concatenate win0 and win1 */ 3093 win[0].win_limit = win[1].win_limit; 3094 /* allocate win[1] to new space */ 3095 win[1].win_start = chainp->wc_start & mask; 3096 win[1].win_limit = chainp->wc_end & mask; 3097 win[1].win_flags = chainp->wc_flags; 3098 } 3099 } else { 3100 /* the flags of win[0] and win[1] is different */ 3101 if (win[0].win_flags == chainp->wc_flags) { 3102 win[0].win_limit = chainp->wc_end & mask; 3103 /* 3104 * XXX this creates overlapping windows, so 3105 * what should the poor bridge do if one is 3106 * cachable, and the other is not? 3107 */ 3108 printf("%s: overlapping windows\n", 3109 sc->sc_dev.dv_xname); 3110 } else { 3111 win[1].win_limit = chainp->wc_end & mask; 3112 } 3113 } 3114 } 3115 3116 pc = sc->sc_pc; 3117 tag = sc->sc_tag; 3118 pci_conf_write(pc, tag, offs, win[0].win_start); 3119 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3120 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3121 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3122 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3123 pci_conf_read(pc, tag, offs), 3124 pci_conf_read(pc, tag, offs + 4) + align, 3125 pci_conf_read(pc, tag, offs + 8), 3126 pci_conf_read(pc, tag, offs + 12) + align)); 3127 3128 if (bst == sc->sc_memt) { 3129 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3130 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3131 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3132 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3133 } 3134 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3135 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3136 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3137 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3138 } 3139 } 3140 } 3141 3142 #endif /* rbus */ 3143 3144 static void 3145 pccbb_powerhook(why, arg) 3146 int why; 3147 void *arg; 3148 { 3149 struct pccbb_softc *sc = arg; 3150 u_int32_t reg; 3151 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3152 bus_space_handle_t base_memh = sc->sc_base_memh; 3153 3154 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3155 3156 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3157 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3158 if (sc->sc_pil_intr_enable) { 3159 (void)pccbbintr_function(sc); 3160 } 3161 sc->sc_pil_intr_enable = 0; 3162 3163 /* ToDo: deactivate or suspend child devices */ 3164 3165 } 3166 3167 if (why == PWR_RESUME) { 3168 /* CSC Interrupt: Card detect interrupt on */ 3169 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3170 /* Card detect intr is turned on. */ 3171 reg |= CB_SOCKET_MASK_CD; 3172 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3173 /* reset interrupt */ 3174 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3175 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3176 3177 /* 3178 * check for card insertion or removal during suspend period. 3179 * XXX: the code can't cope with card swap (remove then 3180 * insert). how can we detect such situation? 3181 */ 3182 (void)pccbbintr(sc); 3183 3184 sc->sc_pil_intr_enable = 1; 3185 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3186 3187 /* ToDo: activate or wakeup child devices */ 3188 } 3189 } 3190
Indexes created Sat Sep 27 14:09:57 GMT 2025