pccbb.c revision 1.50
1 /* $NetBSD: pccbb.c,v 1.50 2000/12/08 21:51:02 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 93 void pccbbattach __P((struct device *, struct device *, void *)); 94 int pccbbintr __P((void *)); 95 static void pci113x_insert __P((void *)); 96 static int pccbbintr_function __P((struct pccbb_softc *)); 97 98 static int pccbb_detect_card __P((struct pccbb_softc *)); 99 100 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 101 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 102 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 103 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 104 105 STATIC int cb_reset __P((struct pccbb_softc *)); 106 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 107 STATIC int cbbprint __P((void *, const char *)); 108 109 static int cb_chipset __P((u_int32_t, int *)); 110 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 111 struct pcmciabus_attach_args *)); 112 #if 0 113 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 114 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 115 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 116 #endif 117 118 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 119 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 120 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 121 #if !rbus 122 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 123 u_int32_t)); 124 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 125 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 126 u_int32_t)); 127 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 128 #endif /* !rbus */ 129 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 130 int level, int (*ih) (void *), void *sc)); 131 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 132 133 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 static void pccbb_powerhook __P((int, void *)); 171 172 /* bus-space allocation and deallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 178 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t)); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 187 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t)); 189 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int)); 191 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 192 bus_space_handle_t, bus_size_t)); 193 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t)); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback __P((struct device *)); 201 202 #if defined SHOW_REGS 203 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 204 bus_space_tag_t memt, bus_space_handle_t memh)); 205 #endif 206 207 struct cfattach cbb_pci_ca = { 208 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 209 }; 210 211 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 212 pccbb_pcmcia_mem_alloc, 213 pccbb_pcmcia_mem_free, 214 pccbb_pcmcia_mem_map, 215 pccbb_pcmcia_mem_unmap, 216 pccbb_pcmcia_io_alloc, 217 pccbb_pcmcia_io_free, 218 pccbb_pcmcia_io_map, 219 pccbb_pcmcia_io_unmap, 220 pccbb_pcmcia_intr_establish, 221 pccbb_pcmcia_intr_disestablish, 222 pccbb_pcmcia_socket_enable, 223 pccbb_pcmcia_socket_disable, 224 pccbb_pcmcia_card_detect 225 }; 226 227 #if rbus 228 static struct cardbus_functions pccbb_funcs = { 229 pccbb_rbus_cb_space_alloc, 230 pccbb_rbus_cb_space_free, 231 pccbb_cb_intr_establish, 232 pccbb_cb_intr_disestablish, 233 pccbb_ctrl, 234 pccbb_power, 235 pccbb_make_tag, 236 pccbb_free_tag, 237 pccbb_conf_read, 238 pccbb_conf_write, 239 }; 240 #else 241 static struct cardbus_functions pccbb_funcs = { 242 pccbb_ctrl, 243 pccbb_power, 244 pccbb_mem_open, 245 pccbb_mem_close, 246 pccbb_io_open, 247 pccbb_io_close, 248 pccbb_cb_intr_establish, 249 pccbb_cb_intr_disestablish, 250 pccbb_make_tag, 251 pccbb_conf_read, 252 pccbb_conf_write, 253 }; 254 #endif 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 struct cfdata *match; 260 void *aux; 261 { 262 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 263 264 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 265 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 266 PCI_INTERFACE(pa->pa_class) == 0) { 267 return 1; 268 } 269 270 return 0; 271 } 272 273 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 274 | ((prod) << PCI_PRODUCT_SHIFT)) 275 276 struct yenta_chipinfo { 277 pcireg_t yc_id; /* vendor tag | product tag */ 278 int yc_chiptype; 279 int yc_flags; 280 } yc_chipsets[] = { 281 /* Texas Instruments chips */ 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 307 /* Ricoh chips */ 308 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 309 PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 311 PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 313 PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 315 PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 319 PCCBB_PCMCIA_MEM_32}, 320 321 /* Toshiba products */ 322 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 323 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 325 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 327 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 329 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 330 331 /* Cirrus Logic products */ 332 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 333 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 335 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 336 337 /* sentinel, or Generic chip */ 338 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 339 }; 340 341 static int 342 cb_chipset(pci_id, flagp) 343 u_int32_t pci_id; 344 int *flagp; 345 { 346 struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return (yc->yc_chiptype); 358 } 359 360 static void 361 pccbb_shutdown(void *arg) 362 { 363 struct pccbb_softc *sc = arg; 364 pcireg_t command; 365 366 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 367 368 /* 369 * turn off power 370 * 371 * XXX - do not turn off power if chipset is TI 113X because 372 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 373 */ 374 if (sc->sc_chipset != CB_TI113X) { 375 pccbb_power((cardbus_chipset_tag_t)sc, 376 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 377 } 378 379 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 380 0); 381 382 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 383 384 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 385 PCI_COMMAND_MASTER_ENABLE); 386 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 387 388 } 389 390 void 391 pccbbattach(parent, self, aux) 392 struct device *parent; 393 struct device *self; 394 void *aux; 395 { 396 struct pccbb_softc *sc = (void *)self; 397 struct pci_attach_args *pa = aux; 398 pci_chipset_tag_t pc = pa->pa_pc; 399 pcireg_t busreg, reg, sock_base; 400 bus_addr_t sockbase; 401 char devinfo[256]; 402 int flags; 403 404 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 405 406 pci_devinfo(pa->pa_id, 0, 0, devinfo); 407 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 408 #ifdef CBB_DEBUG 409 printf(" (chipflags %x)", flags); 410 #endif 411 printf("\n"); 412 413 TAILQ_INIT(&sc->sc_memwindow); 414 TAILQ_INIT(&sc->sc_iowindow); 415 416 #if rbus 417 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 418 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 419 #endif /* rbus */ 420 421 sc->sc_base_memh = 0; 422 423 /* 424 * MAP socket registers and ExCA registers on memory-space 425 * When no valid address is set on socket base registers (on pci 426 * config space), get it not polite way. 427 */ 428 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 429 430 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 431 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 432 /* The address must be valid. */ 433 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 434 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 435 printf("%s: can't map socket base address 0x%x\n", 436 sc->sc_dev.dv_xname, sock_base); 437 /* 438 * I think it's funny: socket base registers must be 439 * mapped on memory space, but ... 440 */ 441 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 442 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 443 NULL)) { 444 printf("%s: can't map socket base address" 445 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 446 sockbase); 447 /* give up... allocate reg space via rbus. */ 448 sc->sc_base_memh = 0; 449 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 450 } 451 } else { 452 DPRINTF(("%s: socket base address 0x%lx\n", 453 sc->sc_dev.dv_xname, sockbase)); 454 } 455 } 456 457 sc->sc_mem_start = 0; /* XXX */ 458 sc->sc_mem_end = 0xffffffff; /* XXX */ 459 460 /* 461 * When interrupt isn't routed correctly, give up probing cbb and do 462 * not kill pcic-compatible port. 463 */ 464 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 465 printf("%s: NOT USED because of unconfigured interrupt\n", 466 sc->sc_dev.dv_xname); 467 return; 468 } 469 470 /* 471 * When bus number isn't set correctly, give up using 32-bit CardBus 472 * mode. 473 */ 474 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 475 #if notyet 476 if (((busreg >> 8) & 0xff) == 0) { 477 printf("%s: CardBus support disabled because of unconfigured bus number\n", 478 sc->sc_dev.dv_xname); 479 flags |= PCCBB_PCMCIA_16BITONLY; 480 } 481 #endif 482 483 /* pccbb_machdep.c end */ 484 485 #if defined CBB_DEBUG 486 { 487 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 488 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 489 intrname[pa->pa_intrpin], pa->pa_intrline); 490 } 491 #endif 492 493 /* setup softc */ 494 sc->sc_pc = pc; 495 sc->sc_iot = pa->pa_iot; 496 sc->sc_memt = pa->pa_memt; 497 sc->sc_dmat = pa->pa_dmat; 498 sc->sc_tag = pa->pa_tag; 499 sc->sc_function = pa->pa_function; 500 501 sc->sc_intrline = pa->pa_intrline; 502 sc->sc_intrtag = pa->pa_intrtag; 503 sc->sc_intrpin = pa->pa_intrpin; 504 505 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 506 507 shutdownhook_establish(pccbb_shutdown, sc); 508 509 /* Disable legacy register mapping. */ 510 switch (sc->sc_chipset) { 511 case CB_RX5C46X: /* fallthrough */ 512 #if 0 513 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 514 case CB_RX5C47X: 515 #endif 516 /* 517 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 518 * cannot be disabled by substituting 0 into PCI_LEGACY 519 * register. Ricoh CardBus bridges have special bits on Bridge 520 * control reg (addr 0x3e on PCI config space). 521 */ 522 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 523 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 524 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 525 break; 526 527 default: 528 /* XXX I don't know proper way to kill legacy I/O. */ 529 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 530 break; 531 } 532 533 config_defer(self, pccbb_pci_callback); 534 } 535 536 537 538 539 /* 540 * static void pccbb_pci_callback(struct device *self) 541 * 542 * The actual attach routine: get memory space for YENTA register 543 * space, setup YENTA register and route interrupt. 544 * 545 * This function should be deferred because this device may obtain 546 * memory space dynamically. This function must avoid obtaining 547 * memory area which has already kept for another device. 548 */ 549 static void 550 pccbb_pci_callback(self) 551 struct device *self; 552 { 553 struct pccbb_softc *sc = (void *)self; 554 pci_chipset_tag_t pc = sc->sc_pc; 555 bus_space_tag_t base_memt; 556 bus_space_handle_t base_memh; 557 u_int32_t maskreg; 558 pci_intr_handle_t ih; 559 const char *intrstr = NULL; 560 bus_addr_t sockbase; 561 struct cbslot_attach_args cba; 562 struct pcmciabus_attach_args paa; 563 struct cardslot_attach_args caa; 564 struct cardslot_softc *csc; 565 566 if (0 == sc->sc_base_memh) { 567 /* The socket registers aren't mapped correctly. */ 568 #if rbus 569 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 570 (sc->sc_chipset == CB_RX5C47X 571 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 572 0, &sockbase, &sc->sc_base_memh)) { 573 return; 574 } 575 sc->sc_base_memt = sc->sc_memt; 576 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 577 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 578 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 579 PCI_SOCKBASE))); 580 #else 581 sc->sc_base_memt = sc->sc_memt; 582 #if !defined CBB_PCI_BASE 583 #define CBB_PCI_BASE 0x20000000 584 #endif 585 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 586 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 587 /* cannot allocate memory space */ 588 return; 589 } 590 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 591 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 592 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 593 sc->sc_tag, PCI_SOCKBASE))); 594 #endif 595 } 596 597 /* bus bridge initialization */ 598 pccbb_chipinit(sc); 599 600 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 601 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 602 603 /* CSC Interrupt: Card detect interrupt on */ 604 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 605 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 606 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 607 /* reset interrupt */ 608 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 609 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 610 611 /* clear data structure for child device interrupt handlers */ 612 sc->sc_pil = NULL; 613 sc->sc_pil_intr_enable = 1; 614 615 /* Map and establish the interrupt. */ 616 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 617 sc->sc_intrline, &ih)) { 618 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 619 return; 620 } 621 intrstr = pci_intr_string(pc, ih); 622 623 /* 624 * XXX pccbbintr should be called under the priority lower 625 * than any other hard interrputs. 626 */ 627 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 628 629 if (sc->sc_ih == NULL) { 630 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 631 if (intrstr != NULL) { 632 printf(" at %s", intrstr); 633 } 634 printf("\n"); 635 return; 636 } 637 638 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 639 powerhook_establish(pccbb_powerhook, sc); 640 641 { 642 u_int32_t sockstat = 643 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 644 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 645 sc->sc_flags |= CBB_CARDEXIST; 646 } 647 } 648 649 /* 650 * attach cardbus 651 */ 652 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 653 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 654 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 655 656 /* initialize cbslot_attach */ 657 cba.cba_busname = "cardbus"; 658 cba.cba_iot = sc->sc_iot; 659 cba.cba_memt = sc->sc_memt; 660 cba.cba_dmat = sc->sc_dmat; 661 cba.cba_bus = (busreg >> 8) & 0x0ff; 662 cba.cba_cc = (void *)sc; 663 cba.cba_cf = &pccbb_funcs; 664 cba.cba_intrline = sc->sc_intrline; 665 666 #if rbus 667 cba.cba_rbus_iot = sc->sc_rbus_iot; 668 cba.cba_rbus_memt = sc->sc_rbus_memt; 669 #endif 670 671 cba.cba_cacheline = PCI_CACHELINE(bhlc); 672 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 673 674 printf("%s: cacheline 0x%x lattimer 0x%x\n", 675 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 676 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 677 busreg); 678 #if defined SHOW_REGS 679 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 680 sc->sc_base_memh); 681 #endif 682 } 683 684 pccbb_pcmcia_attach_setup(sc, &paa); 685 caa.caa_cb_attach = NULL; 686 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 687 caa.caa_cb_attach = &cba; 688 } 689 caa.caa_16_attach = &paa; 690 caa.caa_ph = &sc->sc_pcmcia_h; 691 692 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 693 DPRINTF(("pccbbattach: found cardslot\n")); 694 sc->sc_csc = csc; 695 } 696 697 return; 698 } 699 700 701 702 703 704 /* 705 * static void pccbb_chipinit(struct pccbb_softc *sc) 706 * 707 * This function initialize YENTA chip registers listed below: 708 * 1) PCI command reg, 709 * 2) PCI and CardBus latency timer, 710 * 3) route PCI interrupt, 711 * 4) close all memory and io windows. 712 */ 713 static void 714 pccbb_chipinit(sc) 715 struct pccbb_softc *sc; 716 { 717 pci_chipset_tag_t pc = sc->sc_pc; 718 pcitag_t tag = sc->sc_tag; 719 pcireg_t reg; 720 721 /* 722 * Set PCI command reg. 723 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 724 */ 725 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 726 /* I believe it is harmless. */ 727 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 728 PCI_COMMAND_MASTER_ENABLE); 729 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 730 731 /* 732 * Set CardBus latency timer. 733 */ 734 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 735 if (PCI_CB_LATENCY(reg) < 0x20) { 736 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 737 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 738 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 739 } 740 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 741 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 742 743 /* 744 * Set PCI latency timer. 745 */ 746 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 747 if (PCI_LATTIMER(reg) < 0x10) { 748 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 749 reg |= (0x10 << PCI_LATTIMER_SHIFT); 750 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 751 } 752 DPRINTF(("PCI latency timer 0x%x (%x)\n", 753 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 754 755 756 /* Route functional interrupts to PCI. */ 757 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 758 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 759 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 760 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 761 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 762 763 switch (sc->sc_chipset) { 764 case CB_TI113X: 765 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 766 /* This bit is shared, but may read as 0 on some chips, so set 767 it explicitly on both functions. */ 768 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 769 /* CSC intr enable */ 770 reg |= PCI113X_CBCTRL_PCI_CSC; 771 /* functional intr prohibit | prohibit ISA routing */ 772 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 773 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 774 break; 775 776 case CB_TI12XX: 777 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 778 reg |= PCI12XX_SYSCTRL_VCCPROT; 779 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 780 break; 781 782 case CB_TOPIC95B: 783 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 784 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 785 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 786 787 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 788 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 789 sc->sc_dev.dv_xname, reg)); 790 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 791 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 792 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 793 DPRINTF(("0x%x\n", reg)); 794 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 795 break; 796 } 797 798 /* Close all memory and I/O windows. */ 799 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 800 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 801 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 802 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 803 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 804 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 805 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 806 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 807 808 /* reset 16-bit pcmcia bus */ 809 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 810 0x800 + PCIC_INTR, 811 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 812 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 813 814 /* turn of power */ 815 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 816 } 817 818 819 820 821 /* 822 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 823 * struct pcmciabus_attach_args *paa) 824 * 825 * This function attaches 16-bit PCcard bus. 826 */ 827 STATIC void 828 pccbb_pcmcia_attach_setup(sc, paa) 829 struct pccbb_softc *sc; 830 struct pcmciabus_attach_args *paa; 831 { 832 struct pcic_handle *ph = &sc->sc_pcmcia_h; 833 #if rbus 834 rbus_tag_t rb; 835 #endif 836 837 /* initialize pcmcia part in pccbb_softc */ 838 ph->ph_parent = (struct device *)sc; 839 ph->sock = sc->sc_function; 840 ph->flags = 0; 841 ph->shutdown = 0; 842 ph->ih_irq = sc->sc_intrline; 843 ph->ph_bus_t = sc->sc_base_memt; 844 ph->ph_bus_h = sc->sc_base_memh; 845 ph->ph_read = pccbb_pcmcia_read; 846 ph->ph_write = pccbb_pcmcia_write; 847 sc->sc_pct = &pccbb_pcmcia_funcs; 848 849 /* 850 * We need to do a few things here: 851 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 852 * setting the IRQ numbers to 0. 853 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 854 * routing of CSC interrupts (e.g. card removal) to PCI while in 855 * PCMCIA mode. We just leave this set all the time. 856 * 3) Enable card insertion/removal interrupts in case the chip also 857 * needs that while in PCMCIA mode. 858 * 4) Clear any pending CSC interrupt. 859 */ 860 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 861 if (sc->sc_chipset == CB_TI113X) { 862 Pcic_write(ph, PCIC_CSC_INTR, 0); 863 } else { 864 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 865 Pcic_read(ph, PCIC_CSC); 866 } 867 868 /* initialize pcmcia bus attachment */ 869 paa->paa_busname = "pcmcia"; 870 paa->pct = sc->sc_pct; 871 paa->pch = ph; 872 paa->iobase = 0; /* I don't use them */ 873 paa->iosize = 0; 874 #if rbus 875 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 876 paa->iobase = rb->rb_start + rb->rb_offset; 877 paa->iosize = rb->rb_end - rb->rb_start; 878 #endif 879 880 return; 881 } 882 883 #if 0 884 STATIC void 885 pccbb_pcmcia_attach_card(ph) 886 struct pcic_handle *ph; 887 { 888 if (ph->flags & PCIC_FLAG_CARDP) { 889 panic("pccbb_pcmcia_attach_card: already attached"); 890 } 891 892 /* call the MI attach function */ 893 pcmcia_card_attach(ph->pcmcia); 894 895 ph->flags |= PCIC_FLAG_CARDP; 896 } 897 898 STATIC void 899 pccbb_pcmcia_detach_card(ph, flags) 900 struct pcic_handle *ph; 901 int flags; 902 { 903 if (!(ph->flags & PCIC_FLAG_CARDP)) { 904 panic("pccbb_pcmcia_detach_card: already detached"); 905 } 906 907 ph->flags &= ~PCIC_FLAG_CARDP; 908 909 /* call the MI detach function */ 910 pcmcia_card_detach(ph->pcmcia, flags); 911 } 912 #endif 913 914 /* 915 * int pccbbintr(arg) 916 * void *arg; 917 * This routine handles the interrupt from Yenta PCI-CardBus bridge 918 * itself. 919 */ 920 int 921 pccbbintr(arg) 922 void *arg; 923 { 924 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 925 u_int32_t sockevent, sockstate; 926 bus_space_tag_t memt = sc->sc_base_memt; 927 bus_space_handle_t memh = sc->sc_base_memh; 928 struct pcic_handle *ph = &sc->sc_pcmcia_h; 929 930 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 931 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 932 Pcic_read(ph, PCIC_CSC); 933 934 if (sockevent == 0) { 935 /* This intr is not for me: it may be for my child devices. */ 936 if (sc->sc_pil_intr_enable) { 937 return pccbbintr_function(sc); 938 } else { 939 return 0; 940 } 941 } 942 943 if (sockevent & CB_SOCKET_EVENT_CD) { 944 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 945 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 946 /* A card should be removed. */ 947 if (sc->sc_flags & CBB_CARDEXIST) { 948 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 949 sockevent)); 950 DPRINTF((" card removed, 0x%08x\n", sockstate)); 951 sc->sc_flags &= ~CBB_CARDEXIST; 952 if (sc->sc_csc->sc_status & 953 CARDSLOT_STATUS_CARD_16) { 954 #if 0 955 struct pcic_handle *ph = 956 &sc->sc_pcmcia_h; 957 958 pcmcia_card_deactivate(ph->pcmcia); 959 pccbb_pcmcia_socket_disable(ph); 960 pccbb_pcmcia_detach_card(ph, 961 DETACH_FORCE); 962 #endif 963 cardslot_event_throw(sc->sc_csc, 964 CARDSLOT_EVENT_REMOVAL_16); 965 } else if (sc->sc_csc->sc_status & 966 CARDSLOT_STATUS_CARD_CB) { 967 /* Cardbus intr removed */ 968 cardslot_event_throw(sc->sc_csc, 969 CARDSLOT_EVENT_REMOVAL_CB); 970 } 971 } 972 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 973 /* 974 * The pccbbintr may called from powerdown hook when 975 * the system resumed, to detect the card 976 * insertion/removal during suspension. 977 */ 978 (sc->sc_flags & CBB_CARDEXIST) == 0) { 979 if (sc->sc_flags & CBB_INSERTING) { 980 callout_stop(&sc->sc_insert_ch); 981 } 982 callout_reset(&sc->sc_insert_ch, hz / 10, 983 pci113x_insert, sc); 984 sc->sc_flags |= CBB_INSERTING; 985 } 986 } 987 988 return (1); 989 } 990 991 /* 992 * static int pccbbintr_function(struct pccbb_softc *sc) 993 * 994 * This function calls each interrupt handler registered at the 995 * bridge. The interrupt handlers are called in registered order. 996 */ 997 static int 998 pccbbintr_function(sc) 999 struct pccbb_softc *sc; 1000 { 1001 int retval = 0, val; 1002 struct pccbb_intrhand_list *pil; 1003 int s, splchanged; 1004 1005 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1006 /* 1007 * XXX priority change. gross. I use if-else 1008 * sentense instead of switch-case sentense because of 1009 * avoiding duplicate case value error. More than one 1010 * IPL_XXX use same value. It depends on 1011 * implimentation. 1012 */ 1013 splchanged = 1; 1014 if (pil->pil_level == IPL_SERIAL) { 1015 s = splserial(); 1016 } else if (pil->pil_level == IPL_HIGH) { 1017 s = splhigh(); 1018 } else if (pil->pil_level == IPL_CLOCK) { 1019 s = splclock(); 1020 } else if (pil->pil_level == IPL_AUDIO) { 1021 s = splaudio(); 1022 } else if (pil->pil_level == IPL_IMP) { 1023 s = splimp(); 1024 } else if (pil->pil_level == IPL_TTY) { 1025 s = spltty(); 1026 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1027 s = splsoftserial(); 1028 } else if (pil->pil_level == IPL_NET) { 1029 s = splnet(); 1030 } else { 1031 splchanged = 0; 1032 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1033 } 1034 1035 val = (*pil->pil_func)(pil->pil_arg); 1036 1037 if (splchanged != 0) { 1038 splx(s); 1039 } 1040 1041 retval = retval == 1 ? 1 : 1042 retval == 0 ? val : val != 0 ? val : retval; 1043 } 1044 1045 return retval; 1046 } 1047 1048 static void 1049 pci113x_insert(arg) 1050 void *arg; 1051 { 1052 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1053 u_int32_t sockevent, sockstate; 1054 1055 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1056 CB_SOCKET_EVENT); 1057 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1058 CB_SOCKET_STAT); 1059 1060 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1061 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1062 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1063 sc->sc_flags |= CBB_CARDEXIST; 1064 /* call pccard interrupt handler here */ 1065 if (sockstate & CB_SOCKET_STAT_16BIT) { 1066 /* 16-bit card found */ 1067 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1068 cardslot_event_throw(sc->sc_csc, 1069 CARDSLOT_EVENT_INSERTION_16); 1070 } else if (sockstate & CB_SOCKET_STAT_CB) { 1071 /* cardbus card found */ 1072 /* cardbus_attach_card(sc->sc_csc); */ 1073 cardslot_event_throw(sc->sc_csc, 1074 CARDSLOT_EVENT_INSERTION_CB); 1075 } else { 1076 /* who are you? */ 1077 } 1078 } else { 1079 callout_reset(&sc->sc_insert_ch, hz / 10, 1080 pci113x_insert, sc); 1081 } 1082 } 1083 1084 #define PCCBB_PCMCIA_OFFSET 0x800 1085 static u_int8_t 1086 pccbb_pcmcia_read(ph, reg) 1087 struct pcic_handle *ph; 1088 int reg; 1089 { 1090 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1091 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1092 1093 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1094 PCCBB_PCMCIA_OFFSET + reg); 1095 } 1096 1097 static void 1098 pccbb_pcmcia_write(ph, reg, val) 1099 struct pcic_handle *ph; 1100 int reg; 1101 u_int8_t val; 1102 { 1103 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1104 val); 1105 1106 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1107 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1108 } 1109 1110 /* 1111 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1112 */ 1113 STATIC int 1114 pccbb_ctrl(ct, command) 1115 cardbus_chipset_tag_t ct; 1116 int command; 1117 { 1118 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1119 1120 switch (command) { 1121 case CARDBUS_CD: 1122 if (2 == pccbb_detect_card(sc)) { 1123 int retval = 0; 1124 int status = cb_detect_voltage(sc); 1125 if (PCCARD_VCC_5V & status) { 1126 retval |= CARDBUS_5V_CARD; 1127 } 1128 if (PCCARD_VCC_3V & status) { 1129 retval |= CARDBUS_3V_CARD; 1130 } 1131 if (PCCARD_VCC_XV & status) { 1132 retval |= CARDBUS_XV_CARD; 1133 } 1134 if (PCCARD_VCC_YV & status) { 1135 retval |= CARDBUS_YV_CARD; 1136 } 1137 return retval; 1138 } else { 1139 return 0; 1140 } 1141 break; 1142 case CARDBUS_RESET: 1143 return cb_reset(sc); 1144 break; 1145 case CARDBUS_IO_ENABLE: /* fallthrough */ 1146 case CARDBUS_IO_DISABLE: /* fallthrough */ 1147 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1148 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1149 case CARDBUS_BM_ENABLE: /* fallthrough */ 1150 case CARDBUS_BM_DISABLE: /* fallthrough */ 1151 return pccbb_cardenable(sc, command); 1152 break; 1153 } 1154 1155 return 0; 1156 } 1157 1158 /* 1159 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1160 * This function returns true when it succeeds and returns false when 1161 * it fails. 1162 */ 1163 STATIC int 1164 pccbb_power(ct, command) 1165 cardbus_chipset_tag_t ct; 1166 int command; 1167 { 1168 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1169 1170 u_int32_t status, sock_ctrl; 1171 bus_space_tag_t memt = sc->sc_base_memt; 1172 bus_space_handle_t memh = sc->sc_base_memh; 1173 1174 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1175 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1176 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1177 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1178 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1179 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1180 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1181 "UNKNOWN", 1182 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1183 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1184 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1185 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1186 "UNKNOWN", command)); 1187 1188 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1189 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1190 1191 switch (command & CARDBUS_VCCMASK) { 1192 case CARDBUS_VCC_UC: 1193 break; 1194 case CARDBUS_VCC_5V: 1195 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1196 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1197 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1198 } else { 1199 printf("%s: BAD voltage request: no 5 V card\n", 1200 sc->sc_dev.dv_xname); 1201 } 1202 break; 1203 case CARDBUS_VCC_3V: 1204 if (CB_SOCKET_STAT_3VCARD & status) { 1205 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1206 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1207 } else { 1208 printf("%s: BAD voltage request: no 3.3 V card\n", 1209 sc->sc_dev.dv_xname); 1210 } 1211 break; 1212 case CARDBUS_VCC_0V: 1213 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1214 break; 1215 default: 1216 return 0; /* power NEVER changed */ 1217 break; 1218 } 1219 1220 switch (command & CARDBUS_VPPMASK) { 1221 case CARDBUS_VPP_UC: 1222 break; 1223 case CARDBUS_VPP_0V: 1224 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1225 break; 1226 case CARDBUS_VPP_VCC: 1227 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1228 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1229 break; 1230 case CARDBUS_VPP_12V: 1231 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1232 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1233 break; 1234 } 1235 1236 #if 0 1237 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1238 #endif 1239 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1240 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1241 1242 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1243 printf 1244 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1245 sc->sc_dev.dv_xname, sock_ctrl, status); 1246 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1247 (command & CARDBUS_VCCMASK) == 1248 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1249 CARDBUS_VCCMASK) == 1250 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1251 CARDBUS_VCCMASK) == 1252 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1253 CARDBUS_VCCMASK) == 1254 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1255 CARDBUS_VCCMASK) == 1256 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1257 CARDBUS_VCCMASK) == 1258 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1259 (command & CARDBUS_VPPMASK) == 1260 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1261 CARDBUS_VPPMASK) == 1262 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1263 CARDBUS_VPPMASK) == 1264 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1265 CARDBUS_VPPMASK) == 1266 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1267 #if 0 1268 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1269 u_int32_t force = 1270 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1271 /* Reset Bad Vcc request */ 1272 force &= ~CB_SOCKET_FORCE_BADVCC; 1273 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1274 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1275 CB_SOCKET_STAT)); 1276 return 1; 1277 } 1278 #endif 1279 return 0; 1280 } 1281 1282 /* 1283 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1284 * time is 20 ms, some PC-Card bridge requires longer duration. 1285 */ 1286 delay(300 * 1000); 1287 1288 return 1; /* power changed correctly */ 1289 } 1290 1291 #if defined CB_PCMCIA_POLL 1292 struct cb_poll_str { 1293 void *arg; 1294 int (*func) __P((void *)); 1295 int level; 1296 pccard_chipset_tag_t ct; 1297 int count; 1298 struct callout poll_ch; 1299 }; 1300 1301 static struct cb_poll_str cb_poll[10]; 1302 static int cb_poll_n = 0; 1303 1304 static void cb_pcmcia_poll __P((void *arg)); 1305 1306 static void 1307 cb_pcmcia_poll(arg) 1308 void *arg; 1309 { 1310 struct cb_poll_str *poll = arg; 1311 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1312 struct pccbb_softc *sc = psc->cpc_parent; 1313 int s; 1314 u_int32_t spsr; /* socket present-state reg */ 1315 1316 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1317 switch (poll->level) { 1318 case IPL_NET: 1319 s = splnet(); 1320 break; 1321 case IPL_BIO: 1322 s = splbio(); 1323 break; 1324 case IPL_TTY: /* fallthrough */ 1325 default: 1326 s = spltty(); 1327 break; 1328 } 1329 1330 spsr = 1331 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1332 CB_SOCKET_STAT); 1333 1334 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1335 if (!(spsr & 0x40)) { /* CINT low */ 1336 #else 1337 if (1) { 1338 #endif 1339 if ((*poll->func) (poll->arg) == 1) { 1340 ++poll->count; 1341 printf("intr: reported from poller, 0x%x\n", spsr); 1342 #if defined LEVEL2 1343 } else { 1344 printf("intr: miss! 0x%x\n", spsr); 1345 #endif 1346 } 1347 } 1348 splx(s); 1349 } 1350 #endif /* defined CB_PCMCIA_POLL */ 1351 1352 /* 1353 * static int pccbb_detect_card(struct pccbb_softc *sc) 1354 * return value: 0 if no card exists. 1355 * 1 if 16-bit card exists. 1356 * 2 if cardbus card exists. 1357 */ 1358 static int 1359 pccbb_detect_card(sc) 1360 struct pccbb_softc *sc; 1361 { 1362 bus_space_handle_t base_memh = sc->sc_base_memh; 1363 bus_space_tag_t base_memt = sc->sc_base_memt; 1364 u_int32_t sockstat = 1365 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1366 int retval = 0; 1367 1368 /* CD1 and CD2 asserted */ 1369 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1370 /* card must be present */ 1371 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1372 /* NOTACARD DEASSERTED */ 1373 if (CB_SOCKET_STAT_CB & sockstat) { 1374 /* CardBus mode */ 1375 retval = 2; 1376 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1377 /* 16-bit mode */ 1378 retval = 1; 1379 } 1380 } 1381 } 1382 return retval; 1383 } 1384 1385 /* 1386 * STATIC int cb_reset(struct pccbb_softc *sc) 1387 * This function resets CardBus card. 1388 */ 1389 STATIC int 1390 cb_reset(sc) 1391 struct pccbb_softc *sc; 1392 { 1393 /* 1394 * Reset Assert at least 20 ms 1395 * Some machines request longer duration. 1396 */ 1397 int reset_duration = 1398 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1399 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1400 1401 /* Reset bit Assert (bit 6 at 0x3E) */ 1402 bcr |= CB_BCR_RESET_ENABLE; 1403 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1404 delay(reset_duration); 1405 1406 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1407 /* Reset bit Deassert (bit 6 at 0x3E) */ 1408 bcr &= ~CB_BCR_RESET_ENABLE; 1409 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1410 delay(reset_duration); 1411 } 1412 /* No card found on the slot. Keep Reset. */ 1413 return 1; 1414 } 1415 1416 /* 1417 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1418 * This function detect card Voltage. 1419 */ 1420 STATIC int 1421 cb_detect_voltage(sc) 1422 struct pccbb_softc *sc; 1423 { 1424 u_int32_t psr; /* socket present-state reg */ 1425 bus_space_tag_t iot = sc->sc_base_memt; 1426 bus_space_handle_t ioh = sc->sc_base_memh; 1427 int vol = PCCARD_VCC_UKN; /* set 0 */ 1428 1429 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1430 1431 if (0x400u & psr) { 1432 vol |= PCCARD_VCC_5V; 1433 } 1434 if (0x800u & psr) { 1435 vol |= PCCARD_VCC_3V; 1436 } 1437 1438 return vol; 1439 } 1440 1441 STATIC int 1442 cbbprint(aux, pcic) 1443 void *aux; 1444 const char *pcic; 1445 { 1446 /* 1447 struct cbslot_attach_args *cba = aux; 1448 1449 if (cba->cba_slot >= 0) { 1450 printf(" slot %d", cba->cba_slot); 1451 } 1452 */ 1453 return UNCONF; 1454 } 1455 1456 /* 1457 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1458 * This function enables and disables the card 1459 */ 1460 STATIC int 1461 pccbb_cardenable(sc, function) 1462 struct pccbb_softc *sc; 1463 int function; 1464 { 1465 u_int32_t command = 1466 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1467 1468 DPRINTF(("pccbb_cardenable:")); 1469 switch (function) { 1470 case CARDBUS_IO_ENABLE: 1471 command |= PCI_COMMAND_IO_ENABLE; 1472 break; 1473 case CARDBUS_IO_DISABLE: 1474 command &= ~PCI_COMMAND_IO_ENABLE; 1475 break; 1476 case CARDBUS_MEM_ENABLE: 1477 command |= PCI_COMMAND_MEM_ENABLE; 1478 break; 1479 case CARDBUS_MEM_DISABLE: 1480 command &= ~PCI_COMMAND_MEM_ENABLE; 1481 break; 1482 case CARDBUS_BM_ENABLE: 1483 command |= PCI_COMMAND_MASTER_ENABLE; 1484 break; 1485 case CARDBUS_BM_DISABLE: 1486 command &= ~PCI_COMMAND_MASTER_ENABLE; 1487 break; 1488 default: 1489 return 0; 1490 } 1491 1492 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1493 DPRINTF((" command reg 0x%x\n", command)); 1494 return 1; 1495 } 1496 1497 #if !rbus 1498 /* 1499 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1500 */ 1501 static int 1502 pccbb_io_open(ct, win, start, end) 1503 cardbus_chipset_tag_t ct; 1504 int win; 1505 u_int32_t start, end; 1506 { 1507 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1508 int basereg; 1509 int limitreg; 1510 1511 if ((win < 0) || (win > 2)) { 1512 #if defined DIAGNOSTIC 1513 printf("cardbus_io_open: window out of range %d\n", win); 1514 #endif 1515 return 0; 1516 } 1517 1518 basereg = win * 8 + 0x2c; 1519 limitreg = win * 8 + 0x30; 1520 1521 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1522 start, basereg, end, limitreg)); 1523 1524 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1525 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1526 return 1; 1527 } 1528 1529 /* 1530 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1531 */ 1532 static int 1533 pccbb_io_close(ct, win) 1534 cardbus_chipset_tag_t ct; 1535 int win; 1536 { 1537 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1538 int basereg; 1539 int limitreg; 1540 1541 if ((win < 0) || (win > 2)) { 1542 #if defined DIAGNOSTIC 1543 printf("cardbus_io_close: window out of range %d\n", win); 1544 #endif 1545 return 0; 1546 } 1547 1548 basereg = win * 8 + 0x2c; 1549 limitreg = win * 8 + 0x30; 1550 1551 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1552 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1553 return 1; 1554 } 1555 1556 /* 1557 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1558 */ 1559 static int 1560 pccbb_mem_open(ct, win, start, end) 1561 cardbus_chipset_tag_t ct; 1562 int win; 1563 u_int32_t start, end; 1564 { 1565 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1566 int basereg; 1567 int limitreg; 1568 1569 if ((win < 0) || (win > 2)) { 1570 #if defined DIAGNOSTIC 1571 printf("cardbus_mem_open: window out of range %d\n", win); 1572 #endif 1573 return 0; 1574 } 1575 1576 basereg = win * 8 + 0x1c; 1577 limitreg = win * 8 + 0x20; 1578 1579 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1580 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1581 return 1; 1582 } 1583 1584 /* 1585 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1586 */ 1587 static int 1588 pccbb_mem_close(ct, win) 1589 cardbus_chipset_tag_t ct; 1590 int win; 1591 { 1592 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1593 int basereg; 1594 int limitreg; 1595 1596 if ((win < 0) || (win > 2)) { 1597 #if defined DIAGNOSTIC 1598 printf("cardbus_mem_close: window out of range %d\n", win); 1599 #endif 1600 return 0; 1601 } 1602 1603 basereg = win * 8 + 0x1c; 1604 limitreg = win * 8 + 0x20; 1605 1606 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1607 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1608 return 1; 1609 } 1610 #endif 1611 1612 /* 1613 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1614 * int irq, 1615 * int level, 1616 * int (* func) __P((void *)), 1617 * void *arg) 1618 * 1619 * This function registers an interrupt handler at the bridge, in 1620 * order not to call the interrupt handlers of child devices when 1621 * a card-deletion interrupt occurs. 1622 * 1623 * The arguments irq and level are not used. 1624 */ 1625 static void * 1626 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1627 cardbus_chipset_tag_t ct; 1628 int irq, level; 1629 int (*func) __P((void *)); 1630 void *arg; 1631 { 1632 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1633 1634 return pccbb_intr_establish(sc, irq, level, func, arg); 1635 } 1636 1637 1638 /* 1639 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1640 * void *ih) 1641 * 1642 * This function removes an interrupt handler pointed by ih. 1643 */ 1644 static void 1645 pccbb_cb_intr_disestablish(ct, ih) 1646 cardbus_chipset_tag_t ct; 1647 void *ih; 1648 { 1649 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1650 1651 pccbb_intr_disestablish(sc, ih); 1652 } 1653 1654 1655 /* 1656 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1657 * int irq, 1658 * int level, 1659 * int (* func) __P((void *)), 1660 * void *arg) 1661 * 1662 * This function registers an interrupt handler at the bridge, in 1663 * order not to call the interrupt handlers of child devices when 1664 * a card-deletion interrupt occurs. 1665 * 1666 * The arguments irq is not used because pccbb selects intr vector. 1667 */ 1668 static void * 1669 pccbb_intr_establish(sc, irq, level, func, arg) 1670 struct pccbb_softc *sc; 1671 int irq, level; 1672 int (*func) __P((void *)); 1673 void *arg; 1674 { 1675 struct pccbb_intrhand_list *pil, *newpil; 1676 pcireg_t reg; 1677 1678 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1679 1680 if (sc->sc_pil == NULL) { 1681 /* initialize bridge intr routing */ 1682 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1683 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1684 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1685 1686 switch (sc->sc_chipset) { 1687 case CB_TI113X: 1688 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1689 /* functional intr enabled */ 1690 reg |= PCI113X_CBCTRL_PCI_INTR; 1691 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1692 break; 1693 default: 1694 break; 1695 } 1696 } 1697 1698 /* 1699 * Allocate a room for interrupt handler structure. 1700 */ 1701 if (NULL == (newpil = 1702 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1703 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1704 return NULL; 1705 } 1706 1707 newpil->pil_func = func; 1708 newpil->pil_arg = arg; 1709 newpil->pil_level = level; 1710 newpil->pil_next = NULL; 1711 1712 if (sc->sc_pil == NULL) { 1713 sc->sc_pil = newpil; 1714 } else { 1715 for (pil = sc->sc_pil; pil->pil_next != NULL; 1716 pil = pil->pil_next); 1717 pil->pil_next = newpil; 1718 } 1719 1720 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1721 1722 return newpil; 1723 } 1724 1725 /* 1726 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1727 * void *ih) 1728 * 1729 * This function removes an interrupt handler pointed by ih. 1730 */ 1731 static void 1732 pccbb_intr_disestablish(sc, ih) 1733 struct pccbb_softc *sc; 1734 void *ih; 1735 { 1736 struct pccbb_intrhand_list *pil, **pil_prev; 1737 pcireg_t reg; 1738 1739 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1740 1741 pil_prev = &sc->sc_pil; 1742 1743 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1744 if (pil == ih) { 1745 *pil_prev = pil->pil_next; 1746 free(pil, M_DEVBUF); 1747 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1748 break; 1749 } 1750 pil_prev = &pil->pil_next; 1751 } 1752 1753 if (sc->sc_pil == NULL) { 1754 /* No interrupt handlers */ 1755 1756 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1757 1758 /* stop routing PCI intr */ 1759 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1760 reg |= CB_BCR_INTR_IREQ_ENABLE; 1761 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1762 1763 switch (sc->sc_chipset) { 1764 case CB_TI113X: 1765 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1766 /* functional intr disabled */ 1767 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1768 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1769 break; 1770 default: 1771 break; 1772 } 1773 } 1774 } 1775 1776 #if defined SHOW_REGS 1777 static void 1778 cb_show_regs(pc, tag, memt, memh) 1779 pci_chipset_tag_t pc; 1780 pcitag_t tag; 1781 bus_space_tag_t memt; 1782 bus_space_handle_t memh; 1783 { 1784 int i; 1785 printf("PCI config regs:"); 1786 for (i = 0; i < 0x50; i += 4) { 1787 if (i % 16 == 0) { 1788 printf("\n 0x%02x:", i); 1789 } 1790 printf(" %08x", pci_conf_read(pc, tag, i)); 1791 } 1792 for (i = 0x80; i < 0xb0; i += 4) { 1793 if (i % 16 == 0) { 1794 printf("\n 0x%02x:", i); 1795 } 1796 printf(" %08x", pci_conf_read(pc, tag, i)); 1797 } 1798 1799 if (memh == 0) { 1800 printf("\n"); 1801 return; 1802 } 1803 1804 printf("\nsocket regs:"); 1805 for (i = 0; i <= 0x10; i += 0x04) { 1806 printf(" %08x", bus_space_read_4(memt, memh, i)); 1807 } 1808 printf("\nExCA regs:"); 1809 for (i = 0; i < 0x08; ++i) { 1810 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1811 } 1812 printf("\n"); 1813 return; 1814 } 1815 #endif 1816 1817 /* 1818 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1819 * int busno, int devno, int function) 1820 * This is the function to make a tag to access config space of 1821 * a CardBus Card. It works same as pci_conf_read. 1822 */ 1823 static cardbustag_t 1824 pccbb_make_tag(cc, busno, devno, function) 1825 cardbus_chipset_tag_t cc; 1826 int busno, devno, function; 1827 { 1828 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1829 1830 return pci_make_tag(sc->sc_pc, busno, devno, function); 1831 } 1832 1833 static void 1834 pccbb_free_tag(cc, tag) 1835 cardbus_chipset_tag_t cc; 1836 cardbustag_t tag; 1837 { 1838 } 1839 1840 /* 1841 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1842 * cardbustag_t tag, int offset) 1843 * This is the function to read the config space of a CardBus Card. 1844 * It works same as pci_conf_read. 1845 */ 1846 static cardbusreg_t 1847 pccbb_conf_read(cc, tag, offset) 1848 cardbus_chipset_tag_t cc; 1849 cardbustag_t tag; 1850 int offset; /* register offset */ 1851 { 1852 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1853 1854 return pci_conf_read(sc->sc_pc, tag, offset); 1855 } 1856 1857 /* 1858 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1859 * int offs, cardbusreg_t val) 1860 * This is the function to write the config space of a CardBus Card. 1861 * It works same as pci_conf_write. 1862 */ 1863 static void 1864 pccbb_conf_write(cc, tag, reg, val) 1865 cardbus_chipset_tag_t cc; 1866 cardbustag_t tag; 1867 int reg; /* register offset */ 1868 cardbusreg_t val; 1869 { 1870 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1871 1872 pci_conf_write(sc->sc_pc, tag, reg, val); 1873 } 1874 1875 #if 0 1876 STATIC int 1877 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1878 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1879 int speed, int flags, 1880 bus_space_handle_t * iohp) 1881 #endif 1882 /* 1883 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1884 * bus_addr_t start, bus_size_t size, 1885 * bus_size_t align, 1886 * struct pcmcia_io_handle *pcihp 1887 * 1888 * This function only allocates I/O region for pccard. This function 1889 * never maps the allocated region to pccard I/O area. 1890 * 1891 * XXX: The interface of this function is not very good, I believe. 1892 */ 1893 STATIC int 1894 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1895 pcmcia_chipset_handle_t pch; 1896 bus_addr_t start; /* start address */ 1897 bus_size_t size; 1898 bus_size_t align; 1899 struct pcmcia_io_handle *pcihp; 1900 { 1901 struct pcic_handle *ph = (struct pcic_handle *)pch; 1902 bus_addr_t ioaddr; 1903 int flags = 0; 1904 bus_space_tag_t iot; 1905 bus_space_handle_t ioh; 1906 #if rbus 1907 rbus_tag_t rb; 1908 #endif 1909 if (align == 0) { 1910 align = size; /* XXX: funny??? */ 1911 } 1912 1913 /* 1914 * Allocate some arbitrary I/O space. 1915 */ 1916 1917 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1918 1919 #if rbus 1920 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1921 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1922 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1923 return 1; 1924 } 1925 #else 1926 if (start) { 1927 ioaddr = start; 1928 if (bus_space_map(iot, start, size, 0, &ioh)) { 1929 return 1; 1930 } 1931 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1932 (u_long) ioaddr, (u_long) size)); 1933 } else { 1934 flags |= PCMCIA_IO_ALLOCATED; 1935 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1936 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1937 size, align, 0, 0, &ioaddr, &ioh)) { 1938 /* No room be able to be get. */ 1939 return 1; 1940 } 1941 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1942 (u_long) ioaddr, (u_long) size)); 1943 } 1944 #endif 1945 1946 pcihp->iot = iot; 1947 pcihp->ioh = ioh; 1948 pcihp->addr = ioaddr; 1949 pcihp->size = size; 1950 pcihp->flags = flags; 1951 1952 return 0; 1953 } 1954 1955 /* 1956 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1957 * struct pcmcia_io_handle *pcihp) 1958 * 1959 * This function only frees I/O region for pccard. 1960 * 1961 * XXX: The interface of this function is not very good, I believe. 1962 */ 1963 void 1964 pccbb_pcmcia_io_free(pch, pcihp) 1965 pcmcia_chipset_handle_t pch; 1966 struct pcmcia_io_handle *pcihp; 1967 { 1968 #if !rbus 1969 bus_space_tag_t iot = pcihp->iot; 1970 #endif 1971 bus_space_handle_t ioh = pcihp->ioh; 1972 bus_size_t size = pcihp->size; 1973 1974 #if rbus 1975 struct pccbb_softc *sc = 1976 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1977 rbus_tag_t rb = sc->sc_rbus_iot; 1978 1979 rbus_space_free(rb, ioh, size, NULL); 1980 #else 1981 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1982 bus_space_free(iot, ioh, size); 1983 else 1984 bus_space_unmap(iot, ioh, size); 1985 #endif 1986 } 1987 1988 /* 1989 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1990 * bus_addr_t offset, bus_size_t size, 1991 * struct pcmcia_io_handle *pcihp, 1992 * int *windowp) 1993 * 1994 * This function maps the allocated I/O region to pccard. This function 1995 * never allocates any I/O region for pccard I/O area. I don't 1996 * understand why the original authors of pcmciabus separated alloc and 1997 * map. I believe the two must be unite. 1998 * 1999 * XXX: no wait timing control? 2000 */ 2001 int 2002 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2003 pcmcia_chipset_handle_t pch; 2004 int width; 2005 bus_addr_t offset; 2006 bus_size_t size; 2007 struct pcmcia_io_handle *pcihp; 2008 int *windowp; 2009 { 2010 struct pcic_handle *ph = (struct pcic_handle *)pch; 2011 bus_addr_t ioaddr = pcihp->addr + offset; 2012 int i, win; 2013 #if defined CBB_DEBUG 2014 static char *width_names[] = { "dynamic", "io8", "io16" }; 2015 #endif 2016 2017 /* Sanity check I/O handle. */ 2018 2019 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2020 panic("pccbb_pcmcia_io_map iot is bogus"); 2021 } 2022 2023 /* XXX Sanity check offset/size. */ 2024 2025 win = -1; 2026 for (i = 0; i < PCIC_IO_WINS; i++) { 2027 if ((ph->ioalloc & (1 << i)) == 0) { 2028 win = i; 2029 ph->ioalloc |= (1 << i); 2030 break; 2031 } 2032 } 2033 2034 if (win == -1) { 2035 return 1; 2036 } 2037 2038 *windowp = win; 2039 2040 /* XXX this is pretty gross */ 2041 2042 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2043 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2044 2045 /* XXX wtf is this doing here? */ 2046 2047 #if 0 2048 printf(" port 0x%lx", (u_long) ioaddr); 2049 if (size > 1) { 2050 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2051 } 2052 #endif 2053 2054 ph->io[win].addr = ioaddr; 2055 ph->io[win].size = size; 2056 ph->io[win].width = width; 2057 2058 /* actual dirty register-value changing in the function below. */ 2059 pccbb_pcmcia_do_io_map(ph, win); 2060 2061 return 0; 2062 } 2063 2064 /* 2065 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2066 * 2067 * This function changes register-value to map I/O region for pccard. 2068 */ 2069 static void 2070 pccbb_pcmcia_do_io_map(ph, win) 2071 struct pcic_handle *ph; 2072 int win; 2073 { 2074 static u_int8_t pcic_iowidth[3] = { 2075 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2076 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2077 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2078 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2079 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2080 }; 2081 2082 #define PCIC_SIA_START_LOW 0 2083 #define PCIC_SIA_START_HIGH 1 2084 #define PCIC_SIA_STOP_LOW 2 2085 #define PCIC_SIA_STOP_HIGH 3 2086 2087 int regbase_win = 0x8 + win * 0x04; 2088 u_int8_t ioctl, enable; 2089 2090 DPRINTF( 2091 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2092 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2093 ph->io[win].width * 8)); 2094 2095 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2096 ph->io[win].addr & 0xff); 2097 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2098 (ph->io[win].addr >> 8) & 0xff); 2099 2100 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2101 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2102 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2103 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2104 2105 ioctl = Pcic_read(ph, PCIC_IOCTL); 2106 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2107 switch (win) { 2108 case 0: 2109 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2110 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2111 PCIC_IOCTL_IO0_DATASIZE_MASK); 2112 ioctl |= pcic_iowidth[ph->io[win].width]; 2113 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2114 break; 2115 case 1: 2116 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2117 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2118 PCIC_IOCTL_IO1_DATASIZE_MASK); 2119 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2120 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2121 break; 2122 } 2123 Pcic_write(ph, PCIC_IOCTL, ioctl); 2124 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2125 #if defined CBB_DEBUG 2126 { 2127 u_int8_t start_low = 2128 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2129 u_int8_t start_high = 2130 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2131 u_int8_t stop_low = 2132 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2133 u_int8_t stop_high = 2134 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2135 printf 2136 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2137 start_low, start_high, stop_low, stop_high, ioctl, enable); 2138 } 2139 #endif 2140 } 2141 2142 /* 2143 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2144 * 2145 * This function unmaps I/O region. No return value. 2146 */ 2147 STATIC void 2148 pccbb_pcmcia_io_unmap(pch, win) 2149 pcmcia_chipset_handle_t pch; 2150 int win; 2151 { 2152 struct pcic_handle *ph = (struct pcic_handle *)pch; 2153 int reg; 2154 2155 if (win >= PCIC_IO_WINS || win < 0) { 2156 panic("pccbb_pcmcia_io_unmap: window out of range"); 2157 } 2158 2159 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2160 switch (win) { 2161 case 0: 2162 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2163 break; 2164 case 1: 2165 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2166 break; 2167 } 2168 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2169 2170 ph->ioalloc &= ~(1 << win); 2171 } 2172 2173 /* 2174 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2175 * 2176 * This function enables the card. All information is stored in 2177 * the first argument, pcmcia_chipset_handle_t. 2178 */ 2179 static void 2180 pccbb_pcmcia_wait_ready(ph) 2181 struct pcic_handle *ph; 2182 { 2183 int i; 2184 2185 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2186 Pcic_read(ph, PCIC_IF_STATUS))); 2187 2188 for (i = 0; i < 10000; i++) { 2189 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2190 return; 2191 } 2192 delay(500); 2193 #ifdef CBB_DEBUG 2194 if ((i > 5000) && (i % 100 == 99)) 2195 printf("."); 2196 #endif 2197 } 2198 2199 #ifdef DIAGNOSTIC 2200 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2201 Pcic_read(ph, PCIC_IF_STATUS)); 2202 #endif 2203 } 2204 2205 /* 2206 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2207 * 2208 * This function enables the card. All information is stored in 2209 * the first argument, pcmcia_chipset_handle_t. 2210 */ 2211 STATIC void 2212 pccbb_pcmcia_socket_enable(pch) 2213 pcmcia_chipset_handle_t pch; 2214 { 2215 struct pcic_handle *ph = (struct pcic_handle *)pch; 2216 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2217 int cardtype, win; 2218 u_int8_t power, intr; 2219 pcireg_t spsr; 2220 int voltage; 2221 2222 /* this bit is mostly stolen from pcic_attach_card */ 2223 2224 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2225 2226 /* get card Vcc info */ 2227 2228 spsr = 2229 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2230 CB_SOCKET_STAT); 2231 if (spsr & CB_SOCKET_STAT_5VCARD) { 2232 DPRINTF(("5V card\n")); 2233 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2234 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2235 DPRINTF(("3V card\n")); 2236 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2237 } else { 2238 printf("?V card, 0x%x\n", spsr); /* XXX */ 2239 return; 2240 } 2241 2242 /* disable socket i/o: negate output enable bit */ 2243 2244 power = 0; 2245 Pcic_write(ph, PCIC_PWRCTL, power); 2246 2247 /* power down the socket to reset it, clear the card reset pin */ 2248 2249 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2250 2251 /* 2252 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2253 * we are changing Vcc (Toff). 2254 */ 2255 /* delay(300*1000); too much */ 2256 2257 /* assert reset bit */ 2258 intr = Pcic_read(ph, PCIC_INTR); 2259 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2260 Pcic_write(ph, PCIC_INTR, intr); 2261 2262 /* power up the socket and output enable */ 2263 power = Pcic_read(ph, PCIC_PWRCTL); 2264 power |= PCIC_PWRCTL_OE; 2265 Pcic_write(ph, PCIC_PWRCTL, power); 2266 pccbb_power(sc, voltage); 2267 2268 /* 2269 * hold RESET at least 10us. 2270 */ 2271 delay(10); 2272 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2273 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2274 2275 /* clear the reset flag */ 2276 2277 intr |= PCIC_INTR_RESET; 2278 Pcic_write(ph, PCIC_INTR, intr); 2279 2280 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2281 2282 delay(20000); 2283 2284 /* wait for the chip to finish initializing */ 2285 2286 pccbb_pcmcia_wait_ready(ph); 2287 2288 /* zero out the address windows */ 2289 2290 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2291 2292 /* set the card type */ 2293 2294 cardtype = pcmcia_card_gettype(ph->pcmcia); 2295 2296 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2297 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2298 Pcic_write(ph, PCIC_INTR, intr); 2299 2300 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2301 ph->ph_parent->dv_xname, ph->sock, 2302 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2303 2304 /* reinstall all the memory and io mappings */ 2305 2306 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2307 if (ph->memalloc & (1 << win)) { 2308 pccbb_pcmcia_do_mem_map(ph, win); 2309 } 2310 } 2311 2312 for (win = 0; win < PCIC_IO_WINS; ++win) { 2313 if (ph->ioalloc & (1 << win)) { 2314 pccbb_pcmcia_do_io_map(ph, win); 2315 } 2316 } 2317 } 2318 2319 /* 2320 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2321 * 2322 * This function disables the card. All information is stored in 2323 * the first argument, pcmcia_chipset_handle_t. 2324 */ 2325 STATIC void 2326 pccbb_pcmcia_socket_disable(pch) 2327 pcmcia_chipset_handle_t pch; 2328 { 2329 struct pcic_handle *ph = (struct pcic_handle *)pch; 2330 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2331 u_int8_t power, intr; 2332 2333 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2334 2335 /* reset signal asserting... */ 2336 2337 intr = Pcic_read(ph, PCIC_INTR); 2338 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2339 Pcic_write(ph, PCIC_INTR, intr); 2340 delay(2 * 1000); 2341 2342 /* power down the socket */ 2343 power = Pcic_read(ph, PCIC_PWRCTL); 2344 power &= ~PCIC_PWRCTL_OE; 2345 Pcic_write(ph, PCIC_PWRCTL, power); 2346 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2347 /* 2348 * wait 300ms until power fails (Tpf). 2349 */ 2350 delay(300 * 1000); 2351 } 2352 2353 /* 2354 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2355 * 2356 * This function detects whether a card is in the slot or not. 2357 * If a card is inserted, return 1. Otherwise, return 0. 2358 */ 2359 STATIC int 2360 pccbb_pcmcia_card_detect(pch) 2361 pcmcia_chipset_handle_t pch; 2362 { 2363 struct pcic_handle *ph = (struct pcic_handle *)pch; 2364 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2365 2366 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2367 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2368 } 2369 2370 #if 0 2371 STATIC int 2372 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2373 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2374 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2375 #endif 2376 /* 2377 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2378 * bus_size_t size, 2379 * struct pcmcia_mem_handle *pcmhp) 2380 * 2381 * This function only allocates memory region for pccard. This 2382 * function never maps the allocated region to pccard memory area. 2383 * 2384 * XXX: Why the argument of start address is not in? 2385 */ 2386 STATIC int 2387 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2388 pcmcia_chipset_handle_t pch; 2389 bus_size_t size; 2390 struct pcmcia_mem_handle *pcmhp; 2391 { 2392 struct pcic_handle *ph = (struct pcic_handle *)pch; 2393 bus_space_handle_t memh; 2394 bus_addr_t addr; 2395 bus_size_t sizepg; 2396 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2397 #if rbus 2398 rbus_tag_t rb; 2399 #endif 2400 2401 /* out of sc->memh, allocate as many pages as necessary */ 2402 2403 /* convert size to PCIC pages */ 2404 /* 2405 * This is not enough; when the requested region is on the page 2406 * boundaries, this may calculate wrong result. 2407 */ 2408 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2409 #if 0 2410 if (sizepg > PCIC_MAX_MEM_PAGES) { 2411 return 1; 2412 } 2413 #endif 2414 2415 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2416 return 1; 2417 } 2418 2419 addr = 0; /* XXX gcc -Wuninitialized */ 2420 2421 #if rbus 2422 rb = sc->sc_rbus_memt; 2423 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2424 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2425 &addr, &memh)) { 2426 return 1; 2427 } 2428 #else 2429 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2430 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2431 0, /* boundary */ 2432 0, /* flags */ 2433 &addr, &memh)) { 2434 return 1; 2435 } 2436 #endif 2437 2438 DPRINTF( 2439 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2440 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2441 2442 pcmhp->memt = sc->sc_memt; 2443 pcmhp->memh = memh; 2444 pcmhp->addr = addr; 2445 pcmhp->size = size; 2446 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2447 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2448 pcmhp->mhandle = 0; 2449 /* No offset??? Funny. */ 2450 2451 return 0; 2452 } 2453 2454 /* 2455 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2456 * struct pcmcia_mem_handle *pcmhp) 2457 * 2458 * This function release the memory space allocated by the function 2459 * pccbb_pcmcia_mem_alloc(). 2460 */ 2461 STATIC void 2462 pccbb_pcmcia_mem_free(pch, pcmhp) 2463 pcmcia_chipset_handle_t pch; 2464 struct pcmcia_mem_handle *pcmhp; 2465 { 2466 #if rbus 2467 struct pcic_handle *ph = (struct pcic_handle *)pch; 2468 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2469 2470 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2471 #else 2472 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2473 #endif 2474 } 2475 2476 /* 2477 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2478 * 2479 * This function release the memory space allocated by the function 2480 * pccbb_pcmcia_mem_alloc(). 2481 */ 2482 STATIC void 2483 pccbb_pcmcia_do_mem_map(ph, win) 2484 struct pcic_handle *ph; 2485 int win; 2486 { 2487 int regbase_win; 2488 bus_addr_t phys_addr; 2489 bus_addr_t phys_end; 2490 2491 #define PCIC_SMM_START_LOW 0 2492 #define PCIC_SMM_START_HIGH 1 2493 #define PCIC_SMM_STOP_LOW 2 2494 #define PCIC_SMM_STOP_HIGH 3 2495 #define PCIC_CMA_LOW 4 2496 #define PCIC_CMA_HIGH 5 2497 2498 u_int8_t start_low, start_high = 0; 2499 u_int8_t stop_low, stop_high; 2500 u_int8_t off_low, off_high; 2501 u_int8_t mem_window; 2502 int reg; 2503 2504 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2505 int mem8 = 2506 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2507 || (kind == PCMCIA_MEM_ATTR); 2508 2509 regbase_win = 0x10 + win * 0x08; 2510 2511 phys_addr = ph->mem[win].addr; 2512 phys_end = phys_addr + ph->mem[win].size; 2513 2514 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2515 phys_addr, phys_end, ph->mem[win].offset)); 2516 2517 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2518 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2519 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2520 2521 /* bit 19:12 */ 2522 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2523 /* bit 23:20 and bit 7 on */ 2524 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2525 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2526 /* bit 31:24, for 32-bit address */ 2527 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2528 2529 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2530 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2531 2532 if (((struct pccbb_softc *)ph-> 2533 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2534 Pcic_write(ph, 0x40 + win, mem_window); 2535 } 2536 2537 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2538 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2539 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2540 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2541 2542 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2543 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2544 2545 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2546 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2547 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2548 | ((kind == PCMCIA_MEM_ATTR) ? 2549 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2550 2551 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2552 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2553 2554 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2555 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2556 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2557 2558 #if defined CBB_DEBUG 2559 { 2560 int r1, r2, r3, r4, r5, r6, r7 = 0; 2561 2562 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2563 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2564 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2565 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2566 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2567 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2568 if (((struct pccbb_softc *)(ph-> 2569 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2570 r7 = Pcic_read(ph, 0x40 + win); 2571 } 2572 2573 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2574 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2575 if (((struct pccbb_softc *)(ph-> 2576 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2577 DPRINTF((" %02x", r7)); 2578 } 2579 DPRINTF(("\n")); 2580 } 2581 #endif 2582 } 2583 2584 /* 2585 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2586 * bus_addr_t card_addr, bus_size_t size, 2587 * struct pcmcia_mem_handle *pcmhp, 2588 * bus_addr_t *offsetp, int *windowp) 2589 * 2590 * This function maps memory space allocated by the function 2591 * pccbb_pcmcia_mem_alloc(). 2592 */ 2593 STATIC int 2594 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2595 pcmcia_chipset_handle_t pch; 2596 int kind; 2597 bus_addr_t card_addr; 2598 bus_size_t size; 2599 struct pcmcia_mem_handle *pcmhp; 2600 bus_addr_t *offsetp; 2601 int *windowp; 2602 { 2603 struct pcic_handle *ph = (struct pcic_handle *)pch; 2604 bus_addr_t busaddr; 2605 long card_offset; 2606 int win; 2607 2608 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2609 if ((ph->memalloc & (1 << win)) == 0) { 2610 ph->memalloc |= (1 << win); 2611 break; 2612 } 2613 } 2614 2615 if (win == PCIC_MEM_WINS) { 2616 return 1; 2617 } 2618 2619 *windowp = win; 2620 2621 /* XXX this is pretty gross */ 2622 2623 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2624 panic("pccbb_pcmcia_mem_map memt is bogus"); 2625 } 2626 2627 busaddr = pcmhp->addr; 2628 2629 /* 2630 * compute the address offset to the pcmcia address space for the 2631 * pcic. this is intentionally signed. The masks and shifts below 2632 * will cause TRT to happen in the pcic registers. Deal with making 2633 * sure the address is aligned, and return the alignment offset. 2634 */ 2635 2636 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2637 card_addr -= *offsetp; 2638 2639 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2640 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2641 (u_long) card_addr)); 2642 2643 /* 2644 * include the offset in the size, and decrement size by one, since 2645 * the hw wants start/stop 2646 */ 2647 size += *offsetp - 1; 2648 2649 card_offset = (((long)card_addr) - ((long)busaddr)); 2650 2651 ph->mem[win].addr = busaddr; 2652 ph->mem[win].size = size; 2653 ph->mem[win].offset = card_offset; 2654 ph->mem[win].kind = kind; 2655 2656 pccbb_pcmcia_do_mem_map(ph, win); 2657 2658 return 0; 2659 } 2660 2661 /* 2662 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2663 * int window) 2664 * 2665 * This function unmaps memory space which mapped by the function 2666 * pccbb_pcmcia_mem_map(). 2667 */ 2668 STATIC void 2669 pccbb_pcmcia_mem_unmap(pch, window) 2670 pcmcia_chipset_handle_t pch; 2671 int window; 2672 { 2673 struct pcic_handle *ph = (struct pcic_handle *)pch; 2674 int reg; 2675 2676 if (window >= PCIC_MEM_WINS) { 2677 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2678 } 2679 2680 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2681 reg &= ~(1 << window); 2682 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2683 2684 ph->memalloc &= ~(1 << window); 2685 } 2686 2687 #if defined PCCBB_PCMCIA_POLL 2688 struct pccbb_poll_str { 2689 void *arg; 2690 int (*func) __P((void *)); 2691 int level; 2692 struct pcic_handle *ph; 2693 int count; 2694 int num; 2695 struct callout poll_ch; 2696 }; 2697 2698 static struct pccbb_poll_str pccbb_poll[10]; 2699 static int pccbb_poll_n = 0; 2700 2701 static void pccbb_pcmcia_poll __P((void *arg)); 2702 2703 static void 2704 pccbb_pcmcia_poll(arg) 2705 void *arg; 2706 { 2707 struct pccbb_poll_str *poll = arg; 2708 struct pcic_handle *ph = poll->ph; 2709 struct pccbb_softc *sc = ph->sc; 2710 int s; 2711 u_int32_t spsr; /* socket present-state reg */ 2712 2713 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2714 switch (poll->level) { 2715 case IPL_NET: 2716 s = splnet(); 2717 break; 2718 case IPL_BIO: 2719 s = splbio(); 2720 break; 2721 case IPL_TTY: /* fallthrough */ 2722 default: 2723 s = spltty(); 2724 break; 2725 } 2726 2727 spsr = 2728 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2729 CB_SOCKET_STAT); 2730 2731 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2732 if (!(spsr & 0x40)) /* CINT low */ 2733 #else 2734 if (1) 2735 #endif 2736 { 2737 if ((*poll->func) (poll->arg) > 0) { 2738 ++poll->count; 2739 // printf("intr: reported from poller, 0x%x\n", spsr); 2740 #if defined LEVEL2 2741 } else { 2742 printf("intr: miss! 0x%x\n", spsr); 2743 #endif 2744 } 2745 } 2746 splx(s); 2747 } 2748 #endif /* defined CB_PCMCIA_POLL */ 2749 2750 /* 2751 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2752 * struct pcmcia_function *pf, 2753 * int ipl, 2754 * int (*func)(void *), 2755 * void *arg); 2756 * 2757 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2758 */ 2759 STATIC void * 2760 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2761 pcmcia_chipset_handle_t pch; 2762 struct pcmcia_function *pf; 2763 int ipl; 2764 int (*func) __P((void *)); 2765 void *arg; 2766 { 2767 struct pcic_handle *ph = (struct pcic_handle *)pch; 2768 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2769 2770 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2771 /* what should I do? */ 2772 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2773 DPRINTF( 2774 ("%s does not provide edge nor pulse interrupt\n", 2775 sc->sc_dev.dv_xname)); 2776 return NULL; 2777 } 2778 /* 2779 * XXX Noooooo! The interrupt flag must set properly!! 2780 * dumb pcmcia driver!! 2781 */ 2782 } 2783 2784 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2785 } 2786 2787 /* 2788 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2789 * void *ih) 2790 * 2791 * This function disables PC-Card interrupt. 2792 */ 2793 STATIC void 2794 pccbb_pcmcia_intr_disestablish(pch, ih) 2795 pcmcia_chipset_handle_t pch; 2796 void *ih; 2797 { 2798 struct pcic_handle *ph = (struct pcic_handle *)pch; 2799 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2800 2801 pccbb_intr_disestablish(sc, ih); 2802 } 2803 2804 #if rbus 2805 /* 2806 * static int 2807 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2808 * bus_addr_t addr, bus_size_t size, 2809 * bus_addr_t mask, bus_size_t align, 2810 * int flags, bus_addr_t *addrp; 2811 * bus_space_handle_t *bshp) 2812 * 2813 * This function allocates a portion of memory or io space for 2814 * clients. This function is called from CardBus card drivers. 2815 */ 2816 static int 2817 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2818 cardbus_chipset_tag_t ct; 2819 rbus_tag_t rb; 2820 bus_addr_t addr; 2821 bus_size_t size; 2822 bus_addr_t mask; 2823 bus_size_t align; 2824 int flags; 2825 bus_addr_t *addrp; 2826 bus_space_handle_t *bshp; 2827 { 2828 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2829 2830 DPRINTF( 2831 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2832 addr, size, mask, align)); 2833 2834 if (align == 0) { 2835 align = size; 2836 } 2837 2838 if (rb->rb_bt == sc->sc_memt) { 2839 if (align < 16) { 2840 return 1; 2841 } 2842 } else if (rb->rb_bt == sc->sc_iot) { 2843 if (align < 4) { 2844 return 1; 2845 } 2846 /* XXX: hack for avoiding ISA image */ 2847 if (mask < 0x0100) { 2848 mask = 0x3ff; 2849 addr = 0x300; 2850 } 2851 2852 } else { 2853 DPRINTF( 2854 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2855 rb->rb_bt)); 2856 return 1; 2857 /* XXX: panic here? */ 2858 } 2859 2860 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2861 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2862 return 1; 2863 } 2864 2865 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2866 2867 return 0; 2868 } 2869 2870 /* 2871 * static int 2872 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2873 * bus_space_handle_t *bshp, bus_size_t size); 2874 * 2875 * This function is called from CardBus card drivers. 2876 */ 2877 static int 2878 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2879 cardbus_chipset_tag_t ct; 2880 rbus_tag_t rb; 2881 bus_space_handle_t bsh; 2882 bus_size_t size; 2883 { 2884 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2885 bus_space_tag_t bt = rb->rb_bt; 2886 2887 pccbb_close_win(sc, bt, bsh, size); 2888 2889 if (bt == sc->sc_memt) { 2890 } else if (bt == sc->sc_iot) { 2891 } else { 2892 return 1; 2893 /* XXX: panic here? */ 2894 } 2895 2896 return rbus_space_free(rb, bsh, size, NULL); 2897 } 2898 #endif /* rbus */ 2899 2900 #if rbus 2901 2902 static int 2903 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2904 struct pccbb_softc *sc; 2905 bus_space_tag_t bst; 2906 bus_addr_t addr; 2907 bus_size_t size; 2908 bus_space_handle_t bsh; 2909 int flags; 2910 { 2911 struct pccbb_win_chain_head *head; 2912 bus_addr_t align; 2913 2914 head = &sc->sc_iowindow; 2915 align = 0x04; 2916 if (sc->sc_memt == bst) { 2917 head = &sc->sc_memwindow; 2918 align = 0x1000; 2919 DPRINTF(("using memory window, %x %x %x\n\n", 2920 sc->sc_iot, sc->sc_memt, bst)); 2921 } 2922 2923 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2924 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2925 sc->sc_dev.dv_xname, 2926 (head == &sc->sc_memwindow) ? "mem" : "io"); 2927 } 2928 pccbb_winset(align, sc, bst); 2929 2930 return 0; 2931 } 2932 2933 static int 2934 pccbb_close_win(sc, bst, bsh, size) 2935 struct pccbb_softc *sc; 2936 bus_space_tag_t bst; 2937 bus_space_handle_t bsh; 2938 bus_size_t size; 2939 { 2940 struct pccbb_win_chain_head *head; 2941 bus_addr_t align; 2942 2943 head = &sc->sc_iowindow; 2944 align = 0x04; 2945 if (sc->sc_memt == bst) { 2946 head = &sc->sc_memwindow; 2947 align = 0x1000; 2948 } 2949 2950 if (pccbb_winlist_delete(head, bsh, size)) { 2951 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2952 sc->sc_dev.dv_xname, 2953 (head == &sc->sc_memwindow) ? "mem" : "io"); 2954 } 2955 pccbb_winset(align, sc, bst); 2956 2957 return 0; 2958 } 2959 2960 static int 2961 pccbb_winlist_insert(head, start, size, bsh, flags) 2962 struct pccbb_win_chain_head *head; 2963 bus_addr_t start; 2964 bus_size_t size; 2965 bus_space_handle_t bsh; 2966 int flags; 2967 { 2968 struct pccbb_win_chain *chainp, *elem; 2969 2970 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2971 M_NOWAIT)) == NULL) 2972 return (1); /* fail */ 2973 2974 elem->wc_start = start; 2975 elem->wc_end = start + (size - 1); 2976 elem->wc_handle = bsh; 2977 elem->wc_flags = flags; 2978 2979 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2980 chainp = TAILQ_NEXT(chainp, wc_list)) { 2981 if (chainp->wc_end < start) 2982 continue; 2983 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2984 return (0); 2985 } 2986 2987 TAILQ_INSERT_TAIL(head, elem, wc_list); 2988 return (0); 2989 } 2990 2991 static int 2992 pccbb_winlist_delete(head, bsh, size) 2993 struct pccbb_win_chain_head *head; 2994 bus_space_handle_t bsh; 2995 bus_size_t size; 2996 { 2997 struct pccbb_win_chain *chainp; 2998 2999 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3000 chainp = TAILQ_NEXT(chainp, wc_list)) { 3001 if (chainp->wc_handle != bsh) 3002 continue; 3003 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3004 printf("pccbb_winlist_delete: window 0x%lx size " 3005 "inconsistent: 0x%lx, 0x%lx\n", 3006 chainp->wc_start, 3007 chainp->wc_end - chainp->wc_start, 3008 size - 1); 3009 return 1; 3010 } 3011 3012 TAILQ_REMOVE(head, chainp, wc_list); 3013 free(chainp, M_DEVBUF); 3014 3015 return 0; 3016 } 3017 3018 return 1; /* fail: no candidate to remove */ 3019 } 3020 3021 static void 3022 pccbb_winset(align, sc, bst) 3023 bus_addr_t align; 3024 struct pccbb_softc *sc; 3025 bus_space_tag_t bst; 3026 { 3027 pci_chipset_tag_t pc; 3028 pcitag_t tag; 3029 bus_addr_t mask = ~(align - 1); 3030 struct { 3031 cardbusreg_t win_start; 3032 cardbusreg_t win_limit; 3033 int win_flags; 3034 } win[2]; 3035 struct pccbb_win_chain *chainp; 3036 int offs; 3037 3038 win[0].win_start = 0xffffffff; 3039 win[0].win_limit = 0; 3040 win[1].win_start = 0xffffffff; 3041 win[1].win_limit = 0; 3042 3043 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3044 offs = 0x2c; 3045 if (sc->sc_memt == bst) { 3046 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3047 offs = 0x1c; 3048 } 3049 3050 if (chainp != NULL) { 3051 win[0].win_start = chainp->wc_start & mask; 3052 win[0].win_limit = chainp->wc_end & mask; 3053 win[0].win_flags = chainp->wc_flags; 3054 chainp = TAILQ_NEXT(chainp, wc_list); 3055 } 3056 3057 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3058 if (win[1].win_start == 0xffffffff) { 3059 /* window 1 is not used */ 3060 if ((win[0].win_flags == chainp->wc_flags) && 3061 (win[0].win_limit + align >= 3062 (chainp->wc_start & mask))) { 3063 /* concatenate */ 3064 win[0].win_limit = chainp->wc_end & mask; 3065 } else { 3066 /* make new window */ 3067 win[1].win_start = chainp->wc_start & mask; 3068 win[1].win_limit = chainp->wc_end & mask; 3069 win[1].win_flags = chainp->wc_flags; 3070 } 3071 continue; 3072 } 3073 3074 /* Both windows are engaged. */ 3075 if (win[0].win_flags == win[1].win_flags) { 3076 /* same flags */ 3077 if (win[0].win_flags == chainp->wc_flags) { 3078 if (win[1].win_start - (win[0].win_limit + 3079 align) < 3080 (chainp->wc_start & mask) - 3081 ((chainp->wc_end & mask) + align)) { 3082 /* 3083 * merge window 0 and 1, and set win1 3084 * to chainp 3085 */ 3086 win[0].win_limit = win[1].win_limit; 3087 win[1].win_start = 3088 chainp->wc_start & mask; 3089 win[1].win_limit = 3090 chainp->wc_end & mask; 3091 } else { 3092 win[1].win_limit = 3093 chainp->wc_end & mask; 3094 } 3095 } else { 3096 /* different flags */ 3097 3098 /* concatenate win0 and win1 */ 3099 win[0].win_limit = win[1].win_limit; 3100 /* allocate win[1] to new space */ 3101 win[1].win_start = chainp->wc_start & mask; 3102 win[1].win_limit = chainp->wc_end & mask; 3103 win[1].win_flags = chainp->wc_flags; 3104 } 3105 } else { 3106 /* the flags of win[0] and win[1] is different */ 3107 if (win[0].win_flags == chainp->wc_flags) { 3108 win[0].win_limit = chainp->wc_end & mask; 3109 /* 3110 * XXX this creates overlapping windows, so 3111 * what should the poor bridge do if one is 3112 * cachable, and the other is not? 3113 */ 3114 printf("%s: overlapping windows\n", 3115 sc->sc_dev.dv_xname); 3116 } else { 3117 win[1].win_limit = chainp->wc_end & mask; 3118 } 3119 } 3120 } 3121 3122 pc = sc->sc_pc; 3123 tag = sc->sc_tag; 3124 pci_conf_write(pc, tag, offs, win[0].win_start); 3125 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3126 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3127 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3128 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3129 pci_conf_read(pc, tag, offs), 3130 pci_conf_read(pc, tag, offs + 4) + align, 3131 pci_conf_read(pc, tag, offs + 8), 3132 pci_conf_read(pc, tag, offs + 12) + align)); 3133 3134 if (bst == sc->sc_memt) { 3135 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3136 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3137 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3138 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3139 } 3140 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3141 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3142 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3143 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3144 } 3145 } 3146 } 3147 3148 #endif /* rbus */ 3149 3150 static void 3151 pccbb_powerhook(why, arg) 3152 int why; 3153 void *arg; 3154 { 3155 struct pccbb_softc *sc = arg; 3156 u_int32_t reg; 3157 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3158 bus_space_handle_t base_memh = sc->sc_base_memh; 3159 3160 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3161 3162 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3163 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3164 if (sc->sc_pil_intr_enable) { 3165 (void)pccbbintr_function(sc); 3166 } 3167 sc->sc_pil_intr_enable = 0; 3168 3169 /* ToDo: deactivate or suspend child devices */ 3170 3171 } 3172 3173 if (why == PWR_RESUME) { 3174 /* CSC Interrupt: Card detect interrupt on */ 3175 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3176 /* Card detect intr is turned on. */ 3177 reg |= CB_SOCKET_MASK_CD; 3178 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3179 /* reset interrupt */ 3180 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3181 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3182 3183 /* 3184 * check for card insertion or removal during suspend period. 3185 * XXX: the code can't cope with card swap (remove then 3186 * insert). how can we detect such situation? 3187 */ 3188 (void)pccbbintr(sc); 3189 3190 sc->sc_pil_intr_enable = 1; 3191 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3192 3193 /* ToDo: activate or wakeup child devices */ 3194 } 3195 } 3196
Indexes created Fri Sep 26 08:10:20 GMT 2025