pccbb.c revision 1.51
1 /* $NetBSD: pccbb.c,v 1.51 2000/12/28 22:59:14 sommerfeld Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 56 #include <machine/intr.h> 57 #include <machine/bus.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/pci/pccbbreg.h> 64 65 #include <dev/cardbus/cardslotvar.h> 66 67 #include <dev/cardbus/cardbusvar.h> 68 69 #include <dev/pcmcia/pcmciareg.h> 70 #include <dev/pcmcia/pcmciavar.h> 71 72 #include <dev/ic/i82365reg.h> 73 #include <dev/ic/i82365var.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include "locators.h" 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 93 void pccbbattach __P((struct device *, struct device *, void *)); 94 int pccbbintr __P((void *)); 95 static void pci113x_insert __P((void *)); 96 static int pccbbintr_function __P((struct pccbb_softc *)); 97 98 static int pccbb_detect_card __P((struct pccbb_softc *)); 99 100 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 101 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 102 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 103 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 104 105 STATIC int cb_reset __P((struct pccbb_softc *)); 106 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 107 STATIC int cbbprint __P((void *, const char *)); 108 109 static int cb_chipset __P((u_int32_t, int *)); 110 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 111 struct pcmciabus_attach_args *)); 112 #if 0 113 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 114 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 115 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 116 #endif 117 118 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 119 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 120 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 121 #if !rbus 122 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 123 u_int32_t)); 124 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 125 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 126 u_int32_t)); 127 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 128 #endif /* !rbus */ 129 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 130 int level, int (*ih) (void *), void *sc)); 131 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 132 133 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 134 int level, int (*ih) (void *), void *sc)); 135 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 136 137 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 138 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 139 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 140 int)); 141 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 142 cardbusreg_t)); 143 static void pccbb_chipinit __P((struct pccbb_softc *)); 144 145 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *)); 147 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *)); 149 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 151 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 152 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 154 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *)); 156 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *)); 158 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 159 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 160 struct pcmcia_function *, int, int (*)(void *), void *)); 161 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 162 void *)); 163 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 164 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 165 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 166 167 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 168 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 169 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 170 static void pccbb_powerhook __P((int, void *)); 171 172 /* bus-space allocation and deallocation functions */ 173 #if rbus 174 175 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 176 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 177 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 178 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 179 bus_space_handle_t, bus_size_t)); 180 181 #endif /* rbus */ 182 183 #if rbus 184 185 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 186 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 187 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 188 bus_space_handle_t, bus_size_t)); 189 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 190 bus_size_t, bus_space_handle_t, int)); 191 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 192 bus_space_handle_t, bus_size_t)); 193 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 194 bus_space_tag_t)); 195 void pccbb_winlist_show(struct pccbb_win_chain *); 196 197 #endif /* rbus */ 198 199 /* for config_defer */ 200 static void pccbb_pci_callback __P((struct device *)); 201 202 #if defined SHOW_REGS 203 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 204 bus_space_tag_t memt, bus_space_handle_t memh)); 205 #endif 206 207 struct cfattach cbb_pci_ca = { 208 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 209 }; 210 211 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 212 pccbb_pcmcia_mem_alloc, 213 pccbb_pcmcia_mem_free, 214 pccbb_pcmcia_mem_map, 215 pccbb_pcmcia_mem_unmap, 216 pccbb_pcmcia_io_alloc, 217 pccbb_pcmcia_io_free, 218 pccbb_pcmcia_io_map, 219 pccbb_pcmcia_io_unmap, 220 pccbb_pcmcia_intr_establish, 221 pccbb_pcmcia_intr_disestablish, 222 pccbb_pcmcia_socket_enable, 223 pccbb_pcmcia_socket_disable, 224 pccbb_pcmcia_card_detect 225 }; 226 227 #if rbus 228 static struct cardbus_functions pccbb_funcs = { 229 pccbb_rbus_cb_space_alloc, 230 pccbb_rbus_cb_space_free, 231 pccbb_cb_intr_establish, 232 pccbb_cb_intr_disestablish, 233 pccbb_ctrl, 234 pccbb_power, 235 pccbb_make_tag, 236 pccbb_free_tag, 237 pccbb_conf_read, 238 pccbb_conf_write, 239 }; 240 #else 241 static struct cardbus_functions pccbb_funcs = { 242 pccbb_ctrl, 243 pccbb_power, 244 pccbb_mem_open, 245 pccbb_mem_close, 246 pccbb_io_open, 247 pccbb_io_close, 248 pccbb_cb_intr_establish, 249 pccbb_cb_intr_disestablish, 250 pccbb_make_tag, 251 pccbb_conf_read, 252 pccbb_conf_write, 253 }; 254 #endif 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 struct cfdata *match; 260 void *aux; 261 { 262 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 263 264 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 265 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 266 PCI_INTERFACE(pa->pa_class) == 0) { 267 return 1; 268 } 269 270 return 0; 271 } 272 273 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 274 | ((prod) << PCI_PRODUCT_SHIFT)) 275 276 struct yenta_chipinfo { 277 pcireg_t yc_id; /* vendor tag | product tag */ 278 int yc_chiptype; 279 int yc_flags; 280 } yc_chipsets[] = { 281 /* Texas Instruments chips */ 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 307 /* Ricoh chips */ 308 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 309 PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 311 PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 313 PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 315 PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 317 PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 319 PCCBB_PCMCIA_MEM_32}, 320 321 /* Toshiba products */ 322 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 323 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 325 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 327 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 329 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 330 331 /* Cirrus Logic products */ 332 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 333 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 335 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 336 337 /* sentinel, or Generic chip */ 338 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 339 }; 340 341 static int 342 cb_chipset(pci_id, flagp) 343 u_int32_t pci_id; 344 int *flagp; 345 { 346 struct yenta_chipinfo *yc; 347 348 /* Loop over except the last default entry. */ 349 for (yc = yc_chipsets; yc < yc_chipsets + 350 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 351 if (pci_id == yc->yc_id) 352 break; 353 354 if (flagp != NULL) 355 *flagp = yc->yc_flags; 356 357 return (yc->yc_chiptype); 358 } 359 360 static void 361 pccbb_shutdown(void *arg) 362 { 363 struct pccbb_softc *sc = arg; 364 pcireg_t command; 365 366 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 367 368 /* 369 * turn off power 370 * 371 * XXX - do not turn off power if chipset is TI 113X because 372 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 373 */ 374 if (sc->sc_chipset != CB_TI113X) { 375 pccbb_power((cardbus_chipset_tag_t)sc, 376 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 377 } 378 379 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 380 0); 381 382 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 383 384 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 385 PCI_COMMAND_MASTER_ENABLE); 386 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 387 388 } 389 390 void 391 pccbbattach(parent, self, aux) 392 struct device *parent; 393 struct device *self; 394 void *aux; 395 { 396 struct pccbb_softc *sc = (void *)self; 397 struct pci_attach_args *pa = aux; 398 pci_chipset_tag_t pc = pa->pa_pc; 399 pcireg_t busreg, reg, sock_base; 400 bus_addr_t sockbase; 401 char devinfo[256]; 402 int flags; 403 404 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 405 406 pci_devinfo(pa->pa_id, 0, 0, devinfo); 407 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 408 #ifdef CBB_DEBUG 409 printf(" (chipflags %x)", flags); 410 #endif 411 printf("\n"); 412 413 TAILQ_INIT(&sc->sc_memwindow); 414 TAILQ_INIT(&sc->sc_iowindow); 415 416 #if rbus 417 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 418 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 419 #endif /* rbus */ 420 421 sc->sc_base_memh = 0; 422 423 /* 424 * MAP socket registers and ExCA registers on memory-space 425 * When no valid address is set on socket base registers (on pci 426 * config space), get it not polite way. 427 */ 428 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 429 430 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 431 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 432 /* The address must be valid. */ 433 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 434 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 435 printf("%s: can't map socket base address 0x%x\n", 436 sc->sc_dev.dv_xname, sock_base); 437 /* 438 * I think it's funny: socket base registers must be 439 * mapped on memory space, but ... 440 */ 441 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 442 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 443 NULL)) { 444 printf("%s: can't map socket base address" 445 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 446 sockbase); 447 /* give up... allocate reg space via rbus. */ 448 sc->sc_base_memh = 0; 449 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 450 } 451 } else { 452 DPRINTF(("%s: socket base address 0x%lx\n", 453 sc->sc_dev.dv_xname, sockbase)); 454 } 455 } 456 457 sc->sc_mem_start = 0; /* XXX */ 458 sc->sc_mem_end = 0xffffffff; /* XXX */ 459 460 /* 461 * When interrupt isn't routed correctly, give up probing cbb and do 462 * not kill pcic-compatible port. 463 */ 464 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 465 printf("%s: NOT USED because of unconfigured interrupt\n", 466 sc->sc_dev.dv_xname); 467 return; 468 } 469 470 /* 471 * When bus number isn't set correctly, give up using 32-bit CardBus 472 * mode. 473 */ 474 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 475 #if notyet 476 if (((busreg >> 8) & 0xff) == 0) { 477 printf("%s: CardBus support disabled because of unconfigured bus number\n", 478 sc->sc_dev.dv_xname); 479 flags |= PCCBB_PCMCIA_16BITONLY; 480 } 481 #endif 482 483 /* pccbb_machdep.c end */ 484 485 #if defined CBB_DEBUG 486 { 487 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 488 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 489 intrname[pa->pa_intrpin], pa->pa_intrline); 490 } 491 #endif 492 493 /* setup softc */ 494 sc->sc_pc = pc; 495 sc->sc_iot = pa->pa_iot; 496 sc->sc_memt = pa->pa_memt; 497 sc->sc_dmat = pa->pa_dmat; 498 sc->sc_tag = pa->pa_tag; 499 sc->sc_function = pa->pa_function; 500 501 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 502 503 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 504 505 shutdownhook_establish(pccbb_shutdown, sc); 506 507 /* Disable legacy register mapping. */ 508 switch (sc->sc_chipset) { 509 case CB_RX5C46X: /* fallthrough */ 510 #if 0 511 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 512 case CB_RX5C47X: 513 #endif 514 /* 515 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 516 * cannot be disabled by substituting 0 into PCI_LEGACY 517 * register. Ricoh CardBus bridges have special bits on Bridge 518 * control reg (addr 0x3e on PCI config space). 519 */ 520 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 521 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 522 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 523 break; 524 525 default: 526 /* XXX I don't know proper way to kill legacy I/O. */ 527 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 528 break; 529 } 530 531 config_defer(self, pccbb_pci_callback); 532 } 533 534 535 536 537 /* 538 * static void pccbb_pci_callback(struct device *self) 539 * 540 * The actual attach routine: get memory space for YENTA register 541 * space, setup YENTA register and route interrupt. 542 * 543 * This function should be deferred because this device may obtain 544 * memory space dynamically. This function must avoid obtaining 545 * memory area which has already kept for another device. 546 */ 547 static void 548 pccbb_pci_callback(self) 549 struct device *self; 550 { 551 struct pccbb_softc *sc = (void *)self; 552 pci_chipset_tag_t pc = sc->sc_pc; 553 bus_space_tag_t base_memt; 554 bus_space_handle_t base_memh; 555 u_int32_t maskreg; 556 pci_intr_handle_t ih; 557 const char *intrstr = NULL; 558 bus_addr_t sockbase; 559 struct cbslot_attach_args cba; 560 struct pcmciabus_attach_args paa; 561 struct cardslot_attach_args caa; 562 struct cardslot_softc *csc; 563 564 if (0 == sc->sc_base_memh) { 565 /* The socket registers aren't mapped correctly. */ 566 #if rbus 567 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 568 (sc->sc_chipset == CB_RX5C47X 569 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 570 0, &sockbase, &sc->sc_base_memh)) { 571 return; 572 } 573 sc->sc_base_memt = sc->sc_memt; 574 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 575 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 576 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 577 PCI_SOCKBASE))); 578 #else 579 sc->sc_base_memt = sc->sc_memt; 580 #if !defined CBB_PCI_BASE 581 #define CBB_PCI_BASE 0x20000000 582 #endif 583 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 584 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 585 /* cannot allocate memory space */ 586 return; 587 } 588 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 589 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 590 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 591 sc->sc_tag, PCI_SOCKBASE))); 592 #endif 593 } 594 595 /* bus bridge initialization */ 596 pccbb_chipinit(sc); 597 598 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 599 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 600 601 /* CSC Interrupt: Card detect interrupt on */ 602 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 603 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 604 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 605 /* reset interrupt */ 606 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 607 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 608 609 /* clear data structure for child device interrupt handlers */ 610 sc->sc_pil = NULL; 611 sc->sc_pil_intr_enable = 1; 612 613 /* Map and establish the interrupt. */ 614 if (pci_intr_map(&sc->sc_pa, &ih)) { 615 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 616 return; 617 } 618 intrstr = pci_intr_string(pc, ih); 619 620 /* 621 * XXX pccbbintr should be called under the priority lower 622 * than any other hard interrputs. 623 */ 624 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 625 626 if (sc->sc_ih == NULL) { 627 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 628 if (intrstr != NULL) { 629 printf(" at %s", intrstr); 630 } 631 printf("\n"); 632 return; 633 } 634 635 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 636 powerhook_establish(pccbb_powerhook, sc); 637 638 { 639 u_int32_t sockstat = 640 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 641 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 642 sc->sc_flags |= CBB_CARDEXIST; 643 } 644 } 645 646 /* 647 * attach cardbus 648 */ 649 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 650 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 651 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 652 653 /* initialize cbslot_attach */ 654 cba.cba_busname = "cardbus"; 655 cba.cba_iot = sc->sc_iot; 656 cba.cba_memt = sc->sc_memt; 657 cba.cba_dmat = sc->sc_dmat; 658 cba.cba_bus = (busreg >> 8) & 0x0ff; 659 cba.cba_cc = (void *)sc; 660 cba.cba_cf = &pccbb_funcs; 661 cba.cba_intrline = sc->sc_pa.pa_intrline; 662 663 #if rbus 664 cba.cba_rbus_iot = sc->sc_rbus_iot; 665 cba.cba_rbus_memt = sc->sc_rbus_memt; 666 #endif 667 668 cba.cba_cacheline = PCI_CACHELINE(bhlc); 669 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 670 671 printf("%s: cacheline 0x%x lattimer 0x%x\n", 672 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 673 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 674 busreg); 675 #if defined SHOW_REGS 676 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 677 sc->sc_base_memh); 678 #endif 679 } 680 681 pccbb_pcmcia_attach_setup(sc, &paa); 682 caa.caa_cb_attach = NULL; 683 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 684 caa.caa_cb_attach = &cba; 685 } 686 caa.caa_16_attach = &paa; 687 caa.caa_ph = &sc->sc_pcmcia_h; 688 689 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 690 DPRINTF(("pccbbattach: found cardslot\n")); 691 sc->sc_csc = csc; 692 } 693 694 return; 695 } 696 697 698 699 700 701 /* 702 * static void pccbb_chipinit(struct pccbb_softc *sc) 703 * 704 * This function initialize YENTA chip registers listed below: 705 * 1) PCI command reg, 706 * 2) PCI and CardBus latency timer, 707 * 3) route PCI interrupt, 708 * 4) close all memory and io windows. 709 */ 710 static void 711 pccbb_chipinit(sc) 712 struct pccbb_softc *sc; 713 { 714 pci_chipset_tag_t pc = sc->sc_pc; 715 pcitag_t tag = sc->sc_tag; 716 pcireg_t reg; 717 718 /* 719 * Set PCI command reg. 720 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 721 */ 722 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 723 /* I believe it is harmless. */ 724 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 725 PCI_COMMAND_MASTER_ENABLE); 726 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 727 728 /* 729 * Set CardBus latency timer. 730 */ 731 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 732 if (PCI_CB_LATENCY(reg) < 0x20) { 733 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 734 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 735 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 736 } 737 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 738 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 739 740 /* 741 * Set PCI latency timer. 742 */ 743 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 744 if (PCI_LATTIMER(reg) < 0x10) { 745 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 746 reg |= (0x10 << PCI_LATTIMER_SHIFT); 747 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 748 } 749 DPRINTF(("PCI latency timer 0x%x (%x)\n", 750 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 751 752 753 /* Route functional interrupts to PCI. */ 754 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 755 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 756 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 757 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 758 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 759 760 switch (sc->sc_chipset) { 761 case CB_TI113X: 762 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 763 /* This bit is shared, but may read as 0 on some chips, so set 764 it explicitly on both functions. */ 765 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 766 /* CSC intr enable */ 767 reg |= PCI113X_CBCTRL_PCI_CSC; 768 /* functional intr prohibit | prohibit ISA routing */ 769 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 770 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 771 break; 772 773 case CB_TI12XX: 774 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 775 reg |= PCI12XX_SYSCTRL_VCCPROT; 776 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 777 break; 778 779 case CB_TOPIC95B: 780 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 781 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 782 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 783 784 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 785 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 786 sc->sc_dev.dv_xname, reg)); 787 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 788 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 789 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 790 DPRINTF(("0x%x\n", reg)); 791 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 792 break; 793 } 794 795 /* Close all memory and I/O windows. */ 796 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 797 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 798 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 799 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 800 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 801 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 802 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 803 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 804 805 /* reset 16-bit pcmcia bus */ 806 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 807 0x800 + PCIC_INTR, 808 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 809 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 810 811 /* turn of power */ 812 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 813 } 814 815 816 817 818 /* 819 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 820 * struct pcmciabus_attach_args *paa) 821 * 822 * This function attaches 16-bit PCcard bus. 823 */ 824 STATIC void 825 pccbb_pcmcia_attach_setup(sc, paa) 826 struct pccbb_softc *sc; 827 struct pcmciabus_attach_args *paa; 828 { 829 struct pcic_handle *ph = &sc->sc_pcmcia_h; 830 #if rbus 831 rbus_tag_t rb; 832 #endif 833 834 /* initialize pcmcia part in pccbb_softc */ 835 ph->ph_parent = (struct device *)sc; 836 ph->sock = sc->sc_function; 837 ph->flags = 0; 838 ph->shutdown = 0; 839 ph->ih_irq = sc->sc_pa.pa_intrline; 840 ph->ph_bus_t = sc->sc_base_memt; 841 ph->ph_bus_h = sc->sc_base_memh; 842 ph->ph_read = pccbb_pcmcia_read; 843 ph->ph_write = pccbb_pcmcia_write; 844 sc->sc_pct = &pccbb_pcmcia_funcs; 845 846 /* 847 * We need to do a few things here: 848 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 849 * setting the IRQ numbers to 0. 850 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 851 * routing of CSC interrupts (e.g. card removal) to PCI while in 852 * PCMCIA mode. We just leave this set all the time. 853 * 3) Enable card insertion/removal interrupts in case the chip also 854 * needs that while in PCMCIA mode. 855 * 4) Clear any pending CSC interrupt. 856 */ 857 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 858 if (sc->sc_chipset == CB_TI113X) { 859 Pcic_write(ph, PCIC_CSC_INTR, 0); 860 } else { 861 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 862 Pcic_read(ph, PCIC_CSC); 863 } 864 865 /* initialize pcmcia bus attachment */ 866 paa->paa_busname = "pcmcia"; 867 paa->pct = sc->sc_pct; 868 paa->pch = ph; 869 paa->iobase = 0; /* I don't use them */ 870 paa->iosize = 0; 871 #if rbus 872 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 873 paa->iobase = rb->rb_start + rb->rb_offset; 874 paa->iosize = rb->rb_end - rb->rb_start; 875 #endif 876 877 return; 878 } 879 880 #if 0 881 STATIC void 882 pccbb_pcmcia_attach_card(ph) 883 struct pcic_handle *ph; 884 { 885 if (ph->flags & PCIC_FLAG_CARDP) { 886 panic("pccbb_pcmcia_attach_card: already attached"); 887 } 888 889 /* call the MI attach function */ 890 pcmcia_card_attach(ph->pcmcia); 891 892 ph->flags |= PCIC_FLAG_CARDP; 893 } 894 895 STATIC void 896 pccbb_pcmcia_detach_card(ph, flags) 897 struct pcic_handle *ph; 898 int flags; 899 { 900 if (!(ph->flags & PCIC_FLAG_CARDP)) { 901 panic("pccbb_pcmcia_detach_card: already detached"); 902 } 903 904 ph->flags &= ~PCIC_FLAG_CARDP; 905 906 /* call the MI detach function */ 907 pcmcia_card_detach(ph->pcmcia, flags); 908 } 909 #endif 910 911 /* 912 * int pccbbintr(arg) 913 * void *arg; 914 * This routine handles the interrupt from Yenta PCI-CardBus bridge 915 * itself. 916 */ 917 int 918 pccbbintr(arg) 919 void *arg; 920 { 921 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 922 u_int32_t sockevent, sockstate; 923 bus_space_tag_t memt = sc->sc_base_memt; 924 bus_space_handle_t memh = sc->sc_base_memh; 925 struct pcic_handle *ph = &sc->sc_pcmcia_h; 926 927 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 928 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 929 Pcic_read(ph, PCIC_CSC); 930 931 if (sockevent == 0) { 932 /* This intr is not for me: it may be for my child devices. */ 933 if (sc->sc_pil_intr_enable) { 934 return pccbbintr_function(sc); 935 } else { 936 return 0; 937 } 938 } 939 940 if (sockevent & CB_SOCKET_EVENT_CD) { 941 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 942 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 943 /* A card should be removed. */ 944 if (sc->sc_flags & CBB_CARDEXIST) { 945 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 946 sockevent)); 947 DPRINTF((" card removed, 0x%08x\n", sockstate)); 948 sc->sc_flags &= ~CBB_CARDEXIST; 949 if (sc->sc_csc->sc_status & 950 CARDSLOT_STATUS_CARD_16) { 951 #if 0 952 struct pcic_handle *ph = 953 &sc->sc_pcmcia_h; 954 955 pcmcia_card_deactivate(ph->pcmcia); 956 pccbb_pcmcia_socket_disable(ph); 957 pccbb_pcmcia_detach_card(ph, 958 DETACH_FORCE); 959 #endif 960 cardslot_event_throw(sc->sc_csc, 961 CARDSLOT_EVENT_REMOVAL_16); 962 } else if (sc->sc_csc->sc_status & 963 CARDSLOT_STATUS_CARD_CB) { 964 /* Cardbus intr removed */ 965 cardslot_event_throw(sc->sc_csc, 966 CARDSLOT_EVENT_REMOVAL_CB); 967 } 968 } 969 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 970 /* 971 * The pccbbintr may called from powerdown hook when 972 * the system resumed, to detect the card 973 * insertion/removal during suspension. 974 */ 975 (sc->sc_flags & CBB_CARDEXIST) == 0) { 976 if (sc->sc_flags & CBB_INSERTING) { 977 callout_stop(&sc->sc_insert_ch); 978 } 979 callout_reset(&sc->sc_insert_ch, hz / 10, 980 pci113x_insert, sc); 981 sc->sc_flags |= CBB_INSERTING; 982 } 983 } 984 985 return (1); 986 } 987 988 /* 989 * static int pccbbintr_function(struct pccbb_softc *sc) 990 * 991 * This function calls each interrupt handler registered at the 992 * bridge. The interrupt handlers are called in registered order. 993 */ 994 static int 995 pccbbintr_function(sc) 996 struct pccbb_softc *sc; 997 { 998 int retval = 0, val; 999 struct pccbb_intrhand_list *pil; 1000 int s, splchanged; 1001 1002 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1003 /* 1004 * XXX priority change. gross. I use if-else 1005 * sentense instead of switch-case sentense because of 1006 * avoiding duplicate case value error. More than one 1007 * IPL_XXX use same value. It depends on 1008 * implimentation. 1009 */ 1010 splchanged = 1; 1011 if (pil->pil_level == IPL_SERIAL) { 1012 s = splserial(); 1013 } else if (pil->pil_level == IPL_HIGH) { 1014 s = splhigh(); 1015 } else if (pil->pil_level == IPL_CLOCK) { 1016 s = splclock(); 1017 } else if (pil->pil_level == IPL_AUDIO) { 1018 s = splaudio(); 1019 } else if (pil->pil_level == IPL_IMP) { 1020 s = splimp(); 1021 } else if (pil->pil_level == IPL_TTY) { 1022 s = spltty(); 1023 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1024 s = splsoftserial(); 1025 } else if (pil->pil_level == IPL_NET) { 1026 s = splnet(); 1027 } else { 1028 splchanged = 0; 1029 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1030 } 1031 1032 val = (*pil->pil_func)(pil->pil_arg); 1033 1034 if (splchanged != 0) { 1035 splx(s); 1036 } 1037 1038 retval = retval == 1 ? 1 : 1039 retval == 0 ? val : val != 0 ? val : retval; 1040 } 1041 1042 return retval; 1043 } 1044 1045 static void 1046 pci113x_insert(arg) 1047 void *arg; 1048 { 1049 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1050 u_int32_t sockevent, sockstate; 1051 1052 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1053 CB_SOCKET_EVENT); 1054 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1055 CB_SOCKET_STAT); 1056 1057 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1058 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1059 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1060 sc->sc_flags |= CBB_CARDEXIST; 1061 /* call pccard interrupt handler here */ 1062 if (sockstate & CB_SOCKET_STAT_16BIT) { 1063 /* 16-bit card found */ 1064 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1065 cardslot_event_throw(sc->sc_csc, 1066 CARDSLOT_EVENT_INSERTION_16); 1067 } else if (sockstate & CB_SOCKET_STAT_CB) { 1068 /* cardbus card found */ 1069 /* cardbus_attach_card(sc->sc_csc); */ 1070 cardslot_event_throw(sc->sc_csc, 1071 CARDSLOT_EVENT_INSERTION_CB); 1072 } else { 1073 /* who are you? */ 1074 } 1075 } else { 1076 callout_reset(&sc->sc_insert_ch, hz / 10, 1077 pci113x_insert, sc); 1078 } 1079 } 1080 1081 #define PCCBB_PCMCIA_OFFSET 0x800 1082 static u_int8_t 1083 pccbb_pcmcia_read(ph, reg) 1084 struct pcic_handle *ph; 1085 int reg; 1086 { 1087 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1088 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1089 1090 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1091 PCCBB_PCMCIA_OFFSET + reg); 1092 } 1093 1094 static void 1095 pccbb_pcmcia_write(ph, reg, val) 1096 struct pcic_handle *ph; 1097 int reg; 1098 u_int8_t val; 1099 { 1100 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1101 val); 1102 1103 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1104 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1105 } 1106 1107 /* 1108 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1109 */ 1110 STATIC int 1111 pccbb_ctrl(ct, command) 1112 cardbus_chipset_tag_t ct; 1113 int command; 1114 { 1115 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1116 1117 switch (command) { 1118 case CARDBUS_CD: 1119 if (2 == pccbb_detect_card(sc)) { 1120 int retval = 0; 1121 int status = cb_detect_voltage(sc); 1122 if (PCCARD_VCC_5V & status) { 1123 retval |= CARDBUS_5V_CARD; 1124 } 1125 if (PCCARD_VCC_3V & status) { 1126 retval |= CARDBUS_3V_CARD; 1127 } 1128 if (PCCARD_VCC_XV & status) { 1129 retval |= CARDBUS_XV_CARD; 1130 } 1131 if (PCCARD_VCC_YV & status) { 1132 retval |= CARDBUS_YV_CARD; 1133 } 1134 return retval; 1135 } else { 1136 return 0; 1137 } 1138 break; 1139 case CARDBUS_RESET: 1140 return cb_reset(sc); 1141 break; 1142 case CARDBUS_IO_ENABLE: /* fallthrough */ 1143 case CARDBUS_IO_DISABLE: /* fallthrough */ 1144 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1145 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1146 case CARDBUS_BM_ENABLE: /* fallthrough */ 1147 case CARDBUS_BM_DISABLE: /* fallthrough */ 1148 return pccbb_cardenable(sc, command); 1149 break; 1150 } 1151 1152 return 0; 1153 } 1154 1155 /* 1156 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1157 * This function returns true when it succeeds and returns false when 1158 * it fails. 1159 */ 1160 STATIC int 1161 pccbb_power(ct, command) 1162 cardbus_chipset_tag_t ct; 1163 int command; 1164 { 1165 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1166 1167 u_int32_t status, sock_ctrl; 1168 bus_space_tag_t memt = sc->sc_base_memt; 1169 bus_space_handle_t memh = sc->sc_base_memh; 1170 1171 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1172 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1173 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1174 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1175 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1176 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1177 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1178 "UNKNOWN", 1179 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1180 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1181 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1182 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1183 "UNKNOWN", command)); 1184 1185 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1186 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1187 1188 switch (command & CARDBUS_VCCMASK) { 1189 case CARDBUS_VCC_UC: 1190 break; 1191 case CARDBUS_VCC_5V: 1192 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1193 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1194 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1195 } else { 1196 printf("%s: BAD voltage request: no 5 V card\n", 1197 sc->sc_dev.dv_xname); 1198 } 1199 break; 1200 case CARDBUS_VCC_3V: 1201 if (CB_SOCKET_STAT_3VCARD & status) { 1202 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1203 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1204 } else { 1205 printf("%s: BAD voltage request: no 3.3 V card\n", 1206 sc->sc_dev.dv_xname); 1207 } 1208 break; 1209 case CARDBUS_VCC_0V: 1210 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1211 break; 1212 default: 1213 return 0; /* power NEVER changed */ 1214 break; 1215 } 1216 1217 switch (command & CARDBUS_VPPMASK) { 1218 case CARDBUS_VPP_UC: 1219 break; 1220 case CARDBUS_VPP_0V: 1221 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1222 break; 1223 case CARDBUS_VPP_VCC: 1224 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1225 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1226 break; 1227 case CARDBUS_VPP_12V: 1228 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1229 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1230 break; 1231 } 1232 1233 #if 0 1234 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1235 #endif 1236 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1237 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1238 1239 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1240 printf 1241 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1242 sc->sc_dev.dv_xname, sock_ctrl, status); 1243 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1244 (command & CARDBUS_VCCMASK) == 1245 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1246 CARDBUS_VCCMASK) == 1247 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1248 CARDBUS_VCCMASK) == 1249 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1250 CARDBUS_VCCMASK) == 1251 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1252 CARDBUS_VCCMASK) == 1253 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1254 CARDBUS_VCCMASK) == 1255 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1256 (command & CARDBUS_VPPMASK) == 1257 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1258 CARDBUS_VPPMASK) == 1259 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1260 CARDBUS_VPPMASK) == 1261 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1262 CARDBUS_VPPMASK) == 1263 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1264 #if 0 1265 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1266 u_int32_t force = 1267 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1268 /* Reset Bad Vcc request */ 1269 force &= ~CB_SOCKET_FORCE_BADVCC; 1270 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1271 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1272 CB_SOCKET_STAT)); 1273 return 1; 1274 } 1275 #endif 1276 return 0; 1277 } 1278 1279 /* 1280 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1281 * time is 20 ms, some PC-Card bridge requires longer duration. 1282 */ 1283 delay(300 * 1000); 1284 1285 return 1; /* power changed correctly */ 1286 } 1287 1288 #if defined CB_PCMCIA_POLL 1289 struct cb_poll_str { 1290 void *arg; 1291 int (*func) __P((void *)); 1292 int level; 1293 pccard_chipset_tag_t ct; 1294 int count; 1295 struct callout poll_ch; 1296 }; 1297 1298 static struct cb_poll_str cb_poll[10]; 1299 static int cb_poll_n = 0; 1300 1301 static void cb_pcmcia_poll __P((void *arg)); 1302 1303 static void 1304 cb_pcmcia_poll(arg) 1305 void *arg; 1306 { 1307 struct cb_poll_str *poll = arg; 1308 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1309 struct pccbb_softc *sc = psc->cpc_parent; 1310 int s; 1311 u_int32_t spsr; /* socket present-state reg */ 1312 1313 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1314 switch (poll->level) { 1315 case IPL_NET: 1316 s = splnet(); 1317 break; 1318 case IPL_BIO: 1319 s = splbio(); 1320 break; 1321 case IPL_TTY: /* fallthrough */ 1322 default: 1323 s = spltty(); 1324 break; 1325 } 1326 1327 spsr = 1328 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1329 CB_SOCKET_STAT); 1330 1331 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1332 if (!(spsr & 0x40)) { /* CINT low */ 1333 #else 1334 if (1) { 1335 #endif 1336 if ((*poll->func) (poll->arg) == 1) { 1337 ++poll->count; 1338 printf("intr: reported from poller, 0x%x\n", spsr); 1339 #if defined LEVEL2 1340 } else { 1341 printf("intr: miss! 0x%x\n", spsr); 1342 #endif 1343 } 1344 } 1345 splx(s); 1346 } 1347 #endif /* defined CB_PCMCIA_POLL */ 1348 1349 /* 1350 * static int pccbb_detect_card(struct pccbb_softc *sc) 1351 * return value: 0 if no card exists. 1352 * 1 if 16-bit card exists. 1353 * 2 if cardbus card exists. 1354 */ 1355 static int 1356 pccbb_detect_card(sc) 1357 struct pccbb_softc *sc; 1358 { 1359 bus_space_handle_t base_memh = sc->sc_base_memh; 1360 bus_space_tag_t base_memt = sc->sc_base_memt; 1361 u_int32_t sockstat = 1362 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1363 int retval = 0; 1364 1365 /* CD1 and CD2 asserted */ 1366 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1367 /* card must be present */ 1368 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1369 /* NOTACARD DEASSERTED */ 1370 if (CB_SOCKET_STAT_CB & sockstat) { 1371 /* CardBus mode */ 1372 retval = 2; 1373 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1374 /* 16-bit mode */ 1375 retval = 1; 1376 } 1377 } 1378 } 1379 return retval; 1380 } 1381 1382 /* 1383 * STATIC int cb_reset(struct pccbb_softc *sc) 1384 * This function resets CardBus card. 1385 */ 1386 STATIC int 1387 cb_reset(sc) 1388 struct pccbb_softc *sc; 1389 { 1390 /* 1391 * Reset Assert at least 20 ms 1392 * Some machines request longer duration. 1393 */ 1394 int reset_duration = 1395 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1396 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1397 1398 /* Reset bit Assert (bit 6 at 0x3E) */ 1399 bcr |= CB_BCR_RESET_ENABLE; 1400 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1401 delay(reset_duration); 1402 1403 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1404 /* Reset bit Deassert (bit 6 at 0x3E) */ 1405 bcr &= ~CB_BCR_RESET_ENABLE; 1406 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1407 delay(reset_duration); 1408 } 1409 /* No card found on the slot. Keep Reset. */ 1410 return 1; 1411 } 1412 1413 /* 1414 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1415 * This function detect card Voltage. 1416 */ 1417 STATIC int 1418 cb_detect_voltage(sc) 1419 struct pccbb_softc *sc; 1420 { 1421 u_int32_t psr; /* socket present-state reg */ 1422 bus_space_tag_t iot = sc->sc_base_memt; 1423 bus_space_handle_t ioh = sc->sc_base_memh; 1424 int vol = PCCARD_VCC_UKN; /* set 0 */ 1425 1426 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1427 1428 if (0x400u & psr) { 1429 vol |= PCCARD_VCC_5V; 1430 } 1431 if (0x800u & psr) { 1432 vol |= PCCARD_VCC_3V; 1433 } 1434 1435 return vol; 1436 } 1437 1438 STATIC int 1439 cbbprint(aux, pcic) 1440 void *aux; 1441 const char *pcic; 1442 { 1443 /* 1444 struct cbslot_attach_args *cba = aux; 1445 1446 if (cba->cba_slot >= 0) { 1447 printf(" slot %d", cba->cba_slot); 1448 } 1449 */ 1450 return UNCONF; 1451 } 1452 1453 /* 1454 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1455 * This function enables and disables the card 1456 */ 1457 STATIC int 1458 pccbb_cardenable(sc, function) 1459 struct pccbb_softc *sc; 1460 int function; 1461 { 1462 u_int32_t command = 1463 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1464 1465 DPRINTF(("pccbb_cardenable:")); 1466 switch (function) { 1467 case CARDBUS_IO_ENABLE: 1468 command |= PCI_COMMAND_IO_ENABLE; 1469 break; 1470 case CARDBUS_IO_DISABLE: 1471 command &= ~PCI_COMMAND_IO_ENABLE; 1472 break; 1473 case CARDBUS_MEM_ENABLE: 1474 command |= PCI_COMMAND_MEM_ENABLE; 1475 break; 1476 case CARDBUS_MEM_DISABLE: 1477 command &= ~PCI_COMMAND_MEM_ENABLE; 1478 break; 1479 case CARDBUS_BM_ENABLE: 1480 command |= PCI_COMMAND_MASTER_ENABLE; 1481 break; 1482 case CARDBUS_BM_DISABLE: 1483 command &= ~PCI_COMMAND_MASTER_ENABLE; 1484 break; 1485 default: 1486 return 0; 1487 } 1488 1489 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1490 DPRINTF((" command reg 0x%x\n", command)); 1491 return 1; 1492 } 1493 1494 #if !rbus 1495 /* 1496 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1497 */ 1498 static int 1499 pccbb_io_open(ct, win, start, end) 1500 cardbus_chipset_tag_t ct; 1501 int win; 1502 u_int32_t start, end; 1503 { 1504 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1505 int basereg; 1506 int limitreg; 1507 1508 if ((win < 0) || (win > 2)) { 1509 #if defined DIAGNOSTIC 1510 printf("cardbus_io_open: window out of range %d\n", win); 1511 #endif 1512 return 0; 1513 } 1514 1515 basereg = win * 8 + 0x2c; 1516 limitreg = win * 8 + 0x30; 1517 1518 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1519 start, basereg, end, limitreg)); 1520 1521 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1522 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1523 return 1; 1524 } 1525 1526 /* 1527 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1528 */ 1529 static int 1530 pccbb_io_close(ct, win) 1531 cardbus_chipset_tag_t ct; 1532 int win; 1533 { 1534 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1535 int basereg; 1536 int limitreg; 1537 1538 if ((win < 0) || (win > 2)) { 1539 #if defined DIAGNOSTIC 1540 printf("cardbus_io_close: window out of range %d\n", win); 1541 #endif 1542 return 0; 1543 } 1544 1545 basereg = win * 8 + 0x2c; 1546 limitreg = win * 8 + 0x30; 1547 1548 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1549 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1550 return 1; 1551 } 1552 1553 /* 1554 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1555 */ 1556 static int 1557 pccbb_mem_open(ct, win, start, end) 1558 cardbus_chipset_tag_t ct; 1559 int win; 1560 u_int32_t start, end; 1561 { 1562 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1563 int basereg; 1564 int limitreg; 1565 1566 if ((win < 0) || (win > 2)) { 1567 #if defined DIAGNOSTIC 1568 printf("cardbus_mem_open: window out of range %d\n", win); 1569 #endif 1570 return 0; 1571 } 1572 1573 basereg = win * 8 + 0x1c; 1574 limitreg = win * 8 + 0x20; 1575 1576 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1577 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1578 return 1; 1579 } 1580 1581 /* 1582 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1583 */ 1584 static int 1585 pccbb_mem_close(ct, win) 1586 cardbus_chipset_tag_t ct; 1587 int win; 1588 { 1589 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1590 int basereg; 1591 int limitreg; 1592 1593 if ((win < 0) || (win > 2)) { 1594 #if defined DIAGNOSTIC 1595 printf("cardbus_mem_close: window out of range %d\n", win); 1596 #endif 1597 return 0; 1598 } 1599 1600 basereg = win * 8 + 0x1c; 1601 limitreg = win * 8 + 0x20; 1602 1603 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1604 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1605 return 1; 1606 } 1607 #endif 1608 1609 /* 1610 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1611 * int irq, 1612 * int level, 1613 * int (* func) __P((void *)), 1614 * void *arg) 1615 * 1616 * This function registers an interrupt handler at the bridge, in 1617 * order not to call the interrupt handlers of child devices when 1618 * a card-deletion interrupt occurs. 1619 * 1620 * The arguments irq and level are not used. 1621 */ 1622 static void * 1623 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1624 cardbus_chipset_tag_t ct; 1625 int irq, level; 1626 int (*func) __P((void *)); 1627 void *arg; 1628 { 1629 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1630 1631 return pccbb_intr_establish(sc, irq, level, func, arg); 1632 } 1633 1634 1635 /* 1636 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1637 * void *ih) 1638 * 1639 * This function removes an interrupt handler pointed by ih. 1640 */ 1641 static void 1642 pccbb_cb_intr_disestablish(ct, ih) 1643 cardbus_chipset_tag_t ct; 1644 void *ih; 1645 { 1646 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1647 1648 pccbb_intr_disestablish(sc, ih); 1649 } 1650 1651 1652 /* 1653 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1654 * int irq, 1655 * int level, 1656 * int (* func) __P((void *)), 1657 * void *arg) 1658 * 1659 * This function registers an interrupt handler at the bridge, in 1660 * order not to call the interrupt handlers of child devices when 1661 * a card-deletion interrupt occurs. 1662 * 1663 * The arguments irq is not used because pccbb selects intr vector. 1664 */ 1665 static void * 1666 pccbb_intr_establish(sc, irq, level, func, arg) 1667 struct pccbb_softc *sc; 1668 int irq, level; 1669 int (*func) __P((void *)); 1670 void *arg; 1671 { 1672 struct pccbb_intrhand_list *pil, *newpil; 1673 pcireg_t reg; 1674 1675 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1676 1677 if (sc->sc_pil == NULL) { 1678 /* initialize bridge intr routing */ 1679 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1680 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1681 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1682 1683 switch (sc->sc_chipset) { 1684 case CB_TI113X: 1685 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1686 /* functional intr enabled */ 1687 reg |= PCI113X_CBCTRL_PCI_INTR; 1688 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1689 break; 1690 default: 1691 break; 1692 } 1693 } 1694 1695 /* 1696 * Allocate a room for interrupt handler structure. 1697 */ 1698 if (NULL == (newpil = 1699 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1700 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1701 return NULL; 1702 } 1703 1704 newpil->pil_func = func; 1705 newpil->pil_arg = arg; 1706 newpil->pil_level = level; 1707 newpil->pil_next = NULL; 1708 1709 if (sc->sc_pil == NULL) { 1710 sc->sc_pil = newpil; 1711 } else { 1712 for (pil = sc->sc_pil; pil->pil_next != NULL; 1713 pil = pil->pil_next); 1714 pil->pil_next = newpil; 1715 } 1716 1717 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1718 1719 return newpil; 1720 } 1721 1722 /* 1723 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1724 * void *ih) 1725 * 1726 * This function removes an interrupt handler pointed by ih. 1727 */ 1728 static void 1729 pccbb_intr_disestablish(sc, ih) 1730 struct pccbb_softc *sc; 1731 void *ih; 1732 { 1733 struct pccbb_intrhand_list *pil, **pil_prev; 1734 pcireg_t reg; 1735 1736 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1737 1738 pil_prev = &sc->sc_pil; 1739 1740 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1741 if (pil == ih) { 1742 *pil_prev = pil->pil_next; 1743 free(pil, M_DEVBUF); 1744 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1745 break; 1746 } 1747 pil_prev = &pil->pil_next; 1748 } 1749 1750 if (sc->sc_pil == NULL) { 1751 /* No interrupt handlers */ 1752 1753 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1754 1755 /* stop routing PCI intr */ 1756 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1757 reg |= CB_BCR_INTR_IREQ_ENABLE; 1758 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1759 1760 switch (sc->sc_chipset) { 1761 case CB_TI113X: 1762 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1763 /* functional intr disabled */ 1764 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1765 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1766 break; 1767 default: 1768 break; 1769 } 1770 } 1771 } 1772 1773 #if defined SHOW_REGS 1774 static void 1775 cb_show_regs(pc, tag, memt, memh) 1776 pci_chipset_tag_t pc; 1777 pcitag_t tag; 1778 bus_space_tag_t memt; 1779 bus_space_handle_t memh; 1780 { 1781 int i; 1782 printf("PCI config regs:"); 1783 for (i = 0; i < 0x50; i += 4) { 1784 if (i % 16 == 0) { 1785 printf("\n 0x%02x:", i); 1786 } 1787 printf(" %08x", pci_conf_read(pc, tag, i)); 1788 } 1789 for (i = 0x80; i < 0xb0; i += 4) { 1790 if (i % 16 == 0) { 1791 printf("\n 0x%02x:", i); 1792 } 1793 printf(" %08x", pci_conf_read(pc, tag, i)); 1794 } 1795 1796 if (memh == 0) { 1797 printf("\n"); 1798 return; 1799 } 1800 1801 printf("\nsocket regs:"); 1802 for (i = 0; i <= 0x10; i += 0x04) { 1803 printf(" %08x", bus_space_read_4(memt, memh, i)); 1804 } 1805 printf("\nExCA regs:"); 1806 for (i = 0; i < 0x08; ++i) { 1807 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1808 } 1809 printf("\n"); 1810 return; 1811 } 1812 #endif 1813 1814 /* 1815 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1816 * int busno, int devno, int function) 1817 * This is the function to make a tag to access config space of 1818 * a CardBus Card. It works same as pci_conf_read. 1819 */ 1820 static cardbustag_t 1821 pccbb_make_tag(cc, busno, devno, function) 1822 cardbus_chipset_tag_t cc; 1823 int busno, devno, function; 1824 { 1825 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1826 1827 return pci_make_tag(sc->sc_pc, busno, devno, function); 1828 } 1829 1830 static void 1831 pccbb_free_tag(cc, tag) 1832 cardbus_chipset_tag_t cc; 1833 cardbustag_t tag; 1834 { 1835 } 1836 1837 /* 1838 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1839 * cardbustag_t tag, int offset) 1840 * This is the function to read the config space of a CardBus Card. 1841 * It works same as pci_conf_read. 1842 */ 1843 static cardbusreg_t 1844 pccbb_conf_read(cc, tag, offset) 1845 cardbus_chipset_tag_t cc; 1846 cardbustag_t tag; 1847 int offset; /* register offset */ 1848 { 1849 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1850 1851 return pci_conf_read(sc->sc_pc, tag, offset); 1852 } 1853 1854 /* 1855 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1856 * int offs, cardbusreg_t val) 1857 * This is the function to write the config space of a CardBus Card. 1858 * It works same as pci_conf_write. 1859 */ 1860 static void 1861 pccbb_conf_write(cc, tag, reg, val) 1862 cardbus_chipset_tag_t cc; 1863 cardbustag_t tag; 1864 int reg; /* register offset */ 1865 cardbusreg_t val; 1866 { 1867 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1868 1869 pci_conf_write(sc->sc_pc, tag, reg, val); 1870 } 1871 1872 #if 0 1873 STATIC int 1874 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1875 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1876 int speed, int flags, 1877 bus_space_handle_t * iohp) 1878 #endif 1879 /* 1880 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1881 * bus_addr_t start, bus_size_t size, 1882 * bus_size_t align, 1883 * struct pcmcia_io_handle *pcihp 1884 * 1885 * This function only allocates I/O region for pccard. This function 1886 * never maps the allocated region to pccard I/O area. 1887 * 1888 * XXX: The interface of this function is not very good, I believe. 1889 */ 1890 STATIC int 1891 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1892 pcmcia_chipset_handle_t pch; 1893 bus_addr_t start; /* start address */ 1894 bus_size_t size; 1895 bus_size_t align; 1896 struct pcmcia_io_handle *pcihp; 1897 { 1898 struct pcic_handle *ph = (struct pcic_handle *)pch; 1899 bus_addr_t ioaddr; 1900 int flags = 0; 1901 bus_space_tag_t iot; 1902 bus_space_handle_t ioh; 1903 #if rbus 1904 rbus_tag_t rb; 1905 #endif 1906 if (align == 0) { 1907 align = size; /* XXX: funny??? */ 1908 } 1909 1910 /* 1911 * Allocate some arbitrary I/O space. 1912 */ 1913 1914 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1915 1916 #if rbus 1917 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1918 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1919 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1920 return 1; 1921 } 1922 #else 1923 if (start) { 1924 ioaddr = start; 1925 if (bus_space_map(iot, start, size, 0, &ioh)) { 1926 return 1; 1927 } 1928 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1929 (u_long) ioaddr, (u_long) size)); 1930 } else { 1931 flags |= PCMCIA_IO_ALLOCATED; 1932 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1933 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1934 size, align, 0, 0, &ioaddr, &ioh)) { 1935 /* No room be able to be get. */ 1936 return 1; 1937 } 1938 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1939 (u_long) ioaddr, (u_long) size)); 1940 } 1941 #endif 1942 1943 pcihp->iot = iot; 1944 pcihp->ioh = ioh; 1945 pcihp->addr = ioaddr; 1946 pcihp->size = size; 1947 pcihp->flags = flags; 1948 1949 return 0; 1950 } 1951 1952 /* 1953 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1954 * struct pcmcia_io_handle *pcihp) 1955 * 1956 * This function only frees I/O region for pccard. 1957 * 1958 * XXX: The interface of this function is not very good, I believe. 1959 */ 1960 void 1961 pccbb_pcmcia_io_free(pch, pcihp) 1962 pcmcia_chipset_handle_t pch; 1963 struct pcmcia_io_handle *pcihp; 1964 { 1965 #if !rbus 1966 bus_space_tag_t iot = pcihp->iot; 1967 #endif 1968 bus_space_handle_t ioh = pcihp->ioh; 1969 bus_size_t size = pcihp->size; 1970 1971 #if rbus 1972 struct pccbb_softc *sc = 1973 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1974 rbus_tag_t rb = sc->sc_rbus_iot; 1975 1976 rbus_space_free(rb, ioh, size, NULL); 1977 #else 1978 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1979 bus_space_free(iot, ioh, size); 1980 else 1981 bus_space_unmap(iot, ioh, size); 1982 #endif 1983 } 1984 1985 /* 1986 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1987 * bus_addr_t offset, bus_size_t size, 1988 * struct pcmcia_io_handle *pcihp, 1989 * int *windowp) 1990 * 1991 * This function maps the allocated I/O region to pccard. This function 1992 * never allocates any I/O region for pccard I/O area. I don't 1993 * understand why the original authors of pcmciabus separated alloc and 1994 * map. I believe the two must be unite. 1995 * 1996 * XXX: no wait timing control? 1997 */ 1998 int 1999 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2000 pcmcia_chipset_handle_t pch; 2001 int width; 2002 bus_addr_t offset; 2003 bus_size_t size; 2004 struct pcmcia_io_handle *pcihp; 2005 int *windowp; 2006 { 2007 struct pcic_handle *ph = (struct pcic_handle *)pch; 2008 bus_addr_t ioaddr = pcihp->addr + offset; 2009 int i, win; 2010 #if defined CBB_DEBUG 2011 static char *width_names[] = { "dynamic", "io8", "io16" }; 2012 #endif 2013 2014 /* Sanity check I/O handle. */ 2015 2016 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2017 panic("pccbb_pcmcia_io_map iot is bogus"); 2018 } 2019 2020 /* XXX Sanity check offset/size. */ 2021 2022 win = -1; 2023 for (i = 0; i < PCIC_IO_WINS; i++) { 2024 if ((ph->ioalloc & (1 << i)) == 0) { 2025 win = i; 2026 ph->ioalloc |= (1 << i); 2027 break; 2028 } 2029 } 2030 2031 if (win == -1) { 2032 return 1; 2033 } 2034 2035 *windowp = win; 2036 2037 /* XXX this is pretty gross */ 2038 2039 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2040 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2041 2042 /* XXX wtf is this doing here? */ 2043 2044 #if 0 2045 printf(" port 0x%lx", (u_long) ioaddr); 2046 if (size > 1) { 2047 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2048 } 2049 #endif 2050 2051 ph->io[win].addr = ioaddr; 2052 ph->io[win].size = size; 2053 ph->io[win].width = width; 2054 2055 /* actual dirty register-value changing in the function below. */ 2056 pccbb_pcmcia_do_io_map(ph, win); 2057 2058 return 0; 2059 } 2060 2061 /* 2062 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2063 * 2064 * This function changes register-value to map I/O region for pccard. 2065 */ 2066 static void 2067 pccbb_pcmcia_do_io_map(ph, win) 2068 struct pcic_handle *ph; 2069 int win; 2070 { 2071 static u_int8_t pcic_iowidth[3] = { 2072 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2073 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2074 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2075 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2076 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2077 }; 2078 2079 #define PCIC_SIA_START_LOW 0 2080 #define PCIC_SIA_START_HIGH 1 2081 #define PCIC_SIA_STOP_LOW 2 2082 #define PCIC_SIA_STOP_HIGH 3 2083 2084 int regbase_win = 0x8 + win * 0x04; 2085 u_int8_t ioctl, enable; 2086 2087 DPRINTF( 2088 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2089 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2090 ph->io[win].width * 8)); 2091 2092 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2093 ph->io[win].addr & 0xff); 2094 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2095 (ph->io[win].addr >> 8) & 0xff); 2096 2097 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2098 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2099 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2100 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2101 2102 ioctl = Pcic_read(ph, PCIC_IOCTL); 2103 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2104 switch (win) { 2105 case 0: 2106 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2107 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2108 PCIC_IOCTL_IO0_DATASIZE_MASK); 2109 ioctl |= pcic_iowidth[ph->io[win].width]; 2110 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2111 break; 2112 case 1: 2113 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2114 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2115 PCIC_IOCTL_IO1_DATASIZE_MASK); 2116 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2117 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2118 break; 2119 } 2120 Pcic_write(ph, PCIC_IOCTL, ioctl); 2121 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2122 #if defined CBB_DEBUG 2123 { 2124 u_int8_t start_low = 2125 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2126 u_int8_t start_high = 2127 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2128 u_int8_t stop_low = 2129 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2130 u_int8_t stop_high = 2131 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2132 printf 2133 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2134 start_low, start_high, stop_low, stop_high, ioctl, enable); 2135 } 2136 #endif 2137 } 2138 2139 /* 2140 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2141 * 2142 * This function unmaps I/O region. No return value. 2143 */ 2144 STATIC void 2145 pccbb_pcmcia_io_unmap(pch, win) 2146 pcmcia_chipset_handle_t pch; 2147 int win; 2148 { 2149 struct pcic_handle *ph = (struct pcic_handle *)pch; 2150 int reg; 2151 2152 if (win >= PCIC_IO_WINS || win < 0) { 2153 panic("pccbb_pcmcia_io_unmap: window out of range"); 2154 } 2155 2156 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2157 switch (win) { 2158 case 0: 2159 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2160 break; 2161 case 1: 2162 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2163 break; 2164 } 2165 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2166 2167 ph->ioalloc &= ~(1 << win); 2168 } 2169 2170 /* 2171 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2172 * 2173 * This function enables the card. All information is stored in 2174 * the first argument, pcmcia_chipset_handle_t. 2175 */ 2176 static void 2177 pccbb_pcmcia_wait_ready(ph) 2178 struct pcic_handle *ph; 2179 { 2180 int i; 2181 2182 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2183 Pcic_read(ph, PCIC_IF_STATUS))); 2184 2185 for (i = 0; i < 10000; i++) { 2186 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2187 return; 2188 } 2189 delay(500); 2190 #ifdef CBB_DEBUG 2191 if ((i > 5000) && (i % 100 == 99)) 2192 printf("."); 2193 #endif 2194 } 2195 2196 #ifdef DIAGNOSTIC 2197 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2198 Pcic_read(ph, PCIC_IF_STATUS)); 2199 #endif 2200 } 2201 2202 /* 2203 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2204 * 2205 * This function enables the card. All information is stored in 2206 * the first argument, pcmcia_chipset_handle_t. 2207 */ 2208 STATIC void 2209 pccbb_pcmcia_socket_enable(pch) 2210 pcmcia_chipset_handle_t pch; 2211 { 2212 struct pcic_handle *ph = (struct pcic_handle *)pch; 2213 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2214 int cardtype, win; 2215 u_int8_t power, intr; 2216 pcireg_t spsr; 2217 int voltage; 2218 2219 /* this bit is mostly stolen from pcic_attach_card */ 2220 2221 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2222 2223 /* get card Vcc info */ 2224 2225 spsr = 2226 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2227 CB_SOCKET_STAT); 2228 if (spsr & CB_SOCKET_STAT_5VCARD) { 2229 DPRINTF(("5V card\n")); 2230 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2231 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2232 DPRINTF(("3V card\n")); 2233 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2234 } else { 2235 printf("?V card, 0x%x\n", spsr); /* XXX */ 2236 return; 2237 } 2238 2239 /* disable socket i/o: negate output enable bit */ 2240 2241 power = 0; 2242 Pcic_write(ph, PCIC_PWRCTL, power); 2243 2244 /* power down the socket to reset it, clear the card reset pin */ 2245 2246 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2247 2248 /* 2249 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2250 * we are changing Vcc (Toff). 2251 */ 2252 /* delay(300*1000); too much */ 2253 2254 /* assert reset bit */ 2255 intr = Pcic_read(ph, PCIC_INTR); 2256 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2257 Pcic_write(ph, PCIC_INTR, intr); 2258 2259 /* power up the socket and output enable */ 2260 power = Pcic_read(ph, PCIC_PWRCTL); 2261 power |= PCIC_PWRCTL_OE; 2262 Pcic_write(ph, PCIC_PWRCTL, power); 2263 pccbb_power(sc, voltage); 2264 2265 /* 2266 * hold RESET at least 10us. 2267 */ 2268 delay(10); 2269 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2270 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2271 2272 /* clear the reset flag */ 2273 2274 intr |= PCIC_INTR_RESET; 2275 Pcic_write(ph, PCIC_INTR, intr); 2276 2277 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2278 2279 delay(20000); 2280 2281 /* wait for the chip to finish initializing */ 2282 2283 pccbb_pcmcia_wait_ready(ph); 2284 2285 /* zero out the address windows */ 2286 2287 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2288 2289 /* set the card type */ 2290 2291 cardtype = pcmcia_card_gettype(ph->pcmcia); 2292 2293 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2294 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2295 Pcic_write(ph, PCIC_INTR, intr); 2296 2297 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2298 ph->ph_parent->dv_xname, ph->sock, 2299 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2300 2301 /* reinstall all the memory and io mappings */ 2302 2303 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2304 if (ph->memalloc & (1 << win)) { 2305 pccbb_pcmcia_do_mem_map(ph, win); 2306 } 2307 } 2308 2309 for (win = 0; win < PCIC_IO_WINS; ++win) { 2310 if (ph->ioalloc & (1 << win)) { 2311 pccbb_pcmcia_do_io_map(ph, win); 2312 } 2313 } 2314 } 2315 2316 /* 2317 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2318 * 2319 * This function disables the card. All information is stored in 2320 * the first argument, pcmcia_chipset_handle_t. 2321 */ 2322 STATIC void 2323 pccbb_pcmcia_socket_disable(pch) 2324 pcmcia_chipset_handle_t pch; 2325 { 2326 struct pcic_handle *ph = (struct pcic_handle *)pch; 2327 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2328 u_int8_t power, intr; 2329 2330 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2331 2332 /* reset signal asserting... */ 2333 2334 intr = Pcic_read(ph, PCIC_INTR); 2335 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2336 Pcic_write(ph, PCIC_INTR, intr); 2337 delay(2 * 1000); 2338 2339 /* power down the socket */ 2340 power = Pcic_read(ph, PCIC_PWRCTL); 2341 power &= ~PCIC_PWRCTL_OE; 2342 Pcic_write(ph, PCIC_PWRCTL, power); 2343 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2344 /* 2345 * wait 300ms until power fails (Tpf). 2346 */ 2347 delay(300 * 1000); 2348 } 2349 2350 /* 2351 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2352 * 2353 * This function detects whether a card is in the slot or not. 2354 * If a card is inserted, return 1. Otherwise, return 0. 2355 */ 2356 STATIC int 2357 pccbb_pcmcia_card_detect(pch) 2358 pcmcia_chipset_handle_t pch; 2359 { 2360 struct pcic_handle *ph = (struct pcic_handle *)pch; 2361 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2362 2363 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2364 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2365 } 2366 2367 #if 0 2368 STATIC int 2369 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2370 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2371 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2372 #endif 2373 /* 2374 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2375 * bus_size_t size, 2376 * struct pcmcia_mem_handle *pcmhp) 2377 * 2378 * This function only allocates memory region for pccard. This 2379 * function never maps the allocated region to pccard memory area. 2380 * 2381 * XXX: Why the argument of start address is not in? 2382 */ 2383 STATIC int 2384 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2385 pcmcia_chipset_handle_t pch; 2386 bus_size_t size; 2387 struct pcmcia_mem_handle *pcmhp; 2388 { 2389 struct pcic_handle *ph = (struct pcic_handle *)pch; 2390 bus_space_handle_t memh; 2391 bus_addr_t addr; 2392 bus_size_t sizepg; 2393 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2394 #if rbus 2395 rbus_tag_t rb; 2396 #endif 2397 2398 /* out of sc->memh, allocate as many pages as necessary */ 2399 2400 /* convert size to PCIC pages */ 2401 /* 2402 * This is not enough; when the requested region is on the page 2403 * boundaries, this may calculate wrong result. 2404 */ 2405 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2406 #if 0 2407 if (sizepg > PCIC_MAX_MEM_PAGES) { 2408 return 1; 2409 } 2410 #endif 2411 2412 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2413 return 1; 2414 } 2415 2416 addr = 0; /* XXX gcc -Wuninitialized */ 2417 2418 #if rbus 2419 rb = sc->sc_rbus_memt; 2420 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2421 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2422 &addr, &memh)) { 2423 return 1; 2424 } 2425 #else 2426 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2427 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2428 0, /* boundary */ 2429 0, /* flags */ 2430 &addr, &memh)) { 2431 return 1; 2432 } 2433 #endif 2434 2435 DPRINTF( 2436 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2437 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2438 2439 pcmhp->memt = sc->sc_memt; 2440 pcmhp->memh = memh; 2441 pcmhp->addr = addr; 2442 pcmhp->size = size; 2443 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2444 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2445 pcmhp->mhandle = 0; 2446 /* No offset??? Funny. */ 2447 2448 return 0; 2449 } 2450 2451 /* 2452 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2453 * struct pcmcia_mem_handle *pcmhp) 2454 * 2455 * This function release the memory space allocated by the function 2456 * pccbb_pcmcia_mem_alloc(). 2457 */ 2458 STATIC void 2459 pccbb_pcmcia_mem_free(pch, pcmhp) 2460 pcmcia_chipset_handle_t pch; 2461 struct pcmcia_mem_handle *pcmhp; 2462 { 2463 #if rbus 2464 struct pcic_handle *ph = (struct pcic_handle *)pch; 2465 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2466 2467 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2468 #else 2469 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2470 #endif 2471 } 2472 2473 /* 2474 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2475 * 2476 * This function release the memory space allocated by the function 2477 * pccbb_pcmcia_mem_alloc(). 2478 */ 2479 STATIC void 2480 pccbb_pcmcia_do_mem_map(ph, win) 2481 struct pcic_handle *ph; 2482 int win; 2483 { 2484 int regbase_win; 2485 bus_addr_t phys_addr; 2486 bus_addr_t phys_end; 2487 2488 #define PCIC_SMM_START_LOW 0 2489 #define PCIC_SMM_START_HIGH 1 2490 #define PCIC_SMM_STOP_LOW 2 2491 #define PCIC_SMM_STOP_HIGH 3 2492 #define PCIC_CMA_LOW 4 2493 #define PCIC_CMA_HIGH 5 2494 2495 u_int8_t start_low, start_high = 0; 2496 u_int8_t stop_low, stop_high; 2497 u_int8_t off_low, off_high; 2498 u_int8_t mem_window; 2499 int reg; 2500 2501 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2502 int mem8 = 2503 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2504 || (kind == PCMCIA_MEM_ATTR); 2505 2506 regbase_win = 0x10 + win * 0x08; 2507 2508 phys_addr = ph->mem[win].addr; 2509 phys_end = phys_addr + ph->mem[win].size; 2510 2511 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2512 phys_addr, phys_end, ph->mem[win].offset)); 2513 2514 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2515 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2516 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2517 2518 /* bit 19:12 */ 2519 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2520 /* bit 23:20 and bit 7 on */ 2521 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2522 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2523 /* bit 31:24, for 32-bit address */ 2524 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2525 2526 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2527 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2528 2529 if (((struct pccbb_softc *)ph-> 2530 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2531 Pcic_write(ph, 0x40 + win, mem_window); 2532 } 2533 2534 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2535 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2536 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2537 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2538 2539 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2540 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2541 2542 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2543 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2544 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2545 | ((kind == PCMCIA_MEM_ATTR) ? 2546 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2547 2548 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2549 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2550 2551 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2552 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2553 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2554 2555 #if defined CBB_DEBUG 2556 { 2557 int r1, r2, r3, r4, r5, r6, r7 = 0; 2558 2559 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2560 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2561 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2562 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2563 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2564 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2565 if (((struct pccbb_softc *)(ph-> 2566 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2567 r7 = Pcic_read(ph, 0x40 + win); 2568 } 2569 2570 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2571 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2572 if (((struct pccbb_softc *)(ph-> 2573 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2574 DPRINTF((" %02x", r7)); 2575 } 2576 DPRINTF(("\n")); 2577 } 2578 #endif 2579 } 2580 2581 /* 2582 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2583 * bus_addr_t card_addr, bus_size_t size, 2584 * struct pcmcia_mem_handle *pcmhp, 2585 * bus_addr_t *offsetp, int *windowp) 2586 * 2587 * This function maps memory space allocated by the function 2588 * pccbb_pcmcia_mem_alloc(). 2589 */ 2590 STATIC int 2591 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2592 pcmcia_chipset_handle_t pch; 2593 int kind; 2594 bus_addr_t card_addr; 2595 bus_size_t size; 2596 struct pcmcia_mem_handle *pcmhp; 2597 bus_addr_t *offsetp; 2598 int *windowp; 2599 { 2600 struct pcic_handle *ph = (struct pcic_handle *)pch; 2601 bus_addr_t busaddr; 2602 long card_offset; 2603 int win; 2604 2605 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2606 if ((ph->memalloc & (1 << win)) == 0) { 2607 ph->memalloc |= (1 << win); 2608 break; 2609 } 2610 } 2611 2612 if (win == PCIC_MEM_WINS) { 2613 return 1; 2614 } 2615 2616 *windowp = win; 2617 2618 /* XXX this is pretty gross */ 2619 2620 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2621 panic("pccbb_pcmcia_mem_map memt is bogus"); 2622 } 2623 2624 busaddr = pcmhp->addr; 2625 2626 /* 2627 * compute the address offset to the pcmcia address space for the 2628 * pcic. this is intentionally signed. The masks and shifts below 2629 * will cause TRT to happen in the pcic registers. Deal with making 2630 * sure the address is aligned, and return the alignment offset. 2631 */ 2632 2633 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2634 card_addr -= *offsetp; 2635 2636 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2637 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2638 (u_long) card_addr)); 2639 2640 /* 2641 * include the offset in the size, and decrement size by one, since 2642 * the hw wants start/stop 2643 */ 2644 size += *offsetp - 1; 2645 2646 card_offset = (((long)card_addr) - ((long)busaddr)); 2647 2648 ph->mem[win].addr = busaddr; 2649 ph->mem[win].size = size; 2650 ph->mem[win].offset = card_offset; 2651 ph->mem[win].kind = kind; 2652 2653 pccbb_pcmcia_do_mem_map(ph, win); 2654 2655 return 0; 2656 } 2657 2658 /* 2659 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2660 * int window) 2661 * 2662 * This function unmaps memory space which mapped by the function 2663 * pccbb_pcmcia_mem_map(). 2664 */ 2665 STATIC void 2666 pccbb_pcmcia_mem_unmap(pch, window) 2667 pcmcia_chipset_handle_t pch; 2668 int window; 2669 { 2670 struct pcic_handle *ph = (struct pcic_handle *)pch; 2671 int reg; 2672 2673 if (window >= PCIC_MEM_WINS) { 2674 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2675 } 2676 2677 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2678 reg &= ~(1 << window); 2679 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2680 2681 ph->memalloc &= ~(1 << window); 2682 } 2683 2684 #if defined PCCBB_PCMCIA_POLL 2685 struct pccbb_poll_str { 2686 void *arg; 2687 int (*func) __P((void *)); 2688 int level; 2689 struct pcic_handle *ph; 2690 int count; 2691 int num; 2692 struct callout poll_ch; 2693 }; 2694 2695 static struct pccbb_poll_str pccbb_poll[10]; 2696 static int pccbb_poll_n = 0; 2697 2698 static void pccbb_pcmcia_poll __P((void *arg)); 2699 2700 static void 2701 pccbb_pcmcia_poll(arg) 2702 void *arg; 2703 { 2704 struct pccbb_poll_str *poll = arg; 2705 struct pcic_handle *ph = poll->ph; 2706 struct pccbb_softc *sc = ph->sc; 2707 int s; 2708 u_int32_t spsr; /* socket present-state reg */ 2709 2710 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2711 switch (poll->level) { 2712 case IPL_NET: 2713 s = splnet(); 2714 break; 2715 case IPL_BIO: 2716 s = splbio(); 2717 break; 2718 case IPL_TTY: /* fallthrough */ 2719 default: 2720 s = spltty(); 2721 break; 2722 } 2723 2724 spsr = 2725 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2726 CB_SOCKET_STAT); 2727 2728 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2729 if (!(spsr & 0x40)) /* CINT low */ 2730 #else 2731 if (1) 2732 #endif 2733 { 2734 if ((*poll->func) (poll->arg) > 0) { 2735 ++poll->count; 2736 // printf("intr: reported from poller, 0x%x\n", spsr); 2737 #if defined LEVEL2 2738 } else { 2739 printf("intr: miss! 0x%x\n", spsr); 2740 #endif 2741 } 2742 } 2743 splx(s); 2744 } 2745 #endif /* defined CB_PCMCIA_POLL */ 2746 2747 /* 2748 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2749 * struct pcmcia_function *pf, 2750 * int ipl, 2751 * int (*func)(void *), 2752 * void *arg); 2753 * 2754 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2755 */ 2756 STATIC void * 2757 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2758 pcmcia_chipset_handle_t pch; 2759 struct pcmcia_function *pf; 2760 int ipl; 2761 int (*func) __P((void *)); 2762 void *arg; 2763 { 2764 struct pcic_handle *ph = (struct pcic_handle *)pch; 2765 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2766 2767 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2768 /* what should I do? */ 2769 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2770 DPRINTF( 2771 ("%s does not provide edge nor pulse interrupt\n", 2772 sc->sc_dev.dv_xname)); 2773 return NULL; 2774 } 2775 /* 2776 * XXX Noooooo! The interrupt flag must set properly!! 2777 * dumb pcmcia driver!! 2778 */ 2779 } 2780 2781 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2782 } 2783 2784 /* 2785 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2786 * void *ih) 2787 * 2788 * This function disables PC-Card interrupt. 2789 */ 2790 STATIC void 2791 pccbb_pcmcia_intr_disestablish(pch, ih) 2792 pcmcia_chipset_handle_t pch; 2793 void *ih; 2794 { 2795 struct pcic_handle *ph = (struct pcic_handle *)pch; 2796 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2797 2798 pccbb_intr_disestablish(sc, ih); 2799 } 2800 2801 #if rbus 2802 /* 2803 * static int 2804 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2805 * bus_addr_t addr, bus_size_t size, 2806 * bus_addr_t mask, bus_size_t align, 2807 * int flags, bus_addr_t *addrp; 2808 * bus_space_handle_t *bshp) 2809 * 2810 * This function allocates a portion of memory or io space for 2811 * clients. This function is called from CardBus card drivers. 2812 */ 2813 static int 2814 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2815 cardbus_chipset_tag_t ct; 2816 rbus_tag_t rb; 2817 bus_addr_t addr; 2818 bus_size_t size; 2819 bus_addr_t mask; 2820 bus_size_t align; 2821 int flags; 2822 bus_addr_t *addrp; 2823 bus_space_handle_t *bshp; 2824 { 2825 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2826 2827 DPRINTF( 2828 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2829 addr, size, mask, align)); 2830 2831 if (align == 0) { 2832 align = size; 2833 } 2834 2835 if (rb->rb_bt == sc->sc_memt) { 2836 if (align < 16) { 2837 return 1; 2838 } 2839 } else if (rb->rb_bt == sc->sc_iot) { 2840 if (align < 4) { 2841 return 1; 2842 } 2843 /* XXX: hack for avoiding ISA image */ 2844 if (mask < 0x0100) { 2845 mask = 0x3ff; 2846 addr = 0x300; 2847 } 2848 2849 } else { 2850 DPRINTF( 2851 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2852 rb->rb_bt)); 2853 return 1; 2854 /* XXX: panic here? */ 2855 } 2856 2857 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2858 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2859 return 1; 2860 } 2861 2862 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2863 2864 return 0; 2865 } 2866 2867 /* 2868 * static int 2869 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2870 * bus_space_handle_t *bshp, bus_size_t size); 2871 * 2872 * This function is called from CardBus card drivers. 2873 */ 2874 static int 2875 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2876 cardbus_chipset_tag_t ct; 2877 rbus_tag_t rb; 2878 bus_space_handle_t bsh; 2879 bus_size_t size; 2880 { 2881 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2882 bus_space_tag_t bt = rb->rb_bt; 2883 2884 pccbb_close_win(sc, bt, bsh, size); 2885 2886 if (bt == sc->sc_memt) { 2887 } else if (bt == sc->sc_iot) { 2888 } else { 2889 return 1; 2890 /* XXX: panic here? */ 2891 } 2892 2893 return rbus_space_free(rb, bsh, size, NULL); 2894 } 2895 #endif /* rbus */ 2896 2897 #if rbus 2898 2899 static int 2900 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2901 struct pccbb_softc *sc; 2902 bus_space_tag_t bst; 2903 bus_addr_t addr; 2904 bus_size_t size; 2905 bus_space_handle_t bsh; 2906 int flags; 2907 { 2908 struct pccbb_win_chain_head *head; 2909 bus_addr_t align; 2910 2911 head = &sc->sc_iowindow; 2912 align = 0x04; 2913 if (sc->sc_memt == bst) { 2914 head = &sc->sc_memwindow; 2915 align = 0x1000; 2916 DPRINTF(("using memory window, %x %x %x\n\n", 2917 sc->sc_iot, sc->sc_memt, bst)); 2918 } 2919 2920 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2921 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2922 sc->sc_dev.dv_xname, 2923 (head == &sc->sc_memwindow) ? "mem" : "io"); 2924 } 2925 pccbb_winset(align, sc, bst); 2926 2927 return 0; 2928 } 2929 2930 static int 2931 pccbb_close_win(sc, bst, bsh, size) 2932 struct pccbb_softc *sc; 2933 bus_space_tag_t bst; 2934 bus_space_handle_t bsh; 2935 bus_size_t size; 2936 { 2937 struct pccbb_win_chain_head *head; 2938 bus_addr_t align; 2939 2940 head = &sc->sc_iowindow; 2941 align = 0x04; 2942 if (sc->sc_memt == bst) { 2943 head = &sc->sc_memwindow; 2944 align = 0x1000; 2945 } 2946 2947 if (pccbb_winlist_delete(head, bsh, size)) { 2948 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2949 sc->sc_dev.dv_xname, 2950 (head == &sc->sc_memwindow) ? "mem" : "io"); 2951 } 2952 pccbb_winset(align, sc, bst); 2953 2954 return 0; 2955 } 2956 2957 static int 2958 pccbb_winlist_insert(head, start, size, bsh, flags) 2959 struct pccbb_win_chain_head *head; 2960 bus_addr_t start; 2961 bus_size_t size; 2962 bus_space_handle_t bsh; 2963 int flags; 2964 { 2965 struct pccbb_win_chain *chainp, *elem; 2966 2967 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2968 M_NOWAIT)) == NULL) 2969 return (1); /* fail */ 2970 2971 elem->wc_start = start; 2972 elem->wc_end = start + (size - 1); 2973 elem->wc_handle = bsh; 2974 elem->wc_flags = flags; 2975 2976 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2977 chainp = TAILQ_NEXT(chainp, wc_list)) { 2978 if (chainp->wc_end < start) 2979 continue; 2980 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2981 return (0); 2982 } 2983 2984 TAILQ_INSERT_TAIL(head, elem, wc_list); 2985 return (0); 2986 } 2987 2988 static int 2989 pccbb_winlist_delete(head, bsh, size) 2990 struct pccbb_win_chain_head *head; 2991 bus_space_handle_t bsh; 2992 bus_size_t size; 2993 { 2994 struct pccbb_win_chain *chainp; 2995 2996 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2997 chainp = TAILQ_NEXT(chainp, wc_list)) { 2998 if (chainp->wc_handle != bsh) 2999 continue; 3000 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3001 printf("pccbb_winlist_delete: window 0x%lx size " 3002 "inconsistent: 0x%lx, 0x%lx\n", 3003 chainp->wc_start, 3004 chainp->wc_end - chainp->wc_start, 3005 size - 1); 3006 return 1; 3007 } 3008 3009 TAILQ_REMOVE(head, chainp, wc_list); 3010 free(chainp, M_DEVBUF); 3011 3012 return 0; 3013 } 3014 3015 return 1; /* fail: no candidate to remove */ 3016 } 3017 3018 static void 3019 pccbb_winset(align, sc, bst) 3020 bus_addr_t align; 3021 struct pccbb_softc *sc; 3022 bus_space_tag_t bst; 3023 { 3024 pci_chipset_tag_t pc; 3025 pcitag_t tag; 3026 bus_addr_t mask = ~(align - 1); 3027 struct { 3028 cardbusreg_t win_start; 3029 cardbusreg_t win_limit; 3030 int win_flags; 3031 } win[2]; 3032 struct pccbb_win_chain *chainp; 3033 int offs; 3034 3035 win[0].win_start = 0xffffffff; 3036 win[0].win_limit = 0; 3037 win[1].win_start = 0xffffffff; 3038 win[1].win_limit = 0; 3039 3040 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3041 offs = 0x2c; 3042 if (sc->sc_memt == bst) { 3043 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3044 offs = 0x1c; 3045 } 3046 3047 if (chainp != NULL) { 3048 win[0].win_start = chainp->wc_start & mask; 3049 win[0].win_limit = chainp->wc_end & mask; 3050 win[0].win_flags = chainp->wc_flags; 3051 chainp = TAILQ_NEXT(chainp, wc_list); 3052 } 3053 3054 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3055 if (win[1].win_start == 0xffffffff) { 3056 /* window 1 is not used */ 3057 if ((win[0].win_flags == chainp->wc_flags) && 3058 (win[0].win_limit + align >= 3059 (chainp->wc_start & mask))) { 3060 /* concatenate */ 3061 win[0].win_limit = chainp->wc_end & mask; 3062 } else { 3063 /* make new window */ 3064 win[1].win_start = chainp->wc_start & mask; 3065 win[1].win_limit = chainp->wc_end & mask; 3066 win[1].win_flags = chainp->wc_flags; 3067 } 3068 continue; 3069 } 3070 3071 /* Both windows are engaged. */ 3072 if (win[0].win_flags == win[1].win_flags) { 3073 /* same flags */ 3074 if (win[0].win_flags == chainp->wc_flags) { 3075 if (win[1].win_start - (win[0].win_limit + 3076 align) < 3077 (chainp->wc_start & mask) - 3078 ((chainp->wc_end & mask) + align)) { 3079 /* 3080 * merge window 0 and 1, and set win1 3081 * to chainp 3082 */ 3083 win[0].win_limit = win[1].win_limit; 3084 win[1].win_start = 3085 chainp->wc_start & mask; 3086 win[1].win_limit = 3087 chainp->wc_end & mask; 3088 } else { 3089 win[1].win_limit = 3090 chainp->wc_end & mask; 3091 } 3092 } else { 3093 /* different flags */ 3094 3095 /* concatenate win0 and win1 */ 3096 win[0].win_limit = win[1].win_limit; 3097 /* allocate win[1] to new space */ 3098 win[1].win_start = chainp->wc_start & mask; 3099 win[1].win_limit = chainp->wc_end & mask; 3100 win[1].win_flags = chainp->wc_flags; 3101 } 3102 } else { 3103 /* the flags of win[0] and win[1] is different */ 3104 if (win[0].win_flags == chainp->wc_flags) { 3105 win[0].win_limit = chainp->wc_end & mask; 3106 /* 3107 * XXX this creates overlapping windows, so 3108 * what should the poor bridge do if one is 3109 * cachable, and the other is not? 3110 */ 3111 printf("%s: overlapping windows\n", 3112 sc->sc_dev.dv_xname); 3113 } else { 3114 win[1].win_limit = chainp->wc_end & mask; 3115 } 3116 } 3117 } 3118 3119 pc = sc->sc_pc; 3120 tag = sc->sc_tag; 3121 pci_conf_write(pc, tag, offs, win[0].win_start); 3122 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3123 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3124 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3125 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3126 pci_conf_read(pc, tag, offs), 3127 pci_conf_read(pc, tag, offs + 4) + align, 3128 pci_conf_read(pc, tag, offs + 8), 3129 pci_conf_read(pc, tag, offs + 12) + align)); 3130 3131 if (bst == sc->sc_memt) { 3132 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3133 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3134 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3135 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3136 } 3137 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3138 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3139 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3140 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3141 } 3142 } 3143 } 3144 3145 #endif /* rbus */ 3146 3147 static void 3148 pccbb_powerhook(why, arg) 3149 int why; 3150 void *arg; 3151 { 3152 struct pccbb_softc *sc = arg; 3153 u_int32_t reg; 3154 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3155 bus_space_handle_t base_memh = sc->sc_base_memh; 3156 3157 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3158 3159 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3160 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3161 if (sc->sc_pil_intr_enable) { 3162 (void)pccbbintr_function(sc); 3163 } 3164 sc->sc_pil_intr_enable = 0; 3165 3166 /* ToDo: deactivate or suspend child devices */ 3167 3168 } 3169 3170 if (why == PWR_RESUME) { 3171 /* CSC Interrupt: Card detect interrupt on */ 3172 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3173 /* Card detect intr is turned on. */ 3174 reg |= CB_SOCKET_MASK_CD; 3175 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3176 /* reset interrupt */ 3177 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3178 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3179 3180 /* 3181 * check for card insertion or removal during suspend period. 3182 * XXX: the code can't cope with card swap (remove then 3183 * insert). how can we detect such situation? 3184 */ 3185 (void)pccbbintr(sc); 3186 3187 sc->sc_pil_intr_enable = 1; 3188 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3189 3190 /* ToDo: activate or wakeup child devices */ 3191 } 3192 } 3193
Indexes created Fri Sep 26 20:09:58 GMT 2025