pccbb.c revision 1.52
1 /* $NetBSD: pccbb.c,v 1.52 2000/12/30 00:37:24 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/reboot.h> 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 57 #include <machine/intr.h> 58 #include <machine/bus.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/pci/pccbbreg.h> 65 66 #include <dev/cardbus/cardslotvar.h> 67 68 #include <dev/cardbus/cardbusvar.h> 69 70 #include <dev/pcmcia/pcmciareg.h> 71 #include <dev/pcmcia/pcmciavar.h> 72 73 #include <dev/ic/i82365reg.h> 74 #include <dev/ic/i82365var.h> 75 #include <dev/pci/pccbbvar.h> 76 77 #include "locators.h" 78 79 #ifndef __NetBSD_Version__ 80 struct cfdriver cbb_cd = { 81 NULL, "cbb", DV_DULL 82 }; 83 #endif 84 85 #if defined CBB_DEBUG 86 #define DPRINTF(x) printf x 87 #define STATIC 88 #else 89 #define DPRINTF(x) 90 #define STATIC static 91 #endif 92 93 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 94 void pccbbattach __P((struct device *, struct device *, void *)); 95 int pccbbintr __P((void *)); 96 static void pci113x_insert __P((void *)); 97 static int pccbbintr_function __P((struct pccbb_softc *)); 98 99 static int pccbb_detect_card __P((struct pccbb_softc *)); 100 101 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 102 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 103 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 104 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 105 106 STATIC int cb_reset __P((struct pccbb_softc *)); 107 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 108 STATIC int cbbprint __P((void *, const char *)); 109 110 static int cb_chipset __P((u_int32_t, int *)); 111 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 112 struct pcmciabus_attach_args *)); 113 #if 0 114 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 115 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 116 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 117 #endif 118 119 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 120 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 121 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 122 #if !rbus 123 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 124 u_int32_t)); 125 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 126 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 127 u_int32_t)); 128 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 129 #endif /* !rbus */ 130 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 131 int level, int (*ih) (void *), void *sc)); 132 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 133 134 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 135 int level, int (*ih) (void *), void *sc)); 136 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 137 138 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 139 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 140 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 141 int)); 142 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 143 cardbusreg_t)); 144 static void pccbb_chipinit __P((struct pccbb_softc *)); 145 146 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 147 struct pcmcia_mem_handle *)); 148 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 149 struct pcmcia_mem_handle *)); 150 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 151 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 152 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 153 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 154 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 155 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 156 struct pcmcia_io_handle *)); 157 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 158 bus_size_t, struct pcmcia_io_handle *, int *)); 159 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 160 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 161 struct pcmcia_function *, int, int (*)(void *), void *)); 162 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 163 void *)); 164 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 165 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 166 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 167 168 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 169 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 170 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 171 static void pccbb_powerhook __P((int, void *)); 172 173 /* bus-space allocation and deallocation functions */ 174 #if rbus 175 176 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 177 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 178 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 179 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 180 bus_space_handle_t, bus_size_t)); 181 182 #endif /* rbus */ 183 184 #if rbus 185 186 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 187 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 188 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 189 bus_space_handle_t, bus_size_t)); 190 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 191 bus_size_t, bus_space_handle_t, int)); 192 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 193 bus_space_handle_t, bus_size_t)); 194 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 195 bus_space_tag_t)); 196 void pccbb_winlist_show(struct pccbb_win_chain *); 197 198 #endif /* rbus */ 199 200 /* for config_defer */ 201 static void pccbb_pci_callback __P((struct device *)); 202 203 #if defined SHOW_REGS 204 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 205 bus_space_tag_t memt, bus_space_handle_t memh)); 206 #endif 207 208 struct cfattach cbb_pci_ca = { 209 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 210 }; 211 212 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 213 pccbb_pcmcia_mem_alloc, 214 pccbb_pcmcia_mem_free, 215 pccbb_pcmcia_mem_map, 216 pccbb_pcmcia_mem_unmap, 217 pccbb_pcmcia_io_alloc, 218 pccbb_pcmcia_io_free, 219 pccbb_pcmcia_io_map, 220 pccbb_pcmcia_io_unmap, 221 pccbb_pcmcia_intr_establish, 222 pccbb_pcmcia_intr_disestablish, 223 pccbb_pcmcia_socket_enable, 224 pccbb_pcmcia_socket_disable, 225 pccbb_pcmcia_card_detect 226 }; 227 228 #if rbus 229 static struct cardbus_functions pccbb_funcs = { 230 pccbb_rbus_cb_space_alloc, 231 pccbb_rbus_cb_space_free, 232 pccbb_cb_intr_establish, 233 pccbb_cb_intr_disestablish, 234 pccbb_ctrl, 235 pccbb_power, 236 pccbb_make_tag, 237 pccbb_free_tag, 238 pccbb_conf_read, 239 pccbb_conf_write, 240 }; 241 #else 242 static struct cardbus_functions pccbb_funcs = { 243 pccbb_ctrl, 244 pccbb_power, 245 pccbb_mem_open, 246 pccbb_mem_close, 247 pccbb_io_open, 248 pccbb_io_close, 249 pccbb_cb_intr_establish, 250 pccbb_cb_intr_disestablish, 251 pccbb_make_tag, 252 pccbb_conf_read, 253 pccbb_conf_write, 254 }; 255 #endif 256 257 int 258 pcicbbmatch(parent, match, aux) 259 struct device *parent; 260 struct cfdata *match; 261 void *aux; 262 { 263 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 264 265 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 266 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 267 PCI_INTERFACE(pa->pa_class) == 0) { 268 return 1; 269 } 270 271 return 0; 272 } 273 274 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 275 | ((prod) << PCI_PRODUCT_SHIFT)) 276 277 struct yenta_chipinfo { 278 pcireg_t yc_id; /* vendor tag | product tag */ 279 int yc_chiptype; 280 int yc_flags; 281 } yc_chipsets[] = { 282 /* Texas Instruments chips */ 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 294 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 308 /* Ricoh chips */ 309 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 310 PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 312 PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 314 PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 316 PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 318 PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 320 PCCBB_PCMCIA_MEM_32}, 321 322 /* Toshiba products */ 323 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 324 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 326 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 328 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 330 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 331 332 /* Cirrus Logic products */ 333 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 334 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 336 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 337 338 /* sentinel, or Generic chip */ 339 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 340 }; 341 342 static int 343 cb_chipset(pci_id, flagp) 344 u_int32_t pci_id; 345 int *flagp; 346 { 347 struct yenta_chipinfo *yc; 348 349 /* Loop over except the last default entry. */ 350 for (yc = yc_chipsets; yc < yc_chipsets + 351 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 352 if (pci_id == yc->yc_id) 353 break; 354 355 if (flagp != NULL) 356 *flagp = yc->yc_flags; 357 358 return (yc->yc_chiptype); 359 } 360 361 static void 362 pccbb_shutdown(void *arg) 363 { 364 struct pccbb_softc *sc = arg; 365 pcireg_t command; 366 367 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 368 369 /* 370 * turn off power 371 * 372 * XXX - do not turn off power if chipset is TI 113X because 373 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 374 */ 375 if (sc->sc_chipset != CB_TI113X) { 376 pccbb_power((cardbus_chipset_tag_t)sc, 377 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 378 } 379 380 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 381 0); 382 383 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 384 385 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 386 PCI_COMMAND_MASTER_ENABLE); 387 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 388 389 } 390 391 void 392 pccbbattach(parent, self, aux) 393 struct device *parent; 394 struct device *self; 395 void *aux; 396 { 397 struct pccbb_softc *sc = (void *)self; 398 struct pci_attach_args *pa = aux; 399 pci_chipset_tag_t pc = pa->pa_pc; 400 pcireg_t busreg, reg, sock_base; 401 bus_addr_t sockbase; 402 char devinfo[256]; 403 int flags; 404 405 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 406 407 pci_devinfo(pa->pa_id, 0, 0, devinfo); 408 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 409 #ifdef CBB_DEBUG 410 printf(" (chipflags %x)", flags); 411 #endif 412 printf("\n"); 413 414 TAILQ_INIT(&sc->sc_memwindow); 415 TAILQ_INIT(&sc->sc_iowindow); 416 417 #if rbus 418 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 419 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 420 #endif /* rbus */ 421 422 sc->sc_base_memh = 0; 423 424 /* 425 * MAP socket registers and ExCA registers on memory-space 426 * When no valid address is set on socket base registers (on pci 427 * config space), get it not polite way. 428 */ 429 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 430 431 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 432 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 433 /* The address must be valid. */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 435 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 436 printf("%s: can't map socket base address 0x%x\n", 437 sc->sc_dev.dv_xname, sock_base); 438 /* 439 * I think it's funny: socket base registers must be 440 * mapped on memory space, but ... 441 */ 442 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 443 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 444 NULL)) { 445 printf("%s: can't map socket base address" 446 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 447 sockbase); 448 /* give up... allocate reg space via rbus. */ 449 sc->sc_base_memh = 0; 450 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 451 } 452 } else { 453 DPRINTF(("%s: socket base address 0x%lx\n", 454 sc->sc_dev.dv_xname, sockbase)); 455 } 456 } 457 458 sc->sc_mem_start = 0; /* XXX */ 459 sc->sc_mem_end = 0xffffffff; /* XXX */ 460 461 /* 462 * When interrupt isn't routed correctly, give up probing cbb and do 463 * not kill pcic-compatible port. 464 */ 465 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 466 printf("%s: NOT USED because of unconfigured interrupt\n", 467 sc->sc_dev.dv_xname); 468 return; 469 } 470 471 /* 472 * When bus number isn't set correctly, give up using 32-bit CardBus 473 * mode. 474 */ 475 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 476 #if notyet 477 if (((busreg >> 8) & 0xff) == 0) { 478 printf("%s: CardBus support disabled because of unconfigured bus number\n", 479 sc->sc_dev.dv_xname); 480 flags |= PCCBB_PCMCIA_16BITONLY; 481 } 482 #endif 483 484 /* pccbb_machdep.c end */ 485 486 #if defined CBB_DEBUG 487 { 488 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 489 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 490 intrname[pa->pa_intrpin], pa->pa_intrline); 491 } 492 #endif 493 494 /* setup softc */ 495 sc->sc_pc = pc; 496 sc->sc_iot = pa->pa_iot; 497 sc->sc_memt = pa->pa_memt; 498 sc->sc_dmat = pa->pa_dmat; 499 sc->sc_tag = pa->pa_tag; 500 sc->sc_function = pa->pa_function; 501 502 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 503 504 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 505 506 shutdownhook_establish(pccbb_shutdown, sc); 507 508 /* Disable legacy register mapping. */ 509 switch (sc->sc_chipset) { 510 case CB_RX5C46X: /* fallthrough */ 511 #if 0 512 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 513 case CB_RX5C47X: 514 #endif 515 /* 516 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 517 * cannot be disabled by substituting 0 into PCI_LEGACY 518 * register. Ricoh CardBus bridges have special bits on Bridge 519 * control reg (addr 0x3e on PCI config space). 520 */ 521 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 522 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 523 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 524 break; 525 526 default: 527 /* XXX I don't know proper way to kill legacy I/O. */ 528 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 529 break; 530 } 531 532 config_defer(self, pccbb_pci_callback); 533 } 534 535 536 537 538 /* 539 * static void pccbb_pci_callback(struct device *self) 540 * 541 * The actual attach routine: get memory space for YENTA register 542 * space, setup YENTA register and route interrupt. 543 * 544 * This function should be deferred because this device may obtain 545 * memory space dynamically. This function must avoid obtaining 546 * memory area which has already kept for another device. 547 */ 548 static void 549 pccbb_pci_callback(self) 550 struct device *self; 551 { 552 struct pccbb_softc *sc = (void *)self; 553 pci_chipset_tag_t pc = sc->sc_pc; 554 bus_space_tag_t base_memt; 555 bus_space_handle_t base_memh; 556 u_int32_t maskreg; 557 pci_intr_handle_t ih; 558 const char *intrstr = NULL; 559 bus_addr_t sockbase; 560 struct cbslot_attach_args cba; 561 struct pcmciabus_attach_args paa; 562 struct cardslot_attach_args caa; 563 struct cardslot_softc *csc; 564 565 if (0 == sc->sc_base_memh) { 566 /* The socket registers aren't mapped correctly. */ 567 #if rbus 568 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 569 (sc->sc_chipset == CB_RX5C47X 570 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 571 0, &sockbase, &sc->sc_base_memh)) { 572 return; 573 } 574 sc->sc_base_memt = sc->sc_memt; 575 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 576 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 577 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 578 PCI_SOCKBASE))); 579 #else 580 sc->sc_base_memt = sc->sc_memt; 581 #if !defined CBB_PCI_BASE 582 #define CBB_PCI_BASE 0x20000000 583 #endif 584 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 585 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 586 /* cannot allocate memory space */ 587 return; 588 } 589 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 590 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 591 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 592 sc->sc_tag, PCI_SOCKBASE))); 593 #endif 594 } 595 596 /* bus bridge initialization */ 597 pccbb_chipinit(sc); 598 599 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 600 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 601 602 /* CSC Interrupt: Card detect interrupt on */ 603 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 604 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 605 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 606 /* reset interrupt */ 607 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 608 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 609 610 /* clear data structure for child device interrupt handlers */ 611 sc->sc_pil = NULL; 612 sc->sc_pil_intr_enable = 1; 613 614 /* Map and establish the interrupt. */ 615 if (pci_intr_map(&sc->sc_pa, &ih)) { 616 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 617 return; 618 } 619 intrstr = pci_intr_string(pc, ih); 620 621 /* 622 * XXX pccbbintr should be called under the priority lower 623 * than any other hard interrputs. 624 */ 625 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 626 627 if (sc->sc_ih == NULL) { 628 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 629 if (intrstr != NULL) { 630 printf(" at %s", intrstr); 631 } 632 printf("\n"); 633 return; 634 } 635 636 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 637 powerhook_establish(pccbb_powerhook, sc); 638 639 { 640 u_int32_t sockstat = 641 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 642 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 643 sc->sc_flags |= CBB_CARDEXIST; 644 } 645 } 646 647 /* 648 * attach cardbus 649 */ 650 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 651 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 652 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 653 654 /* initialize cbslot_attach */ 655 cba.cba_busname = "cardbus"; 656 cba.cba_iot = sc->sc_iot; 657 cba.cba_memt = sc->sc_memt; 658 cba.cba_dmat = sc->sc_dmat; 659 cba.cba_bus = (busreg >> 8) & 0x0ff; 660 cba.cba_cc = (void *)sc; 661 cba.cba_cf = &pccbb_funcs; 662 cba.cba_intrline = sc->sc_pa.pa_intrline; 663 664 #if rbus 665 cba.cba_rbus_iot = sc->sc_rbus_iot; 666 cba.cba_rbus_memt = sc->sc_rbus_memt; 667 #endif 668 669 cba.cba_cacheline = PCI_CACHELINE(bhlc); 670 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 671 672 if (bootverbose) { 673 printf("%s: cacheline 0x%x lattimer 0x%x\n", 674 sc->sc_dev.dv_xname, cba.cba_cacheline, 675 cba.cba_lattimer); 676 printf("%s: bhlc 0x%x lscp 0x%x\n", 677 sc->sc_dev.dv_xname, bhlc, busreg); 678 } 679 #if defined SHOW_REGS 680 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 681 sc->sc_base_memh); 682 #endif 683 } 684 685 pccbb_pcmcia_attach_setup(sc, &paa); 686 caa.caa_cb_attach = NULL; 687 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 688 caa.caa_cb_attach = &cba; 689 } 690 caa.caa_16_attach = &paa; 691 caa.caa_ph = &sc->sc_pcmcia_h; 692 693 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 694 DPRINTF(("pccbbattach: found cardslot\n")); 695 sc->sc_csc = csc; 696 } 697 698 return; 699 } 700 701 702 703 704 705 /* 706 * static void pccbb_chipinit(struct pccbb_softc *sc) 707 * 708 * This function initialize YENTA chip registers listed below: 709 * 1) PCI command reg, 710 * 2) PCI and CardBus latency timer, 711 * 3) route PCI interrupt, 712 * 4) close all memory and io windows. 713 */ 714 static void 715 pccbb_chipinit(sc) 716 struct pccbb_softc *sc; 717 { 718 pci_chipset_tag_t pc = sc->sc_pc; 719 pcitag_t tag = sc->sc_tag; 720 pcireg_t reg; 721 722 /* 723 * Set PCI command reg. 724 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 725 */ 726 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 727 /* I believe it is harmless. */ 728 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 729 PCI_COMMAND_MASTER_ENABLE); 730 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 731 732 /* 733 * Set CardBus latency timer. 734 */ 735 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 736 if (PCI_CB_LATENCY(reg) < 0x20) { 737 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 738 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 739 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 740 } 741 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 742 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 743 744 /* 745 * Set PCI latency timer. 746 */ 747 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 748 if (PCI_LATTIMER(reg) < 0x10) { 749 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 750 reg |= (0x10 << PCI_LATTIMER_SHIFT); 751 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 752 } 753 DPRINTF(("PCI latency timer 0x%x (%x)\n", 754 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 755 756 757 /* Route functional interrupts to PCI. */ 758 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 759 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 760 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 761 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 762 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 763 764 switch (sc->sc_chipset) { 765 case CB_TI113X: 766 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 767 /* This bit is shared, but may read as 0 on some chips, so set 768 it explicitly on both functions. */ 769 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 770 /* CSC intr enable */ 771 reg |= PCI113X_CBCTRL_PCI_CSC; 772 /* functional intr prohibit | prohibit ISA routing */ 773 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 774 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 775 break; 776 777 case CB_TI12XX: 778 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 779 reg |= PCI12XX_SYSCTRL_VCCPROT; 780 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 781 break; 782 783 case CB_TOPIC95B: 784 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 785 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 786 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 787 788 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 789 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 790 sc->sc_dev.dv_xname, reg)); 791 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 792 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 793 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 794 DPRINTF(("0x%x\n", reg)); 795 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 796 break; 797 } 798 799 /* Close all memory and I/O windows. */ 800 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 801 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 802 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 803 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 804 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 805 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 806 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 807 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 808 809 /* reset 16-bit pcmcia bus */ 810 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 811 0x800 + PCIC_INTR, 812 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 813 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 814 815 /* turn of power */ 816 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 817 } 818 819 820 821 822 /* 823 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 824 * struct pcmciabus_attach_args *paa) 825 * 826 * This function attaches 16-bit PCcard bus. 827 */ 828 STATIC void 829 pccbb_pcmcia_attach_setup(sc, paa) 830 struct pccbb_softc *sc; 831 struct pcmciabus_attach_args *paa; 832 { 833 struct pcic_handle *ph = &sc->sc_pcmcia_h; 834 #if rbus 835 rbus_tag_t rb; 836 #endif 837 838 /* initialize pcmcia part in pccbb_softc */ 839 ph->ph_parent = (struct device *)sc; 840 ph->sock = sc->sc_function; 841 ph->flags = 0; 842 ph->shutdown = 0; 843 ph->ih_irq = sc->sc_pa.pa_intrline; 844 ph->ph_bus_t = sc->sc_base_memt; 845 ph->ph_bus_h = sc->sc_base_memh; 846 ph->ph_read = pccbb_pcmcia_read; 847 ph->ph_write = pccbb_pcmcia_write; 848 sc->sc_pct = &pccbb_pcmcia_funcs; 849 850 /* 851 * We need to do a few things here: 852 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 853 * setting the IRQ numbers to 0. 854 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 855 * routing of CSC interrupts (e.g. card removal) to PCI while in 856 * PCMCIA mode. We just leave this set all the time. 857 * 3) Enable card insertion/removal interrupts in case the chip also 858 * needs that while in PCMCIA mode. 859 * 4) Clear any pending CSC interrupt. 860 */ 861 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 862 if (sc->sc_chipset == CB_TI113X) { 863 Pcic_write(ph, PCIC_CSC_INTR, 0); 864 } else { 865 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 866 Pcic_read(ph, PCIC_CSC); 867 } 868 869 /* initialize pcmcia bus attachment */ 870 paa->paa_busname = "pcmcia"; 871 paa->pct = sc->sc_pct; 872 paa->pch = ph; 873 paa->iobase = 0; /* I don't use them */ 874 paa->iosize = 0; 875 #if rbus 876 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 877 paa->iobase = rb->rb_start + rb->rb_offset; 878 paa->iosize = rb->rb_end - rb->rb_start; 879 #endif 880 881 return; 882 } 883 884 #if 0 885 STATIC void 886 pccbb_pcmcia_attach_card(ph) 887 struct pcic_handle *ph; 888 { 889 if (ph->flags & PCIC_FLAG_CARDP) { 890 panic("pccbb_pcmcia_attach_card: already attached"); 891 } 892 893 /* call the MI attach function */ 894 pcmcia_card_attach(ph->pcmcia); 895 896 ph->flags |= PCIC_FLAG_CARDP; 897 } 898 899 STATIC void 900 pccbb_pcmcia_detach_card(ph, flags) 901 struct pcic_handle *ph; 902 int flags; 903 { 904 if (!(ph->flags & PCIC_FLAG_CARDP)) { 905 panic("pccbb_pcmcia_detach_card: already detached"); 906 } 907 908 ph->flags &= ~PCIC_FLAG_CARDP; 909 910 /* call the MI detach function */ 911 pcmcia_card_detach(ph->pcmcia, flags); 912 } 913 #endif 914 915 /* 916 * int pccbbintr(arg) 917 * void *arg; 918 * This routine handles the interrupt from Yenta PCI-CardBus bridge 919 * itself. 920 */ 921 int 922 pccbbintr(arg) 923 void *arg; 924 { 925 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 926 u_int32_t sockevent, sockstate; 927 bus_space_tag_t memt = sc->sc_base_memt; 928 bus_space_handle_t memh = sc->sc_base_memh; 929 struct pcic_handle *ph = &sc->sc_pcmcia_h; 930 931 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 932 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 933 Pcic_read(ph, PCIC_CSC); 934 935 if (sockevent == 0) { 936 /* This intr is not for me: it may be for my child devices. */ 937 if (sc->sc_pil_intr_enable) { 938 return pccbbintr_function(sc); 939 } else { 940 return 0; 941 } 942 } 943 944 if (sockevent & CB_SOCKET_EVENT_CD) { 945 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 946 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 947 /* A card should be removed. */ 948 if (sc->sc_flags & CBB_CARDEXIST) { 949 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 950 sockevent)); 951 DPRINTF((" card removed, 0x%08x\n", sockstate)); 952 sc->sc_flags &= ~CBB_CARDEXIST; 953 if (sc->sc_csc->sc_status & 954 CARDSLOT_STATUS_CARD_16) { 955 #if 0 956 struct pcic_handle *ph = 957 &sc->sc_pcmcia_h; 958 959 pcmcia_card_deactivate(ph->pcmcia); 960 pccbb_pcmcia_socket_disable(ph); 961 pccbb_pcmcia_detach_card(ph, 962 DETACH_FORCE); 963 #endif 964 cardslot_event_throw(sc->sc_csc, 965 CARDSLOT_EVENT_REMOVAL_16); 966 } else if (sc->sc_csc->sc_status & 967 CARDSLOT_STATUS_CARD_CB) { 968 /* Cardbus intr removed */ 969 cardslot_event_throw(sc->sc_csc, 970 CARDSLOT_EVENT_REMOVAL_CB); 971 } 972 } 973 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 974 /* 975 * The pccbbintr may called from powerdown hook when 976 * the system resumed, to detect the card 977 * insertion/removal during suspension. 978 */ 979 (sc->sc_flags & CBB_CARDEXIST) == 0) { 980 if (sc->sc_flags & CBB_INSERTING) { 981 callout_stop(&sc->sc_insert_ch); 982 } 983 callout_reset(&sc->sc_insert_ch, hz / 10, 984 pci113x_insert, sc); 985 sc->sc_flags |= CBB_INSERTING; 986 } 987 } 988 989 return (1); 990 } 991 992 /* 993 * static int pccbbintr_function(struct pccbb_softc *sc) 994 * 995 * This function calls each interrupt handler registered at the 996 * bridge. The interrupt handlers are called in registered order. 997 */ 998 static int 999 pccbbintr_function(sc) 1000 struct pccbb_softc *sc; 1001 { 1002 int retval = 0, val; 1003 struct pccbb_intrhand_list *pil; 1004 int s, splchanged; 1005 1006 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1007 /* 1008 * XXX priority change. gross. I use if-else 1009 * sentense instead of switch-case sentense because of 1010 * avoiding duplicate case value error. More than one 1011 * IPL_XXX use same value. It depends on 1012 * implimentation. 1013 */ 1014 splchanged = 1; 1015 if (pil->pil_level == IPL_SERIAL) { 1016 s = splserial(); 1017 } else if (pil->pil_level == IPL_HIGH) { 1018 s = splhigh(); 1019 } else if (pil->pil_level == IPL_CLOCK) { 1020 s = splclock(); 1021 } else if (pil->pil_level == IPL_AUDIO) { 1022 s = splaudio(); 1023 } else if (pil->pil_level == IPL_IMP) { 1024 s = splimp(); 1025 } else if (pil->pil_level == IPL_TTY) { 1026 s = spltty(); 1027 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1028 s = splsoftserial(); 1029 } else if (pil->pil_level == IPL_NET) { 1030 s = splnet(); 1031 } else { 1032 splchanged = 0; 1033 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1034 } 1035 1036 val = (*pil->pil_func)(pil->pil_arg); 1037 1038 if (splchanged != 0) { 1039 splx(s); 1040 } 1041 1042 retval = retval == 1 ? 1 : 1043 retval == 0 ? val : val != 0 ? val : retval; 1044 } 1045 1046 return retval; 1047 } 1048 1049 static void 1050 pci113x_insert(arg) 1051 void *arg; 1052 { 1053 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1054 u_int32_t sockevent, sockstate; 1055 1056 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1057 CB_SOCKET_EVENT); 1058 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1059 CB_SOCKET_STAT); 1060 1061 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1062 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1063 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1064 sc->sc_flags |= CBB_CARDEXIST; 1065 /* call pccard interrupt handler here */ 1066 if (sockstate & CB_SOCKET_STAT_16BIT) { 1067 /* 16-bit card found */ 1068 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1069 cardslot_event_throw(sc->sc_csc, 1070 CARDSLOT_EVENT_INSERTION_16); 1071 } else if (sockstate & CB_SOCKET_STAT_CB) { 1072 /* cardbus card found */ 1073 /* cardbus_attach_card(sc->sc_csc); */ 1074 cardslot_event_throw(sc->sc_csc, 1075 CARDSLOT_EVENT_INSERTION_CB); 1076 } else { 1077 /* who are you? */ 1078 } 1079 } else { 1080 callout_reset(&sc->sc_insert_ch, hz / 10, 1081 pci113x_insert, sc); 1082 } 1083 } 1084 1085 #define PCCBB_PCMCIA_OFFSET 0x800 1086 static u_int8_t 1087 pccbb_pcmcia_read(ph, reg) 1088 struct pcic_handle *ph; 1089 int reg; 1090 { 1091 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1092 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1093 1094 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1095 PCCBB_PCMCIA_OFFSET + reg); 1096 } 1097 1098 static void 1099 pccbb_pcmcia_write(ph, reg, val) 1100 struct pcic_handle *ph; 1101 int reg; 1102 u_int8_t val; 1103 { 1104 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1105 val); 1106 1107 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1108 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1109 } 1110 1111 /* 1112 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1113 */ 1114 STATIC int 1115 pccbb_ctrl(ct, command) 1116 cardbus_chipset_tag_t ct; 1117 int command; 1118 { 1119 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1120 1121 switch (command) { 1122 case CARDBUS_CD: 1123 if (2 == pccbb_detect_card(sc)) { 1124 int retval = 0; 1125 int status = cb_detect_voltage(sc); 1126 if (PCCARD_VCC_5V & status) { 1127 retval |= CARDBUS_5V_CARD; 1128 } 1129 if (PCCARD_VCC_3V & status) { 1130 retval |= CARDBUS_3V_CARD; 1131 } 1132 if (PCCARD_VCC_XV & status) { 1133 retval |= CARDBUS_XV_CARD; 1134 } 1135 if (PCCARD_VCC_YV & status) { 1136 retval |= CARDBUS_YV_CARD; 1137 } 1138 return retval; 1139 } else { 1140 return 0; 1141 } 1142 break; 1143 case CARDBUS_RESET: 1144 return cb_reset(sc); 1145 break; 1146 case CARDBUS_IO_ENABLE: /* fallthrough */ 1147 case CARDBUS_IO_DISABLE: /* fallthrough */ 1148 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1149 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1150 case CARDBUS_BM_ENABLE: /* fallthrough */ 1151 case CARDBUS_BM_DISABLE: /* fallthrough */ 1152 return pccbb_cardenable(sc, command); 1153 break; 1154 } 1155 1156 return 0; 1157 } 1158 1159 /* 1160 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1161 * This function returns true when it succeeds and returns false when 1162 * it fails. 1163 */ 1164 STATIC int 1165 pccbb_power(ct, command) 1166 cardbus_chipset_tag_t ct; 1167 int command; 1168 { 1169 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1170 1171 u_int32_t status, sock_ctrl; 1172 bus_space_tag_t memt = sc->sc_base_memt; 1173 bus_space_handle_t memh = sc->sc_base_memh; 1174 1175 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1176 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1177 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1178 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1179 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1180 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1181 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1182 "UNKNOWN", 1183 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1184 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1185 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1186 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1187 "UNKNOWN", command)); 1188 1189 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1190 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1191 1192 switch (command & CARDBUS_VCCMASK) { 1193 case CARDBUS_VCC_UC: 1194 break; 1195 case CARDBUS_VCC_5V: 1196 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1197 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1198 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1199 } else { 1200 printf("%s: BAD voltage request: no 5 V card\n", 1201 sc->sc_dev.dv_xname); 1202 } 1203 break; 1204 case CARDBUS_VCC_3V: 1205 if (CB_SOCKET_STAT_3VCARD & status) { 1206 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1207 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1208 } else { 1209 printf("%s: BAD voltage request: no 3.3 V card\n", 1210 sc->sc_dev.dv_xname); 1211 } 1212 break; 1213 case CARDBUS_VCC_0V: 1214 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1215 break; 1216 default: 1217 return 0; /* power NEVER changed */ 1218 break; 1219 } 1220 1221 switch (command & CARDBUS_VPPMASK) { 1222 case CARDBUS_VPP_UC: 1223 break; 1224 case CARDBUS_VPP_0V: 1225 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1226 break; 1227 case CARDBUS_VPP_VCC: 1228 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1229 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1230 break; 1231 case CARDBUS_VPP_12V: 1232 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1233 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1234 break; 1235 } 1236 1237 #if 0 1238 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1239 #endif 1240 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1241 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1242 1243 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1244 printf 1245 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1246 sc->sc_dev.dv_xname, sock_ctrl, status); 1247 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1248 (command & CARDBUS_VCCMASK) == 1249 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1250 CARDBUS_VCCMASK) == 1251 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1252 CARDBUS_VCCMASK) == 1253 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1254 CARDBUS_VCCMASK) == 1255 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1256 CARDBUS_VCCMASK) == 1257 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1258 CARDBUS_VCCMASK) == 1259 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1260 (command & CARDBUS_VPPMASK) == 1261 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1262 CARDBUS_VPPMASK) == 1263 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1264 CARDBUS_VPPMASK) == 1265 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1266 CARDBUS_VPPMASK) == 1267 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1268 #if 0 1269 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1270 u_int32_t force = 1271 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1272 /* Reset Bad Vcc request */ 1273 force &= ~CB_SOCKET_FORCE_BADVCC; 1274 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1275 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1276 CB_SOCKET_STAT)); 1277 return 1; 1278 } 1279 #endif 1280 return 0; 1281 } 1282 1283 /* 1284 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1285 * time is 20 ms, some PC-Card bridge requires longer duration. 1286 */ 1287 delay(300 * 1000); 1288 1289 return 1; /* power changed correctly */ 1290 } 1291 1292 #if defined CB_PCMCIA_POLL 1293 struct cb_poll_str { 1294 void *arg; 1295 int (*func) __P((void *)); 1296 int level; 1297 pccard_chipset_tag_t ct; 1298 int count; 1299 struct callout poll_ch; 1300 }; 1301 1302 static struct cb_poll_str cb_poll[10]; 1303 static int cb_poll_n = 0; 1304 1305 static void cb_pcmcia_poll __P((void *arg)); 1306 1307 static void 1308 cb_pcmcia_poll(arg) 1309 void *arg; 1310 { 1311 struct cb_poll_str *poll = arg; 1312 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1313 struct pccbb_softc *sc = psc->cpc_parent; 1314 int s; 1315 u_int32_t spsr; /* socket present-state reg */ 1316 1317 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1318 switch (poll->level) { 1319 case IPL_NET: 1320 s = splnet(); 1321 break; 1322 case IPL_BIO: 1323 s = splbio(); 1324 break; 1325 case IPL_TTY: /* fallthrough */ 1326 default: 1327 s = spltty(); 1328 break; 1329 } 1330 1331 spsr = 1332 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1333 CB_SOCKET_STAT); 1334 1335 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1336 if (!(spsr & 0x40)) { /* CINT low */ 1337 #else 1338 if (1) { 1339 #endif 1340 if ((*poll->func) (poll->arg) == 1) { 1341 ++poll->count; 1342 printf("intr: reported from poller, 0x%x\n", spsr); 1343 #if defined LEVEL2 1344 } else { 1345 printf("intr: miss! 0x%x\n", spsr); 1346 #endif 1347 } 1348 } 1349 splx(s); 1350 } 1351 #endif /* defined CB_PCMCIA_POLL */ 1352 1353 /* 1354 * static int pccbb_detect_card(struct pccbb_softc *sc) 1355 * return value: 0 if no card exists. 1356 * 1 if 16-bit card exists. 1357 * 2 if cardbus card exists. 1358 */ 1359 static int 1360 pccbb_detect_card(sc) 1361 struct pccbb_softc *sc; 1362 { 1363 bus_space_handle_t base_memh = sc->sc_base_memh; 1364 bus_space_tag_t base_memt = sc->sc_base_memt; 1365 u_int32_t sockstat = 1366 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1367 int retval = 0; 1368 1369 /* CD1 and CD2 asserted */ 1370 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1371 /* card must be present */ 1372 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1373 /* NOTACARD DEASSERTED */ 1374 if (CB_SOCKET_STAT_CB & sockstat) { 1375 /* CardBus mode */ 1376 retval = 2; 1377 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1378 /* 16-bit mode */ 1379 retval = 1; 1380 } 1381 } 1382 } 1383 return retval; 1384 } 1385 1386 /* 1387 * STATIC int cb_reset(struct pccbb_softc *sc) 1388 * This function resets CardBus card. 1389 */ 1390 STATIC int 1391 cb_reset(sc) 1392 struct pccbb_softc *sc; 1393 { 1394 /* 1395 * Reset Assert at least 20 ms 1396 * Some machines request longer duration. 1397 */ 1398 int reset_duration = 1399 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1400 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1401 1402 /* Reset bit Assert (bit 6 at 0x3E) */ 1403 bcr |= CB_BCR_RESET_ENABLE; 1404 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1405 delay(reset_duration); 1406 1407 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1408 /* Reset bit Deassert (bit 6 at 0x3E) */ 1409 bcr &= ~CB_BCR_RESET_ENABLE; 1410 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1411 delay(reset_duration); 1412 } 1413 /* No card found on the slot. Keep Reset. */ 1414 return 1; 1415 } 1416 1417 /* 1418 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1419 * This function detect card Voltage. 1420 */ 1421 STATIC int 1422 cb_detect_voltage(sc) 1423 struct pccbb_softc *sc; 1424 { 1425 u_int32_t psr; /* socket present-state reg */ 1426 bus_space_tag_t iot = sc->sc_base_memt; 1427 bus_space_handle_t ioh = sc->sc_base_memh; 1428 int vol = PCCARD_VCC_UKN; /* set 0 */ 1429 1430 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1431 1432 if (0x400u & psr) { 1433 vol |= PCCARD_VCC_5V; 1434 } 1435 if (0x800u & psr) { 1436 vol |= PCCARD_VCC_3V; 1437 } 1438 1439 return vol; 1440 } 1441 1442 STATIC int 1443 cbbprint(aux, pcic) 1444 void *aux; 1445 const char *pcic; 1446 { 1447 /* 1448 struct cbslot_attach_args *cba = aux; 1449 1450 if (cba->cba_slot >= 0) { 1451 printf(" slot %d", cba->cba_slot); 1452 } 1453 */ 1454 return UNCONF; 1455 } 1456 1457 /* 1458 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1459 * This function enables and disables the card 1460 */ 1461 STATIC int 1462 pccbb_cardenable(sc, function) 1463 struct pccbb_softc *sc; 1464 int function; 1465 { 1466 u_int32_t command = 1467 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1468 1469 DPRINTF(("pccbb_cardenable:")); 1470 switch (function) { 1471 case CARDBUS_IO_ENABLE: 1472 command |= PCI_COMMAND_IO_ENABLE; 1473 break; 1474 case CARDBUS_IO_DISABLE: 1475 command &= ~PCI_COMMAND_IO_ENABLE; 1476 break; 1477 case CARDBUS_MEM_ENABLE: 1478 command |= PCI_COMMAND_MEM_ENABLE; 1479 break; 1480 case CARDBUS_MEM_DISABLE: 1481 command &= ~PCI_COMMAND_MEM_ENABLE; 1482 break; 1483 case CARDBUS_BM_ENABLE: 1484 command |= PCI_COMMAND_MASTER_ENABLE; 1485 break; 1486 case CARDBUS_BM_DISABLE: 1487 command &= ~PCI_COMMAND_MASTER_ENABLE; 1488 break; 1489 default: 1490 return 0; 1491 } 1492 1493 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1494 DPRINTF((" command reg 0x%x\n", command)); 1495 return 1; 1496 } 1497 1498 #if !rbus 1499 /* 1500 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1501 */ 1502 static int 1503 pccbb_io_open(ct, win, start, end) 1504 cardbus_chipset_tag_t ct; 1505 int win; 1506 u_int32_t start, end; 1507 { 1508 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1509 int basereg; 1510 int limitreg; 1511 1512 if ((win < 0) || (win > 2)) { 1513 #if defined DIAGNOSTIC 1514 printf("cardbus_io_open: window out of range %d\n", win); 1515 #endif 1516 return 0; 1517 } 1518 1519 basereg = win * 8 + 0x2c; 1520 limitreg = win * 8 + 0x30; 1521 1522 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1523 start, basereg, end, limitreg)); 1524 1525 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1526 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1527 return 1; 1528 } 1529 1530 /* 1531 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1532 */ 1533 static int 1534 pccbb_io_close(ct, win) 1535 cardbus_chipset_tag_t ct; 1536 int win; 1537 { 1538 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1539 int basereg; 1540 int limitreg; 1541 1542 if ((win < 0) || (win > 2)) { 1543 #if defined DIAGNOSTIC 1544 printf("cardbus_io_close: window out of range %d\n", win); 1545 #endif 1546 return 0; 1547 } 1548 1549 basereg = win * 8 + 0x2c; 1550 limitreg = win * 8 + 0x30; 1551 1552 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1553 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1554 return 1; 1555 } 1556 1557 /* 1558 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1559 */ 1560 static int 1561 pccbb_mem_open(ct, win, start, end) 1562 cardbus_chipset_tag_t ct; 1563 int win; 1564 u_int32_t start, end; 1565 { 1566 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1567 int basereg; 1568 int limitreg; 1569 1570 if ((win < 0) || (win > 2)) { 1571 #if defined DIAGNOSTIC 1572 printf("cardbus_mem_open: window out of range %d\n", win); 1573 #endif 1574 return 0; 1575 } 1576 1577 basereg = win * 8 + 0x1c; 1578 limitreg = win * 8 + 0x20; 1579 1580 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1581 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1582 return 1; 1583 } 1584 1585 /* 1586 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1587 */ 1588 static int 1589 pccbb_mem_close(ct, win) 1590 cardbus_chipset_tag_t ct; 1591 int win; 1592 { 1593 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1594 int basereg; 1595 int limitreg; 1596 1597 if ((win < 0) || (win > 2)) { 1598 #if defined DIAGNOSTIC 1599 printf("cardbus_mem_close: window out of range %d\n", win); 1600 #endif 1601 return 0; 1602 } 1603 1604 basereg = win * 8 + 0x1c; 1605 limitreg = win * 8 + 0x20; 1606 1607 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1608 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1609 return 1; 1610 } 1611 #endif 1612 1613 /* 1614 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1615 * int irq, 1616 * int level, 1617 * int (* func) __P((void *)), 1618 * void *arg) 1619 * 1620 * This function registers an interrupt handler at the bridge, in 1621 * order not to call the interrupt handlers of child devices when 1622 * a card-deletion interrupt occurs. 1623 * 1624 * The arguments irq and level are not used. 1625 */ 1626 static void * 1627 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1628 cardbus_chipset_tag_t ct; 1629 int irq, level; 1630 int (*func) __P((void *)); 1631 void *arg; 1632 { 1633 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1634 1635 return pccbb_intr_establish(sc, irq, level, func, arg); 1636 } 1637 1638 1639 /* 1640 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1641 * void *ih) 1642 * 1643 * This function removes an interrupt handler pointed by ih. 1644 */ 1645 static void 1646 pccbb_cb_intr_disestablish(ct, ih) 1647 cardbus_chipset_tag_t ct; 1648 void *ih; 1649 { 1650 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1651 1652 pccbb_intr_disestablish(sc, ih); 1653 } 1654 1655 1656 /* 1657 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1658 * int irq, 1659 * int level, 1660 * int (* func) __P((void *)), 1661 * void *arg) 1662 * 1663 * This function registers an interrupt handler at the bridge, in 1664 * order not to call the interrupt handlers of child devices when 1665 * a card-deletion interrupt occurs. 1666 * 1667 * The arguments irq is not used because pccbb selects intr vector. 1668 */ 1669 static void * 1670 pccbb_intr_establish(sc, irq, level, func, arg) 1671 struct pccbb_softc *sc; 1672 int irq, level; 1673 int (*func) __P((void *)); 1674 void *arg; 1675 { 1676 struct pccbb_intrhand_list *pil, *newpil; 1677 pcireg_t reg; 1678 1679 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1680 1681 if (sc->sc_pil == NULL) { 1682 /* initialize bridge intr routing */ 1683 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1684 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1685 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1686 1687 switch (sc->sc_chipset) { 1688 case CB_TI113X: 1689 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1690 /* functional intr enabled */ 1691 reg |= PCI113X_CBCTRL_PCI_INTR; 1692 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1693 break; 1694 default: 1695 break; 1696 } 1697 } 1698 1699 /* 1700 * Allocate a room for interrupt handler structure. 1701 */ 1702 if (NULL == (newpil = 1703 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1704 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1705 return NULL; 1706 } 1707 1708 newpil->pil_func = func; 1709 newpil->pil_arg = arg; 1710 newpil->pil_level = level; 1711 newpil->pil_next = NULL; 1712 1713 if (sc->sc_pil == NULL) { 1714 sc->sc_pil = newpil; 1715 } else { 1716 for (pil = sc->sc_pil; pil->pil_next != NULL; 1717 pil = pil->pil_next); 1718 pil->pil_next = newpil; 1719 } 1720 1721 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1722 1723 return newpil; 1724 } 1725 1726 /* 1727 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1728 * void *ih) 1729 * 1730 * This function removes an interrupt handler pointed by ih. 1731 */ 1732 static void 1733 pccbb_intr_disestablish(sc, ih) 1734 struct pccbb_softc *sc; 1735 void *ih; 1736 { 1737 struct pccbb_intrhand_list *pil, **pil_prev; 1738 pcireg_t reg; 1739 1740 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1741 1742 pil_prev = &sc->sc_pil; 1743 1744 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1745 if (pil == ih) { 1746 *pil_prev = pil->pil_next; 1747 free(pil, M_DEVBUF); 1748 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1749 break; 1750 } 1751 pil_prev = &pil->pil_next; 1752 } 1753 1754 if (sc->sc_pil == NULL) { 1755 /* No interrupt handlers */ 1756 1757 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1758 1759 /* stop routing PCI intr */ 1760 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1761 reg |= CB_BCR_INTR_IREQ_ENABLE; 1762 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1763 1764 switch (sc->sc_chipset) { 1765 case CB_TI113X: 1766 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1767 /* functional intr disabled */ 1768 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1769 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1770 break; 1771 default: 1772 break; 1773 } 1774 } 1775 } 1776 1777 #if defined SHOW_REGS 1778 static void 1779 cb_show_regs(pc, tag, memt, memh) 1780 pci_chipset_tag_t pc; 1781 pcitag_t tag; 1782 bus_space_tag_t memt; 1783 bus_space_handle_t memh; 1784 { 1785 int i; 1786 printf("PCI config regs:"); 1787 for (i = 0; i < 0x50; i += 4) { 1788 if (i % 16 == 0) { 1789 printf("\n 0x%02x:", i); 1790 } 1791 printf(" %08x", pci_conf_read(pc, tag, i)); 1792 } 1793 for (i = 0x80; i < 0xb0; i += 4) { 1794 if (i % 16 == 0) { 1795 printf("\n 0x%02x:", i); 1796 } 1797 printf(" %08x", pci_conf_read(pc, tag, i)); 1798 } 1799 1800 if (memh == 0) { 1801 printf("\n"); 1802 return; 1803 } 1804 1805 printf("\nsocket regs:"); 1806 for (i = 0; i <= 0x10; i += 0x04) { 1807 printf(" %08x", bus_space_read_4(memt, memh, i)); 1808 } 1809 printf("\nExCA regs:"); 1810 for (i = 0; i < 0x08; ++i) { 1811 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1812 } 1813 printf("\n"); 1814 return; 1815 } 1816 #endif 1817 1818 /* 1819 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1820 * int busno, int devno, int function) 1821 * This is the function to make a tag to access config space of 1822 * a CardBus Card. It works same as pci_conf_read. 1823 */ 1824 static cardbustag_t 1825 pccbb_make_tag(cc, busno, devno, function) 1826 cardbus_chipset_tag_t cc; 1827 int busno, devno, function; 1828 { 1829 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1830 1831 return pci_make_tag(sc->sc_pc, busno, devno, function); 1832 } 1833 1834 static void 1835 pccbb_free_tag(cc, tag) 1836 cardbus_chipset_tag_t cc; 1837 cardbustag_t tag; 1838 { 1839 } 1840 1841 /* 1842 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1843 * cardbustag_t tag, int offset) 1844 * This is the function to read the config space of a CardBus Card. 1845 * It works same as pci_conf_read. 1846 */ 1847 static cardbusreg_t 1848 pccbb_conf_read(cc, tag, offset) 1849 cardbus_chipset_tag_t cc; 1850 cardbustag_t tag; 1851 int offset; /* register offset */ 1852 { 1853 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1854 1855 return pci_conf_read(sc->sc_pc, tag, offset); 1856 } 1857 1858 /* 1859 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1860 * int offs, cardbusreg_t val) 1861 * This is the function to write the config space of a CardBus Card. 1862 * It works same as pci_conf_write. 1863 */ 1864 static void 1865 pccbb_conf_write(cc, tag, reg, val) 1866 cardbus_chipset_tag_t cc; 1867 cardbustag_t tag; 1868 int reg; /* register offset */ 1869 cardbusreg_t val; 1870 { 1871 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1872 1873 pci_conf_write(sc->sc_pc, tag, reg, val); 1874 } 1875 1876 #if 0 1877 STATIC int 1878 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1879 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1880 int speed, int flags, 1881 bus_space_handle_t * iohp) 1882 #endif 1883 /* 1884 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1885 * bus_addr_t start, bus_size_t size, 1886 * bus_size_t align, 1887 * struct pcmcia_io_handle *pcihp 1888 * 1889 * This function only allocates I/O region for pccard. This function 1890 * never maps the allocated region to pccard I/O area. 1891 * 1892 * XXX: The interface of this function is not very good, I believe. 1893 */ 1894 STATIC int 1895 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1896 pcmcia_chipset_handle_t pch; 1897 bus_addr_t start; /* start address */ 1898 bus_size_t size; 1899 bus_size_t align; 1900 struct pcmcia_io_handle *pcihp; 1901 { 1902 struct pcic_handle *ph = (struct pcic_handle *)pch; 1903 bus_addr_t ioaddr; 1904 int flags = 0; 1905 bus_space_tag_t iot; 1906 bus_space_handle_t ioh; 1907 #if rbus 1908 rbus_tag_t rb; 1909 #endif 1910 if (align == 0) { 1911 align = size; /* XXX: funny??? */ 1912 } 1913 1914 /* 1915 * Allocate some arbitrary I/O space. 1916 */ 1917 1918 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1919 1920 #if rbus 1921 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1922 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1923 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1924 return 1; 1925 } 1926 #else 1927 if (start) { 1928 ioaddr = start; 1929 if (bus_space_map(iot, start, size, 0, &ioh)) { 1930 return 1; 1931 } 1932 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1933 (u_long) ioaddr, (u_long) size)); 1934 } else { 1935 flags |= PCMCIA_IO_ALLOCATED; 1936 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1937 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1938 size, align, 0, 0, &ioaddr, &ioh)) { 1939 /* No room be able to be get. */ 1940 return 1; 1941 } 1942 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1943 (u_long) ioaddr, (u_long) size)); 1944 } 1945 #endif 1946 1947 pcihp->iot = iot; 1948 pcihp->ioh = ioh; 1949 pcihp->addr = ioaddr; 1950 pcihp->size = size; 1951 pcihp->flags = flags; 1952 1953 return 0; 1954 } 1955 1956 /* 1957 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1958 * struct pcmcia_io_handle *pcihp) 1959 * 1960 * This function only frees I/O region for pccard. 1961 * 1962 * XXX: The interface of this function is not very good, I believe. 1963 */ 1964 void 1965 pccbb_pcmcia_io_free(pch, pcihp) 1966 pcmcia_chipset_handle_t pch; 1967 struct pcmcia_io_handle *pcihp; 1968 { 1969 #if !rbus 1970 bus_space_tag_t iot = pcihp->iot; 1971 #endif 1972 bus_space_handle_t ioh = pcihp->ioh; 1973 bus_size_t size = pcihp->size; 1974 1975 #if rbus 1976 struct pccbb_softc *sc = 1977 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1978 rbus_tag_t rb = sc->sc_rbus_iot; 1979 1980 rbus_space_free(rb, ioh, size, NULL); 1981 #else 1982 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1983 bus_space_free(iot, ioh, size); 1984 else 1985 bus_space_unmap(iot, ioh, size); 1986 #endif 1987 } 1988 1989 /* 1990 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1991 * bus_addr_t offset, bus_size_t size, 1992 * struct pcmcia_io_handle *pcihp, 1993 * int *windowp) 1994 * 1995 * This function maps the allocated I/O region to pccard. This function 1996 * never allocates any I/O region for pccard I/O area. I don't 1997 * understand why the original authors of pcmciabus separated alloc and 1998 * map. I believe the two must be unite. 1999 * 2000 * XXX: no wait timing control? 2001 */ 2002 int 2003 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2004 pcmcia_chipset_handle_t pch; 2005 int width; 2006 bus_addr_t offset; 2007 bus_size_t size; 2008 struct pcmcia_io_handle *pcihp; 2009 int *windowp; 2010 { 2011 struct pcic_handle *ph = (struct pcic_handle *)pch; 2012 bus_addr_t ioaddr = pcihp->addr + offset; 2013 int i, win; 2014 #if defined CBB_DEBUG 2015 static char *width_names[] = { "dynamic", "io8", "io16" }; 2016 #endif 2017 2018 /* Sanity check I/O handle. */ 2019 2020 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2021 panic("pccbb_pcmcia_io_map iot is bogus"); 2022 } 2023 2024 /* XXX Sanity check offset/size. */ 2025 2026 win = -1; 2027 for (i = 0; i < PCIC_IO_WINS; i++) { 2028 if ((ph->ioalloc & (1 << i)) == 0) { 2029 win = i; 2030 ph->ioalloc |= (1 << i); 2031 break; 2032 } 2033 } 2034 2035 if (win == -1) { 2036 return 1; 2037 } 2038 2039 *windowp = win; 2040 2041 /* XXX this is pretty gross */ 2042 2043 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2044 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2045 2046 /* XXX wtf is this doing here? */ 2047 2048 #if 0 2049 printf(" port 0x%lx", (u_long) ioaddr); 2050 if (size > 1) { 2051 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2052 } 2053 #endif 2054 2055 ph->io[win].addr = ioaddr; 2056 ph->io[win].size = size; 2057 ph->io[win].width = width; 2058 2059 /* actual dirty register-value changing in the function below. */ 2060 pccbb_pcmcia_do_io_map(ph, win); 2061 2062 return 0; 2063 } 2064 2065 /* 2066 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2067 * 2068 * This function changes register-value to map I/O region for pccard. 2069 */ 2070 static void 2071 pccbb_pcmcia_do_io_map(ph, win) 2072 struct pcic_handle *ph; 2073 int win; 2074 { 2075 static u_int8_t pcic_iowidth[3] = { 2076 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2077 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2078 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2079 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2080 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2081 }; 2082 2083 #define PCIC_SIA_START_LOW 0 2084 #define PCIC_SIA_START_HIGH 1 2085 #define PCIC_SIA_STOP_LOW 2 2086 #define PCIC_SIA_STOP_HIGH 3 2087 2088 int regbase_win = 0x8 + win * 0x04; 2089 u_int8_t ioctl, enable; 2090 2091 DPRINTF( 2092 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2093 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2094 ph->io[win].width * 8)); 2095 2096 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2097 ph->io[win].addr & 0xff); 2098 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2099 (ph->io[win].addr >> 8) & 0xff); 2100 2101 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2102 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2103 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2104 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2105 2106 ioctl = Pcic_read(ph, PCIC_IOCTL); 2107 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2108 switch (win) { 2109 case 0: 2110 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2111 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2112 PCIC_IOCTL_IO0_DATASIZE_MASK); 2113 ioctl |= pcic_iowidth[ph->io[win].width]; 2114 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2115 break; 2116 case 1: 2117 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2118 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2119 PCIC_IOCTL_IO1_DATASIZE_MASK); 2120 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2121 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2122 break; 2123 } 2124 Pcic_write(ph, PCIC_IOCTL, ioctl); 2125 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2126 #if defined CBB_DEBUG 2127 { 2128 u_int8_t start_low = 2129 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2130 u_int8_t start_high = 2131 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2132 u_int8_t stop_low = 2133 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2134 u_int8_t stop_high = 2135 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2136 printf 2137 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2138 start_low, start_high, stop_low, stop_high, ioctl, enable); 2139 } 2140 #endif 2141 } 2142 2143 /* 2144 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2145 * 2146 * This function unmaps I/O region. No return value. 2147 */ 2148 STATIC void 2149 pccbb_pcmcia_io_unmap(pch, win) 2150 pcmcia_chipset_handle_t pch; 2151 int win; 2152 { 2153 struct pcic_handle *ph = (struct pcic_handle *)pch; 2154 int reg; 2155 2156 if (win >= PCIC_IO_WINS || win < 0) { 2157 panic("pccbb_pcmcia_io_unmap: window out of range"); 2158 } 2159 2160 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2161 switch (win) { 2162 case 0: 2163 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2164 break; 2165 case 1: 2166 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2167 break; 2168 } 2169 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2170 2171 ph->ioalloc &= ~(1 << win); 2172 } 2173 2174 /* 2175 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2176 * 2177 * This function enables the card. All information is stored in 2178 * the first argument, pcmcia_chipset_handle_t. 2179 */ 2180 static void 2181 pccbb_pcmcia_wait_ready(ph) 2182 struct pcic_handle *ph; 2183 { 2184 int i; 2185 2186 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2187 Pcic_read(ph, PCIC_IF_STATUS))); 2188 2189 for (i = 0; i < 10000; i++) { 2190 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2191 return; 2192 } 2193 delay(500); 2194 #ifdef CBB_DEBUG 2195 if ((i > 5000) && (i % 100 == 99)) 2196 printf("."); 2197 #endif 2198 } 2199 2200 #ifdef DIAGNOSTIC 2201 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2202 Pcic_read(ph, PCIC_IF_STATUS)); 2203 #endif 2204 } 2205 2206 /* 2207 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2208 * 2209 * This function enables the card. All information is stored in 2210 * the first argument, pcmcia_chipset_handle_t. 2211 */ 2212 STATIC void 2213 pccbb_pcmcia_socket_enable(pch) 2214 pcmcia_chipset_handle_t pch; 2215 { 2216 struct pcic_handle *ph = (struct pcic_handle *)pch; 2217 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2218 int cardtype, win; 2219 u_int8_t power, intr; 2220 pcireg_t spsr; 2221 int voltage; 2222 2223 /* this bit is mostly stolen from pcic_attach_card */ 2224 2225 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2226 2227 /* get card Vcc info */ 2228 2229 spsr = 2230 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2231 CB_SOCKET_STAT); 2232 if (spsr & CB_SOCKET_STAT_5VCARD) { 2233 DPRINTF(("5V card\n")); 2234 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2235 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2236 DPRINTF(("3V card\n")); 2237 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2238 } else { 2239 printf("?V card, 0x%x\n", spsr); /* XXX */ 2240 return; 2241 } 2242 2243 /* disable socket i/o: negate output enable bit */ 2244 2245 power = 0; 2246 Pcic_write(ph, PCIC_PWRCTL, power); 2247 2248 /* power down the socket to reset it, clear the card reset pin */ 2249 2250 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2251 2252 /* 2253 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2254 * we are changing Vcc (Toff). 2255 */ 2256 /* delay(300*1000); too much */ 2257 2258 /* assert reset bit */ 2259 intr = Pcic_read(ph, PCIC_INTR); 2260 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2261 Pcic_write(ph, PCIC_INTR, intr); 2262 2263 /* power up the socket and output enable */ 2264 power = Pcic_read(ph, PCIC_PWRCTL); 2265 power |= PCIC_PWRCTL_OE; 2266 Pcic_write(ph, PCIC_PWRCTL, power); 2267 pccbb_power(sc, voltage); 2268 2269 /* 2270 * hold RESET at least 10us. 2271 */ 2272 delay(10); 2273 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2274 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2275 2276 /* clear the reset flag */ 2277 2278 intr |= PCIC_INTR_RESET; 2279 Pcic_write(ph, PCIC_INTR, intr); 2280 2281 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2282 2283 delay(20000); 2284 2285 /* wait for the chip to finish initializing */ 2286 2287 pccbb_pcmcia_wait_ready(ph); 2288 2289 /* zero out the address windows */ 2290 2291 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2292 2293 /* set the card type */ 2294 2295 cardtype = pcmcia_card_gettype(ph->pcmcia); 2296 2297 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2298 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2299 Pcic_write(ph, PCIC_INTR, intr); 2300 2301 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2302 ph->ph_parent->dv_xname, ph->sock, 2303 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2304 2305 /* reinstall all the memory and io mappings */ 2306 2307 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2308 if (ph->memalloc & (1 << win)) { 2309 pccbb_pcmcia_do_mem_map(ph, win); 2310 } 2311 } 2312 2313 for (win = 0; win < PCIC_IO_WINS; ++win) { 2314 if (ph->ioalloc & (1 << win)) { 2315 pccbb_pcmcia_do_io_map(ph, win); 2316 } 2317 } 2318 } 2319 2320 /* 2321 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2322 * 2323 * This function disables the card. All information is stored in 2324 * the first argument, pcmcia_chipset_handle_t. 2325 */ 2326 STATIC void 2327 pccbb_pcmcia_socket_disable(pch) 2328 pcmcia_chipset_handle_t pch; 2329 { 2330 struct pcic_handle *ph = (struct pcic_handle *)pch; 2331 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2332 u_int8_t power, intr; 2333 2334 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2335 2336 /* reset signal asserting... */ 2337 2338 intr = Pcic_read(ph, PCIC_INTR); 2339 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2340 Pcic_write(ph, PCIC_INTR, intr); 2341 delay(2 * 1000); 2342 2343 /* power down the socket */ 2344 power = Pcic_read(ph, PCIC_PWRCTL); 2345 power &= ~PCIC_PWRCTL_OE; 2346 Pcic_write(ph, PCIC_PWRCTL, power); 2347 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2348 /* 2349 * wait 300ms until power fails (Tpf). 2350 */ 2351 delay(300 * 1000); 2352 } 2353 2354 /* 2355 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2356 * 2357 * This function detects whether a card is in the slot or not. 2358 * If a card is inserted, return 1. Otherwise, return 0. 2359 */ 2360 STATIC int 2361 pccbb_pcmcia_card_detect(pch) 2362 pcmcia_chipset_handle_t pch; 2363 { 2364 struct pcic_handle *ph = (struct pcic_handle *)pch; 2365 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2366 2367 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2368 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2369 } 2370 2371 #if 0 2372 STATIC int 2373 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2374 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2375 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2376 #endif 2377 /* 2378 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2379 * bus_size_t size, 2380 * struct pcmcia_mem_handle *pcmhp) 2381 * 2382 * This function only allocates memory region for pccard. This 2383 * function never maps the allocated region to pccard memory area. 2384 * 2385 * XXX: Why the argument of start address is not in? 2386 */ 2387 STATIC int 2388 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2389 pcmcia_chipset_handle_t pch; 2390 bus_size_t size; 2391 struct pcmcia_mem_handle *pcmhp; 2392 { 2393 struct pcic_handle *ph = (struct pcic_handle *)pch; 2394 bus_space_handle_t memh; 2395 bus_addr_t addr; 2396 bus_size_t sizepg; 2397 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2398 #if rbus 2399 rbus_tag_t rb; 2400 #endif 2401 2402 /* out of sc->memh, allocate as many pages as necessary */ 2403 2404 /* convert size to PCIC pages */ 2405 /* 2406 * This is not enough; when the requested region is on the page 2407 * boundaries, this may calculate wrong result. 2408 */ 2409 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2410 #if 0 2411 if (sizepg > PCIC_MAX_MEM_PAGES) { 2412 return 1; 2413 } 2414 #endif 2415 2416 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2417 return 1; 2418 } 2419 2420 addr = 0; /* XXX gcc -Wuninitialized */ 2421 2422 #if rbus 2423 rb = sc->sc_rbus_memt; 2424 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2425 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2426 &addr, &memh)) { 2427 return 1; 2428 } 2429 #else 2430 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2431 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2432 0, /* boundary */ 2433 0, /* flags */ 2434 &addr, &memh)) { 2435 return 1; 2436 } 2437 #endif 2438 2439 DPRINTF( 2440 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2441 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2442 2443 pcmhp->memt = sc->sc_memt; 2444 pcmhp->memh = memh; 2445 pcmhp->addr = addr; 2446 pcmhp->size = size; 2447 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2448 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2449 pcmhp->mhandle = 0; 2450 /* No offset??? Funny. */ 2451 2452 return 0; 2453 } 2454 2455 /* 2456 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2457 * struct pcmcia_mem_handle *pcmhp) 2458 * 2459 * This function release the memory space allocated by the function 2460 * pccbb_pcmcia_mem_alloc(). 2461 */ 2462 STATIC void 2463 pccbb_pcmcia_mem_free(pch, pcmhp) 2464 pcmcia_chipset_handle_t pch; 2465 struct pcmcia_mem_handle *pcmhp; 2466 { 2467 #if rbus 2468 struct pcic_handle *ph = (struct pcic_handle *)pch; 2469 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2470 2471 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2472 #else 2473 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2474 #endif 2475 } 2476 2477 /* 2478 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2479 * 2480 * This function release the memory space allocated by the function 2481 * pccbb_pcmcia_mem_alloc(). 2482 */ 2483 STATIC void 2484 pccbb_pcmcia_do_mem_map(ph, win) 2485 struct pcic_handle *ph; 2486 int win; 2487 { 2488 int regbase_win; 2489 bus_addr_t phys_addr; 2490 bus_addr_t phys_end; 2491 2492 #define PCIC_SMM_START_LOW 0 2493 #define PCIC_SMM_START_HIGH 1 2494 #define PCIC_SMM_STOP_LOW 2 2495 #define PCIC_SMM_STOP_HIGH 3 2496 #define PCIC_CMA_LOW 4 2497 #define PCIC_CMA_HIGH 5 2498 2499 u_int8_t start_low, start_high = 0; 2500 u_int8_t stop_low, stop_high; 2501 u_int8_t off_low, off_high; 2502 u_int8_t mem_window; 2503 int reg; 2504 2505 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2506 int mem8 = 2507 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2508 || (kind == PCMCIA_MEM_ATTR); 2509 2510 regbase_win = 0x10 + win * 0x08; 2511 2512 phys_addr = ph->mem[win].addr; 2513 phys_end = phys_addr + ph->mem[win].size; 2514 2515 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2516 phys_addr, phys_end, ph->mem[win].offset)); 2517 2518 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2519 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2520 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2521 2522 /* bit 19:12 */ 2523 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2524 /* bit 23:20 and bit 7 on */ 2525 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2526 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2527 /* bit 31:24, for 32-bit address */ 2528 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2529 2530 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2531 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2532 2533 if (((struct pccbb_softc *)ph-> 2534 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2535 Pcic_write(ph, 0x40 + win, mem_window); 2536 } 2537 2538 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2539 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2540 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2541 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2542 2543 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2544 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2545 2546 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2547 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2548 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2549 | ((kind == PCMCIA_MEM_ATTR) ? 2550 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2551 2552 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2553 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2554 2555 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2556 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2557 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2558 2559 #if defined CBB_DEBUG 2560 { 2561 int r1, r2, r3, r4, r5, r6, r7 = 0; 2562 2563 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2564 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2565 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2566 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2567 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2568 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2569 if (((struct pccbb_softc *)(ph-> 2570 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2571 r7 = Pcic_read(ph, 0x40 + win); 2572 } 2573 2574 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2575 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2576 if (((struct pccbb_softc *)(ph-> 2577 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2578 DPRINTF((" %02x", r7)); 2579 } 2580 DPRINTF(("\n")); 2581 } 2582 #endif 2583 } 2584 2585 /* 2586 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2587 * bus_addr_t card_addr, bus_size_t size, 2588 * struct pcmcia_mem_handle *pcmhp, 2589 * bus_addr_t *offsetp, int *windowp) 2590 * 2591 * This function maps memory space allocated by the function 2592 * pccbb_pcmcia_mem_alloc(). 2593 */ 2594 STATIC int 2595 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2596 pcmcia_chipset_handle_t pch; 2597 int kind; 2598 bus_addr_t card_addr; 2599 bus_size_t size; 2600 struct pcmcia_mem_handle *pcmhp; 2601 bus_addr_t *offsetp; 2602 int *windowp; 2603 { 2604 struct pcic_handle *ph = (struct pcic_handle *)pch; 2605 bus_addr_t busaddr; 2606 long card_offset; 2607 int win; 2608 2609 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2610 if ((ph->memalloc & (1 << win)) == 0) { 2611 ph->memalloc |= (1 << win); 2612 break; 2613 } 2614 } 2615 2616 if (win == PCIC_MEM_WINS) { 2617 return 1; 2618 } 2619 2620 *windowp = win; 2621 2622 /* XXX this is pretty gross */ 2623 2624 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2625 panic("pccbb_pcmcia_mem_map memt is bogus"); 2626 } 2627 2628 busaddr = pcmhp->addr; 2629 2630 /* 2631 * compute the address offset to the pcmcia address space for the 2632 * pcic. this is intentionally signed. The masks and shifts below 2633 * will cause TRT to happen in the pcic registers. Deal with making 2634 * sure the address is aligned, and return the alignment offset. 2635 */ 2636 2637 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2638 card_addr -= *offsetp; 2639 2640 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2641 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2642 (u_long) card_addr)); 2643 2644 /* 2645 * include the offset in the size, and decrement size by one, since 2646 * the hw wants start/stop 2647 */ 2648 size += *offsetp - 1; 2649 2650 card_offset = (((long)card_addr) - ((long)busaddr)); 2651 2652 ph->mem[win].addr = busaddr; 2653 ph->mem[win].size = size; 2654 ph->mem[win].offset = card_offset; 2655 ph->mem[win].kind = kind; 2656 2657 pccbb_pcmcia_do_mem_map(ph, win); 2658 2659 return 0; 2660 } 2661 2662 /* 2663 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2664 * int window) 2665 * 2666 * This function unmaps memory space which mapped by the function 2667 * pccbb_pcmcia_mem_map(). 2668 */ 2669 STATIC void 2670 pccbb_pcmcia_mem_unmap(pch, window) 2671 pcmcia_chipset_handle_t pch; 2672 int window; 2673 { 2674 struct pcic_handle *ph = (struct pcic_handle *)pch; 2675 int reg; 2676 2677 if (window >= PCIC_MEM_WINS) { 2678 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2679 } 2680 2681 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2682 reg &= ~(1 << window); 2683 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2684 2685 ph->memalloc &= ~(1 << window); 2686 } 2687 2688 #if defined PCCBB_PCMCIA_POLL 2689 struct pccbb_poll_str { 2690 void *arg; 2691 int (*func) __P((void *)); 2692 int level; 2693 struct pcic_handle *ph; 2694 int count; 2695 int num; 2696 struct callout poll_ch; 2697 }; 2698 2699 static struct pccbb_poll_str pccbb_poll[10]; 2700 static int pccbb_poll_n = 0; 2701 2702 static void pccbb_pcmcia_poll __P((void *arg)); 2703 2704 static void 2705 pccbb_pcmcia_poll(arg) 2706 void *arg; 2707 { 2708 struct pccbb_poll_str *poll = arg; 2709 struct pcic_handle *ph = poll->ph; 2710 struct pccbb_softc *sc = ph->sc; 2711 int s; 2712 u_int32_t spsr; /* socket present-state reg */ 2713 2714 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2715 switch (poll->level) { 2716 case IPL_NET: 2717 s = splnet(); 2718 break; 2719 case IPL_BIO: 2720 s = splbio(); 2721 break; 2722 case IPL_TTY: /* fallthrough */ 2723 default: 2724 s = spltty(); 2725 break; 2726 } 2727 2728 spsr = 2729 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2730 CB_SOCKET_STAT); 2731 2732 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2733 if (!(spsr & 0x40)) /* CINT low */ 2734 #else 2735 if (1) 2736 #endif 2737 { 2738 if ((*poll->func) (poll->arg) > 0) { 2739 ++poll->count; 2740 // printf("intr: reported from poller, 0x%x\n", spsr); 2741 #if defined LEVEL2 2742 } else { 2743 printf("intr: miss! 0x%x\n", spsr); 2744 #endif 2745 } 2746 } 2747 splx(s); 2748 } 2749 #endif /* defined CB_PCMCIA_POLL */ 2750 2751 /* 2752 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2753 * struct pcmcia_function *pf, 2754 * int ipl, 2755 * int (*func)(void *), 2756 * void *arg); 2757 * 2758 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2759 */ 2760 STATIC void * 2761 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2762 pcmcia_chipset_handle_t pch; 2763 struct pcmcia_function *pf; 2764 int ipl; 2765 int (*func) __P((void *)); 2766 void *arg; 2767 { 2768 struct pcic_handle *ph = (struct pcic_handle *)pch; 2769 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2770 2771 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2772 /* what should I do? */ 2773 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2774 DPRINTF( 2775 ("%s does not provide edge nor pulse interrupt\n", 2776 sc->sc_dev.dv_xname)); 2777 return NULL; 2778 } 2779 /* 2780 * XXX Noooooo! The interrupt flag must set properly!! 2781 * dumb pcmcia driver!! 2782 */ 2783 } 2784 2785 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2786 } 2787 2788 /* 2789 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2790 * void *ih) 2791 * 2792 * This function disables PC-Card interrupt. 2793 */ 2794 STATIC void 2795 pccbb_pcmcia_intr_disestablish(pch, ih) 2796 pcmcia_chipset_handle_t pch; 2797 void *ih; 2798 { 2799 struct pcic_handle *ph = (struct pcic_handle *)pch; 2800 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2801 2802 pccbb_intr_disestablish(sc, ih); 2803 } 2804 2805 #if rbus 2806 /* 2807 * static int 2808 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2809 * bus_addr_t addr, bus_size_t size, 2810 * bus_addr_t mask, bus_size_t align, 2811 * int flags, bus_addr_t *addrp; 2812 * bus_space_handle_t *bshp) 2813 * 2814 * This function allocates a portion of memory or io space for 2815 * clients. This function is called from CardBus card drivers. 2816 */ 2817 static int 2818 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2819 cardbus_chipset_tag_t ct; 2820 rbus_tag_t rb; 2821 bus_addr_t addr; 2822 bus_size_t size; 2823 bus_addr_t mask; 2824 bus_size_t align; 2825 int flags; 2826 bus_addr_t *addrp; 2827 bus_space_handle_t *bshp; 2828 { 2829 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2830 2831 DPRINTF( 2832 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2833 addr, size, mask, align)); 2834 2835 if (align == 0) { 2836 align = size; 2837 } 2838 2839 if (rb->rb_bt == sc->sc_memt) { 2840 if (align < 16) { 2841 return 1; 2842 } 2843 } else if (rb->rb_bt == sc->sc_iot) { 2844 if (align < 4) { 2845 return 1; 2846 } 2847 /* XXX: hack for avoiding ISA image */ 2848 if (mask < 0x0100) { 2849 mask = 0x3ff; 2850 addr = 0x300; 2851 } 2852 2853 } else { 2854 DPRINTF( 2855 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2856 rb->rb_bt)); 2857 return 1; 2858 /* XXX: panic here? */ 2859 } 2860 2861 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2862 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2863 return 1; 2864 } 2865 2866 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2867 2868 return 0; 2869 } 2870 2871 /* 2872 * static int 2873 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2874 * bus_space_handle_t *bshp, bus_size_t size); 2875 * 2876 * This function is called from CardBus card drivers. 2877 */ 2878 static int 2879 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2880 cardbus_chipset_tag_t ct; 2881 rbus_tag_t rb; 2882 bus_space_handle_t bsh; 2883 bus_size_t size; 2884 { 2885 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2886 bus_space_tag_t bt = rb->rb_bt; 2887 2888 pccbb_close_win(sc, bt, bsh, size); 2889 2890 if (bt == sc->sc_memt) { 2891 } else if (bt == sc->sc_iot) { 2892 } else { 2893 return 1; 2894 /* XXX: panic here? */ 2895 } 2896 2897 return rbus_space_free(rb, bsh, size, NULL); 2898 } 2899 #endif /* rbus */ 2900 2901 #if rbus 2902 2903 static int 2904 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2905 struct pccbb_softc *sc; 2906 bus_space_tag_t bst; 2907 bus_addr_t addr; 2908 bus_size_t size; 2909 bus_space_handle_t bsh; 2910 int flags; 2911 { 2912 struct pccbb_win_chain_head *head; 2913 bus_addr_t align; 2914 2915 head = &sc->sc_iowindow; 2916 align = 0x04; 2917 if (sc->sc_memt == bst) { 2918 head = &sc->sc_memwindow; 2919 align = 0x1000; 2920 DPRINTF(("using memory window, %x %x %x\n\n", 2921 sc->sc_iot, sc->sc_memt, bst)); 2922 } 2923 2924 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2925 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2926 sc->sc_dev.dv_xname, 2927 (head == &sc->sc_memwindow) ? "mem" : "io"); 2928 } 2929 pccbb_winset(align, sc, bst); 2930 2931 return 0; 2932 } 2933 2934 static int 2935 pccbb_close_win(sc, bst, bsh, size) 2936 struct pccbb_softc *sc; 2937 bus_space_tag_t bst; 2938 bus_space_handle_t bsh; 2939 bus_size_t size; 2940 { 2941 struct pccbb_win_chain_head *head; 2942 bus_addr_t align; 2943 2944 head = &sc->sc_iowindow; 2945 align = 0x04; 2946 if (sc->sc_memt == bst) { 2947 head = &sc->sc_memwindow; 2948 align = 0x1000; 2949 } 2950 2951 if (pccbb_winlist_delete(head, bsh, size)) { 2952 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2953 sc->sc_dev.dv_xname, 2954 (head == &sc->sc_memwindow) ? "mem" : "io"); 2955 } 2956 pccbb_winset(align, sc, bst); 2957 2958 return 0; 2959 } 2960 2961 static int 2962 pccbb_winlist_insert(head, start, size, bsh, flags) 2963 struct pccbb_win_chain_head *head; 2964 bus_addr_t start; 2965 bus_size_t size; 2966 bus_space_handle_t bsh; 2967 int flags; 2968 { 2969 struct pccbb_win_chain *chainp, *elem; 2970 2971 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2972 M_NOWAIT)) == NULL) 2973 return (1); /* fail */ 2974 2975 elem->wc_start = start; 2976 elem->wc_end = start + (size - 1); 2977 elem->wc_handle = bsh; 2978 elem->wc_flags = flags; 2979 2980 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2981 chainp = TAILQ_NEXT(chainp, wc_list)) { 2982 if (chainp->wc_end < start) 2983 continue; 2984 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2985 return (0); 2986 } 2987 2988 TAILQ_INSERT_TAIL(head, elem, wc_list); 2989 return (0); 2990 } 2991 2992 static int 2993 pccbb_winlist_delete(head, bsh, size) 2994 struct pccbb_win_chain_head *head; 2995 bus_space_handle_t bsh; 2996 bus_size_t size; 2997 { 2998 struct pccbb_win_chain *chainp; 2999 3000 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3001 chainp = TAILQ_NEXT(chainp, wc_list)) { 3002 if (chainp->wc_handle != bsh) 3003 continue; 3004 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3005 printf("pccbb_winlist_delete: window 0x%lx size " 3006 "inconsistent: 0x%lx, 0x%lx\n", 3007 chainp->wc_start, 3008 chainp->wc_end - chainp->wc_start, 3009 size - 1); 3010 return 1; 3011 } 3012 3013 TAILQ_REMOVE(head, chainp, wc_list); 3014 free(chainp, M_DEVBUF); 3015 3016 return 0; 3017 } 3018 3019 return 1; /* fail: no candidate to remove */ 3020 } 3021 3022 static void 3023 pccbb_winset(align, sc, bst) 3024 bus_addr_t align; 3025 struct pccbb_softc *sc; 3026 bus_space_tag_t bst; 3027 { 3028 pci_chipset_tag_t pc; 3029 pcitag_t tag; 3030 bus_addr_t mask = ~(align - 1); 3031 struct { 3032 cardbusreg_t win_start; 3033 cardbusreg_t win_limit; 3034 int win_flags; 3035 } win[2]; 3036 struct pccbb_win_chain *chainp; 3037 int offs; 3038 3039 win[0].win_start = 0xffffffff; 3040 win[0].win_limit = 0; 3041 win[1].win_start = 0xffffffff; 3042 win[1].win_limit = 0; 3043 3044 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3045 offs = 0x2c; 3046 if (sc->sc_memt == bst) { 3047 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3048 offs = 0x1c; 3049 } 3050 3051 if (chainp != NULL) { 3052 win[0].win_start = chainp->wc_start & mask; 3053 win[0].win_limit = chainp->wc_end & mask; 3054 win[0].win_flags = chainp->wc_flags; 3055 chainp = TAILQ_NEXT(chainp, wc_list); 3056 } 3057 3058 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3059 if (win[1].win_start == 0xffffffff) { 3060 /* window 1 is not used */ 3061 if ((win[0].win_flags == chainp->wc_flags) && 3062 (win[0].win_limit + align >= 3063 (chainp->wc_start & mask))) { 3064 /* concatenate */ 3065 win[0].win_limit = chainp->wc_end & mask; 3066 } else { 3067 /* make new window */ 3068 win[1].win_start = chainp->wc_start & mask; 3069 win[1].win_limit = chainp->wc_end & mask; 3070 win[1].win_flags = chainp->wc_flags; 3071 } 3072 continue; 3073 } 3074 3075 /* Both windows are engaged. */ 3076 if (win[0].win_flags == win[1].win_flags) { 3077 /* same flags */ 3078 if (win[0].win_flags == chainp->wc_flags) { 3079 if (win[1].win_start - (win[0].win_limit + 3080 align) < 3081 (chainp->wc_start & mask) - 3082 ((chainp->wc_end & mask) + align)) { 3083 /* 3084 * merge window 0 and 1, and set win1 3085 * to chainp 3086 */ 3087 win[0].win_limit = win[1].win_limit; 3088 win[1].win_start = 3089 chainp->wc_start & mask; 3090 win[1].win_limit = 3091 chainp->wc_end & mask; 3092 } else { 3093 win[1].win_limit = 3094 chainp->wc_end & mask; 3095 } 3096 } else { 3097 /* different flags */ 3098 3099 /* concatenate win0 and win1 */ 3100 win[0].win_limit = win[1].win_limit; 3101 /* allocate win[1] to new space */ 3102 win[1].win_start = chainp->wc_start & mask; 3103 win[1].win_limit = chainp->wc_end & mask; 3104 win[1].win_flags = chainp->wc_flags; 3105 } 3106 } else { 3107 /* the flags of win[0] and win[1] is different */ 3108 if (win[0].win_flags == chainp->wc_flags) { 3109 win[0].win_limit = chainp->wc_end & mask; 3110 /* 3111 * XXX this creates overlapping windows, so 3112 * what should the poor bridge do if one is 3113 * cachable, and the other is not? 3114 */ 3115 printf("%s: overlapping windows\n", 3116 sc->sc_dev.dv_xname); 3117 } else { 3118 win[1].win_limit = chainp->wc_end & mask; 3119 } 3120 } 3121 } 3122 3123 pc = sc->sc_pc; 3124 tag = sc->sc_tag; 3125 pci_conf_write(pc, tag, offs, win[0].win_start); 3126 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3127 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3128 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3129 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3130 pci_conf_read(pc, tag, offs), 3131 pci_conf_read(pc, tag, offs + 4) + align, 3132 pci_conf_read(pc, tag, offs + 8), 3133 pci_conf_read(pc, tag, offs + 12) + align)); 3134 3135 if (bst == sc->sc_memt) { 3136 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3137 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3138 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3139 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3140 } 3141 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3142 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3143 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3144 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3145 } 3146 } 3147 } 3148 3149 #endif /* rbus */ 3150 3151 static void 3152 pccbb_powerhook(why, arg) 3153 int why; 3154 void *arg; 3155 { 3156 struct pccbb_softc *sc = arg; 3157 u_int32_t reg; 3158 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3159 bus_space_handle_t base_memh = sc->sc_base_memh; 3160 3161 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3162 3163 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3164 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3165 if (sc->sc_pil_intr_enable) { 3166 (void)pccbbintr_function(sc); 3167 } 3168 sc->sc_pil_intr_enable = 0; 3169 3170 /* ToDo: deactivate or suspend child devices */ 3171 3172 } 3173 3174 if (why == PWR_RESUME) { 3175 /* CSC Interrupt: Card detect interrupt on */ 3176 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3177 /* Card detect intr is turned on. */ 3178 reg |= CB_SOCKET_MASK_CD; 3179 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3180 /* reset interrupt */ 3181 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3182 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3183 3184 /* 3185 * check for card insertion or removal during suspend period. 3186 * XXX: the code can't cope with card swap (remove then 3187 * insert). how can we detect such situation? 3188 */ 3189 (void)pccbbintr(sc); 3190 3191 sc->sc_pil_intr_enable = 1; 3192 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3193 3194 /* ToDo: activate or wakeup child devices */ 3195 } 3196 } 3197
Indexes created Fri Sep 26 08:10:20 GMT 2025