pccbb.c revision 1.55
1 /* $NetBSD: pccbb.c,v 1.55 2001/01/24 10:10:04 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/reboot.h> /* for bootverbose */ 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 #include <sys/proc.h> 57 58 #include <machine/intr.h> 59 #include <machine/bus.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/pccbbreg.h> 66 67 #include <dev/cardbus/cardslotvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 71 #include <dev/pcmcia/pcmciareg.h> 72 #include <dev/pcmcia/pcmciavar.h> 73 74 #include <dev/ic/i82365reg.h> 75 #include <dev/ic/i82365var.h> 76 #include <dev/pci/pccbbvar.h> 77 78 #include "locators.h" 79 80 #ifndef __NetBSD_Version__ 81 struct cfdriver cbb_cd = { 82 NULL, "cbb", DV_DULL 83 }; 84 #endif 85 86 #if defined CBB_DEBUG 87 #define DPRINTF(x) printf x 88 #define STATIC 89 #else 90 #define DPRINTF(x) 91 #define STATIC static 92 #endif 93 94 /* 95 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 96 * if you want to wait more than 1 ms. 97 */ 98 #define DELAY_MS(time, param) \ 99 do { \ 100 if (cold == 0) { \ 101 int tick = (hz*(time))/1000; \ 102 \ 103 if (tick <= 1) { \ 104 tick = 2; \ 105 } \ 106 tsleep((void *)(param), PCATCH, "pccbb", tick); \ 107 } else { \ 108 delay((time)*1000); \ 109 } \ 110 } while (0) 111 112 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 113 void pccbbattach __P((struct device *, struct device *, void *)); 114 int pccbbintr __P((void *)); 115 static void pci113x_insert __P((void *)); 116 static int pccbbintr_function __P((struct pccbb_softc *)); 117 118 static int pccbb_detect_card __P((struct pccbb_softc *)); 119 120 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 121 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset __P((struct pccbb_softc *)); 126 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 127 STATIC int cbbprint __P((void *, const char *)); 128 129 static int cb_chipset __P((u_int32_t, int *)); 130 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 131 struct pcmciabus_attach_args *)); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 134 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 135 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 136 #endif 137 138 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 139 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 140 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 141 #if !rbus 142 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 143 u_int32_t)); 144 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 145 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 146 u_int32_t)); 147 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc)); 151 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 152 153 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc)); 155 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 156 157 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 158 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 159 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 160 int)); 161 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 162 cardbusreg_t)); 163 static void pccbb_chipinit __P((struct pccbb_softc *)); 164 165 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 166 struct pcmcia_mem_handle *)); 167 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 168 struct pcmcia_mem_handle *)); 169 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 171 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 172 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 173 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 174 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *)); 176 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *)); 178 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 179 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 180 struct pcmcia_function *, int, int (*)(void *), void *)); 181 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 182 void *)); 183 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 184 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 185 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 186 187 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 188 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 189 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 190 static void pccbb_powerhook __P((int, void *)); 191 192 /* bus-space allocation and deallocation functions */ 193 #if rbus 194 195 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 196 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 197 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 198 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 199 bus_space_handle_t, bus_size_t)); 200 201 #endif /* rbus */ 202 203 #if rbus 204 205 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 206 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 207 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_space_handle_t, bus_size_t)); 209 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 210 bus_size_t, bus_space_handle_t, int)); 211 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 212 bus_space_handle_t, bus_size_t)); 213 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 214 bus_space_tag_t)); 215 void pccbb_winlist_show(struct pccbb_win_chain *); 216 217 #endif /* rbus */ 218 219 /* for config_defer */ 220 static void pccbb_pci_callback __P((struct device *)); 221 222 #if defined SHOW_REGS 223 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 224 bus_space_tag_t memt, bus_space_handle_t memh)); 225 #endif 226 227 struct cfattach cbb_pci_ca = { 228 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 229 }; 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_card_detect 245 }; 246 247 #if rbus 248 static struct cardbus_functions pccbb_funcs = { 249 pccbb_rbus_cb_space_alloc, 250 pccbb_rbus_cb_space_free, 251 pccbb_cb_intr_establish, 252 pccbb_cb_intr_disestablish, 253 pccbb_ctrl, 254 pccbb_power, 255 pccbb_make_tag, 256 pccbb_free_tag, 257 pccbb_conf_read, 258 pccbb_conf_write, 259 }; 260 #else 261 static struct cardbus_functions pccbb_funcs = { 262 pccbb_ctrl, 263 pccbb_power, 264 pccbb_mem_open, 265 pccbb_mem_close, 266 pccbb_io_open, 267 pccbb_io_close, 268 pccbb_cb_intr_establish, 269 pccbb_cb_intr_disestablish, 270 pccbb_make_tag, 271 pccbb_conf_read, 272 pccbb_conf_write, 273 }; 274 #endif 275 276 int 277 pcicbbmatch(parent, match, aux) 278 struct device *parent; 279 struct cfdata *match; 280 void *aux; 281 { 282 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 283 284 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 285 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 286 PCI_INTERFACE(pa->pa_class) == 0) { 287 return 1; 288 } 289 290 return 0; 291 } 292 293 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 294 | ((prod) << PCI_PRODUCT_SHIFT)) 295 296 struct yenta_chipinfo { 297 pcireg_t yc_id; /* vendor tag | product tag */ 298 int yc_chiptype; 299 int yc_flags; 300 } yc_chipsets[] = { 301 /* Texas Instruments chips */ 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 327 /* Ricoh chips */ 328 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 329 PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 331 PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 339 PCCBB_PCMCIA_MEM_32}, 340 341 /* Toshiba products */ 342 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 343 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 345 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 347 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 349 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 350 351 /* Cirrus Logic products */ 352 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 353 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 355 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 356 357 /* sentinel, or Generic chip */ 358 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 359 }; 360 361 static int 362 cb_chipset(pci_id, flagp) 363 u_int32_t pci_id; 364 int *flagp; 365 { 366 struct yenta_chipinfo *yc; 367 368 /* Loop over except the last default entry. */ 369 for (yc = yc_chipsets; yc < yc_chipsets + 370 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 371 if (pci_id == yc->yc_id) 372 break; 373 374 if (flagp != NULL) 375 *flagp = yc->yc_flags; 376 377 return (yc->yc_chiptype); 378 } 379 380 static void 381 pccbb_shutdown(void *arg) 382 { 383 struct pccbb_softc *sc = arg; 384 pcireg_t command; 385 386 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 387 388 /* 389 * turn off power 390 * 391 * XXX - do not turn off power if chipset is TI 113X because 392 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 393 */ 394 if (sc->sc_chipset != CB_TI113X) { 395 pccbb_power((cardbus_chipset_tag_t)sc, 396 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 397 } 398 399 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 400 0); 401 402 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 403 404 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 405 PCI_COMMAND_MASTER_ENABLE); 406 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 407 408 } 409 410 void 411 pccbbattach(parent, self, aux) 412 struct device *parent; 413 struct device *self; 414 void *aux; 415 { 416 struct pccbb_softc *sc = (void *)self; 417 struct pci_attach_args *pa = aux; 418 pci_chipset_tag_t pc = pa->pa_pc; 419 pcireg_t busreg, reg, sock_base; 420 bus_addr_t sockbase; 421 char devinfo[256]; 422 int flags; 423 424 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 425 426 pci_devinfo(pa->pa_id, 0, 0, devinfo); 427 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 428 #ifdef CBB_DEBUG 429 printf(" (chipflags %x)", flags); 430 #endif 431 printf("\n"); 432 433 TAILQ_INIT(&sc->sc_memwindow); 434 TAILQ_INIT(&sc->sc_iowindow); 435 436 #if rbus 437 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 438 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 439 #endif /* rbus */ 440 441 sc->sc_base_memh = 0; 442 443 /* 444 * MAP socket registers and ExCA registers on memory-space 445 * When no valid address is set on socket base registers (on pci 446 * config space), get it not polite way. 447 */ 448 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 449 450 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 451 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 452 /* The address must be valid. */ 453 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 454 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 455 printf("%s: can't map socket base address 0x%x\n", 456 sc->sc_dev.dv_xname, sock_base); 457 /* 458 * I think it's funny: socket base registers must be 459 * mapped on memory space, but ... 460 */ 461 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 462 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 463 NULL)) { 464 printf("%s: can't map socket base address" 465 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 466 sockbase); 467 /* give up... allocate reg space via rbus. */ 468 sc->sc_base_memh = 0; 469 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 470 } 471 } else { 472 DPRINTF(("%s: socket base address 0x%lx\n", 473 sc->sc_dev.dv_xname, sockbase)); 474 } 475 } 476 477 sc->sc_mem_start = 0; /* XXX */ 478 sc->sc_mem_end = 0xffffffff; /* XXX */ 479 480 /* 481 * When interrupt isn't routed correctly, give up probing cbb and do 482 * not kill pcic-compatible port. 483 */ 484 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 485 printf("%s: NOT USED because of unconfigured interrupt\n", 486 sc->sc_dev.dv_xname); 487 return; 488 } 489 490 /* 491 * When bus number isn't set correctly, give up using 32-bit CardBus 492 * mode. 493 */ 494 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 495 #if notyet 496 if (((busreg >> 8) & 0xff) == 0) { 497 printf("%s: CardBus support disabled because of unconfigured bus number\n", 498 sc->sc_dev.dv_xname); 499 flags |= PCCBB_PCMCIA_16BITONLY; 500 } 501 #endif 502 503 /* pccbb_machdep.c end */ 504 505 #if defined CBB_DEBUG 506 { 507 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 508 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 509 intrname[pa->pa_intrpin], pa->pa_intrline); 510 } 511 #endif 512 513 /* setup softc */ 514 sc->sc_pc = pc; 515 sc->sc_iot = pa->pa_iot; 516 sc->sc_memt = pa->pa_memt; 517 sc->sc_dmat = pa->pa_dmat; 518 sc->sc_tag = pa->pa_tag; 519 sc->sc_function = pa->pa_function; 520 521 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 522 523 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 524 525 shutdownhook_establish(pccbb_shutdown, sc); 526 527 /* Disable legacy register mapping. */ 528 switch (sc->sc_chipset) { 529 case CB_RX5C46X: /* fallthrough */ 530 #if 0 531 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 532 case CB_RX5C47X: 533 #endif 534 /* 535 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 536 * cannot be disabled by substituting 0 into PCI_LEGACY 537 * register. Ricoh CardBus bridges have special bits on Bridge 538 * control reg (addr 0x3e on PCI config space). 539 */ 540 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 541 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 542 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 543 break; 544 545 default: 546 /* XXX I don't know proper way to kill legacy I/O. */ 547 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 548 break; 549 } 550 551 config_defer(self, pccbb_pci_callback); 552 } 553 554 555 556 557 /* 558 * static void pccbb_pci_callback(struct device *self) 559 * 560 * The actual attach routine: get memory space for YENTA register 561 * space, setup YENTA register and route interrupt. 562 * 563 * This function should be deferred because this device may obtain 564 * memory space dynamically. This function must avoid obtaining 565 * memory area which has already kept for another device. 566 */ 567 static void 568 pccbb_pci_callback(self) 569 struct device *self; 570 { 571 struct pccbb_softc *sc = (void *)self; 572 pci_chipset_tag_t pc = sc->sc_pc; 573 bus_space_tag_t base_memt; 574 bus_space_handle_t base_memh; 575 u_int32_t maskreg; 576 pci_intr_handle_t ih; 577 const char *intrstr = NULL; 578 bus_addr_t sockbase; 579 struct cbslot_attach_args cba; 580 struct pcmciabus_attach_args paa; 581 struct cardslot_attach_args caa; 582 struct cardslot_softc *csc; 583 584 if (0 == sc->sc_base_memh) { 585 /* The socket registers aren't mapped correctly. */ 586 #if rbus 587 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 588 (sc->sc_chipset == CB_RX5C47X 589 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 590 0, &sockbase, &sc->sc_base_memh)) { 591 return; 592 } 593 sc->sc_base_memt = sc->sc_memt; 594 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 595 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 596 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 597 PCI_SOCKBASE))); 598 #else 599 sc->sc_base_memt = sc->sc_memt; 600 #if !defined CBB_PCI_BASE 601 #define CBB_PCI_BASE 0x20000000 602 #endif 603 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 604 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 605 /* cannot allocate memory space */ 606 return; 607 } 608 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 609 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 610 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 611 sc->sc_tag, PCI_SOCKBASE))); 612 #endif 613 } 614 615 /* bus bridge initialization */ 616 pccbb_chipinit(sc); 617 618 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 619 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 620 621 /* CSC Interrupt: Card detect interrupt on */ 622 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 623 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 624 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 625 /* reset interrupt */ 626 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 627 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 628 629 /* clear data structure for child device interrupt handlers */ 630 sc->sc_pil = NULL; 631 sc->sc_pil_intr_enable = 1; 632 633 /* Map and establish the interrupt. */ 634 if (pci_intr_map(&sc->sc_pa, &ih)) { 635 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 636 return; 637 } 638 intrstr = pci_intr_string(pc, ih); 639 640 /* 641 * XXX pccbbintr should be called under the priority lower 642 * than any other hard interrputs. 643 */ 644 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 645 646 if (sc->sc_ih == NULL) { 647 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 648 if (intrstr != NULL) { 649 printf(" at %s", intrstr); 650 } 651 printf("\n"); 652 return; 653 } 654 655 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 656 powerhook_establish(pccbb_powerhook, sc); 657 658 { 659 u_int32_t sockstat = 660 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 661 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 662 sc->sc_flags |= CBB_CARDEXIST; 663 } 664 } 665 666 /* 667 * attach cardbus 668 */ 669 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 670 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 671 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 672 673 /* initialize cbslot_attach */ 674 cba.cba_busname = "cardbus"; 675 cba.cba_iot = sc->sc_iot; 676 cba.cba_memt = sc->sc_memt; 677 cba.cba_dmat = sc->sc_dmat; 678 cba.cba_bus = (busreg >> 8) & 0x0ff; 679 cba.cba_cc = (void *)sc; 680 cba.cba_cf = &pccbb_funcs; 681 cba.cba_intrline = sc->sc_pa.pa_intrline; 682 683 #if rbus 684 cba.cba_rbus_iot = sc->sc_rbus_iot; 685 cba.cba_rbus_memt = sc->sc_rbus_memt; 686 #endif 687 688 cba.cba_cacheline = PCI_CACHELINE(bhlc); 689 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 690 691 if (bootverbose) { 692 printf("%s: cacheline 0x%x lattimer 0x%x\n", 693 sc->sc_dev.dv_xname, cba.cba_cacheline, 694 cba.cba_lattimer); 695 printf("%s: bhlc 0x%x lscp 0x%x\n", 696 sc->sc_dev.dv_xname, bhlc, busreg); 697 } 698 #if defined SHOW_REGS 699 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 700 sc->sc_base_memh); 701 #endif 702 } 703 704 pccbb_pcmcia_attach_setup(sc, &paa); 705 caa.caa_cb_attach = NULL; 706 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 707 caa.caa_cb_attach = &cba; 708 } 709 caa.caa_16_attach = &paa; 710 caa.caa_ph = &sc->sc_pcmcia_h; 711 712 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 713 DPRINTF(("pccbbattach: found cardslot\n")); 714 sc->sc_csc = csc; 715 } 716 717 return; 718 } 719 720 721 722 723 724 /* 725 * static void pccbb_chipinit(struct pccbb_softc *sc) 726 * 727 * This function initialize YENTA chip registers listed below: 728 * 1) PCI command reg, 729 * 2) PCI and CardBus latency timer, 730 * 3) route PCI interrupt, 731 * 4) close all memory and io windows. 732 */ 733 static void 734 pccbb_chipinit(sc) 735 struct pccbb_softc *sc; 736 { 737 pci_chipset_tag_t pc = sc->sc_pc; 738 pcitag_t tag = sc->sc_tag; 739 pcireg_t reg; 740 741 /* 742 * Set PCI command reg. 743 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 744 */ 745 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 746 /* I believe it is harmless. */ 747 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 748 PCI_COMMAND_MASTER_ENABLE); 749 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 750 751 /* 752 * Set CardBus latency timer. 753 */ 754 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 755 if (PCI_CB_LATENCY(reg) < 0x20) { 756 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 757 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 758 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 759 } 760 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 761 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 762 763 /* 764 * Set PCI latency timer. 765 */ 766 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 767 if (PCI_LATTIMER(reg) < 0x10) { 768 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 769 reg |= (0x10 << PCI_LATTIMER_SHIFT); 770 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 771 } 772 DPRINTF(("PCI latency timer 0x%x (%x)\n", 773 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 774 775 776 /* Route functional interrupts to PCI. */ 777 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 778 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 779 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 780 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 781 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 782 783 switch (sc->sc_chipset) { 784 case CB_TI113X: 785 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 786 /* This bit is shared, but may read as 0 on some chips, so set 787 it explicitly on both functions. */ 788 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 789 /* CSC intr enable */ 790 reg |= PCI113X_CBCTRL_PCI_CSC; 791 /* functional intr prohibit | prohibit ISA routing */ 792 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 793 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 794 break; 795 796 case CB_TI12XX: 797 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 798 reg |= PCI12XX_SYSCTRL_VCCPROT; 799 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 800 break; 801 802 case CB_TOPIC95B: 803 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 804 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 805 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 806 807 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 808 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 809 sc->sc_dev.dv_xname, reg)); 810 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 811 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 812 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 813 DPRINTF(("0x%x\n", reg)); 814 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 815 break; 816 } 817 818 /* Close all memory and I/O windows. */ 819 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 820 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 821 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 822 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 823 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 824 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 825 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 826 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 827 828 /* reset 16-bit pcmcia bus */ 829 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 830 0x800 + PCIC_INTR, 831 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 832 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 833 834 /* turn of power */ 835 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 836 } 837 838 839 840 841 /* 842 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 843 * struct pcmciabus_attach_args *paa) 844 * 845 * This function attaches 16-bit PCcard bus. 846 */ 847 STATIC void 848 pccbb_pcmcia_attach_setup(sc, paa) 849 struct pccbb_softc *sc; 850 struct pcmciabus_attach_args *paa; 851 { 852 struct pcic_handle *ph = &sc->sc_pcmcia_h; 853 #if rbus 854 rbus_tag_t rb; 855 #endif 856 857 /* initialize pcmcia part in pccbb_softc */ 858 ph->ph_parent = (struct device *)sc; 859 ph->sock = sc->sc_function; 860 ph->flags = 0; 861 ph->shutdown = 0; 862 ph->ih_irq = sc->sc_pa.pa_intrline; 863 ph->ph_bus_t = sc->sc_base_memt; 864 ph->ph_bus_h = sc->sc_base_memh; 865 ph->ph_read = pccbb_pcmcia_read; 866 ph->ph_write = pccbb_pcmcia_write; 867 sc->sc_pct = &pccbb_pcmcia_funcs; 868 869 /* 870 * We need to do a few things here: 871 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 872 * setting the IRQ numbers to 0. 873 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 874 * routing of CSC interrupts (e.g. card removal) to PCI while in 875 * PCMCIA mode. We just leave this set all the time. 876 * 3) Enable card insertion/removal interrupts in case the chip also 877 * needs that while in PCMCIA mode. 878 * 4) Clear any pending CSC interrupt. 879 */ 880 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 881 if (sc->sc_chipset == CB_TI113X) { 882 Pcic_write(ph, PCIC_CSC_INTR, 0); 883 } else { 884 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 885 Pcic_read(ph, PCIC_CSC); 886 } 887 888 /* initialize pcmcia bus attachment */ 889 paa->paa_busname = "pcmcia"; 890 paa->pct = sc->sc_pct; 891 paa->pch = ph; 892 paa->iobase = 0; /* I don't use them */ 893 paa->iosize = 0; 894 #if rbus 895 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 896 paa->iobase = rb->rb_start + rb->rb_offset; 897 paa->iosize = rb->rb_end - rb->rb_start; 898 #endif 899 900 return; 901 } 902 903 #if 0 904 STATIC void 905 pccbb_pcmcia_attach_card(ph) 906 struct pcic_handle *ph; 907 { 908 if (ph->flags & PCIC_FLAG_CARDP) { 909 panic("pccbb_pcmcia_attach_card: already attached"); 910 } 911 912 /* call the MI attach function */ 913 pcmcia_card_attach(ph->pcmcia); 914 915 ph->flags |= PCIC_FLAG_CARDP; 916 } 917 918 STATIC void 919 pccbb_pcmcia_detach_card(ph, flags) 920 struct pcic_handle *ph; 921 int flags; 922 { 923 if (!(ph->flags & PCIC_FLAG_CARDP)) { 924 panic("pccbb_pcmcia_detach_card: already detached"); 925 } 926 927 ph->flags &= ~PCIC_FLAG_CARDP; 928 929 /* call the MI detach function */ 930 pcmcia_card_detach(ph->pcmcia, flags); 931 } 932 #endif 933 934 /* 935 * int pccbbintr(arg) 936 * void *arg; 937 * This routine handles the interrupt from Yenta PCI-CardBus bridge 938 * itself. 939 */ 940 int 941 pccbbintr(arg) 942 void *arg; 943 { 944 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 945 u_int32_t sockevent, sockstate; 946 bus_space_tag_t memt = sc->sc_base_memt; 947 bus_space_handle_t memh = sc->sc_base_memh; 948 struct pcic_handle *ph = &sc->sc_pcmcia_h; 949 950 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 951 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 952 Pcic_read(ph, PCIC_CSC); 953 954 if (sockevent == 0) { 955 /* This intr is not for me: it may be for my child devices. */ 956 if (sc->sc_pil_intr_enable) { 957 return pccbbintr_function(sc); 958 } else { 959 return 0; 960 } 961 } 962 963 if (sockevent & CB_SOCKET_EVENT_CD) { 964 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 965 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 966 /* A card should be removed. */ 967 if (sc->sc_flags & CBB_CARDEXIST) { 968 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 969 sockevent)); 970 DPRINTF((" card removed, 0x%08x\n", sockstate)); 971 sc->sc_flags &= ~CBB_CARDEXIST; 972 if (sc->sc_csc->sc_status & 973 CARDSLOT_STATUS_CARD_16) { 974 #if 0 975 struct pcic_handle *ph = 976 &sc->sc_pcmcia_h; 977 978 pcmcia_card_deactivate(ph->pcmcia); 979 pccbb_pcmcia_socket_disable(ph); 980 pccbb_pcmcia_detach_card(ph, 981 DETACH_FORCE); 982 #endif 983 cardslot_event_throw(sc->sc_csc, 984 CARDSLOT_EVENT_REMOVAL_16); 985 } else if (sc->sc_csc->sc_status & 986 CARDSLOT_STATUS_CARD_CB) { 987 /* Cardbus intr removed */ 988 cardslot_event_throw(sc->sc_csc, 989 CARDSLOT_EVENT_REMOVAL_CB); 990 } 991 } 992 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 993 /* 994 * The pccbbintr may called from powerdown hook when 995 * the system resumed, to detect the card 996 * insertion/removal during suspension. 997 */ 998 (sc->sc_flags & CBB_CARDEXIST) == 0) { 999 if (sc->sc_flags & CBB_INSERTING) { 1000 callout_stop(&sc->sc_insert_ch); 1001 } 1002 callout_reset(&sc->sc_insert_ch, hz / 10, 1003 pci113x_insert, sc); 1004 sc->sc_flags |= CBB_INSERTING; 1005 } 1006 } 1007 1008 return (1); 1009 } 1010 1011 /* 1012 * static int pccbbintr_function(struct pccbb_softc *sc) 1013 * 1014 * This function calls each interrupt handler registered at the 1015 * bridge. The interrupt handlers are called in registered order. 1016 */ 1017 static int 1018 pccbbintr_function(sc) 1019 struct pccbb_softc *sc; 1020 { 1021 int retval = 0, val; 1022 struct pccbb_intrhand_list *pil; 1023 int s, splchanged; 1024 1025 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1026 /* 1027 * XXX priority change. gross. I use if-else 1028 * sentense instead of switch-case sentense because of 1029 * avoiding duplicate case value error. More than one 1030 * IPL_XXX use same value. It depends on 1031 * implimentation. 1032 */ 1033 splchanged = 1; 1034 if (pil->pil_level == IPL_SERIAL) { 1035 s = splserial(); 1036 } else if (pil->pil_level == IPL_HIGH) { 1037 s = splhigh(); 1038 } else if (pil->pil_level == IPL_CLOCK) { 1039 s = splclock(); 1040 } else if (pil->pil_level == IPL_AUDIO) { 1041 s = splaudio(); 1042 } else if (pil->pil_level == IPL_IMP) { 1043 s = splimp(); 1044 } else if (pil->pil_level == IPL_TTY) { 1045 s = spltty(); 1046 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1047 s = splsoftserial(); 1048 } else if (pil->pil_level == IPL_NET) { 1049 s = splnet(); 1050 } else { 1051 splchanged = 0; 1052 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1053 } 1054 1055 val = (*pil->pil_func)(pil->pil_arg); 1056 1057 if (splchanged != 0) { 1058 splx(s); 1059 } 1060 1061 retval = retval == 1 ? 1 : 1062 retval == 0 ? val : val != 0 ? val : retval; 1063 } 1064 1065 return retval; 1066 } 1067 1068 static void 1069 pci113x_insert(arg) 1070 void *arg; 1071 { 1072 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1073 u_int32_t sockevent, sockstate; 1074 1075 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1076 CB_SOCKET_EVENT); 1077 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1078 CB_SOCKET_STAT); 1079 1080 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1081 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1082 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1083 sc->sc_flags |= CBB_CARDEXIST; 1084 /* call pccard interrupt handler here */ 1085 if (sockstate & CB_SOCKET_STAT_16BIT) { 1086 /* 16-bit card found */ 1087 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1088 cardslot_event_throw(sc->sc_csc, 1089 CARDSLOT_EVENT_INSERTION_16); 1090 } else if (sockstate & CB_SOCKET_STAT_CB) { 1091 /* cardbus card found */ 1092 /* cardbus_attach_card(sc->sc_csc); */ 1093 cardslot_event_throw(sc->sc_csc, 1094 CARDSLOT_EVENT_INSERTION_CB); 1095 } else { 1096 /* who are you? */ 1097 } 1098 } else { 1099 callout_reset(&sc->sc_insert_ch, hz / 10, 1100 pci113x_insert, sc); 1101 } 1102 } 1103 1104 #define PCCBB_PCMCIA_OFFSET 0x800 1105 static u_int8_t 1106 pccbb_pcmcia_read(ph, reg) 1107 struct pcic_handle *ph; 1108 int reg; 1109 { 1110 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1111 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1112 1113 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1114 PCCBB_PCMCIA_OFFSET + reg); 1115 } 1116 1117 static void 1118 pccbb_pcmcia_write(ph, reg, val) 1119 struct pcic_handle *ph; 1120 int reg; 1121 u_int8_t val; 1122 { 1123 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1124 val); 1125 1126 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1127 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1128 } 1129 1130 /* 1131 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1132 */ 1133 STATIC int 1134 pccbb_ctrl(ct, command) 1135 cardbus_chipset_tag_t ct; 1136 int command; 1137 { 1138 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1139 1140 switch (command) { 1141 case CARDBUS_CD: 1142 if (2 == pccbb_detect_card(sc)) { 1143 int retval = 0; 1144 int status = cb_detect_voltage(sc); 1145 if (PCCARD_VCC_5V & status) { 1146 retval |= CARDBUS_5V_CARD; 1147 } 1148 if (PCCARD_VCC_3V & status) { 1149 retval |= CARDBUS_3V_CARD; 1150 } 1151 if (PCCARD_VCC_XV & status) { 1152 retval |= CARDBUS_XV_CARD; 1153 } 1154 if (PCCARD_VCC_YV & status) { 1155 retval |= CARDBUS_YV_CARD; 1156 } 1157 return retval; 1158 } else { 1159 return 0; 1160 } 1161 break; 1162 case CARDBUS_RESET: 1163 return cb_reset(sc); 1164 break; 1165 case CARDBUS_IO_ENABLE: /* fallthrough */ 1166 case CARDBUS_IO_DISABLE: /* fallthrough */ 1167 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1168 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1169 case CARDBUS_BM_ENABLE: /* fallthrough */ 1170 case CARDBUS_BM_DISABLE: /* fallthrough */ 1171 return pccbb_cardenable(sc, command); 1172 break; 1173 } 1174 1175 return 0; 1176 } 1177 1178 /* 1179 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1180 * This function returns true when it succeeds and returns false when 1181 * it fails. 1182 */ 1183 STATIC int 1184 pccbb_power(ct, command) 1185 cardbus_chipset_tag_t ct; 1186 int command; 1187 { 1188 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1189 1190 u_int32_t status, sock_ctrl; 1191 bus_space_tag_t memt = sc->sc_base_memt; 1192 bus_space_handle_t memh = sc->sc_base_memh; 1193 1194 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1195 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1196 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1197 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1198 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1199 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1200 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1201 "UNKNOWN", 1202 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1203 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1204 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1205 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1206 "UNKNOWN", command)); 1207 1208 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1209 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1210 1211 switch (command & CARDBUS_VCCMASK) { 1212 case CARDBUS_VCC_UC: 1213 break; 1214 case CARDBUS_VCC_5V: 1215 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1216 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1217 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1218 } else { 1219 printf("%s: BAD voltage request: no 5 V card\n", 1220 sc->sc_dev.dv_xname); 1221 } 1222 break; 1223 case CARDBUS_VCC_3V: 1224 if (CB_SOCKET_STAT_3VCARD & status) { 1225 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1226 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1227 } else { 1228 printf("%s: BAD voltage request: no 3.3 V card\n", 1229 sc->sc_dev.dv_xname); 1230 } 1231 break; 1232 case CARDBUS_VCC_0V: 1233 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1234 break; 1235 default: 1236 return 0; /* power NEVER changed */ 1237 break; 1238 } 1239 1240 switch (command & CARDBUS_VPPMASK) { 1241 case CARDBUS_VPP_UC: 1242 break; 1243 case CARDBUS_VPP_0V: 1244 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1245 break; 1246 case CARDBUS_VPP_VCC: 1247 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1248 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1249 break; 1250 case CARDBUS_VPP_12V: 1251 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1252 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1253 break; 1254 } 1255 1256 #if 0 1257 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1258 #endif 1259 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1260 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1261 1262 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1263 printf 1264 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1265 sc->sc_dev.dv_xname, sock_ctrl, status); 1266 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1267 (command & CARDBUS_VCCMASK) == 1268 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1269 CARDBUS_VCCMASK) == 1270 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1271 CARDBUS_VCCMASK) == 1272 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1273 CARDBUS_VCCMASK) == 1274 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1275 CARDBUS_VCCMASK) == 1276 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1277 CARDBUS_VCCMASK) == 1278 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1279 (command & CARDBUS_VPPMASK) == 1280 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1281 CARDBUS_VPPMASK) == 1282 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1283 CARDBUS_VPPMASK) == 1284 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1285 CARDBUS_VPPMASK) == 1286 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1287 #if 0 1288 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1289 u_int32_t force = 1290 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1291 /* Reset Bad Vcc request */ 1292 force &= ~CB_SOCKET_FORCE_BADVCC; 1293 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1294 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1295 CB_SOCKET_STAT)); 1296 return 1; 1297 } 1298 #endif 1299 return 0; 1300 } 1301 1302 /* 1303 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1304 * time is 20 ms, some PC-Card bridge requires longer duration. 1305 */ 1306 DELAY_MS(300, sc); 1307 1308 return 1; /* power changed correctly */ 1309 } 1310 1311 #if defined CB_PCMCIA_POLL 1312 struct cb_poll_str { 1313 void *arg; 1314 int (*func) __P((void *)); 1315 int level; 1316 pccard_chipset_tag_t ct; 1317 int count; 1318 struct callout poll_ch; 1319 }; 1320 1321 static struct cb_poll_str cb_poll[10]; 1322 static int cb_poll_n = 0; 1323 1324 static void cb_pcmcia_poll __P((void *arg)); 1325 1326 static void 1327 cb_pcmcia_poll(arg) 1328 void *arg; 1329 { 1330 struct cb_poll_str *poll = arg; 1331 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1332 struct pccbb_softc *sc = psc->cpc_parent; 1333 int s; 1334 u_int32_t spsr; /* socket present-state reg */ 1335 1336 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1337 switch (poll->level) { 1338 case IPL_NET: 1339 s = splnet(); 1340 break; 1341 case IPL_BIO: 1342 s = splbio(); 1343 break; 1344 case IPL_TTY: /* fallthrough */ 1345 default: 1346 s = spltty(); 1347 break; 1348 } 1349 1350 spsr = 1351 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1352 CB_SOCKET_STAT); 1353 1354 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1355 if (!(spsr & 0x40)) { /* CINT low */ 1356 #else 1357 if (1) { 1358 #endif 1359 if ((*poll->func) (poll->arg) == 1) { 1360 ++poll->count; 1361 printf("intr: reported from poller, 0x%x\n", spsr); 1362 #if defined LEVEL2 1363 } else { 1364 printf("intr: miss! 0x%x\n", spsr); 1365 #endif 1366 } 1367 } 1368 splx(s); 1369 } 1370 #endif /* defined CB_PCMCIA_POLL */ 1371 1372 /* 1373 * static int pccbb_detect_card(struct pccbb_softc *sc) 1374 * return value: 0 if no card exists. 1375 * 1 if 16-bit card exists. 1376 * 2 if cardbus card exists. 1377 */ 1378 static int 1379 pccbb_detect_card(sc) 1380 struct pccbb_softc *sc; 1381 { 1382 bus_space_handle_t base_memh = sc->sc_base_memh; 1383 bus_space_tag_t base_memt = sc->sc_base_memt; 1384 u_int32_t sockstat = 1385 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1386 int retval = 0; 1387 1388 /* CD1 and CD2 asserted */ 1389 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1390 /* card must be present */ 1391 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1392 /* NOTACARD DEASSERTED */ 1393 if (CB_SOCKET_STAT_CB & sockstat) { 1394 /* CardBus mode */ 1395 retval = 2; 1396 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1397 /* 16-bit mode */ 1398 retval = 1; 1399 } 1400 } 1401 } 1402 return retval; 1403 } 1404 1405 /* 1406 * STATIC int cb_reset(struct pccbb_softc *sc) 1407 * This function resets CardBus card. 1408 */ 1409 STATIC int 1410 cb_reset(sc) 1411 struct pccbb_softc *sc; 1412 { 1413 /* 1414 * Reset Assert at least 20 ms 1415 * Some machines request longer duration. 1416 */ 1417 int reset_duration = 1418 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1419 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1420 1421 /* Reset bit Assert (bit 6 at 0x3E) */ 1422 bcr |= CB_BCR_RESET_ENABLE; 1423 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1424 DELAY_MS(reset_duration, sc); 1425 1426 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1427 /* Reset bit Deassert (bit 6 at 0x3E) */ 1428 bcr &= ~CB_BCR_RESET_ENABLE; 1429 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1430 DELAY_MS(reset_duration, sc); 1431 } 1432 /* No card found on the slot. Keep Reset. */ 1433 return 1; 1434 } 1435 1436 /* 1437 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1438 * This function detect card Voltage. 1439 */ 1440 STATIC int 1441 cb_detect_voltage(sc) 1442 struct pccbb_softc *sc; 1443 { 1444 u_int32_t psr; /* socket present-state reg */ 1445 bus_space_tag_t iot = sc->sc_base_memt; 1446 bus_space_handle_t ioh = sc->sc_base_memh; 1447 int vol = PCCARD_VCC_UKN; /* set 0 */ 1448 1449 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1450 1451 if (0x400u & psr) { 1452 vol |= PCCARD_VCC_5V; 1453 } 1454 if (0x800u & psr) { 1455 vol |= PCCARD_VCC_3V; 1456 } 1457 1458 return vol; 1459 } 1460 1461 STATIC int 1462 cbbprint(aux, pcic) 1463 void *aux; 1464 const char *pcic; 1465 { 1466 /* 1467 struct cbslot_attach_args *cba = aux; 1468 1469 if (cba->cba_slot >= 0) { 1470 printf(" slot %d", cba->cba_slot); 1471 } 1472 */ 1473 return UNCONF; 1474 } 1475 1476 /* 1477 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1478 * This function enables and disables the card 1479 */ 1480 STATIC int 1481 pccbb_cardenable(sc, function) 1482 struct pccbb_softc *sc; 1483 int function; 1484 { 1485 u_int32_t command = 1486 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1487 1488 DPRINTF(("pccbb_cardenable:")); 1489 switch (function) { 1490 case CARDBUS_IO_ENABLE: 1491 command |= PCI_COMMAND_IO_ENABLE; 1492 break; 1493 case CARDBUS_IO_DISABLE: 1494 command &= ~PCI_COMMAND_IO_ENABLE; 1495 break; 1496 case CARDBUS_MEM_ENABLE: 1497 command |= PCI_COMMAND_MEM_ENABLE; 1498 break; 1499 case CARDBUS_MEM_DISABLE: 1500 command &= ~PCI_COMMAND_MEM_ENABLE; 1501 break; 1502 case CARDBUS_BM_ENABLE: 1503 command |= PCI_COMMAND_MASTER_ENABLE; 1504 break; 1505 case CARDBUS_BM_DISABLE: 1506 command &= ~PCI_COMMAND_MASTER_ENABLE; 1507 break; 1508 default: 1509 return 0; 1510 } 1511 1512 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1513 DPRINTF((" command reg 0x%x\n", command)); 1514 return 1; 1515 } 1516 1517 #if !rbus 1518 /* 1519 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1520 */ 1521 static int 1522 pccbb_io_open(ct, win, start, end) 1523 cardbus_chipset_tag_t ct; 1524 int win; 1525 u_int32_t start, end; 1526 { 1527 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1528 int basereg; 1529 int limitreg; 1530 1531 if ((win < 0) || (win > 2)) { 1532 #if defined DIAGNOSTIC 1533 printf("cardbus_io_open: window out of range %d\n", win); 1534 #endif 1535 return 0; 1536 } 1537 1538 basereg = win * 8 + 0x2c; 1539 limitreg = win * 8 + 0x30; 1540 1541 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1542 start, basereg, end, limitreg)); 1543 1544 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1545 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1546 return 1; 1547 } 1548 1549 /* 1550 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1551 */ 1552 static int 1553 pccbb_io_close(ct, win) 1554 cardbus_chipset_tag_t ct; 1555 int win; 1556 { 1557 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1558 int basereg; 1559 int limitreg; 1560 1561 if ((win < 0) || (win > 2)) { 1562 #if defined DIAGNOSTIC 1563 printf("cardbus_io_close: window out of range %d\n", win); 1564 #endif 1565 return 0; 1566 } 1567 1568 basereg = win * 8 + 0x2c; 1569 limitreg = win * 8 + 0x30; 1570 1571 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1572 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1573 return 1; 1574 } 1575 1576 /* 1577 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1578 */ 1579 static int 1580 pccbb_mem_open(ct, win, start, end) 1581 cardbus_chipset_tag_t ct; 1582 int win; 1583 u_int32_t start, end; 1584 { 1585 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1586 int basereg; 1587 int limitreg; 1588 1589 if ((win < 0) || (win > 2)) { 1590 #if defined DIAGNOSTIC 1591 printf("cardbus_mem_open: window out of range %d\n", win); 1592 #endif 1593 return 0; 1594 } 1595 1596 basereg = win * 8 + 0x1c; 1597 limitreg = win * 8 + 0x20; 1598 1599 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1600 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1601 return 1; 1602 } 1603 1604 /* 1605 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1606 */ 1607 static int 1608 pccbb_mem_close(ct, win) 1609 cardbus_chipset_tag_t ct; 1610 int win; 1611 { 1612 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1613 int basereg; 1614 int limitreg; 1615 1616 if ((win < 0) || (win > 2)) { 1617 #if defined DIAGNOSTIC 1618 printf("cardbus_mem_close: window out of range %d\n", win); 1619 #endif 1620 return 0; 1621 } 1622 1623 basereg = win * 8 + 0x1c; 1624 limitreg = win * 8 + 0x20; 1625 1626 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1627 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1628 return 1; 1629 } 1630 #endif 1631 1632 /* 1633 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1634 * int irq, 1635 * int level, 1636 * int (* func) __P((void *)), 1637 * void *arg) 1638 * 1639 * This function registers an interrupt handler at the bridge, in 1640 * order not to call the interrupt handlers of child devices when 1641 * a card-deletion interrupt occurs. 1642 * 1643 * The arguments irq and level are not used. 1644 */ 1645 static void * 1646 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1647 cardbus_chipset_tag_t ct; 1648 int irq, level; 1649 int (*func) __P((void *)); 1650 void *arg; 1651 { 1652 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1653 1654 return pccbb_intr_establish(sc, irq, level, func, arg); 1655 } 1656 1657 1658 /* 1659 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1660 * void *ih) 1661 * 1662 * This function removes an interrupt handler pointed by ih. 1663 */ 1664 static void 1665 pccbb_cb_intr_disestablish(ct, ih) 1666 cardbus_chipset_tag_t ct; 1667 void *ih; 1668 { 1669 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1670 1671 pccbb_intr_disestablish(sc, ih); 1672 } 1673 1674 1675 /* 1676 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1677 * int irq, 1678 * int level, 1679 * int (* func) __P((void *)), 1680 * void *arg) 1681 * 1682 * This function registers an interrupt handler at the bridge, in 1683 * order not to call the interrupt handlers of child devices when 1684 * a card-deletion interrupt occurs. 1685 * 1686 * The arguments irq is not used because pccbb selects intr vector. 1687 */ 1688 static void * 1689 pccbb_intr_establish(sc, irq, level, func, arg) 1690 struct pccbb_softc *sc; 1691 int irq, level; 1692 int (*func) __P((void *)); 1693 void *arg; 1694 { 1695 struct pccbb_intrhand_list *pil, *newpil; 1696 pcireg_t reg; 1697 1698 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1699 1700 if (sc->sc_pil == NULL) { 1701 /* initialize bridge intr routing */ 1702 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1703 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1704 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1705 1706 switch (sc->sc_chipset) { 1707 case CB_TI113X: 1708 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1709 /* functional intr enabled */ 1710 reg |= PCI113X_CBCTRL_PCI_INTR; 1711 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1712 break; 1713 default: 1714 break; 1715 } 1716 } 1717 1718 /* 1719 * Allocate a room for interrupt handler structure. 1720 */ 1721 if (NULL == (newpil = 1722 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1723 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1724 return NULL; 1725 } 1726 1727 newpil->pil_func = func; 1728 newpil->pil_arg = arg; 1729 newpil->pil_level = level; 1730 newpil->pil_next = NULL; 1731 1732 if (sc->sc_pil == NULL) { 1733 sc->sc_pil = newpil; 1734 } else { 1735 for (pil = sc->sc_pil; pil->pil_next != NULL; 1736 pil = pil->pil_next); 1737 pil->pil_next = newpil; 1738 } 1739 1740 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1741 1742 return newpil; 1743 } 1744 1745 /* 1746 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1747 * void *ih) 1748 * 1749 * This function removes an interrupt handler pointed by ih. 1750 */ 1751 static void 1752 pccbb_intr_disestablish(sc, ih) 1753 struct pccbb_softc *sc; 1754 void *ih; 1755 { 1756 struct pccbb_intrhand_list *pil, **pil_prev; 1757 pcireg_t reg; 1758 1759 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1760 1761 pil_prev = &sc->sc_pil; 1762 1763 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1764 if (pil == ih) { 1765 *pil_prev = pil->pil_next; 1766 free(pil, M_DEVBUF); 1767 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1768 break; 1769 } 1770 pil_prev = &pil->pil_next; 1771 } 1772 1773 if (sc->sc_pil == NULL) { 1774 /* No interrupt handlers */ 1775 1776 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1777 1778 /* stop routing PCI intr */ 1779 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1780 reg |= CB_BCR_INTR_IREQ_ENABLE; 1781 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1782 1783 switch (sc->sc_chipset) { 1784 case CB_TI113X: 1785 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1786 /* functional intr disabled */ 1787 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1788 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1789 break; 1790 default: 1791 break; 1792 } 1793 } 1794 } 1795 1796 #if defined SHOW_REGS 1797 static void 1798 cb_show_regs(pc, tag, memt, memh) 1799 pci_chipset_tag_t pc; 1800 pcitag_t tag; 1801 bus_space_tag_t memt; 1802 bus_space_handle_t memh; 1803 { 1804 int i; 1805 printf("PCI config regs:"); 1806 for (i = 0; i < 0x50; i += 4) { 1807 if (i % 16 == 0) { 1808 printf("\n 0x%02x:", i); 1809 } 1810 printf(" %08x", pci_conf_read(pc, tag, i)); 1811 } 1812 for (i = 0x80; i < 0xb0; i += 4) { 1813 if (i % 16 == 0) { 1814 printf("\n 0x%02x:", i); 1815 } 1816 printf(" %08x", pci_conf_read(pc, tag, i)); 1817 } 1818 1819 if (memh == 0) { 1820 printf("\n"); 1821 return; 1822 } 1823 1824 printf("\nsocket regs:"); 1825 for (i = 0; i <= 0x10; i += 0x04) { 1826 printf(" %08x", bus_space_read_4(memt, memh, i)); 1827 } 1828 printf("\nExCA regs:"); 1829 for (i = 0; i < 0x08; ++i) { 1830 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1831 } 1832 printf("\n"); 1833 return; 1834 } 1835 #endif 1836 1837 /* 1838 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1839 * int busno, int devno, int function) 1840 * This is the function to make a tag to access config space of 1841 * a CardBus Card. It works same as pci_conf_read. 1842 */ 1843 static cardbustag_t 1844 pccbb_make_tag(cc, busno, devno, function) 1845 cardbus_chipset_tag_t cc; 1846 int busno, devno, function; 1847 { 1848 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1849 1850 return pci_make_tag(sc->sc_pc, busno, devno, function); 1851 } 1852 1853 static void 1854 pccbb_free_tag(cc, tag) 1855 cardbus_chipset_tag_t cc; 1856 cardbustag_t tag; 1857 { 1858 } 1859 1860 /* 1861 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1862 * cardbustag_t tag, int offset) 1863 * This is the function to read the config space of a CardBus Card. 1864 * It works same as pci_conf_read. 1865 */ 1866 static cardbusreg_t 1867 pccbb_conf_read(cc, tag, offset) 1868 cardbus_chipset_tag_t cc; 1869 cardbustag_t tag; 1870 int offset; /* register offset */ 1871 { 1872 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1873 1874 return pci_conf_read(sc->sc_pc, tag, offset); 1875 } 1876 1877 /* 1878 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1879 * int offs, cardbusreg_t val) 1880 * This is the function to write the config space of a CardBus Card. 1881 * It works same as pci_conf_write. 1882 */ 1883 static void 1884 pccbb_conf_write(cc, tag, reg, val) 1885 cardbus_chipset_tag_t cc; 1886 cardbustag_t tag; 1887 int reg; /* register offset */ 1888 cardbusreg_t val; 1889 { 1890 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1891 1892 pci_conf_write(sc->sc_pc, tag, reg, val); 1893 } 1894 1895 #if 0 1896 STATIC int 1897 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1898 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1899 int speed, int flags, 1900 bus_space_handle_t * iohp) 1901 #endif 1902 /* 1903 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1904 * bus_addr_t start, bus_size_t size, 1905 * bus_size_t align, 1906 * struct pcmcia_io_handle *pcihp 1907 * 1908 * This function only allocates I/O region for pccard. This function 1909 * never maps the allocated region to pccard I/O area. 1910 * 1911 * XXX: The interface of this function is not very good, I believe. 1912 */ 1913 STATIC int 1914 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1915 pcmcia_chipset_handle_t pch; 1916 bus_addr_t start; /* start address */ 1917 bus_size_t size; 1918 bus_size_t align; 1919 struct pcmcia_io_handle *pcihp; 1920 { 1921 struct pcic_handle *ph = (struct pcic_handle *)pch; 1922 bus_addr_t ioaddr; 1923 int flags = 0; 1924 bus_space_tag_t iot; 1925 bus_space_handle_t ioh; 1926 #if rbus 1927 rbus_tag_t rb; 1928 #endif 1929 if (align == 0) { 1930 align = size; /* XXX: funny??? */ 1931 } 1932 1933 /* 1934 * Allocate some arbitrary I/O space. 1935 */ 1936 1937 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1938 1939 #if rbus 1940 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1941 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1942 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1943 return 1; 1944 } 1945 #else 1946 if (start) { 1947 ioaddr = start; 1948 if (bus_space_map(iot, start, size, 0, &ioh)) { 1949 return 1; 1950 } 1951 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1952 (u_long) ioaddr, (u_long) size)); 1953 } else { 1954 flags |= PCMCIA_IO_ALLOCATED; 1955 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1956 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1957 size, align, 0, 0, &ioaddr, &ioh)) { 1958 /* No room be able to be get. */ 1959 return 1; 1960 } 1961 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1962 (u_long) ioaddr, (u_long) size)); 1963 } 1964 #endif 1965 1966 pcihp->iot = iot; 1967 pcihp->ioh = ioh; 1968 pcihp->addr = ioaddr; 1969 pcihp->size = size; 1970 pcihp->flags = flags; 1971 1972 return 0; 1973 } 1974 1975 /* 1976 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1977 * struct pcmcia_io_handle *pcihp) 1978 * 1979 * This function only frees I/O region for pccard. 1980 * 1981 * XXX: The interface of this function is not very good, I believe. 1982 */ 1983 void 1984 pccbb_pcmcia_io_free(pch, pcihp) 1985 pcmcia_chipset_handle_t pch; 1986 struct pcmcia_io_handle *pcihp; 1987 { 1988 #if !rbus 1989 bus_space_tag_t iot = pcihp->iot; 1990 #endif 1991 bus_space_handle_t ioh = pcihp->ioh; 1992 bus_size_t size = pcihp->size; 1993 1994 #if rbus 1995 struct pccbb_softc *sc = 1996 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1997 rbus_tag_t rb = sc->sc_rbus_iot; 1998 1999 rbus_space_free(rb, ioh, size, NULL); 2000 #else 2001 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2002 bus_space_free(iot, ioh, size); 2003 else 2004 bus_space_unmap(iot, ioh, size); 2005 #endif 2006 } 2007 2008 /* 2009 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2010 * bus_addr_t offset, bus_size_t size, 2011 * struct pcmcia_io_handle *pcihp, 2012 * int *windowp) 2013 * 2014 * This function maps the allocated I/O region to pccard. This function 2015 * never allocates any I/O region for pccard I/O area. I don't 2016 * understand why the original authors of pcmciabus separated alloc and 2017 * map. I believe the two must be unite. 2018 * 2019 * XXX: no wait timing control? 2020 */ 2021 int 2022 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2023 pcmcia_chipset_handle_t pch; 2024 int width; 2025 bus_addr_t offset; 2026 bus_size_t size; 2027 struct pcmcia_io_handle *pcihp; 2028 int *windowp; 2029 { 2030 struct pcic_handle *ph = (struct pcic_handle *)pch; 2031 bus_addr_t ioaddr = pcihp->addr + offset; 2032 int i, win; 2033 #if defined CBB_DEBUG 2034 static char *width_names[] = { "dynamic", "io8", "io16" }; 2035 #endif 2036 2037 /* Sanity check I/O handle. */ 2038 2039 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2040 panic("pccbb_pcmcia_io_map iot is bogus"); 2041 } 2042 2043 /* XXX Sanity check offset/size. */ 2044 2045 win = -1; 2046 for (i = 0; i < PCIC_IO_WINS; i++) { 2047 if ((ph->ioalloc & (1 << i)) == 0) { 2048 win = i; 2049 ph->ioalloc |= (1 << i); 2050 break; 2051 } 2052 } 2053 2054 if (win == -1) { 2055 return 1; 2056 } 2057 2058 *windowp = win; 2059 2060 /* XXX this is pretty gross */ 2061 2062 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2063 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2064 2065 /* XXX wtf is this doing here? */ 2066 2067 #if 0 2068 printf(" port 0x%lx", (u_long) ioaddr); 2069 if (size > 1) { 2070 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2071 } 2072 #endif 2073 2074 ph->io[win].addr = ioaddr; 2075 ph->io[win].size = size; 2076 ph->io[win].width = width; 2077 2078 /* actual dirty register-value changing in the function below. */ 2079 pccbb_pcmcia_do_io_map(ph, win); 2080 2081 return 0; 2082 } 2083 2084 /* 2085 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2086 * 2087 * This function changes register-value to map I/O region for pccard. 2088 */ 2089 static void 2090 pccbb_pcmcia_do_io_map(ph, win) 2091 struct pcic_handle *ph; 2092 int win; 2093 { 2094 static u_int8_t pcic_iowidth[3] = { 2095 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2096 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2097 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2098 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2099 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2100 }; 2101 2102 #define PCIC_SIA_START_LOW 0 2103 #define PCIC_SIA_START_HIGH 1 2104 #define PCIC_SIA_STOP_LOW 2 2105 #define PCIC_SIA_STOP_HIGH 3 2106 2107 int regbase_win = 0x8 + win * 0x04; 2108 u_int8_t ioctl, enable; 2109 2110 DPRINTF( 2111 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2112 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2113 ph->io[win].width * 8)); 2114 2115 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2116 ph->io[win].addr & 0xff); 2117 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2118 (ph->io[win].addr >> 8) & 0xff); 2119 2120 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2121 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2122 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2123 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2124 2125 ioctl = Pcic_read(ph, PCIC_IOCTL); 2126 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2127 switch (win) { 2128 case 0: 2129 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2130 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2131 PCIC_IOCTL_IO0_DATASIZE_MASK); 2132 ioctl |= pcic_iowidth[ph->io[win].width]; 2133 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2134 break; 2135 case 1: 2136 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2137 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2138 PCIC_IOCTL_IO1_DATASIZE_MASK); 2139 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2140 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2141 break; 2142 } 2143 Pcic_write(ph, PCIC_IOCTL, ioctl); 2144 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2145 #if defined CBB_DEBUG 2146 { 2147 u_int8_t start_low = 2148 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2149 u_int8_t start_high = 2150 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2151 u_int8_t stop_low = 2152 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2153 u_int8_t stop_high = 2154 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2155 printf 2156 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2157 start_low, start_high, stop_low, stop_high, ioctl, enable); 2158 } 2159 #endif 2160 } 2161 2162 /* 2163 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2164 * 2165 * This function unmaps I/O region. No return value. 2166 */ 2167 STATIC void 2168 pccbb_pcmcia_io_unmap(pch, win) 2169 pcmcia_chipset_handle_t pch; 2170 int win; 2171 { 2172 struct pcic_handle *ph = (struct pcic_handle *)pch; 2173 int reg; 2174 2175 if (win >= PCIC_IO_WINS || win < 0) { 2176 panic("pccbb_pcmcia_io_unmap: window out of range"); 2177 } 2178 2179 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2180 switch (win) { 2181 case 0: 2182 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2183 break; 2184 case 1: 2185 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2186 break; 2187 } 2188 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2189 2190 ph->ioalloc &= ~(1 << win); 2191 } 2192 2193 /* 2194 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2195 * 2196 * This function enables the card. All information is stored in 2197 * the first argument, pcmcia_chipset_handle_t. 2198 */ 2199 static void 2200 pccbb_pcmcia_wait_ready(ph) 2201 struct pcic_handle *ph; 2202 { 2203 int i; 2204 2205 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2206 Pcic_read(ph, PCIC_IF_STATUS))); 2207 2208 for (i = 0; i < 2000; i++) { 2209 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2210 return; 2211 } 2212 DELAY_MS(2, ph->ph_parent); 2213 #ifdef CBB_DEBUG 2214 if ((i > 1000) && (i % 25 == 24)) 2215 printf("."); 2216 #endif 2217 } 2218 2219 #ifdef DIAGNOSTIC 2220 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2221 Pcic_read(ph, PCIC_IF_STATUS)); 2222 #endif 2223 } 2224 2225 /* 2226 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2227 * 2228 * This function enables the card. All information is stored in 2229 * the first argument, pcmcia_chipset_handle_t. 2230 */ 2231 STATIC void 2232 pccbb_pcmcia_socket_enable(pch) 2233 pcmcia_chipset_handle_t pch; 2234 { 2235 struct pcic_handle *ph = (struct pcic_handle *)pch; 2236 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2237 int cardtype, win; 2238 u_int8_t power, intr; 2239 pcireg_t spsr; 2240 int voltage; 2241 2242 /* this bit is mostly stolen from pcic_attach_card */ 2243 2244 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2245 2246 /* get card Vcc info */ 2247 2248 spsr = 2249 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2250 CB_SOCKET_STAT); 2251 if (spsr & CB_SOCKET_STAT_5VCARD) { 2252 DPRINTF(("5V card\n")); 2253 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2254 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2255 DPRINTF(("3V card\n")); 2256 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2257 } else { 2258 printf("?V card, 0x%x\n", spsr); /* XXX */ 2259 return; 2260 } 2261 2262 /* disable socket: negate output enable bit and power off */ 2263 2264 power = 0; 2265 Pcic_write(ph, PCIC_PWRCTL, power); 2266 2267 /* power down the socket to reset it, clear the card reset pin */ 2268 2269 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2270 2271 /* 2272 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2273 * we are changing Vcc (Toff). 2274 */ 2275 /* delay(300*1000); too much */ 2276 2277 /* assert reset bit */ 2278 intr = Pcic_read(ph, PCIC_INTR); 2279 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2280 Pcic_write(ph, PCIC_INTR, intr); 2281 2282 /* power up the socket and output enable */ 2283 power = Pcic_read(ph, PCIC_PWRCTL); 2284 power |= PCIC_PWRCTL_OE; 2285 Pcic_write(ph, PCIC_PWRCTL, power); 2286 pccbb_power(sc, voltage); 2287 2288 /* 2289 * hold RESET at least 20 ms: the spec says only 10 us is 2290 * enough, but TI1130 requires at least 20 ms. 2291 */ 2292 DELAY_MS(20, sc); 2293 2294 /* clear the reset flag */ 2295 2296 intr |= PCIC_INTR_RESET; 2297 Pcic_write(ph, PCIC_INTR, intr); 2298 2299 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2300 2301 DELAY_MS(20, sc); 2302 2303 /* wait for the chip to finish initializing */ 2304 2305 pccbb_pcmcia_wait_ready(ph); 2306 2307 /* zero out the address windows */ 2308 2309 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2310 2311 /* set the card type */ 2312 2313 cardtype = pcmcia_card_gettype(ph->pcmcia); 2314 2315 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2316 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2317 Pcic_write(ph, PCIC_INTR, intr); 2318 2319 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2320 ph->ph_parent->dv_xname, ph->sock, 2321 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2322 2323 /* reinstall all the memory and io mappings */ 2324 2325 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2326 if (ph->memalloc & (1 << win)) { 2327 pccbb_pcmcia_do_mem_map(ph, win); 2328 } 2329 } 2330 2331 for (win = 0; win < PCIC_IO_WINS; ++win) { 2332 if (ph->ioalloc & (1 << win)) { 2333 pccbb_pcmcia_do_io_map(ph, win); 2334 } 2335 } 2336 } 2337 2338 /* 2339 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2340 * 2341 * This function disables the card. All information is stored in 2342 * the first argument, pcmcia_chipset_handle_t. 2343 */ 2344 STATIC void 2345 pccbb_pcmcia_socket_disable(pch) 2346 pcmcia_chipset_handle_t pch; 2347 { 2348 struct pcic_handle *ph = (struct pcic_handle *)pch; 2349 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2350 u_int8_t power, intr; 2351 2352 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2353 2354 /* reset signal asserting... */ 2355 2356 intr = Pcic_read(ph, PCIC_INTR); 2357 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2358 Pcic_write(ph, PCIC_INTR, intr); 2359 delay(2 * 1000); 2360 2361 /* power down the socket */ 2362 power = Pcic_read(ph, PCIC_PWRCTL); 2363 power &= ~PCIC_PWRCTL_OE; 2364 Pcic_write(ph, PCIC_PWRCTL, power); 2365 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2366 /* 2367 * wait 300ms until power fails (Tpf). 2368 */ 2369 DELAY_MS(300, sc); 2370 } 2371 2372 /* 2373 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2374 * 2375 * This function detects whether a card is in the slot or not. 2376 * If a card is inserted, return 1. Otherwise, return 0. 2377 */ 2378 STATIC int 2379 pccbb_pcmcia_card_detect(pch) 2380 pcmcia_chipset_handle_t pch; 2381 { 2382 struct pcic_handle *ph = (struct pcic_handle *)pch; 2383 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2384 2385 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2386 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2387 } 2388 2389 #if 0 2390 STATIC int 2391 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2392 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2393 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2394 #endif 2395 /* 2396 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2397 * bus_size_t size, 2398 * struct pcmcia_mem_handle *pcmhp) 2399 * 2400 * This function only allocates memory region for pccard. This 2401 * function never maps the allocated region to pccard memory area. 2402 * 2403 * XXX: Why the argument of start address is not in? 2404 */ 2405 STATIC int 2406 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2407 pcmcia_chipset_handle_t pch; 2408 bus_size_t size; 2409 struct pcmcia_mem_handle *pcmhp; 2410 { 2411 struct pcic_handle *ph = (struct pcic_handle *)pch; 2412 bus_space_handle_t memh; 2413 bus_addr_t addr; 2414 bus_size_t sizepg; 2415 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2416 #if rbus 2417 rbus_tag_t rb; 2418 #endif 2419 2420 /* out of sc->memh, allocate as many pages as necessary */ 2421 2422 /* convert size to PCIC pages */ 2423 /* 2424 * This is not enough; when the requested region is on the page 2425 * boundaries, this may calculate wrong result. 2426 */ 2427 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2428 #if 0 2429 if (sizepg > PCIC_MAX_MEM_PAGES) { 2430 return 1; 2431 } 2432 #endif 2433 2434 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2435 return 1; 2436 } 2437 2438 addr = 0; /* XXX gcc -Wuninitialized */ 2439 2440 #if rbus 2441 rb = sc->sc_rbus_memt; 2442 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2443 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2444 &addr, &memh)) { 2445 return 1; 2446 } 2447 #else 2448 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2449 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2450 0, /* boundary */ 2451 0, /* flags */ 2452 &addr, &memh)) { 2453 return 1; 2454 } 2455 #endif 2456 2457 DPRINTF( 2458 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2459 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2460 2461 pcmhp->memt = sc->sc_memt; 2462 pcmhp->memh = memh; 2463 pcmhp->addr = addr; 2464 pcmhp->size = size; 2465 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2466 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2467 pcmhp->mhandle = 0; 2468 /* No offset??? Funny. */ 2469 2470 return 0; 2471 } 2472 2473 /* 2474 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2475 * struct pcmcia_mem_handle *pcmhp) 2476 * 2477 * This function release the memory space allocated by the function 2478 * pccbb_pcmcia_mem_alloc(). 2479 */ 2480 STATIC void 2481 pccbb_pcmcia_mem_free(pch, pcmhp) 2482 pcmcia_chipset_handle_t pch; 2483 struct pcmcia_mem_handle *pcmhp; 2484 { 2485 #if rbus 2486 struct pcic_handle *ph = (struct pcic_handle *)pch; 2487 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2488 2489 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2490 #else 2491 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2492 #endif 2493 } 2494 2495 /* 2496 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2497 * 2498 * This function release the memory space allocated by the function 2499 * pccbb_pcmcia_mem_alloc(). 2500 */ 2501 STATIC void 2502 pccbb_pcmcia_do_mem_map(ph, win) 2503 struct pcic_handle *ph; 2504 int win; 2505 { 2506 int regbase_win; 2507 bus_addr_t phys_addr; 2508 bus_addr_t phys_end; 2509 2510 #define PCIC_SMM_START_LOW 0 2511 #define PCIC_SMM_START_HIGH 1 2512 #define PCIC_SMM_STOP_LOW 2 2513 #define PCIC_SMM_STOP_HIGH 3 2514 #define PCIC_CMA_LOW 4 2515 #define PCIC_CMA_HIGH 5 2516 2517 u_int8_t start_low, start_high = 0; 2518 u_int8_t stop_low, stop_high; 2519 u_int8_t off_low, off_high; 2520 u_int8_t mem_window; 2521 int reg; 2522 2523 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2524 int mem8 = 2525 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2526 || (kind == PCMCIA_MEM_ATTR); 2527 2528 regbase_win = 0x10 + win * 0x08; 2529 2530 phys_addr = ph->mem[win].addr; 2531 phys_end = phys_addr + ph->mem[win].size; 2532 2533 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2534 phys_addr, phys_end, ph->mem[win].offset)); 2535 2536 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2537 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2538 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2539 2540 /* bit 19:12 */ 2541 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2542 /* bit 23:20 and bit 7 on */ 2543 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2544 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2545 /* bit 31:24, for 32-bit address */ 2546 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2547 2548 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2549 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2550 2551 if (((struct pccbb_softc *)ph-> 2552 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2553 Pcic_write(ph, 0x40 + win, mem_window); 2554 } 2555 2556 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2557 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2558 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2559 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2560 2561 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2562 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2563 2564 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2565 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2566 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2567 | ((kind == PCMCIA_MEM_ATTR) ? 2568 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2569 2570 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2571 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2572 2573 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2574 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2575 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2576 2577 #if defined CBB_DEBUG 2578 { 2579 int r1, r2, r3, r4, r5, r6, r7 = 0; 2580 2581 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2582 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2583 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2584 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2585 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2586 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2587 if (((struct pccbb_softc *)(ph-> 2588 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2589 r7 = Pcic_read(ph, 0x40 + win); 2590 } 2591 2592 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2593 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2594 if (((struct pccbb_softc *)(ph-> 2595 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2596 DPRINTF((" %02x", r7)); 2597 } 2598 DPRINTF(("\n")); 2599 } 2600 #endif 2601 } 2602 2603 /* 2604 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2605 * bus_addr_t card_addr, bus_size_t size, 2606 * struct pcmcia_mem_handle *pcmhp, 2607 * bus_addr_t *offsetp, int *windowp) 2608 * 2609 * This function maps memory space allocated by the function 2610 * pccbb_pcmcia_mem_alloc(). 2611 */ 2612 STATIC int 2613 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2614 pcmcia_chipset_handle_t pch; 2615 int kind; 2616 bus_addr_t card_addr; 2617 bus_size_t size; 2618 struct pcmcia_mem_handle *pcmhp; 2619 bus_addr_t *offsetp; 2620 int *windowp; 2621 { 2622 struct pcic_handle *ph = (struct pcic_handle *)pch; 2623 bus_addr_t busaddr; 2624 long card_offset; 2625 int win; 2626 2627 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2628 if ((ph->memalloc & (1 << win)) == 0) { 2629 ph->memalloc |= (1 << win); 2630 break; 2631 } 2632 } 2633 2634 if (win == PCIC_MEM_WINS) { 2635 return 1; 2636 } 2637 2638 *windowp = win; 2639 2640 /* XXX this is pretty gross */ 2641 2642 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2643 panic("pccbb_pcmcia_mem_map memt is bogus"); 2644 } 2645 2646 busaddr = pcmhp->addr; 2647 2648 /* 2649 * compute the address offset to the pcmcia address space for the 2650 * pcic. this is intentionally signed. The masks and shifts below 2651 * will cause TRT to happen in the pcic registers. Deal with making 2652 * sure the address is aligned, and return the alignment offset. 2653 */ 2654 2655 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2656 card_addr -= *offsetp; 2657 2658 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2659 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2660 (u_long) card_addr)); 2661 2662 /* 2663 * include the offset in the size, and decrement size by one, since 2664 * the hw wants start/stop 2665 */ 2666 size += *offsetp - 1; 2667 2668 card_offset = (((long)card_addr) - ((long)busaddr)); 2669 2670 ph->mem[win].addr = busaddr; 2671 ph->mem[win].size = size; 2672 ph->mem[win].offset = card_offset; 2673 ph->mem[win].kind = kind; 2674 2675 pccbb_pcmcia_do_mem_map(ph, win); 2676 2677 return 0; 2678 } 2679 2680 /* 2681 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2682 * int window) 2683 * 2684 * This function unmaps memory space which mapped by the function 2685 * pccbb_pcmcia_mem_map(). 2686 */ 2687 STATIC void 2688 pccbb_pcmcia_mem_unmap(pch, window) 2689 pcmcia_chipset_handle_t pch; 2690 int window; 2691 { 2692 struct pcic_handle *ph = (struct pcic_handle *)pch; 2693 int reg; 2694 2695 if (window >= PCIC_MEM_WINS) { 2696 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2697 } 2698 2699 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2700 reg &= ~(1 << window); 2701 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2702 2703 ph->memalloc &= ~(1 << window); 2704 } 2705 2706 #if defined PCCBB_PCMCIA_POLL 2707 struct pccbb_poll_str { 2708 void *arg; 2709 int (*func) __P((void *)); 2710 int level; 2711 struct pcic_handle *ph; 2712 int count; 2713 int num; 2714 struct callout poll_ch; 2715 }; 2716 2717 static struct pccbb_poll_str pccbb_poll[10]; 2718 static int pccbb_poll_n = 0; 2719 2720 static void pccbb_pcmcia_poll __P((void *arg)); 2721 2722 static void 2723 pccbb_pcmcia_poll(arg) 2724 void *arg; 2725 { 2726 struct pccbb_poll_str *poll = arg; 2727 struct pcic_handle *ph = poll->ph; 2728 struct pccbb_softc *sc = ph->sc; 2729 int s; 2730 u_int32_t spsr; /* socket present-state reg */ 2731 2732 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2733 switch (poll->level) { 2734 case IPL_NET: 2735 s = splnet(); 2736 break; 2737 case IPL_BIO: 2738 s = splbio(); 2739 break; 2740 case IPL_TTY: /* fallthrough */ 2741 default: 2742 s = spltty(); 2743 break; 2744 } 2745 2746 spsr = 2747 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2748 CB_SOCKET_STAT); 2749 2750 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2751 if (!(spsr & 0x40)) /* CINT low */ 2752 #else 2753 if (1) 2754 #endif 2755 { 2756 if ((*poll->func) (poll->arg) > 0) { 2757 ++poll->count; 2758 // printf("intr: reported from poller, 0x%x\n", spsr); 2759 #if defined LEVEL2 2760 } else { 2761 printf("intr: miss! 0x%x\n", spsr); 2762 #endif 2763 } 2764 } 2765 splx(s); 2766 } 2767 #endif /* defined CB_PCMCIA_POLL */ 2768 2769 /* 2770 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2771 * struct pcmcia_function *pf, 2772 * int ipl, 2773 * int (*func)(void *), 2774 * void *arg); 2775 * 2776 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2777 */ 2778 STATIC void * 2779 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2780 pcmcia_chipset_handle_t pch; 2781 struct pcmcia_function *pf; 2782 int ipl; 2783 int (*func) __P((void *)); 2784 void *arg; 2785 { 2786 struct pcic_handle *ph = (struct pcic_handle *)pch; 2787 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2788 2789 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2790 /* what should I do? */ 2791 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2792 DPRINTF( 2793 ("%s does not provide edge nor pulse interrupt\n", 2794 sc->sc_dev.dv_xname)); 2795 return NULL; 2796 } 2797 /* 2798 * XXX Noooooo! The interrupt flag must set properly!! 2799 * dumb pcmcia driver!! 2800 */ 2801 } 2802 2803 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2804 } 2805 2806 /* 2807 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2808 * void *ih) 2809 * 2810 * This function disables PC-Card interrupt. 2811 */ 2812 STATIC void 2813 pccbb_pcmcia_intr_disestablish(pch, ih) 2814 pcmcia_chipset_handle_t pch; 2815 void *ih; 2816 { 2817 struct pcic_handle *ph = (struct pcic_handle *)pch; 2818 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2819 2820 pccbb_intr_disestablish(sc, ih); 2821 } 2822 2823 #if rbus 2824 /* 2825 * static int 2826 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2827 * bus_addr_t addr, bus_size_t size, 2828 * bus_addr_t mask, bus_size_t align, 2829 * int flags, bus_addr_t *addrp; 2830 * bus_space_handle_t *bshp) 2831 * 2832 * This function allocates a portion of memory or io space for 2833 * clients. This function is called from CardBus card drivers. 2834 */ 2835 static int 2836 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2837 cardbus_chipset_tag_t ct; 2838 rbus_tag_t rb; 2839 bus_addr_t addr; 2840 bus_size_t size; 2841 bus_addr_t mask; 2842 bus_size_t align; 2843 int flags; 2844 bus_addr_t *addrp; 2845 bus_space_handle_t *bshp; 2846 { 2847 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2848 2849 DPRINTF( 2850 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2851 addr, size, mask, align)); 2852 2853 if (align == 0) { 2854 align = size; 2855 } 2856 2857 if (rb->rb_bt == sc->sc_memt) { 2858 if (align < 16) { 2859 return 1; 2860 } 2861 } else if (rb->rb_bt == sc->sc_iot) { 2862 if (align < 4) { 2863 return 1; 2864 } 2865 /* XXX: hack for avoiding ISA image */ 2866 if (mask < 0x0100) { 2867 mask = 0x3ff; 2868 addr = 0x300; 2869 } 2870 2871 } else { 2872 DPRINTF( 2873 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2874 rb->rb_bt)); 2875 return 1; 2876 /* XXX: panic here? */ 2877 } 2878 2879 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2880 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2881 return 1; 2882 } 2883 2884 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2885 2886 return 0; 2887 } 2888 2889 /* 2890 * static int 2891 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2892 * bus_space_handle_t *bshp, bus_size_t size); 2893 * 2894 * This function is called from CardBus card drivers. 2895 */ 2896 static int 2897 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2898 cardbus_chipset_tag_t ct; 2899 rbus_tag_t rb; 2900 bus_space_handle_t bsh; 2901 bus_size_t size; 2902 { 2903 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2904 bus_space_tag_t bt = rb->rb_bt; 2905 2906 pccbb_close_win(sc, bt, bsh, size); 2907 2908 if (bt == sc->sc_memt) { 2909 } else if (bt == sc->sc_iot) { 2910 } else { 2911 return 1; 2912 /* XXX: panic here? */ 2913 } 2914 2915 return rbus_space_free(rb, bsh, size, NULL); 2916 } 2917 #endif /* rbus */ 2918 2919 #if rbus 2920 2921 static int 2922 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2923 struct pccbb_softc *sc; 2924 bus_space_tag_t bst; 2925 bus_addr_t addr; 2926 bus_size_t size; 2927 bus_space_handle_t bsh; 2928 int flags; 2929 { 2930 struct pccbb_win_chain_head *head; 2931 bus_addr_t align; 2932 2933 head = &sc->sc_iowindow; 2934 align = 0x04; 2935 if (sc->sc_memt == bst) { 2936 head = &sc->sc_memwindow; 2937 align = 0x1000; 2938 DPRINTF(("using memory window, %x %x %x\n\n", 2939 sc->sc_iot, sc->sc_memt, bst)); 2940 } 2941 2942 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2943 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2944 sc->sc_dev.dv_xname, 2945 (head == &sc->sc_memwindow) ? "mem" : "io"); 2946 } 2947 pccbb_winset(align, sc, bst); 2948 2949 return 0; 2950 } 2951 2952 static int 2953 pccbb_close_win(sc, bst, bsh, size) 2954 struct pccbb_softc *sc; 2955 bus_space_tag_t bst; 2956 bus_space_handle_t bsh; 2957 bus_size_t size; 2958 { 2959 struct pccbb_win_chain_head *head; 2960 bus_addr_t align; 2961 2962 head = &sc->sc_iowindow; 2963 align = 0x04; 2964 if (sc->sc_memt == bst) { 2965 head = &sc->sc_memwindow; 2966 align = 0x1000; 2967 } 2968 2969 if (pccbb_winlist_delete(head, bsh, size)) { 2970 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2971 sc->sc_dev.dv_xname, 2972 (head == &sc->sc_memwindow) ? "mem" : "io"); 2973 } 2974 pccbb_winset(align, sc, bst); 2975 2976 return 0; 2977 } 2978 2979 static int 2980 pccbb_winlist_insert(head, start, size, bsh, flags) 2981 struct pccbb_win_chain_head *head; 2982 bus_addr_t start; 2983 bus_size_t size; 2984 bus_space_handle_t bsh; 2985 int flags; 2986 { 2987 struct pccbb_win_chain *chainp, *elem; 2988 2989 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2990 M_NOWAIT)) == NULL) 2991 return (1); /* fail */ 2992 2993 elem->wc_start = start; 2994 elem->wc_end = start + (size - 1); 2995 elem->wc_handle = bsh; 2996 elem->wc_flags = flags; 2997 2998 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2999 chainp = TAILQ_NEXT(chainp, wc_list)) { 3000 if (chainp->wc_end < start) 3001 continue; 3002 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3003 return (0); 3004 } 3005 3006 TAILQ_INSERT_TAIL(head, elem, wc_list); 3007 return (0); 3008 } 3009 3010 static int 3011 pccbb_winlist_delete(head, bsh, size) 3012 struct pccbb_win_chain_head *head; 3013 bus_space_handle_t bsh; 3014 bus_size_t size; 3015 { 3016 struct pccbb_win_chain *chainp; 3017 3018 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3019 chainp = TAILQ_NEXT(chainp, wc_list)) { 3020 if (chainp->wc_handle != bsh) 3021 continue; 3022 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3023 printf("pccbb_winlist_delete: window 0x%lx size " 3024 "inconsistent: 0x%lx, 0x%lx\n", 3025 chainp->wc_start, 3026 chainp->wc_end - chainp->wc_start, 3027 size - 1); 3028 return 1; 3029 } 3030 3031 TAILQ_REMOVE(head, chainp, wc_list); 3032 free(chainp, M_DEVBUF); 3033 3034 return 0; 3035 } 3036 3037 return 1; /* fail: no candidate to remove */ 3038 } 3039 3040 static void 3041 pccbb_winset(align, sc, bst) 3042 bus_addr_t align; 3043 struct pccbb_softc *sc; 3044 bus_space_tag_t bst; 3045 { 3046 pci_chipset_tag_t pc; 3047 pcitag_t tag; 3048 bus_addr_t mask = ~(align - 1); 3049 struct { 3050 cardbusreg_t win_start; 3051 cardbusreg_t win_limit; 3052 int win_flags; 3053 } win[2]; 3054 struct pccbb_win_chain *chainp; 3055 int offs; 3056 3057 win[0].win_start = 0xffffffff; 3058 win[0].win_limit = 0; 3059 win[1].win_start = 0xffffffff; 3060 win[1].win_limit = 0; 3061 3062 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3063 offs = 0x2c; 3064 if (sc->sc_memt == bst) { 3065 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3066 offs = 0x1c; 3067 } 3068 3069 if (chainp != NULL) { 3070 win[0].win_start = chainp->wc_start & mask; 3071 win[0].win_limit = chainp->wc_end & mask; 3072 win[0].win_flags = chainp->wc_flags; 3073 chainp = TAILQ_NEXT(chainp, wc_list); 3074 } 3075 3076 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3077 if (win[1].win_start == 0xffffffff) { 3078 /* window 1 is not used */ 3079 if ((win[0].win_flags == chainp->wc_flags) && 3080 (win[0].win_limit + align >= 3081 (chainp->wc_start & mask))) { 3082 /* concatenate */ 3083 win[0].win_limit = chainp->wc_end & mask; 3084 } else { 3085 /* make new window */ 3086 win[1].win_start = chainp->wc_start & mask; 3087 win[1].win_limit = chainp->wc_end & mask; 3088 win[1].win_flags = chainp->wc_flags; 3089 } 3090 continue; 3091 } 3092 3093 /* Both windows are engaged. */ 3094 if (win[0].win_flags == win[1].win_flags) { 3095 /* same flags */ 3096 if (win[0].win_flags == chainp->wc_flags) { 3097 if (win[1].win_start - (win[0].win_limit + 3098 align) < 3099 (chainp->wc_start & mask) - 3100 ((chainp->wc_end & mask) + align)) { 3101 /* 3102 * merge window 0 and 1, and set win1 3103 * to chainp 3104 */ 3105 win[0].win_limit = win[1].win_limit; 3106 win[1].win_start = 3107 chainp->wc_start & mask; 3108 win[1].win_limit = 3109 chainp->wc_end & mask; 3110 } else { 3111 win[1].win_limit = 3112 chainp->wc_end & mask; 3113 } 3114 } else { 3115 /* different flags */ 3116 3117 /* concatenate win0 and win1 */ 3118 win[0].win_limit = win[1].win_limit; 3119 /* allocate win[1] to new space */ 3120 win[1].win_start = chainp->wc_start & mask; 3121 win[1].win_limit = chainp->wc_end & mask; 3122 win[1].win_flags = chainp->wc_flags; 3123 } 3124 } else { 3125 /* the flags of win[0] and win[1] is different */ 3126 if (win[0].win_flags == chainp->wc_flags) { 3127 win[0].win_limit = chainp->wc_end & mask; 3128 /* 3129 * XXX this creates overlapping windows, so 3130 * what should the poor bridge do if one is 3131 * cachable, and the other is not? 3132 */ 3133 printf("%s: overlapping windows\n", 3134 sc->sc_dev.dv_xname); 3135 } else { 3136 win[1].win_limit = chainp->wc_end & mask; 3137 } 3138 } 3139 } 3140 3141 pc = sc->sc_pc; 3142 tag = sc->sc_tag; 3143 pci_conf_write(pc, tag, offs, win[0].win_start); 3144 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3145 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3146 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3147 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3148 pci_conf_read(pc, tag, offs), 3149 pci_conf_read(pc, tag, offs + 4) + align, 3150 pci_conf_read(pc, tag, offs + 8), 3151 pci_conf_read(pc, tag, offs + 12) + align)); 3152 3153 if (bst == sc->sc_memt) { 3154 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3155 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3156 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3157 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3158 } 3159 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3160 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3161 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3162 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3163 } 3164 } 3165 } 3166 3167 #endif /* rbus */ 3168 3169 static void 3170 pccbb_powerhook(why, arg) 3171 int why; 3172 void *arg; 3173 { 3174 struct pccbb_softc *sc = arg; 3175 u_int32_t reg; 3176 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3177 bus_space_handle_t base_memh = sc->sc_base_memh; 3178 3179 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3180 3181 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3182 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3183 if (sc->sc_pil_intr_enable) { 3184 (void)pccbbintr_function(sc); 3185 } 3186 sc->sc_pil_intr_enable = 0; 3187 3188 /* ToDo: deactivate or suspend child devices */ 3189 3190 } 3191 3192 if (why == PWR_RESUME) { 3193 /* CSC Interrupt: Card detect interrupt on */ 3194 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3195 /* Card detect intr is turned on. */ 3196 reg |= CB_SOCKET_MASK_CD; 3197 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3198 /* reset interrupt */ 3199 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3200 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3201 3202 /* 3203 * check for card insertion or removal during suspend period. 3204 * XXX: the code can't cope with card swap (remove then 3205 * insert). how can we detect such situation? 3206 */ 3207 (void)pccbbintr(sc); 3208 3209 sc->sc_pil_intr_enable = 1; 3210 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3211 3212 /* ToDo: activate or wakeup child devices */ 3213 } 3214 } 3215
Indexes created Fri Sep 26 08:10:20 GMT 2025