pccbb.c revision 1.57
1 /* $NetBSD: pccbb.c,v 1.57 2001/02/09 10:41:50 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/reboot.h> /* for bootverbose */ 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 #include <sys/proc.h> 57 58 #include <machine/intr.h> 59 #include <machine/bus.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/pccbbreg.h> 66 67 #include <dev/cardbus/cardslotvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 71 #include <dev/pcmcia/pcmciareg.h> 72 #include <dev/pcmcia/pcmciavar.h> 73 74 #include <dev/ic/i82365reg.h> 75 #include <dev/ic/i82365var.h> 76 #include <dev/pci/pccbbvar.h> 77 78 #include "locators.h" 79 80 #ifndef __NetBSD_Version__ 81 struct cfdriver cbb_cd = { 82 NULL, "cbb", DV_DULL 83 }; 84 #endif 85 86 #if defined CBB_DEBUG 87 #define DPRINTF(x) printf x 88 #define STATIC 89 #else 90 #define DPRINTF(x) 91 #define STATIC static 92 #endif 93 94 /* 95 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 96 * if you want to wait more than 1 ms. 97 */ 98 #define DELAY_MS(time, param) \ 99 do { \ 100 if (cold == 0) { \ 101 int tick = (hz*(time))/1000; \ 102 \ 103 if (tick <= 1) { \ 104 tick = 2; \ 105 } \ 106 tsleep((void *)(param), PCATCH, "pccbb", tick); \ 107 } else { \ 108 delay((time)*1000); \ 109 } \ 110 } while (0) 111 112 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 113 void pccbbattach __P((struct device *, struct device *, void *)); 114 int pccbbintr __P((void *)); 115 static void pci113x_insert __P((void *)); 116 static int pccbbintr_function __P((struct pccbb_softc *)); 117 118 static int pccbb_detect_card __P((struct pccbb_softc *)); 119 120 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 121 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset __P((struct pccbb_softc *)); 126 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 127 STATIC int cbbprint __P((void *, const char *)); 128 129 static int cb_chipset __P((u_int32_t, int *)); 130 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 131 struct pcmciabus_attach_args *)); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 134 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 135 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 136 #endif 137 138 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 139 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 140 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 141 #if !rbus 142 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 143 u_int32_t)); 144 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 145 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 146 u_int32_t)); 147 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc)); 151 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 152 153 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc)); 155 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 156 157 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 158 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 159 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 160 int)); 161 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 162 cardbusreg_t)); 163 static void pccbb_chipinit __P((struct pccbb_softc *)); 164 165 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 166 struct pcmcia_mem_handle *)); 167 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 168 struct pcmcia_mem_handle *)); 169 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 171 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 172 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 173 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 174 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *)); 176 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *)); 178 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 179 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 180 struct pcmcia_function *, int, int (*)(void *), void *)); 181 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 182 void *)); 183 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 184 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 185 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 186 187 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 188 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 189 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 190 static void pccbb_powerhook __P((int, void *)); 191 192 /* bus-space allocation and deallocation functions */ 193 #if rbus 194 195 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 196 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 197 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 198 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 199 bus_space_handle_t, bus_size_t)); 200 201 #endif /* rbus */ 202 203 #if rbus 204 205 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 206 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 207 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_space_handle_t, bus_size_t)); 209 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 210 bus_size_t, bus_space_handle_t, int)); 211 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 212 bus_space_handle_t, bus_size_t)); 213 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 214 bus_space_tag_t)); 215 void pccbb_winlist_show(struct pccbb_win_chain *); 216 217 #endif /* rbus */ 218 219 /* for config_defer */ 220 static void pccbb_pci_callback __P((struct device *)); 221 222 #if defined SHOW_REGS 223 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 224 bus_space_tag_t memt, bus_space_handle_t memh)); 225 #endif 226 227 struct cfattach cbb_pci_ca = { 228 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 229 }; 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_card_detect 245 }; 246 247 #if rbus 248 static struct cardbus_functions pccbb_funcs = { 249 pccbb_rbus_cb_space_alloc, 250 pccbb_rbus_cb_space_free, 251 pccbb_cb_intr_establish, 252 pccbb_cb_intr_disestablish, 253 pccbb_ctrl, 254 pccbb_power, 255 pccbb_make_tag, 256 pccbb_free_tag, 257 pccbb_conf_read, 258 pccbb_conf_write, 259 }; 260 #else 261 static struct cardbus_functions pccbb_funcs = { 262 pccbb_ctrl, 263 pccbb_power, 264 pccbb_mem_open, 265 pccbb_mem_close, 266 pccbb_io_open, 267 pccbb_io_close, 268 pccbb_cb_intr_establish, 269 pccbb_cb_intr_disestablish, 270 pccbb_make_tag, 271 pccbb_conf_read, 272 pccbb_conf_write, 273 }; 274 #endif 275 276 int 277 pcicbbmatch(parent, match, aux) 278 struct device *parent; 279 struct cfdata *match; 280 void *aux; 281 { 282 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 283 284 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 285 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 286 PCI_INTERFACE(pa->pa_class) == 0) { 287 return 1; 288 } 289 290 return 0; 291 } 292 293 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 294 | ((prod) << PCI_PRODUCT_SHIFT)) 295 296 struct yenta_chipinfo { 297 pcireg_t yc_id; /* vendor tag | product tag */ 298 int yc_chiptype; 299 int yc_flags; 300 } yc_chipsets[] = { 301 /* Texas Instruments chips */ 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 327 /* Ricoh chips */ 328 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 329 PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 331 PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 339 PCCBB_PCMCIA_MEM_32}, 340 341 /* Toshiba products */ 342 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 343 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 345 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 347 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 349 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 350 351 /* Cirrus Logic products */ 352 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 353 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 355 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 356 357 /* sentinel, or Generic chip */ 358 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 359 }; 360 361 static int 362 cb_chipset(pci_id, flagp) 363 u_int32_t pci_id; 364 int *flagp; 365 { 366 struct yenta_chipinfo *yc; 367 368 /* Loop over except the last default entry. */ 369 for (yc = yc_chipsets; yc < yc_chipsets + 370 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 371 if (pci_id == yc->yc_id) 372 break; 373 374 if (flagp != NULL) 375 *flagp = yc->yc_flags; 376 377 return (yc->yc_chiptype); 378 } 379 380 static void 381 pccbb_shutdown(void *arg) 382 { 383 struct pccbb_softc *sc = arg; 384 pcireg_t command; 385 386 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 387 388 /* 389 * turn off power 390 * 391 * XXX - do not turn off power if chipset is TI 113X because 392 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 393 */ 394 if (sc->sc_chipset != CB_TI113X) { 395 pccbb_power((cardbus_chipset_tag_t)sc, 396 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 397 } 398 399 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 400 0); 401 402 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 403 404 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 405 PCI_COMMAND_MASTER_ENABLE); 406 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 407 408 } 409 410 void 411 pccbbattach(parent, self, aux) 412 struct device *parent; 413 struct device *self; 414 void *aux; 415 { 416 struct pccbb_softc *sc = (void *)self; 417 struct pci_attach_args *pa = aux; 418 pci_chipset_tag_t pc = pa->pa_pc; 419 pcireg_t busreg, reg, sock_base; 420 bus_addr_t sockbase; 421 char devinfo[256]; 422 int flags; 423 424 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 425 426 pci_devinfo(pa->pa_id, 0, 0, devinfo); 427 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 428 #ifdef CBB_DEBUG 429 printf(" (chipflags %x)", flags); 430 #endif 431 printf("\n"); 432 433 TAILQ_INIT(&sc->sc_memwindow); 434 TAILQ_INIT(&sc->sc_iowindow); 435 436 #if rbus 437 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 438 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 439 #endif /* rbus */ 440 441 sc->sc_base_memh = 0; 442 443 /* 444 * MAP socket registers and ExCA registers on memory-space 445 * When no valid address is set on socket base registers (on pci 446 * config space), get it not polite way. 447 */ 448 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 449 450 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 451 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 452 /* The address must be valid. */ 453 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 454 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 455 printf("%s: can't map socket base address 0x%x\n", 456 sc->sc_dev.dv_xname, sock_base); 457 /* 458 * I think it's funny: socket base registers must be 459 * mapped on memory space, but ... 460 */ 461 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 462 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 463 NULL)) { 464 printf("%s: can't map socket base address" 465 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 466 sockbase); 467 /* give up... allocate reg space via rbus. */ 468 sc->sc_base_memh = 0; 469 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 470 } 471 } else { 472 DPRINTF(("%s: socket base address 0x%lx\n", 473 sc->sc_dev.dv_xname, sockbase)); 474 } 475 } 476 477 sc->sc_mem_start = 0; /* XXX */ 478 sc->sc_mem_end = 0xffffffff; /* XXX */ 479 480 /* 481 * When interrupt isn't routed correctly, give up probing cbb and do 482 * not kill pcic-compatible port. 483 */ 484 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 485 printf("%s: NOT USED because of unconfigured interrupt\n", 486 sc->sc_dev.dv_xname); 487 return; 488 } 489 490 /* 491 * When bus number isn't set correctly, give up using 32-bit CardBus 492 * mode. 493 */ 494 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 495 #if notyet 496 if (((busreg >> 8) & 0xff) == 0) { 497 printf("%s: CardBus support disabled because of unconfigured bus number\n", 498 sc->sc_dev.dv_xname); 499 flags |= PCCBB_PCMCIA_16BITONLY; 500 } 501 #endif 502 503 /* pccbb_machdep.c end */ 504 505 #if defined CBB_DEBUG 506 { 507 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 508 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 509 intrname[pa->pa_intrpin], pa->pa_intrline); 510 } 511 #endif 512 513 /* setup softc */ 514 sc->sc_pc = pc; 515 sc->sc_iot = pa->pa_iot; 516 sc->sc_memt = pa->pa_memt; 517 sc->sc_dmat = pa->pa_dmat; 518 sc->sc_tag = pa->pa_tag; 519 sc->sc_function = pa->pa_function; 520 521 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 522 523 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 524 525 shutdownhook_establish(pccbb_shutdown, sc); 526 527 /* Disable legacy register mapping. */ 528 switch (sc->sc_chipset) { 529 case CB_RX5C46X: /* fallthrough */ 530 #if 0 531 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 532 case CB_RX5C47X: 533 #endif 534 /* 535 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 536 * cannot be disabled by substituting 0 into PCI_LEGACY 537 * register. Ricoh CardBus bridges have special bits on Bridge 538 * control reg (addr 0x3e on PCI config space). 539 */ 540 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 541 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 542 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 543 break; 544 545 default: 546 /* XXX I don't know proper way to kill legacy I/O. */ 547 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 548 break; 549 } 550 551 config_defer(self, pccbb_pci_callback); 552 } 553 554 555 556 557 /* 558 * static void pccbb_pci_callback(struct device *self) 559 * 560 * The actual attach routine: get memory space for YENTA register 561 * space, setup YENTA register and route interrupt. 562 * 563 * This function should be deferred because this device may obtain 564 * memory space dynamically. This function must avoid obtaining 565 * memory area which has already kept for another device. 566 */ 567 static void 568 pccbb_pci_callback(self) 569 struct device *self; 570 { 571 struct pccbb_softc *sc = (void *)self; 572 pci_chipset_tag_t pc = sc->sc_pc; 573 bus_space_tag_t base_memt; 574 bus_space_handle_t base_memh; 575 u_int32_t maskreg; 576 pci_intr_handle_t ih; 577 const char *intrstr = NULL; 578 bus_addr_t sockbase; 579 struct cbslot_attach_args cba; 580 struct pcmciabus_attach_args paa; 581 struct cardslot_attach_args caa; 582 struct cardslot_softc *csc; 583 584 if (0 == sc->sc_base_memh) { 585 /* The socket registers aren't mapped correctly. */ 586 #if rbus 587 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 588 (sc->sc_chipset == CB_RX5C47X 589 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 590 0, &sockbase, &sc->sc_base_memh)) { 591 return; 592 } 593 sc->sc_base_memt = sc->sc_memt; 594 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 595 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 596 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 597 PCI_SOCKBASE))); 598 #else 599 sc->sc_base_memt = sc->sc_memt; 600 #if !defined CBB_PCI_BASE 601 #define CBB_PCI_BASE 0x20000000 602 #endif 603 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 604 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 605 /* cannot allocate memory space */ 606 return; 607 } 608 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 609 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 610 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 611 sc->sc_tag, PCI_SOCKBASE))); 612 #endif 613 } 614 615 /* bus bridge initialization */ 616 pccbb_chipinit(sc); 617 618 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 619 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 620 621 /* CSC Interrupt: Card detect interrupt on */ 622 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 623 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 624 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 625 /* reset interrupt */ 626 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 627 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 628 629 /* clear data structure for child device interrupt handlers */ 630 sc->sc_pil = NULL; 631 sc->sc_pil_intr_enable = 1; 632 633 /* Map and establish the interrupt. */ 634 if (pci_intr_map(&sc->sc_pa, &ih)) { 635 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 636 return; 637 } 638 intrstr = pci_intr_string(pc, ih); 639 640 /* 641 * XXX pccbbintr should be called under the priority lower 642 * than any other hard interrputs. 643 */ 644 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 645 646 if (sc->sc_ih == NULL) { 647 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 648 if (intrstr != NULL) { 649 printf(" at %s", intrstr); 650 } 651 printf("\n"); 652 return; 653 } 654 655 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 656 powerhook_establish(pccbb_powerhook, sc); 657 658 { 659 u_int32_t sockstat = 660 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 661 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 662 sc->sc_flags |= CBB_CARDEXIST; 663 } 664 } 665 666 /* 667 * attach cardbus 668 */ 669 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 670 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 671 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 672 673 /* initialize cbslot_attach */ 674 cba.cba_busname = "cardbus"; 675 cba.cba_iot = sc->sc_iot; 676 cba.cba_memt = sc->sc_memt; 677 cba.cba_dmat = sc->sc_dmat; 678 cba.cba_bus = (busreg >> 8) & 0x0ff; 679 cba.cba_cc = (void *)sc; 680 cba.cba_cf = &pccbb_funcs; 681 cba.cba_intrline = sc->sc_pa.pa_intrline; 682 683 #if rbus 684 cba.cba_rbus_iot = sc->sc_rbus_iot; 685 cba.cba_rbus_memt = sc->sc_rbus_memt; 686 #endif 687 688 cba.cba_cacheline = PCI_CACHELINE(bhlc); 689 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 690 691 if (bootverbose) { 692 printf("%s: cacheline 0x%x lattimer 0x%x\n", 693 sc->sc_dev.dv_xname, cba.cba_cacheline, 694 cba.cba_lattimer); 695 printf("%s: bhlc 0x%x lscp 0x%x\n", 696 sc->sc_dev.dv_xname, bhlc, busreg); 697 } 698 #if defined SHOW_REGS 699 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 700 sc->sc_base_memh); 701 #endif 702 } 703 704 pccbb_pcmcia_attach_setup(sc, &paa); 705 caa.caa_cb_attach = NULL; 706 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 707 caa.caa_cb_attach = &cba; 708 } 709 caa.caa_16_attach = &paa; 710 caa.caa_ph = &sc->sc_pcmcia_h; 711 712 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 713 DPRINTF(("pccbbattach: found cardslot\n")); 714 sc->sc_csc = csc; 715 } 716 717 return; 718 } 719 720 721 722 723 724 /* 725 * static void pccbb_chipinit(struct pccbb_softc *sc) 726 * 727 * This function initialize YENTA chip registers listed below: 728 * 1) PCI command reg, 729 * 2) PCI and CardBus latency timer, 730 * 3) route PCI interrupt, 731 * 4) close all memory and io windows. 732 */ 733 static void 734 pccbb_chipinit(sc) 735 struct pccbb_softc *sc; 736 { 737 pci_chipset_tag_t pc = sc->sc_pc; 738 pcitag_t tag = sc->sc_tag; 739 pcireg_t reg; 740 741 /* 742 * Set PCI command reg. 743 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 744 */ 745 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 746 /* I believe it is harmless. */ 747 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 748 PCI_COMMAND_MASTER_ENABLE); 749 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 750 751 /* 752 * Set CardBus latency timer. 753 */ 754 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 755 if (PCI_CB_LATENCY(reg) < 0x20) { 756 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 757 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 758 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 759 } 760 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 761 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 762 763 /* 764 * Set PCI latency timer. 765 */ 766 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 767 if (PCI_LATTIMER(reg) < 0x10) { 768 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 769 reg |= (0x10 << PCI_LATTIMER_SHIFT); 770 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 771 } 772 DPRINTF(("PCI latency timer 0x%x (%x)\n", 773 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 774 775 776 /* Route functional interrupts to PCI. */ 777 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 778 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 779 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 780 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 781 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 782 783 switch (sc->sc_chipset) { 784 case CB_TI113X: 785 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 786 /* This bit is shared, but may read as 0 on some chips, so set 787 it explicitly on both functions. */ 788 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 789 /* CSC intr enable */ 790 reg |= PCI113X_CBCTRL_PCI_CSC; 791 /* functional intr prohibit | prohibit ISA routing */ 792 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 793 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 794 break; 795 796 case CB_TI12XX: 797 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 798 reg |= PCI12XX_SYSCTRL_VCCPROT; 799 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 800 break; 801 802 case CB_TOPIC95B: 803 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 804 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 805 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 806 807 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 808 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 809 sc->sc_dev.dv_xname, reg)); 810 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 811 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 812 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 813 DPRINTF(("0x%x\n", reg)); 814 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 815 break; 816 } 817 818 /* Close all memory and I/O windows. */ 819 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 820 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 821 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 822 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 823 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 824 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 825 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 826 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 827 828 /* reset 16-bit pcmcia bus */ 829 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 830 0x800 + PCIC_INTR, 831 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 832 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 833 834 /* turn of power */ 835 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 836 } 837 838 839 840 841 /* 842 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 843 * struct pcmciabus_attach_args *paa) 844 * 845 * This function attaches 16-bit PCcard bus. 846 */ 847 STATIC void 848 pccbb_pcmcia_attach_setup(sc, paa) 849 struct pccbb_softc *sc; 850 struct pcmciabus_attach_args *paa; 851 { 852 struct pcic_handle *ph = &sc->sc_pcmcia_h; 853 #if rbus 854 rbus_tag_t rb; 855 #endif 856 857 /* initialize pcmcia part in pccbb_softc */ 858 ph->ph_parent = (struct device *)sc; 859 ph->sock = sc->sc_function; 860 ph->flags = 0; 861 ph->shutdown = 0; 862 ph->ih_irq = sc->sc_pa.pa_intrline; 863 ph->ph_bus_t = sc->sc_base_memt; 864 ph->ph_bus_h = sc->sc_base_memh; 865 ph->ph_read = pccbb_pcmcia_read; 866 ph->ph_write = pccbb_pcmcia_write; 867 sc->sc_pct = &pccbb_pcmcia_funcs; 868 869 /* 870 * We need to do a few things here: 871 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 872 * setting the IRQ numbers to 0. 873 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 874 * routing of CSC interrupts (e.g. card removal) to PCI while in 875 * PCMCIA mode. We just leave this set all the time. 876 * 3) Enable card insertion/removal interrupts in case the chip also 877 * needs that while in PCMCIA mode. 878 * 4) Clear any pending CSC interrupt. 879 */ 880 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 881 if (sc->sc_chipset == CB_TI113X) { 882 Pcic_write(ph, PCIC_CSC_INTR, 0); 883 } else { 884 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 885 Pcic_read(ph, PCIC_CSC); 886 } 887 888 /* initialize pcmcia bus attachment */ 889 paa->paa_busname = "pcmcia"; 890 paa->pct = sc->sc_pct; 891 paa->pch = ph; 892 paa->iobase = 0; /* I don't use them */ 893 paa->iosize = 0; 894 #if rbus 895 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 896 paa->iobase = rb->rb_start + rb->rb_offset; 897 paa->iosize = rb->rb_end - rb->rb_start; 898 #endif 899 900 return; 901 } 902 903 #if 0 904 STATIC void 905 pccbb_pcmcia_attach_card(ph) 906 struct pcic_handle *ph; 907 { 908 if (ph->flags & PCIC_FLAG_CARDP) { 909 panic("pccbb_pcmcia_attach_card: already attached"); 910 } 911 912 /* call the MI attach function */ 913 pcmcia_card_attach(ph->pcmcia); 914 915 ph->flags |= PCIC_FLAG_CARDP; 916 } 917 918 STATIC void 919 pccbb_pcmcia_detach_card(ph, flags) 920 struct pcic_handle *ph; 921 int flags; 922 { 923 if (!(ph->flags & PCIC_FLAG_CARDP)) { 924 panic("pccbb_pcmcia_detach_card: already detached"); 925 } 926 927 ph->flags &= ~PCIC_FLAG_CARDP; 928 929 /* call the MI detach function */ 930 pcmcia_card_detach(ph->pcmcia, flags); 931 } 932 #endif 933 934 /* 935 * int pccbbintr(arg) 936 * void *arg; 937 * This routine handles the interrupt from Yenta PCI-CardBus bridge 938 * itself. 939 */ 940 int 941 pccbbintr(arg) 942 void *arg; 943 { 944 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 945 u_int32_t sockevent, sockstate; 946 bus_space_tag_t memt = sc->sc_base_memt; 947 bus_space_handle_t memh = sc->sc_base_memh; 948 struct pcic_handle *ph = &sc->sc_pcmcia_h; 949 950 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 951 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 952 Pcic_read(ph, PCIC_CSC); 953 954 if (sockevent == 0) { 955 /* This intr is not for me: it may be for my child devices. */ 956 if (sc->sc_pil_intr_enable) { 957 return pccbbintr_function(sc); 958 } else { 959 return 0; 960 } 961 } 962 963 if (sockevent & CB_SOCKET_EVENT_CD) { 964 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 965 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 966 /* A card should be removed. */ 967 if (sc->sc_flags & CBB_CARDEXIST) { 968 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 969 sockevent)); 970 DPRINTF((" card removed, 0x%08x\n", sockstate)); 971 sc->sc_flags &= ~CBB_CARDEXIST; 972 if (sc->sc_csc->sc_status & 973 CARDSLOT_STATUS_CARD_16) { 974 #if 0 975 struct pcic_handle *ph = 976 &sc->sc_pcmcia_h; 977 978 pcmcia_card_deactivate(ph->pcmcia); 979 pccbb_pcmcia_socket_disable(ph); 980 pccbb_pcmcia_detach_card(ph, 981 DETACH_FORCE); 982 #endif 983 cardslot_event_throw(sc->sc_csc, 984 CARDSLOT_EVENT_REMOVAL_16); 985 } else if (sc->sc_csc->sc_status & 986 CARDSLOT_STATUS_CARD_CB) { 987 /* Cardbus intr removed */ 988 cardslot_event_throw(sc->sc_csc, 989 CARDSLOT_EVENT_REMOVAL_CB); 990 } 991 } 992 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 993 /* 994 * The pccbbintr may called from powerdown hook when 995 * the system resumed, to detect the card 996 * insertion/removal during suspension. 997 */ 998 (sc->sc_flags & CBB_CARDEXIST) == 0) { 999 if (sc->sc_flags & CBB_INSERTING) { 1000 callout_stop(&sc->sc_insert_ch); 1001 } 1002 callout_reset(&sc->sc_insert_ch, hz / 10, 1003 pci113x_insert, sc); 1004 sc->sc_flags |= CBB_INSERTING; 1005 } 1006 } 1007 1008 return (1); 1009 } 1010 1011 /* 1012 * static int pccbbintr_function(struct pccbb_softc *sc) 1013 * 1014 * This function calls each interrupt handler registered at the 1015 * bridge. The interrupt handlers are called in registered order. 1016 */ 1017 static int 1018 pccbbintr_function(sc) 1019 struct pccbb_softc *sc; 1020 { 1021 int retval = 0, val; 1022 struct pccbb_intrhand_list *pil; 1023 int s, splchanged; 1024 1025 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1026 /* 1027 * XXX priority change. gross. I use if-else 1028 * sentense instead of switch-case sentense because of 1029 * avoiding duplicate case value error. More than one 1030 * IPL_XXX use same value. It depends on 1031 * implimentation. 1032 */ 1033 splchanged = 1; 1034 if (pil->pil_level == IPL_SERIAL) { 1035 s = splserial(); 1036 } else if (pil->pil_level == IPL_HIGH) { 1037 s = splhigh(); 1038 } else if (pil->pil_level == IPL_CLOCK) { 1039 s = splclock(); 1040 } else if (pil->pil_level == IPL_AUDIO) { 1041 s = splaudio(); 1042 } else if (pil->pil_level == IPL_IMP) { 1043 s = splimp(); 1044 } else if (pil->pil_level == IPL_TTY) { 1045 s = spltty(); 1046 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1047 s = splsoftserial(); 1048 } else if (pil->pil_level == IPL_NET) { 1049 s = splnet(); 1050 } else { 1051 splchanged = 0; 1052 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1053 } 1054 1055 val = (*pil->pil_func)(pil->pil_arg); 1056 1057 if (splchanged != 0) { 1058 splx(s); 1059 } 1060 1061 retval = retval == 1 ? 1 : 1062 retval == 0 ? val : val != 0 ? val : retval; 1063 } 1064 1065 return retval; 1066 } 1067 1068 static void 1069 pci113x_insert(arg) 1070 void *arg; 1071 { 1072 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1073 u_int32_t sockevent, sockstate; 1074 1075 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1076 CB_SOCKET_EVENT); 1077 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1078 CB_SOCKET_STAT); 1079 1080 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1081 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1082 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1083 sc->sc_flags |= CBB_CARDEXIST; 1084 /* call pccard interrupt handler here */ 1085 if (sockstate & CB_SOCKET_STAT_16BIT) { 1086 /* 16-bit card found */ 1087 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1088 cardslot_event_throw(sc->sc_csc, 1089 CARDSLOT_EVENT_INSERTION_16); 1090 } else if (sockstate & CB_SOCKET_STAT_CB) { 1091 /* cardbus card found */ 1092 /* cardbus_attach_card(sc->sc_csc); */ 1093 cardslot_event_throw(sc->sc_csc, 1094 CARDSLOT_EVENT_INSERTION_CB); 1095 } else { 1096 /* who are you? */ 1097 } 1098 } else { 1099 callout_reset(&sc->sc_insert_ch, hz / 10, 1100 pci113x_insert, sc); 1101 } 1102 } 1103 1104 #define PCCBB_PCMCIA_OFFSET 0x800 1105 static u_int8_t 1106 pccbb_pcmcia_read(ph, reg) 1107 struct pcic_handle *ph; 1108 int reg; 1109 { 1110 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1111 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1112 1113 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1114 PCCBB_PCMCIA_OFFSET + reg); 1115 } 1116 1117 static void 1118 pccbb_pcmcia_write(ph, reg, val) 1119 struct pcic_handle *ph; 1120 int reg; 1121 u_int8_t val; 1122 { 1123 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1124 val); 1125 1126 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1127 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1128 } 1129 1130 /* 1131 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1132 */ 1133 STATIC int 1134 pccbb_ctrl(ct, command) 1135 cardbus_chipset_tag_t ct; 1136 int command; 1137 { 1138 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1139 1140 switch (command) { 1141 case CARDBUS_CD: 1142 if (2 == pccbb_detect_card(sc)) { 1143 int retval = 0; 1144 int status = cb_detect_voltage(sc); 1145 if (PCCARD_VCC_5V & status) { 1146 retval |= CARDBUS_5V_CARD; 1147 } 1148 if (PCCARD_VCC_3V & status) { 1149 retval |= CARDBUS_3V_CARD; 1150 } 1151 if (PCCARD_VCC_XV & status) { 1152 retval |= CARDBUS_XV_CARD; 1153 } 1154 if (PCCARD_VCC_YV & status) { 1155 retval |= CARDBUS_YV_CARD; 1156 } 1157 return retval; 1158 } else { 1159 return 0; 1160 } 1161 break; 1162 case CARDBUS_RESET: 1163 return cb_reset(sc); 1164 break; 1165 case CARDBUS_IO_ENABLE: /* fallthrough */ 1166 case CARDBUS_IO_DISABLE: /* fallthrough */ 1167 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1168 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1169 case CARDBUS_BM_ENABLE: /* fallthrough */ 1170 case CARDBUS_BM_DISABLE: /* fallthrough */ 1171 return pccbb_cardenable(sc, command); 1172 break; 1173 } 1174 1175 return 0; 1176 } 1177 1178 /* 1179 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1180 * This function returns true when it succeeds and returns false when 1181 * it fails. 1182 */ 1183 STATIC int 1184 pccbb_power(ct, command) 1185 cardbus_chipset_tag_t ct; 1186 int command; 1187 { 1188 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1189 1190 u_int32_t status, sock_ctrl; 1191 bus_space_tag_t memt = sc->sc_base_memt; 1192 bus_space_handle_t memh = sc->sc_base_memh; 1193 1194 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1195 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1196 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1197 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1198 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1199 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1200 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1201 "UNKNOWN", 1202 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1203 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1204 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1205 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1206 "UNKNOWN", command)); 1207 1208 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1209 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1210 1211 switch (command & CARDBUS_VCCMASK) { 1212 case CARDBUS_VCC_UC: 1213 break; 1214 case CARDBUS_VCC_5V: 1215 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1216 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1217 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1218 } else { 1219 printf("%s: BAD voltage request: no 5 V card\n", 1220 sc->sc_dev.dv_xname); 1221 } 1222 break; 1223 case CARDBUS_VCC_3V: 1224 if (CB_SOCKET_STAT_3VCARD & status) { 1225 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1226 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1227 } else { 1228 printf("%s: BAD voltage request: no 3.3 V card\n", 1229 sc->sc_dev.dv_xname); 1230 } 1231 break; 1232 case CARDBUS_VCC_0V: 1233 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1234 break; 1235 default: 1236 return 0; /* power NEVER changed */ 1237 break; 1238 } 1239 1240 switch (command & CARDBUS_VPPMASK) { 1241 case CARDBUS_VPP_UC: 1242 break; 1243 case CARDBUS_VPP_0V: 1244 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1245 break; 1246 case CARDBUS_VPP_VCC: 1247 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1248 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1249 break; 1250 case CARDBUS_VPP_12V: 1251 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1252 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1253 break; 1254 } 1255 1256 #if 0 1257 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1258 #endif 1259 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1260 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1261 1262 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1263 printf 1264 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1265 sc->sc_dev.dv_xname, sock_ctrl, status); 1266 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1267 (command & CARDBUS_VCCMASK) == 1268 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1269 CARDBUS_VCCMASK) == 1270 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1271 CARDBUS_VCCMASK) == 1272 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1273 CARDBUS_VCCMASK) == 1274 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1275 CARDBUS_VCCMASK) == 1276 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1277 CARDBUS_VCCMASK) == 1278 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1279 (command & CARDBUS_VPPMASK) == 1280 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1281 CARDBUS_VPPMASK) == 1282 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1283 CARDBUS_VPPMASK) == 1284 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1285 CARDBUS_VPPMASK) == 1286 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1287 #if 0 1288 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1289 u_int32_t force = 1290 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1291 /* Reset Bad Vcc request */ 1292 force &= ~CB_SOCKET_FORCE_BADVCC; 1293 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1294 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1295 CB_SOCKET_STAT)); 1296 return 1; 1297 } 1298 #endif 1299 return 0; 1300 } 1301 1302 /* 1303 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1304 * time is 20 ms, some PC-Card bridge requires longer duration. 1305 */ 1306 #if 0 /* XXX called on interrupt context */ 1307 DELAY_MS(300, sc); 1308 #else 1309 delay(300 * 1000); 1310 #endif 1311 1312 return 1; /* power changed correctly */ 1313 } 1314 1315 #if defined CB_PCMCIA_POLL 1316 struct cb_poll_str { 1317 void *arg; 1318 int (*func) __P((void *)); 1319 int level; 1320 pccard_chipset_tag_t ct; 1321 int count; 1322 struct callout poll_ch; 1323 }; 1324 1325 static struct cb_poll_str cb_poll[10]; 1326 static int cb_poll_n = 0; 1327 1328 static void cb_pcmcia_poll __P((void *arg)); 1329 1330 static void 1331 cb_pcmcia_poll(arg) 1332 void *arg; 1333 { 1334 struct cb_poll_str *poll = arg; 1335 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1336 struct pccbb_softc *sc = psc->cpc_parent; 1337 int s; 1338 u_int32_t spsr; /* socket present-state reg */ 1339 1340 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1341 switch (poll->level) { 1342 case IPL_NET: 1343 s = splnet(); 1344 break; 1345 case IPL_BIO: 1346 s = splbio(); 1347 break; 1348 case IPL_TTY: /* fallthrough */ 1349 default: 1350 s = spltty(); 1351 break; 1352 } 1353 1354 spsr = 1355 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1356 CB_SOCKET_STAT); 1357 1358 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1359 if (!(spsr & 0x40)) { /* CINT low */ 1360 #else 1361 if (1) { 1362 #endif 1363 if ((*poll->func) (poll->arg) == 1) { 1364 ++poll->count; 1365 printf("intr: reported from poller, 0x%x\n", spsr); 1366 #if defined LEVEL2 1367 } else { 1368 printf("intr: miss! 0x%x\n", spsr); 1369 #endif 1370 } 1371 } 1372 splx(s); 1373 } 1374 #endif /* defined CB_PCMCIA_POLL */ 1375 1376 /* 1377 * static int pccbb_detect_card(struct pccbb_softc *sc) 1378 * return value: 0 if no card exists. 1379 * 1 if 16-bit card exists. 1380 * 2 if cardbus card exists. 1381 */ 1382 static int 1383 pccbb_detect_card(sc) 1384 struct pccbb_softc *sc; 1385 { 1386 bus_space_handle_t base_memh = sc->sc_base_memh; 1387 bus_space_tag_t base_memt = sc->sc_base_memt; 1388 u_int32_t sockstat = 1389 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1390 int retval = 0; 1391 1392 /* CD1 and CD2 asserted */ 1393 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1394 /* card must be present */ 1395 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1396 /* NOTACARD DEASSERTED */ 1397 if (CB_SOCKET_STAT_CB & sockstat) { 1398 /* CardBus mode */ 1399 retval = 2; 1400 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1401 /* 16-bit mode */ 1402 retval = 1; 1403 } 1404 } 1405 } 1406 return retval; 1407 } 1408 1409 /* 1410 * STATIC int cb_reset(struct pccbb_softc *sc) 1411 * This function resets CardBus card. 1412 */ 1413 STATIC int 1414 cb_reset(sc) 1415 struct pccbb_softc *sc; 1416 { 1417 /* 1418 * Reset Assert at least 20 ms 1419 * Some machines request longer duration. 1420 */ 1421 int reset_duration = 1422 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1423 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1424 1425 /* Reset bit Assert (bit 6 at 0x3E) */ 1426 bcr |= CB_BCR_RESET_ENABLE; 1427 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1428 DELAY_MS(reset_duration, sc); 1429 1430 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1431 /* Reset bit Deassert (bit 6 at 0x3E) */ 1432 bcr &= ~CB_BCR_RESET_ENABLE; 1433 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1434 DELAY_MS(reset_duration, sc); 1435 } 1436 /* No card found on the slot. Keep Reset. */ 1437 return 1; 1438 } 1439 1440 /* 1441 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1442 * This function detect card Voltage. 1443 */ 1444 STATIC int 1445 cb_detect_voltage(sc) 1446 struct pccbb_softc *sc; 1447 { 1448 u_int32_t psr; /* socket present-state reg */ 1449 bus_space_tag_t iot = sc->sc_base_memt; 1450 bus_space_handle_t ioh = sc->sc_base_memh; 1451 int vol = PCCARD_VCC_UKN; /* set 0 */ 1452 1453 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1454 1455 if (0x400u & psr) { 1456 vol |= PCCARD_VCC_5V; 1457 } 1458 if (0x800u & psr) { 1459 vol |= PCCARD_VCC_3V; 1460 } 1461 1462 return vol; 1463 } 1464 1465 STATIC int 1466 cbbprint(aux, pcic) 1467 void *aux; 1468 const char *pcic; 1469 { 1470 /* 1471 struct cbslot_attach_args *cba = aux; 1472 1473 if (cba->cba_slot >= 0) { 1474 printf(" slot %d", cba->cba_slot); 1475 } 1476 */ 1477 return UNCONF; 1478 } 1479 1480 /* 1481 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1482 * This function enables and disables the card 1483 */ 1484 STATIC int 1485 pccbb_cardenable(sc, function) 1486 struct pccbb_softc *sc; 1487 int function; 1488 { 1489 u_int32_t command = 1490 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1491 1492 DPRINTF(("pccbb_cardenable:")); 1493 switch (function) { 1494 case CARDBUS_IO_ENABLE: 1495 command |= PCI_COMMAND_IO_ENABLE; 1496 break; 1497 case CARDBUS_IO_DISABLE: 1498 command &= ~PCI_COMMAND_IO_ENABLE; 1499 break; 1500 case CARDBUS_MEM_ENABLE: 1501 command |= PCI_COMMAND_MEM_ENABLE; 1502 break; 1503 case CARDBUS_MEM_DISABLE: 1504 command &= ~PCI_COMMAND_MEM_ENABLE; 1505 break; 1506 case CARDBUS_BM_ENABLE: 1507 command |= PCI_COMMAND_MASTER_ENABLE; 1508 break; 1509 case CARDBUS_BM_DISABLE: 1510 command &= ~PCI_COMMAND_MASTER_ENABLE; 1511 break; 1512 default: 1513 return 0; 1514 } 1515 1516 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1517 DPRINTF((" command reg 0x%x\n", command)); 1518 return 1; 1519 } 1520 1521 #if !rbus 1522 /* 1523 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1524 */ 1525 static int 1526 pccbb_io_open(ct, win, start, end) 1527 cardbus_chipset_tag_t ct; 1528 int win; 1529 u_int32_t start, end; 1530 { 1531 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1532 int basereg; 1533 int limitreg; 1534 1535 if ((win < 0) || (win > 2)) { 1536 #if defined DIAGNOSTIC 1537 printf("cardbus_io_open: window out of range %d\n", win); 1538 #endif 1539 return 0; 1540 } 1541 1542 basereg = win * 8 + 0x2c; 1543 limitreg = win * 8 + 0x30; 1544 1545 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1546 start, basereg, end, limitreg)); 1547 1548 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1549 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1550 return 1; 1551 } 1552 1553 /* 1554 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1555 */ 1556 static int 1557 pccbb_io_close(ct, win) 1558 cardbus_chipset_tag_t ct; 1559 int win; 1560 { 1561 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1562 int basereg; 1563 int limitreg; 1564 1565 if ((win < 0) || (win > 2)) { 1566 #if defined DIAGNOSTIC 1567 printf("cardbus_io_close: window out of range %d\n", win); 1568 #endif 1569 return 0; 1570 } 1571 1572 basereg = win * 8 + 0x2c; 1573 limitreg = win * 8 + 0x30; 1574 1575 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1576 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1577 return 1; 1578 } 1579 1580 /* 1581 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1582 */ 1583 static int 1584 pccbb_mem_open(ct, win, start, end) 1585 cardbus_chipset_tag_t ct; 1586 int win; 1587 u_int32_t start, end; 1588 { 1589 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1590 int basereg; 1591 int limitreg; 1592 1593 if ((win < 0) || (win > 2)) { 1594 #if defined DIAGNOSTIC 1595 printf("cardbus_mem_open: window out of range %d\n", win); 1596 #endif 1597 return 0; 1598 } 1599 1600 basereg = win * 8 + 0x1c; 1601 limitreg = win * 8 + 0x20; 1602 1603 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1604 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1605 return 1; 1606 } 1607 1608 /* 1609 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1610 */ 1611 static int 1612 pccbb_mem_close(ct, win) 1613 cardbus_chipset_tag_t ct; 1614 int win; 1615 { 1616 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1617 int basereg; 1618 int limitreg; 1619 1620 if ((win < 0) || (win > 2)) { 1621 #if defined DIAGNOSTIC 1622 printf("cardbus_mem_close: window out of range %d\n", win); 1623 #endif 1624 return 0; 1625 } 1626 1627 basereg = win * 8 + 0x1c; 1628 limitreg = win * 8 + 0x20; 1629 1630 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1631 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1632 return 1; 1633 } 1634 #endif 1635 1636 /* 1637 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1638 * int irq, 1639 * int level, 1640 * int (* func) __P((void *)), 1641 * void *arg) 1642 * 1643 * This function registers an interrupt handler at the bridge, in 1644 * order not to call the interrupt handlers of child devices when 1645 * a card-deletion interrupt occurs. 1646 * 1647 * The arguments irq and level are not used. 1648 */ 1649 static void * 1650 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1651 cardbus_chipset_tag_t ct; 1652 int irq, level; 1653 int (*func) __P((void *)); 1654 void *arg; 1655 { 1656 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1657 1658 return pccbb_intr_establish(sc, irq, level, func, arg); 1659 } 1660 1661 1662 /* 1663 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1664 * void *ih) 1665 * 1666 * This function removes an interrupt handler pointed by ih. 1667 */ 1668 static void 1669 pccbb_cb_intr_disestablish(ct, ih) 1670 cardbus_chipset_tag_t ct; 1671 void *ih; 1672 { 1673 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1674 1675 pccbb_intr_disestablish(sc, ih); 1676 } 1677 1678 1679 /* 1680 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1681 * int irq, 1682 * int level, 1683 * int (* func) __P((void *)), 1684 * void *arg) 1685 * 1686 * This function registers an interrupt handler at the bridge, in 1687 * order not to call the interrupt handlers of child devices when 1688 * a card-deletion interrupt occurs. 1689 * 1690 * The arguments irq is not used because pccbb selects intr vector. 1691 */ 1692 static void * 1693 pccbb_intr_establish(sc, irq, level, func, arg) 1694 struct pccbb_softc *sc; 1695 int irq, level; 1696 int (*func) __P((void *)); 1697 void *arg; 1698 { 1699 struct pccbb_intrhand_list *pil, *newpil; 1700 pcireg_t reg; 1701 1702 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1703 1704 if (sc->sc_pil == NULL) { 1705 /* initialize bridge intr routing */ 1706 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1707 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1708 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1709 1710 switch (sc->sc_chipset) { 1711 case CB_TI113X: 1712 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1713 /* functional intr enabled */ 1714 reg |= PCI113X_CBCTRL_PCI_INTR; 1715 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1716 break; 1717 default: 1718 break; 1719 } 1720 } 1721 1722 /* 1723 * Allocate a room for interrupt handler structure. 1724 */ 1725 if (NULL == (newpil = 1726 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1727 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1728 return NULL; 1729 } 1730 1731 newpil->pil_func = func; 1732 newpil->pil_arg = arg; 1733 newpil->pil_level = level; 1734 newpil->pil_next = NULL; 1735 1736 if (sc->sc_pil == NULL) { 1737 sc->sc_pil = newpil; 1738 } else { 1739 for (pil = sc->sc_pil; pil->pil_next != NULL; 1740 pil = pil->pil_next); 1741 pil->pil_next = newpil; 1742 } 1743 1744 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1745 1746 return newpil; 1747 } 1748 1749 /* 1750 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1751 * void *ih) 1752 * 1753 * This function removes an interrupt handler pointed by ih. 1754 */ 1755 static void 1756 pccbb_intr_disestablish(sc, ih) 1757 struct pccbb_softc *sc; 1758 void *ih; 1759 { 1760 struct pccbb_intrhand_list *pil, **pil_prev; 1761 pcireg_t reg; 1762 1763 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1764 1765 pil_prev = &sc->sc_pil; 1766 1767 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1768 if (pil == ih) { 1769 *pil_prev = pil->pil_next; 1770 free(pil, M_DEVBUF); 1771 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1772 break; 1773 } 1774 pil_prev = &pil->pil_next; 1775 } 1776 1777 if (sc->sc_pil == NULL) { 1778 /* No interrupt handlers */ 1779 1780 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1781 1782 /* stop routing PCI intr */ 1783 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1784 reg |= CB_BCR_INTR_IREQ_ENABLE; 1785 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1786 1787 switch (sc->sc_chipset) { 1788 case CB_TI113X: 1789 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1790 /* functional intr disabled */ 1791 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1792 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1793 break; 1794 default: 1795 break; 1796 } 1797 } 1798 } 1799 1800 #if defined SHOW_REGS 1801 static void 1802 cb_show_regs(pc, tag, memt, memh) 1803 pci_chipset_tag_t pc; 1804 pcitag_t tag; 1805 bus_space_tag_t memt; 1806 bus_space_handle_t memh; 1807 { 1808 int i; 1809 printf("PCI config regs:"); 1810 for (i = 0; i < 0x50; i += 4) { 1811 if (i % 16 == 0) { 1812 printf("\n 0x%02x:", i); 1813 } 1814 printf(" %08x", pci_conf_read(pc, tag, i)); 1815 } 1816 for (i = 0x80; i < 0xb0; i += 4) { 1817 if (i % 16 == 0) { 1818 printf("\n 0x%02x:", i); 1819 } 1820 printf(" %08x", pci_conf_read(pc, tag, i)); 1821 } 1822 1823 if (memh == 0) { 1824 printf("\n"); 1825 return; 1826 } 1827 1828 printf("\nsocket regs:"); 1829 for (i = 0; i <= 0x10; i += 0x04) { 1830 printf(" %08x", bus_space_read_4(memt, memh, i)); 1831 } 1832 printf("\nExCA regs:"); 1833 for (i = 0; i < 0x08; ++i) { 1834 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1835 } 1836 printf("\n"); 1837 return; 1838 } 1839 #endif 1840 1841 /* 1842 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1843 * int busno, int devno, int function) 1844 * This is the function to make a tag to access config space of 1845 * a CardBus Card. It works same as pci_conf_read. 1846 */ 1847 static cardbustag_t 1848 pccbb_make_tag(cc, busno, devno, function) 1849 cardbus_chipset_tag_t cc; 1850 int busno, devno, function; 1851 { 1852 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1853 1854 return pci_make_tag(sc->sc_pc, busno, devno, function); 1855 } 1856 1857 static void 1858 pccbb_free_tag(cc, tag) 1859 cardbus_chipset_tag_t cc; 1860 cardbustag_t tag; 1861 { 1862 } 1863 1864 /* 1865 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1866 * cardbustag_t tag, int offset) 1867 * This is the function to read the config space of a CardBus Card. 1868 * It works same as pci_conf_read. 1869 */ 1870 static cardbusreg_t 1871 pccbb_conf_read(cc, tag, offset) 1872 cardbus_chipset_tag_t cc; 1873 cardbustag_t tag; 1874 int offset; /* register offset */ 1875 { 1876 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1877 1878 return pci_conf_read(sc->sc_pc, tag, offset); 1879 } 1880 1881 /* 1882 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1883 * int offs, cardbusreg_t val) 1884 * This is the function to write the config space of a CardBus Card. 1885 * It works same as pci_conf_write. 1886 */ 1887 static void 1888 pccbb_conf_write(cc, tag, reg, val) 1889 cardbus_chipset_tag_t cc; 1890 cardbustag_t tag; 1891 int reg; /* register offset */ 1892 cardbusreg_t val; 1893 { 1894 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1895 1896 pci_conf_write(sc->sc_pc, tag, reg, val); 1897 } 1898 1899 #if 0 1900 STATIC int 1901 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1902 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1903 int speed, int flags, 1904 bus_space_handle_t * iohp) 1905 #endif 1906 /* 1907 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1908 * bus_addr_t start, bus_size_t size, 1909 * bus_size_t align, 1910 * struct pcmcia_io_handle *pcihp 1911 * 1912 * This function only allocates I/O region for pccard. This function 1913 * never maps the allocated region to pccard I/O area. 1914 * 1915 * XXX: The interface of this function is not very good, I believe. 1916 */ 1917 STATIC int 1918 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1919 pcmcia_chipset_handle_t pch; 1920 bus_addr_t start; /* start address */ 1921 bus_size_t size; 1922 bus_size_t align; 1923 struct pcmcia_io_handle *pcihp; 1924 { 1925 struct pcic_handle *ph = (struct pcic_handle *)pch; 1926 bus_addr_t ioaddr; 1927 int flags = 0; 1928 bus_space_tag_t iot; 1929 bus_space_handle_t ioh; 1930 bus_addr_t mask; 1931 #if rbus 1932 rbus_tag_t rb; 1933 #endif 1934 if (align == 0) { 1935 align = size; /* XXX: funny??? */ 1936 } 1937 1938 if (start != 0) { 1939 /* XXX: assume all card decode lower 10 bits by its hardware */ 1940 mask = 0x3ff; 1941 } else { 1942 /* 1943 * calculate mask: 1944 * 1. get the most significant bit of size (call it msb). 1945 * 2. compare msb with the value of size. 1946 * 3. if size is larger, shift msb left once. 1947 * 4. obtain mask value to decrement msb. 1948 */ 1949 bus_size_t size_tmp = size; 1950 int shifts = 0; 1951 1952 mask = 1; 1953 while (size_tmp) { 1954 ++shifts; 1955 size_tmp >>= 1; 1956 } 1957 mask = (1 << shifts); 1958 if (mask < size) { 1959 mask <<= 1; 1960 } 1961 --mask; 1962 } 1963 1964 /* 1965 * Allocate some arbitrary I/O space. 1966 */ 1967 1968 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1969 1970 #if rbus 1971 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1972 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1973 return 1; 1974 } 1975 #else 1976 if (start) { 1977 ioaddr = start; 1978 if (bus_space_map(iot, start, size, 0, &ioh)) { 1979 return 1; 1980 } 1981 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1982 (u_long) ioaddr, (u_long) size)); 1983 } else { 1984 flags |= PCMCIA_IO_ALLOCATED; 1985 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1986 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1987 size, align, 0, 0, &ioaddr, &ioh)) { 1988 /* No room be able to be get. */ 1989 return 1; 1990 } 1991 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1992 (u_long) ioaddr, (u_long) size)); 1993 } 1994 #endif 1995 1996 pcihp->iot = iot; 1997 pcihp->ioh = ioh; 1998 pcihp->addr = ioaddr; 1999 pcihp->size = size; 2000 pcihp->flags = flags; 2001 2002 return 0; 2003 } 2004 2005 /* 2006 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2007 * struct pcmcia_io_handle *pcihp) 2008 * 2009 * This function only frees I/O region for pccard. 2010 * 2011 * XXX: The interface of this function is not very good, I believe. 2012 */ 2013 void 2014 pccbb_pcmcia_io_free(pch, pcihp) 2015 pcmcia_chipset_handle_t pch; 2016 struct pcmcia_io_handle *pcihp; 2017 { 2018 #if !rbus 2019 bus_space_tag_t iot = pcihp->iot; 2020 #endif 2021 bus_space_handle_t ioh = pcihp->ioh; 2022 bus_size_t size = pcihp->size; 2023 2024 #if rbus 2025 struct pccbb_softc *sc = 2026 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2027 rbus_tag_t rb = sc->sc_rbus_iot; 2028 2029 rbus_space_free(rb, ioh, size, NULL); 2030 #else 2031 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2032 bus_space_free(iot, ioh, size); 2033 else 2034 bus_space_unmap(iot, ioh, size); 2035 #endif 2036 } 2037 2038 /* 2039 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2040 * bus_addr_t offset, bus_size_t size, 2041 * struct pcmcia_io_handle *pcihp, 2042 * int *windowp) 2043 * 2044 * This function maps the allocated I/O region to pccard. This function 2045 * never allocates any I/O region for pccard I/O area. I don't 2046 * understand why the original authors of pcmciabus separated alloc and 2047 * map. I believe the two must be unite. 2048 * 2049 * XXX: no wait timing control? 2050 */ 2051 int 2052 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2053 pcmcia_chipset_handle_t pch; 2054 int width; 2055 bus_addr_t offset; 2056 bus_size_t size; 2057 struct pcmcia_io_handle *pcihp; 2058 int *windowp; 2059 { 2060 struct pcic_handle *ph = (struct pcic_handle *)pch; 2061 bus_addr_t ioaddr = pcihp->addr + offset; 2062 int i, win; 2063 #if defined CBB_DEBUG 2064 static char *width_names[] = { "dynamic", "io8", "io16" }; 2065 #endif 2066 2067 /* Sanity check I/O handle. */ 2068 2069 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2070 panic("pccbb_pcmcia_io_map iot is bogus"); 2071 } 2072 2073 /* XXX Sanity check offset/size. */ 2074 2075 win = -1; 2076 for (i = 0; i < PCIC_IO_WINS; i++) { 2077 if ((ph->ioalloc & (1 << i)) == 0) { 2078 win = i; 2079 ph->ioalloc |= (1 << i); 2080 break; 2081 } 2082 } 2083 2084 if (win == -1) { 2085 return 1; 2086 } 2087 2088 *windowp = win; 2089 2090 /* XXX this is pretty gross */ 2091 2092 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2093 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2094 2095 /* XXX wtf is this doing here? */ 2096 2097 #if 0 2098 printf(" port 0x%lx", (u_long) ioaddr); 2099 if (size > 1) { 2100 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2101 } 2102 #endif 2103 2104 ph->io[win].addr = ioaddr; 2105 ph->io[win].size = size; 2106 ph->io[win].width = width; 2107 2108 /* actual dirty register-value changing in the function below. */ 2109 pccbb_pcmcia_do_io_map(ph, win); 2110 2111 return 0; 2112 } 2113 2114 /* 2115 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2116 * 2117 * This function changes register-value to map I/O region for pccard. 2118 */ 2119 static void 2120 pccbb_pcmcia_do_io_map(ph, win) 2121 struct pcic_handle *ph; 2122 int win; 2123 { 2124 static u_int8_t pcic_iowidth[3] = { 2125 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2126 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2127 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2128 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2129 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2130 }; 2131 2132 #define PCIC_SIA_START_LOW 0 2133 #define PCIC_SIA_START_HIGH 1 2134 #define PCIC_SIA_STOP_LOW 2 2135 #define PCIC_SIA_STOP_HIGH 3 2136 2137 int regbase_win = 0x8 + win * 0x04; 2138 u_int8_t ioctl, enable; 2139 2140 DPRINTF( 2141 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2142 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2143 ph->io[win].width * 8)); 2144 2145 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2146 ph->io[win].addr & 0xff); 2147 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2148 (ph->io[win].addr >> 8) & 0xff); 2149 2150 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2151 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2152 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2153 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2154 2155 ioctl = Pcic_read(ph, PCIC_IOCTL); 2156 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2157 switch (win) { 2158 case 0: 2159 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2160 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2161 PCIC_IOCTL_IO0_DATASIZE_MASK); 2162 ioctl |= pcic_iowidth[ph->io[win].width]; 2163 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2164 break; 2165 case 1: 2166 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2167 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2168 PCIC_IOCTL_IO1_DATASIZE_MASK); 2169 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2170 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2171 break; 2172 } 2173 Pcic_write(ph, PCIC_IOCTL, ioctl); 2174 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2175 #if defined CBB_DEBUG 2176 { 2177 u_int8_t start_low = 2178 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2179 u_int8_t start_high = 2180 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2181 u_int8_t stop_low = 2182 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2183 u_int8_t stop_high = 2184 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2185 printf 2186 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2187 start_low, start_high, stop_low, stop_high, ioctl, enable); 2188 } 2189 #endif 2190 } 2191 2192 /* 2193 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2194 * 2195 * This function unmaps I/O region. No return value. 2196 */ 2197 STATIC void 2198 pccbb_pcmcia_io_unmap(pch, win) 2199 pcmcia_chipset_handle_t pch; 2200 int win; 2201 { 2202 struct pcic_handle *ph = (struct pcic_handle *)pch; 2203 int reg; 2204 2205 if (win >= PCIC_IO_WINS || win < 0) { 2206 panic("pccbb_pcmcia_io_unmap: window out of range"); 2207 } 2208 2209 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2210 switch (win) { 2211 case 0: 2212 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2213 break; 2214 case 1: 2215 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2216 break; 2217 } 2218 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2219 2220 ph->ioalloc &= ~(1 << win); 2221 } 2222 2223 /* 2224 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2225 * 2226 * This function enables the card. All information is stored in 2227 * the first argument, pcmcia_chipset_handle_t. 2228 */ 2229 static void 2230 pccbb_pcmcia_wait_ready(ph) 2231 struct pcic_handle *ph; 2232 { 2233 int i; 2234 2235 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2236 Pcic_read(ph, PCIC_IF_STATUS))); 2237 2238 for (i = 0; i < 2000; i++) { 2239 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2240 return; 2241 } 2242 DELAY_MS(2, ph->ph_parent); 2243 #ifdef CBB_DEBUG 2244 if ((i > 1000) && (i % 25 == 24)) 2245 printf("."); 2246 #endif 2247 } 2248 2249 #ifdef DIAGNOSTIC 2250 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2251 Pcic_read(ph, PCIC_IF_STATUS)); 2252 #endif 2253 } 2254 2255 /* 2256 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2257 * 2258 * This function enables the card. All information is stored in 2259 * the first argument, pcmcia_chipset_handle_t. 2260 */ 2261 STATIC void 2262 pccbb_pcmcia_socket_enable(pch) 2263 pcmcia_chipset_handle_t pch; 2264 { 2265 struct pcic_handle *ph = (struct pcic_handle *)pch; 2266 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2267 int cardtype, win; 2268 u_int8_t power, intr; 2269 pcireg_t spsr; 2270 int voltage; 2271 2272 /* this bit is mostly stolen from pcic_attach_card */ 2273 2274 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2275 2276 /* get card Vcc info */ 2277 2278 spsr = 2279 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2280 CB_SOCKET_STAT); 2281 if (spsr & CB_SOCKET_STAT_5VCARD) { 2282 DPRINTF(("5V card\n")); 2283 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2284 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2285 DPRINTF(("3V card\n")); 2286 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2287 } else { 2288 printf("?V card, 0x%x\n", spsr); /* XXX */ 2289 return; 2290 } 2291 2292 /* disable socket: negate output enable bit and power off */ 2293 2294 power = 0; 2295 Pcic_write(ph, PCIC_PWRCTL, power); 2296 2297 /* power down the socket to reset it, clear the card reset pin */ 2298 2299 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2300 2301 /* 2302 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2303 * we are changing Vcc (Toff). 2304 */ 2305 /* delay(300*1000); too much */ 2306 2307 /* assert reset bit */ 2308 intr = Pcic_read(ph, PCIC_INTR); 2309 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2310 Pcic_write(ph, PCIC_INTR, intr); 2311 2312 /* power up the socket and output enable */ 2313 power = Pcic_read(ph, PCIC_PWRCTL); 2314 power |= PCIC_PWRCTL_OE; 2315 Pcic_write(ph, PCIC_PWRCTL, power); 2316 pccbb_power(sc, voltage); 2317 2318 /* 2319 * hold RESET at least 20 ms: the spec says only 10 us is 2320 * enough, but TI1130 requires at least 20 ms. 2321 */ 2322 #if 0 /* XXX called on interrupt context */ 2323 DELAY_MS(20, sc); 2324 #else 2325 delay(20 * 1000); 2326 #endif 2327 2328 /* clear the reset flag */ 2329 2330 intr |= PCIC_INTR_RESET; 2331 Pcic_write(ph, PCIC_INTR, intr); 2332 2333 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2334 2335 #if 0 /* XXX called on interrupt context */ 2336 DELAY_MS(20, sc); 2337 #else 2338 delay(20 * 1000); 2339 #endif 2340 2341 /* wait for the chip to finish initializing */ 2342 2343 pccbb_pcmcia_wait_ready(ph); 2344 2345 /* zero out the address windows */ 2346 2347 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2348 2349 /* set the card type */ 2350 2351 cardtype = pcmcia_card_gettype(ph->pcmcia); 2352 2353 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2354 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2355 Pcic_write(ph, PCIC_INTR, intr); 2356 2357 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2358 ph->ph_parent->dv_xname, ph->sock, 2359 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2360 2361 /* reinstall all the memory and io mappings */ 2362 2363 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2364 if (ph->memalloc & (1 << win)) { 2365 pccbb_pcmcia_do_mem_map(ph, win); 2366 } 2367 } 2368 2369 for (win = 0; win < PCIC_IO_WINS; ++win) { 2370 if (ph->ioalloc & (1 << win)) { 2371 pccbb_pcmcia_do_io_map(ph, win); 2372 } 2373 } 2374 } 2375 2376 /* 2377 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2378 * 2379 * This function disables the card. All information is stored in 2380 * the first argument, pcmcia_chipset_handle_t. 2381 */ 2382 STATIC void 2383 pccbb_pcmcia_socket_disable(pch) 2384 pcmcia_chipset_handle_t pch; 2385 { 2386 struct pcic_handle *ph = (struct pcic_handle *)pch; 2387 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2388 u_int8_t power, intr; 2389 2390 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2391 2392 /* reset signal asserting... */ 2393 2394 intr = Pcic_read(ph, PCIC_INTR); 2395 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2396 Pcic_write(ph, PCIC_INTR, intr); 2397 delay(2 * 1000); 2398 2399 /* power down the socket */ 2400 power = Pcic_read(ph, PCIC_PWRCTL); 2401 power &= ~PCIC_PWRCTL_OE; 2402 Pcic_write(ph, PCIC_PWRCTL, power); 2403 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2404 /* 2405 * wait 300ms until power fails (Tpf). 2406 */ 2407 #if 0 /* XXX called on interrupt context */ 2408 DELAY_MS(300, sc); 2409 #else 2410 delay(300 * 1000); 2411 #endif 2412 } 2413 2414 /* 2415 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2416 * 2417 * This function detects whether a card is in the slot or not. 2418 * If a card is inserted, return 1. Otherwise, return 0. 2419 */ 2420 STATIC int 2421 pccbb_pcmcia_card_detect(pch) 2422 pcmcia_chipset_handle_t pch; 2423 { 2424 struct pcic_handle *ph = (struct pcic_handle *)pch; 2425 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2426 2427 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2428 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2429 } 2430 2431 #if 0 2432 STATIC int 2433 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2434 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2435 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2436 #endif 2437 /* 2438 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2439 * bus_size_t size, 2440 * struct pcmcia_mem_handle *pcmhp) 2441 * 2442 * This function only allocates memory region for pccard. This 2443 * function never maps the allocated region to pccard memory area. 2444 * 2445 * XXX: Why the argument of start address is not in? 2446 */ 2447 STATIC int 2448 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2449 pcmcia_chipset_handle_t pch; 2450 bus_size_t size; 2451 struct pcmcia_mem_handle *pcmhp; 2452 { 2453 struct pcic_handle *ph = (struct pcic_handle *)pch; 2454 bus_space_handle_t memh; 2455 bus_addr_t addr; 2456 bus_size_t sizepg; 2457 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2458 #if rbus 2459 rbus_tag_t rb; 2460 #endif 2461 2462 /* out of sc->memh, allocate as many pages as necessary */ 2463 2464 /* convert size to PCIC pages */ 2465 /* 2466 * This is not enough; when the requested region is on the page 2467 * boundaries, this may calculate wrong result. 2468 */ 2469 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2470 #if 0 2471 if (sizepg > PCIC_MAX_MEM_PAGES) { 2472 return 1; 2473 } 2474 #endif 2475 2476 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2477 return 1; 2478 } 2479 2480 addr = 0; /* XXX gcc -Wuninitialized */ 2481 2482 #if rbus 2483 rb = sc->sc_rbus_memt; 2484 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2485 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2486 &addr, &memh)) { 2487 return 1; 2488 } 2489 #else 2490 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2491 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2492 0, /* boundary */ 2493 0, /* flags */ 2494 &addr, &memh)) { 2495 return 1; 2496 } 2497 #endif 2498 2499 DPRINTF( 2500 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2501 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2502 2503 pcmhp->memt = sc->sc_memt; 2504 pcmhp->memh = memh; 2505 pcmhp->addr = addr; 2506 pcmhp->size = size; 2507 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2508 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2509 pcmhp->mhandle = 0; 2510 /* No offset??? Funny. */ 2511 2512 return 0; 2513 } 2514 2515 /* 2516 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2517 * struct pcmcia_mem_handle *pcmhp) 2518 * 2519 * This function release the memory space allocated by the function 2520 * pccbb_pcmcia_mem_alloc(). 2521 */ 2522 STATIC void 2523 pccbb_pcmcia_mem_free(pch, pcmhp) 2524 pcmcia_chipset_handle_t pch; 2525 struct pcmcia_mem_handle *pcmhp; 2526 { 2527 #if rbus 2528 struct pcic_handle *ph = (struct pcic_handle *)pch; 2529 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2530 2531 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2532 #else 2533 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2534 #endif 2535 } 2536 2537 /* 2538 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2539 * 2540 * This function release the memory space allocated by the function 2541 * pccbb_pcmcia_mem_alloc(). 2542 */ 2543 STATIC void 2544 pccbb_pcmcia_do_mem_map(ph, win) 2545 struct pcic_handle *ph; 2546 int win; 2547 { 2548 int regbase_win; 2549 bus_addr_t phys_addr; 2550 bus_addr_t phys_end; 2551 2552 #define PCIC_SMM_START_LOW 0 2553 #define PCIC_SMM_START_HIGH 1 2554 #define PCIC_SMM_STOP_LOW 2 2555 #define PCIC_SMM_STOP_HIGH 3 2556 #define PCIC_CMA_LOW 4 2557 #define PCIC_CMA_HIGH 5 2558 2559 u_int8_t start_low, start_high = 0; 2560 u_int8_t stop_low, stop_high; 2561 u_int8_t off_low, off_high; 2562 u_int8_t mem_window; 2563 int reg; 2564 2565 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2566 int mem8 = 2567 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2568 || (kind == PCMCIA_MEM_ATTR); 2569 2570 regbase_win = 0x10 + win * 0x08; 2571 2572 phys_addr = ph->mem[win].addr; 2573 phys_end = phys_addr + ph->mem[win].size; 2574 2575 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2576 phys_addr, phys_end, ph->mem[win].offset)); 2577 2578 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2579 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2580 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2581 2582 /* bit 19:12 */ 2583 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2584 /* bit 23:20 and bit 7 on */ 2585 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2586 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2587 /* bit 31:24, for 32-bit address */ 2588 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2589 2590 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2591 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2592 2593 if (((struct pccbb_softc *)ph-> 2594 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2595 Pcic_write(ph, 0x40 + win, mem_window); 2596 } 2597 2598 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2599 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2600 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2601 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2602 2603 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2604 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2605 2606 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2607 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2608 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2609 | ((kind == PCMCIA_MEM_ATTR) ? 2610 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2611 2612 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2613 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2614 2615 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2616 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2617 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2618 2619 #if defined CBB_DEBUG 2620 { 2621 int r1, r2, r3, r4, r5, r6, r7 = 0; 2622 2623 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2624 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2625 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2626 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2627 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2628 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2629 if (((struct pccbb_softc *)(ph-> 2630 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2631 r7 = Pcic_read(ph, 0x40 + win); 2632 } 2633 2634 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2635 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2636 if (((struct pccbb_softc *)(ph-> 2637 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2638 DPRINTF((" %02x", r7)); 2639 } 2640 DPRINTF(("\n")); 2641 } 2642 #endif 2643 } 2644 2645 /* 2646 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2647 * bus_addr_t card_addr, bus_size_t size, 2648 * struct pcmcia_mem_handle *pcmhp, 2649 * bus_addr_t *offsetp, int *windowp) 2650 * 2651 * This function maps memory space allocated by the function 2652 * pccbb_pcmcia_mem_alloc(). 2653 */ 2654 STATIC int 2655 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2656 pcmcia_chipset_handle_t pch; 2657 int kind; 2658 bus_addr_t card_addr; 2659 bus_size_t size; 2660 struct pcmcia_mem_handle *pcmhp; 2661 bus_addr_t *offsetp; 2662 int *windowp; 2663 { 2664 struct pcic_handle *ph = (struct pcic_handle *)pch; 2665 bus_addr_t busaddr; 2666 long card_offset; 2667 int win; 2668 2669 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2670 if ((ph->memalloc & (1 << win)) == 0) { 2671 ph->memalloc |= (1 << win); 2672 break; 2673 } 2674 } 2675 2676 if (win == PCIC_MEM_WINS) { 2677 return 1; 2678 } 2679 2680 *windowp = win; 2681 2682 /* XXX this is pretty gross */ 2683 2684 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2685 panic("pccbb_pcmcia_mem_map memt is bogus"); 2686 } 2687 2688 busaddr = pcmhp->addr; 2689 2690 /* 2691 * compute the address offset to the pcmcia address space for the 2692 * pcic. this is intentionally signed. The masks and shifts below 2693 * will cause TRT to happen in the pcic registers. Deal with making 2694 * sure the address is aligned, and return the alignment offset. 2695 */ 2696 2697 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2698 card_addr -= *offsetp; 2699 2700 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2701 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2702 (u_long) card_addr)); 2703 2704 /* 2705 * include the offset in the size, and decrement size by one, since 2706 * the hw wants start/stop 2707 */ 2708 size += *offsetp - 1; 2709 2710 card_offset = (((long)card_addr) - ((long)busaddr)); 2711 2712 ph->mem[win].addr = busaddr; 2713 ph->mem[win].size = size; 2714 ph->mem[win].offset = card_offset; 2715 ph->mem[win].kind = kind; 2716 2717 pccbb_pcmcia_do_mem_map(ph, win); 2718 2719 return 0; 2720 } 2721 2722 /* 2723 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2724 * int window) 2725 * 2726 * This function unmaps memory space which mapped by the function 2727 * pccbb_pcmcia_mem_map(). 2728 */ 2729 STATIC void 2730 pccbb_pcmcia_mem_unmap(pch, window) 2731 pcmcia_chipset_handle_t pch; 2732 int window; 2733 { 2734 struct pcic_handle *ph = (struct pcic_handle *)pch; 2735 int reg; 2736 2737 if (window >= PCIC_MEM_WINS) { 2738 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2739 } 2740 2741 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2742 reg &= ~(1 << window); 2743 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2744 2745 ph->memalloc &= ~(1 << window); 2746 } 2747 2748 #if defined PCCBB_PCMCIA_POLL 2749 struct pccbb_poll_str { 2750 void *arg; 2751 int (*func) __P((void *)); 2752 int level; 2753 struct pcic_handle *ph; 2754 int count; 2755 int num; 2756 struct callout poll_ch; 2757 }; 2758 2759 static struct pccbb_poll_str pccbb_poll[10]; 2760 static int pccbb_poll_n = 0; 2761 2762 static void pccbb_pcmcia_poll __P((void *arg)); 2763 2764 static void 2765 pccbb_pcmcia_poll(arg) 2766 void *arg; 2767 { 2768 struct pccbb_poll_str *poll = arg; 2769 struct pcic_handle *ph = poll->ph; 2770 struct pccbb_softc *sc = ph->sc; 2771 int s; 2772 u_int32_t spsr; /* socket present-state reg */ 2773 2774 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2775 switch (poll->level) { 2776 case IPL_NET: 2777 s = splnet(); 2778 break; 2779 case IPL_BIO: 2780 s = splbio(); 2781 break; 2782 case IPL_TTY: /* fallthrough */ 2783 default: 2784 s = spltty(); 2785 break; 2786 } 2787 2788 spsr = 2789 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2790 CB_SOCKET_STAT); 2791 2792 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2793 if (!(spsr & 0x40)) /* CINT low */ 2794 #else 2795 if (1) 2796 #endif 2797 { 2798 if ((*poll->func) (poll->arg) > 0) { 2799 ++poll->count; 2800 // printf("intr: reported from poller, 0x%x\n", spsr); 2801 #if defined LEVEL2 2802 } else { 2803 printf("intr: miss! 0x%x\n", spsr); 2804 #endif 2805 } 2806 } 2807 splx(s); 2808 } 2809 #endif /* defined CB_PCMCIA_POLL */ 2810 2811 /* 2812 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2813 * struct pcmcia_function *pf, 2814 * int ipl, 2815 * int (*func)(void *), 2816 * void *arg); 2817 * 2818 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2819 */ 2820 STATIC void * 2821 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2822 pcmcia_chipset_handle_t pch; 2823 struct pcmcia_function *pf; 2824 int ipl; 2825 int (*func) __P((void *)); 2826 void *arg; 2827 { 2828 struct pcic_handle *ph = (struct pcic_handle *)pch; 2829 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2830 2831 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2832 /* what should I do? */ 2833 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2834 DPRINTF( 2835 ("%s does not provide edge nor pulse interrupt\n", 2836 sc->sc_dev.dv_xname)); 2837 return NULL; 2838 } 2839 /* 2840 * XXX Noooooo! The interrupt flag must set properly!! 2841 * dumb pcmcia driver!! 2842 */ 2843 } 2844 2845 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2846 } 2847 2848 /* 2849 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2850 * void *ih) 2851 * 2852 * This function disables PC-Card interrupt. 2853 */ 2854 STATIC void 2855 pccbb_pcmcia_intr_disestablish(pch, ih) 2856 pcmcia_chipset_handle_t pch; 2857 void *ih; 2858 { 2859 struct pcic_handle *ph = (struct pcic_handle *)pch; 2860 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2861 2862 pccbb_intr_disestablish(sc, ih); 2863 } 2864 2865 #if rbus 2866 /* 2867 * static int 2868 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2869 * bus_addr_t addr, bus_size_t size, 2870 * bus_addr_t mask, bus_size_t align, 2871 * int flags, bus_addr_t *addrp; 2872 * bus_space_handle_t *bshp) 2873 * 2874 * This function allocates a portion of memory or io space for 2875 * clients. This function is called from CardBus card drivers. 2876 */ 2877 static int 2878 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2879 cardbus_chipset_tag_t ct; 2880 rbus_tag_t rb; 2881 bus_addr_t addr; 2882 bus_size_t size; 2883 bus_addr_t mask; 2884 bus_size_t align; 2885 int flags; 2886 bus_addr_t *addrp; 2887 bus_space_handle_t *bshp; 2888 { 2889 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2890 2891 DPRINTF( 2892 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2893 addr, size, mask, align)); 2894 2895 if (align == 0) { 2896 align = size; 2897 } 2898 2899 if (rb->rb_bt == sc->sc_memt) { 2900 if (align < 16) { 2901 return 1; 2902 } 2903 } else if (rb->rb_bt == sc->sc_iot) { 2904 if (align < 4) { 2905 return 1; 2906 } 2907 /* XXX: hack for avoiding ISA image */ 2908 if (mask < 0x0100) { 2909 mask = 0x3ff; 2910 addr = 0x300; 2911 } 2912 2913 } else { 2914 DPRINTF( 2915 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2916 rb->rb_bt)); 2917 return 1; 2918 /* XXX: panic here? */ 2919 } 2920 2921 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2922 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2923 return 1; 2924 } 2925 2926 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2927 2928 return 0; 2929 } 2930 2931 /* 2932 * static int 2933 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2934 * bus_space_handle_t *bshp, bus_size_t size); 2935 * 2936 * This function is called from CardBus card drivers. 2937 */ 2938 static int 2939 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2940 cardbus_chipset_tag_t ct; 2941 rbus_tag_t rb; 2942 bus_space_handle_t bsh; 2943 bus_size_t size; 2944 { 2945 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2946 bus_space_tag_t bt = rb->rb_bt; 2947 2948 pccbb_close_win(sc, bt, bsh, size); 2949 2950 if (bt == sc->sc_memt) { 2951 } else if (bt == sc->sc_iot) { 2952 } else { 2953 return 1; 2954 /* XXX: panic here? */ 2955 } 2956 2957 return rbus_space_free(rb, bsh, size, NULL); 2958 } 2959 #endif /* rbus */ 2960 2961 #if rbus 2962 2963 static int 2964 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2965 struct pccbb_softc *sc; 2966 bus_space_tag_t bst; 2967 bus_addr_t addr; 2968 bus_size_t size; 2969 bus_space_handle_t bsh; 2970 int flags; 2971 { 2972 struct pccbb_win_chain_head *head; 2973 bus_addr_t align; 2974 2975 head = &sc->sc_iowindow; 2976 align = 0x04; 2977 if (sc->sc_memt == bst) { 2978 head = &sc->sc_memwindow; 2979 align = 0x1000; 2980 DPRINTF(("using memory window, %x %x %x\n\n", 2981 sc->sc_iot, sc->sc_memt, bst)); 2982 } 2983 2984 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2985 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2986 sc->sc_dev.dv_xname, 2987 (head == &sc->sc_memwindow) ? "mem" : "io"); 2988 } 2989 pccbb_winset(align, sc, bst); 2990 2991 return 0; 2992 } 2993 2994 static int 2995 pccbb_close_win(sc, bst, bsh, size) 2996 struct pccbb_softc *sc; 2997 bus_space_tag_t bst; 2998 bus_space_handle_t bsh; 2999 bus_size_t size; 3000 { 3001 struct pccbb_win_chain_head *head; 3002 bus_addr_t align; 3003 3004 head = &sc->sc_iowindow; 3005 align = 0x04; 3006 if (sc->sc_memt == bst) { 3007 head = &sc->sc_memwindow; 3008 align = 0x1000; 3009 } 3010 3011 if (pccbb_winlist_delete(head, bsh, size)) { 3012 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3013 sc->sc_dev.dv_xname, 3014 (head == &sc->sc_memwindow) ? "mem" : "io"); 3015 } 3016 pccbb_winset(align, sc, bst); 3017 3018 return 0; 3019 } 3020 3021 static int 3022 pccbb_winlist_insert(head, start, size, bsh, flags) 3023 struct pccbb_win_chain_head *head; 3024 bus_addr_t start; 3025 bus_size_t size; 3026 bus_space_handle_t bsh; 3027 int flags; 3028 { 3029 struct pccbb_win_chain *chainp, *elem; 3030 3031 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3032 M_NOWAIT)) == NULL) 3033 return (1); /* fail */ 3034 3035 elem->wc_start = start; 3036 elem->wc_end = start + (size - 1); 3037 elem->wc_handle = bsh; 3038 elem->wc_flags = flags; 3039 3040 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3041 chainp = TAILQ_NEXT(chainp, wc_list)) { 3042 if (chainp->wc_end < start) 3043 continue; 3044 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3045 return (0); 3046 } 3047 3048 TAILQ_INSERT_TAIL(head, elem, wc_list); 3049 return (0); 3050 } 3051 3052 static int 3053 pccbb_winlist_delete(head, bsh, size) 3054 struct pccbb_win_chain_head *head; 3055 bus_space_handle_t bsh; 3056 bus_size_t size; 3057 { 3058 struct pccbb_win_chain *chainp; 3059 3060 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3061 chainp = TAILQ_NEXT(chainp, wc_list)) { 3062 if (chainp->wc_handle != bsh) 3063 continue; 3064 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3065 printf("pccbb_winlist_delete: window 0x%lx size " 3066 "inconsistent: 0x%lx, 0x%lx\n", 3067 chainp->wc_start, 3068 chainp->wc_end - chainp->wc_start, 3069 size - 1); 3070 return 1; 3071 } 3072 3073 TAILQ_REMOVE(head, chainp, wc_list); 3074 free(chainp, M_DEVBUF); 3075 3076 return 0; 3077 } 3078 3079 return 1; /* fail: no candidate to remove */ 3080 } 3081 3082 static void 3083 pccbb_winset(align, sc, bst) 3084 bus_addr_t align; 3085 struct pccbb_softc *sc; 3086 bus_space_tag_t bst; 3087 { 3088 pci_chipset_tag_t pc; 3089 pcitag_t tag; 3090 bus_addr_t mask = ~(align - 1); 3091 struct { 3092 cardbusreg_t win_start; 3093 cardbusreg_t win_limit; 3094 int win_flags; 3095 } win[2]; 3096 struct pccbb_win_chain *chainp; 3097 int offs; 3098 3099 win[0].win_start = 0xffffffff; 3100 win[0].win_limit = 0; 3101 win[1].win_start = 0xffffffff; 3102 win[1].win_limit = 0; 3103 3104 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3105 offs = 0x2c; 3106 if (sc->sc_memt == bst) { 3107 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3108 offs = 0x1c; 3109 } 3110 3111 if (chainp != NULL) { 3112 win[0].win_start = chainp->wc_start & mask; 3113 win[0].win_limit = chainp->wc_end & mask; 3114 win[0].win_flags = chainp->wc_flags; 3115 chainp = TAILQ_NEXT(chainp, wc_list); 3116 } 3117 3118 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3119 if (win[1].win_start == 0xffffffff) { 3120 /* window 1 is not used */ 3121 if ((win[0].win_flags == chainp->wc_flags) && 3122 (win[0].win_limit + align >= 3123 (chainp->wc_start & mask))) { 3124 /* concatenate */ 3125 win[0].win_limit = chainp->wc_end & mask; 3126 } else { 3127 /* make new window */ 3128 win[1].win_start = chainp->wc_start & mask; 3129 win[1].win_limit = chainp->wc_end & mask; 3130 win[1].win_flags = chainp->wc_flags; 3131 } 3132 continue; 3133 } 3134 3135 /* Both windows are engaged. */ 3136 if (win[0].win_flags == win[1].win_flags) { 3137 /* same flags */ 3138 if (win[0].win_flags == chainp->wc_flags) { 3139 if (win[1].win_start - (win[0].win_limit + 3140 align) < 3141 (chainp->wc_start & mask) - 3142 ((chainp->wc_end & mask) + align)) { 3143 /* 3144 * merge window 0 and 1, and set win1 3145 * to chainp 3146 */ 3147 win[0].win_limit = win[1].win_limit; 3148 win[1].win_start = 3149 chainp->wc_start & mask; 3150 win[1].win_limit = 3151 chainp->wc_end & mask; 3152 } else { 3153 win[1].win_limit = 3154 chainp->wc_end & mask; 3155 } 3156 } else { 3157 /* different flags */ 3158 3159 /* concatenate win0 and win1 */ 3160 win[0].win_limit = win[1].win_limit; 3161 /* allocate win[1] to new space */ 3162 win[1].win_start = chainp->wc_start & mask; 3163 win[1].win_limit = chainp->wc_end & mask; 3164 win[1].win_flags = chainp->wc_flags; 3165 } 3166 } else { 3167 /* the flags of win[0] and win[1] is different */ 3168 if (win[0].win_flags == chainp->wc_flags) { 3169 win[0].win_limit = chainp->wc_end & mask; 3170 /* 3171 * XXX this creates overlapping windows, so 3172 * what should the poor bridge do if one is 3173 * cachable, and the other is not? 3174 */ 3175 printf("%s: overlapping windows\n", 3176 sc->sc_dev.dv_xname); 3177 } else { 3178 win[1].win_limit = chainp->wc_end & mask; 3179 } 3180 } 3181 } 3182 3183 pc = sc->sc_pc; 3184 tag = sc->sc_tag; 3185 pci_conf_write(pc, tag, offs, win[0].win_start); 3186 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3187 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3188 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3189 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3190 pci_conf_read(pc, tag, offs), 3191 pci_conf_read(pc, tag, offs + 4) + align, 3192 pci_conf_read(pc, tag, offs + 8), 3193 pci_conf_read(pc, tag, offs + 12) + align)); 3194 3195 if (bst == sc->sc_memt) { 3196 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3197 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3198 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3199 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3200 } 3201 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3202 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3203 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3204 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3205 } 3206 } 3207 } 3208 3209 #endif /* rbus */ 3210 3211 static void 3212 pccbb_powerhook(why, arg) 3213 int why; 3214 void *arg; 3215 { 3216 struct pccbb_softc *sc = arg; 3217 u_int32_t reg; 3218 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3219 bus_space_handle_t base_memh = sc->sc_base_memh; 3220 3221 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3222 3223 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3224 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3225 if (sc->sc_pil_intr_enable) { 3226 (void)pccbbintr_function(sc); 3227 } 3228 sc->sc_pil_intr_enable = 0; 3229 3230 /* ToDo: deactivate or suspend child devices */ 3231 3232 } 3233 3234 if (why == PWR_RESUME) { 3235 /* CSC Interrupt: Card detect interrupt on */ 3236 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3237 /* Card detect intr is turned on. */ 3238 reg |= CB_SOCKET_MASK_CD; 3239 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3240 /* reset interrupt */ 3241 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3242 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3243 3244 /* 3245 * check for card insertion or removal during suspend period. 3246 * XXX: the code can't cope with card swap (remove then 3247 * insert). how can we detect such situation? 3248 */ 3249 (void)pccbbintr(sc); 3250 3251 sc->sc_pil_intr_enable = 1; 3252 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3253 3254 /* ToDo: activate or wakeup child devices */ 3255 } 3256 } 3257
Indexes created Fri Sep 26 08:10:20 GMT 2025