pccbb.c revision 1.6
1 /* $NetBSD: pccbb.c,v 1.6 1999/10/30 16:02:28 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 and 1999 HAYAKAWA Koichi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by HAYAKAWA Koichi. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 #define CBB_DEBUG 34 #define SHOW_REGS 35 #define PCCBB_PCMCIA_POLL 36 */ 37 /* #define CBB_DEBUG */ 38 39 /* 40 #define CB_PCMCIA_POLL 41 #define CB_PCMCIA_POLL_ONLY 42 #define LEVEL2 43 */ 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/ioctl.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 55 #include <machine/intr.h> 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/pccbbreg.h> 63 64 #include <dev/cardbus/cardslotvar.h> 65 66 #include <dev/cardbus/cardbusvar.h> 67 68 #include <dev/pcmcia/pcmciareg.h> 69 #include <dev/pcmcia/pcmciavar.h> 70 71 #include <dev/ic/i82365reg.h> 72 #include <dev/ic/i82365var.h> 73 #include <dev/pci/pccbbvar.h> 74 75 #include "locators.h" 76 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 93 #ifdef __BROKEN_INDIRECT_CONFIG 94 int pcicbbmatch __P((struct device *, void *, void *)); 95 #else 96 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 97 #endif 98 void pccbbattach __P((struct device *, struct device *, void *)); 99 int pccbbintr __P((void *)); 100 static void pci113x_insert __P((void *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 110 STATIC int cb_reset __P((struct pccbb_softc *)); 111 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 112 STATIC int cbbprint __P((void *, const char *)); 113 114 static int cb_chipset __P((u_int32_t, char const **, int *)); 115 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc *sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 127 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 128 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 129 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 130 #endif /* !rbus */ 131 static void *pccbb_intr_establish __P((cardbus_chipset_tag_t, int irq, int level, int (* ih)(void *), void *sc)); 132 static void pccbb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 133 134 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 135 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 136 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, int)); 137 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, cardbusreg_t)); 138 static void pccbb_chipinit __P((struct pccbb_softc *)); 139 140 141 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 142 struct pcmcia_mem_handle *)); 143 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 144 struct pcmcia_mem_handle *)); 145 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 146 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 147 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 148 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 149 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 150 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 151 struct pcmcia_io_handle *)); 152 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_io_handle *, int *)); 154 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 155 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 156 struct pcmcia_function *, int, int (*) (void *), void *)); 157 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, void *)); 158 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 159 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 160 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 161 162 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 163 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 164 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 165 166 /* bus-space allocation and disallocation functions */ 167 #if rbus 168 169 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 170 bus_addr_t addr, bus_size_t size, 171 bus_addr_t mask, bus_size_t align, 172 int flags, bus_addr_t *addrp, 173 bus_space_handle_t *bshp)); 174 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 175 bus_space_handle_t, bus_size_t)); 176 177 #endif /* rbus */ 178 179 #if rbus 180 181 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 182 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, bus_space_handle_t, bus_size_t)); 183 static int pccbb_winlist_insert __P((struct pccbb_win_chain **, bus_addr_t, 184 bus_size_t, bus_space_handle_t, int)); 185 static int pccbb_winlist_delete __P((struct pccbb_win_chain **, 186 bus_space_handle_t, bus_size_t)); 187 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 188 bus_space_tag_t)); 189 void pccbb_winlist_show(struct pccbb_win_chain *); 190 191 #endif /* rbus */ 192 193 /* for config_defer */ 194 static void pccbb_pci_callback __P((struct device *)); 195 196 197 #if defined SHOW_REGS 198 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, bus_space_handle_t memh)); 199 #endif 200 201 202 203 struct cfattach cbb_pci_ca = { 204 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 205 }; 206 207 208 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 209 pccbb_pcmcia_mem_alloc, 210 pccbb_pcmcia_mem_free, 211 pccbb_pcmcia_mem_map, 212 pccbb_pcmcia_mem_unmap, 213 pccbb_pcmcia_io_alloc, 214 pccbb_pcmcia_io_free, 215 pccbb_pcmcia_io_map, 216 pccbb_pcmcia_io_unmap, 217 pccbb_pcmcia_intr_establish, 218 pccbb_pcmcia_intr_disestablish, 219 pccbb_pcmcia_socket_enable, 220 pccbb_pcmcia_socket_disable, 221 pccbb_pcmcia_card_detect 222 }; 223 224 #if rbus 225 static struct cardbus_functions pccbb_funcs = { 226 pccbb_rbus_cb_space_alloc, 227 pccbb_rbus_cb_space_free, 228 pccbb_intr_establish, 229 pccbb_intr_disestablish, 230 pccbb_ctrl, 231 pccbb_power, 232 pccbb_make_tag, 233 pccbb_free_tag, 234 pccbb_conf_read, 235 pccbb_conf_write, 236 }; 237 #else 238 static struct cardbus_functions pccbb_funcs = { 239 pccbb_ctrl, 240 pccbb_power, 241 pccbb_mem_open, 242 pccbb_mem_close, 243 pccbb_io_open, 244 pccbb_io_close, 245 pccbb_intr_establish, 246 pccbb_intr_disestablish, 247 pccbb_make_tag, 248 pccbb_conf_read, 249 pccbb_conf_write, 250 }; 251 #endif 252 253 254 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 #ifdef __BROKEN_INDIRECT_CONFIG 260 void *match; 261 #else 262 struct cfdata *match; 263 #endif 264 void *aux; 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if ((pa->pa_class & PCI_CLASS_INTERFACE_MASK) == PCI_CLASS_INTERFACE_YENTA) { 269 /* OK, It must be YENTA PCI-CardBus bridge */ 270 271 return 1; 272 } 273 274 return 0; 275 } 276 277 278 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 279 | ((prod) << PCI_PRODUCT_SHIFT)) 280 281 282 struct yenta_chipinfo { 283 pcireg_t yc_id; /* vendor tag | product tag */ 284 const char *yc_name; 285 int yc_chiptype; 286 int yc_flags; 287 } yc_chipsets[] = { 288 /* Texas Instruments chips */ 289 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), "TI1130", CB_TI113X, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), "TI1131", CB_TI113X, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 294 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), "TI1250", CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), "TI1220", CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), "TI1221", CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), "TI1225", CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), "TI1251", CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), "TI1251B", CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), "TI1211", CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), "TI1420", CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), "TI1450", CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI2030), "TI2030", CB_UNKNOWN, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), "RF5C475", 317 CB_RF5C47X, PCCBB_PCMCIA_MEM_32}, 318 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), "RF5C476", 319 CB_RF5C47X, PCCBB_PCMCIA_MEM_32}, 320 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), "RF5C477", 321 CB_RF5C47X, PCCBB_PCMCIA_MEM_32}, 322 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), "RF5C478", 323 CB_RF5C47X, PCCBB_PCMCIA_MEM_32}, 324 325 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), "RF5C465", 326 CB_RF5C46X, PCCBB_PCMCIA_MEM_32}, 327 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), "RF5C466", 328 CB_RF5C46X, PCCBB_PCMCIA_MEM_32}, 329 330 /* Toshiba products */ 331 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), "ToPIC95", 332 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 333 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), "ToPIC95B", 334 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 335 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), "ToPIC97", 336 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 337 338 /* Cirrus Logic products */ 339 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), "CL-PD683X", 340 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 341 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), "CL-PD683X", 342 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 343 344 /* sentinel, or Generic chip */ 345 {0 /* null id */, "unknown", CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 346 }; 347 348 349 350 static int 351 cb_chipset(pci_id, namep, flagp) 352 u_int32_t pci_id; 353 char const **namep; 354 int *flagp; 355 { 356 int loopend = sizeof(yc_chipsets)/sizeof(yc_chipsets[0]); 357 struct yenta_chipinfo *ycp, *ycend; 358 359 ycend = yc_chipsets + loopend; 360 361 for (ycp =yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 362 363 if (ycp == ycend) { 364 /* not found */ 365 ycp = yc_chipsets + loopend - 1; /* to point the sentinel */ 366 } 367 368 if (namep != NULL) { 369 *namep = ycp->yc_name; 370 } 371 372 if (flagp != NULL) { 373 *flagp = ycp->yc_flags; 374 } 375 376 return ycp->yc_chiptype; 377 } 378 379 380 381 382 383 void 384 pccbbattach(parent, self, aux) 385 struct device *parent; 386 struct device *self; 387 void *aux; 388 { 389 struct pccbb_softc *sc = (void *)self; 390 struct pci_attach_args *pa = aux; 391 pci_chipset_tag_t pc = pa->pa_pc; 392 pcireg_t sock_base, busreg; 393 bus_addr_t sockbase; 394 char const *name; 395 int flags; 396 397 sc->sc_chipset = cb_chipset(pa->pa_id, &name, &flags); 398 printf(" (%s), chipflags %d\n", name, flags); 399 400 #if rbus 401 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 402 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 403 #endif /* rbus */ 404 405 sc->sc_base_memh = 0; 406 407 /* 408 * MAP socket registers and ExCA registers on memory-space 409 * When no valid address is set on socket base registers (on pci 410 * config space), get it not polite way. 411 */ 412 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 413 414 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 415 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 416 /* The address must be valid. */ 417 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 418 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 419 NULL)) { 420 printf("%s: can't map socket base address 0x%x\n", sc->sc_dev.dv_xname, 421 sock_base); 422 /* I think it's funny: socket base registers must be mapped on 423 memory space, but ... */ 424 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 0, 425 &sc->sc_base_memt, &sc->sc_base_memh, 426 &sockbase, NULL)) { 427 printf("%s: can't map socket base address 0x%lx: io mode\n", 428 sc->sc_dev.dv_xname, sockbase); 429 /* give up... allocate register space via rbus. */ 430 sc->sc_base_memh = 0; 431 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 432 } 433 } else { 434 DPRINTF(("%s: socket base address 0x%lx",sc->sc_dev.dv_xname, sockbase)); 435 } 436 } 437 438 439 sc->sc_mem_start = 0; /* XXX */ 440 sc->sc_mem_end = 0xffffffff; /* XXX */ 441 442 /* 443 * When interrupt isn't routed correctly, give up probing cbb and do 444 * not kill pcic-compatible port. 445 */ 446 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 447 printf(" Do not use %s because of intr unconfig.\n", sc->sc_dev.dv_xname); 448 return; 449 } 450 451 /* 452 * When bus number isn't set correctly, give up using 32-bit CardBus 453 * mode. 454 */ 455 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 456 #if notyet 457 if (((busreg >> 8) & 0xff) == 0) { 458 printf(" CardBus on %s will not be configured, because of bus no unconfig.\n", sc->sc_dev.dv_xname); 459 flags |= PCCBB_PCMCIA_16BITONLY; 460 } 461 #endif 462 463 /* pccbb_machdep.c end */ 464 465 466 #if defined CBB_DEBUG 467 { 468 static char *intrname[5] = {"NON", "A", "B", "C", "D"}; 469 printf(" intrpin %s, intrtag %d\n", intrname[pa->pa_intrpin], 470 pa->pa_intrline); 471 } 472 #endif 473 474 475 /* setup softc */ 476 sc->sc_pc = pc; 477 sc->sc_iot = pa->pa_iot; 478 sc->sc_memt = pa->pa_memt; 479 sc->sc_dmat = pa->pa_dmat; 480 sc->sc_tag = pa->pa_tag; 481 sc->sc_function = pa->pa_function; 482 483 sc->sc_intrline = pa->pa_intrline; 484 sc->sc_intrtag = pa->pa_intrtag; 485 sc->sc_intrpin = pa->pa_intrpin; 486 487 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 488 489 /* bus bridge initialisation */ 490 pccbb_chipinit(sc); 491 492 #if __NetBSD_Version__ > 103060000 493 config_defer(self, pccbb_pci_callback); 494 #else 495 pccbb_pci_callback(self); 496 #endif 497 } 498 499 500 501 502 static void 503 pccbb_pci_callback(self) 504 struct device *self; 505 { 506 struct pccbb_softc *sc = (void *)self; 507 pci_chipset_tag_t pc = sc->sc_pc; 508 bus_space_tag_t base_memt; 509 bus_space_handle_t base_memh; 510 u_int32_t maskreg; 511 pci_intr_handle_t ih; 512 const char *intrstr = NULL; 513 bus_addr_t sockbase; 514 struct cbslot_attach_args cba; 515 struct pcmciabus_attach_args paa; 516 struct cardslot_attach_args caa; 517 struct cardslot_softc *csc; 518 519 if (0 == sc->sc_base_memh) { 520 /* The socket registers aren't mapped correctly. */ 521 #if rbus 522 if (rbus_space_alloc(sc->sc_rbus_memt, 523 0, /* address: I don't mind where it is mapped */ 524 0x1000, /* size */ 525 0x0fff, /* mask */ 526 0x1000, /* align */ 527 0, /* flags */ 528 &sockbase, &sc->sc_base_memh)) { 529 return; 530 } 531 sc->sc_base_memt = sc->sc_memt; 532 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 533 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 534 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 535 #else 536 sc->sc_base_memt = sc->sc_memt; 537 #if !defined CBB_PCI_BASE 538 #define CBB_PCI_BASE 0x20000000 539 #endif 540 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 541 0x1000, /* size */ 542 0x1000, /* alignment */ 543 0, /* boundary */ 544 0, /* flags */ 545 &sockbase, &sc->sc_base_memh)) { 546 /* cannot allocate memory space */ 547 return; 548 } 549 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 550 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n",sc->sc_dev.dv_xname, 551 sock_base, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 552 #endif 553 } 554 555 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 556 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 557 558 559 /* CSC Interrupt: Card detect interrupt on */ 560 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 561 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 562 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 563 /* reset interrupt */ 564 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 565 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 566 567 568 /* Map and establish the interrupt. */ 569 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 570 sc->sc_intrline, &ih)) { 571 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 572 return; 573 } 574 intrstr = pci_intr_string(pc, ih); 575 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 576 577 if (sc->sc_ih == NULL) { 578 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 579 if (intrstr != NULL) { 580 printf(" at %s", intrstr); 581 } 582 printf("\n"); 583 return; 584 } 585 586 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 587 588 { 589 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 590 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { /* card exist */ 591 sc->sc_flags |= CBB_CARDEXIST; 592 } 593 } 594 595 /* 596 * attach cardbus 597 */ 598 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 599 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 600 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 601 pcireg_t pci_lscp = pci_conf_read(pc, sc->sc_tag, PCI_CB_LSCP_REG); 602 603 /* initialise cbslot_attach */ 604 cba.cba_busname = "cardbus"; 605 cba.cba_iot = sc->sc_iot; 606 cba.cba_memt = sc->sc_memt; 607 cba.cba_dmat = sc->sc_dmat; 608 cba.cba_function = 0; 609 cba.cba_bus = (busreg >> 8) & 0x0ff; 610 cba.cba_cc = (void *)sc; 611 cba.cba_cf = &pccbb_funcs; 612 cba.cba_intrline = sc->sc_intrline; 613 614 #if rbus 615 cba.cba_rbus_iot = sc->sc_rbus_iot; 616 cba.cba_rbus_memt = sc->sc_rbus_memt; 617 #endif 618 619 cba.cba_cacheline = PCI_CACHELINE(bhlc); 620 cba.cba_lattimer = PCI_CB_LATENCY(pci_lscp); 621 622 printf("%s: cacheline 0x%x lattimer 0x%x\n", sc->sc_dev.dv_xname, 623 cba.cba_cacheline, cba.cba_lattimer); 624 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, 625 bhlc, pci_lscp); 626 #if defined SHOW_REGS 627 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 628 #endif 629 } 630 631 pccbb_pcmcia_attach_setup(sc, &paa); 632 caa.caa_cb_attach = NULL; 633 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 634 caa.caa_cb_attach = &cba; 635 } 636 caa.caa_16_attach = &paa; 637 caa.caa_ph = &sc->sc_pcmcia_h; 638 639 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 640 DPRINTF(("pccbbattach: found cardslot\n")); 641 sc->sc_csc = csc; 642 } 643 644 return; 645 } 646 647 648 649 static void 650 pccbb_chipinit(sc) 651 struct pccbb_softc *sc; 652 { 653 pci_chipset_tag_t pc = sc->sc_pc; 654 pcitag_t tag = sc->sc_tag; 655 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory tag */ 656 bus_space_handle_t base_memh = sc->sc_base_memh; /* socket regs memory handle */ 657 pcireg_t cbctrl; 658 659 /* 660 * Set PCI command reg. 661 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 662 */ 663 { 664 pcireg_t command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 665 666 /* I believe it is harmless. */ 667 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 668 PCI_COMMAND_MASTER_ENABLE); 669 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 670 } 671 672 /* 673 * Set CardBus latency timer 674 */ 675 { 676 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 677 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 678 pci_lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 679 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 680 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 681 } 682 DPRINTF(("CardBus latency timer 0x%x (%x)\n", PCI_CB_LATENCY(pci_lscp), 683 pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 684 } 685 686 /* 687 * Set PCI latency timer 688 */ 689 { 690 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 691 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 692 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 693 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 694 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 695 } 696 DPRINTF(("PCI latency timer 0x%x (%x)\n", PCI_LATTIMER(pci_bhlc), 697 pci_conf_read(pc, tag, PCI_BHLC_REG))); 698 } 699 700 /* disable Legacy IO */ 701 702 switch (sc->sc_chipset) { 703 case CB_RF5C46X: /* fallthrogh */ 704 case CB_RF5C47X: 705 /* 706 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 707 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 708 * CardBus bridges have special bits on Bridge control reg (addr 709 * 0x3e on PCI config space). 710 */ 711 { 712 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 713 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 714 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 715 } 716 break; 717 default: 718 /* XXX: I don't know proper way to kill Legacy IO properly. */ 719 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 720 break; 721 } 722 723 724 725 /* 726 * Interrupt routing: use PCI interrupt 727 */ 728 { 729 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 730 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 731 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 732 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 733 } 734 735 if (CB_TI113X == sc->sc_chipset) { 736 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 737 if (0 == sc->sc_function) { 738 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 739 } 740 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; /* XXX: bug in PCI113X */ 741 cbctrl |= PCI113X_CBCTRL_PCI_CSC; /* CSC intr enable */ 742 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr prohibit */ 743 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; /* prohibit ISA routing */ 744 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 745 746 /* set ExCA regs: PCI113X required to be set bit 4 at Interrupt 747 and General Register, which is IRQ Enable Register, and clear 748 bit 3:0 to zero in order to route CSC interrupt to PCI 749 interrupt pin. */ 750 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 751 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 752 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 753 #if 1 754 DPRINTF(("ExCA regs:")); 755 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 0x803))); 756 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 0x805))); 757 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt,base_memh,0x81e))); 758 #endif 759 } else if (sc->sc_chipset == CB_TI12XX) { 760 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 761 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 762 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 763 /* 764 * set ExCA regs: PCI12XX required to be set bit 4 at Interrupt 765 * and General Register, which is IRQ Enable Register, and clear 766 * bit 3:0 to zero in order to route CSC interrupt to PCI 767 * interrupt pin. 768 */ 769 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 770 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 771 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 772 } else if (sc->sc_chipset == CB_TOPIC95B) { 773 cardbusreg_t sock_ctrl, slot_ctrl; 774 775 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 776 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 777 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 778 779 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 780 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", sc->sc_dev.dv_xname, 781 slot_ctrl)); 782 slot_ctrl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 783 TOPIC_SLOT_CTRL_ID_LOCK); 784 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 785 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 786 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 787 DPRINTF(("0x%x\n", slot_ctrl)); 788 } 789 790 /* close all memory and io windows */ 791 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 792 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 793 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 794 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 795 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 796 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 797 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 798 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 799 800 return; 801 } 802 803 804 805 /* 806 * attach pccard bus 807 */ 808 STATIC void 809 pccbb_pcmcia_attach_setup(sc, paa) 810 struct pccbb_softc *sc; 811 struct pcmciabus_attach_args *paa; 812 { 813 struct pcic_handle *ph = &sc->sc_pcmcia_h; 814 815 /* initialise pcmcia part in pccbb_softc */ 816 ph->ph_parent = (struct device *)sc; 817 ph->sock = sc->sc_function; 818 ph->flags = 0; 819 ph->shutdown = 0; 820 ph->ih_irq = sc->sc_intrline; 821 ph->ph_bus_t = sc->sc_base_memt; 822 ph->ph_bus_h = sc->sc_base_memh; 823 ph->ph_read = pccbb_pcmcia_read; 824 ph->ph_write = pccbb_pcmcia_write; 825 sc->sc_pct = &pccbb_pcmcia_funcs; 826 827 Pcic_write(ph, PCIC_CSC_INTR, 0); 828 Pcic_read(ph, PCIC_CSC); 829 830 /* initialise pcmcia bus attachment */ 831 paa->paa_busname = "pcmcia"; 832 paa->pct = sc->sc_pct; 833 paa->pch = ph; 834 paa->iobase = 0; /* I don't use them */ 835 paa->iosize = 0; 836 837 return; 838 } 839 840 841 #if 0 842 STATIC void 843 pccbb_pcmcia_attach_card(ph) 844 struct pcic_handle *ph; 845 { 846 if (ph->flags & PCIC_FLAG_CARDP) { 847 panic("pccbb_pcmcia_attach_card: already attached"); 848 } 849 850 /* call the MI attach function */ 851 pcmcia_card_attach(ph->pcmcia); 852 853 ph->flags |= PCIC_FLAG_CARDP; 854 } 855 856 857 STATIC void 858 pccbb_pcmcia_detach_card(ph, flags) 859 struct pcic_handle *ph; 860 int flags; 861 { 862 if (!(ph->flags & PCIC_FLAG_CARDP)) { 863 panic("pccbb_pcmcia_detach_card: already detached"); 864 } 865 866 ph->flags &= ~PCIC_FLAG_CARDP; 867 868 /* call the MI detach function */ 869 pcmcia_card_detach(ph->pcmcia, flags); 870 } 871 #endif 872 873 874 875 876 /* 877 * int pccbbintr(arg) 878 * void *arg; 879 * This routine handles the interrupt from Yenta PCI-CardBus bridge 880 * itself. 881 */ 882 int 883 pccbbintr(arg) 884 void *arg; 885 { 886 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 887 u_int32_t sockevent; 888 bus_space_tag_t memt = sc->sc_base_memt; 889 bus_space_handle_t memh = sc->sc_base_memh; 890 u_int32_t sockstate; 891 892 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 893 if (0 == sockevent) { /* not for me */ 894 return 0; 895 } else { 896 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); /* reset bit */ 897 } 898 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 899 900 if (sockevent & CB_SOCKET_EVENT_CD) { 901 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 902 /* A card should be removed. */ 903 if (sc->sc_flags & CBB_CARDEXIST) { 904 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 905 DPRINTF((" card removed, 0x%08x\n", sockstate)); 906 sc->sc_flags &= ~CBB_CARDEXIST; 907 if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { 908 #if 0 909 struct pcic_handle *ph = &sc->sc_pcmcia_h; 910 911 pcmcia_card_deactivate(ph->pcmcia); 912 pccbb_pcmcia_socket_disable(ph); 913 pccbb_pcmcia_detach_card(ph, DETACH_FORCE); 914 #endif 915 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_16); 916 } else if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) { 917 /* Cardbus intr removed */ 918 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_CB); 919 } 920 } 921 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 922 if (sc->sc_flags & CBB_INSERTING) { 923 untimeout(pci113x_insert, sc); 924 } 925 timeout(pci113x_insert, sc, hz/10); 926 sc->sc_flags |= CBB_INSERTING; 927 } 928 } else { 929 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 930 if (sockevent & CB_SOCKET_EVENT_CSTS) { 931 DPRINTF((" cstsevent occures, 0x%08x\n", sockstate)); 932 } 933 if (sockevent & CB_SOCKET_EVENT_POWER) { 934 DPRINTF((" pwrevent occures, 0x%08x\n", sockstate)); 935 } 936 } 937 938 return 1; 939 } 940 941 942 943 static void 944 pci113x_insert(arg) 945 void *arg; 946 { 947 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 948 u_int32_t sockevent, sockstate; 949 950 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 951 CB_SOCKET_EVENT); 952 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 953 CB_SOCKET_STAT); 954 955 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 956 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 957 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 958 sc->sc_flags |= CBB_CARDEXIST; 959 /* call pccard intterupt handler here */ 960 if (sockstate & CB_SOCKET_STAT_16BIT) { 961 /* 16-bit card found */ 962 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 963 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_16); 964 } else if (sockstate & CB_SOCKET_STAT_CB) { 965 /* cardbus card fuond */ 966 /* cardbus_attach_card(sc->sc_csc); */ 967 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_CB); 968 } else { 969 /* who are you? */ 970 } 971 } else { 972 timeout(pci113x_insert, sc, hz/10); 973 } 974 } 975 976 977 978 979 #define PCCBB_PCMCIA_OFFSET 0x800 980 static u_int8_t 981 pccbb_pcmcia_read(ph, reg) 982 struct pcic_handle *ph; 983 int reg; 984 { 985 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg); 986 } 987 988 989 990 static void 991 pccbb_pcmcia_write(ph, reg, val) 992 struct pcic_handle *ph; 993 int reg; 994 u_int8_t val; 995 { 996 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, val); 997 998 return; 999 } 1000 1001 1002 1003 1004 /* 1005 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1006 */ 1007 STATIC int 1008 pccbb_ctrl(ct, command) 1009 cardbus_chipset_tag_t ct; 1010 int command; 1011 { 1012 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1013 1014 switch(command) { 1015 case CARDBUS_CD: 1016 if (2 == pccbb_detect_card(sc)) { 1017 int retval = 0; 1018 int status = cb_detect_voltage(sc); 1019 if (PCCARD_VCC_5V & status) { 1020 retval |= CARDBUS_5V_CARD; 1021 } 1022 if (PCCARD_VCC_3V & status) { 1023 retval |= CARDBUS_3V_CARD; 1024 } 1025 if (PCCARD_VCC_XV & status) { 1026 retval |= CARDBUS_XV_CARD; 1027 } 1028 if (PCCARD_VCC_YV & status) { 1029 retval |= CARDBUS_YV_CARD; 1030 } 1031 return retval; 1032 } else { 1033 return 0; 1034 } 1035 break; 1036 case CARDBUS_RESET: 1037 return cb_reset(sc); 1038 break; 1039 case CARDBUS_IO_ENABLE: /* fallthrough */ 1040 case CARDBUS_IO_DISABLE: /* fallthrough */ 1041 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1042 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1043 case CARDBUS_BM_ENABLE: /* fallthrough */ 1044 case CARDBUS_BM_DISABLE: /* fallthrough */ 1045 return pccbb_cardenable(sc, command); 1046 break; 1047 } 1048 1049 return 0; 1050 } 1051 1052 1053 1054 /* 1055 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1056 * This function returns true when it succeeds and returns false when 1057 * it fails. 1058 */ 1059 STATIC int 1060 pccbb_power(ct, command) 1061 cardbus_chipset_tag_t ct; 1062 int command; 1063 { 1064 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1065 1066 u_int32_t status, sock_ctrl; 1067 bus_space_tag_t memt = sc->sc_base_memt; 1068 bus_space_handle_t memh = sc->sc_base_memh; 1069 1070 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1071 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1072 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1073 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1074 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1075 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1076 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1077 "UNKNOWN", 1078 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1079 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1080 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1081 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1082 "UNKNOWN", 1083 command)); 1084 1085 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1086 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1087 1088 switch (command & CARDBUS_VCCMASK) { 1089 case CARDBUS_VCC_UC: 1090 break; 1091 case CARDBUS_VCC_5V: 1092 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1093 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1094 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1095 } else { 1096 printf("%s: BAD voltage request: no 5 V card\n", sc->sc_dev.dv_xname); 1097 } 1098 break; 1099 case CARDBUS_VCC_3V: 1100 if (CB_SOCKET_STAT_3VCARD & status) { 1101 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1102 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1103 } else { 1104 printf("%s: BAD voltage request: no 3.3 V card\n", sc->sc_dev.dv_xname); 1105 } 1106 break; 1107 case CARDBUS_VCC_0V: 1108 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1109 break; 1110 default: 1111 return 0; /* power NEVER changed */ 1112 break; 1113 } 1114 1115 switch (command & CARDBUS_VPPMASK) { 1116 case CARDBUS_VPP_UC: 1117 break; 1118 case CARDBUS_VPP_0V: 1119 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1120 break; 1121 case CARDBUS_VPP_VCC: 1122 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1123 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1124 break; 1125 case CARDBUS_VPP_12V: 1126 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1127 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1128 break; 1129 } 1130 1131 #if 0 1132 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1133 #endif 1134 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1135 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1136 1137 delay(20*1000); /* wait 20 ms: Vcc setup time */ 1138 /* XXX 1139 delay 200 ms: though the standard defines that the Vcc set-up time 1140 is 20 ms, some PC-Card bridge requires longer duration. 1141 */ 1142 delay(200*1000); 1143 1144 1145 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1146 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1147 sc->sc_dev.dv_xname, sock_ctrl ,status); 1148 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1149 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1150 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V": 1151 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V": 1152 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV": 1153 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV": 1154 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V": 1155 "UNKNOWN", 1156 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC": 1157 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ?"CARDBUS_VPP_12V": 1158 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ?"CARDBUS_VPP_VCC": 1159 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1160 "UNKNOWN", 1161 command)); 1162 #if 0 1163 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1164 u_int32_t force = bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1165 /* Reset Bad Vcc request */ 1166 force &= ~CB_SOCKET_FORCE_BADVCC; 1167 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1168 printf("new status 0x%x\n", bus_space_read_4(memt, memh,CB_SOCKET_STAT)); 1169 return 1; 1170 } 1171 #endif 1172 return 0; 1173 } 1174 return 1; /* power changed correctly */ 1175 } 1176 1177 1178 1179 1180 1181 1182 #if defined CB_PCMCIA_POLL 1183 struct cb_poll_str { 1184 void *arg; 1185 int (* func) __P((void *)); 1186 int level; 1187 pccard_chipset_tag_t ct; 1188 int count; 1189 }; 1190 1191 static struct cb_poll_str cb_poll[10]; 1192 static int cb_poll_n = 0; 1193 1194 static void cb_pcmcia_poll __P((void *arg)); 1195 1196 static void 1197 cb_pcmcia_poll(arg) 1198 void *arg; 1199 { 1200 struct cb_poll_str *poll = arg; 1201 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1202 struct pccbb_softc *sc = psc->cpc_parent; 1203 int s; 1204 u_int32_t spsr; /* socket present-state reg */ 1205 1206 timeout(cb_pcmcia_poll, arg, hz/10); 1207 switch (poll->level) { 1208 case IPL_NET: 1209 s = splnet(); 1210 break; 1211 case IPL_BIO: 1212 s = splbio(); 1213 break; 1214 case IPL_TTY: /* fallthrough */ 1215 default: 1216 s = spltty(); 1217 break; 1218 } 1219 1220 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 1221 1222 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1223 if (!(spsr & 0x40)) { /* CINT low */ 1224 #else 1225 if (1) { 1226 #endif 1227 if ((*poll->func)(poll->arg) == 1) { 1228 ++poll->count; 1229 printf("intr: reported from poller, 0x%x\n", spsr); 1230 #if defined LEVEL2 1231 } else { 1232 printf("intr: miss! 0x%x\n", spsr); 1233 #endif 1234 } 1235 } 1236 splx(s); 1237 } 1238 #endif /* defined CB_PCMCIA_POLL */ 1239 1240 1241 1242 1243 /* 1244 * static int pccbb_detect_card(struct pccbb_softc *sc) 1245 * return value: 0 if no card exists. 1246 * 1 if 16-bit card exists. 1247 * 2 if cardbus card exists. 1248 */ 1249 static int 1250 pccbb_detect_card(sc) 1251 struct pccbb_softc *sc; 1252 { 1253 bus_space_handle_t base_memh = sc->sc_base_memh; 1254 bus_space_tag_t base_memt = sc->sc_base_memt; 1255 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 1256 int retval = 0; 1257 1258 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { /* CD1 and CD2 asserted */ 1259 /* card must be present */ 1260 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { /* NOTACARD DEASSERTED */ 1261 if (CB_SOCKET_STAT_CB & sockstat) { /* CardBus mode */ 1262 retval = 2; 1263 } else if (CB_SOCKET_STAT_16BIT & sockstat) { /* 16-bit mode */ 1264 retval = 1; 1265 } 1266 } 1267 } 1268 return retval; 1269 } 1270 1271 1272 1273 1274 /* 1275 * STATIC int cb_reset(struct pccbb_softc *sc) 1276 * This function resets CardBus card. 1277 */ 1278 STATIC int 1279 cb_reset(sc) 1280 struct pccbb_softc *sc; 1281 { 1282 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1283 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1284 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1285 /* Reset Assert at least 20 ms */ 1286 delay(20*1000); 1287 1288 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1289 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1290 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1291 delay(20*1000); 1292 } 1293 /* No card found on the slot. Keep Reset. */ 1294 return 1; 1295 } 1296 1297 1298 1299 1300 /* 1301 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1302 * This function detect card Voltage. 1303 */ 1304 STATIC int 1305 cb_detect_voltage(sc) 1306 struct pccbb_softc *sc; 1307 { 1308 u_int32_t psr; /* socket present-state reg */ 1309 bus_space_tag_t iot = sc->sc_base_memt; 1310 bus_space_handle_t ioh = sc->sc_base_memh; 1311 int vol = PCCARD_VCC_UKN; /* set 0 */ 1312 1313 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1314 1315 if (0x400u & psr) { 1316 vol |= PCCARD_VCC_5V; 1317 } 1318 if (0x800u & psr) { 1319 vol |= PCCARD_VCC_3V; 1320 } 1321 1322 return vol; 1323 } 1324 1325 1326 1327 1328 1329 1330 STATIC int 1331 cbbprint(aux, pcic) 1332 void *aux; 1333 const char *pcic; 1334 { 1335 /* 1336 struct cbslot_attach_args *cba = aux; 1337 1338 if (cba->cba_slot >= 0) { 1339 printf(" slot %d", cba->cba_slot); 1340 } 1341 */ 1342 return UNCONF; 1343 } 1344 1345 1346 1347 1348 /* 1349 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1350 * This function enables and disables the card 1351 */ 1352 STATIC int 1353 pccbb_cardenable(sc, function) 1354 struct pccbb_softc *sc; 1355 int function; 1356 { 1357 u_int32_t command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1358 1359 DPRINTF(("pccbb_cardenable:")); 1360 switch (function) { 1361 case CARDBUS_IO_ENABLE: 1362 command |= PCI_COMMAND_IO_ENABLE; 1363 break; 1364 case CARDBUS_IO_DISABLE: 1365 command &= ~PCI_COMMAND_IO_ENABLE; 1366 break; 1367 case CARDBUS_MEM_ENABLE: 1368 command |= PCI_COMMAND_MEM_ENABLE; 1369 break; 1370 case CARDBUS_MEM_DISABLE: 1371 command &= ~PCI_COMMAND_MEM_ENABLE; 1372 break; 1373 case CARDBUS_BM_ENABLE: 1374 command |= PCI_COMMAND_MASTER_ENABLE; 1375 break; 1376 case CARDBUS_BM_DISABLE: 1377 command &= ~PCI_COMMAND_MASTER_ENABLE; 1378 break; 1379 default: 1380 return 0; 1381 } 1382 1383 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1384 DPRINTF((" command reg 0x%x\n", command)); 1385 return 1; 1386 } 1387 1388 1389 1390 1391 1392 1393 #if !rbus 1394 /* 1395 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1396 */ 1397 static int 1398 pccbb_io_open(ct, win, start, end) 1399 cardbus_chipset_tag_t ct; 1400 int win; 1401 u_int32_t start, end; 1402 { 1403 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1404 int basereg; 1405 int limitreg; 1406 1407 if ((win < 0) || (win > 2)) { 1408 #if defined DIAGNOSTIC 1409 printf("cardbus_io_open: window out of range %d\n", win); 1410 #endif 1411 return 0; 1412 } 1413 1414 basereg = win*8 + 0x2c; 1415 limitreg = win*8 + 0x30; 1416 1417 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1418 start, basereg, end, limitreg)); 1419 1420 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1421 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1422 return 1; 1423 } 1424 1425 /* 1426 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1427 */ 1428 static int 1429 pccbb_io_close(ct, win) 1430 cardbus_chipset_tag_t ct; 1431 int win; 1432 { 1433 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1434 int basereg; 1435 int limitreg; 1436 1437 if ((win < 0) || (win > 2)) { 1438 #if defined DIAGNOSTIC 1439 printf("cardbus_io_close: window out of range %d\n", win); 1440 #endif 1441 return 0; 1442 } 1443 1444 basereg = win*8 + 0x2c; 1445 limitreg = win*8 + 0x30; 1446 1447 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1448 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1449 return 1; 1450 } 1451 1452 /* 1453 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1454 */ 1455 static int 1456 pccbb_mem_open(ct, win, start, end) 1457 cardbus_chipset_tag_t ct; 1458 int win; 1459 u_int32_t start, end; 1460 { 1461 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1462 int basereg; 1463 int limitreg; 1464 1465 if ((win < 0) || (win > 2)) { 1466 #if defined DIAGNOSTIC 1467 printf("cardbus_mem_open: window out of range %d\n", win); 1468 #endif 1469 return 0; 1470 } 1471 1472 basereg = win*8 + 0x1c; 1473 limitreg = win*8 + 0x20; 1474 1475 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1476 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1477 return 1; 1478 } 1479 1480 1481 /* 1482 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1483 */ 1484 static int 1485 pccbb_mem_close(ct, win) 1486 cardbus_chipset_tag_t ct; 1487 int win; 1488 { 1489 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1490 int basereg; 1491 int limitreg; 1492 1493 if ((win < 0) || (win > 2)) { 1494 #if defined DIAGNOSTIC 1495 printf("cardbus_mem_close: window out of range %d\n", win); 1496 #endif 1497 return 0; 1498 } 1499 1500 basereg = win*8 + 0x1c; 1501 limitreg = win*8 + 0x20; 1502 1503 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1504 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1505 return 1; 1506 } 1507 #endif 1508 1509 1510 1511 static void * 1512 pccbb_intr_establish(ct, irq, level, func, arg) 1513 cardbus_chipset_tag_t ct; 1514 int irq, level; 1515 int (* func) __P((void *)); 1516 void *arg; 1517 { 1518 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1519 1520 switch (sc->sc_chipset) { 1521 case CB_TI113X: 1522 { 1523 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1524 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* functional intr enabled */ 1525 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1526 } 1527 break; 1528 default: 1529 break; 1530 } 1531 1532 return pci_intr_establish(sc->sc_pc, irq, level, func, arg); 1533 } 1534 1535 1536 1537 1538 static void 1539 pccbb_intr_disestablish(ct, ih) 1540 cardbus_chipset_tag_t ct; 1541 void *ih; 1542 { 1543 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1544 1545 switch (sc->sc_chipset) { 1546 case CB_TI113X: 1547 { 1548 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1549 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr disabled */ 1550 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1551 } 1552 break; 1553 default: 1554 break; 1555 } 1556 1557 pci_intr_disestablish(sc->sc_pc, ih); 1558 } 1559 1560 1561 1562 1563 1564 #if defined SHOW_REGS 1565 static void 1566 cb_show_regs(pc, tag, memt, memh) 1567 pci_chipset_tag_t pc; 1568 pcitag_t tag; 1569 bus_space_tag_t memt; 1570 bus_space_handle_t memh; 1571 { 1572 int i; 1573 printf("PCI config regs:"); 1574 for (i = 0; i < 0x50; i += 4) { 1575 if (i % 16 == 0) { 1576 printf("\n 0x%02x:", i); 1577 } 1578 printf(" %08x", pci_conf_read(pc, tag, i)); 1579 } 1580 for (i = 0x80; i < 0xb0; i += 4) { 1581 if (i % 16 == 0) { 1582 printf("\n 0x%02x:", i); 1583 } 1584 printf(" %08x", pci_conf_read(pc, tag, i)); 1585 } 1586 1587 if (memh == 0) { 1588 printf("\n"); 1589 return; 1590 } 1591 1592 printf("\nsocket regs:"); 1593 for (i = 0; i <= 0x10; i += 0x04) { 1594 printf(" %08x", bus_space_read_4(memt, memh, i)); 1595 } 1596 printf("\nExCA regs:"); 1597 for (i = 0; i < 0x08; ++i) { 1598 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1599 } 1600 printf("\n"); 1601 return; 1602 } 1603 #endif 1604 1605 1606 1607 /* 1608 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1609 * int busno, int devno, int function) 1610 * This is the function to make a tag to access config space of 1611 * a CardBus Card. It works same as pci_conf_read. 1612 */ 1613 static cardbustag_t 1614 pccbb_make_tag(cc, busno, devno, function) 1615 cardbus_chipset_tag_t cc; 1616 int busno, devno, function; 1617 { 1618 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1619 1620 return pci_make_tag(sc->sc_pc, busno, devno, function); 1621 } 1622 1623 1624 static void 1625 pccbb_free_tag(cc, tag) 1626 cardbus_chipset_tag_t cc; 1627 cardbustag_t tag; 1628 { 1629 } 1630 1631 1632 /* 1633 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1634 * cardbustag_t tag, int offset) 1635 * This is the function to read the config space of a CardBus Card. 1636 * It works same as pci_conf_read. 1637 */ 1638 static cardbusreg_t 1639 pccbb_conf_read(cc, tag, offset) 1640 cardbus_chipset_tag_t cc; 1641 cardbustag_t tag; 1642 int offset; /* register offset */ 1643 { 1644 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1645 1646 return pci_conf_read(sc->sc_pc, tag, offset); 1647 } 1648 1649 1650 1651 /* 1652 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1653 * int offs, cardbusreg_t val) 1654 * This is the function to write the config space of a CardBus Card. 1655 * It works same as pci_conf_write. 1656 */ 1657 static void 1658 pccbb_conf_write(cc, tag, reg, val) 1659 cardbus_chipset_tag_t cc; 1660 cardbustag_t tag; 1661 int reg; /* register offset */ 1662 cardbusreg_t val; 1663 { 1664 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1665 1666 pci_conf_write(sc->sc_pc, tag, reg, val); 1667 } 1668 1669 1670 1671 1672 1673 #if 0 1674 STATIC int 1675 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1676 bus_addr_t start, bus_size_t size, 1677 bus_size_t align, bus_addr_t mask, /* address line width */ 1678 int speed, int flags, /* bus width */ 1679 bus_space_handle_t *iohp) 1680 #endif 1681 1682 1683 /* 1684 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1685 * bus_addr_t start, bus_size_t size, 1686 * bus_size_t align, 1687 * struct pcmcia_io_handle *pcihp 1688 * 1689 * This function only allocates I/O region for pccard. This function 1690 * never maps the allcated region to pccard I/O area. 1691 * 1692 * XXX: The interface of this function is not very good, I believe. 1693 */ 1694 STATIC int 1695 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1696 pcmcia_chipset_handle_t pch; 1697 bus_addr_t start; /* start address */ 1698 bus_size_t size; 1699 bus_size_t align; 1700 struct pcmcia_io_handle *pcihp; 1701 { 1702 struct pcic_handle *ph = (struct pcic_handle *)pch; 1703 bus_addr_t ioaddr; 1704 int flags = 0; 1705 bus_space_tag_t iot; 1706 bus_space_handle_t ioh; 1707 #if rbus 1708 rbus_tag_t rb; 1709 #endif 1710 if (align == 0) { 1711 align = size; /* XXX: funny??? */ 1712 } 1713 1714 1715 /* 1716 * Allocate some arbitrary I/O space. 1717 */ 1718 1719 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1720 1721 #if rbus 1722 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1723 if (rbus_space_alloc(rb, start, size, 0x3ff /* XXX: I assume all card decode lower 10 bits by its hardware */, 1724 align, 0, &ioaddr, &ioh)) { 1725 return 1; 1726 } 1727 #else 1728 if (start) { 1729 ioaddr = start; 1730 if (bus_space_map(iot, start, size, 0, &ioh)) { 1731 return 1; 1732 } 1733 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1734 (u_long) ioaddr, (u_long) size)); 1735 } else { 1736 flags |= PCMCIA_IO_ALLOCATED; 1737 if (bus_space_alloc(iot, 0x700/* ph->sc->sc_iobase */, 1738 0x800/* ph->sc->sc_iobase + ph->sc->sc_iosize*/, 1739 size, align, 0, 0, &ioaddr, &ioh)) { 1740 /* No room be able to be get. */ 1741 return 1; 1742 } 1743 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1744 (u_long) ioaddr, (u_long) size)); 1745 } 1746 #endif 1747 1748 pcihp->iot = iot; 1749 pcihp->ioh = ioh; 1750 pcihp->addr = ioaddr; 1751 pcihp->size = size; 1752 pcihp->flags = flags; 1753 1754 return 0; 1755 } 1756 1757 1758 1759 1760 1761 /* 1762 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1763 * struct pcmcia_io_handle *pcihp) 1764 * 1765 * This function only frees I/O region for pccard. 1766 * 1767 * XXX: The interface of this function is not very good, I believe. 1768 */ 1769 void 1770 pccbb_pcmcia_io_free(pch, pcihp) 1771 pcmcia_chipset_handle_t pch; 1772 struct pcmcia_io_handle *pcihp; 1773 { 1774 #if !rbus 1775 bus_space_tag_t iot = pcihp->iot; 1776 #endif 1777 bus_space_handle_t ioh = pcihp->ioh; 1778 bus_size_t size = pcihp->size; 1779 1780 #if rbus 1781 struct pccbb_softc *sc = (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1782 rbus_tag_t rb = sc->sc_rbus_iot; 1783 1784 rbus_space_free(rb, ioh, size, NULL); 1785 #else 1786 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1787 bus_space_free(iot, ioh, size); 1788 else 1789 bus_space_unmap(iot, ioh, size); 1790 #endif 1791 } 1792 1793 1794 1795 /* 1796 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1797 * bus_addr_t offset, bus_size_t size, 1798 * struct pcmcia_io_handle *pcihp, 1799 * int *windowp) 1800 * 1801 * This function maps the allocated I/O region to pccard. This function 1802 * never allocates any I/O region for pccard I/O area. I don't 1803 * understand why the original authors of pcmciabus separated alloc and 1804 * map. I believe the two must be unite. 1805 * 1806 * XXX: no wait timing control? 1807 */ 1808 int 1809 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1810 pcmcia_chipset_handle_t pch; 1811 int width; 1812 bus_addr_t offset; 1813 bus_size_t size; 1814 struct pcmcia_io_handle *pcihp; 1815 int *windowp; 1816 { 1817 struct pcic_handle *ph = (struct pcic_handle *) pch; 1818 bus_addr_t ioaddr = pcihp->addr + offset; 1819 int i, win; 1820 #if defined CBB_DEBUG 1821 static char *width_names[] = { "dynamic", "io8", "io16" }; 1822 #endif 1823 1824 /* Sanity check I/O handle. */ 1825 1826 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1827 panic("pccbb_pcmcia_io_map iot is bogus"); 1828 } 1829 1830 /* XXX Sanity check offset/size. */ 1831 1832 win = -1; 1833 for (i = 0; i < PCIC_IO_WINS; i++) { 1834 if ((ph->ioalloc & (1 << i)) == 0) { 1835 win = i; 1836 ph->ioalloc |= (1 << i); 1837 break; 1838 } 1839 } 1840 1841 if (win == -1) { 1842 return 1; 1843 } 1844 1845 *windowp = win; 1846 1847 /* XXX this is pretty gross */ 1848 1849 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1850 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1851 1852 /* XXX wtf is this doing here? */ 1853 1854 #if 0 1855 printf(" port 0x%lx", (u_long) ioaddr); 1856 if (size > 1) { 1857 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1858 } 1859 #endif 1860 1861 ph->io[win].addr = ioaddr; 1862 ph->io[win].size = size; 1863 ph->io[win].width = width; 1864 1865 /* actual dirty register-value changing in the function below. */ 1866 pccbb_pcmcia_do_io_map(ph, win); 1867 1868 return 0; 1869 } 1870 1871 1872 1873 /* 1874 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1875 * 1876 * This function changes register-value to map I/O region for pccard. 1877 */ 1878 static void 1879 pccbb_pcmcia_do_io_map(ph, win) 1880 struct pcic_handle *ph; 1881 int win; 1882 { 1883 static u_int8_t pcic_iowidth[3] = { 1884 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1885 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_8BIT, 1886 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_16BIT, 1887 }; 1888 1889 #define PCIC_SIA_START_LOW 0 1890 #define PCIC_SIA_START_HIGH 1 1891 #define PCIC_SIA_STOP_LOW 2 1892 #define PCIC_SIA_STOP_HIGH 3 1893 1894 int regbase_win = 0x8 + win*0x04; 1895 u_int8_t ioctl, enable; 1896 1897 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1898 win, (long) ph->io[win].addr, (long) ph->io[win].size, 1899 ph->io[win].width * 8)); 1900 1901 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1902 ph->io[win].addr & 0xff); 1903 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1904 (ph->io[win].addr >> 8) & 0xff); 1905 1906 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1907 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1908 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1909 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1910 1911 ioctl = Pcic_read(ph, PCIC_IOCTL); 1912 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1913 switch (win) { 1914 case 0: 1915 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1916 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK); 1917 ioctl |= pcic_iowidth[ph->io[win].width]; 1918 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1919 break; 1920 case 1: 1921 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1922 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK); 1923 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1924 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1925 break; 1926 } 1927 Pcic_write(ph, PCIC_IOCTL, ioctl); 1928 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1929 #if defined CBB_DEBUG 1930 { 1931 u_int8_t start_low = Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1932 u_int8_t start_high = Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1933 u_int8_t stop_low = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1934 u_int8_t stop_high = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1935 printf(" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1936 start_low, start_high, stop_low, stop_high, ioctl, enable); 1937 } 1938 #endif 1939 } 1940 1941 1942 1943 /* 1944 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1945 * 1946 * This function unmapss I/O region. No return value. 1947 */ 1948 STATIC void 1949 pccbb_pcmcia_io_unmap(pch, win) 1950 pcmcia_chipset_handle_t pch; 1951 int win; 1952 { 1953 struct pcic_handle *ph = (struct pcic_handle *)pch; 1954 int reg; 1955 1956 if (win >= PCIC_IO_WINS || win < 0) { 1957 panic("pccbb_pcmcia_io_unmap: window out of range"); 1958 } 1959 1960 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1961 switch (win) { 1962 case 0: 1963 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1964 break; 1965 case 1: 1966 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1967 break; 1968 } 1969 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 1970 1971 ph->ioalloc &= ~(1 << win); 1972 } 1973 1974 1975 1976 1977 1978 /* 1979 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1980 * 1981 * This function enables the card. All information is stored in 1982 * the first argument, pcmcia_chipset_handle_t. 1983 */ 1984 static void 1985 pccbb_pcmcia_wait_ready(ph) 1986 struct pcic_handle *ph; 1987 { 1988 int i; 1989 1990 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 1991 Pcic_read(ph, PCIC_IF_STATUS))); 1992 1993 for (i = 0; i < 10000; i++) { 1994 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 1995 return; 1996 } 1997 delay(500); 1998 #ifdef CBB_DEBUG 1999 if ((i > 5000) && (i%100 == 99)) 2000 printf("."); 2001 #endif 2002 } 2003 2004 #ifdef DIAGNOSTIC 2005 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2006 Pcic_read(ph, PCIC_IF_STATUS)); 2007 #endif 2008 } 2009 2010 2011 2012 /* 2013 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2014 * 2015 * This function enables the card. All information is stored in 2016 * the first argument, pcmcia_chipset_handle_t. 2017 */ 2018 STATIC void 2019 pccbb_pcmcia_socket_enable(pch) 2020 pcmcia_chipset_handle_t pch; 2021 { 2022 struct pcic_handle *ph = (struct pcic_handle *)pch; 2023 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2024 int cardtype, win; 2025 u_int8_t power, intr; 2026 pcireg_t spsr; 2027 int voltage; 2028 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2029 2030 /* this bit is mostly stolen from pcic_attach_card */ 2031 2032 DPRINTF(("pccbb_pcmcia_socket_enable:\n")); 2033 2034 /* get card Vcc info */ 2035 2036 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2037 if (spsr & CB_SOCKET_STAT_5VCARD) { 2038 DPRINTF(("5V card\n")); 2039 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2040 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2041 DPRINTF(("3V card\n")); 2042 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2043 } else { 2044 printf("?V card, 0x%x\n", spsr); /* XXX */ 2045 return; 2046 } 2047 2048 /* assert reset bit */ 2049 2050 intr = Pcic_read(ph, PCIC_INTR); 2051 intr &= ~PCIC_INTR_RESET; 2052 intr |= PCIC_INTR_PCI; /* XXX */ 2053 Pcic_write(ph, PCIC_INTR, intr); 2054 2055 /* disable socket i/o: negate output enable bit */ 2056 2057 power = Pcic_read(ph, PCIC_PWRCTL); 2058 power &= ~PCIC_PWRCTL_OE; 2059 Pcic_write(ph, PCIC_PWRCTL, power); 2060 2061 /* power down the socket to reset it, clear the card reset pin */ 2062 2063 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2064 2065 /* 2066 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2067 * we are changing Vcc (Toff). 2068 */ 2069 /* delay(300*1000); too much */ 2070 2071 /* power up the socket */ 2072 pccbb_power(sc, voltage); 2073 2074 /* 2075 * wait 100ms until power raise (Tpr) and 20ms to become 2076 * stable (Tsu(Vcc)). 2077 * 2078 * some machines require some more time to be settled 2079 * (another 200ms is added here). 2080 */ 2081 /* delay((100 + 20 + 200)*1000); too much */ 2082 2083 power = Pcic_read(ph, PCIC_PWRCTL); 2084 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2085 2086 /* 2087 * hold RESET at least 10us. 2088 */ 2089 delay(10); 2090 delay(2*1000); /* XXX: TI1130 requires it. */ 2091 delay(20*1000); /* XXX: TI1130 requires it. */ 2092 2093 /* clear the reset flag */ 2094 2095 intr = Pcic_read(ph, PCIC_INTR); 2096 Pcic_write(ph, PCIC_INTR, intr | PCIC_INTR_RESET); 2097 2098 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2099 2100 delay(20000); 2101 2102 /* wait for the chip to finish initializing */ 2103 2104 pccbb_pcmcia_wait_ready(ph); 2105 2106 /* zero out the address windows */ 2107 2108 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2109 2110 /* set the card type */ 2111 2112 cardtype = pcmcia_card_gettype(ph->pcmcia); 2113 2114 intr = Pcic_read(ph, PCIC_INTR); 2115 intr &= ~PCIC_INTR_CARDTYPE_MASK; 2116 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2117 PCIC_INTR_CARDTYPE_IO : 2118 PCIC_INTR_CARDTYPE_MEM); 2119 Pcic_write(ph, PCIC_INTR, intr); 2120 2121 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2122 ph->ph_parent->dv_xname, ph->sock, 2123 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2124 2125 /* reinstall all the memory and io mappings */ 2126 2127 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2128 if (ph->memalloc & (1 << win)) { 2129 pccbb_pcmcia_do_mem_map(ph, win); 2130 } 2131 } 2132 2133 for (win = 0; win < PCIC_IO_WINS; ++win) { 2134 if (ph->ioalloc & (1 << win)) { 2135 pccbb_pcmcia_do_io_map(ph, win); 2136 } 2137 } 2138 } 2139 2140 2141 2142 /* 2143 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2144 * 2145 * This function disables the card. All information is stored in 2146 * the first argument, pcmcia_chipset_handle_t. 2147 */ 2148 STATIC void 2149 pccbb_pcmcia_socket_disable(pch) 2150 pcmcia_chipset_handle_t pch; 2151 { 2152 struct pcic_handle *ph = (struct pcic_handle *)pch; 2153 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2154 u_int8_t power, intr; 2155 2156 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2157 2158 /* reset signal asserting... */ 2159 2160 intr = Pcic_read(ph, PCIC_INTR); 2161 intr &= ~PCIC_INTR_RESET; 2162 Pcic_write(ph, PCIC_INTR, intr); 2163 delay(2*1000); 2164 2165 /* power down the socket */ 2166 power = Pcic_read(ph, PCIC_PWRCTL); 2167 power &= ~PCIC_PWRCTL_OE; 2168 Pcic_write(ph, PCIC_PWRCTL, power); 2169 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2170 2171 /* 2172 * wait 300ms until power fails (Tpf). 2173 */ 2174 delay(300 * 1000); 2175 } 2176 2177 2178 2179 /* 2180 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2181 * 2182 * This function detects whether a card is in the slot or not. 2183 * If a card is inserted, return 1. Otherwise, return 0. 2184 */ 2185 STATIC int 2186 pccbb_pcmcia_card_detect(pch) 2187 pcmcia_chipset_handle_t pch; 2188 { 2189 struct pcic_handle *ph = (struct pcic_handle *)pch; 2190 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2191 2192 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2193 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2194 } 2195 2196 2197 2198 #if 0 2199 STATIC int 2200 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2201 bus_addr_t start, bus_size_t size, 2202 bus_size_t align, 2203 int speed, int flags, /* bus width */ 2204 bus_space_tag_t *memtp 2205 bus_space_handle_t *memhp) 2206 #endif 2207 2208 2209 /* 2210 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2211 * bus_size_t size, 2212 * struct pcmcia_mem_handle *pcmhp) 2213 * 2214 * This function only allocates memory region for pccard. This 2215 * function never maps the allcated region to pccard memory area. 2216 * 2217 * XXX: Why the argument of start address is not in? 2218 */ 2219 STATIC int 2220 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2221 pcmcia_chipset_handle_t pch; 2222 bus_size_t size; 2223 struct pcmcia_mem_handle *pcmhp; 2224 { 2225 struct pcic_handle *ph = (struct pcic_handle *)pch; 2226 bus_space_handle_t memh; 2227 bus_addr_t addr; 2228 bus_size_t sizepg; 2229 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2230 #if rbus 2231 rbus_tag_t rb; 2232 #endif 2233 2234 /* out of sc->memh, allocate as many pages as necessary */ 2235 2236 /* convert size to PCIC pages */ 2237 /* 2238 This is not enough; when the requested region is on the 2239 page boundaries, this may calculate wrong result. 2240 */ 2241 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2242 #if 0 2243 if (sizepg > PCIC_MAX_MEM_PAGES) { 2244 return 1; 2245 } 2246 #endif 2247 2248 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2249 return 1; 2250 } 2251 2252 addr = 0; /* XXX gcc -Wuninitialized */ 2253 2254 #if rbus 2255 rb = sc->sc_rbus_memt; 2256 if (rbus_space_alloc(rb, 0, sizepg*PCIC_MEM_PAGESIZE, 2257 sizepg*PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 2258 0, &addr, &memh)) { 2259 return 1; 2260 } 2261 2262 #else 2263 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2264 sizepg*PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2265 0 /* boundary */, 0 /* flags */, 2266 &addr, &memh)) { 2267 return 1; 2268 } 2269 #endif 2270 2271 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2272 addr, size, sizepg*PCIC_MEM_PAGESIZE)); 2273 2274 pcmhp->memt = sc->sc_memt; 2275 pcmhp->memh = memh; 2276 pcmhp->addr = addr; 2277 pcmhp->size = size; 2278 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2279 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2280 pcmhp->mhandle = 0; 2281 /* No offset??? Funny. */ 2282 2283 return 0; 2284 } 2285 2286 2287 2288 2289 /* 2290 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2291 * struct pcmcia_mem_handle *pcmhp) 2292 * 2293 * This function release the memory space allocated by the fuction 2294 * pccbb_pcmcia_mem_alloc(). 2295 */ 2296 STATIC void 2297 pccbb_pcmcia_mem_free(pch, pcmhp) 2298 pcmcia_chipset_handle_t pch; 2299 struct pcmcia_mem_handle *pcmhp; 2300 { 2301 #if rbus 2302 struct pcic_handle *ph = (struct pcic_handle *)pch; 2303 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2304 2305 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2306 #else 2307 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2308 #endif 2309 } 2310 2311 2312 2313 2314 /* 2315 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2316 * 2317 * This function release the memory space allocated by the fuction 2318 * pccbb_pcmcia_mem_alloc(). 2319 */ 2320 STATIC void 2321 pccbb_pcmcia_do_mem_map(ph, win) 2322 struct pcic_handle *ph; 2323 int win; 2324 { 2325 int regbase_win; 2326 bus_addr_t phys_addr; 2327 bus_addr_t phys_end; 2328 2329 #define PCIC_SMM_START_LOW 0 2330 #define PCIC_SMM_START_HIGH 1 2331 #define PCIC_SMM_STOP_LOW 2 2332 #define PCIC_SMM_STOP_HIGH 3 2333 #define PCIC_CMA_LOW 4 2334 #define PCIC_CMA_HIGH 5 2335 2336 u_int8_t start_low, start_high = 0; 2337 u_int8_t stop_low, stop_high; 2338 u_int8_t off_low, off_high; 2339 u_int8_t mem_window; 2340 int reg; 2341 2342 regbase_win = 0x10 + win*0x08; 2343 2344 phys_addr = ph->mem[win].addr; 2345 phys_end = phys_addr + ph->mem[win].size; 2346 2347 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2348 phys_addr, phys_end, ph->mem[win].offset)); 2349 2350 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2351 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2352 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2353 2354 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; /* bit 19:12 */ 2355 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) /* bit 23:20 */ 2356 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2357 /* bit 31:24, for 32-bit address */ 2358 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; /* bit 31:24 */ 2359 2360 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2361 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2362 2363 if (((struct pccbb_softc *)ph->ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2364 Pcic_write(ph, 0x40 + win, mem_window); 2365 } 2366 2367 2368 #if 0 2369 /* XXX do I want 16 bit all the time? */ 2370 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 2371 #endif 2372 2373 2374 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2375 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2376 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2377 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2378 2379 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2380 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2381 2382 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2383 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2384 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2385 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2386 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2387 2388 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2389 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2390 2391 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2392 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2393 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2394 2395 #if defined CBB_DEBUG 2396 { 2397 int r1, r2, r3, r4, r5, r6, r7 = 0; 2398 2399 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2400 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2401 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2402 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2403 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2404 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2405 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2406 r7 = Pcic_read(ph, 0x40 + win); 2407 } 2408 2409 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2410 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2411 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2412 DPRINTF((" %02x",r7)); 2413 } 2414 DPRINTF(("\n")); 2415 } 2416 #endif 2417 } 2418 2419 2420 2421 2422 /* 2423 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2424 * bus_addr_t card_addr, bus_size_t size, 2425 * struct pcmcia_mem_handle *pcmhp, 2426 * bus_addr_t *offsetp, int *windowp) 2427 * 2428 * This function maps memory space allocated by the fuction 2429 * pccbb_pcmcia_mem_alloc(). 2430 */ 2431 STATIC int 2432 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2433 pcmcia_chipset_handle_t pch; 2434 int kind; 2435 bus_addr_t card_addr; 2436 bus_size_t size; 2437 struct pcmcia_mem_handle *pcmhp; 2438 bus_addr_t *offsetp; 2439 int *windowp; 2440 { 2441 struct pcic_handle *ph = (struct pcic_handle *)pch; 2442 bus_addr_t busaddr; 2443 long card_offset; 2444 int win; 2445 2446 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2447 if ((ph->memalloc & (1 << win)) == 0) { 2448 ph->memalloc |= (1 << win); 2449 break; 2450 } 2451 } 2452 2453 if (win == PCIC_MEM_WINS) { 2454 return 1; 2455 } 2456 2457 *windowp = win; 2458 2459 /* XXX this is pretty gross */ 2460 2461 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2462 panic("pccbb_pcmcia_mem_map memt is bogus"); 2463 } 2464 2465 busaddr = pcmhp->addr; 2466 2467 /* 2468 * compute the address offset to the pcmcia address space for the 2469 * pcic. this is intentionally signed. The masks and shifts below 2470 * will cause TRT to happen in the pcic registers. Deal with making 2471 * sure the address is aligned, and return the alignment offset. 2472 */ 2473 2474 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2475 card_addr -= *offsetp; 2476 2477 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2478 "%lx\n", win, (u_long)busaddr, (u_long)*offsetp, (u_long)size, 2479 (u_long)card_addr)); 2480 2481 /* 2482 * include the offset in the size, and decrement size by one, since 2483 * the hw wants start/stop 2484 */ 2485 size += *offsetp - 1; 2486 2487 card_offset = (((long) card_addr) - ((long) busaddr)); 2488 2489 ph->mem[win].addr = busaddr; 2490 ph->mem[win].size = size; 2491 ph->mem[win].offset = card_offset; 2492 ph->mem[win].kind = kind; 2493 2494 pccbb_pcmcia_do_mem_map(ph, win); 2495 2496 return 0; 2497 } 2498 2499 2500 2501 /* 2502 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2503 * int window) 2504 * 2505 * This function unmaps memory space which mapped by the fuction 2506 * pccbb_pcmcia_mem_map(). 2507 */ 2508 STATIC void 2509 pccbb_pcmcia_mem_unmap(pch, window) 2510 pcmcia_chipset_handle_t pch; 2511 int window; 2512 { 2513 struct pcic_handle *ph = (struct pcic_handle *)pch; 2514 int reg; 2515 2516 if (window >= PCIC_MEM_WINS) { 2517 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2518 } 2519 2520 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2521 reg &= ~(1 << window); 2522 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2523 2524 ph->memalloc &= ~(1 << window); 2525 } 2526 2527 2528 2529 #if defined PCCBB_PCMCIA_POLL 2530 struct pccbb_poll_str { 2531 void *arg; 2532 int (* func) __P((void *)); 2533 int level; 2534 struct pcic_handle *ph; 2535 int count; 2536 int num; 2537 }; 2538 2539 static struct pccbb_poll_str pccbb_poll[10]; 2540 static int pccbb_poll_n = 0; 2541 2542 static void pccbb_pcmcia_poll __P((void *arg)); 2543 2544 static void 2545 pccbb_pcmcia_poll(arg) 2546 void *arg; 2547 { 2548 struct pccbb_poll_str *poll = arg; 2549 struct pcic_handle *ph = poll->ph; 2550 struct pccbb_softc *sc = ph->sc; 2551 int s; 2552 u_int32_t spsr; /* socket present-state reg */ 2553 2554 timeout(pccbb_pcmcia_poll, arg, hz*2); 2555 switch (poll->level) { 2556 case IPL_NET: 2557 s = splnet(); 2558 break; 2559 case IPL_BIO: 2560 s = splbio(); 2561 break; 2562 case IPL_TTY: /* fallthrough */ 2563 default: 2564 s = spltty(); 2565 break; 2566 } 2567 2568 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2569 2570 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2571 if (!(spsr & 0x40)) /* CINT low */ 2572 #else 2573 if (1) 2574 #endif 2575 { 2576 if ((*poll->func)(poll->arg) > 0) { 2577 ++poll->count; 2578 // printf("intr: reported from poller, 0x%x\n", spsr); 2579 #if defined LEVEL2 2580 } else { 2581 printf("intr: miss! 0x%x\n", spsr); 2582 #endif 2583 } 2584 } 2585 splx(s); 2586 } 2587 #endif /* defined CB_PCMCIA_POLL */ 2588 2589 2590 2591 /* 2592 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2593 * struct pcmcia_function *pf, 2594 * int ipl, 2595 * int (*func)(void *), 2596 * void *arg); 2597 * 2598 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2599 */ 2600 STATIC void * 2601 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2602 pcmcia_chipset_handle_t pch; 2603 struct pcmcia_function *pf; 2604 int ipl; 2605 int (*func) __P((void *)); 2606 void *arg; 2607 { 2608 struct pcic_handle *ph = (struct pcic_handle *)pch; 2609 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2610 pci_intr_handle_t handle; 2611 void *ih; 2612 2613 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2614 /* what should I do? */ 2615 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2616 DPRINTF(("%s does not provide edge nor pulse interrupt\n", 2617 sc->sc_dev.dv_xname)); 2618 return NULL; 2619 } 2620 /* 2621 * XXX Noooooo! The interrupt flag must set properly!! 2622 * dumb pcmcia driver!! 2623 */ 2624 } 2625 2626 if (pci_intr_map(sc->sc_pc, sc->sc_intrtag, sc->sc_intrpin, 2627 sc->sc_intrline, &handle)) { 2628 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 2629 return NULL; 2630 } 2631 DPRINTF(("pccbb_pcmcia_intr_establish: line %d, handle %d\n", 2632 sc->sc_intrline, handle)); 2633 2634 if (NULL != (ih = pci_intr_establish(sc->sc_pc, handle, ipl, func, arg))) 2635 { 2636 u_int32_t cbctrl; 2637 2638 if ((CB_TI113X == sc->sc_chipset)) { 2639 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 2640 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* PCI functional intr req */ 2641 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 2642 } 2643 } 2644 #if defined PCCBB_PCMCIA_POLL 2645 if (pccbb_poll_n < 10) { 2646 pccbb_poll[pccbb_poll_n].arg = arg; 2647 pccbb_poll[pccbb_poll_n].func = func; 2648 pccbb_poll[pccbb_poll_n].level = ipl; 2649 pccbb_poll[pccbb_poll_n].count = 0; 2650 pccbb_poll[pccbb_poll_n].num = pccbb_poll_n; 2651 pccbb_poll[pccbb_poll_n].ph = ph; 2652 timeout(pccbb_pcmcia_poll, &pccbb_poll[pccbb_poll_n++], hz*2); 2653 printf("polling set\n"); 2654 } 2655 #endif 2656 #if defined SHOW_REGS 2657 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 2658 #endif 2659 2660 return ih; 2661 } 2662 2663 2664 2665 2666 /* 2667 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2668 * void *ih) 2669 * 2670 * This function disables PC-Card interrupt. 2671 */ 2672 STATIC void 2673 pccbb_pcmcia_intr_disestablish(pch, ih) 2674 pcmcia_chipset_handle_t pch; 2675 void *ih; 2676 { 2677 struct pcic_handle *ph = (struct pcic_handle *)pch; 2678 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2679 2680 pci_intr_disestablish(sc->sc_pc, ih); 2681 } 2682 2683 2684 2685 2686 #if rbus 2687 /* 2688 * static int 2689 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2690 * bus_addr_t addr, bus_size_t size, 2691 * bus_addr_t mask, bus_size_t align, 2692 * int flags, bus_addr_t *addrp; 2693 * bus_space_handle_t *bshp) 2694 * 2695 * This function allocates a portion of memory or io space for 2696 * clients. This function is called from CardBus card drivers. 2697 */ 2698 static int 2699 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2700 cardbus_chipset_tag_t ct; 2701 rbus_tag_t rb; 2702 bus_addr_t addr; 2703 bus_size_t size; 2704 bus_addr_t mask; 2705 bus_size_t align; 2706 int flags; 2707 bus_addr_t *addrp; 2708 bus_space_handle_t *bshp; 2709 { 2710 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2711 2712 DPRINTF(("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", addr, size, mask, align)); 2713 2714 if (align == 0) { 2715 align = size; 2716 } 2717 2718 if (rb->rb_bt == sc->sc_memt) { 2719 if (align < 16) { 2720 return 1; 2721 } 2722 } else if (rb->rb_bt == sc->sc_iot) { 2723 if (align < 4) { 2724 return 1; 2725 } 2726 } else { 2727 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2728 rb->rb_bt)); 2729 return 1; 2730 /* XXX: panic here? */ 2731 } 2732 2733 /* XXX: hack for avoiding ISA image */ 2734 if (mask < 0x3ff) { 2735 mask = 0x3ff; 2736 addr = 0x300; 2737 } 2738 2739 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2740 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2741 return 1; 2742 } 2743 2744 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2745 2746 return 0; 2747 } 2748 2749 2750 2751 2752 2753 /* 2754 * static int 2755 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2756 * bus_space_handle_t *bshp, bus_size_t size); 2757 * 2758 * This function is called from CardBus card drivers. 2759 */ 2760 static int 2761 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2762 cardbus_chipset_tag_t ct; 2763 rbus_tag_t rb; 2764 bus_space_handle_t bsh; 2765 bus_size_t size; 2766 { 2767 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2768 bus_space_tag_t bt = rb->rb_bt; 2769 2770 pccbb_close_win(sc, bt, bsh, size); 2771 2772 if (bt == sc->sc_memt) { 2773 } else if (bt == sc->sc_iot) { 2774 } else { 2775 return 1; 2776 /* XXX: panic here? */ 2777 } 2778 2779 return rbus_space_free(rb, bsh, size, NULL); 2780 } 2781 #endif /* rbus */ 2782 2783 2784 #if rbus 2785 2786 static int 2787 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2788 struct pccbb_softc *sc; 2789 bus_space_tag_t bst; 2790 bus_addr_t addr; 2791 bus_size_t size; 2792 bus_space_handle_t bsh; 2793 int flags; 2794 { 2795 struct pccbb_win_chain **top; 2796 bus_addr_t align; 2797 2798 top = &sc->sc_iowindow; 2799 align = 0x04; 2800 if (sc->sc_memt == bst) { 2801 top = &sc->sc_memwindow; 2802 align = 0x1000; 2803 DPRINTF(("using memory window, %x %x %x\n\n", 2804 sc->sc_iot, sc->sc_memt, bst)); 2805 } 2806 2807 if (pccbb_winlist_insert(top, addr, size, bsh, flags)) { 2808 printf("winlist insert fails:\n"); 2809 } 2810 pccbb_winset(align, sc, bst); 2811 2812 return 0; 2813 } 2814 2815 2816 2817 static int 2818 pccbb_close_win(sc, bst, bsh, size) 2819 struct pccbb_softc *sc; 2820 bus_space_tag_t bst; 2821 bus_space_handle_t bsh; 2822 bus_size_t size; 2823 { 2824 struct pccbb_win_chain **top; 2825 bus_addr_t align; 2826 2827 top = &sc->sc_iowindow; 2828 align = 0x04; 2829 if (sc->sc_memt == bst) { 2830 top = &sc->sc_memwindow; 2831 align = 0x1000; 2832 } 2833 2834 if (pccbb_winlist_delete(top, bsh, size)) { 2835 printf("winlist delete fails:\n"); 2836 } 2837 pccbb_winset(align, sc, bst); 2838 2839 return 0; 2840 } 2841 2842 2843 static int 2844 pccbb_winlist_insert(top, start, size, bsh, flags) 2845 struct pccbb_win_chain **top; 2846 bus_addr_t start; 2847 bus_size_t size; 2848 bus_space_handle_t bsh; 2849 int flags; 2850 { 2851 struct pccbb_win_chain *chainp = *top; 2852 struct pccbb_win_chain *before = *top; 2853 struct pccbb_win_chain *elem; 2854 2855 if (*top == NULL) { 2856 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2857 return 1; /* fail */ 2858 } 2859 2860 elem->wc_start = start; 2861 elem->wc_end = start + size - 1; 2862 elem->wc_handle = bsh; 2863 elem->wc_flags = flags; 2864 2865 *top = elem; 2866 elem->wc_next = NULL; 2867 return 0; 2868 } 2869 2870 for(; chainp && chainp->wc_start <= start; chainp = chainp->wc_next) { 2871 before = chainp; 2872 } 2873 2874 if (chainp != NULL) { 2875 if (chainp->wc_start < start + size) { 2876 printf("fatal! 0x%lx 0x%lx\n", chainp->wc_start, start+size); 2877 return 1; 2878 } 2879 } 2880 if ((before != *top) && (before->wc_end >= start)) { 2881 printf("fatal!! 0x%lx 0x%lx\n", before->wc_end, start); 2882 return 1; 2883 } 2884 2885 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2886 return 1; /* fail */ 2887 } 2888 2889 elem->wc_start = start; 2890 elem->wc_end = start + size - 1; 2891 elem->wc_handle = bsh; 2892 elem->wc_flags = flags; 2893 2894 elem->wc_next = chainp; 2895 if (chainp == *top) { 2896 *top = elem; 2897 } else { 2898 before->wc_next = elem; 2899 } 2900 return 0; 2901 } 2902 2903 2904 2905 2906 static int 2907 pccbb_winlist_delete(top, bsh, size) 2908 struct pccbb_win_chain **top; 2909 bus_space_handle_t bsh; 2910 bus_size_t size; 2911 { 2912 struct pccbb_win_chain *chainp = *top; 2913 struct pccbb_win_chain **before = top; 2914 2915 for (; chainp && chainp->wc_handle != bsh; chainp = chainp->wc_next) { 2916 before = &chainp->wc_next; 2917 } 2918 2919 if (chainp == NULL) { 2920 return 1; /* fail: no candidate to remove */ 2921 } 2922 2923 if (chainp->wc_end - chainp->wc_start != size - 1) { 2924 printf("fatal!!! 0x%lx\n", chainp->wc_start); 2925 return 1; /* fail: no candidate to remove */ 2926 } 2927 2928 *before = chainp->wc_next; 2929 free(chainp, M_DEVBUF); 2930 2931 return 0; 2932 } 2933 2934 2935 2936 static void 2937 pccbb_winset(align, sc, bst) 2938 bus_addr_t align; 2939 struct pccbb_softc *sc; 2940 bus_space_tag_t bst; 2941 { 2942 pci_chipset_tag_t pc; 2943 pcitag_t tag; 2944 bus_addr_t mask = ~(align - 1); 2945 struct { 2946 cardbusreg_t win_start; 2947 cardbusreg_t win_limit; 2948 int win_flags; 2949 } win[2]; 2950 struct pccbb_win_chain *chainp; 2951 int offs; 2952 2953 win[0].win_start = 0xffffffff; 2954 win[0].win_limit = 0; 2955 win[1].win_start = 0xffffffff; 2956 win[1].win_limit = 0; 2957 2958 chainp = sc->sc_iowindow; 2959 offs = 0x2c; 2960 if (sc->sc_memt == bst) { 2961 chainp = sc->sc_memwindow; 2962 offs = 0x1c; 2963 } 2964 2965 if (chainp) { 2966 win[0].win_start = chainp->wc_start & mask; 2967 win[0].win_limit = chainp->wc_end & mask; 2968 win[0].win_flags = chainp->wc_flags; 2969 chainp = chainp->wc_next; 2970 } 2971 2972 for(; chainp; chainp = chainp->wc_next) { 2973 if (win[1].win_start == 0xffffffff) { 2974 /* window 1 is not used */ 2975 if ((win[0].win_flags == chainp->wc_flags) && 2976 (win[0].win_limit + align >= (chainp->wc_start & mask))) { 2977 /* concatinate */ 2978 win[0].win_limit = chainp->wc_end & mask; 2979 } else { 2980 /* make new window */ 2981 win[1].win_start = chainp->wc_start & mask; 2982 win[1].win_limit = chainp->wc_end & mask; 2983 win[1].win_flags = chainp->wc_flags; 2984 } 2985 continue; 2986 } 2987 2988 /* Both windows are engagad. */ 2989 if (win[0].win_flags == win[1].win_flags) { 2990 /* same flags */ 2991 if (win[0].win_flags == chainp->wc_flags) { 2992 2993 win[1].win_limit = chainp->wc_end & mask; 2994 2995 if (win[1].win_start - (win[0].win_limit + align) 2996 < (chainp->wc_start & mask) - (win[1].win_limit + align)) { 2997 win[0].win_limit = win[1].win_limit; 2998 win[1].win_start = chainp->wc_start & mask; 2999 } 3000 } else { 3001 /* different flags */ 3002 3003 /* concatinate win0 and win1 */ 3004 win[0].win_limit = win[1].win_limit; 3005 /* allocate win[1] to new space */ 3006 win[1].win_start = chainp->wc_start & mask; 3007 win[1].win_limit = chainp->wc_end & mask; 3008 win[1].win_flags = chainp->wc_flags; 3009 } 3010 } else { 3011 /* the flags of win[0] and win[1] is different */ 3012 if (win[0].win_flags == chainp->wc_flags) { 3013 win[0].win_limit = chainp->wc_end & mask; 3014 } else { 3015 win[1].win_limit = chainp->wc_end & mask; 3016 } 3017 } 3018 } 3019 3020 pc = sc->sc_pc; 3021 tag = sc->sc_tag; 3022 pci_conf_write(pc, tag, offs, win[0].win_start); 3023 pci_conf_write(pc, tag, offs+4, win[0].win_limit); 3024 pci_conf_write(pc, tag, offs+8, win[1].win_start); 3025 pci_conf_write(pc, tag, offs+12, win[1].win_limit); 3026 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3027 pci_conf_read(pc, tag, offs), 3028 pci_conf_read(pc, tag, offs+4) + align, 3029 pci_conf_read(pc, tag, offs+8), 3030 pci_conf_read(pc, tag, offs+12) + align)); 3031 3032 if (bst == sc->sc_memt) { 3033 if (win[0].win_start & PCCBB_MEM_CACHABLE) { 3034 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3035 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3036 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3037 } 3038 if (win[1].win_start & PCCBB_MEM_CACHABLE) { 3039 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3040 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3041 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3042 } 3043 } 3044 } 3045 3046 #endif /* rbus */ 3047
Indexes created Fri Sep 26 20:09:58 GMT 2025