pccbb.c revision 1.61.2.1
1 /* $NetBSD: pccbb.c,v 1.61.2.1 2001/06/21 20:05:00 nathanw Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/reboot.h> /* for bootverbose */ 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 #include <sys/proc.h> 57 58 #include <machine/intr.h> 59 #include <machine/bus.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/pccbbreg.h> 66 67 #include <dev/cardbus/cardslotvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 71 #include <dev/pcmcia/pcmciareg.h> 72 #include <dev/pcmcia/pcmciavar.h> 73 74 #include <dev/ic/i82365reg.h> 75 #include <dev/ic/i82365var.h> 76 #include <dev/pci/pccbbvar.h> 77 78 #include "locators.h" 79 80 #ifndef __NetBSD_Version__ 81 struct cfdriver cbb_cd = { 82 NULL, "cbb", DV_DULL 83 }; 84 #endif 85 86 #if defined CBB_DEBUG 87 #define DPRINTF(x) printf x 88 #define STATIC 89 #else 90 #define DPRINTF(x) 91 #define STATIC static 92 #endif 93 94 /* 95 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 96 * if you want to wait more than 1 ms. 97 */ 98 #define DELAY_MS(time, param) \ 99 do { \ 100 if (cold == 0) { \ 101 int tick = (hz*(time))/1000; \ 102 \ 103 if (tick <= 1) { \ 104 tick = 2; \ 105 } \ 106 tsleep((void *)(param), PCATCH, "pccbb", tick); \ 107 } else { \ 108 delay((time)*1000); \ 109 } \ 110 } while (0) 111 112 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 113 void pccbbattach __P((struct device *, struct device *, void *)); 114 int pccbbintr __P((void *)); 115 static void pci113x_insert __P((void *)); 116 static int pccbbintr_function __P((struct pccbb_softc *)); 117 118 static int pccbb_detect_card __P((struct pccbb_softc *)); 119 120 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 121 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset __P((struct pccbb_softc *)); 126 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 127 STATIC int cbbprint __P((void *, const char *)); 128 129 static int cb_chipset __P((u_int32_t, int *)); 130 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 131 struct pcmciabus_attach_args *)); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 134 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 135 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 136 #endif 137 138 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 139 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 140 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 141 #if !rbus 142 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 143 u_int32_t)); 144 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 145 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 146 u_int32_t)); 147 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc)); 151 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 152 153 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc)); 155 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 156 157 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 158 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 159 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 160 int)); 161 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 162 cardbusreg_t)); 163 static void pccbb_chipinit __P((struct pccbb_softc *)); 164 165 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 166 struct pcmcia_mem_handle *)); 167 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 168 struct pcmcia_mem_handle *)); 169 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 171 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 172 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 173 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 174 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *)); 176 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *)); 178 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 179 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 180 struct pcmcia_function *, int, int (*)(void *), void *)); 181 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 182 void *)); 183 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 184 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 185 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 186 187 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 188 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 189 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 190 static void pccbb_powerhook __P((int, void *)); 191 192 /* bus-space allocation and deallocation functions */ 193 #if rbus 194 195 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 196 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 197 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 198 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 199 bus_space_handle_t, bus_size_t)); 200 201 #endif /* rbus */ 202 203 #if rbus 204 205 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 206 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 207 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_space_handle_t, bus_size_t)); 209 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 210 bus_size_t, bus_space_handle_t, int)); 211 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 212 bus_space_handle_t, bus_size_t)); 213 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 214 bus_space_tag_t)); 215 void pccbb_winlist_show(struct pccbb_win_chain *); 216 217 #endif /* rbus */ 218 219 /* for config_defer */ 220 static void pccbb_pci_callback __P((struct device *)); 221 222 #if defined SHOW_REGS 223 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 224 bus_space_tag_t memt, bus_space_handle_t memh)); 225 #endif 226 227 struct cfattach cbb_pci_ca = { 228 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 229 }; 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_card_detect 245 }; 246 247 #if rbus 248 static struct cardbus_functions pccbb_funcs = { 249 pccbb_rbus_cb_space_alloc, 250 pccbb_rbus_cb_space_free, 251 pccbb_cb_intr_establish, 252 pccbb_cb_intr_disestablish, 253 pccbb_ctrl, 254 pccbb_power, 255 pccbb_make_tag, 256 pccbb_free_tag, 257 pccbb_conf_read, 258 pccbb_conf_write, 259 }; 260 #else 261 static struct cardbus_functions pccbb_funcs = { 262 pccbb_ctrl, 263 pccbb_power, 264 pccbb_mem_open, 265 pccbb_mem_close, 266 pccbb_io_open, 267 pccbb_io_close, 268 pccbb_cb_intr_establish, 269 pccbb_cb_intr_disestablish, 270 pccbb_make_tag, 271 pccbb_conf_read, 272 pccbb_conf_write, 273 }; 274 #endif 275 276 int 277 pcicbbmatch(parent, match, aux) 278 struct device *parent; 279 struct cfdata *match; 280 void *aux; 281 { 282 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 283 284 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 285 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 286 PCI_INTERFACE(pa->pa_class) == 0) { 287 return 1; 288 } 289 290 return 0; 291 } 292 293 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 294 | ((prod) << PCI_PRODUCT_SHIFT)) 295 296 const struct yenta_chipinfo { 297 pcireg_t yc_id; /* vendor tag | product tag */ 298 int yc_chiptype; 299 int yc_flags; 300 } yc_chipsets[] = { 301 /* Texas Instruments chips */ 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 329 /* Ricoh chips */ 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 331 PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 341 PCCBB_PCMCIA_MEM_32}, 342 343 /* Toshiba products */ 344 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 345 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 347 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 349 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 351 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 352 353 /* Cirrus Logic products */ 354 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 355 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 357 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 358 359 /* sentinel, or Generic chip */ 360 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 361 }; 362 363 static int 364 cb_chipset(pci_id, flagp) 365 u_int32_t pci_id; 366 int *flagp; 367 { 368 const struct yenta_chipinfo *yc; 369 370 /* Loop over except the last default entry. */ 371 for (yc = yc_chipsets; yc < yc_chipsets + 372 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 373 if (pci_id == yc->yc_id) 374 break; 375 376 if (flagp != NULL) 377 *flagp = yc->yc_flags; 378 379 return (yc->yc_chiptype); 380 } 381 382 static void 383 pccbb_shutdown(void *arg) 384 { 385 struct pccbb_softc *sc = arg; 386 pcireg_t command; 387 388 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 389 390 /* 391 * turn off power 392 * 393 * XXX - do not turn off power if chipset is TI 113X because 394 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 395 */ 396 if (sc->sc_chipset != CB_TI113X) { 397 pccbb_power((cardbus_chipset_tag_t)sc, 398 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 399 } 400 401 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 402 0); 403 404 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 405 406 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 407 PCI_COMMAND_MASTER_ENABLE); 408 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 409 410 } 411 412 void 413 pccbbattach(parent, self, aux) 414 struct device *parent; 415 struct device *self; 416 void *aux; 417 { 418 struct pccbb_softc *sc = (void *)self; 419 struct pci_attach_args *pa = aux; 420 pci_chipset_tag_t pc = pa->pa_pc; 421 pcireg_t busreg, reg, sock_base; 422 bus_addr_t sockbase; 423 char devinfo[256]; 424 int flags; 425 426 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 427 428 pci_devinfo(pa->pa_id, 0, 0, devinfo); 429 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 430 #ifdef CBB_DEBUG 431 printf(" (chipflags %x)", flags); 432 #endif 433 printf("\n"); 434 435 TAILQ_INIT(&sc->sc_memwindow); 436 TAILQ_INIT(&sc->sc_iowindow); 437 438 #if rbus 439 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 440 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 441 #endif /* rbus */ 442 443 sc->sc_base_memh = 0; 444 445 /* 446 * MAP socket registers and ExCA registers on memory-space 447 * When no valid address is set on socket base registers (on pci 448 * config space), get it not polite way. 449 */ 450 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 451 452 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 453 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 454 /* The address must be valid. */ 455 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 456 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 457 printf("%s: can't map socket base address 0x%x\n", 458 sc->sc_dev.dv_xname, sock_base); 459 /* 460 * I think it's funny: socket base registers must be 461 * mapped on memory space, but ... 462 */ 463 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 464 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 465 NULL)) { 466 printf("%s: can't map socket base address" 467 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 468 (unsigned long)sockbase); 469 /* give up... allocate reg space via rbus. */ 470 sc->sc_base_memh = 0; 471 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 472 } 473 } else { 474 DPRINTF(("%s: socket base address 0x%lx\n", 475 sc->sc_dev.dv_xname, sockbase)); 476 } 477 } 478 479 sc->sc_mem_start = 0; /* XXX */ 480 sc->sc_mem_end = 0xffffffff; /* XXX */ 481 482 /* 483 * When interrupt isn't routed correctly, give up probing cbb and do 484 * not kill pcic-compatible port. 485 */ 486 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 487 printf("%s: NOT USED because of unconfigured interrupt\n", 488 sc->sc_dev.dv_xname); 489 return; 490 } 491 492 /* 493 * When bus number isn't set correctly, give up using 32-bit CardBus 494 * mode. 495 */ 496 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 497 #if notyet 498 if (((busreg >> 8) & 0xff) == 0) { 499 printf("%s: CardBus support disabled because of unconfigured bus number\n", 500 sc->sc_dev.dv_xname); 501 flags |= PCCBB_PCMCIA_16BITONLY; 502 } 503 #endif 504 505 /* pccbb_machdep.c end */ 506 507 #if defined CBB_DEBUG 508 { 509 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 510 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 511 intrname[pa->pa_intrpin], pa->pa_intrline); 512 } 513 #endif 514 515 /* setup softc */ 516 sc->sc_pc = pc; 517 sc->sc_iot = pa->pa_iot; 518 sc->sc_memt = pa->pa_memt; 519 sc->sc_dmat = pa->pa_dmat; 520 sc->sc_tag = pa->pa_tag; 521 sc->sc_function = pa->pa_function; 522 sc->sc_sockbase = sock_base; 523 sc->sc_busnum = busreg; 524 525 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 526 527 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 528 529 shutdownhook_establish(pccbb_shutdown, sc); 530 531 /* Disable legacy register mapping. */ 532 switch (sc->sc_chipset) { 533 case CB_RX5C46X: /* fallthrough */ 534 #if 0 535 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 536 case CB_RX5C47X: 537 #endif 538 /* 539 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 540 * cannot be disabled by substituting 0 into PCI_LEGACY 541 * register. Ricoh CardBus bridges have special bits on Bridge 542 * control reg (addr 0x3e on PCI config space). 543 */ 544 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 545 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 546 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 547 break; 548 549 default: 550 /* XXX I don't know proper way to kill legacy I/O. */ 551 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 552 break; 553 } 554 555 config_defer(self, pccbb_pci_callback); 556 } 557 558 559 560 561 /* 562 * static void pccbb_pci_callback(struct device *self) 563 * 564 * The actual attach routine: get memory space for YENTA register 565 * space, setup YENTA register and route interrupt. 566 * 567 * This function should be deferred because this device may obtain 568 * memory space dynamically. This function must avoid obtaining 569 * memory area which has already kept for another device. 570 */ 571 static void 572 pccbb_pci_callback(self) 573 struct device *self; 574 { 575 struct pccbb_softc *sc = (void *)self; 576 pci_chipset_tag_t pc = sc->sc_pc; 577 bus_space_tag_t base_memt; 578 bus_space_handle_t base_memh; 579 u_int32_t maskreg; 580 pci_intr_handle_t ih; 581 const char *intrstr = NULL; 582 bus_addr_t sockbase; 583 struct cbslot_attach_args cba; 584 struct pcmciabus_attach_args paa; 585 struct cardslot_attach_args caa; 586 struct cardslot_softc *csc; 587 588 if (0 == sc->sc_base_memh) { 589 /* The socket registers aren't mapped correctly. */ 590 #if rbus 591 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 592 (sc->sc_chipset == CB_RX5C47X 593 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 594 0, &sockbase, &sc->sc_base_memh)) { 595 return; 596 } 597 sc->sc_base_memt = sc->sc_memt; 598 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 599 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 600 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 601 PCI_SOCKBASE))); 602 #else 603 sc->sc_base_memt = sc->sc_memt; 604 #if !defined CBB_PCI_BASE 605 #define CBB_PCI_BASE 0x20000000 606 #endif 607 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 608 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 609 /* cannot allocate memory space */ 610 return; 611 } 612 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 613 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 614 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 615 sc->sc_tag, PCI_SOCKBASE))); 616 #endif 617 } 618 619 /* bus bridge initialization */ 620 pccbb_chipinit(sc); 621 622 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 623 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 624 625 /* CSC Interrupt: Card detect interrupt on */ 626 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 627 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 628 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 629 /* reset interrupt */ 630 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 631 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 632 633 /* clear data structure for child device interrupt handlers */ 634 sc->sc_pil = NULL; 635 sc->sc_pil_intr_enable = 1; 636 637 /* Map and establish the interrupt. */ 638 if (pci_intr_map(&sc->sc_pa, &ih)) { 639 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 640 return; 641 } 642 intrstr = pci_intr_string(pc, ih); 643 644 /* 645 * XXX pccbbintr should be called under the priority lower 646 * than any other hard interrputs. 647 */ 648 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 649 650 if (sc->sc_ih == NULL) { 651 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 652 if (intrstr != NULL) { 653 printf(" at %s", intrstr); 654 } 655 printf("\n"); 656 return; 657 } 658 659 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 660 powerhook_establish(pccbb_powerhook, sc); 661 662 { 663 u_int32_t sockstat = 664 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 665 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 666 sc->sc_flags |= CBB_CARDEXIST; 667 } 668 } 669 670 /* 671 * attach cardbus 672 */ 673 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 674 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 675 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 676 677 /* initialize cbslot_attach */ 678 cba.cba_busname = "cardbus"; 679 cba.cba_iot = sc->sc_iot; 680 cba.cba_memt = sc->sc_memt; 681 cba.cba_dmat = sc->sc_dmat; 682 cba.cba_bus = (busreg >> 8) & 0x0ff; 683 cba.cba_cc = (void *)sc; 684 cba.cba_cf = &pccbb_funcs; 685 cba.cba_intrline = sc->sc_pa.pa_intrline; 686 687 #if rbus 688 cba.cba_rbus_iot = sc->sc_rbus_iot; 689 cba.cba_rbus_memt = sc->sc_rbus_memt; 690 #endif 691 692 cba.cba_cacheline = PCI_CACHELINE(bhlc); 693 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 694 695 if (bootverbose) { 696 printf("%s: cacheline 0x%x lattimer 0x%x\n", 697 sc->sc_dev.dv_xname, cba.cba_cacheline, 698 cba.cba_lattimer); 699 printf("%s: bhlc 0x%x lscp 0x%x\n", 700 sc->sc_dev.dv_xname, bhlc, busreg); 701 } 702 #if defined SHOW_REGS 703 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 704 sc->sc_base_memh); 705 #endif 706 } 707 708 pccbb_pcmcia_attach_setup(sc, &paa); 709 caa.caa_cb_attach = NULL; 710 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 711 caa.caa_cb_attach = &cba; 712 } 713 caa.caa_16_attach = &paa; 714 caa.caa_ph = &sc->sc_pcmcia_h; 715 716 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 717 DPRINTF(("pccbbattach: found cardslot\n")); 718 sc->sc_csc = csc; 719 } 720 721 return; 722 } 723 724 725 726 727 728 /* 729 * static void pccbb_chipinit(struct pccbb_softc *sc) 730 * 731 * This function initialize YENTA chip registers listed below: 732 * 1) PCI command reg, 733 * 2) PCI and CardBus latency timer, 734 * 3) route PCI interrupt, 735 * 4) close all memory and io windows. 736 */ 737 static void 738 pccbb_chipinit(sc) 739 struct pccbb_softc *sc; 740 { 741 pci_chipset_tag_t pc = sc->sc_pc; 742 pcitag_t tag = sc->sc_tag; 743 pcireg_t reg; 744 745 /* 746 * Set PCI command reg. 747 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 748 */ 749 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 750 /* I believe it is harmless. */ 751 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 752 PCI_COMMAND_MASTER_ENABLE); 753 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 754 755 /* 756 * Set CardBus latency timer. 757 */ 758 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 759 if (PCI_CB_LATENCY(reg) < 0x20) { 760 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 761 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 762 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 763 } 764 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 765 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 766 767 /* 768 * Set PCI latency timer. 769 */ 770 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 771 if (PCI_LATTIMER(reg) < 0x10) { 772 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 773 reg |= (0x10 << PCI_LATTIMER_SHIFT); 774 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 775 } 776 DPRINTF(("PCI latency timer 0x%x (%x)\n", 777 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 778 779 780 /* Route functional interrupts to PCI. */ 781 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 782 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 783 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 784 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 785 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 786 787 switch (sc->sc_chipset) { 788 case CB_TI113X: 789 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 790 /* This bit is shared, but may read as 0 on some chips, so set 791 it explicitly on both functions. */ 792 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 793 /* CSC intr enable */ 794 reg |= PCI113X_CBCTRL_PCI_CSC; 795 /* functional intr prohibit | prohibit ISA routing */ 796 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 797 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 798 break; 799 800 case CB_TI12XX: 801 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 802 reg |= PCI12XX_SYSCTRL_VCCPROT; 803 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 804 break; 805 806 case CB_TOPIC95B: 807 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 808 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 809 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 810 811 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 812 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 813 sc->sc_dev.dv_xname, reg)); 814 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 815 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 816 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 817 DPRINTF(("0x%x\n", reg)); 818 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 819 break; 820 } 821 822 /* Close all memory and I/O windows. */ 823 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 824 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 825 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 826 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 827 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 828 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 829 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 830 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 831 832 /* reset 16-bit pcmcia bus */ 833 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 834 0x800 + PCIC_INTR, 835 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 836 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 837 838 /* turn of power */ 839 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 840 } 841 842 843 844 845 /* 846 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 847 * struct pcmciabus_attach_args *paa) 848 * 849 * This function attaches 16-bit PCcard bus. 850 */ 851 STATIC void 852 pccbb_pcmcia_attach_setup(sc, paa) 853 struct pccbb_softc *sc; 854 struct pcmciabus_attach_args *paa; 855 { 856 struct pcic_handle *ph = &sc->sc_pcmcia_h; 857 #if rbus 858 rbus_tag_t rb; 859 #endif 860 861 /* initialize pcmcia part in pccbb_softc */ 862 ph->ph_parent = (struct device *)sc; 863 ph->sock = sc->sc_function; 864 ph->flags = 0; 865 ph->shutdown = 0; 866 ph->ih_irq = sc->sc_pa.pa_intrline; 867 ph->ph_bus_t = sc->sc_base_memt; 868 ph->ph_bus_h = sc->sc_base_memh; 869 ph->ph_read = pccbb_pcmcia_read; 870 ph->ph_write = pccbb_pcmcia_write; 871 sc->sc_pct = &pccbb_pcmcia_funcs; 872 873 /* 874 * We need to do a few things here: 875 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 876 * setting the IRQ numbers to 0. 877 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 878 * routing of CSC interrupts (e.g. card removal) to PCI while in 879 * PCMCIA mode. We just leave this set all the time. 880 * 3) Enable card insertion/removal interrupts in case the chip also 881 * needs that while in PCMCIA mode. 882 * 4) Clear any pending CSC interrupt. 883 */ 884 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 885 if (sc->sc_chipset == CB_TI113X) { 886 Pcic_write(ph, PCIC_CSC_INTR, 0); 887 } else { 888 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 889 Pcic_read(ph, PCIC_CSC); 890 } 891 892 /* initialize pcmcia bus attachment */ 893 paa->paa_busname = "pcmcia"; 894 paa->pct = sc->sc_pct; 895 paa->pch = ph; 896 paa->iobase = 0; /* I don't use them */ 897 paa->iosize = 0; 898 #if rbus 899 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 900 paa->iobase = rb->rb_start + rb->rb_offset; 901 paa->iosize = rb->rb_end - rb->rb_start; 902 #endif 903 904 return; 905 } 906 907 #if 0 908 STATIC void 909 pccbb_pcmcia_attach_card(ph) 910 struct pcic_handle *ph; 911 { 912 if (ph->flags & PCIC_FLAG_CARDP) { 913 panic("pccbb_pcmcia_attach_card: already attached"); 914 } 915 916 /* call the MI attach function */ 917 pcmcia_card_attach(ph->pcmcia); 918 919 ph->flags |= PCIC_FLAG_CARDP; 920 } 921 922 STATIC void 923 pccbb_pcmcia_detach_card(ph, flags) 924 struct pcic_handle *ph; 925 int flags; 926 { 927 if (!(ph->flags & PCIC_FLAG_CARDP)) { 928 panic("pccbb_pcmcia_detach_card: already detached"); 929 } 930 931 ph->flags &= ~PCIC_FLAG_CARDP; 932 933 /* call the MI detach function */ 934 pcmcia_card_detach(ph->pcmcia, flags); 935 } 936 #endif 937 938 /* 939 * int pccbbintr(arg) 940 * void *arg; 941 * This routine handles the interrupt from Yenta PCI-CardBus bridge 942 * itself. 943 */ 944 int 945 pccbbintr(arg) 946 void *arg; 947 { 948 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 949 u_int32_t sockevent, sockstate; 950 bus_space_tag_t memt = sc->sc_base_memt; 951 bus_space_handle_t memh = sc->sc_base_memh; 952 struct pcic_handle *ph = &sc->sc_pcmcia_h; 953 954 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 955 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 956 Pcic_read(ph, PCIC_CSC); 957 958 if (sockevent == 0) { 959 /* This intr is not for me: it may be for my child devices. */ 960 if (sc->sc_pil_intr_enable) { 961 return pccbbintr_function(sc); 962 } else { 963 return 0; 964 } 965 } 966 967 if (sockevent & CB_SOCKET_EVENT_CD) { 968 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 969 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 970 /* A card should be removed. */ 971 if (sc->sc_flags & CBB_CARDEXIST) { 972 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 973 sockevent)); 974 DPRINTF((" card removed, 0x%08x\n", sockstate)); 975 sc->sc_flags &= ~CBB_CARDEXIST; 976 if (sc->sc_csc->sc_status & 977 CARDSLOT_STATUS_CARD_16) { 978 #if 0 979 struct pcic_handle *ph = 980 &sc->sc_pcmcia_h; 981 982 pcmcia_card_deactivate(ph->pcmcia); 983 pccbb_pcmcia_socket_disable(ph); 984 pccbb_pcmcia_detach_card(ph, 985 DETACH_FORCE); 986 #endif 987 cardslot_event_throw(sc->sc_csc, 988 CARDSLOT_EVENT_REMOVAL_16); 989 } else if (sc->sc_csc->sc_status & 990 CARDSLOT_STATUS_CARD_CB) { 991 /* Cardbus intr removed */ 992 cardslot_event_throw(sc->sc_csc, 993 CARDSLOT_EVENT_REMOVAL_CB); 994 } 995 } 996 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 997 /* 998 * The pccbbintr may called from powerdown hook when 999 * the system resumed, to detect the card 1000 * insertion/removal during suspension. 1001 */ 1002 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1003 if (sc->sc_flags & CBB_INSERTING) { 1004 callout_stop(&sc->sc_insert_ch); 1005 } 1006 callout_reset(&sc->sc_insert_ch, hz / 10, 1007 pci113x_insert, sc); 1008 sc->sc_flags |= CBB_INSERTING; 1009 } 1010 } 1011 1012 return (1); 1013 } 1014 1015 /* 1016 * static int pccbbintr_function(struct pccbb_softc *sc) 1017 * 1018 * This function calls each interrupt handler registered at the 1019 * bridge. The interrupt handlers are called in registered order. 1020 */ 1021 static int 1022 pccbbintr_function(sc) 1023 struct pccbb_softc *sc; 1024 { 1025 int retval = 0, val; 1026 struct pccbb_intrhand_list *pil; 1027 int s, splchanged; 1028 1029 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1030 /* 1031 * XXX priority change. gross. I use if-else 1032 * sentense instead of switch-case sentense because of 1033 * avoiding duplicate case value error. More than one 1034 * IPL_XXX use same value. It depends on 1035 * implimentation. 1036 */ 1037 splchanged = 1; 1038 if (pil->pil_level == IPL_SERIAL) { 1039 s = splserial(); 1040 } else if (pil->pil_level == IPL_HIGH) { 1041 s = splhigh(); 1042 } else if (pil->pil_level == IPL_CLOCK) { 1043 s = splclock(); 1044 } else if (pil->pil_level == IPL_AUDIO) { 1045 s = splaudio(); 1046 } else if (pil->pil_level == IPL_IMP) { 1047 s = splvm(); /* XXX */ 1048 } else if (pil->pil_level == IPL_TTY) { 1049 s = spltty(); 1050 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1051 s = splsoftserial(); 1052 } else if (pil->pil_level == IPL_NET) { 1053 s = splnet(); 1054 } else { 1055 splchanged = 0; 1056 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1057 } 1058 1059 val = (*pil->pil_func)(pil->pil_arg); 1060 1061 if (splchanged != 0) { 1062 splx(s); 1063 } 1064 1065 retval = retval == 1 ? 1 : 1066 retval == 0 ? val : val != 0 ? val : retval; 1067 } 1068 1069 return retval; 1070 } 1071 1072 static void 1073 pci113x_insert(arg) 1074 void *arg; 1075 { 1076 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1077 u_int32_t sockevent, sockstate; 1078 1079 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1080 CB_SOCKET_EVENT); 1081 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1082 CB_SOCKET_STAT); 1083 1084 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1085 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1086 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1087 sc->sc_flags |= CBB_CARDEXIST; 1088 /* call pccard interrupt handler here */ 1089 if (sockstate & CB_SOCKET_STAT_16BIT) { 1090 /* 16-bit card found */ 1091 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1092 cardslot_event_throw(sc->sc_csc, 1093 CARDSLOT_EVENT_INSERTION_16); 1094 } else if (sockstate & CB_SOCKET_STAT_CB) { 1095 /* cardbus card found */ 1096 /* cardbus_attach_card(sc->sc_csc); */ 1097 cardslot_event_throw(sc->sc_csc, 1098 CARDSLOT_EVENT_INSERTION_CB); 1099 } else { 1100 /* who are you? */ 1101 } 1102 } else { 1103 callout_reset(&sc->sc_insert_ch, hz / 10, 1104 pci113x_insert, sc); 1105 } 1106 } 1107 1108 #define PCCBB_PCMCIA_OFFSET 0x800 1109 static u_int8_t 1110 pccbb_pcmcia_read(ph, reg) 1111 struct pcic_handle *ph; 1112 int reg; 1113 { 1114 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1115 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1116 1117 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1118 PCCBB_PCMCIA_OFFSET + reg); 1119 } 1120 1121 static void 1122 pccbb_pcmcia_write(ph, reg, val) 1123 struct pcic_handle *ph; 1124 int reg; 1125 u_int8_t val; 1126 { 1127 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1128 val); 1129 1130 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1131 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1132 } 1133 1134 /* 1135 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1136 */ 1137 STATIC int 1138 pccbb_ctrl(ct, command) 1139 cardbus_chipset_tag_t ct; 1140 int command; 1141 { 1142 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1143 1144 switch (command) { 1145 case CARDBUS_CD: 1146 if (2 == pccbb_detect_card(sc)) { 1147 int retval = 0; 1148 int status = cb_detect_voltage(sc); 1149 if (PCCARD_VCC_5V & status) { 1150 retval |= CARDBUS_5V_CARD; 1151 } 1152 if (PCCARD_VCC_3V & status) { 1153 retval |= CARDBUS_3V_CARD; 1154 } 1155 if (PCCARD_VCC_XV & status) { 1156 retval |= CARDBUS_XV_CARD; 1157 } 1158 if (PCCARD_VCC_YV & status) { 1159 retval |= CARDBUS_YV_CARD; 1160 } 1161 return retval; 1162 } else { 1163 return 0; 1164 } 1165 break; 1166 case CARDBUS_RESET: 1167 return cb_reset(sc); 1168 break; 1169 case CARDBUS_IO_ENABLE: /* fallthrough */ 1170 case CARDBUS_IO_DISABLE: /* fallthrough */ 1171 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1172 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1173 case CARDBUS_BM_ENABLE: /* fallthrough */ 1174 case CARDBUS_BM_DISABLE: /* fallthrough */ 1175 return pccbb_cardenable(sc, command); 1176 break; 1177 } 1178 1179 return 0; 1180 } 1181 1182 /* 1183 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1184 * This function returns true when it succeeds and returns false when 1185 * it fails. 1186 */ 1187 STATIC int 1188 pccbb_power(ct, command) 1189 cardbus_chipset_tag_t ct; 1190 int command; 1191 { 1192 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1193 1194 u_int32_t status, sock_ctrl; 1195 bus_space_tag_t memt = sc->sc_base_memt; 1196 bus_space_handle_t memh = sc->sc_base_memh; 1197 1198 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1199 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1200 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1201 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1202 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1203 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1204 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1205 "UNKNOWN", 1206 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1207 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1208 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1209 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1210 "UNKNOWN", command)); 1211 1212 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1213 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1214 1215 switch (command & CARDBUS_VCCMASK) { 1216 case CARDBUS_VCC_UC: 1217 break; 1218 case CARDBUS_VCC_5V: 1219 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1220 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1221 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1222 } else { 1223 printf("%s: BAD voltage request: no 5 V card\n", 1224 sc->sc_dev.dv_xname); 1225 } 1226 break; 1227 case CARDBUS_VCC_3V: 1228 if (CB_SOCKET_STAT_3VCARD & status) { 1229 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1230 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1231 } else { 1232 printf("%s: BAD voltage request: no 3.3 V card\n", 1233 sc->sc_dev.dv_xname); 1234 } 1235 break; 1236 case CARDBUS_VCC_0V: 1237 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1238 break; 1239 default: 1240 return 0; /* power NEVER changed */ 1241 break; 1242 } 1243 1244 switch (command & CARDBUS_VPPMASK) { 1245 case CARDBUS_VPP_UC: 1246 break; 1247 case CARDBUS_VPP_0V: 1248 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1249 break; 1250 case CARDBUS_VPP_VCC: 1251 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1252 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1253 break; 1254 case CARDBUS_VPP_12V: 1255 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1256 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1257 break; 1258 } 1259 1260 #if 0 1261 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1262 #endif 1263 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1264 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1265 1266 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1267 printf 1268 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1269 sc->sc_dev.dv_xname, sock_ctrl, status); 1270 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1271 (command & CARDBUS_VCCMASK) == 1272 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1273 CARDBUS_VCCMASK) == 1274 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1275 CARDBUS_VCCMASK) == 1276 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1277 CARDBUS_VCCMASK) == 1278 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1279 CARDBUS_VCCMASK) == 1280 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1281 CARDBUS_VCCMASK) == 1282 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1283 (command & CARDBUS_VPPMASK) == 1284 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1285 CARDBUS_VPPMASK) == 1286 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1287 CARDBUS_VPPMASK) == 1288 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1289 CARDBUS_VPPMASK) == 1290 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1291 #if 0 1292 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1293 u_int32_t force = 1294 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1295 /* Reset Bad Vcc request */ 1296 force &= ~CB_SOCKET_FORCE_BADVCC; 1297 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1298 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1299 CB_SOCKET_STAT)); 1300 return 1; 1301 } 1302 #endif 1303 return 0; 1304 } 1305 1306 /* 1307 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1308 * time is 20 ms, some PC-Card bridge requires longer duration. 1309 */ 1310 #if 0 /* XXX called on interrupt context */ 1311 DELAY_MS(300, sc); 1312 #else 1313 delay(300 * 1000); 1314 #endif 1315 1316 return 1; /* power changed correctly */ 1317 } 1318 1319 #if defined CB_PCMCIA_POLL 1320 struct cb_poll_str { 1321 void *arg; 1322 int (*func) __P((void *)); 1323 int level; 1324 pccard_chipset_tag_t ct; 1325 int count; 1326 struct callout poll_ch; 1327 }; 1328 1329 static struct cb_poll_str cb_poll[10]; 1330 static int cb_poll_n = 0; 1331 1332 static void cb_pcmcia_poll __P((void *arg)); 1333 1334 static void 1335 cb_pcmcia_poll(arg) 1336 void *arg; 1337 { 1338 struct cb_poll_str *poll = arg; 1339 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1340 struct pccbb_softc *sc = psc->cpc_parent; 1341 int s; 1342 u_int32_t spsr; /* socket present-state reg */ 1343 1344 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1345 switch (poll->level) { 1346 case IPL_NET: 1347 s = splnet(); 1348 break; 1349 case IPL_BIO: 1350 s = splbio(); 1351 break; 1352 case IPL_TTY: /* fallthrough */ 1353 default: 1354 s = spltty(); 1355 break; 1356 } 1357 1358 spsr = 1359 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1360 CB_SOCKET_STAT); 1361 1362 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1363 if (!(spsr & 0x40)) { /* CINT low */ 1364 #else 1365 if (1) { 1366 #endif 1367 if ((*poll->func) (poll->arg) == 1) { 1368 ++poll->count; 1369 printf("intr: reported from poller, 0x%x\n", spsr); 1370 #if defined LEVEL2 1371 } else { 1372 printf("intr: miss! 0x%x\n", spsr); 1373 #endif 1374 } 1375 } 1376 splx(s); 1377 } 1378 #endif /* defined CB_PCMCIA_POLL */ 1379 1380 /* 1381 * static int pccbb_detect_card(struct pccbb_softc *sc) 1382 * return value: 0 if no card exists. 1383 * 1 if 16-bit card exists. 1384 * 2 if cardbus card exists. 1385 */ 1386 static int 1387 pccbb_detect_card(sc) 1388 struct pccbb_softc *sc; 1389 { 1390 bus_space_handle_t base_memh = sc->sc_base_memh; 1391 bus_space_tag_t base_memt = sc->sc_base_memt; 1392 u_int32_t sockstat = 1393 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1394 int retval = 0; 1395 1396 /* CD1 and CD2 asserted */ 1397 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1398 /* card must be present */ 1399 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1400 /* NOTACARD DEASSERTED */ 1401 if (CB_SOCKET_STAT_CB & sockstat) { 1402 /* CardBus mode */ 1403 retval = 2; 1404 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1405 /* 16-bit mode */ 1406 retval = 1; 1407 } 1408 } 1409 } 1410 return retval; 1411 } 1412 1413 /* 1414 * STATIC int cb_reset(struct pccbb_softc *sc) 1415 * This function resets CardBus card. 1416 */ 1417 STATIC int 1418 cb_reset(sc) 1419 struct pccbb_softc *sc; 1420 { 1421 /* 1422 * Reset Assert at least 20 ms 1423 * Some machines request longer duration. 1424 */ 1425 int reset_duration = 1426 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1427 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1428 1429 /* Reset bit Assert (bit 6 at 0x3E) */ 1430 bcr |= CB_BCR_RESET_ENABLE; 1431 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1432 DELAY_MS(reset_duration, sc); 1433 1434 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1435 /* Reset bit Deassert (bit 6 at 0x3E) */ 1436 bcr &= ~CB_BCR_RESET_ENABLE; 1437 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1438 DELAY_MS(reset_duration, sc); 1439 } 1440 /* No card found on the slot. Keep Reset. */ 1441 return 1; 1442 } 1443 1444 /* 1445 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1446 * This function detect card Voltage. 1447 */ 1448 STATIC int 1449 cb_detect_voltage(sc) 1450 struct pccbb_softc *sc; 1451 { 1452 u_int32_t psr; /* socket present-state reg */ 1453 bus_space_tag_t iot = sc->sc_base_memt; 1454 bus_space_handle_t ioh = sc->sc_base_memh; 1455 int vol = PCCARD_VCC_UKN; /* set 0 */ 1456 1457 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1458 1459 if (0x400u & psr) { 1460 vol |= PCCARD_VCC_5V; 1461 } 1462 if (0x800u & psr) { 1463 vol |= PCCARD_VCC_3V; 1464 } 1465 1466 return vol; 1467 } 1468 1469 STATIC int 1470 cbbprint(aux, pcic) 1471 void *aux; 1472 const char *pcic; 1473 { 1474 /* 1475 struct cbslot_attach_args *cba = aux; 1476 1477 if (cba->cba_slot >= 0) { 1478 printf(" slot %d", cba->cba_slot); 1479 } 1480 */ 1481 return UNCONF; 1482 } 1483 1484 /* 1485 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1486 * This function enables and disables the card 1487 */ 1488 STATIC int 1489 pccbb_cardenable(sc, function) 1490 struct pccbb_softc *sc; 1491 int function; 1492 { 1493 u_int32_t command = 1494 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1495 1496 DPRINTF(("pccbb_cardenable:")); 1497 switch (function) { 1498 case CARDBUS_IO_ENABLE: 1499 command |= PCI_COMMAND_IO_ENABLE; 1500 break; 1501 case CARDBUS_IO_DISABLE: 1502 command &= ~PCI_COMMAND_IO_ENABLE; 1503 break; 1504 case CARDBUS_MEM_ENABLE: 1505 command |= PCI_COMMAND_MEM_ENABLE; 1506 break; 1507 case CARDBUS_MEM_DISABLE: 1508 command &= ~PCI_COMMAND_MEM_ENABLE; 1509 break; 1510 case CARDBUS_BM_ENABLE: 1511 command |= PCI_COMMAND_MASTER_ENABLE; 1512 break; 1513 case CARDBUS_BM_DISABLE: 1514 command &= ~PCI_COMMAND_MASTER_ENABLE; 1515 break; 1516 default: 1517 return 0; 1518 } 1519 1520 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1521 DPRINTF((" command reg 0x%x\n", command)); 1522 return 1; 1523 } 1524 1525 #if !rbus 1526 /* 1527 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1528 */ 1529 static int 1530 pccbb_io_open(ct, win, start, end) 1531 cardbus_chipset_tag_t ct; 1532 int win; 1533 u_int32_t start, end; 1534 { 1535 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1536 int basereg; 1537 int limitreg; 1538 1539 if ((win < 0) || (win > 2)) { 1540 #if defined DIAGNOSTIC 1541 printf("cardbus_io_open: window out of range %d\n", win); 1542 #endif 1543 return 0; 1544 } 1545 1546 basereg = win * 8 + 0x2c; 1547 limitreg = win * 8 + 0x30; 1548 1549 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1550 start, basereg, end, limitreg)); 1551 1552 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1553 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1554 return 1; 1555 } 1556 1557 /* 1558 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1559 */ 1560 static int 1561 pccbb_io_close(ct, win) 1562 cardbus_chipset_tag_t ct; 1563 int win; 1564 { 1565 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1566 int basereg; 1567 int limitreg; 1568 1569 if ((win < 0) || (win > 2)) { 1570 #if defined DIAGNOSTIC 1571 printf("cardbus_io_close: window out of range %d\n", win); 1572 #endif 1573 return 0; 1574 } 1575 1576 basereg = win * 8 + 0x2c; 1577 limitreg = win * 8 + 0x30; 1578 1579 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1580 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1581 return 1; 1582 } 1583 1584 /* 1585 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1586 */ 1587 static int 1588 pccbb_mem_open(ct, win, start, end) 1589 cardbus_chipset_tag_t ct; 1590 int win; 1591 u_int32_t start, end; 1592 { 1593 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1594 int basereg; 1595 int limitreg; 1596 1597 if ((win < 0) || (win > 2)) { 1598 #if defined DIAGNOSTIC 1599 printf("cardbus_mem_open: window out of range %d\n", win); 1600 #endif 1601 return 0; 1602 } 1603 1604 basereg = win * 8 + 0x1c; 1605 limitreg = win * 8 + 0x20; 1606 1607 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1608 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1609 return 1; 1610 } 1611 1612 /* 1613 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1614 */ 1615 static int 1616 pccbb_mem_close(ct, win) 1617 cardbus_chipset_tag_t ct; 1618 int win; 1619 { 1620 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1621 int basereg; 1622 int limitreg; 1623 1624 if ((win < 0) || (win > 2)) { 1625 #if defined DIAGNOSTIC 1626 printf("cardbus_mem_close: window out of range %d\n", win); 1627 #endif 1628 return 0; 1629 } 1630 1631 basereg = win * 8 + 0x1c; 1632 limitreg = win * 8 + 0x20; 1633 1634 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1635 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1636 return 1; 1637 } 1638 #endif 1639 1640 /* 1641 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1642 * int irq, 1643 * int level, 1644 * int (* func) __P((void *)), 1645 * void *arg) 1646 * 1647 * This function registers an interrupt handler at the bridge, in 1648 * order not to call the interrupt handlers of child devices when 1649 * a card-deletion interrupt occurs. 1650 * 1651 * The arguments irq and level are not used. 1652 */ 1653 static void * 1654 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1655 cardbus_chipset_tag_t ct; 1656 int irq, level; 1657 int (*func) __P((void *)); 1658 void *arg; 1659 { 1660 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1661 1662 return pccbb_intr_establish(sc, irq, level, func, arg); 1663 } 1664 1665 1666 /* 1667 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1668 * void *ih) 1669 * 1670 * This function removes an interrupt handler pointed by ih. 1671 */ 1672 static void 1673 pccbb_cb_intr_disestablish(ct, ih) 1674 cardbus_chipset_tag_t ct; 1675 void *ih; 1676 { 1677 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1678 1679 pccbb_intr_disestablish(sc, ih); 1680 } 1681 1682 1683 /* 1684 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1685 * int irq, 1686 * int level, 1687 * int (* func) __P((void *)), 1688 * void *arg) 1689 * 1690 * This function registers an interrupt handler at the bridge, in 1691 * order not to call the interrupt handlers of child devices when 1692 * a card-deletion interrupt occurs. 1693 * 1694 * The arguments irq is not used because pccbb selects intr vector. 1695 */ 1696 static void * 1697 pccbb_intr_establish(sc, irq, level, func, arg) 1698 struct pccbb_softc *sc; 1699 int irq, level; 1700 int (*func) __P((void *)); 1701 void *arg; 1702 { 1703 struct pccbb_intrhand_list *pil, *newpil; 1704 pcireg_t reg; 1705 1706 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1707 1708 if (sc->sc_pil == NULL) { 1709 /* initialize bridge intr routing */ 1710 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1711 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1712 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1713 1714 switch (sc->sc_chipset) { 1715 case CB_TI113X: 1716 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1717 /* functional intr enabled */ 1718 reg |= PCI113X_CBCTRL_PCI_INTR; 1719 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1720 break; 1721 default: 1722 break; 1723 } 1724 } 1725 1726 /* 1727 * Allocate a room for interrupt handler structure. 1728 */ 1729 if (NULL == (newpil = 1730 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1731 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1732 return NULL; 1733 } 1734 1735 newpil->pil_func = func; 1736 newpil->pil_arg = arg; 1737 newpil->pil_level = level; 1738 newpil->pil_next = NULL; 1739 1740 if (sc->sc_pil == NULL) { 1741 sc->sc_pil = newpil; 1742 } else { 1743 for (pil = sc->sc_pil; pil->pil_next != NULL; 1744 pil = pil->pil_next); 1745 pil->pil_next = newpil; 1746 } 1747 1748 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1749 1750 return newpil; 1751 } 1752 1753 /* 1754 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1755 * void *ih) 1756 * 1757 * This function removes an interrupt handler pointed by ih. 1758 */ 1759 static void 1760 pccbb_intr_disestablish(sc, ih) 1761 struct pccbb_softc *sc; 1762 void *ih; 1763 { 1764 struct pccbb_intrhand_list *pil, **pil_prev; 1765 pcireg_t reg; 1766 1767 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1768 1769 pil_prev = &sc->sc_pil; 1770 1771 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1772 if (pil == ih) { 1773 *pil_prev = pil->pil_next; 1774 free(pil, M_DEVBUF); 1775 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1776 break; 1777 } 1778 pil_prev = &pil->pil_next; 1779 } 1780 1781 if (sc->sc_pil == NULL) { 1782 /* No interrupt handlers */ 1783 1784 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1785 1786 /* stop routing PCI intr */ 1787 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1788 reg |= CB_BCR_INTR_IREQ_ENABLE; 1789 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1790 1791 switch (sc->sc_chipset) { 1792 case CB_TI113X: 1793 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1794 /* functional intr disabled */ 1795 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1796 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1797 break; 1798 default: 1799 break; 1800 } 1801 } 1802 } 1803 1804 #if defined SHOW_REGS 1805 static void 1806 cb_show_regs(pc, tag, memt, memh) 1807 pci_chipset_tag_t pc; 1808 pcitag_t tag; 1809 bus_space_tag_t memt; 1810 bus_space_handle_t memh; 1811 { 1812 int i; 1813 printf("PCI config regs:"); 1814 for (i = 0; i < 0x50; i += 4) { 1815 if (i % 16 == 0) { 1816 printf("\n 0x%02x:", i); 1817 } 1818 printf(" %08x", pci_conf_read(pc, tag, i)); 1819 } 1820 for (i = 0x80; i < 0xb0; i += 4) { 1821 if (i % 16 == 0) { 1822 printf("\n 0x%02x:", i); 1823 } 1824 printf(" %08x", pci_conf_read(pc, tag, i)); 1825 } 1826 1827 if (memh == 0) { 1828 printf("\n"); 1829 return; 1830 } 1831 1832 printf("\nsocket regs:"); 1833 for (i = 0; i <= 0x10; i += 0x04) { 1834 printf(" %08x", bus_space_read_4(memt, memh, i)); 1835 } 1836 printf("\nExCA regs:"); 1837 for (i = 0; i < 0x08; ++i) { 1838 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1839 } 1840 printf("\n"); 1841 return; 1842 } 1843 #endif 1844 1845 /* 1846 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1847 * int busno, int devno, int function) 1848 * This is the function to make a tag to access config space of 1849 * a CardBus Card. It works same as pci_conf_read. 1850 */ 1851 static cardbustag_t 1852 pccbb_make_tag(cc, busno, devno, function) 1853 cardbus_chipset_tag_t cc; 1854 int busno, devno, function; 1855 { 1856 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1857 1858 return pci_make_tag(sc->sc_pc, busno, devno, function); 1859 } 1860 1861 static void 1862 pccbb_free_tag(cc, tag) 1863 cardbus_chipset_tag_t cc; 1864 cardbustag_t tag; 1865 { 1866 } 1867 1868 /* 1869 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1870 * cardbustag_t tag, int offset) 1871 * This is the function to read the config space of a CardBus Card. 1872 * It works same as pci_conf_read. 1873 */ 1874 static cardbusreg_t 1875 pccbb_conf_read(cc, tag, offset) 1876 cardbus_chipset_tag_t cc; 1877 cardbustag_t tag; 1878 int offset; /* register offset */ 1879 { 1880 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1881 1882 return pci_conf_read(sc->sc_pc, tag, offset); 1883 } 1884 1885 /* 1886 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1887 * int offs, cardbusreg_t val) 1888 * This is the function to write the config space of a CardBus Card. 1889 * It works same as pci_conf_write. 1890 */ 1891 static void 1892 pccbb_conf_write(cc, tag, reg, val) 1893 cardbus_chipset_tag_t cc; 1894 cardbustag_t tag; 1895 int reg; /* register offset */ 1896 cardbusreg_t val; 1897 { 1898 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1899 1900 pci_conf_write(sc->sc_pc, tag, reg, val); 1901 } 1902 1903 #if 0 1904 STATIC int 1905 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1906 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1907 int speed, int flags, 1908 bus_space_handle_t * iohp) 1909 #endif 1910 /* 1911 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1912 * bus_addr_t start, bus_size_t size, 1913 * bus_size_t align, 1914 * struct pcmcia_io_handle *pcihp 1915 * 1916 * This function only allocates I/O region for pccard. This function 1917 * never maps the allocated region to pccard I/O area. 1918 * 1919 * XXX: The interface of this function is not very good, I believe. 1920 */ 1921 STATIC int 1922 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1923 pcmcia_chipset_handle_t pch; 1924 bus_addr_t start; /* start address */ 1925 bus_size_t size; 1926 bus_size_t align; 1927 struct pcmcia_io_handle *pcihp; 1928 { 1929 struct pcic_handle *ph = (struct pcic_handle *)pch; 1930 bus_addr_t ioaddr; 1931 int flags = 0; 1932 bus_space_tag_t iot; 1933 bus_space_handle_t ioh; 1934 bus_addr_t mask; 1935 #if rbus 1936 rbus_tag_t rb; 1937 #endif 1938 if (align == 0) { 1939 align = size; /* XXX: funny??? */ 1940 } 1941 1942 if (start != 0) { 1943 /* XXX: assume all card decode lower 10 bits by its hardware */ 1944 mask = 0x3ff; 1945 } else { 1946 /* 1947 * calculate mask: 1948 * 1. get the most significant bit of size (call it msb). 1949 * 2. compare msb with the value of size. 1950 * 3. if size is larger, shift msb left once. 1951 * 4. obtain mask value to decrement msb. 1952 */ 1953 bus_size_t size_tmp = size; 1954 int shifts = 0; 1955 1956 mask = 1; 1957 while (size_tmp) { 1958 ++shifts; 1959 size_tmp >>= 1; 1960 } 1961 mask = (1 << shifts); 1962 if (mask < size) { 1963 mask <<= 1; 1964 } 1965 --mask; 1966 } 1967 1968 /* 1969 * Allocate some arbitrary I/O space. 1970 */ 1971 1972 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1973 1974 #if rbus 1975 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1976 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1977 return 1; 1978 } 1979 #else 1980 if (start) { 1981 ioaddr = start; 1982 if (bus_space_map(iot, start, size, 0, &ioh)) { 1983 return 1; 1984 } 1985 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1986 (u_long) ioaddr, (u_long) size)); 1987 } else { 1988 flags |= PCMCIA_IO_ALLOCATED; 1989 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1990 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1991 size, align, 0, 0, &ioaddr, &ioh)) { 1992 /* No room be able to be get. */ 1993 return 1; 1994 } 1995 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1996 (u_long) ioaddr, (u_long) size)); 1997 } 1998 #endif 1999 2000 pcihp->iot = iot; 2001 pcihp->ioh = ioh; 2002 pcihp->addr = ioaddr; 2003 pcihp->size = size; 2004 pcihp->flags = flags; 2005 2006 return 0; 2007 } 2008 2009 /* 2010 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2011 * struct pcmcia_io_handle *pcihp) 2012 * 2013 * This function only frees I/O region for pccard. 2014 * 2015 * XXX: The interface of this function is not very good, I believe. 2016 */ 2017 void 2018 pccbb_pcmcia_io_free(pch, pcihp) 2019 pcmcia_chipset_handle_t pch; 2020 struct pcmcia_io_handle *pcihp; 2021 { 2022 #if !rbus 2023 bus_space_tag_t iot = pcihp->iot; 2024 #endif 2025 bus_space_handle_t ioh = pcihp->ioh; 2026 bus_size_t size = pcihp->size; 2027 2028 #if rbus 2029 struct pccbb_softc *sc = 2030 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2031 rbus_tag_t rb = sc->sc_rbus_iot; 2032 2033 rbus_space_free(rb, ioh, size, NULL); 2034 #else 2035 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2036 bus_space_free(iot, ioh, size); 2037 else 2038 bus_space_unmap(iot, ioh, size); 2039 #endif 2040 } 2041 2042 /* 2043 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2044 * bus_addr_t offset, bus_size_t size, 2045 * struct pcmcia_io_handle *pcihp, 2046 * int *windowp) 2047 * 2048 * This function maps the allocated I/O region to pccard. This function 2049 * never allocates any I/O region for pccard I/O area. I don't 2050 * understand why the original authors of pcmciabus separated alloc and 2051 * map. I believe the two must be unite. 2052 * 2053 * XXX: no wait timing control? 2054 */ 2055 int 2056 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2057 pcmcia_chipset_handle_t pch; 2058 int width; 2059 bus_addr_t offset; 2060 bus_size_t size; 2061 struct pcmcia_io_handle *pcihp; 2062 int *windowp; 2063 { 2064 struct pcic_handle *ph = (struct pcic_handle *)pch; 2065 bus_addr_t ioaddr = pcihp->addr + offset; 2066 int i, win; 2067 #if defined CBB_DEBUG 2068 static char *width_names[] = { "dynamic", "io8", "io16" }; 2069 #endif 2070 2071 /* Sanity check I/O handle. */ 2072 2073 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2074 panic("pccbb_pcmcia_io_map iot is bogus"); 2075 } 2076 2077 /* XXX Sanity check offset/size. */ 2078 2079 win = -1; 2080 for (i = 0; i < PCIC_IO_WINS; i++) { 2081 if ((ph->ioalloc & (1 << i)) == 0) { 2082 win = i; 2083 ph->ioalloc |= (1 << i); 2084 break; 2085 } 2086 } 2087 2088 if (win == -1) { 2089 return 1; 2090 } 2091 2092 *windowp = win; 2093 2094 /* XXX this is pretty gross */ 2095 2096 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2097 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2098 2099 /* XXX wtf is this doing here? */ 2100 2101 #if 0 2102 printf(" port 0x%lx", (u_long) ioaddr); 2103 if (size > 1) { 2104 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2105 } 2106 #endif 2107 2108 ph->io[win].addr = ioaddr; 2109 ph->io[win].size = size; 2110 ph->io[win].width = width; 2111 2112 /* actual dirty register-value changing in the function below. */ 2113 pccbb_pcmcia_do_io_map(ph, win); 2114 2115 return 0; 2116 } 2117 2118 /* 2119 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2120 * 2121 * This function changes register-value to map I/O region for pccard. 2122 */ 2123 static void 2124 pccbb_pcmcia_do_io_map(ph, win) 2125 struct pcic_handle *ph; 2126 int win; 2127 { 2128 static u_int8_t pcic_iowidth[3] = { 2129 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2130 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2131 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2132 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2133 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2134 }; 2135 2136 #define PCIC_SIA_START_LOW 0 2137 #define PCIC_SIA_START_HIGH 1 2138 #define PCIC_SIA_STOP_LOW 2 2139 #define PCIC_SIA_STOP_HIGH 3 2140 2141 int regbase_win = 0x8 + win * 0x04; 2142 u_int8_t ioctl, enable; 2143 2144 DPRINTF( 2145 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2146 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2147 ph->io[win].width * 8)); 2148 2149 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2150 ph->io[win].addr & 0xff); 2151 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2152 (ph->io[win].addr >> 8) & 0xff); 2153 2154 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2155 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2156 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2157 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2158 2159 ioctl = Pcic_read(ph, PCIC_IOCTL); 2160 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2161 switch (win) { 2162 case 0: 2163 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2164 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2165 PCIC_IOCTL_IO0_DATASIZE_MASK); 2166 ioctl |= pcic_iowidth[ph->io[win].width]; 2167 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2168 break; 2169 case 1: 2170 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2171 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2172 PCIC_IOCTL_IO1_DATASIZE_MASK); 2173 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2174 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2175 break; 2176 } 2177 Pcic_write(ph, PCIC_IOCTL, ioctl); 2178 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2179 #if defined CBB_DEBUG 2180 { 2181 u_int8_t start_low = 2182 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2183 u_int8_t start_high = 2184 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2185 u_int8_t stop_low = 2186 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2187 u_int8_t stop_high = 2188 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2189 printf 2190 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2191 start_low, start_high, stop_low, stop_high, ioctl, enable); 2192 } 2193 #endif 2194 } 2195 2196 /* 2197 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2198 * 2199 * This function unmaps I/O region. No return value. 2200 */ 2201 STATIC void 2202 pccbb_pcmcia_io_unmap(pch, win) 2203 pcmcia_chipset_handle_t pch; 2204 int win; 2205 { 2206 struct pcic_handle *ph = (struct pcic_handle *)pch; 2207 int reg; 2208 2209 if (win >= PCIC_IO_WINS || win < 0) { 2210 panic("pccbb_pcmcia_io_unmap: window out of range"); 2211 } 2212 2213 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2214 switch (win) { 2215 case 0: 2216 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2217 break; 2218 case 1: 2219 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2220 break; 2221 } 2222 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2223 2224 ph->ioalloc &= ~(1 << win); 2225 } 2226 2227 /* 2228 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2229 * 2230 * This function enables the card. All information is stored in 2231 * the first argument, pcmcia_chipset_handle_t. 2232 */ 2233 static void 2234 pccbb_pcmcia_wait_ready(ph) 2235 struct pcic_handle *ph; 2236 { 2237 int i; 2238 2239 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2240 Pcic_read(ph, PCIC_IF_STATUS))); 2241 2242 for (i = 0; i < 2000; i++) { 2243 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2244 return; 2245 } 2246 DELAY_MS(2, ph->ph_parent); 2247 #ifdef CBB_DEBUG 2248 if ((i > 1000) && (i % 25 == 24)) 2249 printf("."); 2250 #endif 2251 } 2252 2253 #ifdef DIAGNOSTIC 2254 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2255 Pcic_read(ph, PCIC_IF_STATUS)); 2256 #endif 2257 } 2258 2259 /* 2260 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2261 * 2262 * This function enables the card. All information is stored in 2263 * the first argument, pcmcia_chipset_handle_t. 2264 */ 2265 STATIC void 2266 pccbb_pcmcia_socket_enable(pch) 2267 pcmcia_chipset_handle_t pch; 2268 { 2269 struct pcic_handle *ph = (struct pcic_handle *)pch; 2270 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2271 int cardtype, win; 2272 u_int8_t power, intr; 2273 pcireg_t spsr; 2274 int voltage; 2275 2276 /* this bit is mostly stolen from pcic_attach_card */ 2277 2278 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2279 2280 /* get card Vcc info */ 2281 2282 spsr = 2283 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2284 CB_SOCKET_STAT); 2285 if (spsr & CB_SOCKET_STAT_5VCARD) { 2286 DPRINTF(("5V card\n")); 2287 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2288 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2289 DPRINTF(("3V card\n")); 2290 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2291 } else { 2292 printf("?V card, 0x%x\n", spsr); /* XXX */ 2293 return; 2294 } 2295 2296 /* disable socket: negate output enable bit and power off */ 2297 2298 power = 0; 2299 Pcic_write(ph, PCIC_PWRCTL, power); 2300 2301 /* power down the socket to reset it, clear the card reset pin */ 2302 2303 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2304 2305 /* 2306 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2307 * we are changing Vcc (Toff). 2308 */ 2309 /* delay(300*1000); too much */ 2310 2311 /* assert reset bit */ 2312 intr = Pcic_read(ph, PCIC_INTR); 2313 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2314 Pcic_write(ph, PCIC_INTR, intr); 2315 2316 /* power up the socket and output enable */ 2317 power = Pcic_read(ph, PCIC_PWRCTL); 2318 power |= PCIC_PWRCTL_OE; 2319 Pcic_write(ph, PCIC_PWRCTL, power); 2320 pccbb_power(sc, voltage); 2321 2322 /* 2323 * hold RESET at least 20 ms: the spec says only 10 us is 2324 * enough, but TI1130 requires at least 20 ms. 2325 */ 2326 #if 0 /* XXX called on interrupt context */ 2327 DELAY_MS(20, sc); 2328 #else 2329 delay(20 * 1000); 2330 #endif 2331 2332 /* clear the reset flag */ 2333 2334 intr |= PCIC_INTR_RESET; 2335 Pcic_write(ph, PCIC_INTR, intr); 2336 2337 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2338 2339 #if 0 /* XXX called on interrupt context */ 2340 DELAY_MS(20, sc); 2341 #else 2342 delay(20 * 1000); 2343 #endif 2344 2345 /* wait for the chip to finish initializing */ 2346 2347 pccbb_pcmcia_wait_ready(ph); 2348 2349 /* zero out the address windows */ 2350 2351 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2352 2353 /* set the card type */ 2354 2355 cardtype = pcmcia_card_gettype(ph->pcmcia); 2356 2357 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2358 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2359 Pcic_write(ph, PCIC_INTR, intr); 2360 2361 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2362 ph->ph_parent->dv_xname, ph->sock, 2363 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2364 2365 /* reinstall all the memory and io mappings */ 2366 2367 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2368 if (ph->memalloc & (1 << win)) { 2369 pccbb_pcmcia_do_mem_map(ph, win); 2370 } 2371 } 2372 2373 for (win = 0; win < PCIC_IO_WINS; ++win) { 2374 if (ph->ioalloc & (1 << win)) { 2375 pccbb_pcmcia_do_io_map(ph, win); 2376 } 2377 } 2378 } 2379 2380 /* 2381 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2382 * 2383 * This function disables the card. All information is stored in 2384 * the first argument, pcmcia_chipset_handle_t. 2385 */ 2386 STATIC void 2387 pccbb_pcmcia_socket_disable(pch) 2388 pcmcia_chipset_handle_t pch; 2389 { 2390 struct pcic_handle *ph = (struct pcic_handle *)pch; 2391 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2392 u_int8_t power, intr; 2393 2394 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2395 2396 /* reset signal asserting... */ 2397 2398 intr = Pcic_read(ph, PCIC_INTR); 2399 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2400 Pcic_write(ph, PCIC_INTR, intr); 2401 delay(2 * 1000); 2402 2403 /* power down the socket */ 2404 power = Pcic_read(ph, PCIC_PWRCTL); 2405 power &= ~PCIC_PWRCTL_OE; 2406 Pcic_write(ph, PCIC_PWRCTL, power); 2407 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2408 /* 2409 * wait 300ms until power fails (Tpf). 2410 */ 2411 #if 0 /* XXX called on interrupt context */ 2412 DELAY_MS(300, sc); 2413 #else 2414 delay(300 * 1000); 2415 #endif 2416 } 2417 2418 /* 2419 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2420 * 2421 * This function detects whether a card is in the slot or not. 2422 * If a card is inserted, return 1. Otherwise, return 0. 2423 */ 2424 STATIC int 2425 pccbb_pcmcia_card_detect(pch) 2426 pcmcia_chipset_handle_t pch; 2427 { 2428 struct pcic_handle *ph = (struct pcic_handle *)pch; 2429 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2430 2431 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2432 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2433 } 2434 2435 #if 0 2436 STATIC int 2437 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2438 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2439 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2440 #endif 2441 /* 2442 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2443 * bus_size_t size, 2444 * struct pcmcia_mem_handle *pcmhp) 2445 * 2446 * This function only allocates memory region for pccard. This 2447 * function never maps the allocated region to pccard memory area. 2448 * 2449 * XXX: Why the argument of start address is not in? 2450 */ 2451 STATIC int 2452 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2453 pcmcia_chipset_handle_t pch; 2454 bus_size_t size; 2455 struct pcmcia_mem_handle *pcmhp; 2456 { 2457 struct pcic_handle *ph = (struct pcic_handle *)pch; 2458 bus_space_handle_t memh; 2459 bus_addr_t addr; 2460 bus_size_t sizepg; 2461 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2462 #if rbus 2463 rbus_tag_t rb; 2464 #endif 2465 2466 /* out of sc->memh, allocate as many pages as necessary */ 2467 2468 /* convert size to PCIC pages */ 2469 /* 2470 * This is not enough; when the requested region is on the page 2471 * boundaries, this may calculate wrong result. 2472 */ 2473 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2474 #if 0 2475 if (sizepg > PCIC_MAX_MEM_PAGES) { 2476 return 1; 2477 } 2478 #endif 2479 2480 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2481 return 1; 2482 } 2483 2484 addr = 0; /* XXX gcc -Wuninitialized */ 2485 2486 #if rbus 2487 rb = sc->sc_rbus_memt; 2488 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2489 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2490 &addr, &memh)) { 2491 return 1; 2492 } 2493 #else 2494 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2495 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2496 0, /* boundary */ 2497 0, /* flags */ 2498 &addr, &memh)) { 2499 return 1; 2500 } 2501 #endif 2502 2503 DPRINTF( 2504 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2505 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2506 2507 pcmhp->memt = sc->sc_memt; 2508 pcmhp->memh = memh; 2509 pcmhp->addr = addr; 2510 pcmhp->size = size; 2511 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2512 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2513 pcmhp->mhandle = 0; 2514 /* No offset??? Funny. */ 2515 2516 return 0; 2517 } 2518 2519 /* 2520 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2521 * struct pcmcia_mem_handle *pcmhp) 2522 * 2523 * This function release the memory space allocated by the function 2524 * pccbb_pcmcia_mem_alloc(). 2525 */ 2526 STATIC void 2527 pccbb_pcmcia_mem_free(pch, pcmhp) 2528 pcmcia_chipset_handle_t pch; 2529 struct pcmcia_mem_handle *pcmhp; 2530 { 2531 #if rbus 2532 struct pcic_handle *ph = (struct pcic_handle *)pch; 2533 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2534 2535 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2536 #else 2537 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2538 #endif 2539 } 2540 2541 /* 2542 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2543 * 2544 * This function release the memory space allocated by the function 2545 * pccbb_pcmcia_mem_alloc(). 2546 */ 2547 STATIC void 2548 pccbb_pcmcia_do_mem_map(ph, win) 2549 struct pcic_handle *ph; 2550 int win; 2551 { 2552 int regbase_win; 2553 bus_addr_t phys_addr; 2554 bus_addr_t phys_end; 2555 2556 #define PCIC_SMM_START_LOW 0 2557 #define PCIC_SMM_START_HIGH 1 2558 #define PCIC_SMM_STOP_LOW 2 2559 #define PCIC_SMM_STOP_HIGH 3 2560 #define PCIC_CMA_LOW 4 2561 #define PCIC_CMA_HIGH 5 2562 2563 u_int8_t start_low, start_high = 0; 2564 u_int8_t stop_low, stop_high; 2565 u_int8_t off_low, off_high; 2566 u_int8_t mem_window; 2567 int reg; 2568 2569 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2570 int mem8 = 2571 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2572 || (kind == PCMCIA_MEM_ATTR); 2573 2574 regbase_win = 0x10 + win * 0x08; 2575 2576 phys_addr = ph->mem[win].addr; 2577 phys_end = phys_addr + ph->mem[win].size; 2578 2579 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2580 phys_addr, phys_end, ph->mem[win].offset)); 2581 2582 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2583 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2584 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2585 2586 /* bit 19:12 */ 2587 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2588 /* bit 23:20 and bit 7 on */ 2589 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2590 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2591 /* bit 31:24, for 32-bit address */ 2592 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2593 2594 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2595 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2596 2597 if (((struct pccbb_softc *)ph-> 2598 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2599 Pcic_write(ph, 0x40 + win, mem_window); 2600 } 2601 2602 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2603 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2604 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2605 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2606 2607 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2608 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2609 2610 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2611 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2612 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2613 | ((kind == PCMCIA_MEM_ATTR) ? 2614 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2615 2616 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2617 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2618 2619 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2620 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2621 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2622 2623 #if defined CBB_DEBUG 2624 { 2625 int r1, r2, r3, r4, r5, r6, r7 = 0; 2626 2627 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2628 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2629 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2630 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2631 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2632 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2633 if (((struct pccbb_softc *)(ph-> 2634 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2635 r7 = Pcic_read(ph, 0x40 + win); 2636 } 2637 2638 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2639 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2640 if (((struct pccbb_softc *)(ph-> 2641 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2642 DPRINTF((" %02x", r7)); 2643 } 2644 DPRINTF(("\n")); 2645 } 2646 #endif 2647 } 2648 2649 /* 2650 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2651 * bus_addr_t card_addr, bus_size_t size, 2652 * struct pcmcia_mem_handle *pcmhp, 2653 * bus_addr_t *offsetp, int *windowp) 2654 * 2655 * This function maps memory space allocated by the function 2656 * pccbb_pcmcia_mem_alloc(). 2657 */ 2658 STATIC int 2659 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2660 pcmcia_chipset_handle_t pch; 2661 int kind; 2662 bus_addr_t card_addr; 2663 bus_size_t size; 2664 struct pcmcia_mem_handle *pcmhp; 2665 bus_addr_t *offsetp; 2666 int *windowp; 2667 { 2668 struct pcic_handle *ph = (struct pcic_handle *)pch; 2669 bus_addr_t busaddr; 2670 long card_offset; 2671 int win; 2672 2673 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2674 if ((ph->memalloc & (1 << win)) == 0) { 2675 ph->memalloc |= (1 << win); 2676 break; 2677 } 2678 } 2679 2680 if (win == PCIC_MEM_WINS) { 2681 return 1; 2682 } 2683 2684 *windowp = win; 2685 2686 /* XXX this is pretty gross */ 2687 2688 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2689 panic("pccbb_pcmcia_mem_map memt is bogus"); 2690 } 2691 2692 busaddr = pcmhp->addr; 2693 2694 /* 2695 * compute the address offset to the pcmcia address space for the 2696 * pcic. this is intentionally signed. The masks and shifts below 2697 * will cause TRT to happen in the pcic registers. Deal with making 2698 * sure the address is aligned, and return the alignment offset. 2699 */ 2700 2701 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2702 card_addr -= *offsetp; 2703 2704 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2705 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2706 (u_long) card_addr)); 2707 2708 /* 2709 * include the offset in the size, and decrement size by one, since 2710 * the hw wants start/stop 2711 */ 2712 size += *offsetp - 1; 2713 2714 card_offset = (((long)card_addr) - ((long)busaddr)); 2715 2716 ph->mem[win].addr = busaddr; 2717 ph->mem[win].size = size; 2718 ph->mem[win].offset = card_offset; 2719 ph->mem[win].kind = kind; 2720 2721 pccbb_pcmcia_do_mem_map(ph, win); 2722 2723 return 0; 2724 } 2725 2726 /* 2727 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2728 * int window) 2729 * 2730 * This function unmaps memory space which mapped by the function 2731 * pccbb_pcmcia_mem_map(). 2732 */ 2733 STATIC void 2734 pccbb_pcmcia_mem_unmap(pch, window) 2735 pcmcia_chipset_handle_t pch; 2736 int window; 2737 { 2738 struct pcic_handle *ph = (struct pcic_handle *)pch; 2739 int reg; 2740 2741 if (window >= PCIC_MEM_WINS) { 2742 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2743 } 2744 2745 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2746 reg &= ~(1 << window); 2747 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2748 2749 ph->memalloc &= ~(1 << window); 2750 } 2751 2752 #if defined PCCBB_PCMCIA_POLL 2753 struct pccbb_poll_str { 2754 void *arg; 2755 int (*func) __P((void *)); 2756 int level; 2757 struct pcic_handle *ph; 2758 int count; 2759 int num; 2760 struct callout poll_ch; 2761 }; 2762 2763 static struct pccbb_poll_str pccbb_poll[10]; 2764 static int pccbb_poll_n = 0; 2765 2766 static void pccbb_pcmcia_poll __P((void *arg)); 2767 2768 static void 2769 pccbb_pcmcia_poll(arg) 2770 void *arg; 2771 { 2772 struct pccbb_poll_str *poll = arg; 2773 struct pcic_handle *ph = poll->ph; 2774 struct pccbb_softc *sc = ph->sc; 2775 int s; 2776 u_int32_t spsr; /* socket present-state reg */ 2777 2778 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2779 switch (poll->level) { 2780 case IPL_NET: 2781 s = splnet(); 2782 break; 2783 case IPL_BIO: 2784 s = splbio(); 2785 break; 2786 case IPL_TTY: /* fallthrough */ 2787 default: 2788 s = spltty(); 2789 break; 2790 } 2791 2792 spsr = 2793 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2794 CB_SOCKET_STAT); 2795 2796 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2797 if (!(spsr & 0x40)) /* CINT low */ 2798 #else 2799 if (1) 2800 #endif 2801 { 2802 if ((*poll->func) (poll->arg) > 0) { 2803 ++poll->count; 2804 // printf("intr: reported from poller, 0x%x\n", spsr); 2805 #if defined LEVEL2 2806 } else { 2807 printf("intr: miss! 0x%x\n", spsr); 2808 #endif 2809 } 2810 } 2811 splx(s); 2812 } 2813 #endif /* defined CB_PCMCIA_POLL */ 2814 2815 /* 2816 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2817 * struct pcmcia_function *pf, 2818 * int ipl, 2819 * int (*func)(void *), 2820 * void *arg); 2821 * 2822 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2823 */ 2824 STATIC void * 2825 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2826 pcmcia_chipset_handle_t pch; 2827 struct pcmcia_function *pf; 2828 int ipl; 2829 int (*func) __P((void *)); 2830 void *arg; 2831 { 2832 struct pcic_handle *ph = (struct pcic_handle *)pch; 2833 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2834 2835 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2836 /* what should I do? */ 2837 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2838 DPRINTF( 2839 ("%s does not provide edge nor pulse interrupt\n", 2840 sc->sc_dev.dv_xname)); 2841 return NULL; 2842 } 2843 /* 2844 * XXX Noooooo! The interrupt flag must set properly!! 2845 * dumb pcmcia driver!! 2846 */ 2847 } 2848 2849 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2850 } 2851 2852 /* 2853 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2854 * void *ih) 2855 * 2856 * This function disables PC-Card interrupt. 2857 */ 2858 STATIC void 2859 pccbb_pcmcia_intr_disestablish(pch, ih) 2860 pcmcia_chipset_handle_t pch; 2861 void *ih; 2862 { 2863 struct pcic_handle *ph = (struct pcic_handle *)pch; 2864 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2865 2866 pccbb_intr_disestablish(sc, ih); 2867 } 2868 2869 #if rbus 2870 /* 2871 * static int 2872 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2873 * bus_addr_t addr, bus_size_t size, 2874 * bus_addr_t mask, bus_size_t align, 2875 * int flags, bus_addr_t *addrp; 2876 * bus_space_handle_t *bshp) 2877 * 2878 * This function allocates a portion of memory or io space for 2879 * clients. This function is called from CardBus card drivers. 2880 */ 2881 static int 2882 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2883 cardbus_chipset_tag_t ct; 2884 rbus_tag_t rb; 2885 bus_addr_t addr; 2886 bus_size_t size; 2887 bus_addr_t mask; 2888 bus_size_t align; 2889 int flags; 2890 bus_addr_t *addrp; 2891 bus_space_handle_t *bshp; 2892 { 2893 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2894 2895 DPRINTF( 2896 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2897 addr, size, mask, align)); 2898 2899 if (align == 0) { 2900 align = size; 2901 } 2902 2903 if (rb->rb_bt == sc->sc_memt) { 2904 if (align < 16) { 2905 return 1; 2906 } 2907 } else if (rb->rb_bt == sc->sc_iot) { 2908 if (align < 4) { 2909 return 1; 2910 } 2911 /* XXX: hack for avoiding ISA image */ 2912 if (mask < 0x0100) { 2913 mask = 0x3ff; 2914 addr = 0x300; 2915 } 2916 2917 } else { 2918 DPRINTF( 2919 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2920 rb->rb_bt)); 2921 return 1; 2922 /* XXX: panic here? */ 2923 } 2924 2925 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2926 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2927 return 1; 2928 } 2929 2930 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2931 2932 return 0; 2933 } 2934 2935 /* 2936 * static int 2937 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2938 * bus_space_handle_t *bshp, bus_size_t size); 2939 * 2940 * This function is called from CardBus card drivers. 2941 */ 2942 static int 2943 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2944 cardbus_chipset_tag_t ct; 2945 rbus_tag_t rb; 2946 bus_space_handle_t bsh; 2947 bus_size_t size; 2948 { 2949 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2950 bus_space_tag_t bt = rb->rb_bt; 2951 2952 pccbb_close_win(sc, bt, bsh, size); 2953 2954 if (bt == sc->sc_memt) { 2955 } else if (bt == sc->sc_iot) { 2956 } else { 2957 return 1; 2958 /* XXX: panic here? */ 2959 } 2960 2961 return rbus_space_free(rb, bsh, size, NULL); 2962 } 2963 #endif /* rbus */ 2964 2965 #if rbus 2966 2967 static int 2968 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2969 struct pccbb_softc *sc; 2970 bus_space_tag_t bst; 2971 bus_addr_t addr; 2972 bus_size_t size; 2973 bus_space_handle_t bsh; 2974 int flags; 2975 { 2976 struct pccbb_win_chain_head *head; 2977 bus_addr_t align; 2978 2979 head = &sc->sc_iowindow; 2980 align = 0x04; 2981 if (sc->sc_memt == bst) { 2982 head = &sc->sc_memwindow; 2983 align = 0x1000; 2984 DPRINTF(("using memory window, %x %x %x\n\n", 2985 sc->sc_iot, sc->sc_memt, bst)); 2986 } 2987 2988 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2989 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2990 sc->sc_dev.dv_xname, 2991 (head == &sc->sc_memwindow) ? "mem" : "io"); 2992 } 2993 pccbb_winset(align, sc, bst); 2994 2995 return 0; 2996 } 2997 2998 static int 2999 pccbb_close_win(sc, bst, bsh, size) 3000 struct pccbb_softc *sc; 3001 bus_space_tag_t bst; 3002 bus_space_handle_t bsh; 3003 bus_size_t size; 3004 { 3005 struct pccbb_win_chain_head *head; 3006 bus_addr_t align; 3007 3008 head = &sc->sc_iowindow; 3009 align = 0x04; 3010 if (sc->sc_memt == bst) { 3011 head = &sc->sc_memwindow; 3012 align = 0x1000; 3013 } 3014 3015 if (pccbb_winlist_delete(head, bsh, size)) { 3016 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3017 sc->sc_dev.dv_xname, 3018 (head == &sc->sc_memwindow) ? "mem" : "io"); 3019 } 3020 pccbb_winset(align, sc, bst); 3021 3022 return 0; 3023 } 3024 3025 static int 3026 pccbb_winlist_insert(head, start, size, bsh, flags) 3027 struct pccbb_win_chain_head *head; 3028 bus_addr_t start; 3029 bus_size_t size; 3030 bus_space_handle_t bsh; 3031 int flags; 3032 { 3033 struct pccbb_win_chain *chainp, *elem; 3034 3035 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3036 M_NOWAIT)) == NULL) 3037 return (1); /* fail */ 3038 3039 elem->wc_start = start; 3040 elem->wc_end = start + (size - 1); 3041 elem->wc_handle = bsh; 3042 elem->wc_flags = flags; 3043 3044 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3045 chainp = TAILQ_NEXT(chainp, wc_list)) { 3046 if (chainp->wc_end < start) 3047 continue; 3048 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3049 return (0); 3050 } 3051 3052 TAILQ_INSERT_TAIL(head, elem, wc_list); 3053 return (0); 3054 } 3055 3056 static int 3057 pccbb_winlist_delete(head, bsh, size) 3058 struct pccbb_win_chain_head *head; 3059 bus_space_handle_t bsh; 3060 bus_size_t size; 3061 { 3062 struct pccbb_win_chain *chainp; 3063 3064 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3065 chainp = TAILQ_NEXT(chainp, wc_list)) { 3066 if (chainp->wc_handle != bsh) 3067 continue; 3068 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3069 printf("pccbb_winlist_delete: window 0x%lx size " 3070 "inconsistent: 0x%lx, 0x%lx\n", 3071 (unsigned long)chainp->wc_start, 3072 (unsigned long)(chainp->wc_end - chainp->wc_start), 3073 (unsigned long)(size - 1)); 3074 return 1; 3075 } 3076 3077 TAILQ_REMOVE(head, chainp, wc_list); 3078 free(chainp, M_DEVBUF); 3079 3080 return 0; 3081 } 3082 3083 return 1; /* fail: no candidate to remove */ 3084 } 3085 3086 static void 3087 pccbb_winset(align, sc, bst) 3088 bus_addr_t align; 3089 struct pccbb_softc *sc; 3090 bus_space_tag_t bst; 3091 { 3092 pci_chipset_tag_t pc; 3093 pcitag_t tag; 3094 bus_addr_t mask = ~(align - 1); 3095 struct { 3096 cardbusreg_t win_start; 3097 cardbusreg_t win_limit; 3098 int win_flags; 3099 } win[2]; 3100 struct pccbb_win_chain *chainp; 3101 int offs; 3102 3103 win[0].win_start = win[1].win_start = 0xffffffff; 3104 win[0].win_limit = win[1].win_limit = 0; 3105 win[0].win_flags = win[1].win_flags = 0; 3106 3107 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3108 offs = 0x2c; 3109 if (sc->sc_memt == bst) { 3110 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3111 offs = 0x1c; 3112 } 3113 3114 if (chainp != NULL) { 3115 win[0].win_start = chainp->wc_start & mask; 3116 win[0].win_limit = chainp->wc_end & mask; 3117 win[0].win_flags = chainp->wc_flags; 3118 chainp = TAILQ_NEXT(chainp, wc_list); 3119 } 3120 3121 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3122 if (win[1].win_start == 0xffffffff) { 3123 /* window 1 is not used */ 3124 if ((win[0].win_flags == chainp->wc_flags) && 3125 (win[0].win_limit + align >= 3126 (chainp->wc_start & mask))) { 3127 /* concatenate */ 3128 win[0].win_limit = chainp->wc_end & mask; 3129 } else { 3130 /* make new window */ 3131 win[1].win_start = chainp->wc_start & mask; 3132 win[1].win_limit = chainp->wc_end & mask; 3133 win[1].win_flags = chainp->wc_flags; 3134 } 3135 continue; 3136 } 3137 3138 /* Both windows are engaged. */ 3139 if (win[0].win_flags == win[1].win_flags) { 3140 /* same flags */ 3141 if (win[0].win_flags == chainp->wc_flags) { 3142 if (win[1].win_start - (win[0].win_limit + 3143 align) < 3144 (chainp->wc_start & mask) - 3145 ((chainp->wc_end & mask) + align)) { 3146 /* 3147 * merge window 0 and 1, and set win1 3148 * to chainp 3149 */ 3150 win[0].win_limit = win[1].win_limit; 3151 win[1].win_start = 3152 chainp->wc_start & mask; 3153 win[1].win_limit = 3154 chainp->wc_end & mask; 3155 } else { 3156 win[1].win_limit = 3157 chainp->wc_end & mask; 3158 } 3159 } else { 3160 /* different flags */ 3161 3162 /* concatenate win0 and win1 */ 3163 win[0].win_limit = win[1].win_limit; 3164 /* allocate win[1] to new space */ 3165 win[1].win_start = chainp->wc_start & mask; 3166 win[1].win_limit = chainp->wc_end & mask; 3167 win[1].win_flags = chainp->wc_flags; 3168 } 3169 } else { 3170 /* the flags of win[0] and win[1] is different */ 3171 if (win[0].win_flags == chainp->wc_flags) { 3172 win[0].win_limit = chainp->wc_end & mask; 3173 /* 3174 * XXX this creates overlapping windows, so 3175 * what should the poor bridge do if one is 3176 * cachable, and the other is not? 3177 */ 3178 printf("%s: overlapping windows\n", 3179 sc->sc_dev.dv_xname); 3180 } else { 3181 win[1].win_limit = chainp->wc_end & mask; 3182 } 3183 } 3184 } 3185 3186 pc = sc->sc_pc; 3187 tag = sc->sc_tag; 3188 pci_conf_write(pc, tag, offs, win[0].win_start); 3189 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3190 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3191 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3192 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3193 pci_conf_read(pc, tag, offs), 3194 pci_conf_read(pc, tag, offs + 4) + align, 3195 pci_conf_read(pc, tag, offs + 8), 3196 pci_conf_read(pc, tag, offs + 12) + align)); 3197 3198 if (bst == sc->sc_memt) { 3199 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3200 3201 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3202 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3203 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3204 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3205 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3206 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3207 } 3208 } 3209 3210 #endif /* rbus */ 3211 3212 static void 3213 pccbb_powerhook(why, arg) 3214 int why; 3215 void *arg; 3216 { 3217 struct pccbb_softc *sc = arg; 3218 u_int32_t reg; 3219 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3220 bus_space_handle_t base_memh = sc->sc_base_memh; 3221 3222 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3223 3224 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3225 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3226 if (sc->sc_pil_intr_enable) { 3227 (void)pccbbintr_function(sc); 3228 } 3229 sc->sc_pil_intr_enable = 0; 3230 3231 /* ToDo: deactivate or suspend child devices */ 3232 3233 } 3234 3235 if (why == PWR_RESUME) { 3236 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3237 /* BIOS did not recover this register */ 3238 pci_conf_write (sc->sc_pc, sc->sc_tag, 3239 PCI_SOCKBASE, sc->sc_sockbase); 3240 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3241 /* BIOS did not recover this register */ 3242 pci_conf_write (sc->sc_pc, sc->sc_tag, 3243 PCI_BUSNUM, sc->sc_busnum); 3244 /* CSC Interrupt: Card detect interrupt on */ 3245 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3246 /* Card detect intr is turned on. */ 3247 reg |= CB_SOCKET_MASK_CD; 3248 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3249 /* reset interrupt */ 3250 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3251 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3252 3253 /* 3254 * check for card insertion or removal during suspend period. 3255 * XXX: the code can't cope with card swap (remove then 3256 * insert). how can we detect such situation? 3257 */ 3258 (void)pccbbintr(sc); 3259 3260 sc->sc_pil_intr_enable = 1; 3261 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3262 3263 /* ToDo: activate or wakeup child devices */ 3264 } 3265 } 3266
Indexes created Tue Oct 14 06:10:07 GMT 2025