pccbb.c revision 1.62
1 /* $NetBSD: pccbb.c,v 1.62 2001/04/12 18:18:31 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/reboot.h> /* for bootverbose */ 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 #include <sys/proc.h> 57 58 #include <machine/intr.h> 59 #include <machine/bus.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/pccbbreg.h> 66 67 #include <dev/cardbus/cardslotvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 71 #include <dev/pcmcia/pcmciareg.h> 72 #include <dev/pcmcia/pcmciavar.h> 73 74 #include <dev/ic/i82365reg.h> 75 #include <dev/ic/i82365var.h> 76 #include <dev/pci/pccbbvar.h> 77 78 #include "locators.h" 79 80 #ifndef __NetBSD_Version__ 81 struct cfdriver cbb_cd = { 82 NULL, "cbb", DV_DULL 83 }; 84 #endif 85 86 #if defined CBB_DEBUG 87 #define DPRINTF(x) printf x 88 #define STATIC 89 #else 90 #define DPRINTF(x) 91 #define STATIC static 92 #endif 93 94 /* 95 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 96 * if you want to wait more than 1 ms. 97 */ 98 #define DELAY_MS(time, param) \ 99 do { \ 100 if (cold == 0) { \ 101 int tick = (hz*(time))/1000; \ 102 \ 103 if (tick <= 1) { \ 104 tick = 2; \ 105 } \ 106 tsleep((void *)(param), PCATCH, "pccbb", tick); \ 107 } else { \ 108 delay((time)*1000); \ 109 } \ 110 } while (0) 111 112 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 113 void pccbbattach __P((struct device *, struct device *, void *)); 114 int pccbbintr __P((void *)); 115 static void pci113x_insert __P((void *)); 116 static int pccbbintr_function __P((struct pccbb_softc *)); 117 118 static int pccbb_detect_card __P((struct pccbb_softc *)); 119 120 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 121 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset __P((struct pccbb_softc *)); 126 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 127 STATIC int cbbprint __P((void *, const char *)); 128 129 static int cb_chipset __P((u_int32_t, int *)); 130 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 131 struct pcmciabus_attach_args *)); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 134 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 135 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 136 #endif 137 138 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 139 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 140 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 141 #if !rbus 142 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 143 u_int32_t)); 144 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 145 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 146 u_int32_t)); 147 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc)); 151 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 152 153 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc)); 155 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 156 157 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 158 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 159 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 160 int)); 161 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 162 cardbusreg_t)); 163 static void pccbb_chipinit __P((struct pccbb_softc *)); 164 165 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 166 struct pcmcia_mem_handle *)); 167 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 168 struct pcmcia_mem_handle *)); 169 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 171 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 172 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 173 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 174 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *)); 176 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *)); 178 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 179 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 180 struct pcmcia_function *, int, int (*)(void *), void *)); 181 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 182 void *)); 183 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 184 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 185 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 186 187 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 188 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 189 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 190 static void pccbb_powerhook __P((int, void *)); 191 192 /* bus-space allocation and deallocation functions */ 193 #if rbus 194 195 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 196 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 197 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 198 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 199 bus_space_handle_t, bus_size_t)); 200 201 #endif /* rbus */ 202 203 #if rbus 204 205 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 206 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 207 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_space_handle_t, bus_size_t)); 209 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 210 bus_size_t, bus_space_handle_t, int)); 211 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 212 bus_space_handle_t, bus_size_t)); 213 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 214 bus_space_tag_t)); 215 void pccbb_winlist_show(struct pccbb_win_chain *); 216 217 #endif /* rbus */ 218 219 /* for config_defer */ 220 static void pccbb_pci_callback __P((struct device *)); 221 222 #if defined SHOW_REGS 223 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 224 bus_space_tag_t memt, bus_space_handle_t memh)); 225 #endif 226 227 struct cfattach cbb_pci_ca = { 228 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 229 }; 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_card_detect 245 }; 246 247 #if rbus 248 static struct cardbus_functions pccbb_funcs = { 249 pccbb_rbus_cb_space_alloc, 250 pccbb_rbus_cb_space_free, 251 pccbb_cb_intr_establish, 252 pccbb_cb_intr_disestablish, 253 pccbb_ctrl, 254 pccbb_power, 255 pccbb_make_tag, 256 pccbb_free_tag, 257 pccbb_conf_read, 258 pccbb_conf_write, 259 }; 260 #else 261 static struct cardbus_functions pccbb_funcs = { 262 pccbb_ctrl, 263 pccbb_power, 264 pccbb_mem_open, 265 pccbb_mem_close, 266 pccbb_io_open, 267 pccbb_io_close, 268 pccbb_cb_intr_establish, 269 pccbb_cb_intr_disestablish, 270 pccbb_make_tag, 271 pccbb_conf_read, 272 pccbb_conf_write, 273 }; 274 #endif 275 276 int 277 pcicbbmatch(parent, match, aux) 278 struct device *parent; 279 struct cfdata *match; 280 void *aux; 281 { 282 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 283 284 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 285 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 286 PCI_INTERFACE(pa->pa_class) == 0) { 287 return 1; 288 } 289 290 return 0; 291 } 292 293 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 294 | ((prod) << PCI_PRODUCT_SHIFT)) 295 296 const struct yenta_chipinfo { 297 pcireg_t yc_id; /* vendor tag | product tag */ 298 int yc_chiptype; 299 int yc_flags; 300 } yc_chipsets[] = { 301 /* Texas Instruments chips */ 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 327 /* Ricoh chips */ 328 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 329 PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 331 PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 339 PCCBB_PCMCIA_MEM_32}, 340 341 /* Toshiba products */ 342 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 343 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 344 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 345 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 347 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 349 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 350 351 /* Cirrus Logic products */ 352 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 353 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 355 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 356 357 /* sentinel, or Generic chip */ 358 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 359 }; 360 361 static int 362 cb_chipset(pci_id, flagp) 363 u_int32_t pci_id; 364 int *flagp; 365 { 366 const struct yenta_chipinfo *yc; 367 368 /* Loop over except the last default entry. */ 369 for (yc = yc_chipsets; yc < yc_chipsets + 370 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 371 if (pci_id == yc->yc_id) 372 break; 373 374 if (flagp != NULL) 375 *flagp = yc->yc_flags; 376 377 return (yc->yc_chiptype); 378 } 379 380 static void 381 pccbb_shutdown(void *arg) 382 { 383 struct pccbb_softc *sc = arg; 384 pcireg_t command; 385 386 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 387 388 /* 389 * turn off power 390 * 391 * XXX - do not turn off power if chipset is TI 113X because 392 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 393 */ 394 if (sc->sc_chipset != CB_TI113X) { 395 pccbb_power((cardbus_chipset_tag_t)sc, 396 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 397 } 398 399 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 400 0); 401 402 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 403 404 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 405 PCI_COMMAND_MASTER_ENABLE); 406 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 407 408 } 409 410 void 411 pccbbattach(parent, self, aux) 412 struct device *parent; 413 struct device *self; 414 void *aux; 415 { 416 struct pccbb_softc *sc = (void *)self; 417 struct pci_attach_args *pa = aux; 418 pci_chipset_tag_t pc = pa->pa_pc; 419 pcireg_t busreg, reg, sock_base; 420 bus_addr_t sockbase; 421 char devinfo[256]; 422 int flags; 423 424 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 425 426 pci_devinfo(pa->pa_id, 0, 0, devinfo); 427 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 428 #ifdef CBB_DEBUG 429 printf(" (chipflags %x)", flags); 430 #endif 431 printf("\n"); 432 433 TAILQ_INIT(&sc->sc_memwindow); 434 TAILQ_INIT(&sc->sc_iowindow); 435 436 #if rbus 437 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 438 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 439 #endif /* rbus */ 440 441 sc->sc_base_memh = 0; 442 443 /* 444 * MAP socket registers and ExCA registers on memory-space 445 * When no valid address is set on socket base registers (on pci 446 * config space), get it not polite way. 447 */ 448 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 449 450 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 451 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 452 /* The address must be valid. */ 453 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 454 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 455 printf("%s: can't map socket base address 0x%x\n", 456 sc->sc_dev.dv_xname, sock_base); 457 /* 458 * I think it's funny: socket base registers must be 459 * mapped on memory space, but ... 460 */ 461 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 462 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 463 NULL)) { 464 printf("%s: can't map socket base address" 465 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 466 sockbase); 467 /* give up... allocate reg space via rbus. */ 468 sc->sc_base_memh = 0; 469 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 470 } 471 } else { 472 DPRINTF(("%s: socket base address 0x%lx\n", 473 sc->sc_dev.dv_xname, sockbase)); 474 } 475 } 476 477 sc->sc_mem_start = 0; /* XXX */ 478 sc->sc_mem_end = 0xffffffff; /* XXX */ 479 480 /* 481 * When interrupt isn't routed correctly, give up probing cbb and do 482 * not kill pcic-compatible port. 483 */ 484 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 485 printf("%s: NOT USED because of unconfigured interrupt\n", 486 sc->sc_dev.dv_xname); 487 return; 488 } 489 490 /* 491 * When bus number isn't set correctly, give up using 32-bit CardBus 492 * mode. 493 */ 494 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 495 #if notyet 496 if (((busreg >> 8) & 0xff) == 0) { 497 printf("%s: CardBus support disabled because of unconfigured bus number\n", 498 sc->sc_dev.dv_xname); 499 flags |= PCCBB_PCMCIA_16BITONLY; 500 } 501 #endif 502 503 /* pccbb_machdep.c end */ 504 505 #if defined CBB_DEBUG 506 { 507 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 508 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 509 intrname[pa->pa_intrpin], pa->pa_intrline); 510 } 511 #endif 512 513 /* setup softc */ 514 sc->sc_pc = pc; 515 sc->sc_iot = pa->pa_iot; 516 sc->sc_memt = pa->pa_memt; 517 sc->sc_dmat = pa->pa_dmat; 518 sc->sc_tag = pa->pa_tag; 519 sc->sc_function = pa->pa_function; 520 sc->sc_sockbase = sock_base; 521 sc->sc_busnum = busreg; 522 523 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 524 525 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 526 527 shutdownhook_establish(pccbb_shutdown, sc); 528 529 /* Disable legacy register mapping. */ 530 switch (sc->sc_chipset) { 531 case CB_RX5C46X: /* fallthrough */ 532 #if 0 533 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 534 case CB_RX5C47X: 535 #endif 536 /* 537 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 538 * cannot be disabled by substituting 0 into PCI_LEGACY 539 * register. Ricoh CardBus bridges have special bits on Bridge 540 * control reg (addr 0x3e on PCI config space). 541 */ 542 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 543 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 544 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 545 break; 546 547 default: 548 /* XXX I don't know proper way to kill legacy I/O. */ 549 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 550 break; 551 } 552 553 config_defer(self, pccbb_pci_callback); 554 } 555 556 557 558 559 /* 560 * static void pccbb_pci_callback(struct device *self) 561 * 562 * The actual attach routine: get memory space for YENTA register 563 * space, setup YENTA register and route interrupt. 564 * 565 * This function should be deferred because this device may obtain 566 * memory space dynamically. This function must avoid obtaining 567 * memory area which has already kept for another device. 568 */ 569 static void 570 pccbb_pci_callback(self) 571 struct device *self; 572 { 573 struct pccbb_softc *sc = (void *)self; 574 pci_chipset_tag_t pc = sc->sc_pc; 575 bus_space_tag_t base_memt; 576 bus_space_handle_t base_memh; 577 u_int32_t maskreg; 578 pci_intr_handle_t ih; 579 const char *intrstr = NULL; 580 bus_addr_t sockbase; 581 struct cbslot_attach_args cba; 582 struct pcmciabus_attach_args paa; 583 struct cardslot_attach_args caa; 584 struct cardslot_softc *csc; 585 586 if (0 == sc->sc_base_memh) { 587 /* The socket registers aren't mapped correctly. */ 588 #if rbus 589 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 590 (sc->sc_chipset == CB_RX5C47X 591 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 592 0, &sockbase, &sc->sc_base_memh)) { 593 return; 594 } 595 sc->sc_base_memt = sc->sc_memt; 596 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 597 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 598 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 599 PCI_SOCKBASE))); 600 #else 601 sc->sc_base_memt = sc->sc_memt; 602 #if !defined CBB_PCI_BASE 603 #define CBB_PCI_BASE 0x20000000 604 #endif 605 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 606 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 607 /* cannot allocate memory space */ 608 return; 609 } 610 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 611 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 612 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 613 sc->sc_tag, PCI_SOCKBASE))); 614 #endif 615 } 616 617 /* bus bridge initialization */ 618 pccbb_chipinit(sc); 619 620 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 621 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 622 623 /* CSC Interrupt: Card detect interrupt on */ 624 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 625 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 626 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 627 /* reset interrupt */ 628 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 629 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 630 631 /* clear data structure for child device interrupt handlers */ 632 sc->sc_pil = NULL; 633 sc->sc_pil_intr_enable = 1; 634 635 /* Map and establish the interrupt. */ 636 if (pci_intr_map(&sc->sc_pa, &ih)) { 637 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 638 return; 639 } 640 intrstr = pci_intr_string(pc, ih); 641 642 /* 643 * XXX pccbbintr should be called under the priority lower 644 * than any other hard interrputs. 645 */ 646 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 647 648 if (sc->sc_ih == NULL) { 649 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 650 if (intrstr != NULL) { 651 printf(" at %s", intrstr); 652 } 653 printf("\n"); 654 return; 655 } 656 657 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 658 powerhook_establish(pccbb_powerhook, sc); 659 660 { 661 u_int32_t sockstat = 662 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 663 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 664 sc->sc_flags |= CBB_CARDEXIST; 665 } 666 } 667 668 /* 669 * attach cardbus 670 */ 671 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 672 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 673 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 674 675 /* initialize cbslot_attach */ 676 cba.cba_busname = "cardbus"; 677 cba.cba_iot = sc->sc_iot; 678 cba.cba_memt = sc->sc_memt; 679 cba.cba_dmat = sc->sc_dmat; 680 cba.cba_bus = (busreg >> 8) & 0x0ff; 681 cba.cba_cc = (void *)sc; 682 cba.cba_cf = &pccbb_funcs; 683 cba.cba_intrline = sc->sc_pa.pa_intrline; 684 685 #if rbus 686 cba.cba_rbus_iot = sc->sc_rbus_iot; 687 cba.cba_rbus_memt = sc->sc_rbus_memt; 688 #endif 689 690 cba.cba_cacheline = PCI_CACHELINE(bhlc); 691 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 692 693 if (bootverbose) { 694 printf("%s: cacheline 0x%x lattimer 0x%x\n", 695 sc->sc_dev.dv_xname, cba.cba_cacheline, 696 cba.cba_lattimer); 697 printf("%s: bhlc 0x%x lscp 0x%x\n", 698 sc->sc_dev.dv_xname, bhlc, busreg); 699 } 700 #if defined SHOW_REGS 701 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 702 sc->sc_base_memh); 703 #endif 704 } 705 706 pccbb_pcmcia_attach_setup(sc, &paa); 707 caa.caa_cb_attach = NULL; 708 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 709 caa.caa_cb_attach = &cba; 710 } 711 caa.caa_16_attach = &paa; 712 caa.caa_ph = &sc->sc_pcmcia_h; 713 714 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 715 DPRINTF(("pccbbattach: found cardslot\n")); 716 sc->sc_csc = csc; 717 } 718 719 return; 720 } 721 722 723 724 725 726 /* 727 * static void pccbb_chipinit(struct pccbb_softc *sc) 728 * 729 * This function initialize YENTA chip registers listed below: 730 * 1) PCI command reg, 731 * 2) PCI and CardBus latency timer, 732 * 3) route PCI interrupt, 733 * 4) close all memory and io windows. 734 */ 735 static void 736 pccbb_chipinit(sc) 737 struct pccbb_softc *sc; 738 { 739 pci_chipset_tag_t pc = sc->sc_pc; 740 pcitag_t tag = sc->sc_tag; 741 pcireg_t reg; 742 743 /* 744 * Set PCI command reg. 745 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 746 */ 747 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 748 /* I believe it is harmless. */ 749 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 750 PCI_COMMAND_MASTER_ENABLE); 751 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 752 753 /* 754 * Set CardBus latency timer. 755 */ 756 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 757 if (PCI_CB_LATENCY(reg) < 0x20) { 758 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 759 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 760 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 761 } 762 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 763 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 764 765 /* 766 * Set PCI latency timer. 767 */ 768 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 769 if (PCI_LATTIMER(reg) < 0x10) { 770 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 771 reg |= (0x10 << PCI_LATTIMER_SHIFT); 772 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 773 } 774 DPRINTF(("PCI latency timer 0x%x (%x)\n", 775 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 776 777 778 /* Route functional interrupts to PCI. */ 779 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 780 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 781 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 782 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 783 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 784 785 switch (sc->sc_chipset) { 786 case CB_TI113X: 787 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 788 /* This bit is shared, but may read as 0 on some chips, so set 789 it explicitly on both functions. */ 790 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 791 /* CSC intr enable */ 792 reg |= PCI113X_CBCTRL_PCI_CSC; 793 /* functional intr prohibit | prohibit ISA routing */ 794 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 795 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 796 break; 797 798 case CB_TI12XX: 799 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 800 reg |= PCI12XX_SYSCTRL_VCCPROT; 801 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 802 break; 803 804 case CB_TOPIC95B: 805 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 806 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 807 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 808 809 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 810 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 811 sc->sc_dev.dv_xname, reg)); 812 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 813 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 814 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 815 DPRINTF(("0x%x\n", reg)); 816 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 817 break; 818 } 819 820 /* Close all memory and I/O windows. */ 821 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 822 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 823 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 824 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 825 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 826 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 827 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 828 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 829 830 /* reset 16-bit pcmcia bus */ 831 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 832 0x800 + PCIC_INTR, 833 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 834 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 835 836 /* turn of power */ 837 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 838 } 839 840 841 842 843 /* 844 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 845 * struct pcmciabus_attach_args *paa) 846 * 847 * This function attaches 16-bit PCcard bus. 848 */ 849 STATIC void 850 pccbb_pcmcia_attach_setup(sc, paa) 851 struct pccbb_softc *sc; 852 struct pcmciabus_attach_args *paa; 853 { 854 struct pcic_handle *ph = &sc->sc_pcmcia_h; 855 #if rbus 856 rbus_tag_t rb; 857 #endif 858 859 /* initialize pcmcia part in pccbb_softc */ 860 ph->ph_parent = (struct device *)sc; 861 ph->sock = sc->sc_function; 862 ph->flags = 0; 863 ph->shutdown = 0; 864 ph->ih_irq = sc->sc_pa.pa_intrline; 865 ph->ph_bus_t = sc->sc_base_memt; 866 ph->ph_bus_h = sc->sc_base_memh; 867 ph->ph_read = pccbb_pcmcia_read; 868 ph->ph_write = pccbb_pcmcia_write; 869 sc->sc_pct = &pccbb_pcmcia_funcs; 870 871 /* 872 * We need to do a few things here: 873 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 874 * setting the IRQ numbers to 0. 875 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 876 * routing of CSC interrupts (e.g. card removal) to PCI while in 877 * PCMCIA mode. We just leave this set all the time. 878 * 3) Enable card insertion/removal interrupts in case the chip also 879 * needs that while in PCMCIA mode. 880 * 4) Clear any pending CSC interrupt. 881 */ 882 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 883 if (sc->sc_chipset == CB_TI113X) { 884 Pcic_write(ph, PCIC_CSC_INTR, 0); 885 } else { 886 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 887 Pcic_read(ph, PCIC_CSC); 888 } 889 890 /* initialize pcmcia bus attachment */ 891 paa->paa_busname = "pcmcia"; 892 paa->pct = sc->sc_pct; 893 paa->pch = ph; 894 paa->iobase = 0; /* I don't use them */ 895 paa->iosize = 0; 896 #if rbus 897 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 898 paa->iobase = rb->rb_start + rb->rb_offset; 899 paa->iosize = rb->rb_end - rb->rb_start; 900 #endif 901 902 return; 903 } 904 905 #if 0 906 STATIC void 907 pccbb_pcmcia_attach_card(ph) 908 struct pcic_handle *ph; 909 { 910 if (ph->flags & PCIC_FLAG_CARDP) { 911 panic("pccbb_pcmcia_attach_card: already attached"); 912 } 913 914 /* call the MI attach function */ 915 pcmcia_card_attach(ph->pcmcia); 916 917 ph->flags |= PCIC_FLAG_CARDP; 918 } 919 920 STATIC void 921 pccbb_pcmcia_detach_card(ph, flags) 922 struct pcic_handle *ph; 923 int flags; 924 { 925 if (!(ph->flags & PCIC_FLAG_CARDP)) { 926 panic("pccbb_pcmcia_detach_card: already detached"); 927 } 928 929 ph->flags &= ~PCIC_FLAG_CARDP; 930 931 /* call the MI detach function */ 932 pcmcia_card_detach(ph->pcmcia, flags); 933 } 934 #endif 935 936 /* 937 * int pccbbintr(arg) 938 * void *arg; 939 * This routine handles the interrupt from Yenta PCI-CardBus bridge 940 * itself. 941 */ 942 int 943 pccbbintr(arg) 944 void *arg; 945 { 946 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 947 u_int32_t sockevent, sockstate; 948 bus_space_tag_t memt = sc->sc_base_memt; 949 bus_space_handle_t memh = sc->sc_base_memh; 950 struct pcic_handle *ph = &sc->sc_pcmcia_h; 951 952 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 953 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 954 Pcic_read(ph, PCIC_CSC); 955 956 if (sockevent == 0) { 957 /* This intr is not for me: it may be for my child devices. */ 958 if (sc->sc_pil_intr_enable) { 959 return pccbbintr_function(sc); 960 } else { 961 return 0; 962 } 963 } 964 965 if (sockevent & CB_SOCKET_EVENT_CD) { 966 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 967 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 968 /* A card should be removed. */ 969 if (sc->sc_flags & CBB_CARDEXIST) { 970 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 971 sockevent)); 972 DPRINTF((" card removed, 0x%08x\n", sockstate)); 973 sc->sc_flags &= ~CBB_CARDEXIST; 974 if (sc->sc_csc->sc_status & 975 CARDSLOT_STATUS_CARD_16) { 976 #if 0 977 struct pcic_handle *ph = 978 &sc->sc_pcmcia_h; 979 980 pcmcia_card_deactivate(ph->pcmcia); 981 pccbb_pcmcia_socket_disable(ph); 982 pccbb_pcmcia_detach_card(ph, 983 DETACH_FORCE); 984 #endif 985 cardslot_event_throw(sc->sc_csc, 986 CARDSLOT_EVENT_REMOVAL_16); 987 } else if (sc->sc_csc->sc_status & 988 CARDSLOT_STATUS_CARD_CB) { 989 /* Cardbus intr removed */ 990 cardslot_event_throw(sc->sc_csc, 991 CARDSLOT_EVENT_REMOVAL_CB); 992 } 993 } 994 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 995 /* 996 * The pccbbintr may called from powerdown hook when 997 * the system resumed, to detect the card 998 * insertion/removal during suspension. 999 */ 1000 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1001 if (sc->sc_flags & CBB_INSERTING) { 1002 callout_stop(&sc->sc_insert_ch); 1003 } 1004 callout_reset(&sc->sc_insert_ch, hz / 10, 1005 pci113x_insert, sc); 1006 sc->sc_flags |= CBB_INSERTING; 1007 } 1008 } 1009 1010 return (1); 1011 } 1012 1013 /* 1014 * static int pccbbintr_function(struct pccbb_softc *sc) 1015 * 1016 * This function calls each interrupt handler registered at the 1017 * bridge. The interrupt handlers are called in registered order. 1018 */ 1019 static int 1020 pccbbintr_function(sc) 1021 struct pccbb_softc *sc; 1022 { 1023 int retval = 0, val; 1024 struct pccbb_intrhand_list *pil; 1025 int s, splchanged; 1026 1027 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1028 /* 1029 * XXX priority change. gross. I use if-else 1030 * sentense instead of switch-case sentense because of 1031 * avoiding duplicate case value error. More than one 1032 * IPL_XXX use same value. It depends on 1033 * implimentation. 1034 */ 1035 splchanged = 1; 1036 if (pil->pil_level == IPL_SERIAL) { 1037 s = splserial(); 1038 } else if (pil->pil_level == IPL_HIGH) { 1039 s = splhigh(); 1040 } else if (pil->pil_level == IPL_CLOCK) { 1041 s = splclock(); 1042 } else if (pil->pil_level == IPL_AUDIO) { 1043 s = splaudio(); 1044 } else if (pil->pil_level == IPL_IMP) { 1045 s = splvm(); /* XXX */ 1046 } else if (pil->pil_level == IPL_TTY) { 1047 s = spltty(); 1048 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1049 s = splsoftserial(); 1050 } else if (pil->pil_level == IPL_NET) { 1051 s = splnet(); 1052 } else { 1053 splchanged = 0; 1054 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1055 } 1056 1057 val = (*pil->pil_func)(pil->pil_arg); 1058 1059 if (splchanged != 0) { 1060 splx(s); 1061 } 1062 1063 retval = retval == 1 ? 1 : 1064 retval == 0 ? val : val != 0 ? val : retval; 1065 } 1066 1067 return retval; 1068 } 1069 1070 static void 1071 pci113x_insert(arg) 1072 void *arg; 1073 { 1074 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1075 u_int32_t sockevent, sockstate; 1076 1077 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1078 CB_SOCKET_EVENT); 1079 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1080 CB_SOCKET_STAT); 1081 1082 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1083 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1084 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1085 sc->sc_flags |= CBB_CARDEXIST; 1086 /* call pccard interrupt handler here */ 1087 if (sockstate & CB_SOCKET_STAT_16BIT) { 1088 /* 16-bit card found */ 1089 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1090 cardslot_event_throw(sc->sc_csc, 1091 CARDSLOT_EVENT_INSERTION_16); 1092 } else if (sockstate & CB_SOCKET_STAT_CB) { 1093 /* cardbus card found */ 1094 /* cardbus_attach_card(sc->sc_csc); */ 1095 cardslot_event_throw(sc->sc_csc, 1096 CARDSLOT_EVENT_INSERTION_CB); 1097 } else { 1098 /* who are you? */ 1099 } 1100 } else { 1101 callout_reset(&sc->sc_insert_ch, hz / 10, 1102 pci113x_insert, sc); 1103 } 1104 } 1105 1106 #define PCCBB_PCMCIA_OFFSET 0x800 1107 static u_int8_t 1108 pccbb_pcmcia_read(ph, reg) 1109 struct pcic_handle *ph; 1110 int reg; 1111 { 1112 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1113 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1114 1115 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1116 PCCBB_PCMCIA_OFFSET + reg); 1117 } 1118 1119 static void 1120 pccbb_pcmcia_write(ph, reg, val) 1121 struct pcic_handle *ph; 1122 int reg; 1123 u_int8_t val; 1124 { 1125 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1126 val); 1127 1128 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1129 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1130 } 1131 1132 /* 1133 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1134 */ 1135 STATIC int 1136 pccbb_ctrl(ct, command) 1137 cardbus_chipset_tag_t ct; 1138 int command; 1139 { 1140 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1141 1142 switch (command) { 1143 case CARDBUS_CD: 1144 if (2 == pccbb_detect_card(sc)) { 1145 int retval = 0; 1146 int status = cb_detect_voltage(sc); 1147 if (PCCARD_VCC_5V & status) { 1148 retval |= CARDBUS_5V_CARD; 1149 } 1150 if (PCCARD_VCC_3V & status) { 1151 retval |= CARDBUS_3V_CARD; 1152 } 1153 if (PCCARD_VCC_XV & status) { 1154 retval |= CARDBUS_XV_CARD; 1155 } 1156 if (PCCARD_VCC_YV & status) { 1157 retval |= CARDBUS_YV_CARD; 1158 } 1159 return retval; 1160 } else { 1161 return 0; 1162 } 1163 break; 1164 case CARDBUS_RESET: 1165 return cb_reset(sc); 1166 break; 1167 case CARDBUS_IO_ENABLE: /* fallthrough */ 1168 case CARDBUS_IO_DISABLE: /* fallthrough */ 1169 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1170 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1171 case CARDBUS_BM_ENABLE: /* fallthrough */ 1172 case CARDBUS_BM_DISABLE: /* fallthrough */ 1173 return pccbb_cardenable(sc, command); 1174 break; 1175 } 1176 1177 return 0; 1178 } 1179 1180 /* 1181 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1182 * This function returns true when it succeeds and returns false when 1183 * it fails. 1184 */ 1185 STATIC int 1186 pccbb_power(ct, command) 1187 cardbus_chipset_tag_t ct; 1188 int command; 1189 { 1190 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1191 1192 u_int32_t status, sock_ctrl; 1193 bus_space_tag_t memt = sc->sc_base_memt; 1194 bus_space_handle_t memh = sc->sc_base_memh; 1195 1196 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1197 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1198 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1199 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1200 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1201 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1202 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1203 "UNKNOWN", 1204 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1205 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1206 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1207 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1208 "UNKNOWN", command)); 1209 1210 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1211 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1212 1213 switch (command & CARDBUS_VCCMASK) { 1214 case CARDBUS_VCC_UC: 1215 break; 1216 case CARDBUS_VCC_5V: 1217 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1218 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1219 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1220 } else { 1221 printf("%s: BAD voltage request: no 5 V card\n", 1222 sc->sc_dev.dv_xname); 1223 } 1224 break; 1225 case CARDBUS_VCC_3V: 1226 if (CB_SOCKET_STAT_3VCARD & status) { 1227 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1228 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1229 } else { 1230 printf("%s: BAD voltage request: no 3.3 V card\n", 1231 sc->sc_dev.dv_xname); 1232 } 1233 break; 1234 case CARDBUS_VCC_0V: 1235 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1236 break; 1237 default: 1238 return 0; /* power NEVER changed */ 1239 break; 1240 } 1241 1242 switch (command & CARDBUS_VPPMASK) { 1243 case CARDBUS_VPP_UC: 1244 break; 1245 case CARDBUS_VPP_0V: 1246 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1247 break; 1248 case CARDBUS_VPP_VCC: 1249 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1250 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1251 break; 1252 case CARDBUS_VPP_12V: 1253 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1254 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1255 break; 1256 } 1257 1258 #if 0 1259 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1260 #endif 1261 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1262 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1263 1264 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1265 printf 1266 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1267 sc->sc_dev.dv_xname, sock_ctrl, status); 1268 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1269 (command & CARDBUS_VCCMASK) == 1270 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1271 CARDBUS_VCCMASK) == 1272 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1273 CARDBUS_VCCMASK) == 1274 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1275 CARDBUS_VCCMASK) == 1276 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1277 CARDBUS_VCCMASK) == 1278 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1279 CARDBUS_VCCMASK) == 1280 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1281 (command & CARDBUS_VPPMASK) == 1282 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1283 CARDBUS_VPPMASK) == 1284 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1285 CARDBUS_VPPMASK) == 1286 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1287 CARDBUS_VPPMASK) == 1288 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1289 #if 0 1290 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1291 u_int32_t force = 1292 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1293 /* Reset Bad Vcc request */ 1294 force &= ~CB_SOCKET_FORCE_BADVCC; 1295 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1296 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1297 CB_SOCKET_STAT)); 1298 return 1; 1299 } 1300 #endif 1301 return 0; 1302 } 1303 1304 /* 1305 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1306 * time is 20 ms, some PC-Card bridge requires longer duration. 1307 */ 1308 #if 0 /* XXX called on interrupt context */ 1309 DELAY_MS(300, sc); 1310 #else 1311 delay(300 * 1000); 1312 #endif 1313 1314 return 1; /* power changed correctly */ 1315 } 1316 1317 #if defined CB_PCMCIA_POLL 1318 struct cb_poll_str { 1319 void *arg; 1320 int (*func) __P((void *)); 1321 int level; 1322 pccard_chipset_tag_t ct; 1323 int count; 1324 struct callout poll_ch; 1325 }; 1326 1327 static struct cb_poll_str cb_poll[10]; 1328 static int cb_poll_n = 0; 1329 1330 static void cb_pcmcia_poll __P((void *arg)); 1331 1332 static void 1333 cb_pcmcia_poll(arg) 1334 void *arg; 1335 { 1336 struct cb_poll_str *poll = arg; 1337 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1338 struct pccbb_softc *sc = psc->cpc_parent; 1339 int s; 1340 u_int32_t spsr; /* socket present-state reg */ 1341 1342 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1343 switch (poll->level) { 1344 case IPL_NET: 1345 s = splnet(); 1346 break; 1347 case IPL_BIO: 1348 s = splbio(); 1349 break; 1350 case IPL_TTY: /* fallthrough */ 1351 default: 1352 s = spltty(); 1353 break; 1354 } 1355 1356 spsr = 1357 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1358 CB_SOCKET_STAT); 1359 1360 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1361 if (!(spsr & 0x40)) { /* CINT low */ 1362 #else 1363 if (1) { 1364 #endif 1365 if ((*poll->func) (poll->arg) == 1) { 1366 ++poll->count; 1367 printf("intr: reported from poller, 0x%x\n", spsr); 1368 #if defined LEVEL2 1369 } else { 1370 printf("intr: miss! 0x%x\n", spsr); 1371 #endif 1372 } 1373 } 1374 splx(s); 1375 } 1376 #endif /* defined CB_PCMCIA_POLL */ 1377 1378 /* 1379 * static int pccbb_detect_card(struct pccbb_softc *sc) 1380 * return value: 0 if no card exists. 1381 * 1 if 16-bit card exists. 1382 * 2 if cardbus card exists. 1383 */ 1384 static int 1385 pccbb_detect_card(sc) 1386 struct pccbb_softc *sc; 1387 { 1388 bus_space_handle_t base_memh = sc->sc_base_memh; 1389 bus_space_tag_t base_memt = sc->sc_base_memt; 1390 u_int32_t sockstat = 1391 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1392 int retval = 0; 1393 1394 /* CD1 and CD2 asserted */ 1395 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1396 /* card must be present */ 1397 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1398 /* NOTACARD DEASSERTED */ 1399 if (CB_SOCKET_STAT_CB & sockstat) { 1400 /* CardBus mode */ 1401 retval = 2; 1402 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1403 /* 16-bit mode */ 1404 retval = 1; 1405 } 1406 } 1407 } 1408 return retval; 1409 } 1410 1411 /* 1412 * STATIC int cb_reset(struct pccbb_softc *sc) 1413 * This function resets CardBus card. 1414 */ 1415 STATIC int 1416 cb_reset(sc) 1417 struct pccbb_softc *sc; 1418 { 1419 /* 1420 * Reset Assert at least 20 ms 1421 * Some machines request longer duration. 1422 */ 1423 int reset_duration = 1424 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1425 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1426 1427 /* Reset bit Assert (bit 6 at 0x3E) */ 1428 bcr |= CB_BCR_RESET_ENABLE; 1429 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1430 DELAY_MS(reset_duration, sc); 1431 1432 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1433 /* Reset bit Deassert (bit 6 at 0x3E) */ 1434 bcr &= ~CB_BCR_RESET_ENABLE; 1435 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1436 DELAY_MS(reset_duration, sc); 1437 } 1438 /* No card found on the slot. Keep Reset. */ 1439 return 1; 1440 } 1441 1442 /* 1443 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1444 * This function detect card Voltage. 1445 */ 1446 STATIC int 1447 cb_detect_voltage(sc) 1448 struct pccbb_softc *sc; 1449 { 1450 u_int32_t psr; /* socket present-state reg */ 1451 bus_space_tag_t iot = sc->sc_base_memt; 1452 bus_space_handle_t ioh = sc->sc_base_memh; 1453 int vol = PCCARD_VCC_UKN; /* set 0 */ 1454 1455 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1456 1457 if (0x400u & psr) { 1458 vol |= PCCARD_VCC_5V; 1459 } 1460 if (0x800u & psr) { 1461 vol |= PCCARD_VCC_3V; 1462 } 1463 1464 return vol; 1465 } 1466 1467 STATIC int 1468 cbbprint(aux, pcic) 1469 void *aux; 1470 const char *pcic; 1471 { 1472 /* 1473 struct cbslot_attach_args *cba = aux; 1474 1475 if (cba->cba_slot >= 0) { 1476 printf(" slot %d", cba->cba_slot); 1477 } 1478 */ 1479 return UNCONF; 1480 } 1481 1482 /* 1483 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1484 * This function enables and disables the card 1485 */ 1486 STATIC int 1487 pccbb_cardenable(sc, function) 1488 struct pccbb_softc *sc; 1489 int function; 1490 { 1491 u_int32_t command = 1492 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1493 1494 DPRINTF(("pccbb_cardenable:")); 1495 switch (function) { 1496 case CARDBUS_IO_ENABLE: 1497 command |= PCI_COMMAND_IO_ENABLE; 1498 break; 1499 case CARDBUS_IO_DISABLE: 1500 command &= ~PCI_COMMAND_IO_ENABLE; 1501 break; 1502 case CARDBUS_MEM_ENABLE: 1503 command |= PCI_COMMAND_MEM_ENABLE; 1504 break; 1505 case CARDBUS_MEM_DISABLE: 1506 command &= ~PCI_COMMAND_MEM_ENABLE; 1507 break; 1508 case CARDBUS_BM_ENABLE: 1509 command |= PCI_COMMAND_MASTER_ENABLE; 1510 break; 1511 case CARDBUS_BM_DISABLE: 1512 command &= ~PCI_COMMAND_MASTER_ENABLE; 1513 break; 1514 default: 1515 return 0; 1516 } 1517 1518 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1519 DPRINTF((" command reg 0x%x\n", command)); 1520 return 1; 1521 } 1522 1523 #if !rbus 1524 /* 1525 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1526 */ 1527 static int 1528 pccbb_io_open(ct, win, start, end) 1529 cardbus_chipset_tag_t ct; 1530 int win; 1531 u_int32_t start, end; 1532 { 1533 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1534 int basereg; 1535 int limitreg; 1536 1537 if ((win < 0) || (win > 2)) { 1538 #if defined DIAGNOSTIC 1539 printf("cardbus_io_open: window out of range %d\n", win); 1540 #endif 1541 return 0; 1542 } 1543 1544 basereg = win * 8 + 0x2c; 1545 limitreg = win * 8 + 0x30; 1546 1547 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1548 start, basereg, end, limitreg)); 1549 1550 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1551 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1552 return 1; 1553 } 1554 1555 /* 1556 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1557 */ 1558 static int 1559 pccbb_io_close(ct, win) 1560 cardbus_chipset_tag_t ct; 1561 int win; 1562 { 1563 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1564 int basereg; 1565 int limitreg; 1566 1567 if ((win < 0) || (win > 2)) { 1568 #if defined DIAGNOSTIC 1569 printf("cardbus_io_close: window out of range %d\n", win); 1570 #endif 1571 return 0; 1572 } 1573 1574 basereg = win * 8 + 0x2c; 1575 limitreg = win * 8 + 0x30; 1576 1577 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1578 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1579 return 1; 1580 } 1581 1582 /* 1583 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1584 */ 1585 static int 1586 pccbb_mem_open(ct, win, start, end) 1587 cardbus_chipset_tag_t ct; 1588 int win; 1589 u_int32_t start, end; 1590 { 1591 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1592 int basereg; 1593 int limitreg; 1594 1595 if ((win < 0) || (win > 2)) { 1596 #if defined DIAGNOSTIC 1597 printf("cardbus_mem_open: window out of range %d\n", win); 1598 #endif 1599 return 0; 1600 } 1601 1602 basereg = win * 8 + 0x1c; 1603 limitreg = win * 8 + 0x20; 1604 1605 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1606 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1607 return 1; 1608 } 1609 1610 /* 1611 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1612 */ 1613 static int 1614 pccbb_mem_close(ct, win) 1615 cardbus_chipset_tag_t ct; 1616 int win; 1617 { 1618 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1619 int basereg; 1620 int limitreg; 1621 1622 if ((win < 0) || (win > 2)) { 1623 #if defined DIAGNOSTIC 1624 printf("cardbus_mem_close: window out of range %d\n", win); 1625 #endif 1626 return 0; 1627 } 1628 1629 basereg = win * 8 + 0x1c; 1630 limitreg = win * 8 + 0x20; 1631 1632 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1633 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1634 return 1; 1635 } 1636 #endif 1637 1638 /* 1639 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1640 * int irq, 1641 * int level, 1642 * int (* func) __P((void *)), 1643 * void *arg) 1644 * 1645 * This function registers an interrupt handler at the bridge, in 1646 * order not to call the interrupt handlers of child devices when 1647 * a card-deletion interrupt occurs. 1648 * 1649 * The arguments irq and level are not used. 1650 */ 1651 static void * 1652 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1653 cardbus_chipset_tag_t ct; 1654 int irq, level; 1655 int (*func) __P((void *)); 1656 void *arg; 1657 { 1658 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1659 1660 return pccbb_intr_establish(sc, irq, level, func, arg); 1661 } 1662 1663 1664 /* 1665 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1666 * void *ih) 1667 * 1668 * This function removes an interrupt handler pointed by ih. 1669 */ 1670 static void 1671 pccbb_cb_intr_disestablish(ct, ih) 1672 cardbus_chipset_tag_t ct; 1673 void *ih; 1674 { 1675 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1676 1677 pccbb_intr_disestablish(sc, ih); 1678 } 1679 1680 1681 /* 1682 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1683 * int irq, 1684 * int level, 1685 * int (* func) __P((void *)), 1686 * void *arg) 1687 * 1688 * This function registers an interrupt handler at the bridge, in 1689 * order not to call the interrupt handlers of child devices when 1690 * a card-deletion interrupt occurs. 1691 * 1692 * The arguments irq is not used because pccbb selects intr vector. 1693 */ 1694 static void * 1695 pccbb_intr_establish(sc, irq, level, func, arg) 1696 struct pccbb_softc *sc; 1697 int irq, level; 1698 int (*func) __P((void *)); 1699 void *arg; 1700 { 1701 struct pccbb_intrhand_list *pil, *newpil; 1702 pcireg_t reg; 1703 1704 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1705 1706 if (sc->sc_pil == NULL) { 1707 /* initialize bridge intr routing */ 1708 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1709 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1710 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1711 1712 switch (sc->sc_chipset) { 1713 case CB_TI113X: 1714 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1715 /* functional intr enabled */ 1716 reg |= PCI113X_CBCTRL_PCI_INTR; 1717 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1718 break; 1719 default: 1720 break; 1721 } 1722 } 1723 1724 /* 1725 * Allocate a room for interrupt handler structure. 1726 */ 1727 if (NULL == (newpil = 1728 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1729 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1730 return NULL; 1731 } 1732 1733 newpil->pil_func = func; 1734 newpil->pil_arg = arg; 1735 newpil->pil_level = level; 1736 newpil->pil_next = NULL; 1737 1738 if (sc->sc_pil == NULL) { 1739 sc->sc_pil = newpil; 1740 } else { 1741 for (pil = sc->sc_pil; pil->pil_next != NULL; 1742 pil = pil->pil_next); 1743 pil->pil_next = newpil; 1744 } 1745 1746 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1747 1748 return newpil; 1749 } 1750 1751 /* 1752 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1753 * void *ih) 1754 * 1755 * This function removes an interrupt handler pointed by ih. 1756 */ 1757 static void 1758 pccbb_intr_disestablish(sc, ih) 1759 struct pccbb_softc *sc; 1760 void *ih; 1761 { 1762 struct pccbb_intrhand_list *pil, **pil_prev; 1763 pcireg_t reg; 1764 1765 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1766 1767 pil_prev = &sc->sc_pil; 1768 1769 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1770 if (pil == ih) { 1771 *pil_prev = pil->pil_next; 1772 free(pil, M_DEVBUF); 1773 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1774 break; 1775 } 1776 pil_prev = &pil->pil_next; 1777 } 1778 1779 if (sc->sc_pil == NULL) { 1780 /* No interrupt handlers */ 1781 1782 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1783 1784 /* stop routing PCI intr */ 1785 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1786 reg |= CB_BCR_INTR_IREQ_ENABLE; 1787 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1788 1789 switch (sc->sc_chipset) { 1790 case CB_TI113X: 1791 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1792 /* functional intr disabled */ 1793 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1794 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1795 break; 1796 default: 1797 break; 1798 } 1799 } 1800 } 1801 1802 #if defined SHOW_REGS 1803 static void 1804 cb_show_regs(pc, tag, memt, memh) 1805 pci_chipset_tag_t pc; 1806 pcitag_t tag; 1807 bus_space_tag_t memt; 1808 bus_space_handle_t memh; 1809 { 1810 int i; 1811 printf("PCI config regs:"); 1812 for (i = 0; i < 0x50; i += 4) { 1813 if (i % 16 == 0) { 1814 printf("\n 0x%02x:", i); 1815 } 1816 printf(" %08x", pci_conf_read(pc, tag, i)); 1817 } 1818 for (i = 0x80; i < 0xb0; i += 4) { 1819 if (i % 16 == 0) { 1820 printf("\n 0x%02x:", i); 1821 } 1822 printf(" %08x", pci_conf_read(pc, tag, i)); 1823 } 1824 1825 if (memh == 0) { 1826 printf("\n"); 1827 return; 1828 } 1829 1830 printf("\nsocket regs:"); 1831 for (i = 0; i <= 0x10; i += 0x04) { 1832 printf(" %08x", bus_space_read_4(memt, memh, i)); 1833 } 1834 printf("\nExCA regs:"); 1835 for (i = 0; i < 0x08; ++i) { 1836 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1837 } 1838 printf("\n"); 1839 return; 1840 } 1841 #endif 1842 1843 /* 1844 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1845 * int busno, int devno, int function) 1846 * This is the function to make a tag to access config space of 1847 * a CardBus Card. It works same as pci_conf_read. 1848 */ 1849 static cardbustag_t 1850 pccbb_make_tag(cc, busno, devno, function) 1851 cardbus_chipset_tag_t cc; 1852 int busno, devno, function; 1853 { 1854 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1855 1856 return pci_make_tag(sc->sc_pc, busno, devno, function); 1857 } 1858 1859 static void 1860 pccbb_free_tag(cc, tag) 1861 cardbus_chipset_tag_t cc; 1862 cardbustag_t tag; 1863 { 1864 } 1865 1866 /* 1867 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1868 * cardbustag_t tag, int offset) 1869 * This is the function to read the config space of a CardBus Card. 1870 * It works same as pci_conf_read. 1871 */ 1872 static cardbusreg_t 1873 pccbb_conf_read(cc, tag, offset) 1874 cardbus_chipset_tag_t cc; 1875 cardbustag_t tag; 1876 int offset; /* register offset */ 1877 { 1878 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1879 1880 return pci_conf_read(sc->sc_pc, tag, offset); 1881 } 1882 1883 /* 1884 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1885 * int offs, cardbusreg_t val) 1886 * This is the function to write the config space of a CardBus Card. 1887 * It works same as pci_conf_write. 1888 */ 1889 static void 1890 pccbb_conf_write(cc, tag, reg, val) 1891 cardbus_chipset_tag_t cc; 1892 cardbustag_t tag; 1893 int reg; /* register offset */ 1894 cardbusreg_t val; 1895 { 1896 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1897 1898 pci_conf_write(sc->sc_pc, tag, reg, val); 1899 } 1900 1901 #if 0 1902 STATIC int 1903 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1904 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1905 int speed, int flags, 1906 bus_space_handle_t * iohp) 1907 #endif 1908 /* 1909 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1910 * bus_addr_t start, bus_size_t size, 1911 * bus_size_t align, 1912 * struct pcmcia_io_handle *pcihp 1913 * 1914 * This function only allocates I/O region for pccard. This function 1915 * never maps the allocated region to pccard I/O area. 1916 * 1917 * XXX: The interface of this function is not very good, I believe. 1918 */ 1919 STATIC int 1920 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1921 pcmcia_chipset_handle_t pch; 1922 bus_addr_t start; /* start address */ 1923 bus_size_t size; 1924 bus_size_t align; 1925 struct pcmcia_io_handle *pcihp; 1926 { 1927 struct pcic_handle *ph = (struct pcic_handle *)pch; 1928 bus_addr_t ioaddr; 1929 int flags = 0; 1930 bus_space_tag_t iot; 1931 bus_space_handle_t ioh; 1932 bus_addr_t mask; 1933 #if rbus 1934 rbus_tag_t rb; 1935 #endif 1936 if (align == 0) { 1937 align = size; /* XXX: funny??? */ 1938 } 1939 1940 if (start != 0) { 1941 /* XXX: assume all card decode lower 10 bits by its hardware */ 1942 mask = 0x3ff; 1943 } else { 1944 /* 1945 * calculate mask: 1946 * 1. get the most significant bit of size (call it msb). 1947 * 2. compare msb with the value of size. 1948 * 3. if size is larger, shift msb left once. 1949 * 4. obtain mask value to decrement msb. 1950 */ 1951 bus_size_t size_tmp = size; 1952 int shifts = 0; 1953 1954 mask = 1; 1955 while (size_tmp) { 1956 ++shifts; 1957 size_tmp >>= 1; 1958 } 1959 mask = (1 << shifts); 1960 if (mask < size) { 1961 mask <<= 1; 1962 } 1963 --mask; 1964 } 1965 1966 /* 1967 * Allocate some arbitrary I/O space. 1968 */ 1969 1970 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1971 1972 #if rbus 1973 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1974 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1975 return 1; 1976 } 1977 #else 1978 if (start) { 1979 ioaddr = start; 1980 if (bus_space_map(iot, start, size, 0, &ioh)) { 1981 return 1; 1982 } 1983 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1984 (u_long) ioaddr, (u_long) size)); 1985 } else { 1986 flags |= PCMCIA_IO_ALLOCATED; 1987 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1988 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1989 size, align, 0, 0, &ioaddr, &ioh)) { 1990 /* No room be able to be get. */ 1991 return 1; 1992 } 1993 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1994 (u_long) ioaddr, (u_long) size)); 1995 } 1996 #endif 1997 1998 pcihp->iot = iot; 1999 pcihp->ioh = ioh; 2000 pcihp->addr = ioaddr; 2001 pcihp->size = size; 2002 pcihp->flags = flags; 2003 2004 return 0; 2005 } 2006 2007 /* 2008 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2009 * struct pcmcia_io_handle *pcihp) 2010 * 2011 * This function only frees I/O region for pccard. 2012 * 2013 * XXX: The interface of this function is not very good, I believe. 2014 */ 2015 void 2016 pccbb_pcmcia_io_free(pch, pcihp) 2017 pcmcia_chipset_handle_t pch; 2018 struct pcmcia_io_handle *pcihp; 2019 { 2020 #if !rbus 2021 bus_space_tag_t iot = pcihp->iot; 2022 #endif 2023 bus_space_handle_t ioh = pcihp->ioh; 2024 bus_size_t size = pcihp->size; 2025 2026 #if rbus 2027 struct pccbb_softc *sc = 2028 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2029 rbus_tag_t rb = sc->sc_rbus_iot; 2030 2031 rbus_space_free(rb, ioh, size, NULL); 2032 #else 2033 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2034 bus_space_free(iot, ioh, size); 2035 else 2036 bus_space_unmap(iot, ioh, size); 2037 #endif 2038 } 2039 2040 /* 2041 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2042 * bus_addr_t offset, bus_size_t size, 2043 * struct pcmcia_io_handle *pcihp, 2044 * int *windowp) 2045 * 2046 * This function maps the allocated I/O region to pccard. This function 2047 * never allocates any I/O region for pccard I/O area. I don't 2048 * understand why the original authors of pcmciabus separated alloc and 2049 * map. I believe the two must be unite. 2050 * 2051 * XXX: no wait timing control? 2052 */ 2053 int 2054 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2055 pcmcia_chipset_handle_t pch; 2056 int width; 2057 bus_addr_t offset; 2058 bus_size_t size; 2059 struct pcmcia_io_handle *pcihp; 2060 int *windowp; 2061 { 2062 struct pcic_handle *ph = (struct pcic_handle *)pch; 2063 bus_addr_t ioaddr = pcihp->addr + offset; 2064 int i, win; 2065 #if defined CBB_DEBUG 2066 static char *width_names[] = { "dynamic", "io8", "io16" }; 2067 #endif 2068 2069 /* Sanity check I/O handle. */ 2070 2071 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2072 panic("pccbb_pcmcia_io_map iot is bogus"); 2073 } 2074 2075 /* XXX Sanity check offset/size. */ 2076 2077 win = -1; 2078 for (i = 0; i < PCIC_IO_WINS; i++) { 2079 if ((ph->ioalloc & (1 << i)) == 0) { 2080 win = i; 2081 ph->ioalloc |= (1 << i); 2082 break; 2083 } 2084 } 2085 2086 if (win == -1) { 2087 return 1; 2088 } 2089 2090 *windowp = win; 2091 2092 /* XXX this is pretty gross */ 2093 2094 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2095 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2096 2097 /* XXX wtf is this doing here? */ 2098 2099 #if 0 2100 printf(" port 0x%lx", (u_long) ioaddr); 2101 if (size > 1) { 2102 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2103 } 2104 #endif 2105 2106 ph->io[win].addr = ioaddr; 2107 ph->io[win].size = size; 2108 ph->io[win].width = width; 2109 2110 /* actual dirty register-value changing in the function below. */ 2111 pccbb_pcmcia_do_io_map(ph, win); 2112 2113 return 0; 2114 } 2115 2116 /* 2117 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2118 * 2119 * This function changes register-value to map I/O region for pccard. 2120 */ 2121 static void 2122 pccbb_pcmcia_do_io_map(ph, win) 2123 struct pcic_handle *ph; 2124 int win; 2125 { 2126 static u_int8_t pcic_iowidth[3] = { 2127 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2128 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2129 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2130 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2131 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2132 }; 2133 2134 #define PCIC_SIA_START_LOW 0 2135 #define PCIC_SIA_START_HIGH 1 2136 #define PCIC_SIA_STOP_LOW 2 2137 #define PCIC_SIA_STOP_HIGH 3 2138 2139 int regbase_win = 0x8 + win * 0x04; 2140 u_int8_t ioctl, enable; 2141 2142 DPRINTF( 2143 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2144 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2145 ph->io[win].width * 8)); 2146 2147 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2148 ph->io[win].addr & 0xff); 2149 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2150 (ph->io[win].addr >> 8) & 0xff); 2151 2152 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2153 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2154 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2155 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2156 2157 ioctl = Pcic_read(ph, PCIC_IOCTL); 2158 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2159 switch (win) { 2160 case 0: 2161 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2162 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2163 PCIC_IOCTL_IO0_DATASIZE_MASK); 2164 ioctl |= pcic_iowidth[ph->io[win].width]; 2165 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2166 break; 2167 case 1: 2168 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2169 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2170 PCIC_IOCTL_IO1_DATASIZE_MASK); 2171 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2172 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2173 break; 2174 } 2175 Pcic_write(ph, PCIC_IOCTL, ioctl); 2176 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2177 #if defined CBB_DEBUG 2178 { 2179 u_int8_t start_low = 2180 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2181 u_int8_t start_high = 2182 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2183 u_int8_t stop_low = 2184 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2185 u_int8_t stop_high = 2186 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2187 printf 2188 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2189 start_low, start_high, stop_low, stop_high, ioctl, enable); 2190 } 2191 #endif 2192 } 2193 2194 /* 2195 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2196 * 2197 * This function unmaps I/O region. No return value. 2198 */ 2199 STATIC void 2200 pccbb_pcmcia_io_unmap(pch, win) 2201 pcmcia_chipset_handle_t pch; 2202 int win; 2203 { 2204 struct pcic_handle *ph = (struct pcic_handle *)pch; 2205 int reg; 2206 2207 if (win >= PCIC_IO_WINS || win < 0) { 2208 panic("pccbb_pcmcia_io_unmap: window out of range"); 2209 } 2210 2211 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2212 switch (win) { 2213 case 0: 2214 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2215 break; 2216 case 1: 2217 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2218 break; 2219 } 2220 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2221 2222 ph->ioalloc &= ~(1 << win); 2223 } 2224 2225 /* 2226 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2227 * 2228 * This function enables the card. All information is stored in 2229 * the first argument, pcmcia_chipset_handle_t. 2230 */ 2231 static void 2232 pccbb_pcmcia_wait_ready(ph) 2233 struct pcic_handle *ph; 2234 { 2235 int i; 2236 2237 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2238 Pcic_read(ph, PCIC_IF_STATUS))); 2239 2240 for (i = 0; i < 2000; i++) { 2241 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2242 return; 2243 } 2244 DELAY_MS(2, ph->ph_parent); 2245 #ifdef CBB_DEBUG 2246 if ((i > 1000) && (i % 25 == 24)) 2247 printf("."); 2248 #endif 2249 } 2250 2251 #ifdef DIAGNOSTIC 2252 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2253 Pcic_read(ph, PCIC_IF_STATUS)); 2254 #endif 2255 } 2256 2257 /* 2258 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2259 * 2260 * This function enables the card. All information is stored in 2261 * the first argument, pcmcia_chipset_handle_t. 2262 */ 2263 STATIC void 2264 pccbb_pcmcia_socket_enable(pch) 2265 pcmcia_chipset_handle_t pch; 2266 { 2267 struct pcic_handle *ph = (struct pcic_handle *)pch; 2268 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2269 int cardtype, win; 2270 u_int8_t power, intr; 2271 pcireg_t spsr; 2272 int voltage; 2273 2274 /* this bit is mostly stolen from pcic_attach_card */ 2275 2276 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2277 2278 /* get card Vcc info */ 2279 2280 spsr = 2281 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2282 CB_SOCKET_STAT); 2283 if (spsr & CB_SOCKET_STAT_5VCARD) { 2284 DPRINTF(("5V card\n")); 2285 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2286 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2287 DPRINTF(("3V card\n")); 2288 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2289 } else { 2290 printf("?V card, 0x%x\n", spsr); /* XXX */ 2291 return; 2292 } 2293 2294 /* disable socket: negate output enable bit and power off */ 2295 2296 power = 0; 2297 Pcic_write(ph, PCIC_PWRCTL, power); 2298 2299 /* power down the socket to reset it, clear the card reset pin */ 2300 2301 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2302 2303 /* 2304 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2305 * we are changing Vcc (Toff). 2306 */ 2307 /* delay(300*1000); too much */ 2308 2309 /* assert reset bit */ 2310 intr = Pcic_read(ph, PCIC_INTR); 2311 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2312 Pcic_write(ph, PCIC_INTR, intr); 2313 2314 /* power up the socket and output enable */ 2315 power = Pcic_read(ph, PCIC_PWRCTL); 2316 power |= PCIC_PWRCTL_OE; 2317 Pcic_write(ph, PCIC_PWRCTL, power); 2318 pccbb_power(sc, voltage); 2319 2320 /* 2321 * hold RESET at least 20 ms: the spec says only 10 us is 2322 * enough, but TI1130 requires at least 20 ms. 2323 */ 2324 #if 0 /* XXX called on interrupt context */ 2325 DELAY_MS(20, sc); 2326 #else 2327 delay(20 * 1000); 2328 #endif 2329 2330 /* clear the reset flag */ 2331 2332 intr |= PCIC_INTR_RESET; 2333 Pcic_write(ph, PCIC_INTR, intr); 2334 2335 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2336 2337 #if 0 /* XXX called on interrupt context */ 2338 DELAY_MS(20, sc); 2339 #else 2340 delay(20 * 1000); 2341 #endif 2342 2343 /* wait for the chip to finish initializing */ 2344 2345 pccbb_pcmcia_wait_ready(ph); 2346 2347 /* zero out the address windows */ 2348 2349 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2350 2351 /* set the card type */ 2352 2353 cardtype = pcmcia_card_gettype(ph->pcmcia); 2354 2355 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2356 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2357 Pcic_write(ph, PCIC_INTR, intr); 2358 2359 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2360 ph->ph_parent->dv_xname, ph->sock, 2361 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2362 2363 /* reinstall all the memory and io mappings */ 2364 2365 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2366 if (ph->memalloc & (1 << win)) { 2367 pccbb_pcmcia_do_mem_map(ph, win); 2368 } 2369 } 2370 2371 for (win = 0; win < PCIC_IO_WINS; ++win) { 2372 if (ph->ioalloc & (1 << win)) { 2373 pccbb_pcmcia_do_io_map(ph, win); 2374 } 2375 } 2376 } 2377 2378 /* 2379 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2380 * 2381 * This function disables the card. All information is stored in 2382 * the first argument, pcmcia_chipset_handle_t. 2383 */ 2384 STATIC void 2385 pccbb_pcmcia_socket_disable(pch) 2386 pcmcia_chipset_handle_t pch; 2387 { 2388 struct pcic_handle *ph = (struct pcic_handle *)pch; 2389 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2390 u_int8_t power, intr; 2391 2392 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2393 2394 /* reset signal asserting... */ 2395 2396 intr = Pcic_read(ph, PCIC_INTR); 2397 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2398 Pcic_write(ph, PCIC_INTR, intr); 2399 delay(2 * 1000); 2400 2401 /* power down the socket */ 2402 power = Pcic_read(ph, PCIC_PWRCTL); 2403 power &= ~PCIC_PWRCTL_OE; 2404 Pcic_write(ph, PCIC_PWRCTL, power); 2405 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2406 /* 2407 * wait 300ms until power fails (Tpf). 2408 */ 2409 #if 0 /* XXX called on interrupt context */ 2410 DELAY_MS(300, sc); 2411 #else 2412 delay(300 * 1000); 2413 #endif 2414 } 2415 2416 /* 2417 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2418 * 2419 * This function detects whether a card is in the slot or not. 2420 * If a card is inserted, return 1. Otherwise, return 0. 2421 */ 2422 STATIC int 2423 pccbb_pcmcia_card_detect(pch) 2424 pcmcia_chipset_handle_t pch; 2425 { 2426 struct pcic_handle *ph = (struct pcic_handle *)pch; 2427 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2428 2429 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2430 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2431 } 2432 2433 #if 0 2434 STATIC int 2435 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2436 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2437 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2438 #endif 2439 /* 2440 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2441 * bus_size_t size, 2442 * struct pcmcia_mem_handle *pcmhp) 2443 * 2444 * This function only allocates memory region for pccard. This 2445 * function never maps the allocated region to pccard memory area. 2446 * 2447 * XXX: Why the argument of start address is not in? 2448 */ 2449 STATIC int 2450 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2451 pcmcia_chipset_handle_t pch; 2452 bus_size_t size; 2453 struct pcmcia_mem_handle *pcmhp; 2454 { 2455 struct pcic_handle *ph = (struct pcic_handle *)pch; 2456 bus_space_handle_t memh; 2457 bus_addr_t addr; 2458 bus_size_t sizepg; 2459 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2460 #if rbus 2461 rbus_tag_t rb; 2462 #endif 2463 2464 /* out of sc->memh, allocate as many pages as necessary */ 2465 2466 /* convert size to PCIC pages */ 2467 /* 2468 * This is not enough; when the requested region is on the page 2469 * boundaries, this may calculate wrong result. 2470 */ 2471 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2472 #if 0 2473 if (sizepg > PCIC_MAX_MEM_PAGES) { 2474 return 1; 2475 } 2476 #endif 2477 2478 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2479 return 1; 2480 } 2481 2482 addr = 0; /* XXX gcc -Wuninitialized */ 2483 2484 #if rbus 2485 rb = sc->sc_rbus_memt; 2486 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2487 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2488 &addr, &memh)) { 2489 return 1; 2490 } 2491 #else 2492 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2493 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2494 0, /* boundary */ 2495 0, /* flags */ 2496 &addr, &memh)) { 2497 return 1; 2498 } 2499 #endif 2500 2501 DPRINTF( 2502 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2503 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2504 2505 pcmhp->memt = sc->sc_memt; 2506 pcmhp->memh = memh; 2507 pcmhp->addr = addr; 2508 pcmhp->size = size; 2509 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2510 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2511 pcmhp->mhandle = 0; 2512 /* No offset??? Funny. */ 2513 2514 return 0; 2515 } 2516 2517 /* 2518 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2519 * struct pcmcia_mem_handle *pcmhp) 2520 * 2521 * This function release the memory space allocated by the function 2522 * pccbb_pcmcia_mem_alloc(). 2523 */ 2524 STATIC void 2525 pccbb_pcmcia_mem_free(pch, pcmhp) 2526 pcmcia_chipset_handle_t pch; 2527 struct pcmcia_mem_handle *pcmhp; 2528 { 2529 #if rbus 2530 struct pcic_handle *ph = (struct pcic_handle *)pch; 2531 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2532 2533 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2534 #else 2535 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2536 #endif 2537 } 2538 2539 /* 2540 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2541 * 2542 * This function release the memory space allocated by the function 2543 * pccbb_pcmcia_mem_alloc(). 2544 */ 2545 STATIC void 2546 pccbb_pcmcia_do_mem_map(ph, win) 2547 struct pcic_handle *ph; 2548 int win; 2549 { 2550 int regbase_win; 2551 bus_addr_t phys_addr; 2552 bus_addr_t phys_end; 2553 2554 #define PCIC_SMM_START_LOW 0 2555 #define PCIC_SMM_START_HIGH 1 2556 #define PCIC_SMM_STOP_LOW 2 2557 #define PCIC_SMM_STOP_HIGH 3 2558 #define PCIC_CMA_LOW 4 2559 #define PCIC_CMA_HIGH 5 2560 2561 u_int8_t start_low, start_high = 0; 2562 u_int8_t stop_low, stop_high; 2563 u_int8_t off_low, off_high; 2564 u_int8_t mem_window; 2565 int reg; 2566 2567 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2568 int mem8 = 2569 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2570 || (kind == PCMCIA_MEM_ATTR); 2571 2572 regbase_win = 0x10 + win * 0x08; 2573 2574 phys_addr = ph->mem[win].addr; 2575 phys_end = phys_addr + ph->mem[win].size; 2576 2577 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2578 phys_addr, phys_end, ph->mem[win].offset)); 2579 2580 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2581 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2582 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2583 2584 /* bit 19:12 */ 2585 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2586 /* bit 23:20 and bit 7 on */ 2587 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2588 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2589 /* bit 31:24, for 32-bit address */ 2590 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2591 2592 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2593 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2594 2595 if (((struct pccbb_softc *)ph-> 2596 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2597 Pcic_write(ph, 0x40 + win, mem_window); 2598 } 2599 2600 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2601 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2602 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2603 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2604 2605 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2606 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2607 2608 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2609 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2610 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2611 | ((kind == PCMCIA_MEM_ATTR) ? 2612 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2613 2614 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2615 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2616 2617 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2618 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2619 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2620 2621 #if defined CBB_DEBUG 2622 { 2623 int r1, r2, r3, r4, r5, r6, r7 = 0; 2624 2625 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2626 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2627 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2628 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2629 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2630 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2631 if (((struct pccbb_softc *)(ph-> 2632 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2633 r7 = Pcic_read(ph, 0x40 + win); 2634 } 2635 2636 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2637 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2638 if (((struct pccbb_softc *)(ph-> 2639 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2640 DPRINTF((" %02x", r7)); 2641 } 2642 DPRINTF(("\n")); 2643 } 2644 #endif 2645 } 2646 2647 /* 2648 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2649 * bus_addr_t card_addr, bus_size_t size, 2650 * struct pcmcia_mem_handle *pcmhp, 2651 * bus_addr_t *offsetp, int *windowp) 2652 * 2653 * This function maps memory space allocated by the function 2654 * pccbb_pcmcia_mem_alloc(). 2655 */ 2656 STATIC int 2657 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2658 pcmcia_chipset_handle_t pch; 2659 int kind; 2660 bus_addr_t card_addr; 2661 bus_size_t size; 2662 struct pcmcia_mem_handle *pcmhp; 2663 bus_addr_t *offsetp; 2664 int *windowp; 2665 { 2666 struct pcic_handle *ph = (struct pcic_handle *)pch; 2667 bus_addr_t busaddr; 2668 long card_offset; 2669 int win; 2670 2671 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2672 if ((ph->memalloc & (1 << win)) == 0) { 2673 ph->memalloc |= (1 << win); 2674 break; 2675 } 2676 } 2677 2678 if (win == PCIC_MEM_WINS) { 2679 return 1; 2680 } 2681 2682 *windowp = win; 2683 2684 /* XXX this is pretty gross */ 2685 2686 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2687 panic("pccbb_pcmcia_mem_map memt is bogus"); 2688 } 2689 2690 busaddr = pcmhp->addr; 2691 2692 /* 2693 * compute the address offset to the pcmcia address space for the 2694 * pcic. this is intentionally signed. The masks and shifts below 2695 * will cause TRT to happen in the pcic registers. Deal with making 2696 * sure the address is aligned, and return the alignment offset. 2697 */ 2698 2699 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2700 card_addr -= *offsetp; 2701 2702 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2703 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2704 (u_long) card_addr)); 2705 2706 /* 2707 * include the offset in the size, and decrement size by one, since 2708 * the hw wants start/stop 2709 */ 2710 size += *offsetp - 1; 2711 2712 card_offset = (((long)card_addr) - ((long)busaddr)); 2713 2714 ph->mem[win].addr = busaddr; 2715 ph->mem[win].size = size; 2716 ph->mem[win].offset = card_offset; 2717 ph->mem[win].kind = kind; 2718 2719 pccbb_pcmcia_do_mem_map(ph, win); 2720 2721 return 0; 2722 } 2723 2724 /* 2725 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2726 * int window) 2727 * 2728 * This function unmaps memory space which mapped by the function 2729 * pccbb_pcmcia_mem_map(). 2730 */ 2731 STATIC void 2732 pccbb_pcmcia_mem_unmap(pch, window) 2733 pcmcia_chipset_handle_t pch; 2734 int window; 2735 { 2736 struct pcic_handle *ph = (struct pcic_handle *)pch; 2737 int reg; 2738 2739 if (window >= PCIC_MEM_WINS) { 2740 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2741 } 2742 2743 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2744 reg &= ~(1 << window); 2745 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2746 2747 ph->memalloc &= ~(1 << window); 2748 } 2749 2750 #if defined PCCBB_PCMCIA_POLL 2751 struct pccbb_poll_str { 2752 void *arg; 2753 int (*func) __P((void *)); 2754 int level; 2755 struct pcic_handle *ph; 2756 int count; 2757 int num; 2758 struct callout poll_ch; 2759 }; 2760 2761 static struct pccbb_poll_str pccbb_poll[10]; 2762 static int pccbb_poll_n = 0; 2763 2764 static void pccbb_pcmcia_poll __P((void *arg)); 2765 2766 static void 2767 pccbb_pcmcia_poll(arg) 2768 void *arg; 2769 { 2770 struct pccbb_poll_str *poll = arg; 2771 struct pcic_handle *ph = poll->ph; 2772 struct pccbb_softc *sc = ph->sc; 2773 int s; 2774 u_int32_t spsr; /* socket present-state reg */ 2775 2776 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2777 switch (poll->level) { 2778 case IPL_NET: 2779 s = splnet(); 2780 break; 2781 case IPL_BIO: 2782 s = splbio(); 2783 break; 2784 case IPL_TTY: /* fallthrough */ 2785 default: 2786 s = spltty(); 2787 break; 2788 } 2789 2790 spsr = 2791 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2792 CB_SOCKET_STAT); 2793 2794 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2795 if (!(spsr & 0x40)) /* CINT low */ 2796 #else 2797 if (1) 2798 #endif 2799 { 2800 if ((*poll->func) (poll->arg) > 0) { 2801 ++poll->count; 2802 // printf("intr: reported from poller, 0x%x\n", spsr); 2803 #if defined LEVEL2 2804 } else { 2805 printf("intr: miss! 0x%x\n", spsr); 2806 #endif 2807 } 2808 } 2809 splx(s); 2810 } 2811 #endif /* defined CB_PCMCIA_POLL */ 2812 2813 /* 2814 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2815 * struct pcmcia_function *pf, 2816 * int ipl, 2817 * int (*func)(void *), 2818 * void *arg); 2819 * 2820 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2821 */ 2822 STATIC void * 2823 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2824 pcmcia_chipset_handle_t pch; 2825 struct pcmcia_function *pf; 2826 int ipl; 2827 int (*func) __P((void *)); 2828 void *arg; 2829 { 2830 struct pcic_handle *ph = (struct pcic_handle *)pch; 2831 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2832 2833 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2834 /* what should I do? */ 2835 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2836 DPRINTF( 2837 ("%s does not provide edge nor pulse interrupt\n", 2838 sc->sc_dev.dv_xname)); 2839 return NULL; 2840 } 2841 /* 2842 * XXX Noooooo! The interrupt flag must set properly!! 2843 * dumb pcmcia driver!! 2844 */ 2845 } 2846 2847 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2848 } 2849 2850 /* 2851 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2852 * void *ih) 2853 * 2854 * This function disables PC-Card interrupt. 2855 */ 2856 STATIC void 2857 pccbb_pcmcia_intr_disestablish(pch, ih) 2858 pcmcia_chipset_handle_t pch; 2859 void *ih; 2860 { 2861 struct pcic_handle *ph = (struct pcic_handle *)pch; 2862 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2863 2864 pccbb_intr_disestablish(sc, ih); 2865 } 2866 2867 #if rbus 2868 /* 2869 * static int 2870 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2871 * bus_addr_t addr, bus_size_t size, 2872 * bus_addr_t mask, bus_size_t align, 2873 * int flags, bus_addr_t *addrp; 2874 * bus_space_handle_t *bshp) 2875 * 2876 * This function allocates a portion of memory or io space for 2877 * clients. This function is called from CardBus card drivers. 2878 */ 2879 static int 2880 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2881 cardbus_chipset_tag_t ct; 2882 rbus_tag_t rb; 2883 bus_addr_t addr; 2884 bus_size_t size; 2885 bus_addr_t mask; 2886 bus_size_t align; 2887 int flags; 2888 bus_addr_t *addrp; 2889 bus_space_handle_t *bshp; 2890 { 2891 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2892 2893 DPRINTF( 2894 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2895 addr, size, mask, align)); 2896 2897 if (align == 0) { 2898 align = size; 2899 } 2900 2901 if (rb->rb_bt == sc->sc_memt) { 2902 if (align < 16) { 2903 return 1; 2904 } 2905 } else if (rb->rb_bt == sc->sc_iot) { 2906 if (align < 4) { 2907 return 1; 2908 } 2909 /* XXX: hack for avoiding ISA image */ 2910 if (mask < 0x0100) { 2911 mask = 0x3ff; 2912 addr = 0x300; 2913 } 2914 2915 } else { 2916 DPRINTF( 2917 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2918 rb->rb_bt)); 2919 return 1; 2920 /* XXX: panic here? */ 2921 } 2922 2923 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2924 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2925 return 1; 2926 } 2927 2928 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2929 2930 return 0; 2931 } 2932 2933 /* 2934 * static int 2935 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2936 * bus_space_handle_t *bshp, bus_size_t size); 2937 * 2938 * This function is called from CardBus card drivers. 2939 */ 2940 static int 2941 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2942 cardbus_chipset_tag_t ct; 2943 rbus_tag_t rb; 2944 bus_space_handle_t bsh; 2945 bus_size_t size; 2946 { 2947 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2948 bus_space_tag_t bt = rb->rb_bt; 2949 2950 pccbb_close_win(sc, bt, bsh, size); 2951 2952 if (bt == sc->sc_memt) { 2953 } else if (bt == sc->sc_iot) { 2954 } else { 2955 return 1; 2956 /* XXX: panic here? */ 2957 } 2958 2959 return rbus_space_free(rb, bsh, size, NULL); 2960 } 2961 #endif /* rbus */ 2962 2963 #if rbus 2964 2965 static int 2966 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2967 struct pccbb_softc *sc; 2968 bus_space_tag_t bst; 2969 bus_addr_t addr; 2970 bus_size_t size; 2971 bus_space_handle_t bsh; 2972 int flags; 2973 { 2974 struct pccbb_win_chain_head *head; 2975 bus_addr_t align; 2976 2977 head = &sc->sc_iowindow; 2978 align = 0x04; 2979 if (sc->sc_memt == bst) { 2980 head = &sc->sc_memwindow; 2981 align = 0x1000; 2982 DPRINTF(("using memory window, %x %x %x\n\n", 2983 sc->sc_iot, sc->sc_memt, bst)); 2984 } 2985 2986 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2987 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2988 sc->sc_dev.dv_xname, 2989 (head == &sc->sc_memwindow) ? "mem" : "io"); 2990 } 2991 pccbb_winset(align, sc, bst); 2992 2993 return 0; 2994 } 2995 2996 static int 2997 pccbb_close_win(sc, bst, bsh, size) 2998 struct pccbb_softc *sc; 2999 bus_space_tag_t bst; 3000 bus_space_handle_t bsh; 3001 bus_size_t size; 3002 { 3003 struct pccbb_win_chain_head *head; 3004 bus_addr_t align; 3005 3006 head = &sc->sc_iowindow; 3007 align = 0x04; 3008 if (sc->sc_memt == bst) { 3009 head = &sc->sc_memwindow; 3010 align = 0x1000; 3011 } 3012 3013 if (pccbb_winlist_delete(head, bsh, size)) { 3014 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3015 sc->sc_dev.dv_xname, 3016 (head == &sc->sc_memwindow) ? "mem" : "io"); 3017 } 3018 pccbb_winset(align, sc, bst); 3019 3020 return 0; 3021 } 3022 3023 static int 3024 pccbb_winlist_insert(head, start, size, bsh, flags) 3025 struct pccbb_win_chain_head *head; 3026 bus_addr_t start; 3027 bus_size_t size; 3028 bus_space_handle_t bsh; 3029 int flags; 3030 { 3031 struct pccbb_win_chain *chainp, *elem; 3032 3033 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3034 M_NOWAIT)) == NULL) 3035 return (1); /* fail */ 3036 3037 elem->wc_start = start; 3038 elem->wc_end = start + (size - 1); 3039 elem->wc_handle = bsh; 3040 elem->wc_flags = flags; 3041 3042 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3043 chainp = TAILQ_NEXT(chainp, wc_list)) { 3044 if (chainp->wc_end < start) 3045 continue; 3046 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3047 return (0); 3048 } 3049 3050 TAILQ_INSERT_TAIL(head, elem, wc_list); 3051 return (0); 3052 } 3053 3054 static int 3055 pccbb_winlist_delete(head, bsh, size) 3056 struct pccbb_win_chain_head *head; 3057 bus_space_handle_t bsh; 3058 bus_size_t size; 3059 { 3060 struct pccbb_win_chain *chainp; 3061 3062 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3063 chainp = TAILQ_NEXT(chainp, wc_list)) { 3064 if (chainp->wc_handle != bsh) 3065 continue; 3066 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3067 printf("pccbb_winlist_delete: window 0x%lx size " 3068 "inconsistent: 0x%lx, 0x%lx\n", 3069 chainp->wc_start, 3070 chainp->wc_end - chainp->wc_start, 3071 size - 1); 3072 return 1; 3073 } 3074 3075 TAILQ_REMOVE(head, chainp, wc_list); 3076 free(chainp, M_DEVBUF); 3077 3078 return 0; 3079 } 3080 3081 return 1; /* fail: no candidate to remove */ 3082 } 3083 3084 static void 3085 pccbb_winset(align, sc, bst) 3086 bus_addr_t align; 3087 struct pccbb_softc *sc; 3088 bus_space_tag_t bst; 3089 { 3090 pci_chipset_tag_t pc; 3091 pcitag_t tag; 3092 bus_addr_t mask = ~(align - 1); 3093 struct { 3094 cardbusreg_t win_start; 3095 cardbusreg_t win_limit; 3096 int win_flags; 3097 } win[2]; 3098 struct pccbb_win_chain *chainp; 3099 int offs; 3100 3101 win[0].win_start = win[1].win_start = 0xffffffff; 3102 win[0].win_limit = win[1].win_limit = 0; 3103 win[0].win_flags = win[1].win_flags = 0; 3104 3105 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3106 offs = 0x2c; 3107 if (sc->sc_memt == bst) { 3108 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3109 offs = 0x1c; 3110 } 3111 3112 if (chainp != NULL) { 3113 win[0].win_start = chainp->wc_start & mask; 3114 win[0].win_limit = chainp->wc_end & mask; 3115 win[0].win_flags = chainp->wc_flags; 3116 chainp = TAILQ_NEXT(chainp, wc_list); 3117 } 3118 3119 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3120 if (win[1].win_start == 0xffffffff) { 3121 /* window 1 is not used */ 3122 if ((win[0].win_flags == chainp->wc_flags) && 3123 (win[0].win_limit + align >= 3124 (chainp->wc_start & mask))) { 3125 /* concatenate */ 3126 win[0].win_limit = chainp->wc_end & mask; 3127 } else { 3128 /* make new window */ 3129 win[1].win_start = chainp->wc_start & mask; 3130 win[1].win_limit = chainp->wc_end & mask; 3131 win[1].win_flags = chainp->wc_flags; 3132 } 3133 continue; 3134 } 3135 3136 /* Both windows are engaged. */ 3137 if (win[0].win_flags == win[1].win_flags) { 3138 /* same flags */ 3139 if (win[0].win_flags == chainp->wc_flags) { 3140 if (win[1].win_start - (win[0].win_limit + 3141 align) < 3142 (chainp->wc_start & mask) - 3143 ((chainp->wc_end & mask) + align)) { 3144 /* 3145 * merge window 0 and 1, and set win1 3146 * to chainp 3147 */ 3148 win[0].win_limit = win[1].win_limit; 3149 win[1].win_start = 3150 chainp->wc_start & mask; 3151 win[1].win_limit = 3152 chainp->wc_end & mask; 3153 } else { 3154 win[1].win_limit = 3155 chainp->wc_end & mask; 3156 } 3157 } else { 3158 /* different flags */ 3159 3160 /* concatenate win0 and win1 */ 3161 win[0].win_limit = win[1].win_limit; 3162 /* allocate win[1] to new space */ 3163 win[1].win_start = chainp->wc_start & mask; 3164 win[1].win_limit = chainp->wc_end & mask; 3165 win[1].win_flags = chainp->wc_flags; 3166 } 3167 } else { 3168 /* the flags of win[0] and win[1] is different */ 3169 if (win[0].win_flags == chainp->wc_flags) { 3170 win[0].win_limit = chainp->wc_end & mask; 3171 /* 3172 * XXX this creates overlapping windows, so 3173 * what should the poor bridge do if one is 3174 * cachable, and the other is not? 3175 */ 3176 printf("%s: overlapping windows\n", 3177 sc->sc_dev.dv_xname); 3178 } else { 3179 win[1].win_limit = chainp->wc_end & mask; 3180 } 3181 } 3182 } 3183 3184 pc = sc->sc_pc; 3185 tag = sc->sc_tag; 3186 pci_conf_write(pc, tag, offs, win[0].win_start); 3187 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3188 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3189 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3190 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3191 pci_conf_read(pc, tag, offs), 3192 pci_conf_read(pc, tag, offs + 4) + align, 3193 pci_conf_read(pc, tag, offs + 8), 3194 pci_conf_read(pc, tag, offs + 12) + align)); 3195 3196 if (bst == sc->sc_memt) { 3197 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3198 3199 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3200 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3201 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3202 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3203 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3204 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3205 } 3206 } 3207 3208 #endif /* rbus */ 3209 3210 static void 3211 pccbb_powerhook(why, arg) 3212 int why; 3213 void *arg; 3214 { 3215 struct pccbb_softc *sc = arg; 3216 u_int32_t reg; 3217 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3218 bus_space_handle_t base_memh = sc->sc_base_memh; 3219 3220 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3221 3222 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3223 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3224 if (sc->sc_pil_intr_enable) { 3225 (void)pccbbintr_function(sc); 3226 } 3227 sc->sc_pil_intr_enable = 0; 3228 3229 /* ToDo: deactivate or suspend child devices */ 3230 3231 } 3232 3233 if (why == PWR_RESUME) { 3234 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3235 /* BIOS did not recover this register */ 3236 pci_conf_write (sc->sc_pc, sc->sc_tag, 3237 PCI_SOCKBASE, sc->sc_sockbase); 3238 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3239 /* BIOS did not recover this register */ 3240 pci_conf_write (sc->sc_pc, sc->sc_tag, 3241 PCI_BUSNUM, sc->sc_busnum); 3242 /* CSC Interrupt: Card detect interrupt on */ 3243 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3244 /* Card detect intr is turned on. */ 3245 reg |= CB_SOCKET_MASK_CD; 3246 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3247 /* reset interrupt */ 3248 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3249 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3250 3251 /* 3252 * check for card insertion or removal during suspend period. 3253 * XXX: the code can't cope with card swap (remove then 3254 * insert). how can we detect such situation? 3255 */ 3256 (void)pccbbintr(sc); 3257 3258 sc->sc_pil_intr_enable = 1; 3259 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3260 3261 /* ToDo: activate or wakeup child devices */ 3262 } 3263 } 3264
Indexes created Fri Sep 26 08:10:20 GMT 2025