pccbb.c revision 1.66
1 /* $NetBSD: pccbb.c,v 1.66 2001/08/24 10:55:53 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/reboot.h> /* for bootverbose */ 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 #include <sys/proc.h> 57 58 #include <machine/intr.h> 59 #include <machine/bus.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/pccbbreg.h> 66 67 #include <dev/cardbus/cardslotvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 71 #include <dev/pcmcia/pcmciareg.h> 72 #include <dev/pcmcia/pcmciavar.h> 73 74 #include <dev/ic/i82365reg.h> 75 #include <dev/ic/i82365var.h> 76 #include <dev/pci/pccbbvar.h> 77 78 #include "locators.h" 79 80 #ifndef __NetBSD_Version__ 81 struct cfdriver cbb_cd = { 82 NULL, "cbb", DV_DULL 83 }; 84 #endif 85 86 #if defined CBB_DEBUG 87 #define DPRINTF(x) printf x 88 #define STATIC 89 #else 90 #define DPRINTF(x) 91 #define STATIC static 92 #endif 93 94 /* 95 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 96 * if you want to wait more than 1 ms. 97 */ 98 #define DELAY_MS(time, param) \ 99 do { \ 100 if (cold == 0) { \ 101 int tick = (hz*(time))/1000; \ 102 \ 103 if (tick <= 1) { \ 104 tick = 2; \ 105 } \ 106 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 107 } else { \ 108 delay((time)*1000); \ 109 } \ 110 } while (0) 111 112 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 113 void pccbbattach __P((struct device *, struct device *, void *)); 114 int pccbbintr __P((void *)); 115 static void pci113x_insert __P((void *)); 116 static int pccbbintr_function __P((struct pccbb_softc *)); 117 118 static int pccbb_detect_card __P((struct pccbb_softc *)); 119 120 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 121 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset __P((struct pccbb_softc *)); 126 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 127 STATIC int cbbprint __P((void *, const char *)); 128 129 static int cb_chipset __P((u_int32_t, int *)); 130 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 131 struct pcmciabus_attach_args *)); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 134 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 135 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 136 #endif 137 138 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 139 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 140 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 141 #if !rbus 142 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 143 u_int32_t)); 144 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 145 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 146 u_int32_t)); 147 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc)); 151 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 152 153 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc)); 155 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 156 157 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 158 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 159 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 160 int)); 161 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 162 cardbusreg_t)); 163 static void pccbb_chipinit __P((struct pccbb_softc *)); 164 165 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 166 struct pcmcia_mem_handle *)); 167 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 168 struct pcmcia_mem_handle *)); 169 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 171 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 172 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 173 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 174 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *)); 176 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *)); 178 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 179 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 180 struct pcmcia_function *, int, int (*)(void *), void *)); 181 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 182 void *)); 183 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 184 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 185 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 186 187 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 188 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 189 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 190 static void pccbb_powerhook __P((int, void *)); 191 192 /* bus-space allocation and deallocation functions */ 193 #if rbus 194 195 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 196 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 197 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 198 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 199 bus_space_handle_t, bus_size_t)); 200 201 #endif /* rbus */ 202 203 #if rbus 204 205 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 206 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 207 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_space_handle_t, bus_size_t)); 209 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 210 bus_size_t, bus_space_handle_t, int)); 211 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 212 bus_space_handle_t, bus_size_t)); 213 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 214 bus_space_tag_t)); 215 void pccbb_winlist_show(struct pccbb_win_chain *); 216 217 #endif /* rbus */ 218 219 /* for config_defer */ 220 static void pccbb_pci_callback __P((struct device *)); 221 222 #if defined SHOW_REGS 223 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 224 bus_space_tag_t memt, bus_space_handle_t memh)); 225 #endif 226 227 struct cfattach cbb_pci_ca = { 228 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 229 }; 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_card_detect 245 }; 246 247 #if rbus 248 static struct cardbus_functions pccbb_funcs = { 249 pccbb_rbus_cb_space_alloc, 250 pccbb_rbus_cb_space_free, 251 pccbb_cb_intr_establish, 252 pccbb_cb_intr_disestablish, 253 pccbb_ctrl, 254 pccbb_power, 255 pccbb_make_tag, 256 pccbb_free_tag, 257 pccbb_conf_read, 258 pccbb_conf_write, 259 }; 260 #else 261 static struct cardbus_functions pccbb_funcs = { 262 pccbb_ctrl, 263 pccbb_power, 264 pccbb_mem_open, 265 pccbb_mem_close, 266 pccbb_io_open, 267 pccbb_io_close, 268 pccbb_cb_intr_establish, 269 pccbb_cb_intr_disestablish, 270 pccbb_make_tag, 271 pccbb_conf_read, 272 pccbb_conf_write, 273 }; 274 #endif 275 276 int 277 pcicbbmatch(parent, match, aux) 278 struct device *parent; 279 struct cfdata *match; 280 void *aux; 281 { 282 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 283 284 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 285 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 286 PCI_INTERFACE(pa->pa_class) == 0) { 287 return 1; 288 } 289 290 return 0; 291 } 292 293 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 294 | ((prod) << PCI_PRODUCT_SHIFT)) 295 296 const struct yenta_chipinfo { 297 pcireg_t yc_id; /* vendor tag | product tag */ 298 int yc_chiptype; 299 int yc_flags; 300 } yc_chipsets[] = { 301 /* Texas Instruments chips */ 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 329 /* Ricoh chips */ 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 331 PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 341 PCCBB_PCMCIA_MEM_32}, 342 343 /* Toshiba products */ 344 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 345 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 347 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 349 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 351 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 352 353 /* Cirrus Logic products */ 354 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 355 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 357 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 358 359 /* sentinel, or Generic chip */ 360 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 361 }; 362 363 static int 364 cb_chipset(pci_id, flagp) 365 u_int32_t pci_id; 366 int *flagp; 367 { 368 const struct yenta_chipinfo *yc; 369 370 /* Loop over except the last default entry. */ 371 for (yc = yc_chipsets; yc < yc_chipsets + 372 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 373 if (pci_id == yc->yc_id) 374 break; 375 376 if (flagp != NULL) 377 *flagp = yc->yc_flags; 378 379 return (yc->yc_chiptype); 380 } 381 382 static void 383 pccbb_shutdown(void *arg) 384 { 385 struct pccbb_softc *sc = arg; 386 pcireg_t command; 387 388 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 389 390 /* 391 * turn off power 392 * 393 * XXX - do not turn off power if chipset is TI 113X because 394 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 395 */ 396 if (sc->sc_chipset != CB_TI113X) { 397 pccbb_power((cardbus_chipset_tag_t)sc, 398 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 399 } 400 401 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 402 0); 403 404 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 405 406 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 407 PCI_COMMAND_MASTER_ENABLE); 408 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 409 410 } 411 412 void 413 pccbbattach(parent, self, aux) 414 struct device *parent; 415 struct device *self; 416 void *aux; 417 { 418 struct pccbb_softc *sc = (void *)self; 419 struct pci_attach_args *pa = aux; 420 pci_chipset_tag_t pc = pa->pa_pc; 421 pcireg_t busreg, reg, sock_base; 422 bus_addr_t sockbase; 423 char devinfo[256]; 424 int flags; 425 426 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 427 428 pci_devinfo(pa->pa_id, 0, 0, devinfo); 429 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 430 #ifdef CBB_DEBUG 431 printf(" (chipflags %x)", flags); 432 #endif 433 printf("\n"); 434 435 TAILQ_INIT(&sc->sc_memwindow); 436 TAILQ_INIT(&sc->sc_iowindow); 437 438 #if rbus 439 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 440 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 441 442 #if 0 443 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 444 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 445 #endif 446 #endif /* rbus */ 447 448 sc->sc_base_memh = 0; 449 450 /* 451 * MAP socket registers and ExCA registers on memory-space 452 * When no valid address is set on socket base registers (on pci 453 * config space), get it not polite way. 454 */ 455 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 456 457 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 458 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 459 /* The address must be valid. */ 460 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 461 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 462 printf("%s: can't map socket base address 0x%x\n", 463 sc->sc_dev.dv_xname, sock_base); 464 /* 465 * I think it's funny: socket base registers must be 466 * mapped on memory space, but ... 467 */ 468 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 469 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 470 NULL)) { 471 printf("%s: can't map socket base address" 472 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 473 (unsigned long)sockbase); 474 /* give up... allocate reg space via rbus. */ 475 sc->sc_base_memh = 0; 476 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 477 } 478 } else { 479 DPRINTF(("%s: socket base address 0x%lx\n", 480 sc->sc_dev.dv_xname, sockbase)); 481 } 482 } 483 484 sc->sc_mem_start = 0; /* XXX */ 485 sc->sc_mem_end = 0xffffffff; /* XXX */ 486 487 /* 488 * When interrupt isn't routed correctly, give up probing cbb and do 489 * not kill pcic-compatible port. 490 */ 491 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 492 printf("%s: NOT USED because of unconfigured interrupt\n", 493 sc->sc_dev.dv_xname); 494 return; 495 } 496 497 /* 498 * When bus number isn't set correctly, give up using 32-bit CardBus 499 * mode. 500 */ 501 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 502 #if notyet 503 if (((busreg >> 8) & 0xff) == 0) { 504 printf("%s: CardBus support disabled because of unconfigured bus number\n", 505 sc->sc_dev.dv_xname); 506 flags |= PCCBB_PCMCIA_16BITONLY; 507 } 508 #endif 509 510 /* pccbb_machdep.c end */ 511 512 #if defined CBB_DEBUG 513 { 514 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 515 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 516 intrname[pa->pa_intrpin], pa->pa_intrline); 517 } 518 #endif 519 520 /* setup softc */ 521 sc->sc_pc = pc; 522 sc->sc_iot = pa->pa_iot; 523 sc->sc_memt = pa->pa_memt; 524 sc->sc_dmat = pa->pa_dmat; 525 sc->sc_tag = pa->pa_tag; 526 sc->sc_function = pa->pa_function; 527 sc->sc_sockbase = sock_base; 528 sc->sc_busnum = busreg; 529 530 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 531 532 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 533 534 shutdownhook_establish(pccbb_shutdown, sc); 535 536 /* Disable legacy register mapping. */ 537 switch (sc->sc_chipset) { 538 case CB_RX5C46X: /* fallthrough */ 539 #if 0 540 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 541 case CB_RX5C47X: 542 #endif 543 /* 544 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 545 * cannot be disabled by substituting 0 into PCI_LEGACY 546 * register. Ricoh CardBus bridges have special bits on Bridge 547 * control reg (addr 0x3e on PCI config space). 548 */ 549 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 550 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 551 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 552 break; 553 554 default: 555 /* XXX I don't know proper way to kill legacy I/O. */ 556 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 557 break; 558 } 559 560 config_defer(self, pccbb_pci_callback); 561 } 562 563 564 565 566 /* 567 * static void pccbb_pci_callback(struct device *self) 568 * 569 * The actual attach routine: get memory space for YENTA register 570 * space, setup YENTA register and route interrupt. 571 * 572 * This function should be deferred because this device may obtain 573 * memory space dynamically. This function must avoid obtaining 574 * memory area which has already kept for another device. 575 */ 576 static void 577 pccbb_pci_callback(self) 578 struct device *self; 579 { 580 struct pccbb_softc *sc = (void *)self; 581 pci_chipset_tag_t pc = sc->sc_pc; 582 bus_space_tag_t base_memt; 583 bus_space_handle_t base_memh; 584 u_int32_t maskreg; 585 pci_intr_handle_t ih; 586 const char *intrstr = NULL; 587 bus_addr_t sockbase; 588 struct cbslot_attach_args cba; 589 struct pcmciabus_attach_args paa; 590 struct cardslot_attach_args caa; 591 struct cardslot_softc *csc; 592 593 if (0 == sc->sc_base_memh) { 594 /* The socket registers aren't mapped correctly. */ 595 #if rbus 596 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 597 (sc->sc_chipset == CB_RX5C47X 598 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 599 0, &sockbase, &sc->sc_base_memh)) { 600 return; 601 } 602 sc->sc_base_memt = sc->sc_memt; 603 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 604 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 605 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 606 PCI_SOCKBASE))); 607 #else 608 sc->sc_base_memt = sc->sc_memt; 609 #if !defined CBB_PCI_BASE 610 #define CBB_PCI_BASE 0x20000000 611 #endif 612 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 613 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 614 /* cannot allocate memory space */ 615 return; 616 } 617 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 618 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 619 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 620 sc->sc_tag, PCI_SOCKBASE))); 621 #endif 622 } 623 624 /* bus bridge initialization */ 625 pccbb_chipinit(sc); 626 627 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 628 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 629 630 /* CSC Interrupt: Card detect interrupt on */ 631 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 632 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 633 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 634 /* reset interrupt */ 635 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 636 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 637 638 /* clear data structure for child device interrupt handlers */ 639 sc->sc_pil = NULL; 640 sc->sc_pil_intr_enable = 1; 641 642 /* Map and establish the interrupt. */ 643 if (pci_intr_map(&sc->sc_pa, &ih)) { 644 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 645 return; 646 } 647 intrstr = pci_intr_string(pc, ih); 648 649 /* 650 * XXX pccbbintr should be called under the priority lower 651 * than any other hard interrputs. 652 */ 653 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 654 655 if (sc->sc_ih == NULL) { 656 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 657 if (intrstr != NULL) { 658 printf(" at %s", intrstr); 659 } 660 printf("\n"); 661 return; 662 } 663 664 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 665 powerhook_establish(pccbb_powerhook, sc); 666 667 { 668 u_int32_t sockstat = 669 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 670 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 671 sc->sc_flags |= CBB_CARDEXIST; 672 } 673 } 674 675 /* 676 * attach cardbus 677 */ 678 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 679 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 680 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 681 682 /* initialize cbslot_attach */ 683 cba.cba_busname = "cardbus"; 684 cba.cba_iot = sc->sc_iot; 685 cba.cba_memt = sc->sc_memt; 686 cba.cba_dmat = sc->sc_dmat; 687 cba.cba_bus = (busreg >> 8) & 0x0ff; 688 cba.cba_cc = (void *)sc; 689 cba.cba_cf = &pccbb_funcs; 690 cba.cba_intrline = sc->sc_pa.pa_intrline; 691 692 #if rbus 693 cba.cba_rbus_iot = sc->sc_rbus_iot; 694 cba.cba_rbus_memt = sc->sc_rbus_memt; 695 #endif 696 697 cba.cba_cacheline = PCI_CACHELINE(bhlc); 698 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 699 700 if (bootverbose) { 701 printf("%s: cacheline 0x%x lattimer 0x%x\n", 702 sc->sc_dev.dv_xname, cba.cba_cacheline, 703 cba.cba_lattimer); 704 printf("%s: bhlc 0x%x lscp 0x%x\n", 705 sc->sc_dev.dv_xname, bhlc, busreg); 706 } 707 #if defined SHOW_REGS 708 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 709 sc->sc_base_memh); 710 #endif 711 } 712 713 pccbb_pcmcia_attach_setup(sc, &paa); 714 caa.caa_cb_attach = NULL; 715 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 716 caa.caa_cb_attach = &cba; 717 } 718 caa.caa_16_attach = &paa; 719 caa.caa_ph = &sc->sc_pcmcia_h; 720 721 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 722 DPRINTF(("pccbbattach: found cardslot\n")); 723 sc->sc_csc = csc; 724 } 725 726 return; 727 } 728 729 730 731 732 733 /* 734 * static void pccbb_chipinit(struct pccbb_softc *sc) 735 * 736 * This function initialize YENTA chip registers listed below: 737 * 1) PCI command reg, 738 * 2) PCI and CardBus latency timer, 739 * 3) route PCI interrupt, 740 * 4) close all memory and io windows. 741 */ 742 static void 743 pccbb_chipinit(sc) 744 struct pccbb_softc *sc; 745 { 746 pci_chipset_tag_t pc = sc->sc_pc; 747 pcitag_t tag = sc->sc_tag; 748 pcireg_t reg; 749 750 /* 751 * Set PCI command reg. 752 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 753 */ 754 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 755 /* I believe it is harmless. */ 756 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 757 PCI_COMMAND_MASTER_ENABLE); 758 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 759 760 /* 761 * Set CardBus latency timer. 762 */ 763 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 764 if (PCI_CB_LATENCY(reg) < 0x20) { 765 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 766 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 767 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 768 } 769 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 770 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 771 772 /* 773 * Set PCI latency timer. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 776 if (PCI_LATTIMER(reg) < 0x10) { 777 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 778 reg |= (0x10 << PCI_LATTIMER_SHIFT); 779 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 780 } 781 DPRINTF(("PCI latency timer 0x%x (%x)\n", 782 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 783 784 785 /* Route functional interrupts to PCI. */ 786 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 787 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 788 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 789 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 790 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 791 792 switch (sc->sc_chipset) { 793 case CB_TI113X: 794 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 795 /* This bit is shared, but may read as 0 on some chips, so set 796 it explicitly on both functions. */ 797 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 798 /* CSC intr enable */ 799 reg |= PCI113X_CBCTRL_PCI_CSC; 800 /* functional intr prohibit | prohibit ISA routing */ 801 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 802 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 803 break; 804 805 case CB_TI12XX: 806 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 807 reg |= PCI12XX_SYSCTRL_VCCPROT; 808 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 809 break; 810 811 case CB_TOPIC95B: 812 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 813 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 814 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 815 816 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 817 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 818 sc->sc_dev.dv_xname, reg)); 819 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 820 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 821 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 822 DPRINTF(("0x%x\n", reg)); 823 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 824 break; 825 } 826 827 /* Close all memory and I/O windows. */ 828 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 829 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 830 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 831 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 832 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 833 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 834 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 835 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 836 837 /* reset 16-bit pcmcia bus */ 838 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 839 0x800 + PCIC_INTR, 840 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 841 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 842 843 /* turn of power */ 844 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 845 } 846 847 848 849 850 /* 851 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 852 * struct pcmciabus_attach_args *paa) 853 * 854 * This function attaches 16-bit PCcard bus. 855 */ 856 STATIC void 857 pccbb_pcmcia_attach_setup(sc, paa) 858 struct pccbb_softc *sc; 859 struct pcmciabus_attach_args *paa; 860 { 861 struct pcic_handle *ph = &sc->sc_pcmcia_h; 862 #if rbus 863 rbus_tag_t rb; 864 #endif 865 866 /* initialize pcmcia part in pccbb_softc */ 867 ph->ph_parent = (struct device *)sc; 868 ph->sock = sc->sc_function; 869 ph->flags = 0; 870 ph->shutdown = 0; 871 ph->ih_irq = sc->sc_pa.pa_intrline; 872 ph->ph_bus_t = sc->sc_base_memt; 873 ph->ph_bus_h = sc->sc_base_memh; 874 ph->ph_read = pccbb_pcmcia_read; 875 ph->ph_write = pccbb_pcmcia_write; 876 sc->sc_pct = &pccbb_pcmcia_funcs; 877 878 /* 879 * We need to do a few things here: 880 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 881 * setting the IRQ numbers to 0. 882 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 883 * routing of CSC interrupts (e.g. card removal) to PCI while in 884 * PCMCIA mode. We just leave this set all the time. 885 * 3) Enable card insertion/removal interrupts in case the chip also 886 * needs that while in PCMCIA mode. 887 * 4) Clear any pending CSC interrupt. 888 */ 889 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 890 if (sc->sc_chipset == CB_TI113X) { 891 Pcic_write(ph, PCIC_CSC_INTR, 0); 892 } else { 893 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 894 Pcic_read(ph, PCIC_CSC); 895 } 896 897 /* initialize pcmcia bus attachment */ 898 paa->paa_busname = "pcmcia"; 899 paa->pct = sc->sc_pct; 900 paa->pch = ph; 901 paa->iobase = 0; /* I don't use them */ 902 paa->iosize = 0; 903 #if rbus 904 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 905 paa->iobase = rb->rb_start + rb->rb_offset; 906 paa->iosize = rb->rb_end - rb->rb_start; 907 #endif 908 909 return; 910 } 911 912 #if 0 913 STATIC void 914 pccbb_pcmcia_attach_card(ph) 915 struct pcic_handle *ph; 916 { 917 if (ph->flags & PCIC_FLAG_CARDP) { 918 panic("pccbb_pcmcia_attach_card: already attached"); 919 } 920 921 /* call the MI attach function */ 922 pcmcia_card_attach(ph->pcmcia); 923 924 ph->flags |= PCIC_FLAG_CARDP; 925 } 926 927 STATIC void 928 pccbb_pcmcia_detach_card(ph, flags) 929 struct pcic_handle *ph; 930 int flags; 931 { 932 if (!(ph->flags & PCIC_FLAG_CARDP)) { 933 panic("pccbb_pcmcia_detach_card: already detached"); 934 } 935 936 ph->flags &= ~PCIC_FLAG_CARDP; 937 938 /* call the MI detach function */ 939 pcmcia_card_detach(ph->pcmcia, flags); 940 } 941 #endif 942 943 /* 944 * int pccbbintr(arg) 945 * void *arg; 946 * This routine handles the interrupt from Yenta PCI-CardBus bridge 947 * itself. 948 */ 949 int 950 pccbbintr(arg) 951 void *arg; 952 { 953 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 954 u_int32_t sockevent, sockstate; 955 bus_space_tag_t memt = sc->sc_base_memt; 956 bus_space_handle_t memh = sc->sc_base_memh; 957 struct pcic_handle *ph = &sc->sc_pcmcia_h; 958 959 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 960 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 961 Pcic_read(ph, PCIC_CSC); 962 963 if (sockevent == 0) { 964 /* This intr is not for me: it may be for my child devices. */ 965 if (sc->sc_pil_intr_enable) { 966 return pccbbintr_function(sc); 967 } else { 968 return 0; 969 } 970 } 971 972 if (sockevent & CB_SOCKET_EVENT_CD) { 973 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 974 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 975 /* A card should be removed. */ 976 if (sc->sc_flags & CBB_CARDEXIST) { 977 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 978 sockevent)); 979 DPRINTF((" card removed, 0x%08x\n", sockstate)); 980 sc->sc_flags &= ~CBB_CARDEXIST; 981 if (sc->sc_csc->sc_status & 982 CARDSLOT_STATUS_CARD_16) { 983 #if 0 984 struct pcic_handle *ph = 985 &sc->sc_pcmcia_h; 986 987 pcmcia_card_deactivate(ph->pcmcia); 988 pccbb_pcmcia_socket_disable(ph); 989 pccbb_pcmcia_detach_card(ph, 990 DETACH_FORCE); 991 #endif 992 cardslot_event_throw(sc->sc_csc, 993 CARDSLOT_EVENT_REMOVAL_16); 994 } else if (sc->sc_csc->sc_status & 995 CARDSLOT_STATUS_CARD_CB) { 996 /* Cardbus intr removed */ 997 cardslot_event_throw(sc->sc_csc, 998 CARDSLOT_EVENT_REMOVAL_CB); 999 } 1000 } 1001 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1002 /* 1003 * The pccbbintr may called from powerdown hook when 1004 * the system resumed, to detect the card 1005 * insertion/removal during suspension. 1006 */ 1007 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1008 if (sc->sc_flags & CBB_INSERTING) { 1009 callout_stop(&sc->sc_insert_ch); 1010 } 1011 callout_reset(&sc->sc_insert_ch, hz / 10, 1012 pci113x_insert, sc); 1013 sc->sc_flags |= CBB_INSERTING; 1014 } 1015 } 1016 1017 return (1); 1018 } 1019 1020 /* 1021 * static int pccbbintr_function(struct pccbb_softc *sc) 1022 * 1023 * This function calls each interrupt handler registered at the 1024 * bridge. The interrupt handlers are called in registered order. 1025 */ 1026 static int 1027 pccbbintr_function(sc) 1028 struct pccbb_softc *sc; 1029 { 1030 int retval = 0, val; 1031 struct pccbb_intrhand_list *pil; 1032 int s, splchanged; 1033 1034 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1035 /* 1036 * XXX priority change. gross. I use if-else 1037 * sentense instead of switch-case sentense because of 1038 * avoiding duplicate case value error. More than one 1039 * IPL_XXX use same value. It depends on 1040 * implimentation. 1041 */ 1042 splchanged = 1; 1043 if (pil->pil_level == IPL_SERIAL) { 1044 s = splserial(); 1045 } else if (pil->pil_level == IPL_HIGH) { 1046 s = splhigh(); 1047 } else if (pil->pil_level == IPL_CLOCK) { 1048 s = splclock(); 1049 } else if (pil->pil_level == IPL_AUDIO) { 1050 s = splaudio(); 1051 } else if (pil->pil_level == IPL_IMP) { 1052 s = splvm(); /* XXX */ 1053 } else if (pil->pil_level == IPL_TTY) { 1054 s = spltty(); 1055 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1056 s = splsoftserial(); 1057 } else if (pil->pil_level == IPL_NET) { 1058 s = splnet(); 1059 } else { 1060 splchanged = 0; 1061 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1062 } 1063 1064 val = (*pil->pil_func)(pil->pil_arg); 1065 1066 if (splchanged != 0) { 1067 splx(s); 1068 } 1069 1070 retval = retval == 1 ? 1 : 1071 retval == 0 ? val : val != 0 ? val : retval; 1072 } 1073 1074 return retval; 1075 } 1076 1077 static void 1078 pci113x_insert(arg) 1079 void *arg; 1080 { 1081 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1082 u_int32_t sockevent, sockstate; 1083 1084 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1085 CB_SOCKET_EVENT); 1086 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1087 CB_SOCKET_STAT); 1088 1089 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1090 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1091 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1092 sc->sc_flags |= CBB_CARDEXIST; 1093 /* call pccard interrupt handler here */ 1094 if (sockstate & CB_SOCKET_STAT_16BIT) { 1095 /* 16-bit card found */ 1096 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1097 cardslot_event_throw(sc->sc_csc, 1098 CARDSLOT_EVENT_INSERTION_16); 1099 } else if (sockstate & CB_SOCKET_STAT_CB) { 1100 /* cardbus card found */ 1101 /* cardbus_attach_card(sc->sc_csc); */ 1102 cardslot_event_throw(sc->sc_csc, 1103 CARDSLOT_EVENT_INSERTION_CB); 1104 } else { 1105 /* who are you? */ 1106 } 1107 } else { 1108 callout_reset(&sc->sc_insert_ch, hz / 10, 1109 pci113x_insert, sc); 1110 } 1111 } 1112 1113 #define PCCBB_PCMCIA_OFFSET 0x800 1114 static u_int8_t 1115 pccbb_pcmcia_read(ph, reg) 1116 struct pcic_handle *ph; 1117 int reg; 1118 { 1119 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1120 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1121 1122 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1123 PCCBB_PCMCIA_OFFSET + reg); 1124 } 1125 1126 static void 1127 pccbb_pcmcia_write(ph, reg, val) 1128 struct pcic_handle *ph; 1129 int reg; 1130 u_int8_t val; 1131 { 1132 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1133 val); 1134 1135 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1136 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1137 } 1138 1139 /* 1140 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1141 */ 1142 STATIC int 1143 pccbb_ctrl(ct, command) 1144 cardbus_chipset_tag_t ct; 1145 int command; 1146 { 1147 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1148 1149 switch (command) { 1150 case CARDBUS_CD: 1151 if (2 == pccbb_detect_card(sc)) { 1152 int retval = 0; 1153 int status = cb_detect_voltage(sc); 1154 if (PCCARD_VCC_5V & status) { 1155 retval |= CARDBUS_5V_CARD; 1156 } 1157 if (PCCARD_VCC_3V & status) { 1158 retval |= CARDBUS_3V_CARD; 1159 } 1160 if (PCCARD_VCC_XV & status) { 1161 retval |= CARDBUS_XV_CARD; 1162 } 1163 if (PCCARD_VCC_YV & status) { 1164 retval |= CARDBUS_YV_CARD; 1165 } 1166 return retval; 1167 } else { 1168 return 0; 1169 } 1170 break; 1171 case CARDBUS_RESET: 1172 return cb_reset(sc); 1173 break; 1174 case CARDBUS_IO_ENABLE: /* fallthrough */ 1175 case CARDBUS_IO_DISABLE: /* fallthrough */ 1176 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1177 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1178 case CARDBUS_BM_ENABLE: /* fallthrough */ 1179 case CARDBUS_BM_DISABLE: /* fallthrough */ 1180 return pccbb_cardenable(sc, command); 1181 break; 1182 } 1183 1184 return 0; 1185 } 1186 1187 /* 1188 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1189 * This function returns true when it succeeds and returns false when 1190 * it fails. 1191 */ 1192 STATIC int 1193 pccbb_power(ct, command) 1194 cardbus_chipset_tag_t ct; 1195 int command; 1196 { 1197 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1198 1199 u_int32_t status, sock_ctrl; 1200 bus_space_tag_t memt = sc->sc_base_memt; 1201 bus_space_handle_t memh = sc->sc_base_memh; 1202 1203 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1204 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1205 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1206 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1207 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1208 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1209 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1210 "UNKNOWN", 1211 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1212 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1213 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1214 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1215 "UNKNOWN", command)); 1216 1217 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1218 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1219 1220 switch (command & CARDBUS_VCCMASK) { 1221 case CARDBUS_VCC_UC: 1222 break; 1223 case CARDBUS_VCC_5V: 1224 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1225 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1226 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1227 } else { 1228 printf("%s: BAD voltage request: no 5 V card\n", 1229 sc->sc_dev.dv_xname); 1230 } 1231 break; 1232 case CARDBUS_VCC_3V: 1233 if (CB_SOCKET_STAT_3VCARD & status) { 1234 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1235 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1236 } else { 1237 printf("%s: BAD voltage request: no 3.3 V card\n", 1238 sc->sc_dev.dv_xname); 1239 } 1240 break; 1241 case CARDBUS_VCC_0V: 1242 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1243 break; 1244 default: 1245 return 0; /* power NEVER changed */ 1246 break; 1247 } 1248 1249 switch (command & CARDBUS_VPPMASK) { 1250 case CARDBUS_VPP_UC: 1251 break; 1252 case CARDBUS_VPP_0V: 1253 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1254 break; 1255 case CARDBUS_VPP_VCC: 1256 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1257 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1258 break; 1259 case CARDBUS_VPP_12V: 1260 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1261 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1262 break; 1263 } 1264 1265 #if 0 1266 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1267 #endif 1268 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1269 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1270 1271 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1272 printf 1273 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1274 sc->sc_dev.dv_xname, sock_ctrl, status); 1275 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1276 (command & CARDBUS_VCCMASK) == 1277 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1278 CARDBUS_VCCMASK) == 1279 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1280 CARDBUS_VCCMASK) == 1281 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1282 CARDBUS_VCCMASK) == 1283 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1284 CARDBUS_VCCMASK) == 1285 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1286 CARDBUS_VCCMASK) == 1287 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1288 (command & CARDBUS_VPPMASK) == 1289 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1290 CARDBUS_VPPMASK) == 1291 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1292 CARDBUS_VPPMASK) == 1293 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1294 CARDBUS_VPPMASK) == 1295 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1296 #if 0 1297 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1298 u_int32_t force = 1299 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1300 /* Reset Bad Vcc request */ 1301 force &= ~CB_SOCKET_FORCE_BADVCC; 1302 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1303 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1304 CB_SOCKET_STAT)); 1305 return 1; 1306 } 1307 #endif 1308 return 0; 1309 } 1310 1311 /* 1312 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1313 * time is 20 ms, some PC-Card bridge requires longer duration. 1314 */ 1315 #if 0 /* XXX called on interrupt context */ 1316 DELAY_MS(300, sc); 1317 #else 1318 delay(300 * 1000); 1319 #endif 1320 1321 return 1; /* power changed correctly */ 1322 } 1323 1324 #if defined CB_PCMCIA_POLL 1325 struct cb_poll_str { 1326 void *arg; 1327 int (*func) __P((void *)); 1328 int level; 1329 pccard_chipset_tag_t ct; 1330 int count; 1331 struct callout poll_ch; 1332 }; 1333 1334 static struct cb_poll_str cb_poll[10]; 1335 static int cb_poll_n = 0; 1336 1337 static void cb_pcmcia_poll __P((void *arg)); 1338 1339 static void 1340 cb_pcmcia_poll(arg) 1341 void *arg; 1342 { 1343 struct cb_poll_str *poll = arg; 1344 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1345 struct pccbb_softc *sc = psc->cpc_parent; 1346 int s; 1347 u_int32_t spsr; /* socket present-state reg */ 1348 1349 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1350 switch (poll->level) { 1351 case IPL_NET: 1352 s = splnet(); 1353 break; 1354 case IPL_BIO: 1355 s = splbio(); 1356 break; 1357 case IPL_TTY: /* fallthrough */ 1358 default: 1359 s = spltty(); 1360 break; 1361 } 1362 1363 spsr = 1364 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1365 CB_SOCKET_STAT); 1366 1367 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1368 if (!(spsr & 0x40)) { /* CINT low */ 1369 #else 1370 if (1) { 1371 #endif 1372 if ((*poll->func) (poll->arg) == 1) { 1373 ++poll->count; 1374 printf("intr: reported from poller, 0x%x\n", spsr); 1375 #if defined LEVEL2 1376 } else { 1377 printf("intr: miss! 0x%x\n", spsr); 1378 #endif 1379 } 1380 } 1381 splx(s); 1382 } 1383 #endif /* defined CB_PCMCIA_POLL */ 1384 1385 /* 1386 * static int pccbb_detect_card(struct pccbb_softc *sc) 1387 * return value: 0 if no card exists. 1388 * 1 if 16-bit card exists. 1389 * 2 if cardbus card exists. 1390 */ 1391 static int 1392 pccbb_detect_card(sc) 1393 struct pccbb_softc *sc; 1394 { 1395 bus_space_handle_t base_memh = sc->sc_base_memh; 1396 bus_space_tag_t base_memt = sc->sc_base_memt; 1397 u_int32_t sockstat = 1398 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1399 int retval = 0; 1400 1401 /* CD1 and CD2 asserted */ 1402 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1403 /* card must be present */ 1404 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1405 /* NOTACARD DEASSERTED */ 1406 if (CB_SOCKET_STAT_CB & sockstat) { 1407 /* CardBus mode */ 1408 retval = 2; 1409 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1410 /* 16-bit mode */ 1411 retval = 1; 1412 } 1413 } 1414 } 1415 return retval; 1416 } 1417 1418 /* 1419 * STATIC int cb_reset(struct pccbb_softc *sc) 1420 * This function resets CardBus card. 1421 */ 1422 STATIC int 1423 cb_reset(sc) 1424 struct pccbb_softc *sc; 1425 { 1426 /* 1427 * Reset Assert at least 20 ms 1428 * Some machines request longer duration. 1429 */ 1430 int reset_duration = 1431 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1432 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1433 1434 /* Reset bit Assert (bit 6 at 0x3E) */ 1435 bcr |= CB_BCR_RESET_ENABLE; 1436 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1437 DELAY_MS(reset_duration, sc); 1438 1439 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1440 /* Reset bit Deassert (bit 6 at 0x3E) */ 1441 bcr &= ~CB_BCR_RESET_ENABLE; 1442 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1443 DELAY_MS(reset_duration, sc); 1444 } 1445 /* No card found on the slot. Keep Reset. */ 1446 return 1; 1447 } 1448 1449 /* 1450 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1451 * This function detect card Voltage. 1452 */ 1453 STATIC int 1454 cb_detect_voltage(sc) 1455 struct pccbb_softc *sc; 1456 { 1457 u_int32_t psr; /* socket present-state reg */ 1458 bus_space_tag_t iot = sc->sc_base_memt; 1459 bus_space_handle_t ioh = sc->sc_base_memh; 1460 int vol = PCCARD_VCC_UKN; /* set 0 */ 1461 1462 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1463 1464 if (0x400u & psr) { 1465 vol |= PCCARD_VCC_5V; 1466 } 1467 if (0x800u & psr) { 1468 vol |= PCCARD_VCC_3V; 1469 } 1470 1471 return vol; 1472 } 1473 1474 STATIC int 1475 cbbprint(aux, pcic) 1476 void *aux; 1477 const char *pcic; 1478 { 1479 /* 1480 struct cbslot_attach_args *cba = aux; 1481 1482 if (cba->cba_slot >= 0) { 1483 printf(" slot %d", cba->cba_slot); 1484 } 1485 */ 1486 return UNCONF; 1487 } 1488 1489 /* 1490 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1491 * This function enables and disables the card 1492 */ 1493 STATIC int 1494 pccbb_cardenable(sc, function) 1495 struct pccbb_softc *sc; 1496 int function; 1497 { 1498 u_int32_t command = 1499 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1500 1501 DPRINTF(("pccbb_cardenable:")); 1502 switch (function) { 1503 case CARDBUS_IO_ENABLE: 1504 command |= PCI_COMMAND_IO_ENABLE; 1505 break; 1506 case CARDBUS_IO_DISABLE: 1507 command &= ~PCI_COMMAND_IO_ENABLE; 1508 break; 1509 case CARDBUS_MEM_ENABLE: 1510 command |= PCI_COMMAND_MEM_ENABLE; 1511 break; 1512 case CARDBUS_MEM_DISABLE: 1513 command &= ~PCI_COMMAND_MEM_ENABLE; 1514 break; 1515 case CARDBUS_BM_ENABLE: 1516 command |= PCI_COMMAND_MASTER_ENABLE; 1517 break; 1518 case CARDBUS_BM_DISABLE: 1519 command &= ~PCI_COMMAND_MASTER_ENABLE; 1520 break; 1521 default: 1522 return 0; 1523 } 1524 1525 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1526 DPRINTF((" command reg 0x%x\n", command)); 1527 return 1; 1528 } 1529 1530 #if !rbus 1531 /* 1532 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1533 */ 1534 static int 1535 pccbb_io_open(ct, win, start, end) 1536 cardbus_chipset_tag_t ct; 1537 int win; 1538 u_int32_t start, end; 1539 { 1540 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1541 int basereg; 1542 int limitreg; 1543 1544 if ((win < 0) || (win > 2)) { 1545 #if defined DIAGNOSTIC 1546 printf("cardbus_io_open: window out of range %d\n", win); 1547 #endif 1548 return 0; 1549 } 1550 1551 basereg = win * 8 + 0x2c; 1552 limitreg = win * 8 + 0x30; 1553 1554 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1555 start, basereg, end, limitreg)); 1556 1557 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1558 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1559 return 1; 1560 } 1561 1562 /* 1563 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1564 */ 1565 static int 1566 pccbb_io_close(ct, win) 1567 cardbus_chipset_tag_t ct; 1568 int win; 1569 { 1570 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1571 int basereg; 1572 int limitreg; 1573 1574 if ((win < 0) || (win > 2)) { 1575 #if defined DIAGNOSTIC 1576 printf("cardbus_io_close: window out of range %d\n", win); 1577 #endif 1578 return 0; 1579 } 1580 1581 basereg = win * 8 + 0x2c; 1582 limitreg = win * 8 + 0x30; 1583 1584 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1585 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1586 return 1; 1587 } 1588 1589 /* 1590 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1591 */ 1592 static int 1593 pccbb_mem_open(ct, win, start, end) 1594 cardbus_chipset_tag_t ct; 1595 int win; 1596 u_int32_t start, end; 1597 { 1598 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1599 int basereg; 1600 int limitreg; 1601 1602 if ((win < 0) || (win > 2)) { 1603 #if defined DIAGNOSTIC 1604 printf("cardbus_mem_open: window out of range %d\n", win); 1605 #endif 1606 return 0; 1607 } 1608 1609 basereg = win * 8 + 0x1c; 1610 limitreg = win * 8 + 0x20; 1611 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1613 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1614 return 1; 1615 } 1616 1617 /* 1618 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1619 */ 1620 static int 1621 pccbb_mem_close(ct, win) 1622 cardbus_chipset_tag_t ct; 1623 int win; 1624 { 1625 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1626 int basereg; 1627 int limitreg; 1628 1629 if ((win < 0) || (win > 2)) { 1630 #if defined DIAGNOSTIC 1631 printf("cardbus_mem_close: window out of range %d\n", win); 1632 #endif 1633 return 0; 1634 } 1635 1636 basereg = win * 8 + 0x1c; 1637 limitreg = win * 8 + 0x20; 1638 1639 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1640 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1641 return 1; 1642 } 1643 #endif 1644 1645 /* 1646 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1647 * int irq, 1648 * int level, 1649 * int (* func) __P((void *)), 1650 * void *arg) 1651 * 1652 * This function registers an interrupt handler at the bridge, in 1653 * order not to call the interrupt handlers of child devices when 1654 * a card-deletion interrupt occurs. 1655 * 1656 * The arguments irq and level are not used. 1657 */ 1658 static void * 1659 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1660 cardbus_chipset_tag_t ct; 1661 int irq, level; 1662 int (*func) __P((void *)); 1663 void *arg; 1664 { 1665 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1666 1667 return pccbb_intr_establish(sc, irq, level, func, arg); 1668 } 1669 1670 1671 /* 1672 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1673 * void *ih) 1674 * 1675 * This function removes an interrupt handler pointed by ih. 1676 */ 1677 static void 1678 pccbb_cb_intr_disestablish(ct, ih) 1679 cardbus_chipset_tag_t ct; 1680 void *ih; 1681 { 1682 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1683 1684 pccbb_intr_disestablish(sc, ih); 1685 } 1686 1687 1688 void 1689 pccbb_intr_route(sc) 1690 struct pccbb_softc *sc; 1691 { 1692 pcireg_t reg; 1693 1694 /* initialize bridge intr routing */ 1695 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1696 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1697 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1698 1699 switch (sc->sc_chipset) { 1700 case CB_TI113X: 1701 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1702 /* functional intr enabled */ 1703 reg |= PCI113X_CBCTRL_PCI_INTR; 1704 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1705 break; 1706 default: 1707 break; 1708 } 1709 } 1710 1711 /* 1712 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1713 * int irq, 1714 * int level, 1715 * int (* func) __P((void *)), 1716 * void *arg) 1717 * 1718 * This function registers an interrupt handler at the bridge, in 1719 * order not to call the interrupt handlers of child devices when 1720 * a card-deletion interrupt occurs. 1721 * 1722 * The arguments irq is not used because pccbb selects intr vector. 1723 */ 1724 static void * 1725 pccbb_intr_establish(sc, irq, level, func, arg) 1726 struct pccbb_softc *sc; 1727 int irq, level; 1728 int (*func) __P((void *)); 1729 void *arg; 1730 { 1731 struct pccbb_intrhand_list *pil, *newpil; 1732 1733 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1734 1735 if (sc->sc_pil == NULL) { 1736 pccbb_intr_route(sc); 1737 1738 } 1739 1740 /* 1741 * Allocate a room for interrupt handler structure. 1742 */ 1743 if (NULL == (newpil = 1744 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1745 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1746 return NULL; 1747 } 1748 1749 newpil->pil_func = func; 1750 newpil->pil_arg = arg; 1751 newpil->pil_level = level; 1752 newpil->pil_next = NULL; 1753 1754 if (sc->sc_pil == NULL) { 1755 sc->sc_pil = newpil; 1756 } else { 1757 for (pil = sc->sc_pil; pil->pil_next != NULL; 1758 pil = pil->pil_next); 1759 pil->pil_next = newpil; 1760 } 1761 1762 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1763 1764 return newpil; 1765 } 1766 1767 /* 1768 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1769 * void *ih) 1770 * 1771 * This function removes an interrupt handler pointed by ih. 1772 */ 1773 static void 1774 pccbb_intr_disestablish(sc, ih) 1775 struct pccbb_softc *sc; 1776 void *ih; 1777 { 1778 struct pccbb_intrhand_list *pil, **pil_prev; 1779 pcireg_t reg; 1780 1781 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1782 1783 pil_prev = &sc->sc_pil; 1784 1785 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1786 if (pil == ih) { 1787 *pil_prev = pil->pil_next; 1788 free(pil, M_DEVBUF); 1789 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1790 break; 1791 } 1792 pil_prev = &pil->pil_next; 1793 } 1794 1795 if (sc->sc_pil == NULL) { 1796 /* No interrupt handlers */ 1797 1798 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1799 1800 /* stop routing PCI intr */ 1801 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1802 reg |= CB_BCR_INTR_IREQ_ENABLE; 1803 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1804 1805 switch (sc->sc_chipset) { 1806 case CB_TI113X: 1807 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1808 /* functional intr disabled */ 1809 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1810 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1811 break; 1812 default: 1813 break; 1814 } 1815 } 1816 } 1817 1818 #if defined SHOW_REGS 1819 static void 1820 cb_show_regs(pc, tag, memt, memh) 1821 pci_chipset_tag_t pc; 1822 pcitag_t tag; 1823 bus_space_tag_t memt; 1824 bus_space_handle_t memh; 1825 { 1826 int i; 1827 printf("PCI config regs:"); 1828 for (i = 0; i < 0x50; i += 4) { 1829 if (i % 16 == 0) { 1830 printf("\n 0x%02x:", i); 1831 } 1832 printf(" %08x", pci_conf_read(pc, tag, i)); 1833 } 1834 for (i = 0x80; i < 0xb0; i += 4) { 1835 if (i % 16 == 0) { 1836 printf("\n 0x%02x:", i); 1837 } 1838 printf(" %08x", pci_conf_read(pc, tag, i)); 1839 } 1840 1841 if (memh == 0) { 1842 printf("\n"); 1843 return; 1844 } 1845 1846 printf("\nsocket regs:"); 1847 for (i = 0; i <= 0x10; i += 0x04) { 1848 printf(" %08x", bus_space_read_4(memt, memh, i)); 1849 } 1850 printf("\nExCA regs:"); 1851 for (i = 0; i < 0x08; ++i) { 1852 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1853 } 1854 printf("\n"); 1855 return; 1856 } 1857 #endif 1858 1859 /* 1860 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1861 * int busno, int devno, int function) 1862 * This is the function to make a tag to access config space of 1863 * a CardBus Card. It works same as pci_conf_read. 1864 */ 1865 static cardbustag_t 1866 pccbb_make_tag(cc, busno, devno, function) 1867 cardbus_chipset_tag_t cc; 1868 int busno, devno, function; 1869 { 1870 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1871 1872 return pci_make_tag(sc->sc_pc, busno, devno, function); 1873 } 1874 1875 static void 1876 pccbb_free_tag(cc, tag) 1877 cardbus_chipset_tag_t cc; 1878 cardbustag_t tag; 1879 { 1880 } 1881 1882 /* 1883 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1884 * cardbustag_t tag, int offset) 1885 * This is the function to read the config space of a CardBus Card. 1886 * It works same as pci_conf_read. 1887 */ 1888 static cardbusreg_t 1889 pccbb_conf_read(cc, tag, offset) 1890 cardbus_chipset_tag_t cc; 1891 cardbustag_t tag; 1892 int offset; /* register offset */ 1893 { 1894 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1895 1896 return pci_conf_read(sc->sc_pc, tag, offset); 1897 } 1898 1899 /* 1900 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1901 * int offs, cardbusreg_t val) 1902 * This is the function to write the config space of a CardBus Card. 1903 * It works same as pci_conf_write. 1904 */ 1905 static void 1906 pccbb_conf_write(cc, tag, reg, val) 1907 cardbus_chipset_tag_t cc; 1908 cardbustag_t tag; 1909 int reg; /* register offset */ 1910 cardbusreg_t val; 1911 { 1912 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1913 1914 pci_conf_write(sc->sc_pc, tag, reg, val); 1915 } 1916 1917 #if 0 1918 STATIC int 1919 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1920 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1921 int speed, int flags, 1922 bus_space_handle_t * iohp) 1923 #endif 1924 /* 1925 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1926 * bus_addr_t start, bus_size_t size, 1927 * bus_size_t align, 1928 * struct pcmcia_io_handle *pcihp 1929 * 1930 * This function only allocates I/O region for pccard. This function 1931 * never maps the allocated region to pccard I/O area. 1932 * 1933 * XXX: The interface of this function is not very good, I believe. 1934 */ 1935 STATIC int 1936 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1937 pcmcia_chipset_handle_t pch; 1938 bus_addr_t start; /* start address */ 1939 bus_size_t size; 1940 bus_size_t align; 1941 struct pcmcia_io_handle *pcihp; 1942 { 1943 struct pcic_handle *ph = (struct pcic_handle *)pch; 1944 bus_addr_t ioaddr; 1945 int flags = 0; 1946 bus_space_tag_t iot; 1947 bus_space_handle_t ioh; 1948 bus_addr_t mask; 1949 #if rbus 1950 rbus_tag_t rb; 1951 #endif 1952 if (align == 0) { 1953 align = size; /* XXX: funny??? */ 1954 } 1955 1956 if (start != 0) { 1957 /* XXX: assume all card decode lower 10 bits by its hardware */ 1958 mask = 0x3ff; 1959 } else { 1960 /* 1961 * calculate mask: 1962 * 1. get the most significant bit of size (call it msb). 1963 * 2. compare msb with the value of size. 1964 * 3. if size is larger, shift msb left once. 1965 * 4. obtain mask value to decrement msb. 1966 */ 1967 bus_size_t size_tmp = size; 1968 int shifts = 0; 1969 1970 mask = 1; 1971 while (size_tmp) { 1972 ++shifts; 1973 size_tmp >>= 1; 1974 } 1975 mask = (1 << shifts); 1976 if (mask < size) { 1977 mask <<= 1; 1978 } 1979 --mask; 1980 } 1981 1982 /* 1983 * Allocate some arbitrary I/O space. 1984 */ 1985 1986 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1987 1988 #if rbus 1989 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1990 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1991 return 1; 1992 } 1993 #else 1994 if (start) { 1995 ioaddr = start; 1996 if (bus_space_map(iot, start, size, 0, &ioh)) { 1997 return 1; 1998 } 1999 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2000 (u_long) ioaddr, (u_long) size)); 2001 } else { 2002 flags |= PCMCIA_IO_ALLOCATED; 2003 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2004 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2005 size, align, 0, 0, &ioaddr, &ioh)) { 2006 /* No room be able to be get. */ 2007 return 1; 2008 } 2009 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2010 (u_long) ioaddr, (u_long) size)); 2011 } 2012 #endif 2013 2014 pcihp->iot = iot; 2015 pcihp->ioh = ioh; 2016 pcihp->addr = ioaddr; 2017 pcihp->size = size; 2018 pcihp->flags = flags; 2019 2020 return 0; 2021 } 2022 2023 /* 2024 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2025 * struct pcmcia_io_handle *pcihp) 2026 * 2027 * This function only frees I/O region for pccard. 2028 * 2029 * XXX: The interface of this function is not very good, I believe. 2030 */ 2031 void 2032 pccbb_pcmcia_io_free(pch, pcihp) 2033 pcmcia_chipset_handle_t pch; 2034 struct pcmcia_io_handle *pcihp; 2035 { 2036 #if !rbus 2037 bus_space_tag_t iot = pcihp->iot; 2038 #endif 2039 bus_space_handle_t ioh = pcihp->ioh; 2040 bus_size_t size = pcihp->size; 2041 2042 #if rbus 2043 struct pccbb_softc *sc = 2044 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2045 rbus_tag_t rb = sc->sc_rbus_iot; 2046 2047 rbus_space_free(rb, ioh, size, NULL); 2048 #else 2049 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2050 bus_space_free(iot, ioh, size); 2051 else 2052 bus_space_unmap(iot, ioh, size); 2053 #endif 2054 } 2055 2056 /* 2057 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2058 * bus_addr_t offset, bus_size_t size, 2059 * struct pcmcia_io_handle *pcihp, 2060 * int *windowp) 2061 * 2062 * This function maps the allocated I/O region to pccard. This function 2063 * never allocates any I/O region for pccard I/O area. I don't 2064 * understand why the original authors of pcmciabus separated alloc and 2065 * map. I believe the two must be unite. 2066 * 2067 * XXX: no wait timing control? 2068 */ 2069 int 2070 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2071 pcmcia_chipset_handle_t pch; 2072 int width; 2073 bus_addr_t offset; 2074 bus_size_t size; 2075 struct pcmcia_io_handle *pcihp; 2076 int *windowp; 2077 { 2078 struct pcic_handle *ph = (struct pcic_handle *)pch; 2079 bus_addr_t ioaddr = pcihp->addr + offset; 2080 int i, win; 2081 #if defined CBB_DEBUG 2082 static char *width_names[] = { "dynamic", "io8", "io16" }; 2083 #endif 2084 2085 /* Sanity check I/O handle. */ 2086 2087 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2088 panic("pccbb_pcmcia_io_map iot is bogus"); 2089 } 2090 2091 /* XXX Sanity check offset/size. */ 2092 2093 win = -1; 2094 for (i = 0; i < PCIC_IO_WINS; i++) { 2095 if ((ph->ioalloc & (1 << i)) == 0) { 2096 win = i; 2097 ph->ioalloc |= (1 << i); 2098 break; 2099 } 2100 } 2101 2102 if (win == -1) { 2103 return 1; 2104 } 2105 2106 *windowp = win; 2107 2108 /* XXX this is pretty gross */ 2109 2110 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2111 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2112 2113 /* XXX wtf is this doing here? */ 2114 2115 #if 0 2116 printf(" port 0x%lx", (u_long) ioaddr); 2117 if (size > 1) { 2118 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2119 } 2120 #endif 2121 2122 ph->io[win].addr = ioaddr; 2123 ph->io[win].size = size; 2124 ph->io[win].width = width; 2125 2126 /* actual dirty register-value changing in the function below. */ 2127 pccbb_pcmcia_do_io_map(ph, win); 2128 2129 return 0; 2130 } 2131 2132 /* 2133 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2134 * 2135 * This function changes register-value to map I/O region for pccard. 2136 */ 2137 static void 2138 pccbb_pcmcia_do_io_map(ph, win) 2139 struct pcic_handle *ph; 2140 int win; 2141 { 2142 static u_int8_t pcic_iowidth[3] = { 2143 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2144 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2145 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2146 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2147 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2148 }; 2149 2150 #define PCIC_SIA_START_LOW 0 2151 #define PCIC_SIA_START_HIGH 1 2152 #define PCIC_SIA_STOP_LOW 2 2153 #define PCIC_SIA_STOP_HIGH 3 2154 2155 int regbase_win = 0x8 + win * 0x04; 2156 u_int8_t ioctl, enable; 2157 2158 DPRINTF( 2159 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2160 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2161 ph->io[win].width * 8)); 2162 2163 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2164 ph->io[win].addr & 0xff); 2165 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2166 (ph->io[win].addr >> 8) & 0xff); 2167 2168 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2169 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2170 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2171 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2172 2173 ioctl = Pcic_read(ph, PCIC_IOCTL); 2174 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2175 switch (win) { 2176 case 0: 2177 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2178 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2179 PCIC_IOCTL_IO0_DATASIZE_MASK); 2180 ioctl |= pcic_iowidth[ph->io[win].width]; 2181 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2182 break; 2183 case 1: 2184 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2185 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2186 PCIC_IOCTL_IO1_DATASIZE_MASK); 2187 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2188 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2189 break; 2190 } 2191 Pcic_write(ph, PCIC_IOCTL, ioctl); 2192 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2193 #if defined CBB_DEBUG 2194 { 2195 u_int8_t start_low = 2196 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2197 u_int8_t start_high = 2198 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2199 u_int8_t stop_low = 2200 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2201 u_int8_t stop_high = 2202 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2203 printf 2204 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2205 start_low, start_high, stop_low, stop_high, ioctl, enable); 2206 } 2207 #endif 2208 } 2209 2210 /* 2211 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2212 * 2213 * This function unmaps I/O region. No return value. 2214 */ 2215 STATIC void 2216 pccbb_pcmcia_io_unmap(pch, win) 2217 pcmcia_chipset_handle_t pch; 2218 int win; 2219 { 2220 struct pcic_handle *ph = (struct pcic_handle *)pch; 2221 int reg; 2222 2223 if (win >= PCIC_IO_WINS || win < 0) { 2224 panic("pccbb_pcmcia_io_unmap: window out of range"); 2225 } 2226 2227 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2228 switch (win) { 2229 case 0: 2230 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2231 break; 2232 case 1: 2233 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2234 break; 2235 } 2236 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2237 2238 ph->ioalloc &= ~(1 << win); 2239 } 2240 2241 /* 2242 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2243 * 2244 * This function enables the card. All information is stored in 2245 * the first argument, pcmcia_chipset_handle_t. 2246 */ 2247 static void 2248 pccbb_pcmcia_wait_ready(ph) 2249 struct pcic_handle *ph; 2250 { 2251 int i; 2252 2253 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2254 Pcic_read(ph, PCIC_IF_STATUS))); 2255 2256 for (i = 0; i < 2000; i++) { 2257 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2258 return; 2259 } 2260 DELAY_MS(2, ph->ph_parent); 2261 #ifdef CBB_DEBUG 2262 if ((i > 1000) && (i % 25 == 24)) 2263 printf("."); 2264 #endif 2265 } 2266 2267 #ifdef DIAGNOSTIC 2268 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2269 Pcic_read(ph, PCIC_IF_STATUS)); 2270 #endif 2271 } 2272 2273 /* 2274 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2275 * 2276 * This function enables the card. All information is stored in 2277 * the first argument, pcmcia_chipset_handle_t. 2278 */ 2279 STATIC void 2280 pccbb_pcmcia_socket_enable(pch) 2281 pcmcia_chipset_handle_t pch; 2282 { 2283 struct pcic_handle *ph = (struct pcic_handle *)pch; 2284 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2285 int cardtype, win; 2286 u_int8_t power, intr; 2287 pcireg_t spsr; 2288 int voltage; 2289 2290 /* this bit is mostly stolen from pcic_attach_card */ 2291 2292 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2293 2294 /* get card Vcc info */ 2295 2296 spsr = 2297 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2298 CB_SOCKET_STAT); 2299 if (spsr & CB_SOCKET_STAT_5VCARD) { 2300 DPRINTF(("5V card\n")); 2301 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2302 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2303 DPRINTF(("3V card\n")); 2304 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2305 } else { 2306 printf("?V card, 0x%x\n", spsr); /* XXX */ 2307 return; 2308 } 2309 2310 /* disable socket: negate output enable bit and power off */ 2311 2312 power = 0; 2313 Pcic_write(ph, PCIC_PWRCTL, power); 2314 2315 /* power down the socket to reset it, clear the card reset pin */ 2316 2317 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2318 2319 /* 2320 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2321 * we are changing Vcc (Toff). 2322 */ 2323 /* delay(300*1000); too much */ 2324 2325 /* assert reset bit */ 2326 intr = Pcic_read(ph, PCIC_INTR); 2327 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2328 Pcic_write(ph, PCIC_INTR, intr); 2329 2330 /* power up the socket and output enable */ 2331 power = Pcic_read(ph, PCIC_PWRCTL); 2332 power |= PCIC_PWRCTL_OE; 2333 Pcic_write(ph, PCIC_PWRCTL, power); 2334 pccbb_power(sc, voltage); 2335 2336 /* 2337 * hold RESET at least 20 ms: the spec says only 10 us is 2338 * enough, but TI1130 requires at least 20 ms. 2339 */ 2340 #if 0 /* XXX called on interrupt context */ 2341 DELAY_MS(20, sc); 2342 #else 2343 delay(20 * 1000); 2344 #endif 2345 2346 /* clear the reset flag */ 2347 2348 intr |= PCIC_INTR_RESET; 2349 Pcic_write(ph, PCIC_INTR, intr); 2350 2351 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2352 2353 #if 0 /* XXX called on interrupt context */ 2354 DELAY_MS(20, sc); 2355 #else 2356 delay(20 * 1000); 2357 #endif 2358 2359 /* wait for the chip to finish initializing */ 2360 2361 pccbb_pcmcia_wait_ready(ph); 2362 2363 /* zero out the address windows */ 2364 2365 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2366 2367 /* set the card type */ 2368 2369 cardtype = pcmcia_card_gettype(ph->pcmcia); 2370 2371 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2372 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2373 Pcic_write(ph, PCIC_INTR, intr); 2374 2375 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2376 ph->ph_parent->dv_xname, ph->sock, 2377 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2378 2379 /* reinstall all the memory and io mappings */ 2380 2381 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2382 if (ph->memalloc & (1 << win)) { 2383 pccbb_pcmcia_do_mem_map(ph, win); 2384 } 2385 } 2386 2387 for (win = 0; win < PCIC_IO_WINS; ++win) { 2388 if (ph->ioalloc & (1 << win)) { 2389 pccbb_pcmcia_do_io_map(ph, win); 2390 } 2391 } 2392 } 2393 2394 /* 2395 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2396 * 2397 * This function disables the card. All information is stored in 2398 * the first argument, pcmcia_chipset_handle_t. 2399 */ 2400 STATIC void 2401 pccbb_pcmcia_socket_disable(pch) 2402 pcmcia_chipset_handle_t pch; 2403 { 2404 struct pcic_handle *ph = (struct pcic_handle *)pch; 2405 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2406 u_int8_t power, intr; 2407 2408 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2409 2410 /* reset signal asserting... */ 2411 2412 intr = Pcic_read(ph, PCIC_INTR); 2413 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2414 Pcic_write(ph, PCIC_INTR, intr); 2415 delay(2 * 1000); 2416 2417 /* power down the socket */ 2418 power = Pcic_read(ph, PCIC_PWRCTL); 2419 power &= ~PCIC_PWRCTL_OE; 2420 Pcic_write(ph, PCIC_PWRCTL, power); 2421 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2422 /* 2423 * wait 300ms until power fails (Tpf). 2424 */ 2425 #if 0 /* XXX called on interrupt context */ 2426 DELAY_MS(300, sc); 2427 #else 2428 delay(300 * 1000); 2429 #endif 2430 } 2431 2432 /* 2433 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2434 * 2435 * This function detects whether a card is in the slot or not. 2436 * If a card is inserted, return 1. Otherwise, return 0. 2437 */ 2438 STATIC int 2439 pccbb_pcmcia_card_detect(pch) 2440 pcmcia_chipset_handle_t pch; 2441 { 2442 struct pcic_handle *ph = (struct pcic_handle *)pch; 2443 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2444 2445 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2446 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2447 } 2448 2449 #if 0 2450 STATIC int 2451 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2452 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2453 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2454 #endif 2455 /* 2456 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2457 * bus_size_t size, 2458 * struct pcmcia_mem_handle *pcmhp) 2459 * 2460 * This function only allocates memory region for pccard. This 2461 * function never maps the allocated region to pccard memory area. 2462 * 2463 * XXX: Why the argument of start address is not in? 2464 */ 2465 STATIC int 2466 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2467 pcmcia_chipset_handle_t pch; 2468 bus_size_t size; 2469 struct pcmcia_mem_handle *pcmhp; 2470 { 2471 struct pcic_handle *ph = (struct pcic_handle *)pch; 2472 bus_space_handle_t memh; 2473 bus_addr_t addr; 2474 bus_size_t sizepg; 2475 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2476 #if rbus 2477 rbus_tag_t rb; 2478 #endif 2479 2480 /* out of sc->memh, allocate as many pages as necessary */ 2481 2482 /* convert size to PCIC pages */ 2483 /* 2484 * This is not enough; when the requested region is on the page 2485 * boundaries, this may calculate wrong result. 2486 */ 2487 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2488 #if 0 2489 if (sizepg > PCIC_MAX_MEM_PAGES) { 2490 return 1; 2491 } 2492 #endif 2493 2494 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2495 return 1; 2496 } 2497 2498 addr = 0; /* XXX gcc -Wuninitialized */ 2499 2500 #if rbus 2501 rb = sc->sc_rbus_memt; 2502 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2503 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2504 &addr, &memh)) { 2505 return 1; 2506 } 2507 #else 2508 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2509 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2510 0, /* boundary */ 2511 0, /* flags */ 2512 &addr, &memh)) { 2513 return 1; 2514 } 2515 #endif 2516 2517 DPRINTF( 2518 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2519 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2520 2521 pcmhp->memt = sc->sc_memt; 2522 pcmhp->memh = memh; 2523 pcmhp->addr = addr; 2524 pcmhp->size = size; 2525 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2526 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2527 pcmhp->mhandle = 0; 2528 /* No offset??? Funny. */ 2529 2530 return 0; 2531 } 2532 2533 /* 2534 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2535 * struct pcmcia_mem_handle *pcmhp) 2536 * 2537 * This function release the memory space allocated by the function 2538 * pccbb_pcmcia_mem_alloc(). 2539 */ 2540 STATIC void 2541 pccbb_pcmcia_mem_free(pch, pcmhp) 2542 pcmcia_chipset_handle_t pch; 2543 struct pcmcia_mem_handle *pcmhp; 2544 { 2545 #if rbus 2546 struct pcic_handle *ph = (struct pcic_handle *)pch; 2547 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2548 2549 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2550 #else 2551 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2552 #endif 2553 } 2554 2555 /* 2556 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2557 * 2558 * This function release the memory space allocated by the function 2559 * pccbb_pcmcia_mem_alloc(). 2560 */ 2561 STATIC void 2562 pccbb_pcmcia_do_mem_map(ph, win) 2563 struct pcic_handle *ph; 2564 int win; 2565 { 2566 int regbase_win; 2567 bus_addr_t phys_addr; 2568 bus_addr_t phys_end; 2569 2570 #define PCIC_SMM_START_LOW 0 2571 #define PCIC_SMM_START_HIGH 1 2572 #define PCIC_SMM_STOP_LOW 2 2573 #define PCIC_SMM_STOP_HIGH 3 2574 #define PCIC_CMA_LOW 4 2575 #define PCIC_CMA_HIGH 5 2576 2577 u_int8_t start_low, start_high = 0; 2578 u_int8_t stop_low, stop_high; 2579 u_int8_t off_low, off_high; 2580 u_int8_t mem_window; 2581 int reg; 2582 2583 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2584 int mem8 = 2585 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2586 || (kind == PCMCIA_MEM_ATTR); 2587 2588 regbase_win = 0x10 + win * 0x08; 2589 2590 phys_addr = ph->mem[win].addr; 2591 phys_end = phys_addr + ph->mem[win].size; 2592 2593 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2594 phys_addr, phys_end, ph->mem[win].offset)); 2595 2596 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2597 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2598 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2599 2600 /* bit 19:12 */ 2601 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2602 /* bit 23:20 and bit 7 on */ 2603 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2604 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2605 /* bit 31:24, for 32-bit address */ 2606 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2607 2608 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2609 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2610 2611 if (((struct pccbb_softc *)ph-> 2612 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2613 Pcic_write(ph, 0x40 + win, mem_window); 2614 } 2615 2616 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2617 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2618 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2619 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2620 2621 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2622 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2623 2624 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2625 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2626 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2627 | ((kind == PCMCIA_MEM_ATTR) ? 2628 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2629 2630 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2631 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2632 2633 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2634 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2635 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2636 2637 #if defined CBB_DEBUG 2638 { 2639 int r1, r2, r3, r4, r5, r6, r7 = 0; 2640 2641 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2642 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2643 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2644 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2645 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2646 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2647 if (((struct pccbb_softc *)(ph-> 2648 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2649 r7 = Pcic_read(ph, 0x40 + win); 2650 } 2651 2652 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2653 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2654 if (((struct pccbb_softc *)(ph-> 2655 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2656 DPRINTF((" %02x", r7)); 2657 } 2658 DPRINTF(("\n")); 2659 } 2660 #endif 2661 } 2662 2663 /* 2664 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2665 * bus_addr_t card_addr, bus_size_t size, 2666 * struct pcmcia_mem_handle *pcmhp, 2667 * bus_addr_t *offsetp, int *windowp) 2668 * 2669 * This function maps memory space allocated by the function 2670 * pccbb_pcmcia_mem_alloc(). 2671 */ 2672 STATIC int 2673 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2674 pcmcia_chipset_handle_t pch; 2675 int kind; 2676 bus_addr_t card_addr; 2677 bus_size_t size; 2678 struct pcmcia_mem_handle *pcmhp; 2679 bus_addr_t *offsetp; 2680 int *windowp; 2681 { 2682 struct pcic_handle *ph = (struct pcic_handle *)pch; 2683 bus_addr_t busaddr; 2684 long card_offset; 2685 int win; 2686 2687 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2688 if ((ph->memalloc & (1 << win)) == 0) { 2689 ph->memalloc |= (1 << win); 2690 break; 2691 } 2692 } 2693 2694 if (win == PCIC_MEM_WINS) { 2695 return 1; 2696 } 2697 2698 *windowp = win; 2699 2700 /* XXX this is pretty gross */ 2701 2702 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2703 panic("pccbb_pcmcia_mem_map memt is bogus"); 2704 } 2705 2706 busaddr = pcmhp->addr; 2707 2708 /* 2709 * compute the address offset to the pcmcia address space for the 2710 * pcic. this is intentionally signed. The masks and shifts below 2711 * will cause TRT to happen in the pcic registers. Deal with making 2712 * sure the address is aligned, and return the alignment offset. 2713 */ 2714 2715 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2716 card_addr -= *offsetp; 2717 2718 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2719 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2720 (u_long) card_addr)); 2721 2722 /* 2723 * include the offset in the size, and decrement size by one, since 2724 * the hw wants start/stop 2725 */ 2726 size += *offsetp - 1; 2727 2728 card_offset = (((long)card_addr) - ((long)busaddr)); 2729 2730 ph->mem[win].addr = busaddr; 2731 ph->mem[win].size = size; 2732 ph->mem[win].offset = card_offset; 2733 ph->mem[win].kind = kind; 2734 2735 pccbb_pcmcia_do_mem_map(ph, win); 2736 2737 return 0; 2738 } 2739 2740 /* 2741 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2742 * int window) 2743 * 2744 * This function unmaps memory space which mapped by the function 2745 * pccbb_pcmcia_mem_map(). 2746 */ 2747 STATIC void 2748 pccbb_pcmcia_mem_unmap(pch, window) 2749 pcmcia_chipset_handle_t pch; 2750 int window; 2751 { 2752 struct pcic_handle *ph = (struct pcic_handle *)pch; 2753 int reg; 2754 2755 if (window >= PCIC_MEM_WINS) { 2756 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2757 } 2758 2759 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2760 reg &= ~(1 << window); 2761 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2762 2763 ph->memalloc &= ~(1 << window); 2764 } 2765 2766 #if defined PCCBB_PCMCIA_POLL 2767 struct pccbb_poll_str { 2768 void *arg; 2769 int (*func) __P((void *)); 2770 int level; 2771 struct pcic_handle *ph; 2772 int count; 2773 int num; 2774 struct callout poll_ch; 2775 }; 2776 2777 static struct pccbb_poll_str pccbb_poll[10]; 2778 static int pccbb_poll_n = 0; 2779 2780 static void pccbb_pcmcia_poll __P((void *arg)); 2781 2782 static void 2783 pccbb_pcmcia_poll(arg) 2784 void *arg; 2785 { 2786 struct pccbb_poll_str *poll = arg; 2787 struct pcic_handle *ph = poll->ph; 2788 struct pccbb_softc *sc = ph->sc; 2789 int s; 2790 u_int32_t spsr; /* socket present-state reg */ 2791 2792 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2793 switch (poll->level) { 2794 case IPL_NET: 2795 s = splnet(); 2796 break; 2797 case IPL_BIO: 2798 s = splbio(); 2799 break; 2800 case IPL_TTY: /* fallthrough */ 2801 default: 2802 s = spltty(); 2803 break; 2804 } 2805 2806 spsr = 2807 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2808 CB_SOCKET_STAT); 2809 2810 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2811 if (!(spsr & 0x40)) /* CINT low */ 2812 #else 2813 if (1) 2814 #endif 2815 { 2816 if ((*poll->func) (poll->arg) > 0) { 2817 ++poll->count; 2818 // printf("intr: reported from poller, 0x%x\n", spsr); 2819 #if defined LEVEL2 2820 } else { 2821 printf("intr: miss! 0x%x\n", spsr); 2822 #endif 2823 } 2824 } 2825 splx(s); 2826 } 2827 #endif /* defined CB_PCMCIA_POLL */ 2828 2829 /* 2830 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2831 * struct pcmcia_function *pf, 2832 * int ipl, 2833 * int (*func)(void *), 2834 * void *arg); 2835 * 2836 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2837 */ 2838 STATIC void * 2839 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2840 pcmcia_chipset_handle_t pch; 2841 struct pcmcia_function *pf; 2842 int ipl; 2843 int (*func) __P((void *)); 2844 void *arg; 2845 { 2846 struct pcic_handle *ph = (struct pcic_handle *)pch; 2847 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2848 2849 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2850 /* what should I do? */ 2851 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2852 DPRINTF( 2853 ("%s does not provide edge nor pulse interrupt\n", 2854 sc->sc_dev.dv_xname)); 2855 return NULL; 2856 } 2857 /* 2858 * XXX Noooooo! The interrupt flag must set properly!! 2859 * dumb pcmcia driver!! 2860 */ 2861 } 2862 2863 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2864 } 2865 2866 /* 2867 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2868 * void *ih) 2869 * 2870 * This function disables PC-Card interrupt. 2871 */ 2872 STATIC void 2873 pccbb_pcmcia_intr_disestablish(pch, ih) 2874 pcmcia_chipset_handle_t pch; 2875 void *ih; 2876 { 2877 struct pcic_handle *ph = (struct pcic_handle *)pch; 2878 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2879 2880 pccbb_intr_disestablish(sc, ih); 2881 } 2882 2883 #if rbus 2884 /* 2885 * static int 2886 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2887 * bus_addr_t addr, bus_size_t size, 2888 * bus_addr_t mask, bus_size_t align, 2889 * int flags, bus_addr_t *addrp; 2890 * bus_space_handle_t *bshp) 2891 * 2892 * This function allocates a portion of memory or io space for 2893 * clients. This function is called from CardBus card drivers. 2894 */ 2895 static int 2896 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2897 cardbus_chipset_tag_t ct; 2898 rbus_tag_t rb; 2899 bus_addr_t addr; 2900 bus_size_t size; 2901 bus_addr_t mask; 2902 bus_size_t align; 2903 int flags; 2904 bus_addr_t *addrp; 2905 bus_space_handle_t *bshp; 2906 { 2907 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2908 2909 DPRINTF( 2910 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2911 addr, size, mask, align)); 2912 2913 if (align == 0) { 2914 align = size; 2915 } 2916 2917 if (rb->rb_bt == sc->sc_memt) { 2918 if (align < 16) { 2919 return 1; 2920 } 2921 } else if (rb->rb_bt == sc->sc_iot) { 2922 if (align < 4) { 2923 return 1; 2924 } 2925 /* XXX: hack for avoiding ISA image */ 2926 if (mask < 0x0100) { 2927 mask = 0x3ff; 2928 addr = 0x300; 2929 } 2930 2931 } else { 2932 DPRINTF( 2933 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 2934 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 2935 return 1; 2936 /* XXX: panic here? */ 2937 } 2938 2939 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2940 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2941 return 1; 2942 } 2943 2944 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2945 2946 return 0; 2947 } 2948 2949 /* 2950 * static int 2951 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2952 * bus_space_handle_t *bshp, bus_size_t size); 2953 * 2954 * This function is called from CardBus card drivers. 2955 */ 2956 static int 2957 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2958 cardbus_chipset_tag_t ct; 2959 rbus_tag_t rb; 2960 bus_space_handle_t bsh; 2961 bus_size_t size; 2962 { 2963 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2964 bus_space_tag_t bt = rb->rb_bt; 2965 2966 pccbb_close_win(sc, bt, bsh, size); 2967 2968 if (bt == sc->sc_memt) { 2969 } else if (bt == sc->sc_iot) { 2970 } else { 2971 return 1; 2972 /* XXX: panic here? */ 2973 } 2974 2975 return rbus_space_free(rb, bsh, size, NULL); 2976 } 2977 #endif /* rbus */ 2978 2979 #if rbus 2980 2981 static int 2982 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2983 struct pccbb_softc *sc; 2984 bus_space_tag_t bst; 2985 bus_addr_t addr; 2986 bus_size_t size; 2987 bus_space_handle_t bsh; 2988 int flags; 2989 { 2990 struct pccbb_win_chain_head *head; 2991 bus_addr_t align; 2992 2993 head = &sc->sc_iowindow; 2994 align = 0x04; 2995 if (sc->sc_memt == bst) { 2996 head = &sc->sc_memwindow; 2997 align = 0x1000; 2998 DPRINTF(("using memory window, %x %x %x\n\n", 2999 sc->sc_iot, sc->sc_memt, bst)); 3000 } 3001 3002 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3003 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3004 sc->sc_dev.dv_xname, 3005 (head == &sc->sc_memwindow) ? "mem" : "io"); 3006 } 3007 pccbb_winset(align, sc, bst); 3008 3009 return 0; 3010 } 3011 3012 static int 3013 pccbb_close_win(sc, bst, bsh, size) 3014 struct pccbb_softc *sc; 3015 bus_space_tag_t bst; 3016 bus_space_handle_t bsh; 3017 bus_size_t size; 3018 { 3019 struct pccbb_win_chain_head *head; 3020 bus_addr_t align; 3021 3022 head = &sc->sc_iowindow; 3023 align = 0x04; 3024 if (sc->sc_memt == bst) { 3025 head = &sc->sc_memwindow; 3026 align = 0x1000; 3027 } 3028 3029 if (pccbb_winlist_delete(head, bsh, size)) { 3030 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3031 sc->sc_dev.dv_xname, 3032 (head == &sc->sc_memwindow) ? "mem" : "io"); 3033 } 3034 pccbb_winset(align, sc, bst); 3035 3036 return 0; 3037 } 3038 3039 static int 3040 pccbb_winlist_insert(head, start, size, bsh, flags) 3041 struct pccbb_win_chain_head *head; 3042 bus_addr_t start; 3043 bus_size_t size; 3044 bus_space_handle_t bsh; 3045 int flags; 3046 { 3047 struct pccbb_win_chain *chainp, *elem; 3048 3049 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3050 M_NOWAIT)) == NULL) 3051 return (1); /* fail */ 3052 3053 elem->wc_start = start; 3054 elem->wc_end = start + (size - 1); 3055 elem->wc_handle = bsh; 3056 elem->wc_flags = flags; 3057 3058 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3059 chainp = TAILQ_NEXT(chainp, wc_list)) { 3060 if (chainp->wc_end < start) 3061 continue; 3062 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3063 return (0); 3064 } 3065 3066 TAILQ_INSERT_TAIL(head, elem, wc_list); 3067 return (0); 3068 } 3069 3070 static int 3071 pccbb_winlist_delete(head, bsh, size) 3072 struct pccbb_win_chain_head *head; 3073 bus_space_handle_t bsh; 3074 bus_size_t size; 3075 { 3076 struct pccbb_win_chain *chainp; 3077 3078 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3079 chainp = TAILQ_NEXT(chainp, wc_list)) { 3080 if (chainp->wc_handle != bsh) 3081 continue; 3082 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3083 printf("pccbb_winlist_delete: window 0x%lx size " 3084 "inconsistent: 0x%lx, 0x%lx\n", 3085 (unsigned long)chainp->wc_start, 3086 (unsigned long)(chainp->wc_end - chainp->wc_start), 3087 (unsigned long)(size - 1)); 3088 return 1; 3089 } 3090 3091 TAILQ_REMOVE(head, chainp, wc_list); 3092 free(chainp, M_DEVBUF); 3093 3094 return 0; 3095 } 3096 3097 return 1; /* fail: no candidate to remove */ 3098 } 3099 3100 static void 3101 pccbb_winset(align, sc, bst) 3102 bus_addr_t align; 3103 struct pccbb_softc *sc; 3104 bus_space_tag_t bst; 3105 { 3106 pci_chipset_tag_t pc; 3107 pcitag_t tag; 3108 bus_addr_t mask = ~(align - 1); 3109 struct { 3110 cardbusreg_t win_start; 3111 cardbusreg_t win_limit; 3112 int win_flags; 3113 } win[2]; 3114 struct pccbb_win_chain *chainp; 3115 int offs; 3116 3117 win[0].win_start = win[1].win_start = 0xffffffff; 3118 win[0].win_limit = win[1].win_limit = 0; 3119 win[0].win_flags = win[1].win_flags = 0; 3120 3121 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3122 offs = 0x2c; 3123 if (sc->sc_memt == bst) { 3124 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3125 offs = 0x1c; 3126 } 3127 3128 if (chainp != NULL) { 3129 win[0].win_start = chainp->wc_start & mask; 3130 win[0].win_limit = chainp->wc_end & mask; 3131 win[0].win_flags = chainp->wc_flags; 3132 chainp = TAILQ_NEXT(chainp, wc_list); 3133 } 3134 3135 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3136 if (win[1].win_start == 0xffffffff) { 3137 /* window 1 is not used */ 3138 if ((win[0].win_flags == chainp->wc_flags) && 3139 (win[0].win_limit + align >= 3140 (chainp->wc_start & mask))) { 3141 /* concatenate */ 3142 win[0].win_limit = chainp->wc_end & mask; 3143 } else { 3144 /* make new window */ 3145 win[1].win_start = chainp->wc_start & mask; 3146 win[1].win_limit = chainp->wc_end & mask; 3147 win[1].win_flags = chainp->wc_flags; 3148 } 3149 continue; 3150 } 3151 3152 /* Both windows are engaged. */ 3153 if (win[0].win_flags == win[1].win_flags) { 3154 /* same flags */ 3155 if (win[0].win_flags == chainp->wc_flags) { 3156 if (win[1].win_start - (win[0].win_limit + 3157 align) < 3158 (chainp->wc_start & mask) - 3159 ((chainp->wc_end & mask) + align)) { 3160 /* 3161 * merge window 0 and 1, and set win1 3162 * to chainp 3163 */ 3164 win[0].win_limit = win[1].win_limit; 3165 win[1].win_start = 3166 chainp->wc_start & mask; 3167 win[1].win_limit = 3168 chainp->wc_end & mask; 3169 } else { 3170 win[1].win_limit = 3171 chainp->wc_end & mask; 3172 } 3173 } else { 3174 /* different flags */ 3175 3176 /* concatenate win0 and win1 */ 3177 win[0].win_limit = win[1].win_limit; 3178 /* allocate win[1] to new space */ 3179 win[1].win_start = chainp->wc_start & mask; 3180 win[1].win_limit = chainp->wc_end & mask; 3181 win[1].win_flags = chainp->wc_flags; 3182 } 3183 } else { 3184 /* the flags of win[0] and win[1] is different */ 3185 if (win[0].win_flags == chainp->wc_flags) { 3186 win[0].win_limit = chainp->wc_end & mask; 3187 /* 3188 * XXX this creates overlapping windows, so 3189 * what should the poor bridge do if one is 3190 * cachable, and the other is not? 3191 */ 3192 printf("%s: overlapping windows\n", 3193 sc->sc_dev.dv_xname); 3194 } else { 3195 win[1].win_limit = chainp->wc_end & mask; 3196 } 3197 } 3198 } 3199 3200 pc = sc->sc_pc; 3201 tag = sc->sc_tag; 3202 pci_conf_write(pc, tag, offs, win[0].win_start); 3203 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3204 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3205 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3206 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3207 pci_conf_read(pc, tag, offs), 3208 pci_conf_read(pc, tag, offs + 4) + align, 3209 pci_conf_read(pc, tag, offs + 8), 3210 pci_conf_read(pc, tag, offs + 12) + align)); 3211 3212 if (bst == sc->sc_memt) { 3213 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3214 3215 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3216 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3217 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3218 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3219 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3220 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3221 } 3222 } 3223 3224 #endif /* rbus */ 3225 3226 static void 3227 pccbb_powerhook(why, arg) 3228 int why; 3229 void *arg; 3230 { 3231 struct pccbb_softc *sc = arg; 3232 u_int32_t reg; 3233 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3234 bus_space_handle_t base_memh = sc->sc_base_memh; 3235 3236 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3237 3238 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3239 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3240 if (sc->sc_pil_intr_enable) { 3241 (void)pccbbintr_function(sc); 3242 } 3243 sc->sc_pil_intr_enable = 0; 3244 3245 /* ToDo: deactivate or suspend child devices */ 3246 3247 } 3248 3249 if (why == PWR_RESUME) { 3250 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3251 /* BIOS did not recover this register */ 3252 pci_conf_write (sc->sc_pc, sc->sc_tag, 3253 PCI_SOCKBASE, sc->sc_sockbase); 3254 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3255 /* BIOS did not recover this register */ 3256 pci_conf_write (sc->sc_pc, sc->sc_tag, 3257 PCI_BUSNUM, sc->sc_busnum); 3258 /* CSC Interrupt: Card detect interrupt on */ 3259 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3260 /* Card detect intr is turned on. */ 3261 reg |= CB_SOCKET_MASK_CD; 3262 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3263 /* reset interrupt */ 3264 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3265 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3266 3267 /* 3268 * check for card insertion or removal during suspend period. 3269 * XXX: the code can't cope with card swap (remove then 3270 * insert). how can we detect such situation? 3271 */ 3272 (void)pccbbintr(sc); 3273 3274 sc->sc_pil_intr_enable = 1; 3275 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3276 3277 /* ToDo: activate or wakeup child devices */ 3278 } 3279 } 3280
Indexes created Fri Sep 26 08:10:20 GMT 2025