pccbb.c revision 1.67
1 /* $NetBSD: pccbb.c,v 1.67 2001/08/30 09:20:17 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/reboot.h> /* for bootverbose */ 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 #include <sys/proc.h> 57 58 #include <machine/intr.h> 59 #include <machine/bus.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/pccbbreg.h> 66 67 #include <dev/cardbus/cardslotvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 71 #include <dev/pcmcia/pcmciareg.h> 72 #include <dev/pcmcia/pcmciavar.h> 73 74 #include <dev/ic/i82365reg.h> 75 #include <dev/ic/i82365var.h> 76 #include <dev/pci/pccbbvar.h> 77 78 #include "locators.h" 79 80 #ifndef __NetBSD_Version__ 81 struct cfdriver cbb_cd = { 82 NULL, "cbb", DV_DULL 83 }; 84 #endif 85 86 #if defined CBB_DEBUG 87 #define DPRINTF(x) printf x 88 #define STATIC 89 #else 90 #define DPRINTF(x) 91 #define STATIC static 92 #endif 93 94 /* 95 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 96 * if you want to wait more than 1 ms. 97 */ 98 #define DELAY_MS(time, param) \ 99 do { \ 100 if (cold == 0) { \ 101 int tick = (hz*(time))/1000; \ 102 \ 103 if (tick <= 1) { \ 104 tick = 2; \ 105 } \ 106 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 107 } else { \ 108 delay((time)*1000); \ 109 } \ 110 } while (0) 111 112 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 113 void pccbbattach __P((struct device *, struct device *, void *)); 114 int pccbbintr __P((void *)); 115 static void pci113x_insert __P((void *)); 116 static int pccbbintr_function __P((struct pccbb_softc *)); 117 118 static int pccbb_detect_card __P((struct pccbb_softc *)); 119 120 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 121 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset __P((struct pccbb_softc *)); 126 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 127 STATIC int cbbprint __P((void *, const char *)); 128 129 static int cb_chipset __P((u_int32_t, int *)); 130 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 131 struct pcmciabus_attach_args *)); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 134 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 135 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 136 #endif 137 138 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 139 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 140 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 141 #if !rbus 142 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 143 u_int32_t)); 144 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 145 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 146 u_int32_t)); 147 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc)); 151 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 152 153 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc)); 155 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 156 157 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 158 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 159 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 160 int)); 161 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 162 cardbusreg_t)); 163 static void pccbb_chipinit __P((struct pccbb_softc *)); 164 165 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 166 struct pcmcia_mem_handle *)); 167 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 168 struct pcmcia_mem_handle *)); 169 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 171 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 172 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 173 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 174 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *)); 176 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *)); 178 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 179 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 180 struct pcmcia_function *, int, int (*)(void *), void *)); 181 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 182 void *)); 183 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 184 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 185 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 186 187 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 188 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 189 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 190 static void pccbb_powerhook __P((int, void *)); 191 192 /* bus-space allocation and deallocation functions */ 193 #if rbus 194 195 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 196 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 197 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 198 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 199 bus_space_handle_t, bus_size_t)); 200 201 #endif /* rbus */ 202 203 #if rbus 204 205 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 206 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 207 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_space_handle_t, bus_size_t)); 209 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 210 bus_size_t, bus_space_handle_t, int)); 211 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 212 bus_space_handle_t, bus_size_t)); 213 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 214 bus_space_tag_t)); 215 void pccbb_winlist_show(struct pccbb_win_chain *); 216 217 #endif /* rbus */ 218 219 /* for config_defer */ 220 static void pccbb_pci_callback __P((struct device *)); 221 222 #if defined SHOW_REGS 223 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 224 bus_space_tag_t memt, bus_space_handle_t memh)); 225 #endif 226 227 struct cfattach cbb_pci_ca = { 228 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 229 }; 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_card_detect 245 }; 246 247 #if rbus 248 static struct cardbus_functions pccbb_funcs = { 249 pccbb_rbus_cb_space_alloc, 250 pccbb_rbus_cb_space_free, 251 pccbb_cb_intr_establish, 252 pccbb_cb_intr_disestablish, 253 pccbb_ctrl, 254 pccbb_power, 255 pccbb_make_tag, 256 pccbb_free_tag, 257 pccbb_conf_read, 258 pccbb_conf_write, 259 }; 260 #else 261 static struct cardbus_functions pccbb_funcs = { 262 pccbb_ctrl, 263 pccbb_power, 264 pccbb_mem_open, 265 pccbb_mem_close, 266 pccbb_io_open, 267 pccbb_io_close, 268 pccbb_cb_intr_establish, 269 pccbb_cb_intr_disestablish, 270 pccbb_make_tag, 271 pccbb_conf_read, 272 pccbb_conf_write, 273 }; 274 #endif 275 276 int 277 pcicbbmatch(parent, match, aux) 278 struct device *parent; 279 struct cfdata *match; 280 void *aux; 281 { 282 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 283 284 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 285 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 286 PCI_INTERFACE(pa->pa_class) == 0) { 287 return 1; 288 } 289 290 return 0; 291 } 292 293 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 294 | ((prod) << PCI_PRODUCT_SHIFT)) 295 296 const struct yenta_chipinfo { 297 pcireg_t yc_id; /* vendor tag | product tag */ 298 int yc_chiptype; 299 int yc_flags; 300 } yc_chipsets[] = { 301 /* Texas Instruments chips */ 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 329 /* Ricoh chips */ 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 331 PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 341 PCCBB_PCMCIA_MEM_32}, 342 343 /* Toshiba products */ 344 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 345 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 347 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 349 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 351 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 352 353 /* Cirrus Logic products */ 354 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 355 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 357 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 358 359 /* sentinel, or Generic chip */ 360 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 361 }; 362 363 static int 364 cb_chipset(pci_id, flagp) 365 u_int32_t pci_id; 366 int *flagp; 367 { 368 const struct yenta_chipinfo *yc; 369 370 /* Loop over except the last default entry. */ 371 for (yc = yc_chipsets; yc < yc_chipsets + 372 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 373 if (pci_id == yc->yc_id) 374 break; 375 376 if (flagp != NULL) 377 *flagp = yc->yc_flags; 378 379 return (yc->yc_chiptype); 380 } 381 382 static void 383 pccbb_shutdown(void *arg) 384 { 385 struct pccbb_softc *sc = arg; 386 pcireg_t command; 387 388 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 389 390 /* 391 * turn off power 392 * 393 * XXX - do not turn off power if chipset is TI 113X because 394 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 395 */ 396 if (sc->sc_chipset != CB_TI113X) { 397 pccbb_power((cardbus_chipset_tag_t)sc, 398 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 399 } 400 401 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 402 0); 403 404 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 405 406 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 407 PCI_COMMAND_MASTER_ENABLE); 408 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 409 410 } 411 412 void 413 pccbbattach(parent, self, aux) 414 struct device *parent; 415 struct device *self; 416 void *aux; 417 { 418 struct pccbb_softc *sc = (void *)self; 419 struct pci_attach_args *pa = aux; 420 pci_chipset_tag_t pc = pa->pa_pc; 421 pcireg_t busreg, reg, sock_base; 422 bus_addr_t sockbase; 423 char devinfo[256]; 424 int flags; 425 426 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 427 428 pci_devinfo(pa->pa_id, 0, 0, devinfo); 429 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 430 #ifdef CBB_DEBUG 431 printf(" (chipflags %x)", flags); 432 #endif 433 printf("\n"); 434 435 TAILQ_INIT(&sc->sc_memwindow); 436 TAILQ_INIT(&sc->sc_iowindow); 437 438 #if rbus 439 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 440 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 441 442 #if 0 443 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 444 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 445 #endif 446 #endif /* rbus */ 447 448 sc->sc_base_memh = 0; 449 450 /* 451 * MAP socket registers and ExCA registers on memory-space 452 * When no valid address is set on socket base registers (on pci 453 * config space), get it not polite way. 454 */ 455 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 456 457 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 458 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 459 /* The address must be valid. */ 460 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 461 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 462 printf("%s: can't map socket base address 0x%x\n", 463 sc->sc_dev.dv_xname, sock_base); 464 /* 465 * I think it's funny: socket base registers must be 466 * mapped on memory space, but ... 467 */ 468 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 469 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 470 NULL)) { 471 printf("%s: can't map socket base address" 472 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 473 (unsigned long)sockbase); 474 /* give up... allocate reg space via rbus. */ 475 sc->sc_base_memh = 0; 476 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 477 } 478 } else { 479 DPRINTF(("%s: socket base address 0x%lx\n", 480 sc->sc_dev.dv_xname, sockbase)); 481 } 482 } 483 484 sc->sc_mem_start = 0; /* XXX */ 485 sc->sc_mem_end = 0xffffffff; /* XXX */ 486 487 /* 488 * When interrupt isn't routed correctly, give up probing cbb and do 489 * not kill pcic-compatible port. 490 */ 491 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 492 printf("%s: NOT USED because of unconfigured interrupt\n", 493 sc->sc_dev.dv_xname); 494 return; 495 } 496 497 /* 498 * When bus number isn't set correctly, give up using 32-bit CardBus 499 * mode. 500 */ 501 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 502 #if notyet 503 if (((busreg >> 8) & 0xff) == 0) { 504 printf("%s: CardBus support disabled because of unconfigured bus number\n", 505 sc->sc_dev.dv_xname); 506 flags |= PCCBB_PCMCIA_16BITONLY; 507 } 508 #endif 509 510 /* pccbb_machdep.c end */ 511 512 #if defined CBB_DEBUG 513 { 514 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 515 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 516 intrname[pa->pa_intrpin], pa->pa_intrline); 517 } 518 #endif 519 520 /* setup softc */ 521 sc->sc_pc = pc; 522 sc->sc_iot = pa->pa_iot; 523 sc->sc_memt = pa->pa_memt; 524 sc->sc_dmat = pa->pa_dmat; 525 sc->sc_tag = pa->pa_tag; 526 sc->sc_function = pa->pa_function; 527 sc->sc_sockbase = sock_base; 528 sc->sc_busnum = busreg; 529 530 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 531 532 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 533 534 shutdownhook_establish(pccbb_shutdown, sc); 535 536 /* Disable legacy register mapping. */ 537 switch (sc->sc_chipset) { 538 case CB_RX5C46X: /* fallthrough */ 539 #if 0 540 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 541 case CB_RX5C47X: 542 #endif 543 /* 544 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 545 * cannot be disabled by substituting 0 into PCI_LEGACY 546 * register. Ricoh CardBus bridges have special bits on Bridge 547 * control reg (addr 0x3e on PCI config space). 548 */ 549 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 550 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 551 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 552 break; 553 554 default: 555 /* XXX I don't know proper way to kill legacy I/O. */ 556 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 557 break; 558 } 559 560 config_defer(self, pccbb_pci_callback); 561 } 562 563 564 565 566 /* 567 * static void pccbb_pci_callback(struct device *self) 568 * 569 * The actual attach routine: get memory space for YENTA register 570 * space, setup YENTA register and route interrupt. 571 * 572 * This function should be deferred because this device may obtain 573 * memory space dynamically. This function must avoid obtaining 574 * memory area which has already kept for another device. 575 */ 576 static void 577 pccbb_pci_callback(self) 578 struct device *self; 579 { 580 struct pccbb_softc *sc = (void *)self; 581 pci_chipset_tag_t pc = sc->sc_pc; 582 bus_space_tag_t base_memt; 583 bus_space_handle_t base_memh; 584 u_int32_t maskreg; 585 pci_intr_handle_t ih; 586 const char *intrstr = NULL; 587 bus_addr_t sockbase; 588 struct cbslot_attach_args cba; 589 struct pcmciabus_attach_args paa; 590 struct cardslot_attach_args caa; 591 struct cardslot_softc *csc; 592 593 if (0 == sc->sc_base_memh) { 594 /* The socket registers aren't mapped correctly. */ 595 #if rbus 596 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 597 (sc->sc_chipset == CB_RX5C47X 598 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 599 0, &sockbase, &sc->sc_base_memh)) { 600 return; 601 } 602 sc->sc_base_memt = sc->sc_memt; 603 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 604 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 605 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 606 PCI_SOCKBASE))); 607 #else 608 sc->sc_base_memt = sc->sc_memt; 609 #if !defined CBB_PCI_BASE 610 #define CBB_PCI_BASE 0x20000000 611 #endif 612 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 613 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 614 /* cannot allocate memory space */ 615 return; 616 } 617 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 618 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 619 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 620 sc->sc_tag, PCI_SOCKBASE))); 621 #endif 622 } 623 624 /* bus bridge initialization */ 625 pccbb_chipinit(sc); 626 627 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 628 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 629 630 /* CSC Interrupt: Card detect interrupt on */ 631 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 632 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 633 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 634 /* reset interrupt */ 635 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 636 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 637 638 /* clear data structure for child device interrupt handlers */ 639 sc->sc_pil = NULL; 640 sc->sc_pil_intr_enable = 1; 641 642 /* Map and establish the interrupt. */ 643 if (pci_intr_map(&sc->sc_pa, &ih)) { 644 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 645 return; 646 } 647 intrstr = pci_intr_string(pc, ih); 648 649 /* 650 * XXX pccbbintr should be called under the priority lower 651 * than any other hard interrputs. 652 */ 653 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 654 655 if (sc->sc_ih == NULL) { 656 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 657 if (intrstr != NULL) { 658 printf(" at %s", intrstr); 659 } 660 printf("\n"); 661 return; 662 } 663 664 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 665 powerhook_establish(pccbb_powerhook, sc); 666 667 { 668 u_int32_t sockstat = 669 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 670 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 671 sc->sc_flags |= CBB_CARDEXIST; 672 } 673 } 674 675 /* 676 * attach cardbus 677 */ 678 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 679 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 680 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 681 682 /* initialize cbslot_attach */ 683 cba.cba_busname = "cardbus"; 684 cba.cba_iot = sc->sc_iot; 685 cba.cba_memt = sc->sc_memt; 686 cba.cba_dmat = sc->sc_dmat; 687 cba.cba_bus = (busreg >> 8) & 0x0ff; 688 cba.cba_cc = (void *)sc; 689 cba.cba_cf = &pccbb_funcs; 690 cba.cba_intrline = sc->sc_pa.pa_intrline; 691 692 #if rbus 693 cba.cba_rbus_iot = sc->sc_rbus_iot; 694 cba.cba_rbus_memt = sc->sc_rbus_memt; 695 #endif 696 697 cba.cba_cacheline = PCI_CACHELINE(bhlc); 698 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 699 700 if (bootverbose) { 701 printf("%s: cacheline 0x%x lattimer 0x%x\n", 702 sc->sc_dev.dv_xname, cba.cba_cacheline, 703 cba.cba_lattimer); 704 printf("%s: bhlc 0x%x lscp 0x%x\n", 705 sc->sc_dev.dv_xname, bhlc, busreg); 706 } 707 #if defined SHOW_REGS 708 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 709 sc->sc_base_memh); 710 #endif 711 } 712 713 pccbb_pcmcia_attach_setup(sc, &paa); 714 caa.caa_cb_attach = NULL; 715 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 716 caa.caa_cb_attach = &cba; 717 } 718 caa.caa_16_attach = &paa; 719 caa.caa_ph = &sc->sc_pcmcia_h; 720 721 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 722 DPRINTF(("pccbbattach: found cardslot\n")); 723 sc->sc_csc = csc; 724 } 725 726 return; 727 } 728 729 730 731 732 733 /* 734 * static void pccbb_chipinit(struct pccbb_softc *sc) 735 * 736 * This function initialize YENTA chip registers listed below: 737 * 1) PCI command reg, 738 * 2) PCI and CardBus latency timer, 739 * 3) route PCI interrupt, 740 * 4) close all memory and io windows. 741 */ 742 static void 743 pccbb_chipinit(sc) 744 struct pccbb_softc *sc; 745 { 746 pci_chipset_tag_t pc = sc->sc_pc; 747 pcitag_t tag = sc->sc_tag; 748 pcireg_t reg; 749 750 /* 751 * Set PCI command reg. 752 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 753 */ 754 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 755 /* I believe it is harmless. */ 756 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 757 PCI_COMMAND_MASTER_ENABLE); 758 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 759 760 /* 761 * Set CardBus latency timer. 762 */ 763 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 764 if (PCI_CB_LATENCY(reg) < 0x20) { 765 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 766 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 767 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 768 } 769 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 770 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 771 772 /* 773 * Set PCI latency timer. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 776 if (PCI_LATTIMER(reg) < 0x10) { 777 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 778 reg |= (0x10 << PCI_LATTIMER_SHIFT); 779 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 780 } 781 DPRINTF(("PCI latency timer 0x%x (%x)\n", 782 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 783 784 785 /* Route functional interrupts to PCI. */ 786 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 787 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 788 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 789 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 790 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 791 792 switch (sc->sc_chipset) { 793 case CB_TI113X: 794 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 795 /* This bit is shared, but may read as 0 on some chips, so set 796 it explicitly on both functions. */ 797 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 798 /* CSC intr enable */ 799 reg |= PCI113X_CBCTRL_PCI_CSC; 800 /* functional intr prohibit | prohibit ISA routing */ 801 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 802 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 803 break; 804 805 case CB_TI12XX: 806 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 807 reg |= PCI12XX_SYSCTRL_VCCPROT; 808 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 809 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 810 reg |= PCI12XX_CBCTRL_CSC; 811 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 812 break; 813 814 case CB_TOPIC95B: 815 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 816 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 817 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 818 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 819 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 820 sc->sc_dev.dv_xname, reg)); 821 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 822 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 823 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 824 DPRINTF(("0x%x\n", reg)); 825 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 826 break; 827 828 case CB_TOPIC97: 829 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 830 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 831 sc->sc_dev.dv_xname, reg)); 832 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 833 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 834 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 835 reg |= TOPIC97_SLOT_CTRL_PCIINT; 836 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 837 DPRINTF(("0x%x\n", reg)); 838 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 839 break; 840 } 841 842 /* Close all memory and I/O windows. */ 843 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 844 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 845 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 846 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 847 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 848 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 849 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 850 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 851 852 /* reset 16-bit pcmcia bus */ 853 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 854 0x800 + PCIC_INTR, 855 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 856 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 857 858 /* turn of power */ 859 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 860 } 861 862 863 864 865 /* 866 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 867 * struct pcmciabus_attach_args *paa) 868 * 869 * This function attaches 16-bit PCcard bus. 870 */ 871 STATIC void 872 pccbb_pcmcia_attach_setup(sc, paa) 873 struct pccbb_softc *sc; 874 struct pcmciabus_attach_args *paa; 875 { 876 struct pcic_handle *ph = &sc->sc_pcmcia_h; 877 #if rbus 878 rbus_tag_t rb; 879 #endif 880 881 /* initialize pcmcia part in pccbb_softc */ 882 ph->ph_parent = (struct device *)sc; 883 ph->sock = sc->sc_function; 884 ph->flags = 0; 885 ph->shutdown = 0; 886 ph->ih_irq = sc->sc_pa.pa_intrline; 887 ph->ph_bus_t = sc->sc_base_memt; 888 ph->ph_bus_h = sc->sc_base_memh; 889 ph->ph_read = pccbb_pcmcia_read; 890 ph->ph_write = pccbb_pcmcia_write; 891 sc->sc_pct = &pccbb_pcmcia_funcs; 892 893 /* 894 * We need to do a few things here: 895 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 896 * setting the IRQ numbers to 0. 897 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 898 * routing of CSC interrupts (e.g. card removal) to PCI while in 899 * PCMCIA mode. We just leave this set all the time. 900 * 3) Enable card insertion/removal interrupts in case the chip also 901 * needs that while in PCMCIA mode. 902 * 4) Clear any pending CSC interrupt. 903 */ 904 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 905 if (sc->sc_chipset == CB_TI113X) { 906 Pcic_write(ph, PCIC_CSC_INTR, 0); 907 } else { 908 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 909 Pcic_read(ph, PCIC_CSC); 910 } 911 912 /* initialize pcmcia bus attachment */ 913 paa->paa_busname = "pcmcia"; 914 paa->pct = sc->sc_pct; 915 paa->pch = ph; 916 paa->iobase = 0; /* I don't use them */ 917 paa->iosize = 0; 918 #if rbus 919 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 920 paa->iobase = rb->rb_start + rb->rb_offset; 921 paa->iosize = rb->rb_end - rb->rb_start; 922 #endif 923 924 return; 925 } 926 927 #if 0 928 STATIC void 929 pccbb_pcmcia_attach_card(ph) 930 struct pcic_handle *ph; 931 { 932 if (ph->flags & PCIC_FLAG_CARDP) { 933 panic("pccbb_pcmcia_attach_card: already attached"); 934 } 935 936 /* call the MI attach function */ 937 pcmcia_card_attach(ph->pcmcia); 938 939 ph->flags |= PCIC_FLAG_CARDP; 940 } 941 942 STATIC void 943 pccbb_pcmcia_detach_card(ph, flags) 944 struct pcic_handle *ph; 945 int flags; 946 { 947 if (!(ph->flags & PCIC_FLAG_CARDP)) { 948 panic("pccbb_pcmcia_detach_card: already detached"); 949 } 950 951 ph->flags &= ~PCIC_FLAG_CARDP; 952 953 /* call the MI detach function */ 954 pcmcia_card_detach(ph->pcmcia, flags); 955 } 956 #endif 957 958 /* 959 * int pccbbintr(arg) 960 * void *arg; 961 * This routine handles the interrupt from Yenta PCI-CardBus bridge 962 * itself. 963 */ 964 int 965 pccbbintr(arg) 966 void *arg; 967 { 968 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 969 u_int32_t sockevent, sockstate; 970 bus_space_tag_t memt = sc->sc_base_memt; 971 bus_space_handle_t memh = sc->sc_base_memh; 972 struct pcic_handle *ph = &sc->sc_pcmcia_h; 973 974 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 975 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 976 Pcic_read(ph, PCIC_CSC); 977 978 if (sockevent == 0) { 979 /* This intr is not for me: it may be for my child devices. */ 980 if (sc->sc_pil_intr_enable) { 981 return pccbbintr_function(sc); 982 } else { 983 return 0; 984 } 985 } 986 987 if (sockevent & CB_SOCKET_EVENT_CD) { 988 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 989 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 990 /* A card should be removed. */ 991 if (sc->sc_flags & CBB_CARDEXIST) { 992 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 993 sockevent)); 994 DPRINTF((" card removed, 0x%08x\n", sockstate)); 995 sc->sc_flags &= ~CBB_CARDEXIST; 996 if (sc->sc_csc->sc_status & 997 CARDSLOT_STATUS_CARD_16) { 998 #if 0 999 struct pcic_handle *ph = 1000 &sc->sc_pcmcia_h; 1001 1002 pcmcia_card_deactivate(ph->pcmcia); 1003 pccbb_pcmcia_socket_disable(ph); 1004 pccbb_pcmcia_detach_card(ph, 1005 DETACH_FORCE); 1006 #endif 1007 cardslot_event_throw(sc->sc_csc, 1008 CARDSLOT_EVENT_REMOVAL_16); 1009 } else if (sc->sc_csc->sc_status & 1010 CARDSLOT_STATUS_CARD_CB) { 1011 /* Cardbus intr removed */ 1012 cardslot_event_throw(sc->sc_csc, 1013 CARDSLOT_EVENT_REMOVAL_CB); 1014 } 1015 } 1016 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1017 /* 1018 * The pccbbintr may called from powerdown hook when 1019 * the system resumed, to detect the card 1020 * insertion/removal during suspension. 1021 */ 1022 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1023 if (sc->sc_flags & CBB_INSERTING) { 1024 callout_stop(&sc->sc_insert_ch); 1025 } 1026 callout_reset(&sc->sc_insert_ch, hz / 10, 1027 pci113x_insert, sc); 1028 sc->sc_flags |= CBB_INSERTING; 1029 } 1030 } 1031 1032 return (1); 1033 } 1034 1035 /* 1036 * static int pccbbintr_function(struct pccbb_softc *sc) 1037 * 1038 * This function calls each interrupt handler registered at the 1039 * bridge. The interrupt handlers are called in registered order. 1040 */ 1041 static int 1042 pccbbintr_function(sc) 1043 struct pccbb_softc *sc; 1044 { 1045 int retval = 0, val; 1046 struct pccbb_intrhand_list *pil; 1047 int s, splchanged; 1048 1049 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1050 /* 1051 * XXX priority change. gross. I use if-else 1052 * sentense instead of switch-case sentense because of 1053 * avoiding duplicate case value error. More than one 1054 * IPL_XXX use same value. It depends on 1055 * implimentation. 1056 */ 1057 splchanged = 1; 1058 if (pil->pil_level == IPL_SERIAL) { 1059 s = splserial(); 1060 } else if (pil->pil_level == IPL_HIGH) { 1061 s = splhigh(); 1062 } else if (pil->pil_level == IPL_CLOCK) { 1063 s = splclock(); 1064 } else if (pil->pil_level == IPL_AUDIO) { 1065 s = splaudio(); 1066 } else if (pil->pil_level == IPL_IMP) { 1067 s = splvm(); /* XXX */ 1068 } else if (pil->pil_level == IPL_TTY) { 1069 s = spltty(); 1070 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1071 s = splsoftserial(); 1072 } else if (pil->pil_level == IPL_NET) { 1073 s = splnet(); 1074 } else { 1075 splchanged = 0; 1076 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1077 } 1078 1079 val = (*pil->pil_func)(pil->pil_arg); 1080 1081 if (splchanged != 0) { 1082 splx(s); 1083 } 1084 1085 retval = retval == 1 ? 1 : 1086 retval == 0 ? val : val != 0 ? val : retval; 1087 } 1088 1089 return retval; 1090 } 1091 1092 static void 1093 pci113x_insert(arg) 1094 void *arg; 1095 { 1096 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1097 u_int32_t sockevent, sockstate; 1098 1099 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1100 CB_SOCKET_EVENT); 1101 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1102 CB_SOCKET_STAT); 1103 1104 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1105 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1106 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1107 sc->sc_flags |= CBB_CARDEXIST; 1108 /* call pccard interrupt handler here */ 1109 if (sockstate & CB_SOCKET_STAT_16BIT) { 1110 /* 16-bit card found */ 1111 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1112 cardslot_event_throw(sc->sc_csc, 1113 CARDSLOT_EVENT_INSERTION_16); 1114 } else if (sockstate & CB_SOCKET_STAT_CB) { 1115 /* cardbus card found */ 1116 /* cardbus_attach_card(sc->sc_csc); */ 1117 cardslot_event_throw(sc->sc_csc, 1118 CARDSLOT_EVENT_INSERTION_CB); 1119 } else { 1120 /* who are you? */ 1121 } 1122 } else { 1123 callout_reset(&sc->sc_insert_ch, hz / 10, 1124 pci113x_insert, sc); 1125 } 1126 } 1127 1128 #define PCCBB_PCMCIA_OFFSET 0x800 1129 static u_int8_t 1130 pccbb_pcmcia_read(ph, reg) 1131 struct pcic_handle *ph; 1132 int reg; 1133 { 1134 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1135 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1136 1137 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1138 PCCBB_PCMCIA_OFFSET + reg); 1139 } 1140 1141 static void 1142 pccbb_pcmcia_write(ph, reg, val) 1143 struct pcic_handle *ph; 1144 int reg; 1145 u_int8_t val; 1146 { 1147 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1148 val); 1149 1150 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1151 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1152 } 1153 1154 /* 1155 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1156 */ 1157 STATIC int 1158 pccbb_ctrl(ct, command) 1159 cardbus_chipset_tag_t ct; 1160 int command; 1161 { 1162 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1163 1164 switch (command) { 1165 case CARDBUS_CD: 1166 if (2 == pccbb_detect_card(sc)) { 1167 int retval = 0; 1168 int status = cb_detect_voltage(sc); 1169 if (PCCARD_VCC_5V & status) { 1170 retval |= CARDBUS_5V_CARD; 1171 } 1172 if (PCCARD_VCC_3V & status) { 1173 retval |= CARDBUS_3V_CARD; 1174 } 1175 if (PCCARD_VCC_XV & status) { 1176 retval |= CARDBUS_XV_CARD; 1177 } 1178 if (PCCARD_VCC_YV & status) { 1179 retval |= CARDBUS_YV_CARD; 1180 } 1181 return retval; 1182 } else { 1183 return 0; 1184 } 1185 break; 1186 case CARDBUS_RESET: 1187 return cb_reset(sc); 1188 break; 1189 case CARDBUS_IO_ENABLE: /* fallthrough */ 1190 case CARDBUS_IO_DISABLE: /* fallthrough */ 1191 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1192 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1193 case CARDBUS_BM_ENABLE: /* fallthrough */ 1194 case CARDBUS_BM_DISABLE: /* fallthrough */ 1195 return pccbb_cardenable(sc, command); 1196 break; 1197 } 1198 1199 return 0; 1200 } 1201 1202 /* 1203 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1204 * This function returns true when it succeeds and returns false when 1205 * it fails. 1206 */ 1207 STATIC int 1208 pccbb_power(ct, command) 1209 cardbus_chipset_tag_t ct; 1210 int command; 1211 { 1212 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1213 1214 u_int32_t status, sock_ctrl; 1215 bus_space_tag_t memt = sc->sc_base_memt; 1216 bus_space_handle_t memh = sc->sc_base_memh; 1217 1218 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1219 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1220 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1221 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1222 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1223 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1224 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1225 "UNKNOWN", 1226 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1227 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1228 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1229 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1230 "UNKNOWN", command)); 1231 1232 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1233 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1234 1235 switch (command & CARDBUS_VCCMASK) { 1236 case CARDBUS_VCC_UC: 1237 break; 1238 case CARDBUS_VCC_5V: 1239 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1240 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1241 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1242 } else { 1243 printf("%s: BAD voltage request: no 5 V card\n", 1244 sc->sc_dev.dv_xname); 1245 } 1246 break; 1247 case CARDBUS_VCC_3V: 1248 if (CB_SOCKET_STAT_3VCARD & status) { 1249 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1250 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1251 } else { 1252 printf("%s: BAD voltage request: no 3.3 V card\n", 1253 sc->sc_dev.dv_xname); 1254 } 1255 break; 1256 case CARDBUS_VCC_0V: 1257 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1258 break; 1259 default: 1260 return 0; /* power NEVER changed */ 1261 break; 1262 } 1263 1264 switch (command & CARDBUS_VPPMASK) { 1265 case CARDBUS_VPP_UC: 1266 break; 1267 case CARDBUS_VPP_0V: 1268 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1269 break; 1270 case CARDBUS_VPP_VCC: 1271 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1272 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1273 break; 1274 case CARDBUS_VPP_12V: 1275 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1276 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1277 break; 1278 } 1279 1280 #if 0 1281 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1282 #endif 1283 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1284 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1285 1286 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1287 printf 1288 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1289 sc->sc_dev.dv_xname, sock_ctrl, status); 1290 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1291 (command & CARDBUS_VCCMASK) == 1292 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1293 CARDBUS_VCCMASK) == 1294 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1295 CARDBUS_VCCMASK) == 1296 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1297 CARDBUS_VCCMASK) == 1298 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1299 CARDBUS_VCCMASK) == 1300 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1301 CARDBUS_VCCMASK) == 1302 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1303 (command & CARDBUS_VPPMASK) == 1304 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1305 CARDBUS_VPPMASK) == 1306 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1307 CARDBUS_VPPMASK) == 1308 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1309 CARDBUS_VPPMASK) == 1310 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1311 #if 0 1312 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1313 u_int32_t force = 1314 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1315 /* Reset Bad Vcc request */ 1316 force &= ~CB_SOCKET_FORCE_BADVCC; 1317 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1318 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1319 CB_SOCKET_STAT)); 1320 return 1; 1321 } 1322 #endif 1323 return 0; 1324 } 1325 1326 /* 1327 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1328 * time is 20 ms, some PC-Card bridge requires longer duration. 1329 */ 1330 #if 0 /* XXX called on interrupt context */ 1331 DELAY_MS(300, sc); 1332 #else 1333 delay(300 * 1000); 1334 #endif 1335 1336 return 1; /* power changed correctly */ 1337 } 1338 1339 #if defined CB_PCMCIA_POLL 1340 struct cb_poll_str { 1341 void *arg; 1342 int (*func) __P((void *)); 1343 int level; 1344 pccard_chipset_tag_t ct; 1345 int count; 1346 struct callout poll_ch; 1347 }; 1348 1349 static struct cb_poll_str cb_poll[10]; 1350 static int cb_poll_n = 0; 1351 1352 static void cb_pcmcia_poll __P((void *arg)); 1353 1354 static void 1355 cb_pcmcia_poll(arg) 1356 void *arg; 1357 { 1358 struct cb_poll_str *poll = arg; 1359 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1360 struct pccbb_softc *sc = psc->cpc_parent; 1361 int s; 1362 u_int32_t spsr; /* socket present-state reg */ 1363 1364 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1365 switch (poll->level) { 1366 case IPL_NET: 1367 s = splnet(); 1368 break; 1369 case IPL_BIO: 1370 s = splbio(); 1371 break; 1372 case IPL_TTY: /* fallthrough */ 1373 default: 1374 s = spltty(); 1375 break; 1376 } 1377 1378 spsr = 1379 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1380 CB_SOCKET_STAT); 1381 1382 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1383 if (!(spsr & 0x40)) { /* CINT low */ 1384 #else 1385 if (1) { 1386 #endif 1387 if ((*poll->func) (poll->arg) == 1) { 1388 ++poll->count; 1389 printf("intr: reported from poller, 0x%x\n", spsr); 1390 #if defined LEVEL2 1391 } else { 1392 printf("intr: miss! 0x%x\n", spsr); 1393 #endif 1394 } 1395 } 1396 splx(s); 1397 } 1398 #endif /* defined CB_PCMCIA_POLL */ 1399 1400 /* 1401 * static int pccbb_detect_card(struct pccbb_softc *sc) 1402 * return value: 0 if no card exists. 1403 * 1 if 16-bit card exists. 1404 * 2 if cardbus card exists. 1405 */ 1406 static int 1407 pccbb_detect_card(sc) 1408 struct pccbb_softc *sc; 1409 { 1410 bus_space_handle_t base_memh = sc->sc_base_memh; 1411 bus_space_tag_t base_memt = sc->sc_base_memt; 1412 u_int32_t sockstat = 1413 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1414 int retval = 0; 1415 1416 /* CD1 and CD2 asserted */ 1417 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1418 /* card must be present */ 1419 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1420 /* NOTACARD DEASSERTED */ 1421 if (CB_SOCKET_STAT_CB & sockstat) { 1422 /* CardBus mode */ 1423 retval = 2; 1424 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1425 /* 16-bit mode */ 1426 retval = 1; 1427 } 1428 } 1429 } 1430 return retval; 1431 } 1432 1433 /* 1434 * STATIC int cb_reset(struct pccbb_softc *sc) 1435 * This function resets CardBus card. 1436 */ 1437 STATIC int 1438 cb_reset(sc) 1439 struct pccbb_softc *sc; 1440 { 1441 /* 1442 * Reset Assert at least 20 ms 1443 * Some machines request longer duration. 1444 */ 1445 int reset_duration = 1446 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1447 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1448 1449 /* Reset bit Assert (bit 6 at 0x3E) */ 1450 bcr |= CB_BCR_RESET_ENABLE; 1451 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1452 DELAY_MS(reset_duration, sc); 1453 1454 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1455 /* Reset bit Deassert (bit 6 at 0x3E) */ 1456 bcr &= ~CB_BCR_RESET_ENABLE; 1457 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1458 DELAY_MS(reset_duration, sc); 1459 } 1460 /* No card found on the slot. Keep Reset. */ 1461 return 1; 1462 } 1463 1464 /* 1465 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1466 * This function detect card Voltage. 1467 */ 1468 STATIC int 1469 cb_detect_voltage(sc) 1470 struct pccbb_softc *sc; 1471 { 1472 u_int32_t psr; /* socket present-state reg */ 1473 bus_space_tag_t iot = sc->sc_base_memt; 1474 bus_space_handle_t ioh = sc->sc_base_memh; 1475 int vol = PCCARD_VCC_UKN; /* set 0 */ 1476 1477 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1478 1479 if (0x400u & psr) { 1480 vol |= PCCARD_VCC_5V; 1481 } 1482 if (0x800u & psr) { 1483 vol |= PCCARD_VCC_3V; 1484 } 1485 1486 return vol; 1487 } 1488 1489 STATIC int 1490 cbbprint(aux, pcic) 1491 void *aux; 1492 const char *pcic; 1493 { 1494 /* 1495 struct cbslot_attach_args *cba = aux; 1496 1497 if (cba->cba_slot >= 0) { 1498 printf(" slot %d", cba->cba_slot); 1499 } 1500 */ 1501 return UNCONF; 1502 } 1503 1504 /* 1505 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1506 * This function enables and disables the card 1507 */ 1508 STATIC int 1509 pccbb_cardenable(sc, function) 1510 struct pccbb_softc *sc; 1511 int function; 1512 { 1513 u_int32_t command = 1514 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1515 1516 DPRINTF(("pccbb_cardenable:")); 1517 switch (function) { 1518 case CARDBUS_IO_ENABLE: 1519 command |= PCI_COMMAND_IO_ENABLE; 1520 break; 1521 case CARDBUS_IO_DISABLE: 1522 command &= ~PCI_COMMAND_IO_ENABLE; 1523 break; 1524 case CARDBUS_MEM_ENABLE: 1525 command |= PCI_COMMAND_MEM_ENABLE; 1526 break; 1527 case CARDBUS_MEM_DISABLE: 1528 command &= ~PCI_COMMAND_MEM_ENABLE; 1529 break; 1530 case CARDBUS_BM_ENABLE: 1531 command |= PCI_COMMAND_MASTER_ENABLE; 1532 break; 1533 case CARDBUS_BM_DISABLE: 1534 command &= ~PCI_COMMAND_MASTER_ENABLE; 1535 break; 1536 default: 1537 return 0; 1538 } 1539 1540 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1541 DPRINTF((" command reg 0x%x\n", command)); 1542 return 1; 1543 } 1544 1545 #if !rbus 1546 /* 1547 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1548 */ 1549 static int 1550 pccbb_io_open(ct, win, start, end) 1551 cardbus_chipset_tag_t ct; 1552 int win; 1553 u_int32_t start, end; 1554 { 1555 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1556 int basereg; 1557 int limitreg; 1558 1559 if ((win < 0) || (win > 2)) { 1560 #if defined DIAGNOSTIC 1561 printf("cardbus_io_open: window out of range %d\n", win); 1562 #endif 1563 return 0; 1564 } 1565 1566 basereg = win * 8 + 0x2c; 1567 limitreg = win * 8 + 0x30; 1568 1569 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1570 start, basereg, end, limitreg)); 1571 1572 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1573 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1574 return 1; 1575 } 1576 1577 /* 1578 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1579 */ 1580 static int 1581 pccbb_io_close(ct, win) 1582 cardbus_chipset_tag_t ct; 1583 int win; 1584 { 1585 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1586 int basereg; 1587 int limitreg; 1588 1589 if ((win < 0) || (win > 2)) { 1590 #if defined DIAGNOSTIC 1591 printf("cardbus_io_close: window out of range %d\n", win); 1592 #endif 1593 return 0; 1594 } 1595 1596 basereg = win * 8 + 0x2c; 1597 limitreg = win * 8 + 0x30; 1598 1599 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1600 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1601 return 1; 1602 } 1603 1604 /* 1605 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1606 */ 1607 static int 1608 pccbb_mem_open(ct, win, start, end) 1609 cardbus_chipset_tag_t ct; 1610 int win; 1611 u_int32_t start, end; 1612 { 1613 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1614 int basereg; 1615 int limitreg; 1616 1617 if ((win < 0) || (win > 2)) { 1618 #if defined DIAGNOSTIC 1619 printf("cardbus_mem_open: window out of range %d\n", win); 1620 #endif 1621 return 0; 1622 } 1623 1624 basereg = win * 8 + 0x1c; 1625 limitreg = win * 8 + 0x20; 1626 1627 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1628 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1629 return 1; 1630 } 1631 1632 /* 1633 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1634 */ 1635 static int 1636 pccbb_mem_close(ct, win) 1637 cardbus_chipset_tag_t ct; 1638 int win; 1639 { 1640 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1641 int basereg; 1642 int limitreg; 1643 1644 if ((win < 0) || (win > 2)) { 1645 #if defined DIAGNOSTIC 1646 printf("cardbus_mem_close: window out of range %d\n", win); 1647 #endif 1648 return 0; 1649 } 1650 1651 basereg = win * 8 + 0x1c; 1652 limitreg = win * 8 + 0x20; 1653 1654 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1655 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1656 return 1; 1657 } 1658 #endif 1659 1660 /* 1661 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1662 * int irq, 1663 * int level, 1664 * int (* func) __P((void *)), 1665 * void *arg) 1666 * 1667 * This function registers an interrupt handler at the bridge, in 1668 * order not to call the interrupt handlers of child devices when 1669 * a card-deletion interrupt occurs. 1670 * 1671 * The arguments irq and level are not used. 1672 */ 1673 static void * 1674 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1675 cardbus_chipset_tag_t ct; 1676 int irq, level; 1677 int (*func) __P((void *)); 1678 void *arg; 1679 { 1680 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1681 1682 return pccbb_intr_establish(sc, irq, level, func, arg); 1683 } 1684 1685 1686 /* 1687 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1688 * void *ih) 1689 * 1690 * This function removes an interrupt handler pointed by ih. 1691 */ 1692 static void 1693 pccbb_cb_intr_disestablish(ct, ih) 1694 cardbus_chipset_tag_t ct; 1695 void *ih; 1696 { 1697 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1698 1699 pccbb_intr_disestablish(sc, ih); 1700 } 1701 1702 1703 void 1704 pccbb_intr_route(sc) 1705 struct pccbb_softc *sc; 1706 { 1707 pcireg_t reg; 1708 1709 /* initialize bridge intr routing */ 1710 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1711 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1712 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1713 1714 switch (sc->sc_chipset) { 1715 case CB_TI113X: 1716 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1717 /* functional intr enabled */ 1718 reg |= PCI113X_CBCTRL_PCI_INTR; 1719 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1720 break; 1721 default: 1722 break; 1723 } 1724 } 1725 1726 /* 1727 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1728 * int irq, 1729 * int level, 1730 * int (* func) __P((void *)), 1731 * void *arg) 1732 * 1733 * This function registers an interrupt handler at the bridge, in 1734 * order not to call the interrupt handlers of child devices when 1735 * a card-deletion interrupt occurs. 1736 * 1737 * The arguments irq is not used because pccbb selects intr vector. 1738 */ 1739 static void * 1740 pccbb_intr_establish(sc, irq, level, func, arg) 1741 struct pccbb_softc *sc; 1742 int irq, level; 1743 int (*func) __P((void *)); 1744 void *arg; 1745 { 1746 struct pccbb_intrhand_list *pil, *newpil; 1747 1748 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1749 1750 if (sc->sc_pil == NULL) { 1751 pccbb_intr_route(sc); 1752 1753 } 1754 1755 /* 1756 * Allocate a room for interrupt handler structure. 1757 */ 1758 if (NULL == (newpil = 1759 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1760 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1761 return NULL; 1762 } 1763 1764 newpil->pil_func = func; 1765 newpil->pil_arg = arg; 1766 newpil->pil_level = level; 1767 newpil->pil_next = NULL; 1768 1769 if (sc->sc_pil == NULL) { 1770 sc->sc_pil = newpil; 1771 } else { 1772 for (pil = sc->sc_pil; pil->pil_next != NULL; 1773 pil = pil->pil_next); 1774 pil->pil_next = newpil; 1775 } 1776 1777 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1778 1779 return newpil; 1780 } 1781 1782 /* 1783 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1784 * void *ih) 1785 * 1786 * This function removes an interrupt handler pointed by ih. 1787 */ 1788 static void 1789 pccbb_intr_disestablish(sc, ih) 1790 struct pccbb_softc *sc; 1791 void *ih; 1792 { 1793 struct pccbb_intrhand_list *pil, **pil_prev; 1794 pcireg_t reg; 1795 1796 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1797 1798 pil_prev = &sc->sc_pil; 1799 1800 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1801 if (pil == ih) { 1802 *pil_prev = pil->pil_next; 1803 free(pil, M_DEVBUF); 1804 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1805 break; 1806 } 1807 pil_prev = &pil->pil_next; 1808 } 1809 1810 if (sc->sc_pil == NULL) { 1811 /* No interrupt handlers */ 1812 1813 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1814 1815 /* stop routing PCI intr */ 1816 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1817 reg |= CB_BCR_INTR_IREQ_ENABLE; 1818 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1819 1820 switch (sc->sc_chipset) { 1821 case CB_TI113X: 1822 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1823 /* functional intr disabled */ 1824 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1825 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1826 break; 1827 default: 1828 break; 1829 } 1830 } 1831 } 1832 1833 #if defined SHOW_REGS 1834 static void 1835 cb_show_regs(pc, tag, memt, memh) 1836 pci_chipset_tag_t pc; 1837 pcitag_t tag; 1838 bus_space_tag_t memt; 1839 bus_space_handle_t memh; 1840 { 1841 int i; 1842 printf("PCI config regs:"); 1843 for (i = 0; i < 0x50; i += 4) { 1844 if (i % 16 == 0) { 1845 printf("\n 0x%02x:", i); 1846 } 1847 printf(" %08x", pci_conf_read(pc, tag, i)); 1848 } 1849 for (i = 0x80; i < 0xb0; i += 4) { 1850 if (i % 16 == 0) { 1851 printf("\n 0x%02x:", i); 1852 } 1853 printf(" %08x", pci_conf_read(pc, tag, i)); 1854 } 1855 1856 if (memh == 0) { 1857 printf("\n"); 1858 return; 1859 } 1860 1861 printf("\nsocket regs:"); 1862 for (i = 0; i <= 0x10; i += 0x04) { 1863 printf(" %08x", bus_space_read_4(memt, memh, i)); 1864 } 1865 printf("\nExCA regs:"); 1866 for (i = 0; i < 0x08; ++i) { 1867 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1868 } 1869 printf("\n"); 1870 return; 1871 } 1872 #endif 1873 1874 /* 1875 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1876 * int busno, int devno, int function) 1877 * This is the function to make a tag to access config space of 1878 * a CardBus Card. It works same as pci_conf_read. 1879 */ 1880 static cardbustag_t 1881 pccbb_make_tag(cc, busno, devno, function) 1882 cardbus_chipset_tag_t cc; 1883 int busno, devno, function; 1884 { 1885 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1886 1887 return pci_make_tag(sc->sc_pc, busno, devno, function); 1888 } 1889 1890 static void 1891 pccbb_free_tag(cc, tag) 1892 cardbus_chipset_tag_t cc; 1893 cardbustag_t tag; 1894 { 1895 } 1896 1897 /* 1898 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1899 * cardbustag_t tag, int offset) 1900 * This is the function to read the config space of a CardBus Card. 1901 * It works same as pci_conf_read. 1902 */ 1903 static cardbusreg_t 1904 pccbb_conf_read(cc, tag, offset) 1905 cardbus_chipset_tag_t cc; 1906 cardbustag_t tag; 1907 int offset; /* register offset */ 1908 { 1909 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1910 1911 return pci_conf_read(sc->sc_pc, tag, offset); 1912 } 1913 1914 /* 1915 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1916 * int offs, cardbusreg_t val) 1917 * This is the function to write the config space of a CardBus Card. 1918 * It works same as pci_conf_write. 1919 */ 1920 static void 1921 pccbb_conf_write(cc, tag, reg, val) 1922 cardbus_chipset_tag_t cc; 1923 cardbustag_t tag; 1924 int reg; /* register offset */ 1925 cardbusreg_t val; 1926 { 1927 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1928 1929 pci_conf_write(sc->sc_pc, tag, reg, val); 1930 } 1931 1932 #if 0 1933 STATIC int 1934 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1935 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1936 int speed, int flags, 1937 bus_space_handle_t * iohp) 1938 #endif 1939 /* 1940 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1941 * bus_addr_t start, bus_size_t size, 1942 * bus_size_t align, 1943 * struct pcmcia_io_handle *pcihp 1944 * 1945 * This function only allocates I/O region for pccard. This function 1946 * never maps the allocated region to pccard I/O area. 1947 * 1948 * XXX: The interface of this function is not very good, I believe. 1949 */ 1950 STATIC int 1951 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1952 pcmcia_chipset_handle_t pch; 1953 bus_addr_t start; /* start address */ 1954 bus_size_t size; 1955 bus_size_t align; 1956 struct pcmcia_io_handle *pcihp; 1957 { 1958 struct pcic_handle *ph = (struct pcic_handle *)pch; 1959 bus_addr_t ioaddr; 1960 int flags = 0; 1961 bus_space_tag_t iot; 1962 bus_space_handle_t ioh; 1963 bus_addr_t mask; 1964 #if rbus 1965 rbus_tag_t rb; 1966 #endif 1967 if (align == 0) { 1968 align = size; /* XXX: funny??? */ 1969 } 1970 1971 if (start != 0) { 1972 /* XXX: assume all card decode lower 10 bits by its hardware */ 1973 mask = 0x3ff; 1974 } else { 1975 /* 1976 * calculate mask: 1977 * 1. get the most significant bit of size (call it msb). 1978 * 2. compare msb with the value of size. 1979 * 3. if size is larger, shift msb left once. 1980 * 4. obtain mask value to decrement msb. 1981 */ 1982 bus_size_t size_tmp = size; 1983 int shifts = 0; 1984 1985 mask = 1; 1986 while (size_tmp) { 1987 ++shifts; 1988 size_tmp >>= 1; 1989 } 1990 mask = (1 << shifts); 1991 if (mask < size) { 1992 mask <<= 1; 1993 } 1994 --mask; 1995 } 1996 1997 /* 1998 * Allocate some arbitrary I/O space. 1999 */ 2000 2001 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2002 2003 #if rbus 2004 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2005 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2006 return 1; 2007 } 2008 #else 2009 if (start) { 2010 ioaddr = start; 2011 if (bus_space_map(iot, start, size, 0, &ioh)) { 2012 return 1; 2013 } 2014 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2015 (u_long) ioaddr, (u_long) size)); 2016 } else { 2017 flags |= PCMCIA_IO_ALLOCATED; 2018 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2019 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2020 size, align, 0, 0, &ioaddr, &ioh)) { 2021 /* No room be able to be get. */ 2022 return 1; 2023 } 2024 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2025 (u_long) ioaddr, (u_long) size)); 2026 } 2027 #endif 2028 2029 pcihp->iot = iot; 2030 pcihp->ioh = ioh; 2031 pcihp->addr = ioaddr; 2032 pcihp->size = size; 2033 pcihp->flags = flags; 2034 2035 return 0; 2036 } 2037 2038 /* 2039 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2040 * struct pcmcia_io_handle *pcihp) 2041 * 2042 * This function only frees I/O region for pccard. 2043 * 2044 * XXX: The interface of this function is not very good, I believe. 2045 */ 2046 void 2047 pccbb_pcmcia_io_free(pch, pcihp) 2048 pcmcia_chipset_handle_t pch; 2049 struct pcmcia_io_handle *pcihp; 2050 { 2051 #if !rbus 2052 bus_space_tag_t iot = pcihp->iot; 2053 #endif 2054 bus_space_handle_t ioh = pcihp->ioh; 2055 bus_size_t size = pcihp->size; 2056 2057 #if rbus 2058 struct pccbb_softc *sc = 2059 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2060 rbus_tag_t rb = sc->sc_rbus_iot; 2061 2062 rbus_space_free(rb, ioh, size, NULL); 2063 #else 2064 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2065 bus_space_free(iot, ioh, size); 2066 else 2067 bus_space_unmap(iot, ioh, size); 2068 #endif 2069 } 2070 2071 /* 2072 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2073 * bus_addr_t offset, bus_size_t size, 2074 * struct pcmcia_io_handle *pcihp, 2075 * int *windowp) 2076 * 2077 * This function maps the allocated I/O region to pccard. This function 2078 * never allocates any I/O region for pccard I/O area. I don't 2079 * understand why the original authors of pcmciabus separated alloc and 2080 * map. I believe the two must be unite. 2081 * 2082 * XXX: no wait timing control? 2083 */ 2084 int 2085 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2086 pcmcia_chipset_handle_t pch; 2087 int width; 2088 bus_addr_t offset; 2089 bus_size_t size; 2090 struct pcmcia_io_handle *pcihp; 2091 int *windowp; 2092 { 2093 struct pcic_handle *ph = (struct pcic_handle *)pch; 2094 bus_addr_t ioaddr = pcihp->addr + offset; 2095 int i, win; 2096 #if defined CBB_DEBUG 2097 static char *width_names[] = { "dynamic", "io8", "io16" }; 2098 #endif 2099 2100 /* Sanity check I/O handle. */ 2101 2102 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2103 panic("pccbb_pcmcia_io_map iot is bogus"); 2104 } 2105 2106 /* XXX Sanity check offset/size. */ 2107 2108 win = -1; 2109 for (i = 0; i < PCIC_IO_WINS; i++) { 2110 if ((ph->ioalloc & (1 << i)) == 0) { 2111 win = i; 2112 ph->ioalloc |= (1 << i); 2113 break; 2114 } 2115 } 2116 2117 if (win == -1) { 2118 return 1; 2119 } 2120 2121 *windowp = win; 2122 2123 /* XXX this is pretty gross */ 2124 2125 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2126 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2127 2128 /* XXX wtf is this doing here? */ 2129 2130 #if 0 2131 printf(" port 0x%lx", (u_long) ioaddr); 2132 if (size > 1) { 2133 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2134 } 2135 #endif 2136 2137 ph->io[win].addr = ioaddr; 2138 ph->io[win].size = size; 2139 ph->io[win].width = width; 2140 2141 /* actual dirty register-value changing in the function below. */ 2142 pccbb_pcmcia_do_io_map(ph, win); 2143 2144 return 0; 2145 } 2146 2147 /* 2148 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2149 * 2150 * This function changes register-value to map I/O region for pccard. 2151 */ 2152 static void 2153 pccbb_pcmcia_do_io_map(ph, win) 2154 struct pcic_handle *ph; 2155 int win; 2156 { 2157 static u_int8_t pcic_iowidth[3] = { 2158 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2159 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2160 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2161 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2162 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2163 }; 2164 2165 #define PCIC_SIA_START_LOW 0 2166 #define PCIC_SIA_START_HIGH 1 2167 #define PCIC_SIA_STOP_LOW 2 2168 #define PCIC_SIA_STOP_HIGH 3 2169 2170 int regbase_win = 0x8 + win * 0x04; 2171 u_int8_t ioctl, enable; 2172 2173 DPRINTF( 2174 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2175 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2176 ph->io[win].width * 8)); 2177 2178 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2179 ph->io[win].addr & 0xff); 2180 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2181 (ph->io[win].addr >> 8) & 0xff); 2182 2183 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2184 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2185 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2186 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2187 2188 ioctl = Pcic_read(ph, PCIC_IOCTL); 2189 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2190 switch (win) { 2191 case 0: 2192 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2193 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2194 PCIC_IOCTL_IO0_DATASIZE_MASK); 2195 ioctl |= pcic_iowidth[ph->io[win].width]; 2196 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2197 break; 2198 case 1: 2199 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2200 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2201 PCIC_IOCTL_IO1_DATASIZE_MASK); 2202 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2203 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2204 break; 2205 } 2206 Pcic_write(ph, PCIC_IOCTL, ioctl); 2207 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2208 #if defined CBB_DEBUG 2209 { 2210 u_int8_t start_low = 2211 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2212 u_int8_t start_high = 2213 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2214 u_int8_t stop_low = 2215 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2216 u_int8_t stop_high = 2217 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2218 printf 2219 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2220 start_low, start_high, stop_low, stop_high, ioctl, enable); 2221 } 2222 #endif 2223 } 2224 2225 /* 2226 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2227 * 2228 * This function unmaps I/O region. No return value. 2229 */ 2230 STATIC void 2231 pccbb_pcmcia_io_unmap(pch, win) 2232 pcmcia_chipset_handle_t pch; 2233 int win; 2234 { 2235 struct pcic_handle *ph = (struct pcic_handle *)pch; 2236 int reg; 2237 2238 if (win >= PCIC_IO_WINS || win < 0) { 2239 panic("pccbb_pcmcia_io_unmap: window out of range"); 2240 } 2241 2242 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2243 switch (win) { 2244 case 0: 2245 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2246 break; 2247 case 1: 2248 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2249 break; 2250 } 2251 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2252 2253 ph->ioalloc &= ~(1 << win); 2254 } 2255 2256 /* 2257 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2258 * 2259 * This function enables the card. All information is stored in 2260 * the first argument, pcmcia_chipset_handle_t. 2261 */ 2262 static void 2263 pccbb_pcmcia_wait_ready(ph) 2264 struct pcic_handle *ph; 2265 { 2266 int i; 2267 2268 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2269 Pcic_read(ph, PCIC_IF_STATUS))); 2270 2271 for (i = 0; i < 2000; i++) { 2272 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2273 return; 2274 } 2275 DELAY_MS(2, ph->ph_parent); 2276 #ifdef CBB_DEBUG 2277 if ((i > 1000) && (i % 25 == 24)) 2278 printf("."); 2279 #endif 2280 } 2281 2282 #ifdef DIAGNOSTIC 2283 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2284 Pcic_read(ph, PCIC_IF_STATUS)); 2285 #endif 2286 } 2287 2288 /* 2289 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2290 * 2291 * This function enables the card. All information is stored in 2292 * the first argument, pcmcia_chipset_handle_t. 2293 */ 2294 STATIC void 2295 pccbb_pcmcia_socket_enable(pch) 2296 pcmcia_chipset_handle_t pch; 2297 { 2298 struct pcic_handle *ph = (struct pcic_handle *)pch; 2299 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2300 int cardtype, win; 2301 u_int8_t power, intr; 2302 pcireg_t spsr; 2303 int voltage; 2304 2305 /* this bit is mostly stolen from pcic_attach_card */ 2306 2307 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2308 2309 /* get card Vcc info */ 2310 2311 spsr = 2312 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2313 CB_SOCKET_STAT); 2314 if (spsr & CB_SOCKET_STAT_5VCARD) { 2315 DPRINTF(("5V card\n")); 2316 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2317 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2318 DPRINTF(("3V card\n")); 2319 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2320 } else { 2321 printf("?V card, 0x%x\n", spsr); /* XXX */ 2322 return; 2323 } 2324 2325 /* disable socket: negate output enable bit and power off */ 2326 2327 power = 0; 2328 Pcic_write(ph, PCIC_PWRCTL, power); 2329 2330 /* power down the socket to reset it, clear the card reset pin */ 2331 2332 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2333 2334 /* 2335 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2336 * we are changing Vcc (Toff). 2337 */ 2338 /* delay(300*1000); too much */ 2339 2340 /* assert reset bit */ 2341 intr = Pcic_read(ph, PCIC_INTR); 2342 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2343 Pcic_write(ph, PCIC_INTR, intr); 2344 2345 /* power up the socket and output enable */ 2346 power = Pcic_read(ph, PCIC_PWRCTL); 2347 power |= PCIC_PWRCTL_OE; 2348 Pcic_write(ph, PCIC_PWRCTL, power); 2349 pccbb_power(sc, voltage); 2350 2351 /* 2352 * hold RESET at least 20 ms: the spec says only 10 us is 2353 * enough, but TI1130 requires at least 20 ms. 2354 */ 2355 #if 0 /* XXX called on interrupt context */ 2356 DELAY_MS(20, sc); 2357 #else 2358 delay(20 * 1000); 2359 #endif 2360 2361 /* clear the reset flag */ 2362 2363 intr |= PCIC_INTR_RESET; 2364 Pcic_write(ph, PCIC_INTR, intr); 2365 2366 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2367 2368 #if 0 /* XXX called on interrupt context */ 2369 DELAY_MS(20, sc); 2370 #else 2371 delay(20 * 1000); 2372 #endif 2373 2374 /* wait for the chip to finish initializing */ 2375 2376 pccbb_pcmcia_wait_ready(ph); 2377 2378 /* zero out the address windows */ 2379 2380 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2381 2382 /* set the card type */ 2383 2384 cardtype = pcmcia_card_gettype(ph->pcmcia); 2385 2386 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2387 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2388 Pcic_write(ph, PCIC_INTR, intr); 2389 2390 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2391 ph->ph_parent->dv_xname, ph->sock, 2392 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2393 2394 /* reinstall all the memory and io mappings */ 2395 2396 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2397 if (ph->memalloc & (1 << win)) { 2398 pccbb_pcmcia_do_mem_map(ph, win); 2399 } 2400 } 2401 2402 for (win = 0; win < PCIC_IO_WINS; ++win) { 2403 if (ph->ioalloc & (1 << win)) { 2404 pccbb_pcmcia_do_io_map(ph, win); 2405 } 2406 } 2407 } 2408 2409 /* 2410 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2411 * 2412 * This function disables the card. All information is stored in 2413 * the first argument, pcmcia_chipset_handle_t. 2414 */ 2415 STATIC void 2416 pccbb_pcmcia_socket_disable(pch) 2417 pcmcia_chipset_handle_t pch; 2418 { 2419 struct pcic_handle *ph = (struct pcic_handle *)pch; 2420 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2421 u_int8_t power, intr; 2422 2423 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2424 2425 /* reset signal asserting... */ 2426 2427 intr = Pcic_read(ph, PCIC_INTR); 2428 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2429 Pcic_write(ph, PCIC_INTR, intr); 2430 delay(2 * 1000); 2431 2432 /* power down the socket */ 2433 power = Pcic_read(ph, PCIC_PWRCTL); 2434 power &= ~PCIC_PWRCTL_OE; 2435 Pcic_write(ph, PCIC_PWRCTL, power); 2436 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2437 /* 2438 * wait 300ms until power fails (Tpf). 2439 */ 2440 #if 0 /* XXX called on interrupt context */ 2441 DELAY_MS(300, sc); 2442 #else 2443 delay(300 * 1000); 2444 #endif 2445 } 2446 2447 /* 2448 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2449 * 2450 * This function detects whether a card is in the slot or not. 2451 * If a card is inserted, return 1. Otherwise, return 0. 2452 */ 2453 STATIC int 2454 pccbb_pcmcia_card_detect(pch) 2455 pcmcia_chipset_handle_t pch; 2456 { 2457 struct pcic_handle *ph = (struct pcic_handle *)pch; 2458 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2459 2460 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2461 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2462 } 2463 2464 #if 0 2465 STATIC int 2466 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2467 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2468 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2469 #endif 2470 /* 2471 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2472 * bus_size_t size, 2473 * struct pcmcia_mem_handle *pcmhp) 2474 * 2475 * This function only allocates memory region for pccard. This 2476 * function never maps the allocated region to pccard memory area. 2477 * 2478 * XXX: Why the argument of start address is not in? 2479 */ 2480 STATIC int 2481 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2482 pcmcia_chipset_handle_t pch; 2483 bus_size_t size; 2484 struct pcmcia_mem_handle *pcmhp; 2485 { 2486 struct pcic_handle *ph = (struct pcic_handle *)pch; 2487 bus_space_handle_t memh; 2488 bus_addr_t addr; 2489 bus_size_t sizepg; 2490 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2491 #if rbus 2492 rbus_tag_t rb; 2493 #endif 2494 2495 /* out of sc->memh, allocate as many pages as necessary */ 2496 2497 /* convert size to PCIC pages */ 2498 /* 2499 * This is not enough; when the requested region is on the page 2500 * boundaries, this may calculate wrong result. 2501 */ 2502 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2503 #if 0 2504 if (sizepg > PCIC_MAX_MEM_PAGES) { 2505 return 1; 2506 } 2507 #endif 2508 2509 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2510 return 1; 2511 } 2512 2513 addr = 0; /* XXX gcc -Wuninitialized */ 2514 2515 #if rbus 2516 rb = sc->sc_rbus_memt; 2517 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2518 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2519 &addr, &memh)) { 2520 return 1; 2521 } 2522 #else 2523 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2524 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2525 0, /* boundary */ 2526 0, /* flags */ 2527 &addr, &memh)) { 2528 return 1; 2529 } 2530 #endif 2531 2532 DPRINTF( 2533 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2534 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2535 2536 pcmhp->memt = sc->sc_memt; 2537 pcmhp->memh = memh; 2538 pcmhp->addr = addr; 2539 pcmhp->size = size; 2540 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2541 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2542 pcmhp->mhandle = 0; 2543 /* No offset??? Funny. */ 2544 2545 return 0; 2546 } 2547 2548 /* 2549 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2550 * struct pcmcia_mem_handle *pcmhp) 2551 * 2552 * This function release the memory space allocated by the function 2553 * pccbb_pcmcia_mem_alloc(). 2554 */ 2555 STATIC void 2556 pccbb_pcmcia_mem_free(pch, pcmhp) 2557 pcmcia_chipset_handle_t pch; 2558 struct pcmcia_mem_handle *pcmhp; 2559 { 2560 #if rbus 2561 struct pcic_handle *ph = (struct pcic_handle *)pch; 2562 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2563 2564 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2565 #else 2566 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2567 #endif 2568 } 2569 2570 /* 2571 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2572 * 2573 * This function release the memory space allocated by the function 2574 * pccbb_pcmcia_mem_alloc(). 2575 */ 2576 STATIC void 2577 pccbb_pcmcia_do_mem_map(ph, win) 2578 struct pcic_handle *ph; 2579 int win; 2580 { 2581 int regbase_win; 2582 bus_addr_t phys_addr; 2583 bus_addr_t phys_end; 2584 2585 #define PCIC_SMM_START_LOW 0 2586 #define PCIC_SMM_START_HIGH 1 2587 #define PCIC_SMM_STOP_LOW 2 2588 #define PCIC_SMM_STOP_HIGH 3 2589 #define PCIC_CMA_LOW 4 2590 #define PCIC_CMA_HIGH 5 2591 2592 u_int8_t start_low, start_high = 0; 2593 u_int8_t stop_low, stop_high; 2594 u_int8_t off_low, off_high; 2595 u_int8_t mem_window; 2596 int reg; 2597 2598 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2599 int mem8 = 2600 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2601 || (kind == PCMCIA_MEM_ATTR); 2602 2603 regbase_win = 0x10 + win * 0x08; 2604 2605 phys_addr = ph->mem[win].addr; 2606 phys_end = phys_addr + ph->mem[win].size; 2607 2608 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2609 phys_addr, phys_end, ph->mem[win].offset)); 2610 2611 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2612 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2613 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2614 2615 /* bit 19:12 */ 2616 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2617 /* bit 23:20 and bit 7 on */ 2618 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2619 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2620 /* bit 31:24, for 32-bit address */ 2621 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2622 2623 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2624 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2625 2626 if (((struct pccbb_softc *)ph-> 2627 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2628 Pcic_write(ph, 0x40 + win, mem_window); 2629 } 2630 2631 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2632 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2633 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2634 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2635 2636 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2637 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2638 2639 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2640 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2641 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2642 | ((kind == PCMCIA_MEM_ATTR) ? 2643 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2644 2645 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2646 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2647 2648 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2649 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2650 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2651 2652 #if defined CBB_DEBUG 2653 { 2654 int r1, r2, r3, r4, r5, r6, r7 = 0; 2655 2656 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2657 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2658 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2659 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2660 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2661 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2662 if (((struct pccbb_softc *)(ph-> 2663 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2664 r7 = Pcic_read(ph, 0x40 + win); 2665 } 2666 2667 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2668 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2669 if (((struct pccbb_softc *)(ph-> 2670 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2671 DPRINTF((" %02x", r7)); 2672 } 2673 DPRINTF(("\n")); 2674 } 2675 #endif 2676 } 2677 2678 /* 2679 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2680 * bus_addr_t card_addr, bus_size_t size, 2681 * struct pcmcia_mem_handle *pcmhp, 2682 * bus_addr_t *offsetp, int *windowp) 2683 * 2684 * This function maps memory space allocated by the function 2685 * pccbb_pcmcia_mem_alloc(). 2686 */ 2687 STATIC int 2688 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2689 pcmcia_chipset_handle_t pch; 2690 int kind; 2691 bus_addr_t card_addr; 2692 bus_size_t size; 2693 struct pcmcia_mem_handle *pcmhp; 2694 bus_addr_t *offsetp; 2695 int *windowp; 2696 { 2697 struct pcic_handle *ph = (struct pcic_handle *)pch; 2698 bus_addr_t busaddr; 2699 long card_offset; 2700 int win; 2701 2702 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2703 if ((ph->memalloc & (1 << win)) == 0) { 2704 ph->memalloc |= (1 << win); 2705 break; 2706 } 2707 } 2708 2709 if (win == PCIC_MEM_WINS) { 2710 return 1; 2711 } 2712 2713 *windowp = win; 2714 2715 /* XXX this is pretty gross */ 2716 2717 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2718 panic("pccbb_pcmcia_mem_map memt is bogus"); 2719 } 2720 2721 busaddr = pcmhp->addr; 2722 2723 /* 2724 * compute the address offset to the pcmcia address space for the 2725 * pcic. this is intentionally signed. The masks and shifts below 2726 * will cause TRT to happen in the pcic registers. Deal with making 2727 * sure the address is aligned, and return the alignment offset. 2728 */ 2729 2730 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2731 card_addr -= *offsetp; 2732 2733 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2734 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2735 (u_long) card_addr)); 2736 2737 /* 2738 * include the offset in the size, and decrement size by one, since 2739 * the hw wants start/stop 2740 */ 2741 size += *offsetp - 1; 2742 2743 card_offset = (((long)card_addr) - ((long)busaddr)); 2744 2745 ph->mem[win].addr = busaddr; 2746 ph->mem[win].size = size; 2747 ph->mem[win].offset = card_offset; 2748 ph->mem[win].kind = kind; 2749 2750 pccbb_pcmcia_do_mem_map(ph, win); 2751 2752 return 0; 2753 } 2754 2755 /* 2756 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2757 * int window) 2758 * 2759 * This function unmaps memory space which mapped by the function 2760 * pccbb_pcmcia_mem_map(). 2761 */ 2762 STATIC void 2763 pccbb_pcmcia_mem_unmap(pch, window) 2764 pcmcia_chipset_handle_t pch; 2765 int window; 2766 { 2767 struct pcic_handle *ph = (struct pcic_handle *)pch; 2768 int reg; 2769 2770 if (window >= PCIC_MEM_WINS) { 2771 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2772 } 2773 2774 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2775 reg &= ~(1 << window); 2776 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2777 2778 ph->memalloc &= ~(1 << window); 2779 } 2780 2781 #if defined PCCBB_PCMCIA_POLL 2782 struct pccbb_poll_str { 2783 void *arg; 2784 int (*func) __P((void *)); 2785 int level; 2786 struct pcic_handle *ph; 2787 int count; 2788 int num; 2789 struct callout poll_ch; 2790 }; 2791 2792 static struct pccbb_poll_str pccbb_poll[10]; 2793 static int pccbb_poll_n = 0; 2794 2795 static void pccbb_pcmcia_poll __P((void *arg)); 2796 2797 static void 2798 pccbb_pcmcia_poll(arg) 2799 void *arg; 2800 { 2801 struct pccbb_poll_str *poll = arg; 2802 struct pcic_handle *ph = poll->ph; 2803 struct pccbb_softc *sc = ph->sc; 2804 int s; 2805 u_int32_t spsr; /* socket present-state reg */ 2806 2807 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2808 switch (poll->level) { 2809 case IPL_NET: 2810 s = splnet(); 2811 break; 2812 case IPL_BIO: 2813 s = splbio(); 2814 break; 2815 case IPL_TTY: /* fallthrough */ 2816 default: 2817 s = spltty(); 2818 break; 2819 } 2820 2821 spsr = 2822 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2823 CB_SOCKET_STAT); 2824 2825 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2826 if (!(spsr & 0x40)) /* CINT low */ 2827 #else 2828 if (1) 2829 #endif 2830 { 2831 if ((*poll->func) (poll->arg) > 0) { 2832 ++poll->count; 2833 // printf("intr: reported from poller, 0x%x\n", spsr); 2834 #if defined LEVEL2 2835 } else { 2836 printf("intr: miss! 0x%x\n", spsr); 2837 #endif 2838 } 2839 } 2840 splx(s); 2841 } 2842 #endif /* defined CB_PCMCIA_POLL */ 2843 2844 /* 2845 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2846 * struct pcmcia_function *pf, 2847 * int ipl, 2848 * int (*func)(void *), 2849 * void *arg); 2850 * 2851 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2852 */ 2853 STATIC void * 2854 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2855 pcmcia_chipset_handle_t pch; 2856 struct pcmcia_function *pf; 2857 int ipl; 2858 int (*func) __P((void *)); 2859 void *arg; 2860 { 2861 struct pcic_handle *ph = (struct pcic_handle *)pch; 2862 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2863 2864 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2865 /* what should I do? */ 2866 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2867 DPRINTF( 2868 ("%s does not provide edge nor pulse interrupt\n", 2869 sc->sc_dev.dv_xname)); 2870 return NULL; 2871 } 2872 /* 2873 * XXX Noooooo! The interrupt flag must set properly!! 2874 * dumb pcmcia driver!! 2875 */ 2876 } 2877 2878 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2879 } 2880 2881 /* 2882 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2883 * void *ih) 2884 * 2885 * This function disables PC-Card interrupt. 2886 */ 2887 STATIC void 2888 pccbb_pcmcia_intr_disestablish(pch, ih) 2889 pcmcia_chipset_handle_t pch; 2890 void *ih; 2891 { 2892 struct pcic_handle *ph = (struct pcic_handle *)pch; 2893 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2894 2895 pccbb_intr_disestablish(sc, ih); 2896 } 2897 2898 #if rbus 2899 /* 2900 * static int 2901 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2902 * bus_addr_t addr, bus_size_t size, 2903 * bus_addr_t mask, bus_size_t align, 2904 * int flags, bus_addr_t *addrp; 2905 * bus_space_handle_t *bshp) 2906 * 2907 * This function allocates a portion of memory or io space for 2908 * clients. This function is called from CardBus card drivers. 2909 */ 2910 static int 2911 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2912 cardbus_chipset_tag_t ct; 2913 rbus_tag_t rb; 2914 bus_addr_t addr; 2915 bus_size_t size; 2916 bus_addr_t mask; 2917 bus_size_t align; 2918 int flags; 2919 bus_addr_t *addrp; 2920 bus_space_handle_t *bshp; 2921 { 2922 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2923 2924 DPRINTF( 2925 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2926 addr, size, mask, align)); 2927 2928 if (align == 0) { 2929 align = size; 2930 } 2931 2932 if (rb->rb_bt == sc->sc_memt) { 2933 if (align < 16) { 2934 return 1; 2935 } 2936 } else if (rb->rb_bt == sc->sc_iot) { 2937 if (align < 4) { 2938 return 1; 2939 } 2940 /* XXX: hack for avoiding ISA image */ 2941 if (mask < 0x0100) { 2942 mask = 0x3ff; 2943 addr = 0x300; 2944 } 2945 2946 } else { 2947 DPRINTF( 2948 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 2949 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 2950 return 1; 2951 /* XXX: panic here? */ 2952 } 2953 2954 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2955 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2956 return 1; 2957 } 2958 2959 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2960 2961 return 0; 2962 } 2963 2964 /* 2965 * static int 2966 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2967 * bus_space_handle_t *bshp, bus_size_t size); 2968 * 2969 * This function is called from CardBus card drivers. 2970 */ 2971 static int 2972 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2973 cardbus_chipset_tag_t ct; 2974 rbus_tag_t rb; 2975 bus_space_handle_t bsh; 2976 bus_size_t size; 2977 { 2978 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2979 bus_space_tag_t bt = rb->rb_bt; 2980 2981 pccbb_close_win(sc, bt, bsh, size); 2982 2983 if (bt == sc->sc_memt) { 2984 } else if (bt == sc->sc_iot) { 2985 } else { 2986 return 1; 2987 /* XXX: panic here? */ 2988 } 2989 2990 return rbus_space_free(rb, bsh, size, NULL); 2991 } 2992 #endif /* rbus */ 2993 2994 #if rbus 2995 2996 static int 2997 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2998 struct pccbb_softc *sc; 2999 bus_space_tag_t bst; 3000 bus_addr_t addr; 3001 bus_size_t size; 3002 bus_space_handle_t bsh; 3003 int flags; 3004 { 3005 struct pccbb_win_chain_head *head; 3006 bus_addr_t align; 3007 3008 head = &sc->sc_iowindow; 3009 align = 0x04; 3010 if (sc->sc_memt == bst) { 3011 head = &sc->sc_memwindow; 3012 align = 0x1000; 3013 DPRINTF(("using memory window, %x %x %x\n\n", 3014 sc->sc_iot, sc->sc_memt, bst)); 3015 } 3016 3017 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3018 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3019 sc->sc_dev.dv_xname, 3020 (head == &sc->sc_memwindow) ? "mem" : "io"); 3021 } 3022 pccbb_winset(align, sc, bst); 3023 3024 return 0; 3025 } 3026 3027 static int 3028 pccbb_close_win(sc, bst, bsh, size) 3029 struct pccbb_softc *sc; 3030 bus_space_tag_t bst; 3031 bus_space_handle_t bsh; 3032 bus_size_t size; 3033 { 3034 struct pccbb_win_chain_head *head; 3035 bus_addr_t align; 3036 3037 head = &sc->sc_iowindow; 3038 align = 0x04; 3039 if (sc->sc_memt == bst) { 3040 head = &sc->sc_memwindow; 3041 align = 0x1000; 3042 } 3043 3044 if (pccbb_winlist_delete(head, bsh, size)) { 3045 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3046 sc->sc_dev.dv_xname, 3047 (head == &sc->sc_memwindow) ? "mem" : "io"); 3048 } 3049 pccbb_winset(align, sc, bst); 3050 3051 return 0; 3052 } 3053 3054 static int 3055 pccbb_winlist_insert(head, start, size, bsh, flags) 3056 struct pccbb_win_chain_head *head; 3057 bus_addr_t start; 3058 bus_size_t size; 3059 bus_space_handle_t bsh; 3060 int flags; 3061 { 3062 struct pccbb_win_chain *chainp, *elem; 3063 3064 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3065 M_NOWAIT)) == NULL) 3066 return (1); /* fail */ 3067 3068 elem->wc_start = start; 3069 elem->wc_end = start + (size - 1); 3070 elem->wc_handle = bsh; 3071 elem->wc_flags = flags; 3072 3073 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3074 chainp = TAILQ_NEXT(chainp, wc_list)) { 3075 if (chainp->wc_end < start) 3076 continue; 3077 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3078 return (0); 3079 } 3080 3081 TAILQ_INSERT_TAIL(head, elem, wc_list); 3082 return (0); 3083 } 3084 3085 static int 3086 pccbb_winlist_delete(head, bsh, size) 3087 struct pccbb_win_chain_head *head; 3088 bus_space_handle_t bsh; 3089 bus_size_t size; 3090 { 3091 struct pccbb_win_chain *chainp; 3092 3093 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3094 chainp = TAILQ_NEXT(chainp, wc_list)) { 3095 if (chainp->wc_handle != bsh) 3096 continue; 3097 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3098 printf("pccbb_winlist_delete: window 0x%lx size " 3099 "inconsistent: 0x%lx, 0x%lx\n", 3100 (unsigned long)chainp->wc_start, 3101 (unsigned long)(chainp->wc_end - chainp->wc_start), 3102 (unsigned long)(size - 1)); 3103 return 1; 3104 } 3105 3106 TAILQ_REMOVE(head, chainp, wc_list); 3107 free(chainp, M_DEVBUF); 3108 3109 return 0; 3110 } 3111 3112 return 1; /* fail: no candidate to remove */ 3113 } 3114 3115 static void 3116 pccbb_winset(align, sc, bst) 3117 bus_addr_t align; 3118 struct pccbb_softc *sc; 3119 bus_space_tag_t bst; 3120 { 3121 pci_chipset_tag_t pc; 3122 pcitag_t tag; 3123 bus_addr_t mask = ~(align - 1); 3124 struct { 3125 cardbusreg_t win_start; 3126 cardbusreg_t win_limit; 3127 int win_flags; 3128 } win[2]; 3129 struct pccbb_win_chain *chainp; 3130 int offs; 3131 3132 win[0].win_start = win[1].win_start = 0xffffffff; 3133 win[0].win_limit = win[1].win_limit = 0; 3134 win[0].win_flags = win[1].win_flags = 0; 3135 3136 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3137 offs = 0x2c; 3138 if (sc->sc_memt == bst) { 3139 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3140 offs = 0x1c; 3141 } 3142 3143 if (chainp != NULL) { 3144 win[0].win_start = chainp->wc_start & mask; 3145 win[0].win_limit = chainp->wc_end & mask; 3146 win[0].win_flags = chainp->wc_flags; 3147 chainp = TAILQ_NEXT(chainp, wc_list); 3148 } 3149 3150 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3151 if (win[1].win_start == 0xffffffff) { 3152 /* window 1 is not used */ 3153 if ((win[0].win_flags == chainp->wc_flags) && 3154 (win[0].win_limit + align >= 3155 (chainp->wc_start & mask))) { 3156 /* concatenate */ 3157 win[0].win_limit = chainp->wc_end & mask; 3158 } else { 3159 /* make new window */ 3160 win[1].win_start = chainp->wc_start & mask; 3161 win[1].win_limit = chainp->wc_end & mask; 3162 win[1].win_flags = chainp->wc_flags; 3163 } 3164 continue; 3165 } 3166 3167 /* Both windows are engaged. */ 3168 if (win[0].win_flags == win[1].win_flags) { 3169 /* same flags */ 3170 if (win[0].win_flags == chainp->wc_flags) { 3171 if (win[1].win_start - (win[0].win_limit + 3172 align) < 3173 (chainp->wc_start & mask) - 3174 ((chainp->wc_end & mask) + align)) { 3175 /* 3176 * merge window 0 and 1, and set win1 3177 * to chainp 3178 */ 3179 win[0].win_limit = win[1].win_limit; 3180 win[1].win_start = 3181 chainp->wc_start & mask; 3182 win[1].win_limit = 3183 chainp->wc_end & mask; 3184 } else { 3185 win[1].win_limit = 3186 chainp->wc_end & mask; 3187 } 3188 } else { 3189 /* different flags */ 3190 3191 /* concatenate win0 and win1 */ 3192 win[0].win_limit = win[1].win_limit; 3193 /* allocate win[1] to new space */ 3194 win[1].win_start = chainp->wc_start & mask; 3195 win[1].win_limit = chainp->wc_end & mask; 3196 win[1].win_flags = chainp->wc_flags; 3197 } 3198 } else { 3199 /* the flags of win[0] and win[1] is different */ 3200 if (win[0].win_flags == chainp->wc_flags) { 3201 win[0].win_limit = chainp->wc_end & mask; 3202 /* 3203 * XXX this creates overlapping windows, so 3204 * what should the poor bridge do if one is 3205 * cachable, and the other is not? 3206 */ 3207 printf("%s: overlapping windows\n", 3208 sc->sc_dev.dv_xname); 3209 } else { 3210 win[1].win_limit = chainp->wc_end & mask; 3211 } 3212 } 3213 } 3214 3215 pc = sc->sc_pc; 3216 tag = sc->sc_tag; 3217 pci_conf_write(pc, tag, offs, win[0].win_start); 3218 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3219 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3220 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3221 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3222 pci_conf_read(pc, tag, offs), 3223 pci_conf_read(pc, tag, offs + 4) + align, 3224 pci_conf_read(pc, tag, offs + 8), 3225 pci_conf_read(pc, tag, offs + 12) + align)); 3226 3227 if (bst == sc->sc_memt) { 3228 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3229 3230 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3231 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3232 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3233 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3234 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3235 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3236 } 3237 } 3238 3239 #endif /* rbus */ 3240 3241 static void 3242 pccbb_powerhook(why, arg) 3243 int why; 3244 void *arg; 3245 { 3246 struct pccbb_softc *sc = arg; 3247 u_int32_t reg; 3248 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3249 bus_space_handle_t base_memh = sc->sc_base_memh; 3250 3251 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3252 3253 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3254 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3255 if (sc->sc_pil_intr_enable) { 3256 (void)pccbbintr_function(sc); 3257 } 3258 sc->sc_pil_intr_enable = 0; 3259 3260 /* ToDo: deactivate or suspend child devices */ 3261 3262 } 3263 3264 if (why == PWR_RESUME) { 3265 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3266 /* BIOS did not recover this register */ 3267 pci_conf_write (sc->sc_pc, sc->sc_tag, 3268 PCI_SOCKBASE, sc->sc_sockbase); 3269 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3270 /* BIOS did not recover this register */ 3271 pci_conf_write (sc->sc_pc, sc->sc_tag, 3272 PCI_BUSNUM, sc->sc_busnum); 3273 /* CSC Interrupt: Card detect interrupt on */ 3274 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3275 /* Card detect intr is turned on. */ 3276 reg |= CB_SOCKET_MASK_CD; 3277 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3278 /* reset interrupt */ 3279 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3280 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3281 3282 /* 3283 * check for card insertion or removal during suspend period. 3284 * XXX: the code can't cope with card swap (remove then 3285 * insert). how can we detect such situation? 3286 */ 3287 (void)pccbbintr(sc); 3288 3289 sc->sc_pil_intr_enable = 1; 3290 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3291 3292 /* ToDo: activate or wakeup child devices */ 3293 } 3294 } 3295
Indexes created Fri Sep 26 20:09:58 GMT 2025