pccbb.c revision 1.69
1 /* $NetBSD: pccbb.c,v 1.69 2001/10/17 10:25:51 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/reboot.h> /* for bootverbose */ 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 #include <sys/proc.h> 57 58 #include <machine/intr.h> 59 #include <machine/bus.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/pccbbreg.h> 66 67 #include <dev/cardbus/cardslotvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 71 #include <dev/pcmcia/pcmciareg.h> 72 #include <dev/pcmcia/pcmciavar.h> 73 74 #include <dev/ic/i82365reg.h> 75 #include <dev/ic/i82365var.h> 76 #include <dev/pci/pccbbvar.h> 77 78 #include "locators.h" 79 80 #ifndef __NetBSD_Version__ 81 struct cfdriver cbb_cd = { 82 NULL, "cbb", DV_DULL 83 }; 84 #endif 85 86 #if defined CBB_DEBUG 87 #define DPRINTF(x) printf x 88 #define STATIC 89 #else 90 #define DPRINTF(x) 91 #define STATIC static 92 #endif 93 94 /* 95 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 96 * if you want to wait more than 1 ms. 97 */ 98 #define DELAY_MS(time, param) \ 99 do { \ 100 if (cold == 0) { \ 101 int tick = (hz*(time))/1000; \ 102 \ 103 if (tick <= 1) { \ 104 tick = 2; \ 105 } \ 106 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 107 } else { \ 108 delay((time)*1000); \ 109 } \ 110 } while (0) 111 112 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 113 void pccbbattach __P((struct device *, struct device *, void *)); 114 int pccbbintr __P((void *)); 115 static void pci113x_insert __P((void *)); 116 static int pccbbintr_function __P((struct pccbb_softc *)); 117 118 static int pccbb_detect_card __P((struct pccbb_softc *)); 119 120 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 121 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset __P((struct pccbb_softc *)); 126 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 127 STATIC int cbbprint __P((void *, const char *)); 128 129 static int cb_chipset __P((u_int32_t, int *)); 130 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 131 struct pcmciabus_attach_args *)); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 134 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 135 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 136 #endif 137 138 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 139 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 140 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 141 #if !rbus 142 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 143 u_int32_t)); 144 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 145 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 146 u_int32_t)); 147 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc)); 151 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 152 153 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc)); 155 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 156 157 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 158 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 159 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 160 int)); 161 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 162 cardbusreg_t)); 163 static void pccbb_chipinit __P((struct pccbb_softc *)); 164 165 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 166 struct pcmcia_mem_handle *)); 167 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 168 struct pcmcia_mem_handle *)); 169 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 171 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 172 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 173 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 174 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *)); 176 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *)); 178 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 179 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 180 struct pcmcia_function *, int, int (*)(void *), void *)); 181 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 182 void *)); 183 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 184 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 185 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 186 187 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 188 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 189 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 190 static void pccbb_powerhook __P((int, void *)); 191 192 /* bus-space allocation and deallocation functions */ 193 #if rbus 194 195 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 196 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 197 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 198 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 199 bus_space_handle_t, bus_size_t)); 200 201 #endif /* rbus */ 202 203 #if rbus 204 205 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 206 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 207 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_space_handle_t, bus_size_t)); 209 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 210 bus_size_t, bus_space_handle_t, int)); 211 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 212 bus_space_handle_t, bus_size_t)); 213 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 214 bus_space_tag_t)); 215 void pccbb_winlist_show(struct pccbb_win_chain *); 216 217 #endif /* rbus */ 218 219 /* for config_defer */ 220 static void pccbb_pci_callback __P((struct device *)); 221 222 #if defined SHOW_REGS 223 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 224 bus_space_tag_t memt, bus_space_handle_t memh)); 225 #endif 226 227 struct cfattach cbb_pci_ca = { 228 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 229 }; 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_card_detect 245 }; 246 247 #if rbus 248 static struct cardbus_functions pccbb_funcs = { 249 pccbb_rbus_cb_space_alloc, 250 pccbb_rbus_cb_space_free, 251 pccbb_cb_intr_establish, 252 pccbb_cb_intr_disestablish, 253 pccbb_ctrl, 254 pccbb_power, 255 pccbb_make_tag, 256 pccbb_free_tag, 257 pccbb_conf_read, 258 pccbb_conf_write, 259 }; 260 #else 261 static struct cardbus_functions pccbb_funcs = { 262 pccbb_ctrl, 263 pccbb_power, 264 pccbb_mem_open, 265 pccbb_mem_close, 266 pccbb_io_open, 267 pccbb_io_close, 268 pccbb_cb_intr_establish, 269 pccbb_cb_intr_disestablish, 270 pccbb_make_tag, 271 pccbb_conf_read, 272 pccbb_conf_write, 273 }; 274 #endif 275 276 int 277 pcicbbmatch(parent, match, aux) 278 struct device *parent; 279 struct cfdata *match; 280 void *aux; 281 { 282 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 283 284 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 285 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 286 PCI_INTERFACE(pa->pa_class) == 0) { 287 return 1; 288 } 289 290 return 0; 291 } 292 293 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 294 | ((prod) << PCI_PRODUCT_SHIFT)) 295 296 const struct yenta_chipinfo { 297 pcireg_t yc_id; /* vendor tag | product tag */ 298 int yc_chiptype; 299 int yc_flags; 300 } yc_chipsets[] = { 301 /* Texas Instruments chips */ 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 329 /* Ricoh chips */ 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 331 PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 341 PCCBB_PCMCIA_MEM_32}, 342 343 /* Toshiba products */ 344 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 345 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 347 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 349 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 351 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 352 353 /* Cirrus Logic products */ 354 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 355 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 357 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 358 359 /* sentinel, or Generic chip */ 360 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 361 }; 362 363 static int 364 cb_chipset(pci_id, flagp) 365 u_int32_t pci_id; 366 int *flagp; 367 { 368 const struct yenta_chipinfo *yc; 369 370 /* Loop over except the last default entry. */ 371 for (yc = yc_chipsets; yc < yc_chipsets + 372 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 373 if (pci_id == yc->yc_id) 374 break; 375 376 if (flagp != NULL) 377 *flagp = yc->yc_flags; 378 379 return (yc->yc_chiptype); 380 } 381 382 static void 383 pccbb_shutdown(void *arg) 384 { 385 struct pccbb_softc *sc = arg; 386 pcireg_t command; 387 388 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 389 390 /* 391 * turn off power 392 * 393 * XXX - do not turn off power if chipset is TI 113X because 394 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 395 */ 396 if (sc->sc_chipset != CB_TI113X) { 397 pccbb_power((cardbus_chipset_tag_t)sc, 398 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 399 } 400 401 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 402 0); 403 404 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 405 406 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 407 PCI_COMMAND_MASTER_ENABLE); 408 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 409 410 } 411 412 void 413 pccbbattach(parent, self, aux) 414 struct device *parent; 415 struct device *self; 416 void *aux; 417 { 418 struct pccbb_softc *sc = (void *)self; 419 struct pci_attach_args *pa = aux; 420 pci_chipset_tag_t pc = pa->pa_pc; 421 pcireg_t busreg, reg, sock_base; 422 bus_addr_t sockbase; 423 char devinfo[256]; 424 int flags; 425 426 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 427 428 pci_devinfo(pa->pa_id, 0, 0, devinfo); 429 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 430 #ifdef CBB_DEBUG 431 printf(" (chipflags %x)", flags); 432 #endif 433 printf("\n"); 434 435 TAILQ_INIT(&sc->sc_memwindow); 436 TAILQ_INIT(&sc->sc_iowindow); 437 438 #if rbus 439 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 440 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 441 442 #if 0 443 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 444 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 445 #endif 446 #endif /* rbus */ 447 448 sc->sc_base_memh = 0; 449 450 /* 451 * MAP socket registers and ExCA registers on memory-space 452 * When no valid address is set on socket base registers (on pci 453 * config space), get it not polite way. 454 */ 455 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 456 457 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 458 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 459 /* The address must be valid. */ 460 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 461 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 462 printf("%s: can't map socket base address 0x%x\n", 463 sc->sc_dev.dv_xname, sock_base); 464 /* 465 * I think it's funny: socket base registers must be 466 * mapped on memory space, but ... 467 */ 468 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 469 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 470 NULL)) { 471 printf("%s: can't map socket base address" 472 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 473 (unsigned long)sockbase); 474 /* give up... allocate reg space via rbus. */ 475 sc->sc_base_memh = 0; 476 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 477 } 478 } else { 479 DPRINTF(("%s: socket base address 0x%lx\n", 480 sc->sc_dev.dv_xname, sockbase)); 481 } 482 } 483 484 sc->sc_mem_start = 0; /* XXX */ 485 sc->sc_mem_end = 0xffffffff; /* XXX */ 486 487 /* 488 * When interrupt isn't routed correctly, give up probing cbb and do 489 * not kill pcic-compatible port. 490 */ 491 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 492 printf("%s: NOT USED because of unconfigured interrupt\n", 493 sc->sc_dev.dv_xname); 494 return; 495 } 496 497 /* 498 * When bus number isn't set correctly, give up using 32-bit CardBus 499 * mode. 500 */ 501 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 502 #if notyet 503 if (((busreg >> 8) & 0xff) == 0) { 504 printf("%s: CardBus support disabled because of unconfigured bus number\n", 505 sc->sc_dev.dv_xname); 506 flags |= PCCBB_PCMCIA_16BITONLY; 507 } 508 #endif 509 510 /* pccbb_machdep.c end */ 511 512 #if defined CBB_DEBUG 513 { 514 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 515 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 516 intrname[pa->pa_intrpin], pa->pa_intrline); 517 } 518 #endif 519 520 /* setup softc */ 521 sc->sc_pc = pc; 522 sc->sc_iot = pa->pa_iot; 523 sc->sc_memt = pa->pa_memt; 524 sc->sc_dmat = pa->pa_dmat; 525 sc->sc_tag = pa->pa_tag; 526 sc->sc_function = pa->pa_function; 527 sc->sc_sockbase = sock_base; 528 sc->sc_busnum = busreg; 529 530 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 531 532 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 533 534 shutdownhook_establish(pccbb_shutdown, sc); 535 536 /* Disable legacy register mapping. */ 537 switch (sc->sc_chipset) { 538 case CB_RX5C46X: /* fallthrough */ 539 #if 0 540 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 541 case CB_RX5C47X: 542 #endif 543 /* 544 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 545 * cannot be disabled by substituting 0 into PCI_LEGACY 546 * register. Ricoh CardBus bridges have special bits on Bridge 547 * control reg (addr 0x3e on PCI config space). 548 */ 549 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 550 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 551 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 552 break; 553 554 default: 555 /* XXX I don't know proper way to kill legacy I/O. */ 556 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 557 break; 558 } 559 560 config_defer(self, pccbb_pci_callback); 561 } 562 563 564 565 566 /* 567 * static void pccbb_pci_callback(struct device *self) 568 * 569 * The actual attach routine: get memory space for YENTA register 570 * space, setup YENTA register and route interrupt. 571 * 572 * This function should be deferred because this device may obtain 573 * memory space dynamically. This function must avoid obtaining 574 * memory area which has already kept for another device. 575 */ 576 static void 577 pccbb_pci_callback(self) 578 struct device *self; 579 { 580 struct pccbb_softc *sc = (void *)self; 581 pci_chipset_tag_t pc = sc->sc_pc; 582 pci_intr_handle_t ih; 583 const char *intrstr = NULL; 584 bus_addr_t sockbase; 585 struct cbslot_attach_args cba; 586 struct pcmciabus_attach_args paa; 587 struct cardslot_attach_args caa; 588 struct cardslot_softc *csc; 589 590 if (0 == sc->sc_base_memh) { 591 /* The socket registers aren't mapped correctly. */ 592 #if rbus 593 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 594 (sc->sc_chipset == CB_RX5C47X 595 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 596 0, &sockbase, &sc->sc_base_memh)) { 597 return; 598 } 599 sc->sc_base_memt = sc->sc_memt; 600 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 601 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 602 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 603 PCI_SOCKBASE))); 604 #else 605 sc->sc_base_memt = sc->sc_memt; 606 #if !defined CBB_PCI_BASE 607 #define CBB_PCI_BASE 0x20000000 608 #endif 609 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 610 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 611 /* cannot allocate memory space */ 612 return; 613 } 614 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 615 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 616 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 617 sc->sc_tag, PCI_SOCKBASE))); 618 sc->sc_sockbase = sockbase; 619 #endif 620 } 621 622 /* bus bridge initialization */ 623 pccbb_chipinit(sc); 624 625 /* clear data structure for child device interrupt handlers */ 626 sc->sc_pil = NULL; 627 sc->sc_pil_intr_enable = 1; 628 629 /* Map and establish the interrupt. */ 630 if (pci_intr_map(&sc->sc_pa, &ih)) { 631 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 632 return; 633 } 634 intrstr = pci_intr_string(pc, ih); 635 636 /* 637 * XXX pccbbintr should be called under the priority lower 638 * than any other hard interrputs. 639 */ 640 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 641 642 if (sc->sc_ih == NULL) { 643 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 644 if (intrstr != NULL) { 645 printf(" at %s", intrstr); 646 } 647 printf("\n"); 648 return; 649 } 650 651 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 652 powerhook_establish(pccbb_powerhook, sc); 653 654 { 655 u_int32_t sockstat; 656 657 sockstat = bus_space_read_4(sc->sc_base_memt, 658 sc->sc_base_memh, CB_SOCKET_STAT); 659 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 660 sc->sc_flags |= CBB_CARDEXIST; 661 } 662 } 663 664 /* 665 * attach cardbus 666 */ 667 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 668 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 669 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 670 671 /* initialize cbslot_attach */ 672 cba.cba_busname = "cardbus"; 673 cba.cba_iot = sc->sc_iot; 674 cba.cba_memt = sc->sc_memt; 675 cba.cba_dmat = sc->sc_dmat; 676 cba.cba_bus = (busreg >> 8) & 0x0ff; 677 cba.cba_cc = (void *)sc; 678 cba.cba_cf = &pccbb_funcs; 679 cba.cba_intrline = sc->sc_pa.pa_intrline; 680 681 #if rbus 682 cba.cba_rbus_iot = sc->sc_rbus_iot; 683 cba.cba_rbus_memt = sc->sc_rbus_memt; 684 #endif 685 686 cba.cba_cacheline = PCI_CACHELINE(bhlc); 687 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 688 689 if (bootverbose) { 690 printf("%s: cacheline 0x%x lattimer 0x%x\n", 691 sc->sc_dev.dv_xname, cba.cba_cacheline, 692 cba.cba_lattimer); 693 printf("%s: bhlc 0x%x lscp 0x%x\n", 694 sc->sc_dev.dv_xname, bhlc, busreg); 695 } 696 #if defined SHOW_REGS 697 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 698 sc->sc_base_memh); 699 #endif 700 } 701 702 pccbb_pcmcia_attach_setup(sc, &paa); 703 caa.caa_cb_attach = NULL; 704 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 705 caa.caa_cb_attach = &cba; 706 } 707 caa.caa_16_attach = &paa; 708 caa.caa_ph = &sc->sc_pcmcia_h; 709 710 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 711 DPRINTF(("pccbbattach: found cardslot\n")); 712 sc->sc_csc = csc; 713 } 714 715 return; 716 } 717 718 719 720 721 722 /* 723 * static void pccbb_chipinit(struct pccbb_softc *sc) 724 * 725 * This function initialize YENTA chip registers listed below: 726 * 1) PCI command reg, 727 * 2) PCI and CardBus latency timer, 728 * 3) route PCI interrupt, 729 * 4) close all memory and io windows. 730 * 5) turn off bus power. 731 * 6) card detect interrupt on. 732 * 7) clear interrupt 733 */ 734 static void 735 pccbb_chipinit(sc) 736 struct pccbb_softc *sc; 737 { 738 pci_chipset_tag_t pc = sc->sc_pc; 739 pcitag_t tag = sc->sc_tag; 740 bus_space_tag_t bmt = sc->sc_base_memt; 741 bus_space_handle_t bmh = sc->sc_base_memh; 742 pcireg_t reg; 743 744 /* 745 * Set PCI command reg. 746 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 747 */ 748 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 749 /* I believe it is harmless. */ 750 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 751 PCI_COMMAND_MASTER_ENABLE); 752 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 753 754 /* 755 * Set CardBus latency timer. 756 */ 757 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 758 if (PCI_CB_LATENCY(reg) < 0x20) { 759 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 760 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 761 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 762 } 763 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 764 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 765 766 /* 767 * Set PCI latency timer. 768 */ 769 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 770 if (PCI_LATTIMER(reg) < 0x10) { 771 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 772 reg |= (0x10 << PCI_LATTIMER_SHIFT); 773 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 774 } 775 DPRINTF(("PCI latency timer 0x%x (%x)\n", 776 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 777 778 779 /* Route functional interrupts to PCI. */ 780 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 781 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 782 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 783 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 784 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 785 786 switch (sc->sc_chipset) { 787 case CB_TI113X: 788 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 789 /* This bit is shared, but may read as 0 on some chips, so set 790 it explicitly on both functions. */ 791 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 792 /* CSC intr enable */ 793 reg |= PCI113X_CBCTRL_PCI_CSC; 794 /* functional intr prohibit | prohibit ISA routing */ 795 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 796 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 797 break; 798 799 case CB_TI12XX: 800 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 801 reg |= PCI12XX_SYSCTRL_VCCPROT; 802 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 803 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 804 reg |= PCI12XX_CBCTRL_CSC; 805 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 806 break; 807 808 case CB_TOPIC95B: 809 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 810 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 811 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 812 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 813 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 814 sc->sc_dev.dv_xname, reg)); 815 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 816 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 817 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 818 DPRINTF(("0x%x\n", reg)); 819 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 820 break; 821 822 case CB_TOPIC97: 823 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 824 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 825 sc->sc_dev.dv_xname, reg)); 826 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 827 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 828 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 829 reg |= TOPIC97_SLOT_CTRL_PCIINT; 830 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 831 DPRINTF(("0x%x\n", reg)); 832 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 833 /* make sure to assert LV card support bits */ 834 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 835 0x800 + 0x3e, 836 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 837 0x800 + 0x3e) | 0x03); 838 break; 839 } 840 841 /* Close all memory and I/O windows. */ 842 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 843 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 844 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 845 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 846 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 847 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 848 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 849 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 850 851 /* reset 16-bit pcmcia bus */ 852 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 853 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 854 855 /* turn off power */ 856 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 857 858 /* CSC Interrupt: Card detect interrupt on */ 859 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 860 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 861 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 862 /* reset interrupt */ 863 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 864 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 865 } 866 867 868 869 870 /* 871 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 872 * struct pcmciabus_attach_args *paa) 873 * 874 * This function attaches 16-bit PCcard bus. 875 */ 876 STATIC void 877 pccbb_pcmcia_attach_setup(sc, paa) 878 struct pccbb_softc *sc; 879 struct pcmciabus_attach_args *paa; 880 { 881 struct pcic_handle *ph = &sc->sc_pcmcia_h; 882 #if rbus 883 rbus_tag_t rb; 884 #endif 885 886 /* initialize pcmcia part in pccbb_softc */ 887 ph->ph_parent = (struct device *)sc; 888 ph->sock = sc->sc_function; 889 ph->flags = 0; 890 ph->shutdown = 0; 891 ph->ih_irq = sc->sc_pa.pa_intrline; 892 ph->ph_bus_t = sc->sc_base_memt; 893 ph->ph_bus_h = sc->sc_base_memh; 894 ph->ph_read = pccbb_pcmcia_read; 895 ph->ph_write = pccbb_pcmcia_write; 896 sc->sc_pct = &pccbb_pcmcia_funcs; 897 898 /* 899 * We need to do a few things here: 900 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 901 * setting the IRQ numbers to 0. 902 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 903 * routing of CSC interrupts (e.g. card removal) to PCI while in 904 * PCMCIA mode. We just leave this set all the time. 905 * 3) Enable card insertion/removal interrupts in case the chip also 906 * needs that while in PCMCIA mode. 907 * 4) Clear any pending CSC interrupt. 908 */ 909 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 910 if (sc->sc_chipset == CB_TI113X) { 911 Pcic_write(ph, PCIC_CSC_INTR, 0); 912 } else { 913 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 914 Pcic_read(ph, PCIC_CSC); 915 } 916 917 /* initialize pcmcia bus attachment */ 918 paa->paa_busname = "pcmcia"; 919 paa->pct = sc->sc_pct; 920 paa->pch = ph; 921 paa->iobase = 0; /* I don't use them */ 922 paa->iosize = 0; 923 #if rbus 924 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 925 paa->iobase = rb->rb_start + rb->rb_offset; 926 paa->iosize = rb->rb_end - rb->rb_start; 927 #endif 928 929 return; 930 } 931 932 #if 0 933 STATIC void 934 pccbb_pcmcia_attach_card(ph) 935 struct pcic_handle *ph; 936 { 937 if (ph->flags & PCIC_FLAG_CARDP) { 938 panic("pccbb_pcmcia_attach_card: already attached"); 939 } 940 941 /* call the MI attach function */ 942 pcmcia_card_attach(ph->pcmcia); 943 944 ph->flags |= PCIC_FLAG_CARDP; 945 } 946 947 STATIC void 948 pccbb_pcmcia_detach_card(ph, flags) 949 struct pcic_handle *ph; 950 int flags; 951 { 952 if (!(ph->flags & PCIC_FLAG_CARDP)) { 953 panic("pccbb_pcmcia_detach_card: already detached"); 954 } 955 956 ph->flags &= ~PCIC_FLAG_CARDP; 957 958 /* call the MI detach function */ 959 pcmcia_card_detach(ph->pcmcia, flags); 960 } 961 #endif 962 963 /* 964 * int pccbbintr(arg) 965 * void *arg; 966 * This routine handles the interrupt from Yenta PCI-CardBus bridge 967 * itself. 968 */ 969 int 970 pccbbintr(arg) 971 void *arg; 972 { 973 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 974 u_int32_t sockevent, sockstate; 975 bus_space_tag_t memt = sc->sc_base_memt; 976 bus_space_handle_t memh = sc->sc_base_memh; 977 struct pcic_handle *ph = &sc->sc_pcmcia_h; 978 979 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 980 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 981 Pcic_read(ph, PCIC_CSC); 982 983 if (sockevent == 0) { 984 /* This intr is not for me: it may be for my child devices. */ 985 if (sc->sc_pil_intr_enable) { 986 return pccbbintr_function(sc); 987 } else { 988 return 0; 989 } 990 } 991 992 if (sockevent & CB_SOCKET_EVENT_CD) { 993 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 994 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 995 /* A card should be removed. */ 996 if (sc->sc_flags & CBB_CARDEXIST) { 997 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 998 sockevent)); 999 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1000 sc->sc_flags &= ~CBB_CARDEXIST; 1001 if (sc->sc_csc->sc_status & 1002 CARDSLOT_STATUS_CARD_16) { 1003 #if 0 1004 struct pcic_handle *ph = 1005 &sc->sc_pcmcia_h; 1006 1007 pcmcia_card_deactivate(ph->pcmcia); 1008 pccbb_pcmcia_socket_disable(ph); 1009 pccbb_pcmcia_detach_card(ph, 1010 DETACH_FORCE); 1011 #endif 1012 cardslot_event_throw(sc->sc_csc, 1013 CARDSLOT_EVENT_REMOVAL_16); 1014 } else if (sc->sc_csc->sc_status & 1015 CARDSLOT_STATUS_CARD_CB) { 1016 /* Cardbus intr removed */ 1017 cardslot_event_throw(sc->sc_csc, 1018 CARDSLOT_EVENT_REMOVAL_CB); 1019 } 1020 } 1021 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1022 /* 1023 * The pccbbintr may called from powerdown hook when 1024 * the system resumed, to detect the card 1025 * insertion/removal during suspension. 1026 */ 1027 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1028 if (sc->sc_flags & CBB_INSERTING) { 1029 callout_stop(&sc->sc_insert_ch); 1030 } 1031 callout_reset(&sc->sc_insert_ch, hz / 10, 1032 pci113x_insert, sc); 1033 sc->sc_flags |= CBB_INSERTING; 1034 } 1035 } 1036 1037 return (1); 1038 } 1039 1040 /* 1041 * static int pccbbintr_function(struct pccbb_softc *sc) 1042 * 1043 * This function calls each interrupt handler registered at the 1044 * bridge. The interrupt handlers are called in registered order. 1045 */ 1046 static int 1047 pccbbintr_function(sc) 1048 struct pccbb_softc *sc; 1049 { 1050 int retval = 0, val; 1051 struct pccbb_intrhand_list *pil; 1052 int s, splchanged; 1053 1054 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1055 /* 1056 * XXX priority change. gross. I use if-else 1057 * sentense instead of switch-case sentense because of 1058 * avoiding duplicate case value error. More than one 1059 * IPL_XXX use same value. It depends on 1060 * implimentation. 1061 */ 1062 splchanged = 1; 1063 if (pil->pil_level == IPL_SERIAL) { 1064 s = splserial(); 1065 } else if (pil->pil_level == IPL_HIGH) { 1066 s = splhigh(); 1067 } else if (pil->pil_level == IPL_CLOCK) { 1068 s = splclock(); 1069 } else if (pil->pil_level == IPL_AUDIO) { 1070 s = splaudio(); 1071 } else if (pil->pil_level == IPL_IMP) { 1072 s = splvm(); /* XXX */ 1073 } else if (pil->pil_level == IPL_TTY) { 1074 s = spltty(); 1075 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1076 s = splsoftserial(); 1077 } else if (pil->pil_level == IPL_NET) { 1078 s = splnet(); 1079 } else { 1080 splchanged = 0; 1081 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1082 } 1083 1084 val = (*pil->pil_func)(pil->pil_arg); 1085 1086 if (splchanged != 0) { 1087 splx(s); 1088 } 1089 1090 retval = retval == 1 ? 1 : 1091 retval == 0 ? val : val != 0 ? val : retval; 1092 } 1093 1094 return retval; 1095 } 1096 1097 static void 1098 pci113x_insert(arg) 1099 void *arg; 1100 { 1101 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1102 u_int32_t sockevent, sockstate; 1103 1104 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1105 CB_SOCKET_EVENT); 1106 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1107 CB_SOCKET_STAT); 1108 1109 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1110 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1111 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1112 sc->sc_flags |= CBB_CARDEXIST; 1113 /* call pccard interrupt handler here */ 1114 if (sockstate & CB_SOCKET_STAT_16BIT) { 1115 /* 16-bit card found */ 1116 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1117 cardslot_event_throw(sc->sc_csc, 1118 CARDSLOT_EVENT_INSERTION_16); 1119 } else if (sockstate & CB_SOCKET_STAT_CB) { 1120 /* cardbus card found */ 1121 /* cardbus_attach_card(sc->sc_csc); */ 1122 cardslot_event_throw(sc->sc_csc, 1123 CARDSLOT_EVENT_INSERTION_CB); 1124 } else { 1125 /* who are you? */ 1126 } 1127 } else { 1128 callout_reset(&sc->sc_insert_ch, hz / 10, 1129 pci113x_insert, sc); 1130 } 1131 } 1132 1133 #define PCCBB_PCMCIA_OFFSET 0x800 1134 static u_int8_t 1135 pccbb_pcmcia_read(ph, reg) 1136 struct pcic_handle *ph; 1137 int reg; 1138 { 1139 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1140 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1141 1142 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1143 PCCBB_PCMCIA_OFFSET + reg); 1144 } 1145 1146 static void 1147 pccbb_pcmcia_write(ph, reg, val) 1148 struct pcic_handle *ph; 1149 int reg; 1150 u_int8_t val; 1151 { 1152 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1153 val); 1154 1155 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1156 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1157 } 1158 1159 /* 1160 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1161 */ 1162 STATIC int 1163 pccbb_ctrl(ct, command) 1164 cardbus_chipset_tag_t ct; 1165 int command; 1166 { 1167 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1168 1169 switch (command) { 1170 case CARDBUS_CD: 1171 if (2 == pccbb_detect_card(sc)) { 1172 int retval = 0; 1173 int status = cb_detect_voltage(sc); 1174 if (PCCARD_VCC_5V & status) { 1175 retval |= CARDBUS_5V_CARD; 1176 } 1177 if (PCCARD_VCC_3V & status) { 1178 retval |= CARDBUS_3V_CARD; 1179 } 1180 if (PCCARD_VCC_XV & status) { 1181 retval |= CARDBUS_XV_CARD; 1182 } 1183 if (PCCARD_VCC_YV & status) { 1184 retval |= CARDBUS_YV_CARD; 1185 } 1186 return retval; 1187 } else { 1188 return 0; 1189 } 1190 break; 1191 case CARDBUS_RESET: 1192 return cb_reset(sc); 1193 break; 1194 case CARDBUS_IO_ENABLE: /* fallthrough */ 1195 case CARDBUS_IO_DISABLE: /* fallthrough */ 1196 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1197 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1198 case CARDBUS_BM_ENABLE: /* fallthrough */ 1199 case CARDBUS_BM_DISABLE: /* fallthrough */ 1200 /* XXX: I think we don't need to call this function below. */ 1201 return pccbb_cardenable(sc, command); 1202 break; 1203 } 1204 1205 return 0; 1206 } 1207 1208 /* 1209 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1210 * This function returns true when it succeeds and returns false when 1211 * it fails. 1212 */ 1213 STATIC int 1214 pccbb_power(ct, command) 1215 cardbus_chipset_tag_t ct; 1216 int command; 1217 { 1218 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1219 1220 u_int32_t status, sock_ctrl; 1221 bus_space_tag_t memt = sc->sc_base_memt; 1222 bus_space_handle_t memh = sc->sc_base_memh; 1223 1224 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1225 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1226 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1227 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1228 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1229 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1230 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1231 "UNKNOWN", 1232 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1233 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1234 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1235 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1236 "UNKNOWN", command)); 1237 1238 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1239 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1240 1241 switch (command & CARDBUS_VCCMASK) { 1242 case CARDBUS_VCC_UC: 1243 break; 1244 case CARDBUS_VCC_5V: 1245 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1246 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1247 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1248 } else { 1249 printf("%s: BAD voltage request: no 5 V card\n", 1250 sc->sc_dev.dv_xname); 1251 } 1252 break; 1253 case CARDBUS_VCC_3V: 1254 if (CB_SOCKET_STAT_3VCARD & status) { 1255 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1256 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1257 } else { 1258 printf("%s: BAD voltage request: no 3.3 V card\n", 1259 sc->sc_dev.dv_xname); 1260 } 1261 break; 1262 case CARDBUS_VCC_0V: 1263 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1264 break; 1265 default: 1266 return 0; /* power NEVER changed */ 1267 break; 1268 } 1269 1270 switch (command & CARDBUS_VPPMASK) { 1271 case CARDBUS_VPP_UC: 1272 break; 1273 case CARDBUS_VPP_0V: 1274 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1275 break; 1276 case CARDBUS_VPP_VCC: 1277 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1278 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1279 break; 1280 case CARDBUS_VPP_12V: 1281 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1282 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1283 break; 1284 } 1285 1286 #if 0 1287 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1288 #endif 1289 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1290 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1291 1292 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1293 printf 1294 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1295 sc->sc_dev.dv_xname, sock_ctrl, status); 1296 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1297 (command & CARDBUS_VCCMASK) == 1298 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1299 CARDBUS_VCCMASK) == 1300 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1301 CARDBUS_VCCMASK) == 1302 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1303 CARDBUS_VCCMASK) == 1304 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1305 CARDBUS_VCCMASK) == 1306 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1307 CARDBUS_VCCMASK) == 1308 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1309 (command & CARDBUS_VPPMASK) == 1310 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1311 CARDBUS_VPPMASK) == 1312 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1313 CARDBUS_VPPMASK) == 1314 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1315 CARDBUS_VPPMASK) == 1316 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1317 #if 0 1318 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1319 u_int32_t force = 1320 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1321 /* Reset Bad Vcc request */ 1322 force &= ~CB_SOCKET_FORCE_BADVCC; 1323 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1324 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1325 CB_SOCKET_STAT)); 1326 return 1; 1327 } 1328 #endif 1329 return 0; 1330 } 1331 1332 /* 1333 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1334 * time is 20 ms, some PC-Card bridge requires longer duration. 1335 */ 1336 #if 0 /* XXX called on interrupt context */ 1337 DELAY_MS(300, sc); 1338 #else 1339 delay(300 * 1000); 1340 #endif 1341 1342 return 1; /* power changed correctly */ 1343 } 1344 1345 #if defined CB_PCMCIA_POLL 1346 struct cb_poll_str { 1347 void *arg; 1348 int (*func) __P((void *)); 1349 int level; 1350 pccard_chipset_tag_t ct; 1351 int count; 1352 struct callout poll_ch; 1353 }; 1354 1355 static struct cb_poll_str cb_poll[10]; 1356 static int cb_poll_n = 0; 1357 1358 static void cb_pcmcia_poll __P((void *arg)); 1359 1360 static void 1361 cb_pcmcia_poll(arg) 1362 void *arg; 1363 { 1364 struct cb_poll_str *poll = arg; 1365 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1366 struct pccbb_softc *sc = psc->cpc_parent; 1367 int s; 1368 u_int32_t spsr; /* socket present-state reg */ 1369 1370 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1371 switch (poll->level) { 1372 case IPL_NET: 1373 s = splnet(); 1374 break; 1375 case IPL_BIO: 1376 s = splbio(); 1377 break; 1378 case IPL_TTY: /* fallthrough */ 1379 default: 1380 s = spltty(); 1381 break; 1382 } 1383 1384 spsr = 1385 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1386 CB_SOCKET_STAT); 1387 1388 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1389 if (!(spsr & 0x40)) { /* CINT low */ 1390 #else 1391 if (1) { 1392 #endif 1393 if ((*poll->func) (poll->arg) == 1) { 1394 ++poll->count; 1395 printf("intr: reported from poller, 0x%x\n", spsr); 1396 #if defined LEVEL2 1397 } else { 1398 printf("intr: miss! 0x%x\n", spsr); 1399 #endif 1400 } 1401 } 1402 splx(s); 1403 } 1404 #endif /* defined CB_PCMCIA_POLL */ 1405 1406 /* 1407 * static int pccbb_detect_card(struct pccbb_softc *sc) 1408 * return value: 0 if no card exists. 1409 * 1 if 16-bit card exists. 1410 * 2 if cardbus card exists. 1411 */ 1412 static int 1413 pccbb_detect_card(sc) 1414 struct pccbb_softc *sc; 1415 { 1416 bus_space_handle_t base_memh = sc->sc_base_memh; 1417 bus_space_tag_t base_memt = sc->sc_base_memt; 1418 u_int32_t sockstat = 1419 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1420 int retval = 0; 1421 1422 /* CD1 and CD2 asserted */ 1423 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1424 /* card must be present */ 1425 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1426 /* NOTACARD DEASSERTED */ 1427 if (CB_SOCKET_STAT_CB & sockstat) { 1428 /* CardBus mode */ 1429 retval = 2; 1430 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1431 /* 16-bit mode */ 1432 retval = 1; 1433 } 1434 } 1435 } 1436 return retval; 1437 } 1438 1439 /* 1440 * STATIC int cb_reset(struct pccbb_softc *sc) 1441 * This function resets CardBus card. 1442 */ 1443 STATIC int 1444 cb_reset(sc) 1445 struct pccbb_softc *sc; 1446 { 1447 /* 1448 * Reset Assert at least 20 ms 1449 * Some machines request longer duration. 1450 */ 1451 int reset_duration = 1452 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1453 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1454 1455 /* Reset bit Assert (bit 6 at 0x3E) */ 1456 bcr |= CB_BCR_RESET_ENABLE; 1457 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1458 DELAY_MS(reset_duration, sc); 1459 1460 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1461 /* Reset bit Deassert (bit 6 at 0x3E) */ 1462 bcr &= ~CB_BCR_RESET_ENABLE; 1463 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1464 DELAY_MS(reset_duration, sc); 1465 } 1466 /* No card found on the slot. Keep Reset. */ 1467 return 1; 1468 } 1469 1470 /* 1471 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1472 * This function detect card Voltage. 1473 */ 1474 STATIC int 1475 cb_detect_voltage(sc) 1476 struct pccbb_softc *sc; 1477 { 1478 u_int32_t psr; /* socket present-state reg */ 1479 bus_space_tag_t iot = sc->sc_base_memt; 1480 bus_space_handle_t ioh = sc->sc_base_memh; 1481 int vol = PCCARD_VCC_UKN; /* set 0 */ 1482 1483 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1484 1485 if (0x400u & psr) { 1486 vol |= PCCARD_VCC_5V; 1487 } 1488 if (0x800u & psr) { 1489 vol |= PCCARD_VCC_3V; 1490 } 1491 1492 return vol; 1493 } 1494 1495 STATIC int 1496 cbbprint(aux, pcic) 1497 void *aux; 1498 const char *pcic; 1499 { 1500 /* 1501 struct cbslot_attach_args *cba = aux; 1502 1503 if (cba->cba_slot >= 0) { 1504 printf(" slot %d", cba->cba_slot); 1505 } 1506 */ 1507 return UNCONF; 1508 } 1509 1510 /* 1511 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1512 * This function enables and disables the card 1513 */ 1514 STATIC int 1515 pccbb_cardenable(sc, function) 1516 struct pccbb_softc *sc; 1517 int function; 1518 { 1519 u_int32_t command = 1520 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1521 1522 DPRINTF(("pccbb_cardenable:")); 1523 switch (function) { 1524 case CARDBUS_IO_ENABLE: 1525 command |= PCI_COMMAND_IO_ENABLE; 1526 break; 1527 case CARDBUS_IO_DISABLE: 1528 command &= ~PCI_COMMAND_IO_ENABLE; 1529 break; 1530 case CARDBUS_MEM_ENABLE: 1531 command |= PCI_COMMAND_MEM_ENABLE; 1532 break; 1533 case CARDBUS_MEM_DISABLE: 1534 command &= ~PCI_COMMAND_MEM_ENABLE; 1535 break; 1536 case CARDBUS_BM_ENABLE: 1537 command |= PCI_COMMAND_MASTER_ENABLE; 1538 break; 1539 case CARDBUS_BM_DISABLE: 1540 command &= ~PCI_COMMAND_MASTER_ENABLE; 1541 break; 1542 default: 1543 return 0; 1544 } 1545 1546 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1547 DPRINTF((" command reg 0x%x\n", command)); 1548 return 1; 1549 } 1550 1551 #if !rbus 1552 /* 1553 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1554 */ 1555 static int 1556 pccbb_io_open(ct, win, start, end) 1557 cardbus_chipset_tag_t ct; 1558 int win; 1559 u_int32_t start, end; 1560 { 1561 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1562 int basereg; 1563 int limitreg; 1564 1565 if ((win < 0) || (win > 2)) { 1566 #if defined DIAGNOSTIC 1567 printf("cardbus_io_open: window out of range %d\n", win); 1568 #endif 1569 return 0; 1570 } 1571 1572 basereg = win * 8 + 0x2c; 1573 limitreg = win * 8 + 0x30; 1574 1575 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1576 start, basereg, end, limitreg)); 1577 1578 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1579 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1580 return 1; 1581 } 1582 1583 /* 1584 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1585 */ 1586 static int 1587 pccbb_io_close(ct, win) 1588 cardbus_chipset_tag_t ct; 1589 int win; 1590 { 1591 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1592 int basereg; 1593 int limitreg; 1594 1595 if ((win < 0) || (win > 2)) { 1596 #if defined DIAGNOSTIC 1597 printf("cardbus_io_close: window out of range %d\n", win); 1598 #endif 1599 return 0; 1600 } 1601 1602 basereg = win * 8 + 0x2c; 1603 limitreg = win * 8 + 0x30; 1604 1605 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1606 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1607 return 1; 1608 } 1609 1610 /* 1611 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1612 */ 1613 static int 1614 pccbb_mem_open(ct, win, start, end) 1615 cardbus_chipset_tag_t ct; 1616 int win; 1617 u_int32_t start, end; 1618 { 1619 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1620 int basereg; 1621 int limitreg; 1622 1623 if ((win < 0) || (win > 2)) { 1624 #if defined DIAGNOSTIC 1625 printf("cardbus_mem_open: window out of range %d\n", win); 1626 #endif 1627 return 0; 1628 } 1629 1630 basereg = win * 8 + 0x1c; 1631 limitreg = win * 8 + 0x20; 1632 1633 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1634 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1635 return 1; 1636 } 1637 1638 /* 1639 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1640 */ 1641 static int 1642 pccbb_mem_close(ct, win) 1643 cardbus_chipset_tag_t ct; 1644 int win; 1645 { 1646 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1647 int basereg; 1648 int limitreg; 1649 1650 if ((win < 0) || (win > 2)) { 1651 #if defined DIAGNOSTIC 1652 printf("cardbus_mem_close: window out of range %d\n", win); 1653 #endif 1654 return 0; 1655 } 1656 1657 basereg = win * 8 + 0x1c; 1658 limitreg = win * 8 + 0x20; 1659 1660 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1661 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1662 return 1; 1663 } 1664 #endif 1665 1666 /* 1667 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1668 * int irq, 1669 * int level, 1670 * int (* func) __P((void *)), 1671 * void *arg) 1672 * 1673 * This function registers an interrupt handler at the bridge, in 1674 * order not to call the interrupt handlers of child devices when 1675 * a card-deletion interrupt occurs. 1676 * 1677 * The arguments irq and level are not used. 1678 */ 1679 static void * 1680 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1681 cardbus_chipset_tag_t ct; 1682 int irq, level; 1683 int (*func) __P((void *)); 1684 void *arg; 1685 { 1686 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1687 1688 return pccbb_intr_establish(sc, irq, level, func, arg); 1689 } 1690 1691 1692 /* 1693 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1694 * void *ih) 1695 * 1696 * This function removes an interrupt handler pointed by ih. 1697 */ 1698 static void 1699 pccbb_cb_intr_disestablish(ct, ih) 1700 cardbus_chipset_tag_t ct; 1701 void *ih; 1702 { 1703 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1704 1705 pccbb_intr_disestablish(sc, ih); 1706 } 1707 1708 1709 void 1710 pccbb_intr_route(sc) 1711 struct pccbb_softc *sc; 1712 { 1713 pcireg_t reg; 1714 1715 /* initialize bridge intr routing */ 1716 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1717 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1718 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1719 1720 switch (sc->sc_chipset) { 1721 case CB_TI113X: 1722 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1723 /* functional intr enabled */ 1724 reg |= PCI113X_CBCTRL_PCI_INTR; 1725 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1726 break; 1727 default: 1728 break; 1729 } 1730 } 1731 1732 /* 1733 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1734 * int irq, 1735 * int level, 1736 * int (* func) __P((void *)), 1737 * void *arg) 1738 * 1739 * This function registers an interrupt handler at the bridge, in 1740 * order not to call the interrupt handlers of child devices when 1741 * a card-deletion interrupt occurs. 1742 * 1743 * The arguments irq is not used because pccbb selects intr vector. 1744 */ 1745 static void * 1746 pccbb_intr_establish(sc, irq, level, func, arg) 1747 struct pccbb_softc *sc; 1748 int irq, level; 1749 int (*func) __P((void *)); 1750 void *arg; 1751 { 1752 struct pccbb_intrhand_list *pil, *newpil; 1753 1754 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1755 1756 if (sc->sc_pil == NULL) { 1757 pccbb_intr_route(sc); 1758 1759 } 1760 1761 /* 1762 * Allocate a room for interrupt handler structure. 1763 */ 1764 if (NULL == (newpil = 1765 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1766 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1767 return NULL; 1768 } 1769 1770 newpil->pil_func = func; 1771 newpil->pil_arg = arg; 1772 newpil->pil_level = level; 1773 newpil->pil_next = NULL; 1774 1775 if (sc->sc_pil == NULL) { 1776 sc->sc_pil = newpil; 1777 } else { 1778 for (pil = sc->sc_pil; pil->pil_next != NULL; 1779 pil = pil->pil_next); 1780 pil->pil_next = newpil; 1781 } 1782 1783 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1784 1785 return newpil; 1786 } 1787 1788 /* 1789 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1790 * void *ih) 1791 * 1792 * This function removes an interrupt handler pointed by ih. 1793 */ 1794 static void 1795 pccbb_intr_disestablish(sc, ih) 1796 struct pccbb_softc *sc; 1797 void *ih; 1798 { 1799 struct pccbb_intrhand_list *pil, **pil_prev; 1800 pcireg_t reg; 1801 1802 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1803 1804 pil_prev = &sc->sc_pil; 1805 1806 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1807 if (pil == ih) { 1808 *pil_prev = pil->pil_next; 1809 free(pil, M_DEVBUF); 1810 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1811 break; 1812 } 1813 pil_prev = &pil->pil_next; 1814 } 1815 1816 if (sc->sc_pil == NULL) { 1817 /* No interrupt handlers */ 1818 1819 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1820 1821 /* stop routing PCI intr */ 1822 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1823 reg |= CB_BCR_INTR_IREQ_ENABLE; 1824 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1825 1826 switch (sc->sc_chipset) { 1827 case CB_TI113X: 1828 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1829 /* functional intr disabled */ 1830 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1831 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1832 break; 1833 default: 1834 break; 1835 } 1836 } 1837 } 1838 1839 #if defined SHOW_REGS 1840 static void 1841 cb_show_regs(pc, tag, memt, memh) 1842 pci_chipset_tag_t pc; 1843 pcitag_t tag; 1844 bus_space_tag_t memt; 1845 bus_space_handle_t memh; 1846 { 1847 int i; 1848 printf("PCI config regs:"); 1849 for (i = 0; i < 0x50; i += 4) { 1850 if (i % 16 == 0) { 1851 printf("\n 0x%02x:", i); 1852 } 1853 printf(" %08x", pci_conf_read(pc, tag, i)); 1854 } 1855 for (i = 0x80; i < 0xb0; i += 4) { 1856 if (i % 16 == 0) { 1857 printf("\n 0x%02x:", i); 1858 } 1859 printf(" %08x", pci_conf_read(pc, tag, i)); 1860 } 1861 1862 if (memh == 0) { 1863 printf("\n"); 1864 return; 1865 } 1866 1867 printf("\nsocket regs:"); 1868 for (i = 0; i <= 0x10; i += 0x04) { 1869 printf(" %08x", bus_space_read_4(memt, memh, i)); 1870 } 1871 printf("\nExCA regs:"); 1872 for (i = 0; i < 0x08; ++i) { 1873 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1874 } 1875 printf("\n"); 1876 return; 1877 } 1878 #endif 1879 1880 /* 1881 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1882 * int busno, int devno, int function) 1883 * This is the function to make a tag to access config space of 1884 * a CardBus Card. It works same as pci_conf_read. 1885 */ 1886 static cardbustag_t 1887 pccbb_make_tag(cc, busno, devno, function) 1888 cardbus_chipset_tag_t cc; 1889 int busno, devno, function; 1890 { 1891 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1892 1893 return pci_make_tag(sc->sc_pc, busno, devno, function); 1894 } 1895 1896 static void 1897 pccbb_free_tag(cc, tag) 1898 cardbus_chipset_tag_t cc; 1899 cardbustag_t tag; 1900 { 1901 } 1902 1903 /* 1904 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1905 * cardbustag_t tag, int offset) 1906 * This is the function to read the config space of a CardBus Card. 1907 * It works same as pci_conf_read. 1908 */ 1909 static cardbusreg_t 1910 pccbb_conf_read(cc, tag, offset) 1911 cardbus_chipset_tag_t cc; 1912 cardbustag_t tag; 1913 int offset; /* register offset */ 1914 { 1915 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1916 1917 return pci_conf_read(sc->sc_pc, tag, offset); 1918 } 1919 1920 /* 1921 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1922 * int offs, cardbusreg_t val) 1923 * This is the function to write the config space of a CardBus Card. 1924 * It works same as pci_conf_write. 1925 */ 1926 static void 1927 pccbb_conf_write(cc, tag, reg, val) 1928 cardbus_chipset_tag_t cc; 1929 cardbustag_t tag; 1930 int reg; /* register offset */ 1931 cardbusreg_t val; 1932 { 1933 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1934 1935 pci_conf_write(sc->sc_pc, tag, reg, val); 1936 } 1937 1938 #if 0 1939 STATIC int 1940 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1941 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1942 int speed, int flags, 1943 bus_space_handle_t * iohp) 1944 #endif 1945 /* 1946 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1947 * bus_addr_t start, bus_size_t size, 1948 * bus_size_t align, 1949 * struct pcmcia_io_handle *pcihp 1950 * 1951 * This function only allocates I/O region for pccard. This function 1952 * never maps the allocated region to pccard I/O area. 1953 * 1954 * XXX: The interface of this function is not very good, I believe. 1955 */ 1956 STATIC int 1957 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1958 pcmcia_chipset_handle_t pch; 1959 bus_addr_t start; /* start address */ 1960 bus_size_t size; 1961 bus_size_t align; 1962 struct pcmcia_io_handle *pcihp; 1963 { 1964 struct pcic_handle *ph = (struct pcic_handle *)pch; 1965 bus_addr_t ioaddr; 1966 int flags = 0; 1967 bus_space_tag_t iot; 1968 bus_space_handle_t ioh; 1969 bus_addr_t mask; 1970 #if rbus 1971 rbus_tag_t rb; 1972 #endif 1973 if (align == 0) { 1974 align = size; /* XXX: funny??? */ 1975 } 1976 1977 if (start != 0) { 1978 /* XXX: assume all card decode lower 10 bits by its hardware */ 1979 mask = 0x3ff; 1980 } else { 1981 /* 1982 * calculate mask: 1983 * 1. get the most significant bit of size (call it msb). 1984 * 2. compare msb with the value of size. 1985 * 3. if size is larger, shift msb left once. 1986 * 4. obtain mask value to decrement msb. 1987 */ 1988 bus_size_t size_tmp = size; 1989 int shifts = 0; 1990 1991 mask = 1; 1992 while (size_tmp) { 1993 ++shifts; 1994 size_tmp >>= 1; 1995 } 1996 mask = (1 << shifts); 1997 if (mask < size) { 1998 mask <<= 1; 1999 } 2000 --mask; 2001 } 2002 2003 /* 2004 * Allocate some arbitrary I/O space. 2005 */ 2006 2007 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2008 2009 #if rbus 2010 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2011 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2012 return 1; 2013 } 2014 #else 2015 if (start) { 2016 ioaddr = start; 2017 if (bus_space_map(iot, start, size, 0, &ioh)) { 2018 return 1; 2019 } 2020 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2021 (u_long) ioaddr, (u_long) size)); 2022 } else { 2023 flags |= PCMCIA_IO_ALLOCATED; 2024 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2025 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2026 size, align, 0, 0, &ioaddr, &ioh)) { 2027 /* No room be able to be get. */ 2028 return 1; 2029 } 2030 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2031 (u_long) ioaddr, (u_long) size)); 2032 } 2033 #endif 2034 2035 pcihp->iot = iot; 2036 pcihp->ioh = ioh; 2037 pcihp->addr = ioaddr; 2038 pcihp->size = size; 2039 pcihp->flags = flags; 2040 2041 return 0; 2042 } 2043 2044 /* 2045 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2046 * struct pcmcia_io_handle *pcihp) 2047 * 2048 * This function only frees I/O region for pccard. 2049 * 2050 * XXX: The interface of this function is not very good, I believe. 2051 */ 2052 void 2053 pccbb_pcmcia_io_free(pch, pcihp) 2054 pcmcia_chipset_handle_t pch; 2055 struct pcmcia_io_handle *pcihp; 2056 { 2057 #if !rbus 2058 bus_space_tag_t iot = pcihp->iot; 2059 #endif 2060 bus_space_handle_t ioh = pcihp->ioh; 2061 bus_size_t size = pcihp->size; 2062 2063 #if rbus 2064 struct pccbb_softc *sc = 2065 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2066 rbus_tag_t rb = sc->sc_rbus_iot; 2067 2068 rbus_space_free(rb, ioh, size, NULL); 2069 #else 2070 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2071 bus_space_free(iot, ioh, size); 2072 else 2073 bus_space_unmap(iot, ioh, size); 2074 #endif 2075 } 2076 2077 /* 2078 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2079 * bus_addr_t offset, bus_size_t size, 2080 * struct pcmcia_io_handle *pcihp, 2081 * int *windowp) 2082 * 2083 * This function maps the allocated I/O region to pccard. This function 2084 * never allocates any I/O region for pccard I/O area. I don't 2085 * understand why the original authors of pcmciabus separated alloc and 2086 * map. I believe the two must be unite. 2087 * 2088 * XXX: no wait timing control? 2089 */ 2090 int 2091 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2092 pcmcia_chipset_handle_t pch; 2093 int width; 2094 bus_addr_t offset; 2095 bus_size_t size; 2096 struct pcmcia_io_handle *pcihp; 2097 int *windowp; 2098 { 2099 struct pcic_handle *ph = (struct pcic_handle *)pch; 2100 bus_addr_t ioaddr = pcihp->addr + offset; 2101 int i, win; 2102 #if defined CBB_DEBUG 2103 static char *width_names[] = { "dynamic", "io8", "io16" }; 2104 #endif 2105 2106 /* Sanity check I/O handle. */ 2107 2108 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2109 panic("pccbb_pcmcia_io_map iot is bogus"); 2110 } 2111 2112 /* XXX Sanity check offset/size. */ 2113 2114 win = -1; 2115 for (i = 0; i < PCIC_IO_WINS; i++) { 2116 if ((ph->ioalloc & (1 << i)) == 0) { 2117 win = i; 2118 ph->ioalloc |= (1 << i); 2119 break; 2120 } 2121 } 2122 2123 if (win == -1) { 2124 return 1; 2125 } 2126 2127 *windowp = win; 2128 2129 /* XXX this is pretty gross */ 2130 2131 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2132 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2133 2134 /* XXX wtf is this doing here? */ 2135 2136 #if 0 2137 printf(" port 0x%lx", (u_long) ioaddr); 2138 if (size > 1) { 2139 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2140 } 2141 #endif 2142 2143 ph->io[win].addr = ioaddr; 2144 ph->io[win].size = size; 2145 ph->io[win].width = width; 2146 2147 /* actual dirty register-value changing in the function below. */ 2148 pccbb_pcmcia_do_io_map(ph, win); 2149 2150 return 0; 2151 } 2152 2153 /* 2154 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2155 * 2156 * This function changes register-value to map I/O region for pccard. 2157 */ 2158 static void 2159 pccbb_pcmcia_do_io_map(ph, win) 2160 struct pcic_handle *ph; 2161 int win; 2162 { 2163 static u_int8_t pcic_iowidth[3] = { 2164 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2165 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2166 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2167 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2168 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2169 }; 2170 2171 #define PCIC_SIA_START_LOW 0 2172 #define PCIC_SIA_START_HIGH 1 2173 #define PCIC_SIA_STOP_LOW 2 2174 #define PCIC_SIA_STOP_HIGH 3 2175 2176 int regbase_win = 0x8 + win * 0x04; 2177 u_int8_t ioctl, enable; 2178 2179 DPRINTF( 2180 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2181 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2182 ph->io[win].width * 8)); 2183 2184 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2185 ph->io[win].addr & 0xff); 2186 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2187 (ph->io[win].addr >> 8) & 0xff); 2188 2189 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2190 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2191 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2192 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2193 2194 ioctl = Pcic_read(ph, PCIC_IOCTL); 2195 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2196 switch (win) { 2197 case 0: 2198 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2199 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2200 PCIC_IOCTL_IO0_DATASIZE_MASK); 2201 ioctl |= pcic_iowidth[ph->io[win].width]; 2202 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2203 break; 2204 case 1: 2205 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2206 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2207 PCIC_IOCTL_IO1_DATASIZE_MASK); 2208 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2209 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2210 break; 2211 } 2212 Pcic_write(ph, PCIC_IOCTL, ioctl); 2213 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2214 #if defined CBB_DEBUG 2215 { 2216 u_int8_t start_low = 2217 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2218 u_int8_t start_high = 2219 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2220 u_int8_t stop_low = 2221 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2222 u_int8_t stop_high = 2223 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2224 printf 2225 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2226 start_low, start_high, stop_low, stop_high, ioctl, enable); 2227 } 2228 #endif 2229 } 2230 2231 /* 2232 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2233 * 2234 * This function unmaps I/O region. No return value. 2235 */ 2236 STATIC void 2237 pccbb_pcmcia_io_unmap(pch, win) 2238 pcmcia_chipset_handle_t pch; 2239 int win; 2240 { 2241 struct pcic_handle *ph = (struct pcic_handle *)pch; 2242 int reg; 2243 2244 if (win >= PCIC_IO_WINS || win < 0) { 2245 panic("pccbb_pcmcia_io_unmap: window out of range"); 2246 } 2247 2248 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2249 switch (win) { 2250 case 0: 2251 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2252 break; 2253 case 1: 2254 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2255 break; 2256 } 2257 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2258 2259 ph->ioalloc &= ~(1 << win); 2260 } 2261 2262 /* 2263 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2264 * 2265 * This function enables the card. All information is stored in 2266 * the first argument, pcmcia_chipset_handle_t. 2267 */ 2268 static void 2269 pccbb_pcmcia_wait_ready(ph) 2270 struct pcic_handle *ph; 2271 { 2272 int i; 2273 2274 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2275 Pcic_read(ph, PCIC_IF_STATUS))); 2276 2277 for (i = 0; i < 2000; i++) { 2278 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2279 return; 2280 } 2281 DELAY_MS(2, ph->ph_parent); 2282 #ifdef CBB_DEBUG 2283 if ((i > 1000) && (i % 25 == 24)) 2284 printf("."); 2285 #endif 2286 } 2287 2288 #ifdef DIAGNOSTIC 2289 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2290 Pcic_read(ph, PCIC_IF_STATUS)); 2291 #endif 2292 } 2293 2294 /* 2295 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2296 * 2297 * This function enables the card. All information is stored in 2298 * the first argument, pcmcia_chipset_handle_t. 2299 */ 2300 STATIC void 2301 pccbb_pcmcia_socket_enable(pch) 2302 pcmcia_chipset_handle_t pch; 2303 { 2304 struct pcic_handle *ph = (struct pcic_handle *)pch; 2305 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2306 int cardtype, win; 2307 u_int8_t power, intr; 2308 pcireg_t spsr; 2309 int voltage; 2310 2311 /* this bit is mostly stolen from pcic_attach_card */ 2312 2313 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2314 2315 /* get card Vcc info */ 2316 2317 spsr = 2318 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2319 CB_SOCKET_STAT); 2320 if (spsr & CB_SOCKET_STAT_5VCARD) { 2321 DPRINTF(("5V card\n")); 2322 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2323 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2324 DPRINTF(("3V card\n")); 2325 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2326 } else { 2327 printf("?V card, 0x%x\n", spsr); /* XXX */ 2328 return; 2329 } 2330 2331 /* disable socket: negate output enable bit and power off */ 2332 2333 power = 0; 2334 Pcic_write(ph, PCIC_PWRCTL, power); 2335 2336 /* power down the socket to reset it, clear the card reset pin */ 2337 2338 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2339 2340 /* 2341 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2342 * we are changing Vcc (Toff). 2343 */ 2344 /* delay(300*1000); too much */ 2345 2346 /* assert reset bit */ 2347 intr = Pcic_read(ph, PCIC_INTR); 2348 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2349 Pcic_write(ph, PCIC_INTR, intr); 2350 2351 /* power up the socket and output enable */ 2352 power = Pcic_read(ph, PCIC_PWRCTL); 2353 power |= PCIC_PWRCTL_OE; 2354 Pcic_write(ph, PCIC_PWRCTL, power); 2355 pccbb_power(sc, voltage); 2356 2357 /* 2358 * hold RESET at least 20 ms: the spec says only 10 us is 2359 * enough, but TI1130 requires at least 20 ms. 2360 */ 2361 #if 0 /* XXX called on interrupt context */ 2362 DELAY_MS(20, sc); 2363 #else 2364 delay(20 * 1000); 2365 #endif 2366 2367 /* clear the reset flag */ 2368 2369 intr |= PCIC_INTR_RESET; 2370 Pcic_write(ph, PCIC_INTR, intr); 2371 2372 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2373 2374 #if 0 /* XXX called on interrupt context */ 2375 DELAY_MS(20, sc); 2376 #else 2377 delay(20 * 1000); 2378 #endif 2379 2380 /* wait for the chip to finish initializing */ 2381 2382 pccbb_pcmcia_wait_ready(ph); 2383 2384 /* zero out the address windows */ 2385 2386 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2387 2388 /* set the card type */ 2389 2390 cardtype = pcmcia_card_gettype(ph->pcmcia); 2391 2392 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2393 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2394 Pcic_write(ph, PCIC_INTR, intr); 2395 2396 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2397 ph->ph_parent->dv_xname, ph->sock, 2398 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2399 2400 /* reinstall all the memory and io mappings */ 2401 2402 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2403 if (ph->memalloc & (1 << win)) { 2404 pccbb_pcmcia_do_mem_map(ph, win); 2405 } 2406 } 2407 2408 for (win = 0; win < PCIC_IO_WINS; ++win) { 2409 if (ph->ioalloc & (1 << win)) { 2410 pccbb_pcmcia_do_io_map(ph, win); 2411 } 2412 } 2413 } 2414 2415 /* 2416 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2417 * 2418 * This function disables the card. All information is stored in 2419 * the first argument, pcmcia_chipset_handle_t. 2420 */ 2421 STATIC void 2422 pccbb_pcmcia_socket_disable(pch) 2423 pcmcia_chipset_handle_t pch; 2424 { 2425 struct pcic_handle *ph = (struct pcic_handle *)pch; 2426 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2427 u_int8_t power, intr; 2428 2429 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2430 2431 /* reset signal asserting... */ 2432 2433 intr = Pcic_read(ph, PCIC_INTR); 2434 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2435 Pcic_write(ph, PCIC_INTR, intr); 2436 delay(2 * 1000); 2437 2438 /* power down the socket */ 2439 power = Pcic_read(ph, PCIC_PWRCTL); 2440 power &= ~PCIC_PWRCTL_OE; 2441 Pcic_write(ph, PCIC_PWRCTL, power); 2442 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2443 /* 2444 * wait 300ms until power fails (Tpf). 2445 */ 2446 #if 0 /* XXX called on interrupt context */ 2447 DELAY_MS(300, sc); 2448 #else 2449 delay(300 * 1000); 2450 #endif 2451 } 2452 2453 /* 2454 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2455 * 2456 * This function detects whether a card is in the slot or not. 2457 * If a card is inserted, return 1. Otherwise, return 0. 2458 */ 2459 STATIC int 2460 pccbb_pcmcia_card_detect(pch) 2461 pcmcia_chipset_handle_t pch; 2462 { 2463 struct pcic_handle *ph = (struct pcic_handle *)pch; 2464 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2465 2466 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2467 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2468 } 2469 2470 #if 0 2471 STATIC int 2472 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2473 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2474 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2475 #endif 2476 /* 2477 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2478 * bus_size_t size, 2479 * struct pcmcia_mem_handle *pcmhp) 2480 * 2481 * This function only allocates memory region for pccard. This 2482 * function never maps the allocated region to pccard memory area. 2483 * 2484 * XXX: Why the argument of start address is not in? 2485 */ 2486 STATIC int 2487 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2488 pcmcia_chipset_handle_t pch; 2489 bus_size_t size; 2490 struct pcmcia_mem_handle *pcmhp; 2491 { 2492 struct pcic_handle *ph = (struct pcic_handle *)pch; 2493 bus_space_handle_t memh; 2494 bus_addr_t addr; 2495 bus_size_t sizepg; 2496 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2497 #if rbus 2498 rbus_tag_t rb; 2499 #endif 2500 2501 /* out of sc->memh, allocate as many pages as necessary */ 2502 2503 /* convert size to PCIC pages */ 2504 /* 2505 * This is not enough; when the requested region is on the page 2506 * boundaries, this may calculate wrong result. 2507 */ 2508 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2509 #if 0 2510 if (sizepg > PCIC_MAX_MEM_PAGES) { 2511 return 1; 2512 } 2513 #endif 2514 2515 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2516 return 1; 2517 } 2518 2519 addr = 0; /* XXX gcc -Wuninitialized */ 2520 2521 #if rbus 2522 rb = sc->sc_rbus_memt; 2523 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2524 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2525 &addr, &memh)) { 2526 return 1; 2527 } 2528 #else 2529 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2530 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2531 0, /* boundary */ 2532 0, /* flags */ 2533 &addr, &memh)) { 2534 return 1; 2535 } 2536 #endif 2537 2538 DPRINTF( 2539 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2540 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2541 2542 pcmhp->memt = sc->sc_memt; 2543 pcmhp->memh = memh; 2544 pcmhp->addr = addr; 2545 pcmhp->size = size; 2546 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2547 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2548 pcmhp->mhandle = 0; 2549 /* No offset??? Funny. */ 2550 2551 return 0; 2552 } 2553 2554 /* 2555 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2556 * struct pcmcia_mem_handle *pcmhp) 2557 * 2558 * This function release the memory space allocated by the function 2559 * pccbb_pcmcia_mem_alloc(). 2560 */ 2561 STATIC void 2562 pccbb_pcmcia_mem_free(pch, pcmhp) 2563 pcmcia_chipset_handle_t pch; 2564 struct pcmcia_mem_handle *pcmhp; 2565 { 2566 #if rbus 2567 struct pcic_handle *ph = (struct pcic_handle *)pch; 2568 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2569 2570 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2571 #else 2572 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2573 #endif 2574 } 2575 2576 /* 2577 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2578 * 2579 * This function release the memory space allocated by the function 2580 * pccbb_pcmcia_mem_alloc(). 2581 */ 2582 STATIC void 2583 pccbb_pcmcia_do_mem_map(ph, win) 2584 struct pcic_handle *ph; 2585 int win; 2586 { 2587 int regbase_win; 2588 bus_addr_t phys_addr; 2589 bus_addr_t phys_end; 2590 2591 #define PCIC_SMM_START_LOW 0 2592 #define PCIC_SMM_START_HIGH 1 2593 #define PCIC_SMM_STOP_LOW 2 2594 #define PCIC_SMM_STOP_HIGH 3 2595 #define PCIC_CMA_LOW 4 2596 #define PCIC_CMA_HIGH 5 2597 2598 u_int8_t start_low, start_high = 0; 2599 u_int8_t stop_low, stop_high; 2600 u_int8_t off_low, off_high; 2601 u_int8_t mem_window; 2602 int reg; 2603 2604 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2605 int mem8 = 2606 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2607 || (kind == PCMCIA_MEM_ATTR); 2608 2609 regbase_win = 0x10 + win * 0x08; 2610 2611 phys_addr = ph->mem[win].addr; 2612 phys_end = phys_addr + ph->mem[win].size; 2613 2614 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2615 phys_addr, phys_end, ph->mem[win].offset)); 2616 2617 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2618 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2619 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2620 2621 /* bit 19:12 */ 2622 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2623 /* bit 23:20 and bit 7 on */ 2624 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2625 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2626 /* bit 31:24, for 32-bit address */ 2627 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2628 2629 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2630 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2631 2632 if (((struct pccbb_softc *)ph-> 2633 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2634 Pcic_write(ph, 0x40 + win, mem_window); 2635 } 2636 2637 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2638 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2639 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2640 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2641 2642 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2643 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2644 2645 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2646 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2647 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2648 | ((kind == PCMCIA_MEM_ATTR) ? 2649 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2650 2651 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2652 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2653 2654 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2655 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2656 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2657 2658 #if defined CBB_DEBUG 2659 { 2660 int r1, r2, r3, r4, r5, r6, r7 = 0; 2661 2662 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2663 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2664 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2665 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2666 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2667 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2668 if (((struct pccbb_softc *)(ph-> 2669 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2670 r7 = Pcic_read(ph, 0x40 + win); 2671 } 2672 2673 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2674 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2675 if (((struct pccbb_softc *)(ph-> 2676 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2677 DPRINTF((" %02x", r7)); 2678 } 2679 DPRINTF(("\n")); 2680 } 2681 #endif 2682 } 2683 2684 /* 2685 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2686 * bus_addr_t card_addr, bus_size_t size, 2687 * struct pcmcia_mem_handle *pcmhp, 2688 * bus_addr_t *offsetp, int *windowp) 2689 * 2690 * This function maps memory space allocated by the function 2691 * pccbb_pcmcia_mem_alloc(). 2692 */ 2693 STATIC int 2694 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2695 pcmcia_chipset_handle_t pch; 2696 int kind; 2697 bus_addr_t card_addr; 2698 bus_size_t size; 2699 struct pcmcia_mem_handle *pcmhp; 2700 bus_addr_t *offsetp; 2701 int *windowp; 2702 { 2703 struct pcic_handle *ph = (struct pcic_handle *)pch; 2704 bus_addr_t busaddr; 2705 long card_offset; 2706 int win; 2707 2708 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2709 if ((ph->memalloc & (1 << win)) == 0) { 2710 ph->memalloc |= (1 << win); 2711 break; 2712 } 2713 } 2714 2715 if (win == PCIC_MEM_WINS) { 2716 return 1; 2717 } 2718 2719 *windowp = win; 2720 2721 /* XXX this is pretty gross */ 2722 2723 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2724 panic("pccbb_pcmcia_mem_map memt is bogus"); 2725 } 2726 2727 busaddr = pcmhp->addr; 2728 2729 /* 2730 * compute the address offset to the pcmcia address space for the 2731 * pcic. this is intentionally signed. The masks and shifts below 2732 * will cause TRT to happen in the pcic registers. Deal with making 2733 * sure the address is aligned, and return the alignment offset. 2734 */ 2735 2736 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2737 card_addr -= *offsetp; 2738 2739 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2740 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2741 (u_long) card_addr)); 2742 2743 /* 2744 * include the offset in the size, and decrement size by one, since 2745 * the hw wants start/stop 2746 */ 2747 size += *offsetp - 1; 2748 2749 card_offset = (((long)card_addr) - ((long)busaddr)); 2750 2751 ph->mem[win].addr = busaddr; 2752 ph->mem[win].size = size; 2753 ph->mem[win].offset = card_offset; 2754 ph->mem[win].kind = kind; 2755 2756 pccbb_pcmcia_do_mem_map(ph, win); 2757 2758 return 0; 2759 } 2760 2761 /* 2762 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2763 * int window) 2764 * 2765 * This function unmaps memory space which mapped by the function 2766 * pccbb_pcmcia_mem_map(). 2767 */ 2768 STATIC void 2769 pccbb_pcmcia_mem_unmap(pch, window) 2770 pcmcia_chipset_handle_t pch; 2771 int window; 2772 { 2773 struct pcic_handle *ph = (struct pcic_handle *)pch; 2774 int reg; 2775 2776 if (window >= PCIC_MEM_WINS) { 2777 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2778 } 2779 2780 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2781 reg &= ~(1 << window); 2782 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2783 2784 ph->memalloc &= ~(1 << window); 2785 } 2786 2787 #if defined PCCBB_PCMCIA_POLL 2788 struct pccbb_poll_str { 2789 void *arg; 2790 int (*func) __P((void *)); 2791 int level; 2792 struct pcic_handle *ph; 2793 int count; 2794 int num; 2795 struct callout poll_ch; 2796 }; 2797 2798 static struct pccbb_poll_str pccbb_poll[10]; 2799 static int pccbb_poll_n = 0; 2800 2801 static void pccbb_pcmcia_poll __P((void *arg)); 2802 2803 static void 2804 pccbb_pcmcia_poll(arg) 2805 void *arg; 2806 { 2807 struct pccbb_poll_str *poll = arg; 2808 struct pcic_handle *ph = poll->ph; 2809 struct pccbb_softc *sc = ph->sc; 2810 int s; 2811 u_int32_t spsr; /* socket present-state reg */ 2812 2813 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2814 switch (poll->level) { 2815 case IPL_NET: 2816 s = splnet(); 2817 break; 2818 case IPL_BIO: 2819 s = splbio(); 2820 break; 2821 case IPL_TTY: /* fallthrough */ 2822 default: 2823 s = spltty(); 2824 break; 2825 } 2826 2827 spsr = 2828 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2829 CB_SOCKET_STAT); 2830 2831 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2832 if (!(spsr & 0x40)) /* CINT low */ 2833 #else 2834 if (1) 2835 #endif 2836 { 2837 if ((*poll->func) (poll->arg) > 0) { 2838 ++poll->count; 2839 // printf("intr: reported from poller, 0x%x\n", spsr); 2840 #if defined LEVEL2 2841 } else { 2842 printf("intr: miss! 0x%x\n", spsr); 2843 #endif 2844 } 2845 } 2846 splx(s); 2847 } 2848 #endif /* defined CB_PCMCIA_POLL */ 2849 2850 /* 2851 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2852 * struct pcmcia_function *pf, 2853 * int ipl, 2854 * int (*func)(void *), 2855 * void *arg); 2856 * 2857 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2858 */ 2859 STATIC void * 2860 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2861 pcmcia_chipset_handle_t pch; 2862 struct pcmcia_function *pf; 2863 int ipl; 2864 int (*func) __P((void *)); 2865 void *arg; 2866 { 2867 struct pcic_handle *ph = (struct pcic_handle *)pch; 2868 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2869 2870 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2871 /* what should I do? */ 2872 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2873 DPRINTF( 2874 ("%s does not provide edge nor pulse interrupt\n", 2875 sc->sc_dev.dv_xname)); 2876 return NULL; 2877 } 2878 /* 2879 * XXX Noooooo! The interrupt flag must set properly!! 2880 * dumb pcmcia driver!! 2881 */ 2882 } 2883 2884 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2885 } 2886 2887 /* 2888 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2889 * void *ih) 2890 * 2891 * This function disables PC-Card interrupt. 2892 */ 2893 STATIC void 2894 pccbb_pcmcia_intr_disestablish(pch, ih) 2895 pcmcia_chipset_handle_t pch; 2896 void *ih; 2897 { 2898 struct pcic_handle *ph = (struct pcic_handle *)pch; 2899 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2900 2901 pccbb_intr_disestablish(sc, ih); 2902 } 2903 2904 #if rbus 2905 /* 2906 * static int 2907 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2908 * bus_addr_t addr, bus_size_t size, 2909 * bus_addr_t mask, bus_size_t align, 2910 * int flags, bus_addr_t *addrp; 2911 * bus_space_handle_t *bshp) 2912 * 2913 * This function allocates a portion of memory or io space for 2914 * clients. This function is called from CardBus card drivers. 2915 */ 2916 static int 2917 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2918 cardbus_chipset_tag_t ct; 2919 rbus_tag_t rb; 2920 bus_addr_t addr; 2921 bus_size_t size; 2922 bus_addr_t mask; 2923 bus_size_t align; 2924 int flags; 2925 bus_addr_t *addrp; 2926 bus_space_handle_t *bshp; 2927 { 2928 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2929 2930 DPRINTF( 2931 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2932 addr, size, mask, align)); 2933 2934 if (align == 0) { 2935 align = size; 2936 } 2937 2938 if (rb->rb_bt == sc->sc_memt) { 2939 if (align < 16) { 2940 return 1; 2941 } 2942 if (align < 0x1000) { 2943 align = 0x1000; 2944 } 2945 } else if (rb->rb_bt == sc->sc_iot) { 2946 if (align < 4) { 2947 return 1; 2948 } 2949 /* XXX: hack for avoiding ISA image */ 2950 if (mask < 0x0100) { 2951 mask = 0x3ff; 2952 addr = 0x300; 2953 } 2954 2955 } else { 2956 DPRINTF( 2957 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 2958 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 2959 return 1; 2960 /* XXX: panic here? */ 2961 } 2962 2963 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2964 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2965 return 1; 2966 } 2967 2968 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2969 2970 return 0; 2971 } 2972 2973 /* 2974 * static int 2975 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2976 * bus_space_handle_t *bshp, bus_size_t size); 2977 * 2978 * This function is called from CardBus card drivers. 2979 */ 2980 static int 2981 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2982 cardbus_chipset_tag_t ct; 2983 rbus_tag_t rb; 2984 bus_space_handle_t bsh; 2985 bus_size_t size; 2986 { 2987 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2988 bus_space_tag_t bt = rb->rb_bt; 2989 2990 pccbb_close_win(sc, bt, bsh, size); 2991 2992 if (bt == sc->sc_memt) { 2993 } else if (bt == sc->sc_iot) { 2994 } else { 2995 return 1; 2996 /* XXX: panic here? */ 2997 } 2998 2999 return rbus_space_free(rb, bsh, size, NULL); 3000 } 3001 #endif /* rbus */ 3002 3003 #if rbus 3004 3005 static int 3006 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3007 struct pccbb_softc *sc; 3008 bus_space_tag_t bst; 3009 bus_addr_t addr; 3010 bus_size_t size; 3011 bus_space_handle_t bsh; 3012 int flags; 3013 { 3014 struct pccbb_win_chain_head *head; 3015 bus_addr_t align; 3016 3017 head = &sc->sc_iowindow; 3018 align = 0x04; 3019 if (sc->sc_memt == bst) { 3020 head = &sc->sc_memwindow; 3021 align = 0x1000; 3022 DPRINTF(("using memory window, %x %x %x\n\n", 3023 sc->sc_iot, sc->sc_memt, bst)); 3024 } 3025 3026 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3027 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3028 sc->sc_dev.dv_xname, 3029 (head == &sc->sc_memwindow) ? "mem" : "io"); 3030 } 3031 pccbb_winset(align, sc, bst); 3032 3033 return 0; 3034 } 3035 3036 static int 3037 pccbb_close_win(sc, bst, bsh, size) 3038 struct pccbb_softc *sc; 3039 bus_space_tag_t bst; 3040 bus_space_handle_t bsh; 3041 bus_size_t size; 3042 { 3043 struct pccbb_win_chain_head *head; 3044 bus_addr_t align; 3045 3046 head = &sc->sc_iowindow; 3047 align = 0x04; 3048 if (sc->sc_memt == bst) { 3049 head = &sc->sc_memwindow; 3050 align = 0x1000; 3051 } 3052 3053 if (pccbb_winlist_delete(head, bsh, size)) { 3054 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3055 sc->sc_dev.dv_xname, 3056 (head == &sc->sc_memwindow) ? "mem" : "io"); 3057 } 3058 pccbb_winset(align, sc, bst); 3059 3060 return 0; 3061 } 3062 3063 static int 3064 pccbb_winlist_insert(head, start, size, bsh, flags) 3065 struct pccbb_win_chain_head *head; 3066 bus_addr_t start; 3067 bus_size_t size; 3068 bus_space_handle_t bsh; 3069 int flags; 3070 { 3071 struct pccbb_win_chain *chainp, *elem; 3072 3073 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3074 M_NOWAIT)) == NULL) 3075 return (1); /* fail */ 3076 3077 elem->wc_start = start; 3078 elem->wc_end = start + (size - 1); 3079 elem->wc_handle = bsh; 3080 elem->wc_flags = flags; 3081 3082 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3083 chainp = TAILQ_NEXT(chainp, wc_list)) { 3084 if (chainp->wc_end < start) 3085 continue; 3086 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3087 return (0); 3088 } 3089 3090 TAILQ_INSERT_TAIL(head, elem, wc_list); 3091 return (0); 3092 } 3093 3094 static int 3095 pccbb_winlist_delete(head, bsh, size) 3096 struct pccbb_win_chain_head *head; 3097 bus_space_handle_t bsh; 3098 bus_size_t size; 3099 { 3100 struct pccbb_win_chain *chainp; 3101 3102 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3103 chainp = TAILQ_NEXT(chainp, wc_list)) { 3104 if (chainp->wc_handle != bsh) 3105 continue; 3106 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3107 printf("pccbb_winlist_delete: window 0x%lx size " 3108 "inconsistent: 0x%lx, 0x%lx\n", 3109 (unsigned long)chainp->wc_start, 3110 (unsigned long)(chainp->wc_end - chainp->wc_start), 3111 (unsigned long)(size - 1)); 3112 return 1; 3113 } 3114 3115 TAILQ_REMOVE(head, chainp, wc_list); 3116 free(chainp, M_DEVBUF); 3117 3118 return 0; 3119 } 3120 3121 return 1; /* fail: no candidate to remove */ 3122 } 3123 3124 static void 3125 pccbb_winset(align, sc, bst) 3126 bus_addr_t align; 3127 struct pccbb_softc *sc; 3128 bus_space_tag_t bst; 3129 { 3130 pci_chipset_tag_t pc; 3131 pcitag_t tag; 3132 bus_addr_t mask = ~(align - 1); 3133 struct { 3134 cardbusreg_t win_start; 3135 cardbusreg_t win_limit; 3136 int win_flags; 3137 } win[2]; 3138 struct pccbb_win_chain *chainp; 3139 int offs; 3140 3141 win[0].win_start = win[1].win_start = 0xffffffff; 3142 win[0].win_limit = win[1].win_limit = 0; 3143 win[0].win_flags = win[1].win_flags = 0; 3144 3145 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3146 offs = 0x2c; 3147 if (sc->sc_memt == bst) { 3148 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3149 offs = 0x1c; 3150 } 3151 3152 if (chainp != NULL) { 3153 win[0].win_start = chainp->wc_start & mask; 3154 win[0].win_limit = chainp->wc_end & mask; 3155 win[0].win_flags = chainp->wc_flags; 3156 chainp = TAILQ_NEXT(chainp, wc_list); 3157 } 3158 3159 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3160 if (win[1].win_start == 0xffffffff) { 3161 /* window 1 is not used */ 3162 if ((win[0].win_flags == chainp->wc_flags) && 3163 (win[0].win_limit + align >= 3164 (chainp->wc_start & mask))) { 3165 /* concatenate */ 3166 win[0].win_limit = chainp->wc_end & mask; 3167 } else { 3168 /* make new window */ 3169 win[1].win_start = chainp->wc_start & mask; 3170 win[1].win_limit = chainp->wc_end & mask; 3171 win[1].win_flags = chainp->wc_flags; 3172 } 3173 continue; 3174 } 3175 3176 /* Both windows are engaged. */ 3177 if (win[0].win_flags == win[1].win_flags) { 3178 /* same flags */ 3179 if (win[0].win_flags == chainp->wc_flags) { 3180 if (win[1].win_start - (win[0].win_limit + 3181 align) < 3182 (chainp->wc_start & mask) - 3183 ((chainp->wc_end & mask) + align)) { 3184 /* 3185 * merge window 0 and 1, and set win1 3186 * to chainp 3187 */ 3188 win[0].win_limit = win[1].win_limit; 3189 win[1].win_start = 3190 chainp->wc_start & mask; 3191 win[1].win_limit = 3192 chainp->wc_end & mask; 3193 } else { 3194 win[1].win_limit = 3195 chainp->wc_end & mask; 3196 } 3197 } else { 3198 /* different flags */ 3199 3200 /* concatenate win0 and win1 */ 3201 win[0].win_limit = win[1].win_limit; 3202 /* allocate win[1] to new space */ 3203 win[1].win_start = chainp->wc_start & mask; 3204 win[1].win_limit = chainp->wc_end & mask; 3205 win[1].win_flags = chainp->wc_flags; 3206 } 3207 } else { 3208 /* the flags of win[0] and win[1] is different */ 3209 if (win[0].win_flags == chainp->wc_flags) { 3210 win[0].win_limit = chainp->wc_end & mask; 3211 /* 3212 * XXX this creates overlapping windows, so 3213 * what should the poor bridge do if one is 3214 * cachable, and the other is not? 3215 */ 3216 printf("%s: overlapping windows\n", 3217 sc->sc_dev.dv_xname); 3218 } else { 3219 win[1].win_limit = chainp->wc_end & mask; 3220 } 3221 } 3222 } 3223 3224 pc = sc->sc_pc; 3225 tag = sc->sc_tag; 3226 pci_conf_write(pc, tag, offs, win[0].win_start); 3227 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3228 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3229 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3230 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3231 pci_conf_read(pc, tag, offs), 3232 pci_conf_read(pc, tag, offs + 4) + align, 3233 pci_conf_read(pc, tag, offs + 8), 3234 pci_conf_read(pc, tag, offs + 12) + align)); 3235 3236 if (bst == sc->sc_memt) { 3237 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3238 3239 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3240 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3241 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3242 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3243 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3244 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3245 } 3246 } 3247 3248 #endif /* rbus */ 3249 3250 static void 3251 pccbb_powerhook(why, arg) 3252 int why; 3253 void *arg; 3254 { 3255 struct pccbb_softc *sc = arg; 3256 u_int32_t reg; 3257 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3258 bus_space_handle_t base_memh = sc->sc_base_memh; 3259 3260 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3261 3262 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3263 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3264 if (sc->sc_pil_intr_enable) { 3265 (void)pccbbintr_function(sc); 3266 } 3267 sc->sc_pil_intr_enable = 0; 3268 3269 /* ToDo: deactivate or suspend child devices */ 3270 3271 } 3272 3273 if (why == PWR_RESUME) { 3274 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3275 /* BIOS did not recover this register */ 3276 pci_conf_write (sc->sc_pc, sc->sc_tag, 3277 PCI_SOCKBASE, sc->sc_sockbase); 3278 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3279 /* BIOS did not recover this register */ 3280 pci_conf_write (sc->sc_pc, sc->sc_tag, 3281 PCI_BUSNUM, sc->sc_busnum); 3282 /* CSC Interrupt: Card detect interrupt on */ 3283 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3284 /* Card detect intr is turned on. */ 3285 reg |= CB_SOCKET_MASK_CD; 3286 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3287 /* reset interrupt */ 3288 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3289 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3290 3291 /* 3292 * check for card insertion or removal during suspend period. 3293 * XXX: the code can't cope with card swap (remove then 3294 * insert). how can we detect such situation? 3295 */ 3296 (void)pccbbintr(sc); 3297 3298 sc->sc_pil_intr_enable = 1; 3299 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3300 3301 /* ToDo: activate or wakeup child devices */ 3302 } 3303 } 3304
Indexes created Fri Sep 26 08:10:20 GMT 2025