pccbb.c revision 1.70
1 /* $NetBSD: pccbb.c,v 1.70 2001/11/02 03:32:33 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 #define CBB_DEBUG 35 #define SHOW_REGS 36 #define PCCBB_PCMCIA_POLL 37 */ 38 /* #define CBB_DEBUG */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/reboot.h> /* for bootverbose */ 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 #include <sys/proc.h> 57 58 #include <machine/intr.h> 59 #include <machine/bus.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/pccbbreg.h> 66 67 #include <dev/cardbus/cardslotvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 71 #include <dev/pcmcia/pcmciareg.h> 72 #include <dev/pcmcia/pcmciavar.h> 73 74 #include <dev/ic/i82365reg.h> 75 #include <dev/ic/i82365var.h> 76 #include <dev/pci/pccbbvar.h> 77 78 #include "locators.h" 79 80 #ifndef __NetBSD_Version__ 81 struct cfdriver cbb_cd = { 82 NULL, "cbb", DV_DULL 83 }; 84 #endif 85 86 #if defined CBB_DEBUG 87 #define DPRINTF(x) printf x 88 #define STATIC 89 #else 90 #define DPRINTF(x) 91 #define STATIC static 92 #endif 93 94 /* 95 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 96 * if you want to wait more than 1 ms. 97 */ 98 #define DELAY_MS(time, param) \ 99 do { \ 100 if (cold == 0) { \ 101 int tick = (hz*(time))/1000; \ 102 \ 103 if (tick <= 1) { \ 104 tick = 2; \ 105 } \ 106 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 107 } else { \ 108 delay((time)*1000); \ 109 } \ 110 } while (0) 111 112 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 113 void pccbbattach __P((struct device *, struct device *, void *)); 114 int pccbbintr __P((void *)); 115 static void pci113x_insert __P((void *)); 116 static int pccbbintr_function __P((struct pccbb_softc *)); 117 118 static int pccbb_detect_card __P((struct pccbb_softc *)); 119 120 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 121 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 122 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 123 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 124 125 STATIC int cb_reset __P((struct pccbb_softc *)); 126 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 127 STATIC int cbbprint __P((void *, const char *)); 128 129 static int cb_chipset __P((u_int32_t, int *)); 130 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 131 struct pcmciabus_attach_args *)); 132 #if 0 133 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 134 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 135 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 136 #endif 137 138 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 139 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 140 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 141 #if !rbus 142 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 143 u_int32_t)); 144 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 145 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 146 u_int32_t)); 147 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 148 #endif /* !rbus */ 149 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 150 int level, int (*ih) (void *), void *sc)); 151 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 152 153 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 154 int level, int (*ih) (void *), void *sc)); 155 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 156 157 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 158 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 159 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 160 int)); 161 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 162 cardbusreg_t)); 163 static void pccbb_chipinit __P((struct pccbb_softc *)); 164 165 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 166 struct pcmcia_mem_handle *)); 167 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 168 struct pcmcia_mem_handle *)); 169 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 171 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 172 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 173 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 174 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 175 struct pcmcia_io_handle *)); 176 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *)); 178 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 179 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 180 struct pcmcia_function *, int, int (*)(void *), void *)); 181 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 182 void *)); 183 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 184 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 185 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 186 187 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 188 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 189 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 190 static void pccbb_powerhook __P((int, void *)); 191 192 /* bus-space allocation and deallocation functions */ 193 #if rbus 194 195 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 196 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 197 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 198 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 199 bus_space_handle_t, bus_size_t)); 200 201 #endif /* rbus */ 202 203 #if rbus 204 205 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 206 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 207 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_space_handle_t, bus_size_t)); 209 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 210 bus_size_t, bus_space_handle_t, int)); 211 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 212 bus_space_handle_t, bus_size_t)); 213 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 214 bus_space_tag_t)); 215 void pccbb_winlist_show(struct pccbb_win_chain *); 216 217 #endif /* rbus */ 218 219 /* for config_defer */ 220 static void pccbb_pci_callback __P((struct device *)); 221 222 #if defined SHOW_REGS 223 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 224 bus_space_tag_t memt, bus_space_handle_t memh)); 225 #endif 226 227 struct cfattach cbb_pci_ca = { 228 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 229 }; 230 231 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 232 pccbb_pcmcia_mem_alloc, 233 pccbb_pcmcia_mem_free, 234 pccbb_pcmcia_mem_map, 235 pccbb_pcmcia_mem_unmap, 236 pccbb_pcmcia_io_alloc, 237 pccbb_pcmcia_io_free, 238 pccbb_pcmcia_io_map, 239 pccbb_pcmcia_io_unmap, 240 pccbb_pcmcia_intr_establish, 241 pccbb_pcmcia_intr_disestablish, 242 pccbb_pcmcia_socket_enable, 243 pccbb_pcmcia_socket_disable, 244 pccbb_pcmcia_card_detect 245 }; 246 247 #if rbus 248 static struct cardbus_functions pccbb_funcs = { 249 pccbb_rbus_cb_space_alloc, 250 pccbb_rbus_cb_space_free, 251 pccbb_cb_intr_establish, 252 pccbb_cb_intr_disestablish, 253 pccbb_ctrl, 254 pccbb_power, 255 pccbb_make_tag, 256 pccbb_free_tag, 257 pccbb_conf_read, 258 pccbb_conf_write, 259 }; 260 #else 261 static struct cardbus_functions pccbb_funcs = { 262 pccbb_ctrl, 263 pccbb_power, 264 pccbb_mem_open, 265 pccbb_mem_close, 266 pccbb_io_open, 267 pccbb_io_close, 268 pccbb_cb_intr_establish, 269 pccbb_cb_intr_disestablish, 270 pccbb_make_tag, 271 pccbb_conf_read, 272 pccbb_conf_write, 273 }; 274 #endif 275 276 int 277 pcicbbmatch(parent, match, aux) 278 struct device *parent; 279 struct cfdata *match; 280 void *aux; 281 { 282 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 283 284 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 285 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 286 PCI_INTERFACE(pa->pa_class) == 0) { 287 return 1; 288 } 289 290 return 0; 291 } 292 293 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 294 | ((prod) << PCI_PRODUCT_SHIFT)) 295 296 const struct yenta_chipinfo { 297 pcireg_t yc_id; /* vendor tag | product tag */ 298 int yc_chiptype; 299 int yc_flags; 300 } yc_chipsets[] = { 301 /* Texas Instruments chips */ 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 329 /* Ricoh chips */ 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 331 PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 341 PCCBB_PCMCIA_MEM_32}, 342 343 /* Toshiba products */ 344 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 345 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 347 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 349 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 351 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 352 353 /* Cirrus Logic products */ 354 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 355 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 357 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 358 359 /* sentinel, or Generic chip */ 360 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 361 }; 362 363 static int 364 cb_chipset(pci_id, flagp) 365 u_int32_t pci_id; 366 int *flagp; 367 { 368 const struct yenta_chipinfo *yc; 369 370 /* Loop over except the last default entry. */ 371 for (yc = yc_chipsets; yc < yc_chipsets + 372 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 373 if (pci_id == yc->yc_id) 374 break; 375 376 if (flagp != NULL) 377 *flagp = yc->yc_flags; 378 379 return (yc->yc_chiptype); 380 } 381 382 static void 383 pccbb_shutdown(void *arg) 384 { 385 struct pccbb_softc *sc = arg; 386 pcireg_t command; 387 388 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 389 390 /* 391 * turn off power 392 * 393 * XXX - do not turn off power if chipset is TI 113X because 394 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 395 */ 396 if (sc->sc_chipset != CB_TI113X) { 397 pccbb_power((cardbus_chipset_tag_t)sc, 398 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 399 } 400 401 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 402 0); 403 404 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 405 406 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 407 PCI_COMMAND_MASTER_ENABLE); 408 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 409 410 } 411 412 void 413 pccbbattach(parent, self, aux) 414 struct device *parent; 415 struct device *self; 416 void *aux; 417 { 418 struct pccbb_softc *sc = (void *)self; 419 struct pci_attach_args *pa = aux; 420 pci_chipset_tag_t pc = pa->pa_pc; 421 pcireg_t busreg, reg, sock_base; 422 bus_addr_t sockbase; 423 char devinfo[256]; 424 int flags; 425 int pwrmgt_offs; 426 427 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 428 429 pci_devinfo(pa->pa_id, 0, 0, devinfo); 430 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 431 #ifdef CBB_DEBUG 432 printf(" (chipflags %x)", flags); 433 #endif 434 printf("\n"); 435 436 TAILQ_INIT(&sc->sc_memwindow); 437 TAILQ_INIT(&sc->sc_iowindow); 438 439 #if rbus 440 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 441 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 442 443 #if 0 444 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 445 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 446 #endif 447 #endif /* rbus */ 448 449 sc->sc_base_memh = 0; 450 451 /* power management: set D0 state */ 452 sc->sc_pwrmgt_offs = 0; 453 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 454 &pwrmgt_offs, 0)) { 455 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + 4); 456 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 457 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 458 reg &= ~PCI_PMCSR_STATE_MASK; 459 reg |= PCI_PMCSR_STATE_D0; 460 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 461 pci_conf_write(pc, pa->pa_tag, pwrmgt_offs + 4, reg); 462 } 463 464 sc->sc_pwrmgt_offs = pwrmgt_offs; 465 } 466 467 /* 468 * MAP socket registers and ExCA registers on memory-space 469 * When no valid address is set on socket base registers (on pci 470 * config space), get it not polite way. 471 */ 472 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 473 474 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 475 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 476 /* The address must be valid. */ 477 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 478 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 479 printf("%s: can't map socket base address 0x%x\n", 480 sc->sc_dev.dv_xname, sock_base); 481 /* 482 * I think it's funny: socket base registers must be 483 * mapped on memory space, but ... 484 */ 485 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 486 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 487 NULL)) { 488 printf("%s: can't map socket base address" 489 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 490 (unsigned long)sockbase); 491 /* give up... allocate reg space via rbus. */ 492 sc->sc_base_memh = 0; 493 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 494 } 495 } else { 496 DPRINTF(("%s: socket base address 0x%lx\n", 497 sc->sc_dev.dv_xname, sockbase)); 498 } 499 } 500 501 sc->sc_mem_start = 0; /* XXX */ 502 sc->sc_mem_end = 0xffffffff; /* XXX */ 503 504 /* 505 * When interrupt isn't routed correctly, give up probing cbb and do 506 * not kill pcic-compatible port. 507 */ 508 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 509 printf("%s: NOT USED because of unconfigured interrupt\n", 510 sc->sc_dev.dv_xname); 511 return; 512 } 513 514 /* 515 * When bus number isn't set correctly, give up using 32-bit CardBus 516 * mode. 517 */ 518 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 519 #if notyet 520 if (((busreg >> 8) & 0xff) == 0) { 521 printf("%s: CardBus support disabled because of unconfigured bus number\n", 522 sc->sc_dev.dv_xname); 523 flags |= PCCBB_PCMCIA_16BITONLY; 524 } 525 #endif 526 527 /* pccbb_machdep.c end */ 528 529 #if defined CBB_DEBUG 530 { 531 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 532 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 533 intrname[pa->pa_intrpin], pa->pa_intrline); 534 } 535 #endif 536 537 /* setup softc */ 538 sc->sc_pc = pc; 539 sc->sc_iot = pa->pa_iot; 540 sc->sc_memt = pa->pa_memt; 541 sc->sc_dmat = pa->pa_dmat; 542 sc->sc_tag = pa->pa_tag; 543 sc->sc_function = pa->pa_function; 544 sc->sc_sockbase = sock_base; 545 sc->sc_busnum = busreg; 546 547 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 548 549 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 550 551 shutdownhook_establish(pccbb_shutdown, sc); 552 553 /* Disable legacy register mapping. */ 554 switch (sc->sc_chipset) { 555 case CB_RX5C46X: /* fallthrough */ 556 #if 0 557 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 558 case CB_RX5C47X: 559 #endif 560 /* 561 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 562 * cannot be disabled by substituting 0 into PCI_LEGACY 563 * register. Ricoh CardBus bridges have special bits on Bridge 564 * control reg (addr 0x3e on PCI config space). 565 */ 566 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 567 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 568 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 569 break; 570 571 default: 572 /* XXX I don't know proper way to kill legacy I/O. */ 573 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 574 break; 575 } 576 577 config_defer(self, pccbb_pci_callback); 578 } 579 580 581 582 583 /* 584 * static void pccbb_pci_callback(struct device *self) 585 * 586 * The actual attach routine: get memory space for YENTA register 587 * space, setup YENTA register and route interrupt. 588 * 589 * This function should be deferred because this device may obtain 590 * memory space dynamically. This function must avoid obtaining 591 * memory area which has already kept for another device. 592 */ 593 static void 594 pccbb_pci_callback(self) 595 struct device *self; 596 { 597 struct pccbb_softc *sc = (void *)self; 598 pci_chipset_tag_t pc = sc->sc_pc; 599 pci_intr_handle_t ih; 600 const char *intrstr = NULL; 601 bus_addr_t sockbase; 602 struct cbslot_attach_args cba; 603 struct pcmciabus_attach_args paa; 604 struct cardslot_attach_args caa; 605 struct cardslot_softc *csc; 606 607 if (0 == sc->sc_base_memh) { 608 /* The socket registers aren't mapped correctly. */ 609 #if rbus 610 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 611 (sc->sc_chipset == CB_RX5C47X 612 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 613 0, &sockbase, &sc->sc_base_memh)) { 614 return; 615 } 616 sc->sc_base_memt = sc->sc_memt; 617 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 618 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 619 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 620 PCI_SOCKBASE))); 621 #else 622 sc->sc_base_memt = sc->sc_memt; 623 #if !defined CBB_PCI_BASE 624 #define CBB_PCI_BASE 0x20000000 625 #endif 626 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 627 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 628 /* cannot allocate memory space */ 629 return; 630 } 631 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 632 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 633 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 634 sc->sc_tag, PCI_SOCKBASE))); 635 sc->sc_sockbase = sockbase; 636 #endif 637 } 638 639 /* bus bridge initialization */ 640 pccbb_chipinit(sc); 641 642 /* clear data structure for child device interrupt handlers */ 643 sc->sc_pil = NULL; 644 sc->sc_pil_intr_enable = 1; 645 646 /* Map and establish the interrupt. */ 647 if (pci_intr_map(&sc->sc_pa, &ih)) { 648 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 649 return; 650 } 651 intrstr = pci_intr_string(pc, ih); 652 653 /* 654 * XXX pccbbintr should be called under the priority lower 655 * than any other hard interrputs. 656 */ 657 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 658 659 if (sc->sc_ih == NULL) { 660 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 661 if (intrstr != NULL) { 662 printf(" at %s", intrstr); 663 } 664 printf("\n"); 665 return; 666 } 667 668 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 669 powerhook_establish(pccbb_powerhook, sc); 670 671 { 672 u_int32_t sockstat; 673 674 sockstat = bus_space_read_4(sc->sc_base_memt, 675 sc->sc_base_memh, CB_SOCKET_STAT); 676 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 677 sc->sc_flags |= CBB_CARDEXIST; 678 } 679 } 680 681 /* 682 * attach cardbus 683 */ 684 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 685 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 686 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 687 688 /* initialize cbslot_attach */ 689 cba.cba_busname = "cardbus"; 690 cba.cba_iot = sc->sc_iot; 691 cba.cba_memt = sc->sc_memt; 692 cba.cba_dmat = sc->sc_dmat; 693 cba.cba_bus = (busreg >> 8) & 0x0ff; 694 cba.cba_cc = (void *)sc; 695 cba.cba_cf = &pccbb_funcs; 696 cba.cba_intrline = sc->sc_pa.pa_intrline; 697 698 #if rbus 699 cba.cba_rbus_iot = sc->sc_rbus_iot; 700 cba.cba_rbus_memt = sc->sc_rbus_memt; 701 #endif 702 703 cba.cba_cacheline = PCI_CACHELINE(bhlc); 704 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 705 706 if (bootverbose) { 707 printf("%s: cacheline 0x%x lattimer 0x%x\n", 708 sc->sc_dev.dv_xname, cba.cba_cacheline, 709 cba.cba_lattimer); 710 printf("%s: bhlc 0x%x lscp 0x%x\n", 711 sc->sc_dev.dv_xname, bhlc, busreg); 712 } 713 #if defined SHOW_REGS 714 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 715 sc->sc_base_memh); 716 #endif 717 } 718 719 pccbb_pcmcia_attach_setup(sc, &paa); 720 caa.caa_cb_attach = NULL; 721 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 722 caa.caa_cb_attach = &cba; 723 } 724 caa.caa_16_attach = &paa; 725 caa.caa_ph = &sc->sc_pcmcia_h; 726 727 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 728 DPRINTF(("pccbbattach: found cardslot\n")); 729 sc->sc_csc = csc; 730 } 731 732 return; 733 } 734 735 736 737 738 739 /* 740 * static void pccbb_chipinit(struct pccbb_softc *sc) 741 * 742 * This function initialize YENTA chip registers listed below: 743 * 1) PCI command reg, 744 * 2) PCI and CardBus latency timer, 745 * 3) route PCI interrupt, 746 * 4) close all memory and io windows. 747 * 5) turn off bus power. 748 * 6) card detect interrupt on. 749 * 7) clear interrupt 750 */ 751 static void 752 pccbb_chipinit(sc) 753 struct pccbb_softc *sc; 754 { 755 pci_chipset_tag_t pc = sc->sc_pc; 756 pcitag_t tag = sc->sc_tag; 757 bus_space_tag_t bmt = sc->sc_base_memt; 758 bus_space_handle_t bmh = sc->sc_base_memh; 759 pcireg_t reg; 760 761 /* 762 * Set PCI command reg. 763 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 764 */ 765 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 766 /* I believe it is harmless. */ 767 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 768 PCI_COMMAND_MASTER_ENABLE); 769 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 770 771 /* 772 * Set CardBus latency timer. 773 */ 774 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 775 if (PCI_CB_LATENCY(reg) < 0x20) { 776 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 777 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 778 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 779 } 780 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 781 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 782 783 /* 784 * Set PCI latency timer. 785 */ 786 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 787 if (PCI_LATTIMER(reg) < 0x10) { 788 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 789 reg |= (0x10 << PCI_LATTIMER_SHIFT); 790 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 791 } 792 DPRINTF(("PCI latency timer 0x%x (%x)\n", 793 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 794 795 796 /* Route functional interrupts to PCI. */ 797 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 798 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 799 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 800 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 801 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 802 803 switch (sc->sc_chipset) { 804 case CB_TI113X: 805 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 806 /* This bit is shared, but may read as 0 on some chips, so set 807 it explicitly on both functions. */ 808 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 809 /* CSC intr enable */ 810 reg |= PCI113X_CBCTRL_PCI_CSC; 811 /* functional intr prohibit | prohibit ISA routing */ 812 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 813 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 814 break; 815 816 case CB_TI12XX: 817 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 818 reg |= PCI12XX_SYSCTRL_VCCPROT; 819 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 820 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 821 reg |= PCI12XX_CBCTRL_CSC; 822 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 823 break; 824 825 case CB_TOPIC95B: 826 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 827 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 828 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 829 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 830 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 831 sc->sc_dev.dv_xname, reg)); 832 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 833 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 834 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 835 DPRINTF(("0x%x\n", reg)); 836 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 837 break; 838 839 case CB_TOPIC97: 840 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 841 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 842 sc->sc_dev.dv_xname, reg)); 843 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 844 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 845 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 846 reg |= TOPIC97_SLOT_CTRL_PCIINT; 847 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 848 DPRINTF(("0x%x\n", reg)); 849 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 850 /* make sure to assert LV card support bits */ 851 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 852 0x800 + 0x3e, 853 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 854 0x800 + 0x3e) | 0x03); 855 break; 856 } 857 858 /* Close all memory and I/O windows. */ 859 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 860 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 861 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 862 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 863 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 864 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 865 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 866 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 867 868 /* reset 16-bit pcmcia bus */ 869 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 870 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 871 872 /* turn off power */ 873 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 874 875 /* CSC Interrupt: Card detect interrupt on */ 876 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 877 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 878 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 879 /* reset interrupt */ 880 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 881 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 882 } 883 884 885 886 887 /* 888 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 889 * struct pcmciabus_attach_args *paa) 890 * 891 * This function attaches 16-bit PCcard bus. 892 */ 893 STATIC void 894 pccbb_pcmcia_attach_setup(sc, paa) 895 struct pccbb_softc *sc; 896 struct pcmciabus_attach_args *paa; 897 { 898 struct pcic_handle *ph = &sc->sc_pcmcia_h; 899 #if rbus 900 rbus_tag_t rb; 901 #endif 902 903 /* initialize pcmcia part in pccbb_softc */ 904 ph->ph_parent = (struct device *)sc; 905 ph->sock = sc->sc_function; 906 ph->flags = 0; 907 ph->shutdown = 0; 908 ph->ih_irq = sc->sc_pa.pa_intrline; 909 ph->ph_bus_t = sc->sc_base_memt; 910 ph->ph_bus_h = sc->sc_base_memh; 911 ph->ph_read = pccbb_pcmcia_read; 912 ph->ph_write = pccbb_pcmcia_write; 913 sc->sc_pct = &pccbb_pcmcia_funcs; 914 915 /* 916 * We need to do a few things here: 917 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 918 * setting the IRQ numbers to 0. 919 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 920 * routing of CSC interrupts (e.g. card removal) to PCI while in 921 * PCMCIA mode. We just leave this set all the time. 922 * 3) Enable card insertion/removal interrupts in case the chip also 923 * needs that while in PCMCIA mode. 924 * 4) Clear any pending CSC interrupt. 925 */ 926 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 927 if (sc->sc_chipset == CB_TI113X) { 928 Pcic_write(ph, PCIC_CSC_INTR, 0); 929 } else { 930 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 931 Pcic_read(ph, PCIC_CSC); 932 } 933 934 /* initialize pcmcia bus attachment */ 935 paa->paa_busname = "pcmcia"; 936 paa->pct = sc->sc_pct; 937 paa->pch = ph; 938 paa->iobase = 0; /* I don't use them */ 939 paa->iosize = 0; 940 #if rbus 941 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 942 paa->iobase = rb->rb_start + rb->rb_offset; 943 paa->iosize = rb->rb_end - rb->rb_start; 944 #endif 945 946 return; 947 } 948 949 #if 0 950 STATIC void 951 pccbb_pcmcia_attach_card(ph) 952 struct pcic_handle *ph; 953 { 954 if (ph->flags & PCIC_FLAG_CARDP) { 955 panic("pccbb_pcmcia_attach_card: already attached"); 956 } 957 958 /* call the MI attach function */ 959 pcmcia_card_attach(ph->pcmcia); 960 961 ph->flags |= PCIC_FLAG_CARDP; 962 } 963 964 STATIC void 965 pccbb_pcmcia_detach_card(ph, flags) 966 struct pcic_handle *ph; 967 int flags; 968 { 969 if (!(ph->flags & PCIC_FLAG_CARDP)) { 970 panic("pccbb_pcmcia_detach_card: already detached"); 971 } 972 973 ph->flags &= ~PCIC_FLAG_CARDP; 974 975 /* call the MI detach function */ 976 pcmcia_card_detach(ph->pcmcia, flags); 977 } 978 #endif 979 980 /* 981 * int pccbbintr(arg) 982 * void *arg; 983 * This routine handles the interrupt from Yenta PCI-CardBus bridge 984 * itself. 985 */ 986 int 987 pccbbintr(arg) 988 void *arg; 989 { 990 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 991 u_int32_t sockevent, sockstate; 992 bus_space_tag_t memt = sc->sc_base_memt; 993 bus_space_handle_t memh = sc->sc_base_memh; 994 struct pcic_handle *ph = &sc->sc_pcmcia_h; 995 996 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 997 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 998 Pcic_read(ph, PCIC_CSC); 999 1000 if (sockevent == 0) { 1001 /* This intr is not for me: it may be for my child devices. */ 1002 if (sc->sc_pil_intr_enable) { 1003 return pccbbintr_function(sc); 1004 } else { 1005 return 0; 1006 } 1007 } 1008 1009 if (sockevent & CB_SOCKET_EVENT_CD) { 1010 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1011 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 1012 /* A card should be removed. */ 1013 if (sc->sc_flags & CBB_CARDEXIST) { 1014 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1015 sockevent)); 1016 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1017 sc->sc_flags &= ~CBB_CARDEXIST; 1018 if (sc->sc_csc->sc_status & 1019 CARDSLOT_STATUS_CARD_16) { 1020 #if 0 1021 struct pcic_handle *ph = 1022 &sc->sc_pcmcia_h; 1023 1024 pcmcia_card_deactivate(ph->pcmcia); 1025 pccbb_pcmcia_socket_disable(ph); 1026 pccbb_pcmcia_detach_card(ph, 1027 DETACH_FORCE); 1028 #endif 1029 cardslot_event_throw(sc->sc_csc, 1030 CARDSLOT_EVENT_REMOVAL_16); 1031 } else if (sc->sc_csc->sc_status & 1032 CARDSLOT_STATUS_CARD_CB) { 1033 /* Cardbus intr removed */ 1034 cardslot_event_throw(sc->sc_csc, 1035 CARDSLOT_EVENT_REMOVAL_CB); 1036 } 1037 } 1038 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1039 /* 1040 * The pccbbintr may called from powerdown hook when 1041 * the system resumed, to detect the card 1042 * insertion/removal during suspension. 1043 */ 1044 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1045 if (sc->sc_flags & CBB_INSERTING) { 1046 callout_stop(&sc->sc_insert_ch); 1047 } 1048 callout_reset(&sc->sc_insert_ch, hz / 10, 1049 pci113x_insert, sc); 1050 sc->sc_flags |= CBB_INSERTING; 1051 } 1052 } 1053 1054 return (1); 1055 } 1056 1057 /* 1058 * static int pccbbintr_function(struct pccbb_softc *sc) 1059 * 1060 * This function calls each interrupt handler registered at the 1061 * bridge. The interrupt handlers are called in registered order. 1062 */ 1063 static int 1064 pccbbintr_function(sc) 1065 struct pccbb_softc *sc; 1066 { 1067 int retval = 0, val; 1068 struct pccbb_intrhand_list *pil; 1069 int s, splchanged; 1070 1071 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1072 /* 1073 * XXX priority change. gross. I use if-else 1074 * sentense instead of switch-case sentense because of 1075 * avoiding duplicate case value error. More than one 1076 * IPL_XXX use same value. It depends on 1077 * implimentation. 1078 */ 1079 splchanged = 1; 1080 if (pil->pil_level == IPL_SERIAL) { 1081 s = splserial(); 1082 } else if (pil->pil_level == IPL_HIGH) { 1083 s = splhigh(); 1084 } else if (pil->pil_level == IPL_CLOCK) { 1085 s = splclock(); 1086 } else if (pil->pil_level == IPL_AUDIO) { 1087 s = splaudio(); 1088 } else if (pil->pil_level == IPL_IMP) { 1089 s = splvm(); /* XXX */ 1090 } else if (pil->pil_level == IPL_TTY) { 1091 s = spltty(); 1092 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1093 s = splsoftserial(); 1094 } else if (pil->pil_level == IPL_NET) { 1095 s = splnet(); 1096 } else { 1097 splchanged = 0; 1098 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1099 } 1100 1101 val = (*pil->pil_func)(pil->pil_arg); 1102 1103 if (splchanged != 0) { 1104 splx(s); 1105 } 1106 1107 retval = retval == 1 ? 1 : 1108 retval == 0 ? val : val != 0 ? val : retval; 1109 } 1110 1111 return retval; 1112 } 1113 1114 static void 1115 pci113x_insert(arg) 1116 void *arg; 1117 { 1118 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1119 u_int32_t sockevent, sockstate; 1120 1121 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1122 CB_SOCKET_EVENT); 1123 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1124 CB_SOCKET_STAT); 1125 1126 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1127 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1128 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1129 sc->sc_flags |= CBB_CARDEXIST; 1130 /* call pccard interrupt handler here */ 1131 if (sockstate & CB_SOCKET_STAT_16BIT) { 1132 /* 16-bit card found */ 1133 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1134 cardslot_event_throw(sc->sc_csc, 1135 CARDSLOT_EVENT_INSERTION_16); 1136 } else if (sockstate & CB_SOCKET_STAT_CB) { 1137 /* cardbus card found */ 1138 /* cardbus_attach_card(sc->sc_csc); */ 1139 cardslot_event_throw(sc->sc_csc, 1140 CARDSLOT_EVENT_INSERTION_CB); 1141 } else { 1142 /* who are you? */ 1143 } 1144 } else { 1145 callout_reset(&sc->sc_insert_ch, hz / 10, 1146 pci113x_insert, sc); 1147 } 1148 } 1149 1150 #define PCCBB_PCMCIA_OFFSET 0x800 1151 static u_int8_t 1152 pccbb_pcmcia_read(ph, reg) 1153 struct pcic_handle *ph; 1154 int reg; 1155 { 1156 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1157 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1158 1159 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1160 PCCBB_PCMCIA_OFFSET + reg); 1161 } 1162 1163 static void 1164 pccbb_pcmcia_write(ph, reg, val) 1165 struct pcic_handle *ph; 1166 int reg; 1167 u_int8_t val; 1168 { 1169 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1170 val); 1171 1172 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1173 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1174 } 1175 1176 /* 1177 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1178 */ 1179 STATIC int 1180 pccbb_ctrl(ct, command) 1181 cardbus_chipset_tag_t ct; 1182 int command; 1183 { 1184 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1185 1186 switch (command) { 1187 case CARDBUS_CD: 1188 if (2 == pccbb_detect_card(sc)) { 1189 int retval = 0; 1190 int status = cb_detect_voltage(sc); 1191 if (PCCARD_VCC_5V & status) { 1192 retval |= CARDBUS_5V_CARD; 1193 } 1194 if (PCCARD_VCC_3V & status) { 1195 retval |= CARDBUS_3V_CARD; 1196 } 1197 if (PCCARD_VCC_XV & status) { 1198 retval |= CARDBUS_XV_CARD; 1199 } 1200 if (PCCARD_VCC_YV & status) { 1201 retval |= CARDBUS_YV_CARD; 1202 } 1203 return retval; 1204 } else { 1205 return 0; 1206 } 1207 break; 1208 case CARDBUS_RESET: 1209 return cb_reset(sc); 1210 break; 1211 case CARDBUS_IO_ENABLE: /* fallthrough */ 1212 case CARDBUS_IO_DISABLE: /* fallthrough */ 1213 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1214 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1215 case CARDBUS_BM_ENABLE: /* fallthrough */ 1216 case CARDBUS_BM_DISABLE: /* fallthrough */ 1217 /* XXX: I think we don't need to call this function below. */ 1218 return pccbb_cardenable(sc, command); 1219 break; 1220 } 1221 1222 return 0; 1223 } 1224 1225 /* 1226 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1227 * This function returns true when it succeeds and returns false when 1228 * it fails. 1229 */ 1230 STATIC int 1231 pccbb_power(ct, command) 1232 cardbus_chipset_tag_t ct; 1233 int command; 1234 { 1235 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1236 1237 u_int32_t status, sock_ctrl; 1238 bus_space_tag_t memt = sc->sc_base_memt; 1239 bus_space_handle_t memh = sc->sc_base_memh; 1240 1241 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1242 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1243 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1244 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1245 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1246 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1247 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1248 "UNKNOWN", 1249 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1250 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1251 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1252 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1253 "UNKNOWN", command)); 1254 1255 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1256 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1257 1258 switch (command & CARDBUS_VCCMASK) { 1259 case CARDBUS_VCC_UC: 1260 break; 1261 case CARDBUS_VCC_5V: 1262 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1263 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1264 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1265 } else { 1266 printf("%s: BAD voltage request: no 5 V card\n", 1267 sc->sc_dev.dv_xname); 1268 } 1269 break; 1270 case CARDBUS_VCC_3V: 1271 if (CB_SOCKET_STAT_3VCARD & status) { 1272 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1273 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1274 } else { 1275 printf("%s: BAD voltage request: no 3.3 V card\n", 1276 sc->sc_dev.dv_xname); 1277 } 1278 break; 1279 case CARDBUS_VCC_0V: 1280 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1281 break; 1282 default: 1283 return 0; /* power NEVER changed */ 1284 break; 1285 } 1286 1287 switch (command & CARDBUS_VPPMASK) { 1288 case CARDBUS_VPP_UC: 1289 break; 1290 case CARDBUS_VPP_0V: 1291 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1292 break; 1293 case CARDBUS_VPP_VCC: 1294 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1295 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1296 break; 1297 case CARDBUS_VPP_12V: 1298 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1299 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1300 break; 1301 } 1302 1303 #if 0 1304 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1305 #endif 1306 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1307 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1308 1309 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1310 printf 1311 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1312 sc->sc_dev.dv_xname, sock_ctrl, status); 1313 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1314 (command & CARDBUS_VCCMASK) == 1315 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1316 CARDBUS_VCCMASK) == 1317 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1318 CARDBUS_VCCMASK) == 1319 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1320 CARDBUS_VCCMASK) == 1321 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1322 CARDBUS_VCCMASK) == 1323 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1324 CARDBUS_VCCMASK) == 1325 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1326 (command & CARDBUS_VPPMASK) == 1327 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1328 CARDBUS_VPPMASK) == 1329 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1330 CARDBUS_VPPMASK) == 1331 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1332 CARDBUS_VPPMASK) == 1333 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1334 #if 0 1335 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1336 u_int32_t force = 1337 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1338 /* Reset Bad Vcc request */ 1339 force &= ~CB_SOCKET_FORCE_BADVCC; 1340 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1341 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1342 CB_SOCKET_STAT)); 1343 return 1; 1344 } 1345 #endif 1346 return 0; 1347 } 1348 1349 /* 1350 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1351 * time is 20 ms, some PC-Card bridge requires longer duration. 1352 */ 1353 #if 0 /* XXX called on interrupt context */ 1354 DELAY_MS(300, sc); 1355 #else 1356 delay(300 * 1000); 1357 #endif 1358 1359 return 1; /* power changed correctly */ 1360 } 1361 1362 #if defined CB_PCMCIA_POLL 1363 struct cb_poll_str { 1364 void *arg; 1365 int (*func) __P((void *)); 1366 int level; 1367 pccard_chipset_tag_t ct; 1368 int count; 1369 struct callout poll_ch; 1370 }; 1371 1372 static struct cb_poll_str cb_poll[10]; 1373 static int cb_poll_n = 0; 1374 1375 static void cb_pcmcia_poll __P((void *arg)); 1376 1377 static void 1378 cb_pcmcia_poll(arg) 1379 void *arg; 1380 { 1381 struct cb_poll_str *poll = arg; 1382 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1383 struct pccbb_softc *sc = psc->cpc_parent; 1384 int s; 1385 u_int32_t spsr; /* socket present-state reg */ 1386 1387 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1388 switch (poll->level) { 1389 case IPL_NET: 1390 s = splnet(); 1391 break; 1392 case IPL_BIO: 1393 s = splbio(); 1394 break; 1395 case IPL_TTY: /* fallthrough */ 1396 default: 1397 s = spltty(); 1398 break; 1399 } 1400 1401 spsr = 1402 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1403 CB_SOCKET_STAT); 1404 1405 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1406 if (!(spsr & 0x40)) { /* CINT low */ 1407 #else 1408 if (1) { 1409 #endif 1410 if ((*poll->func) (poll->arg) == 1) { 1411 ++poll->count; 1412 printf("intr: reported from poller, 0x%x\n", spsr); 1413 #if defined LEVEL2 1414 } else { 1415 printf("intr: miss! 0x%x\n", spsr); 1416 #endif 1417 } 1418 } 1419 splx(s); 1420 } 1421 #endif /* defined CB_PCMCIA_POLL */ 1422 1423 /* 1424 * static int pccbb_detect_card(struct pccbb_softc *sc) 1425 * return value: 0 if no card exists. 1426 * 1 if 16-bit card exists. 1427 * 2 if cardbus card exists. 1428 */ 1429 static int 1430 pccbb_detect_card(sc) 1431 struct pccbb_softc *sc; 1432 { 1433 bus_space_handle_t base_memh = sc->sc_base_memh; 1434 bus_space_tag_t base_memt = sc->sc_base_memt; 1435 u_int32_t sockstat = 1436 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1437 int retval = 0; 1438 1439 /* CD1 and CD2 asserted */ 1440 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1441 /* card must be present */ 1442 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1443 /* NOTACARD DEASSERTED */ 1444 if (CB_SOCKET_STAT_CB & sockstat) { 1445 /* CardBus mode */ 1446 retval = 2; 1447 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1448 /* 16-bit mode */ 1449 retval = 1; 1450 } 1451 } 1452 } 1453 return retval; 1454 } 1455 1456 /* 1457 * STATIC int cb_reset(struct pccbb_softc *sc) 1458 * This function resets CardBus card. 1459 */ 1460 STATIC int 1461 cb_reset(sc) 1462 struct pccbb_softc *sc; 1463 { 1464 /* 1465 * Reset Assert at least 20 ms 1466 * Some machines request longer duration. 1467 */ 1468 int reset_duration = 1469 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1470 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1471 1472 /* Reset bit Assert (bit 6 at 0x3E) */ 1473 bcr |= CB_BCR_RESET_ENABLE; 1474 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1475 DELAY_MS(reset_duration, sc); 1476 1477 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1478 /* Reset bit Deassert (bit 6 at 0x3E) */ 1479 bcr &= ~CB_BCR_RESET_ENABLE; 1480 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1481 DELAY_MS(reset_duration, sc); 1482 } 1483 /* No card found on the slot. Keep Reset. */ 1484 return 1; 1485 } 1486 1487 /* 1488 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1489 * This function detect card Voltage. 1490 */ 1491 STATIC int 1492 cb_detect_voltage(sc) 1493 struct pccbb_softc *sc; 1494 { 1495 u_int32_t psr; /* socket present-state reg */ 1496 bus_space_tag_t iot = sc->sc_base_memt; 1497 bus_space_handle_t ioh = sc->sc_base_memh; 1498 int vol = PCCARD_VCC_UKN; /* set 0 */ 1499 1500 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1501 1502 if (0x400u & psr) { 1503 vol |= PCCARD_VCC_5V; 1504 } 1505 if (0x800u & psr) { 1506 vol |= PCCARD_VCC_3V; 1507 } 1508 1509 return vol; 1510 } 1511 1512 STATIC int 1513 cbbprint(aux, pcic) 1514 void *aux; 1515 const char *pcic; 1516 { 1517 /* 1518 struct cbslot_attach_args *cba = aux; 1519 1520 if (cba->cba_slot >= 0) { 1521 printf(" slot %d", cba->cba_slot); 1522 } 1523 */ 1524 return UNCONF; 1525 } 1526 1527 /* 1528 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1529 * This function enables and disables the card 1530 */ 1531 STATIC int 1532 pccbb_cardenable(sc, function) 1533 struct pccbb_softc *sc; 1534 int function; 1535 { 1536 u_int32_t command = 1537 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1538 1539 DPRINTF(("pccbb_cardenable:")); 1540 switch (function) { 1541 case CARDBUS_IO_ENABLE: 1542 command |= PCI_COMMAND_IO_ENABLE; 1543 break; 1544 case CARDBUS_IO_DISABLE: 1545 command &= ~PCI_COMMAND_IO_ENABLE; 1546 break; 1547 case CARDBUS_MEM_ENABLE: 1548 command |= PCI_COMMAND_MEM_ENABLE; 1549 break; 1550 case CARDBUS_MEM_DISABLE: 1551 command &= ~PCI_COMMAND_MEM_ENABLE; 1552 break; 1553 case CARDBUS_BM_ENABLE: 1554 command |= PCI_COMMAND_MASTER_ENABLE; 1555 break; 1556 case CARDBUS_BM_DISABLE: 1557 command &= ~PCI_COMMAND_MASTER_ENABLE; 1558 break; 1559 default: 1560 return 0; 1561 } 1562 1563 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1564 DPRINTF((" command reg 0x%x\n", command)); 1565 return 1; 1566 } 1567 1568 #if !rbus 1569 /* 1570 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1571 */ 1572 static int 1573 pccbb_io_open(ct, win, start, end) 1574 cardbus_chipset_tag_t ct; 1575 int win; 1576 u_int32_t start, end; 1577 { 1578 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1579 int basereg; 1580 int limitreg; 1581 1582 if ((win < 0) || (win > 2)) { 1583 #if defined DIAGNOSTIC 1584 printf("cardbus_io_open: window out of range %d\n", win); 1585 #endif 1586 return 0; 1587 } 1588 1589 basereg = win * 8 + 0x2c; 1590 limitreg = win * 8 + 0x30; 1591 1592 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1593 start, basereg, end, limitreg)); 1594 1595 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1596 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1597 return 1; 1598 } 1599 1600 /* 1601 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1602 */ 1603 static int 1604 pccbb_io_close(ct, win) 1605 cardbus_chipset_tag_t ct; 1606 int win; 1607 { 1608 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1609 int basereg; 1610 int limitreg; 1611 1612 if ((win < 0) || (win > 2)) { 1613 #if defined DIAGNOSTIC 1614 printf("cardbus_io_close: window out of range %d\n", win); 1615 #endif 1616 return 0; 1617 } 1618 1619 basereg = win * 8 + 0x2c; 1620 limitreg = win * 8 + 0x30; 1621 1622 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1623 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1624 return 1; 1625 } 1626 1627 /* 1628 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1629 */ 1630 static int 1631 pccbb_mem_open(ct, win, start, end) 1632 cardbus_chipset_tag_t ct; 1633 int win; 1634 u_int32_t start, end; 1635 { 1636 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1637 int basereg; 1638 int limitreg; 1639 1640 if ((win < 0) || (win > 2)) { 1641 #if defined DIAGNOSTIC 1642 printf("cardbus_mem_open: window out of range %d\n", win); 1643 #endif 1644 return 0; 1645 } 1646 1647 basereg = win * 8 + 0x1c; 1648 limitreg = win * 8 + 0x20; 1649 1650 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1651 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1652 return 1; 1653 } 1654 1655 /* 1656 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1657 */ 1658 static int 1659 pccbb_mem_close(ct, win) 1660 cardbus_chipset_tag_t ct; 1661 int win; 1662 { 1663 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1664 int basereg; 1665 int limitreg; 1666 1667 if ((win < 0) || (win > 2)) { 1668 #if defined DIAGNOSTIC 1669 printf("cardbus_mem_close: window out of range %d\n", win); 1670 #endif 1671 return 0; 1672 } 1673 1674 basereg = win * 8 + 0x1c; 1675 limitreg = win * 8 + 0x20; 1676 1677 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1678 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1679 return 1; 1680 } 1681 #endif 1682 1683 /* 1684 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1685 * int irq, 1686 * int level, 1687 * int (* func) __P((void *)), 1688 * void *arg) 1689 * 1690 * This function registers an interrupt handler at the bridge, in 1691 * order not to call the interrupt handlers of child devices when 1692 * a card-deletion interrupt occurs. 1693 * 1694 * The arguments irq and level are not used. 1695 */ 1696 static void * 1697 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1698 cardbus_chipset_tag_t ct; 1699 int irq, level; 1700 int (*func) __P((void *)); 1701 void *arg; 1702 { 1703 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1704 1705 return pccbb_intr_establish(sc, irq, level, func, arg); 1706 } 1707 1708 1709 /* 1710 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1711 * void *ih) 1712 * 1713 * This function removes an interrupt handler pointed by ih. 1714 */ 1715 static void 1716 pccbb_cb_intr_disestablish(ct, ih) 1717 cardbus_chipset_tag_t ct; 1718 void *ih; 1719 { 1720 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1721 1722 pccbb_intr_disestablish(sc, ih); 1723 } 1724 1725 1726 void 1727 pccbb_intr_route(sc) 1728 struct pccbb_softc *sc; 1729 { 1730 pcireg_t reg; 1731 1732 /* initialize bridge intr routing */ 1733 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1734 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1735 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1736 1737 switch (sc->sc_chipset) { 1738 case CB_TI113X: 1739 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1740 /* functional intr enabled */ 1741 reg |= PCI113X_CBCTRL_PCI_INTR; 1742 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1743 break; 1744 default: 1745 break; 1746 } 1747 } 1748 1749 /* 1750 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1751 * int irq, 1752 * int level, 1753 * int (* func) __P((void *)), 1754 * void *arg) 1755 * 1756 * This function registers an interrupt handler at the bridge, in 1757 * order not to call the interrupt handlers of child devices when 1758 * a card-deletion interrupt occurs. 1759 * 1760 * The arguments irq is not used because pccbb selects intr vector. 1761 */ 1762 static void * 1763 pccbb_intr_establish(sc, irq, level, func, arg) 1764 struct pccbb_softc *sc; 1765 int irq, level; 1766 int (*func) __P((void *)); 1767 void *arg; 1768 { 1769 struct pccbb_intrhand_list *pil, *newpil; 1770 1771 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1772 1773 if (sc->sc_pil == NULL) { 1774 pccbb_intr_route(sc); 1775 1776 } 1777 1778 /* 1779 * Allocate a room for interrupt handler structure. 1780 */ 1781 if (NULL == (newpil = 1782 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1783 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1784 return NULL; 1785 } 1786 1787 newpil->pil_func = func; 1788 newpil->pil_arg = arg; 1789 newpil->pil_level = level; 1790 newpil->pil_next = NULL; 1791 1792 if (sc->sc_pil == NULL) { 1793 sc->sc_pil = newpil; 1794 } else { 1795 for (pil = sc->sc_pil; pil->pil_next != NULL; 1796 pil = pil->pil_next); 1797 pil->pil_next = newpil; 1798 } 1799 1800 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1801 1802 return newpil; 1803 } 1804 1805 /* 1806 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1807 * void *ih) 1808 * 1809 * This function removes an interrupt handler pointed by ih. 1810 */ 1811 static void 1812 pccbb_intr_disestablish(sc, ih) 1813 struct pccbb_softc *sc; 1814 void *ih; 1815 { 1816 struct pccbb_intrhand_list *pil, **pil_prev; 1817 pcireg_t reg; 1818 1819 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1820 1821 pil_prev = &sc->sc_pil; 1822 1823 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1824 if (pil == ih) { 1825 *pil_prev = pil->pil_next; 1826 free(pil, M_DEVBUF); 1827 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1828 break; 1829 } 1830 pil_prev = &pil->pil_next; 1831 } 1832 1833 if (sc->sc_pil == NULL) { 1834 /* No interrupt handlers */ 1835 1836 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1837 1838 /* stop routing PCI intr */ 1839 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1840 reg |= CB_BCR_INTR_IREQ_ENABLE; 1841 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1842 1843 switch (sc->sc_chipset) { 1844 case CB_TI113X: 1845 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1846 /* functional intr disabled */ 1847 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1848 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1849 break; 1850 default: 1851 break; 1852 } 1853 } 1854 } 1855 1856 #if defined SHOW_REGS 1857 static void 1858 cb_show_regs(pc, tag, memt, memh) 1859 pci_chipset_tag_t pc; 1860 pcitag_t tag; 1861 bus_space_tag_t memt; 1862 bus_space_handle_t memh; 1863 { 1864 int i; 1865 printf("PCI config regs:"); 1866 for (i = 0; i < 0x50; i += 4) { 1867 if (i % 16 == 0) { 1868 printf("\n 0x%02x:", i); 1869 } 1870 printf(" %08x", pci_conf_read(pc, tag, i)); 1871 } 1872 for (i = 0x80; i < 0xb0; i += 4) { 1873 if (i % 16 == 0) { 1874 printf("\n 0x%02x:", i); 1875 } 1876 printf(" %08x", pci_conf_read(pc, tag, i)); 1877 } 1878 1879 if (memh == 0) { 1880 printf("\n"); 1881 return; 1882 } 1883 1884 printf("\nsocket regs:"); 1885 for (i = 0; i <= 0x10; i += 0x04) { 1886 printf(" %08x", bus_space_read_4(memt, memh, i)); 1887 } 1888 printf("\nExCA regs:"); 1889 for (i = 0; i < 0x08; ++i) { 1890 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1891 } 1892 printf("\n"); 1893 return; 1894 } 1895 #endif 1896 1897 /* 1898 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1899 * int busno, int devno, int function) 1900 * This is the function to make a tag to access config space of 1901 * a CardBus Card. It works same as pci_conf_read. 1902 */ 1903 static cardbustag_t 1904 pccbb_make_tag(cc, busno, devno, function) 1905 cardbus_chipset_tag_t cc; 1906 int busno, devno, function; 1907 { 1908 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1909 1910 return pci_make_tag(sc->sc_pc, busno, devno, function); 1911 } 1912 1913 static void 1914 pccbb_free_tag(cc, tag) 1915 cardbus_chipset_tag_t cc; 1916 cardbustag_t tag; 1917 { 1918 } 1919 1920 /* 1921 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1922 * cardbustag_t tag, int offset) 1923 * This is the function to read the config space of a CardBus Card. 1924 * It works same as pci_conf_read. 1925 */ 1926 static cardbusreg_t 1927 pccbb_conf_read(cc, tag, offset) 1928 cardbus_chipset_tag_t cc; 1929 cardbustag_t tag; 1930 int offset; /* register offset */ 1931 { 1932 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1933 1934 return pci_conf_read(sc->sc_pc, tag, offset); 1935 } 1936 1937 /* 1938 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1939 * int offs, cardbusreg_t val) 1940 * This is the function to write the config space of a CardBus Card. 1941 * It works same as pci_conf_write. 1942 */ 1943 static void 1944 pccbb_conf_write(cc, tag, reg, val) 1945 cardbus_chipset_tag_t cc; 1946 cardbustag_t tag; 1947 int reg; /* register offset */ 1948 cardbusreg_t val; 1949 { 1950 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1951 1952 pci_conf_write(sc->sc_pc, tag, reg, val); 1953 } 1954 1955 #if 0 1956 STATIC int 1957 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1958 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1959 int speed, int flags, 1960 bus_space_handle_t * iohp) 1961 #endif 1962 /* 1963 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1964 * bus_addr_t start, bus_size_t size, 1965 * bus_size_t align, 1966 * struct pcmcia_io_handle *pcihp 1967 * 1968 * This function only allocates I/O region for pccard. This function 1969 * never maps the allocated region to pccard I/O area. 1970 * 1971 * XXX: The interface of this function is not very good, I believe. 1972 */ 1973 STATIC int 1974 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1975 pcmcia_chipset_handle_t pch; 1976 bus_addr_t start; /* start address */ 1977 bus_size_t size; 1978 bus_size_t align; 1979 struct pcmcia_io_handle *pcihp; 1980 { 1981 struct pcic_handle *ph = (struct pcic_handle *)pch; 1982 bus_addr_t ioaddr; 1983 int flags = 0; 1984 bus_space_tag_t iot; 1985 bus_space_handle_t ioh; 1986 bus_addr_t mask; 1987 #if rbus 1988 rbus_tag_t rb; 1989 #endif 1990 if (align == 0) { 1991 align = size; /* XXX: funny??? */ 1992 } 1993 1994 if (start != 0) { 1995 /* XXX: assume all card decode lower 10 bits by its hardware */ 1996 mask = 0x3ff; 1997 } else { 1998 /* 1999 * calculate mask: 2000 * 1. get the most significant bit of size (call it msb). 2001 * 2. compare msb with the value of size. 2002 * 3. if size is larger, shift msb left once. 2003 * 4. obtain mask value to decrement msb. 2004 */ 2005 bus_size_t size_tmp = size; 2006 int shifts = 0; 2007 2008 mask = 1; 2009 while (size_tmp) { 2010 ++shifts; 2011 size_tmp >>= 1; 2012 } 2013 mask = (1 << shifts); 2014 if (mask < size) { 2015 mask <<= 1; 2016 } 2017 --mask; 2018 } 2019 2020 /* 2021 * Allocate some arbitrary I/O space. 2022 */ 2023 2024 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2025 2026 #if rbus 2027 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2028 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2029 return 1; 2030 } 2031 #else 2032 if (start) { 2033 ioaddr = start; 2034 if (bus_space_map(iot, start, size, 0, &ioh)) { 2035 return 1; 2036 } 2037 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2038 (u_long) ioaddr, (u_long) size)); 2039 } else { 2040 flags |= PCMCIA_IO_ALLOCATED; 2041 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2042 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2043 size, align, 0, 0, &ioaddr, &ioh)) { 2044 /* No room be able to be get. */ 2045 return 1; 2046 } 2047 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2048 (u_long) ioaddr, (u_long) size)); 2049 } 2050 #endif 2051 2052 pcihp->iot = iot; 2053 pcihp->ioh = ioh; 2054 pcihp->addr = ioaddr; 2055 pcihp->size = size; 2056 pcihp->flags = flags; 2057 2058 return 0; 2059 } 2060 2061 /* 2062 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2063 * struct pcmcia_io_handle *pcihp) 2064 * 2065 * This function only frees I/O region for pccard. 2066 * 2067 * XXX: The interface of this function is not very good, I believe. 2068 */ 2069 void 2070 pccbb_pcmcia_io_free(pch, pcihp) 2071 pcmcia_chipset_handle_t pch; 2072 struct pcmcia_io_handle *pcihp; 2073 { 2074 #if !rbus 2075 bus_space_tag_t iot = pcihp->iot; 2076 #endif 2077 bus_space_handle_t ioh = pcihp->ioh; 2078 bus_size_t size = pcihp->size; 2079 2080 #if rbus 2081 struct pccbb_softc *sc = 2082 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2083 rbus_tag_t rb = sc->sc_rbus_iot; 2084 2085 rbus_space_free(rb, ioh, size, NULL); 2086 #else 2087 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2088 bus_space_free(iot, ioh, size); 2089 else 2090 bus_space_unmap(iot, ioh, size); 2091 #endif 2092 } 2093 2094 /* 2095 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2096 * bus_addr_t offset, bus_size_t size, 2097 * struct pcmcia_io_handle *pcihp, 2098 * int *windowp) 2099 * 2100 * This function maps the allocated I/O region to pccard. This function 2101 * never allocates any I/O region for pccard I/O area. I don't 2102 * understand why the original authors of pcmciabus separated alloc and 2103 * map. I believe the two must be unite. 2104 * 2105 * XXX: no wait timing control? 2106 */ 2107 int 2108 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2109 pcmcia_chipset_handle_t pch; 2110 int width; 2111 bus_addr_t offset; 2112 bus_size_t size; 2113 struct pcmcia_io_handle *pcihp; 2114 int *windowp; 2115 { 2116 struct pcic_handle *ph = (struct pcic_handle *)pch; 2117 bus_addr_t ioaddr = pcihp->addr + offset; 2118 int i, win; 2119 #if defined CBB_DEBUG 2120 static char *width_names[] = { "dynamic", "io8", "io16" }; 2121 #endif 2122 2123 /* Sanity check I/O handle. */ 2124 2125 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2126 panic("pccbb_pcmcia_io_map iot is bogus"); 2127 } 2128 2129 /* XXX Sanity check offset/size. */ 2130 2131 win = -1; 2132 for (i = 0; i < PCIC_IO_WINS; i++) { 2133 if ((ph->ioalloc & (1 << i)) == 0) { 2134 win = i; 2135 ph->ioalloc |= (1 << i); 2136 break; 2137 } 2138 } 2139 2140 if (win == -1) { 2141 return 1; 2142 } 2143 2144 *windowp = win; 2145 2146 /* XXX this is pretty gross */ 2147 2148 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2149 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2150 2151 /* XXX wtf is this doing here? */ 2152 2153 #if 0 2154 printf(" port 0x%lx", (u_long) ioaddr); 2155 if (size > 1) { 2156 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2157 } 2158 #endif 2159 2160 ph->io[win].addr = ioaddr; 2161 ph->io[win].size = size; 2162 ph->io[win].width = width; 2163 2164 /* actual dirty register-value changing in the function below. */ 2165 pccbb_pcmcia_do_io_map(ph, win); 2166 2167 return 0; 2168 } 2169 2170 /* 2171 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2172 * 2173 * This function changes register-value to map I/O region for pccard. 2174 */ 2175 static void 2176 pccbb_pcmcia_do_io_map(ph, win) 2177 struct pcic_handle *ph; 2178 int win; 2179 { 2180 static u_int8_t pcic_iowidth[3] = { 2181 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2182 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2183 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2184 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2185 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2186 }; 2187 2188 #define PCIC_SIA_START_LOW 0 2189 #define PCIC_SIA_START_HIGH 1 2190 #define PCIC_SIA_STOP_LOW 2 2191 #define PCIC_SIA_STOP_HIGH 3 2192 2193 int regbase_win = 0x8 + win * 0x04; 2194 u_int8_t ioctl, enable; 2195 2196 DPRINTF( 2197 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2198 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2199 ph->io[win].width * 8)); 2200 2201 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2202 ph->io[win].addr & 0xff); 2203 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2204 (ph->io[win].addr >> 8) & 0xff); 2205 2206 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2207 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2208 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2209 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2210 2211 ioctl = Pcic_read(ph, PCIC_IOCTL); 2212 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2213 switch (win) { 2214 case 0: 2215 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2216 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2217 PCIC_IOCTL_IO0_DATASIZE_MASK); 2218 ioctl |= pcic_iowidth[ph->io[win].width]; 2219 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2220 break; 2221 case 1: 2222 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2223 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2224 PCIC_IOCTL_IO1_DATASIZE_MASK); 2225 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2226 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2227 break; 2228 } 2229 Pcic_write(ph, PCIC_IOCTL, ioctl); 2230 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2231 #if defined CBB_DEBUG 2232 { 2233 u_int8_t start_low = 2234 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2235 u_int8_t start_high = 2236 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2237 u_int8_t stop_low = 2238 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2239 u_int8_t stop_high = 2240 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2241 printf 2242 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2243 start_low, start_high, stop_low, stop_high, ioctl, enable); 2244 } 2245 #endif 2246 } 2247 2248 /* 2249 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2250 * 2251 * This function unmaps I/O region. No return value. 2252 */ 2253 STATIC void 2254 pccbb_pcmcia_io_unmap(pch, win) 2255 pcmcia_chipset_handle_t pch; 2256 int win; 2257 { 2258 struct pcic_handle *ph = (struct pcic_handle *)pch; 2259 int reg; 2260 2261 if (win >= PCIC_IO_WINS || win < 0) { 2262 panic("pccbb_pcmcia_io_unmap: window out of range"); 2263 } 2264 2265 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2266 switch (win) { 2267 case 0: 2268 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2269 break; 2270 case 1: 2271 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2272 break; 2273 } 2274 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2275 2276 ph->ioalloc &= ~(1 << win); 2277 } 2278 2279 /* 2280 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2281 * 2282 * This function enables the card. All information is stored in 2283 * the first argument, pcmcia_chipset_handle_t. 2284 */ 2285 static void 2286 pccbb_pcmcia_wait_ready(ph) 2287 struct pcic_handle *ph; 2288 { 2289 int i; 2290 2291 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2292 Pcic_read(ph, PCIC_IF_STATUS))); 2293 2294 for (i = 0; i < 2000; i++) { 2295 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2296 return; 2297 } 2298 DELAY_MS(2, ph->ph_parent); 2299 #ifdef CBB_DEBUG 2300 if ((i > 1000) && (i % 25 == 24)) 2301 printf("."); 2302 #endif 2303 } 2304 2305 #ifdef DIAGNOSTIC 2306 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2307 Pcic_read(ph, PCIC_IF_STATUS)); 2308 #endif 2309 } 2310 2311 /* 2312 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2313 * 2314 * This function enables the card. All information is stored in 2315 * the first argument, pcmcia_chipset_handle_t. 2316 */ 2317 STATIC void 2318 pccbb_pcmcia_socket_enable(pch) 2319 pcmcia_chipset_handle_t pch; 2320 { 2321 struct pcic_handle *ph = (struct pcic_handle *)pch; 2322 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2323 int cardtype, win; 2324 u_int8_t power, intr; 2325 pcireg_t spsr; 2326 int voltage; 2327 2328 /* this bit is mostly stolen from pcic_attach_card */ 2329 2330 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2331 2332 /* get card Vcc info */ 2333 2334 spsr = 2335 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2336 CB_SOCKET_STAT); 2337 if (spsr & CB_SOCKET_STAT_5VCARD) { 2338 DPRINTF(("5V card\n")); 2339 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2340 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2341 DPRINTF(("3V card\n")); 2342 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2343 } else { 2344 printf("?V card, 0x%x\n", spsr); /* XXX */ 2345 return; 2346 } 2347 2348 /* disable socket: negate output enable bit and power off */ 2349 2350 power = 0; 2351 Pcic_write(ph, PCIC_PWRCTL, power); 2352 2353 /* power down the socket to reset it, clear the card reset pin */ 2354 2355 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2356 2357 /* 2358 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2359 * we are changing Vcc (Toff). 2360 */ 2361 /* delay(300*1000); too much */ 2362 2363 /* assert reset bit */ 2364 intr = Pcic_read(ph, PCIC_INTR); 2365 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2366 Pcic_write(ph, PCIC_INTR, intr); 2367 2368 /* power up the socket and output enable */ 2369 power = Pcic_read(ph, PCIC_PWRCTL); 2370 power |= PCIC_PWRCTL_OE; 2371 Pcic_write(ph, PCIC_PWRCTL, power); 2372 pccbb_power(sc, voltage); 2373 2374 /* 2375 * hold RESET at least 20 ms: the spec says only 10 us is 2376 * enough, but TI1130 requires at least 20 ms. 2377 */ 2378 #if 0 /* XXX called on interrupt context */ 2379 DELAY_MS(20, sc); 2380 #else 2381 delay(20 * 1000); 2382 #endif 2383 2384 /* clear the reset flag */ 2385 2386 intr |= PCIC_INTR_RESET; 2387 Pcic_write(ph, PCIC_INTR, intr); 2388 2389 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2390 2391 #if 0 /* XXX called on interrupt context */ 2392 DELAY_MS(20, sc); 2393 #else 2394 delay(20 * 1000); 2395 #endif 2396 2397 /* wait for the chip to finish initializing */ 2398 2399 pccbb_pcmcia_wait_ready(ph); 2400 2401 /* zero out the address windows */ 2402 2403 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2404 2405 /* set the card type */ 2406 2407 cardtype = pcmcia_card_gettype(ph->pcmcia); 2408 2409 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2410 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2411 Pcic_write(ph, PCIC_INTR, intr); 2412 2413 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2414 ph->ph_parent->dv_xname, ph->sock, 2415 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2416 2417 /* reinstall all the memory and io mappings */ 2418 2419 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2420 if (ph->memalloc & (1 << win)) { 2421 pccbb_pcmcia_do_mem_map(ph, win); 2422 } 2423 } 2424 2425 for (win = 0; win < PCIC_IO_WINS; ++win) { 2426 if (ph->ioalloc & (1 << win)) { 2427 pccbb_pcmcia_do_io_map(ph, win); 2428 } 2429 } 2430 } 2431 2432 /* 2433 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2434 * 2435 * This function disables the card. All information is stored in 2436 * the first argument, pcmcia_chipset_handle_t. 2437 */ 2438 STATIC void 2439 pccbb_pcmcia_socket_disable(pch) 2440 pcmcia_chipset_handle_t pch; 2441 { 2442 struct pcic_handle *ph = (struct pcic_handle *)pch; 2443 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2444 u_int8_t power, intr; 2445 2446 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2447 2448 /* reset signal asserting... */ 2449 2450 intr = Pcic_read(ph, PCIC_INTR); 2451 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2452 Pcic_write(ph, PCIC_INTR, intr); 2453 delay(2 * 1000); 2454 2455 /* power down the socket */ 2456 power = Pcic_read(ph, PCIC_PWRCTL); 2457 power &= ~PCIC_PWRCTL_OE; 2458 Pcic_write(ph, PCIC_PWRCTL, power); 2459 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2460 /* 2461 * wait 300ms until power fails (Tpf). 2462 */ 2463 #if 0 /* XXX called on interrupt context */ 2464 DELAY_MS(300, sc); 2465 #else 2466 delay(300 * 1000); 2467 #endif 2468 } 2469 2470 /* 2471 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2472 * 2473 * This function detects whether a card is in the slot or not. 2474 * If a card is inserted, return 1. Otherwise, return 0. 2475 */ 2476 STATIC int 2477 pccbb_pcmcia_card_detect(pch) 2478 pcmcia_chipset_handle_t pch; 2479 { 2480 struct pcic_handle *ph = (struct pcic_handle *)pch; 2481 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2482 2483 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2484 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2485 } 2486 2487 #if 0 2488 STATIC int 2489 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2490 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2491 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2492 #endif 2493 /* 2494 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2495 * bus_size_t size, 2496 * struct pcmcia_mem_handle *pcmhp) 2497 * 2498 * This function only allocates memory region for pccard. This 2499 * function never maps the allocated region to pccard memory area. 2500 * 2501 * XXX: Why the argument of start address is not in? 2502 */ 2503 STATIC int 2504 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2505 pcmcia_chipset_handle_t pch; 2506 bus_size_t size; 2507 struct pcmcia_mem_handle *pcmhp; 2508 { 2509 struct pcic_handle *ph = (struct pcic_handle *)pch; 2510 bus_space_handle_t memh; 2511 bus_addr_t addr; 2512 bus_size_t sizepg; 2513 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2514 #if rbus 2515 rbus_tag_t rb; 2516 #endif 2517 2518 /* out of sc->memh, allocate as many pages as necessary */ 2519 2520 /* convert size to PCIC pages */ 2521 /* 2522 * This is not enough; when the requested region is on the page 2523 * boundaries, this may calculate wrong result. 2524 */ 2525 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2526 #if 0 2527 if (sizepg > PCIC_MAX_MEM_PAGES) { 2528 return 1; 2529 } 2530 #endif 2531 2532 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2533 return 1; 2534 } 2535 2536 addr = 0; /* XXX gcc -Wuninitialized */ 2537 2538 #if rbus 2539 rb = sc->sc_rbus_memt; 2540 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2541 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2542 &addr, &memh)) { 2543 return 1; 2544 } 2545 #else 2546 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2547 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2548 0, /* boundary */ 2549 0, /* flags */ 2550 &addr, &memh)) { 2551 return 1; 2552 } 2553 #endif 2554 2555 DPRINTF( 2556 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2557 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2558 2559 pcmhp->memt = sc->sc_memt; 2560 pcmhp->memh = memh; 2561 pcmhp->addr = addr; 2562 pcmhp->size = size; 2563 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2564 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2565 pcmhp->mhandle = 0; 2566 /* No offset??? Funny. */ 2567 2568 return 0; 2569 } 2570 2571 /* 2572 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2573 * struct pcmcia_mem_handle *pcmhp) 2574 * 2575 * This function release the memory space allocated by the function 2576 * pccbb_pcmcia_mem_alloc(). 2577 */ 2578 STATIC void 2579 pccbb_pcmcia_mem_free(pch, pcmhp) 2580 pcmcia_chipset_handle_t pch; 2581 struct pcmcia_mem_handle *pcmhp; 2582 { 2583 #if rbus 2584 struct pcic_handle *ph = (struct pcic_handle *)pch; 2585 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2586 2587 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2588 #else 2589 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2590 #endif 2591 } 2592 2593 /* 2594 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2595 * 2596 * This function release the memory space allocated by the function 2597 * pccbb_pcmcia_mem_alloc(). 2598 */ 2599 STATIC void 2600 pccbb_pcmcia_do_mem_map(ph, win) 2601 struct pcic_handle *ph; 2602 int win; 2603 { 2604 int regbase_win; 2605 bus_addr_t phys_addr; 2606 bus_addr_t phys_end; 2607 2608 #define PCIC_SMM_START_LOW 0 2609 #define PCIC_SMM_START_HIGH 1 2610 #define PCIC_SMM_STOP_LOW 2 2611 #define PCIC_SMM_STOP_HIGH 3 2612 #define PCIC_CMA_LOW 4 2613 #define PCIC_CMA_HIGH 5 2614 2615 u_int8_t start_low, start_high = 0; 2616 u_int8_t stop_low, stop_high; 2617 u_int8_t off_low, off_high; 2618 u_int8_t mem_window; 2619 int reg; 2620 2621 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2622 int mem8 = 2623 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2624 || (kind == PCMCIA_MEM_ATTR); 2625 2626 regbase_win = 0x10 + win * 0x08; 2627 2628 phys_addr = ph->mem[win].addr; 2629 phys_end = phys_addr + ph->mem[win].size; 2630 2631 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2632 phys_addr, phys_end, ph->mem[win].offset)); 2633 2634 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2635 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2636 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2637 2638 /* bit 19:12 */ 2639 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2640 /* bit 23:20 and bit 7 on */ 2641 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2642 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2643 /* bit 31:24, for 32-bit address */ 2644 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2645 2646 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2647 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2648 2649 if (((struct pccbb_softc *)ph-> 2650 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2651 Pcic_write(ph, 0x40 + win, mem_window); 2652 } 2653 2654 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2655 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2656 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2657 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2658 2659 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2660 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2661 2662 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2663 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2664 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2665 | ((kind == PCMCIA_MEM_ATTR) ? 2666 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2667 2668 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2669 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2670 2671 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2672 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2673 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2674 2675 #if defined CBB_DEBUG 2676 { 2677 int r1, r2, r3, r4, r5, r6, r7 = 0; 2678 2679 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2680 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2681 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2682 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2683 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2684 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2685 if (((struct pccbb_softc *)(ph-> 2686 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2687 r7 = Pcic_read(ph, 0x40 + win); 2688 } 2689 2690 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2691 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2692 if (((struct pccbb_softc *)(ph-> 2693 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2694 DPRINTF((" %02x", r7)); 2695 } 2696 DPRINTF(("\n")); 2697 } 2698 #endif 2699 } 2700 2701 /* 2702 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2703 * bus_addr_t card_addr, bus_size_t size, 2704 * struct pcmcia_mem_handle *pcmhp, 2705 * bus_addr_t *offsetp, int *windowp) 2706 * 2707 * This function maps memory space allocated by the function 2708 * pccbb_pcmcia_mem_alloc(). 2709 */ 2710 STATIC int 2711 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2712 pcmcia_chipset_handle_t pch; 2713 int kind; 2714 bus_addr_t card_addr; 2715 bus_size_t size; 2716 struct pcmcia_mem_handle *pcmhp; 2717 bus_addr_t *offsetp; 2718 int *windowp; 2719 { 2720 struct pcic_handle *ph = (struct pcic_handle *)pch; 2721 bus_addr_t busaddr; 2722 long card_offset; 2723 int win; 2724 2725 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2726 if ((ph->memalloc & (1 << win)) == 0) { 2727 ph->memalloc |= (1 << win); 2728 break; 2729 } 2730 } 2731 2732 if (win == PCIC_MEM_WINS) { 2733 return 1; 2734 } 2735 2736 *windowp = win; 2737 2738 /* XXX this is pretty gross */ 2739 2740 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2741 panic("pccbb_pcmcia_mem_map memt is bogus"); 2742 } 2743 2744 busaddr = pcmhp->addr; 2745 2746 /* 2747 * compute the address offset to the pcmcia address space for the 2748 * pcic. this is intentionally signed. The masks and shifts below 2749 * will cause TRT to happen in the pcic registers. Deal with making 2750 * sure the address is aligned, and return the alignment offset. 2751 */ 2752 2753 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2754 card_addr -= *offsetp; 2755 2756 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2757 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2758 (u_long) card_addr)); 2759 2760 /* 2761 * include the offset in the size, and decrement size by one, since 2762 * the hw wants start/stop 2763 */ 2764 size += *offsetp - 1; 2765 2766 card_offset = (((long)card_addr) - ((long)busaddr)); 2767 2768 ph->mem[win].addr = busaddr; 2769 ph->mem[win].size = size; 2770 ph->mem[win].offset = card_offset; 2771 ph->mem[win].kind = kind; 2772 2773 pccbb_pcmcia_do_mem_map(ph, win); 2774 2775 return 0; 2776 } 2777 2778 /* 2779 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2780 * int window) 2781 * 2782 * This function unmaps memory space which mapped by the function 2783 * pccbb_pcmcia_mem_map(). 2784 */ 2785 STATIC void 2786 pccbb_pcmcia_mem_unmap(pch, window) 2787 pcmcia_chipset_handle_t pch; 2788 int window; 2789 { 2790 struct pcic_handle *ph = (struct pcic_handle *)pch; 2791 int reg; 2792 2793 if (window >= PCIC_MEM_WINS) { 2794 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2795 } 2796 2797 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2798 reg &= ~(1 << window); 2799 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2800 2801 ph->memalloc &= ~(1 << window); 2802 } 2803 2804 #if defined PCCBB_PCMCIA_POLL 2805 struct pccbb_poll_str { 2806 void *arg; 2807 int (*func) __P((void *)); 2808 int level; 2809 struct pcic_handle *ph; 2810 int count; 2811 int num; 2812 struct callout poll_ch; 2813 }; 2814 2815 static struct pccbb_poll_str pccbb_poll[10]; 2816 static int pccbb_poll_n = 0; 2817 2818 static void pccbb_pcmcia_poll __P((void *arg)); 2819 2820 static void 2821 pccbb_pcmcia_poll(arg) 2822 void *arg; 2823 { 2824 struct pccbb_poll_str *poll = arg; 2825 struct pcic_handle *ph = poll->ph; 2826 struct pccbb_softc *sc = ph->sc; 2827 int s; 2828 u_int32_t spsr; /* socket present-state reg */ 2829 2830 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2831 switch (poll->level) { 2832 case IPL_NET: 2833 s = splnet(); 2834 break; 2835 case IPL_BIO: 2836 s = splbio(); 2837 break; 2838 case IPL_TTY: /* fallthrough */ 2839 default: 2840 s = spltty(); 2841 break; 2842 } 2843 2844 spsr = 2845 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2846 CB_SOCKET_STAT); 2847 2848 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2849 if (!(spsr & 0x40)) /* CINT low */ 2850 #else 2851 if (1) 2852 #endif 2853 { 2854 if ((*poll->func) (poll->arg) > 0) { 2855 ++poll->count; 2856 // printf("intr: reported from poller, 0x%x\n", spsr); 2857 #if defined LEVEL2 2858 } else { 2859 printf("intr: miss! 0x%x\n", spsr); 2860 #endif 2861 } 2862 } 2863 splx(s); 2864 } 2865 #endif /* defined CB_PCMCIA_POLL */ 2866 2867 /* 2868 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2869 * struct pcmcia_function *pf, 2870 * int ipl, 2871 * int (*func)(void *), 2872 * void *arg); 2873 * 2874 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2875 */ 2876 STATIC void * 2877 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2878 pcmcia_chipset_handle_t pch; 2879 struct pcmcia_function *pf; 2880 int ipl; 2881 int (*func) __P((void *)); 2882 void *arg; 2883 { 2884 struct pcic_handle *ph = (struct pcic_handle *)pch; 2885 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2886 2887 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2888 /* what should I do? */ 2889 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2890 DPRINTF( 2891 ("%s does not provide edge nor pulse interrupt\n", 2892 sc->sc_dev.dv_xname)); 2893 return NULL; 2894 } 2895 /* 2896 * XXX Noooooo! The interrupt flag must set properly!! 2897 * dumb pcmcia driver!! 2898 */ 2899 } 2900 2901 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2902 } 2903 2904 /* 2905 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2906 * void *ih) 2907 * 2908 * This function disables PC-Card interrupt. 2909 */ 2910 STATIC void 2911 pccbb_pcmcia_intr_disestablish(pch, ih) 2912 pcmcia_chipset_handle_t pch; 2913 void *ih; 2914 { 2915 struct pcic_handle *ph = (struct pcic_handle *)pch; 2916 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2917 2918 pccbb_intr_disestablish(sc, ih); 2919 } 2920 2921 #if rbus 2922 /* 2923 * static int 2924 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2925 * bus_addr_t addr, bus_size_t size, 2926 * bus_addr_t mask, bus_size_t align, 2927 * int flags, bus_addr_t *addrp; 2928 * bus_space_handle_t *bshp) 2929 * 2930 * This function allocates a portion of memory or io space for 2931 * clients. This function is called from CardBus card drivers. 2932 */ 2933 static int 2934 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2935 cardbus_chipset_tag_t ct; 2936 rbus_tag_t rb; 2937 bus_addr_t addr; 2938 bus_size_t size; 2939 bus_addr_t mask; 2940 bus_size_t align; 2941 int flags; 2942 bus_addr_t *addrp; 2943 bus_space_handle_t *bshp; 2944 { 2945 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2946 2947 DPRINTF( 2948 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2949 addr, size, mask, align)); 2950 2951 if (align == 0) { 2952 align = size; 2953 } 2954 2955 if (rb->rb_bt == sc->sc_memt) { 2956 if (align < 16) { 2957 return 1; 2958 } 2959 if (align < 0x1000) { 2960 align = 0x1000; 2961 } 2962 } else if (rb->rb_bt == sc->sc_iot) { 2963 if (align < 4) { 2964 return 1; 2965 } 2966 /* XXX: hack for avoiding ISA image */ 2967 if (mask < 0x0100) { 2968 mask = 0x3ff; 2969 addr = 0x300; 2970 } 2971 2972 } else { 2973 DPRINTF( 2974 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 2975 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 2976 return 1; 2977 /* XXX: panic here? */ 2978 } 2979 2980 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2981 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2982 return 1; 2983 } 2984 2985 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2986 2987 return 0; 2988 } 2989 2990 /* 2991 * static int 2992 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2993 * bus_space_handle_t *bshp, bus_size_t size); 2994 * 2995 * This function is called from CardBus card drivers. 2996 */ 2997 static int 2998 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2999 cardbus_chipset_tag_t ct; 3000 rbus_tag_t rb; 3001 bus_space_handle_t bsh; 3002 bus_size_t size; 3003 { 3004 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3005 bus_space_tag_t bt = rb->rb_bt; 3006 3007 pccbb_close_win(sc, bt, bsh, size); 3008 3009 if (bt == sc->sc_memt) { 3010 } else if (bt == sc->sc_iot) { 3011 } else { 3012 return 1; 3013 /* XXX: panic here? */ 3014 } 3015 3016 return rbus_space_free(rb, bsh, size, NULL); 3017 } 3018 #endif /* rbus */ 3019 3020 #if rbus 3021 3022 static int 3023 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3024 struct pccbb_softc *sc; 3025 bus_space_tag_t bst; 3026 bus_addr_t addr; 3027 bus_size_t size; 3028 bus_space_handle_t bsh; 3029 int flags; 3030 { 3031 struct pccbb_win_chain_head *head; 3032 bus_addr_t align; 3033 3034 head = &sc->sc_iowindow; 3035 align = 0x04; 3036 if (sc->sc_memt == bst) { 3037 head = &sc->sc_memwindow; 3038 align = 0x1000; 3039 DPRINTF(("using memory window, %x %x %x\n\n", 3040 sc->sc_iot, sc->sc_memt, bst)); 3041 } 3042 3043 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3044 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3045 sc->sc_dev.dv_xname, 3046 (head == &sc->sc_memwindow) ? "mem" : "io"); 3047 } 3048 pccbb_winset(align, sc, bst); 3049 3050 return 0; 3051 } 3052 3053 static int 3054 pccbb_close_win(sc, bst, bsh, size) 3055 struct pccbb_softc *sc; 3056 bus_space_tag_t bst; 3057 bus_space_handle_t bsh; 3058 bus_size_t size; 3059 { 3060 struct pccbb_win_chain_head *head; 3061 bus_addr_t align; 3062 3063 head = &sc->sc_iowindow; 3064 align = 0x04; 3065 if (sc->sc_memt == bst) { 3066 head = &sc->sc_memwindow; 3067 align = 0x1000; 3068 } 3069 3070 if (pccbb_winlist_delete(head, bsh, size)) { 3071 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3072 sc->sc_dev.dv_xname, 3073 (head == &sc->sc_memwindow) ? "mem" : "io"); 3074 } 3075 pccbb_winset(align, sc, bst); 3076 3077 return 0; 3078 } 3079 3080 static int 3081 pccbb_winlist_insert(head, start, size, bsh, flags) 3082 struct pccbb_win_chain_head *head; 3083 bus_addr_t start; 3084 bus_size_t size; 3085 bus_space_handle_t bsh; 3086 int flags; 3087 { 3088 struct pccbb_win_chain *chainp, *elem; 3089 3090 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3091 M_NOWAIT)) == NULL) 3092 return (1); /* fail */ 3093 3094 elem->wc_start = start; 3095 elem->wc_end = start + (size - 1); 3096 elem->wc_handle = bsh; 3097 elem->wc_flags = flags; 3098 3099 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3100 chainp = TAILQ_NEXT(chainp, wc_list)) { 3101 if (chainp->wc_end < start) 3102 continue; 3103 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3104 return (0); 3105 } 3106 3107 TAILQ_INSERT_TAIL(head, elem, wc_list); 3108 return (0); 3109 } 3110 3111 static int 3112 pccbb_winlist_delete(head, bsh, size) 3113 struct pccbb_win_chain_head *head; 3114 bus_space_handle_t bsh; 3115 bus_size_t size; 3116 { 3117 struct pccbb_win_chain *chainp; 3118 3119 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3120 chainp = TAILQ_NEXT(chainp, wc_list)) { 3121 if (chainp->wc_handle != bsh) 3122 continue; 3123 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3124 printf("pccbb_winlist_delete: window 0x%lx size " 3125 "inconsistent: 0x%lx, 0x%lx\n", 3126 (unsigned long)chainp->wc_start, 3127 (unsigned long)(chainp->wc_end - chainp->wc_start), 3128 (unsigned long)(size - 1)); 3129 return 1; 3130 } 3131 3132 TAILQ_REMOVE(head, chainp, wc_list); 3133 free(chainp, M_DEVBUF); 3134 3135 return 0; 3136 } 3137 3138 return 1; /* fail: no candidate to remove */ 3139 } 3140 3141 static void 3142 pccbb_winset(align, sc, bst) 3143 bus_addr_t align; 3144 struct pccbb_softc *sc; 3145 bus_space_tag_t bst; 3146 { 3147 pci_chipset_tag_t pc; 3148 pcitag_t tag; 3149 bus_addr_t mask = ~(align - 1); 3150 struct { 3151 cardbusreg_t win_start; 3152 cardbusreg_t win_limit; 3153 int win_flags; 3154 } win[2]; 3155 struct pccbb_win_chain *chainp; 3156 int offs; 3157 3158 win[0].win_start = win[1].win_start = 0xffffffff; 3159 win[0].win_limit = win[1].win_limit = 0; 3160 win[0].win_flags = win[1].win_flags = 0; 3161 3162 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3163 offs = 0x2c; 3164 if (sc->sc_memt == bst) { 3165 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3166 offs = 0x1c; 3167 } 3168 3169 if (chainp != NULL) { 3170 win[0].win_start = chainp->wc_start & mask; 3171 win[0].win_limit = chainp->wc_end & mask; 3172 win[0].win_flags = chainp->wc_flags; 3173 chainp = TAILQ_NEXT(chainp, wc_list); 3174 } 3175 3176 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3177 if (win[1].win_start == 0xffffffff) { 3178 /* window 1 is not used */ 3179 if ((win[0].win_flags == chainp->wc_flags) && 3180 (win[0].win_limit + align >= 3181 (chainp->wc_start & mask))) { 3182 /* concatenate */ 3183 win[0].win_limit = chainp->wc_end & mask; 3184 } else { 3185 /* make new window */ 3186 win[1].win_start = chainp->wc_start & mask; 3187 win[1].win_limit = chainp->wc_end & mask; 3188 win[1].win_flags = chainp->wc_flags; 3189 } 3190 continue; 3191 } 3192 3193 /* Both windows are engaged. */ 3194 if (win[0].win_flags == win[1].win_flags) { 3195 /* same flags */ 3196 if (win[0].win_flags == chainp->wc_flags) { 3197 if (win[1].win_start - (win[0].win_limit + 3198 align) < 3199 (chainp->wc_start & mask) - 3200 ((chainp->wc_end & mask) + align)) { 3201 /* 3202 * merge window 0 and 1, and set win1 3203 * to chainp 3204 */ 3205 win[0].win_limit = win[1].win_limit; 3206 win[1].win_start = 3207 chainp->wc_start & mask; 3208 win[1].win_limit = 3209 chainp->wc_end & mask; 3210 } else { 3211 win[1].win_limit = 3212 chainp->wc_end & mask; 3213 } 3214 } else { 3215 /* different flags */ 3216 3217 /* concatenate win0 and win1 */ 3218 win[0].win_limit = win[1].win_limit; 3219 /* allocate win[1] to new space */ 3220 win[1].win_start = chainp->wc_start & mask; 3221 win[1].win_limit = chainp->wc_end & mask; 3222 win[1].win_flags = chainp->wc_flags; 3223 } 3224 } else { 3225 /* the flags of win[0] and win[1] is different */ 3226 if (win[0].win_flags == chainp->wc_flags) { 3227 win[0].win_limit = chainp->wc_end & mask; 3228 /* 3229 * XXX this creates overlapping windows, so 3230 * what should the poor bridge do if one is 3231 * cachable, and the other is not? 3232 */ 3233 printf("%s: overlapping windows\n", 3234 sc->sc_dev.dv_xname); 3235 } else { 3236 win[1].win_limit = chainp->wc_end & mask; 3237 } 3238 } 3239 } 3240 3241 pc = sc->sc_pc; 3242 tag = sc->sc_tag; 3243 pci_conf_write(pc, tag, offs, win[0].win_start); 3244 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3245 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3246 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3247 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3248 pci_conf_read(pc, tag, offs), 3249 pci_conf_read(pc, tag, offs + 4) + align, 3250 pci_conf_read(pc, tag, offs + 8), 3251 pci_conf_read(pc, tag, offs + 12) + align)); 3252 3253 if (bst == sc->sc_memt) { 3254 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3255 3256 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3257 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3258 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3259 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3260 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3261 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3262 } 3263 } 3264 3265 #endif /* rbus */ 3266 3267 static void 3268 pccbb_powerhook(why, arg) 3269 int why; 3270 void *arg; 3271 { 3272 struct pccbb_softc *sc = arg; 3273 pcireg_t reg; 3274 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3275 bus_space_handle_t base_memh = sc->sc_base_memh; 3276 3277 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3278 3279 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3280 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3281 if (sc->sc_pil_intr_enable) { 3282 (void)pccbbintr_function(sc); 3283 } 3284 sc->sc_pil_intr_enable = 0; 3285 3286 /* ToDo: deactivate or suspend child devices */ 3287 3288 } 3289 3290 if (why == PWR_RESUME) { 3291 if (sc->sc_pwrmgt_offs != 0) { 3292 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3293 sc->sc_pwrmgt_offs + 4); 3294 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3295 reg & 0x100) { 3296 /* powrstate != D0 */ 3297 3298 printf("%s going back to D0 mode\n", 3299 sc->sc_dev.dv_xname); 3300 reg &= ~PCI_PMCSR_STATE_MASK; 3301 reg |= PCI_PMCSR_STATE_D0; 3302 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3303 pci_conf_write(sc->sc_pc, sc->sc_tag, 3304 sc->sc_pwrmgt_offs + 4, reg); 3305 3306 pci_conf_write(sc->sc_pc, sc->sc_tag, 3307 PCI_SOCKBASE, sc->sc_sockbase); 3308 pci_conf_write(sc->sc_pc, sc->sc_tag, 3309 PCI_BUSNUM, sc->sc_busnum); 3310 pccbb_chipinit(sc); 3311 /* setup memory and io space window for CB */ 3312 pccbb_winset(0x1000, sc, sc->sc_memt); 3313 pccbb_winset(0x04, sc, sc->sc_iot); 3314 } 3315 } 3316 3317 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3318 /* BIOS did not recover this register */ 3319 pci_conf_write (sc->sc_pc, sc->sc_tag, 3320 PCI_SOCKBASE, sc->sc_sockbase); 3321 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3322 /* BIOS did not recover this register */ 3323 pci_conf_write (sc->sc_pc, sc->sc_tag, 3324 PCI_BUSNUM, sc->sc_busnum); 3325 /* CSC Interrupt: Card detect interrupt on */ 3326 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3327 /* Card detect intr is turned on. */ 3328 reg |= CB_SOCKET_MASK_CD; 3329 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3330 /* reset interrupt */ 3331 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3332 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3333 3334 /* 3335 * check for card insertion or removal during suspend period. 3336 * XXX: the code can't cope with card swap (remove then 3337 * insert). how can we detect such situation? 3338 */ 3339 (void)pccbbintr(sc); 3340 3341 sc->sc_pil_intr_enable = 1; 3342 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3343 3344 /* ToDo: activate or wakeup child devices */ 3345 } 3346 } 3347
Indexes created Fri Sep 26 20:09:58 GMT 2025