pccbb.c revision 1.71
1 /* $NetBSD: pccbb.c,v 1.71 2001/11/13 07:48:46 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.71 2001/11/13 07:48:46 lukem Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/types.h> 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/errno.h> 54 #include <sys/ioctl.h> 55 #include <sys/reboot.h> /* for bootverbose */ 56 #include <sys/syslog.h> 57 #include <sys/device.h> 58 #include <sys/malloc.h> 59 #include <sys/proc.h> 60 61 #include <machine/intr.h> 62 #include <machine/bus.h> 63 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcidevs.h> 67 68 #include <dev/pci/pccbbreg.h> 69 70 #include <dev/cardbus/cardslotvar.h> 71 72 #include <dev/cardbus/cardbusvar.h> 73 74 #include <dev/pcmcia/pcmciareg.h> 75 #include <dev/pcmcia/pcmciavar.h> 76 77 #include <dev/ic/i82365reg.h> 78 #include <dev/ic/i82365var.h> 79 #include <dev/pci/pccbbvar.h> 80 81 #include "locators.h" 82 83 #ifndef __NetBSD_Version__ 84 struct cfdriver cbb_cd = { 85 NULL, "cbb", DV_DULL 86 }; 87 #endif 88 89 #if defined CBB_DEBUG 90 #define DPRINTF(x) printf x 91 #define STATIC 92 #else 93 #define DPRINTF(x) 94 #define STATIC static 95 #endif 96 97 /* 98 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 99 * if you want to wait more than 1 ms. 100 */ 101 #define DELAY_MS(time, param) \ 102 do { \ 103 if (cold == 0) { \ 104 int tick = (hz*(time))/1000; \ 105 \ 106 if (tick <= 1) { \ 107 tick = 2; \ 108 } \ 109 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 110 } else { \ 111 delay((time)*1000); \ 112 } \ 113 } while (0) 114 115 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 116 void pccbbattach __P((struct device *, struct device *, void *)); 117 int pccbbintr __P((void *)); 118 static void pci113x_insert __P((void *)); 119 static int pccbbintr_function __P((struct pccbb_softc *)); 120 121 static int pccbb_detect_card __P((struct pccbb_softc *)); 122 123 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 124 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 125 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 126 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 127 128 STATIC int cb_reset __P((struct pccbb_softc *)); 129 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 130 STATIC int cbbprint __P((void *, const char *)); 131 132 static int cb_chipset __P((u_int32_t, int *)); 133 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 134 struct pcmciabus_attach_args *)); 135 #if 0 136 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 137 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 138 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 139 #endif 140 141 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 143 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 144 #if !rbus 145 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 146 u_int32_t)); 147 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 148 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 149 u_int32_t)); 150 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 151 #endif /* !rbus */ 152 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 153 int level, int (*ih) (void *), void *sc)); 154 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 155 156 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 157 int level, int (*ih) (void *), void *sc)); 158 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 159 160 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 161 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 162 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 163 int)); 164 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 165 cardbusreg_t)); 166 static void pccbb_chipinit __P((struct pccbb_softc *)); 167 168 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 169 struct pcmcia_mem_handle *)); 170 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 171 struct pcmcia_mem_handle *)); 172 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 173 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 174 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 175 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 176 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 177 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 178 struct pcmcia_io_handle *)); 179 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 180 bus_size_t, struct pcmcia_io_handle *, int *)); 181 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 182 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 183 struct pcmcia_function *, int, int (*)(void *), void *)); 184 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 185 void *)); 186 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 187 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 188 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 189 190 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 191 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 192 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 193 static void pccbb_powerhook __P((int, void *)); 194 195 /* bus-space allocation and deallocation functions */ 196 #if rbus 197 198 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 199 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 200 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 201 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 202 bus_space_handle_t, bus_size_t)); 203 204 #endif /* rbus */ 205 206 #if rbus 207 208 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 209 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 210 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 211 bus_space_handle_t, bus_size_t)); 212 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 213 bus_size_t, bus_space_handle_t, int)); 214 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 215 bus_space_handle_t, bus_size_t)); 216 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 217 bus_space_tag_t)); 218 void pccbb_winlist_show(struct pccbb_win_chain *); 219 220 #endif /* rbus */ 221 222 /* for config_defer */ 223 static void pccbb_pci_callback __P((struct device *)); 224 225 #if defined SHOW_REGS 226 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 227 bus_space_tag_t memt, bus_space_handle_t memh)); 228 #endif 229 230 struct cfattach cbb_pci_ca = { 231 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 232 }; 233 234 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 235 pccbb_pcmcia_mem_alloc, 236 pccbb_pcmcia_mem_free, 237 pccbb_pcmcia_mem_map, 238 pccbb_pcmcia_mem_unmap, 239 pccbb_pcmcia_io_alloc, 240 pccbb_pcmcia_io_free, 241 pccbb_pcmcia_io_map, 242 pccbb_pcmcia_io_unmap, 243 pccbb_pcmcia_intr_establish, 244 pccbb_pcmcia_intr_disestablish, 245 pccbb_pcmcia_socket_enable, 246 pccbb_pcmcia_socket_disable, 247 pccbb_pcmcia_card_detect 248 }; 249 250 #if rbus 251 static struct cardbus_functions pccbb_funcs = { 252 pccbb_rbus_cb_space_alloc, 253 pccbb_rbus_cb_space_free, 254 pccbb_cb_intr_establish, 255 pccbb_cb_intr_disestablish, 256 pccbb_ctrl, 257 pccbb_power, 258 pccbb_make_tag, 259 pccbb_free_tag, 260 pccbb_conf_read, 261 pccbb_conf_write, 262 }; 263 #else 264 static struct cardbus_functions pccbb_funcs = { 265 pccbb_ctrl, 266 pccbb_power, 267 pccbb_mem_open, 268 pccbb_mem_close, 269 pccbb_io_open, 270 pccbb_io_close, 271 pccbb_cb_intr_establish, 272 pccbb_cb_intr_disestablish, 273 pccbb_make_tag, 274 pccbb_conf_read, 275 pccbb_conf_write, 276 }; 277 #endif 278 279 int 280 pcicbbmatch(parent, match, aux) 281 struct device *parent; 282 struct cfdata *match; 283 void *aux; 284 { 285 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 286 287 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 288 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 289 PCI_INTERFACE(pa->pa_class) == 0) { 290 return 1; 291 } 292 293 return 0; 294 } 295 296 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 297 | ((prod) << PCI_PRODUCT_SHIFT)) 298 299 const struct yenta_chipinfo { 300 pcireg_t yc_id; /* vendor tag | product tag */ 301 int yc_chiptype; 302 int yc_flags; 303 } yc_chipsets[] = { 304 /* Texas Instruments chips */ 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 332 /* Ricoh chips */ 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 346 /* Toshiba products */ 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 348 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 350 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 356 /* Cirrus Logic products */ 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 362 /* sentinel, or Generic chip */ 363 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 364 }; 365 366 static int 367 cb_chipset(pci_id, flagp) 368 u_int32_t pci_id; 369 int *flagp; 370 { 371 const struct yenta_chipinfo *yc; 372 373 /* Loop over except the last default entry. */ 374 for (yc = yc_chipsets; yc < yc_chipsets + 375 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 376 if (pci_id == yc->yc_id) 377 break; 378 379 if (flagp != NULL) 380 *flagp = yc->yc_flags; 381 382 return (yc->yc_chiptype); 383 } 384 385 static void 386 pccbb_shutdown(void *arg) 387 { 388 struct pccbb_softc *sc = arg; 389 pcireg_t command; 390 391 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 392 393 /* 394 * turn off power 395 * 396 * XXX - do not turn off power if chipset is TI 113X because 397 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 398 */ 399 if (sc->sc_chipset != CB_TI113X) { 400 pccbb_power((cardbus_chipset_tag_t)sc, 401 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 402 } 403 404 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 405 0); 406 407 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 408 409 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 410 PCI_COMMAND_MASTER_ENABLE); 411 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 412 413 } 414 415 void 416 pccbbattach(parent, self, aux) 417 struct device *parent; 418 struct device *self; 419 void *aux; 420 { 421 struct pccbb_softc *sc = (void *)self; 422 struct pci_attach_args *pa = aux; 423 pci_chipset_tag_t pc = pa->pa_pc; 424 pcireg_t busreg, reg, sock_base; 425 bus_addr_t sockbase; 426 char devinfo[256]; 427 int flags; 428 int pwrmgt_offs; 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo); 433 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 434 #ifdef CBB_DEBUG 435 printf(" (chipflags %x)", flags); 436 #endif 437 printf("\n"); 438 439 TAILQ_INIT(&sc->sc_memwindow); 440 TAILQ_INIT(&sc->sc_iowindow); 441 442 #if rbus 443 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 444 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 445 446 #if 0 447 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 448 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 449 #endif 450 #endif /* rbus */ 451 452 sc->sc_base_memh = 0; 453 454 /* power management: set D0 state */ 455 sc->sc_pwrmgt_offs = 0; 456 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 457 &pwrmgt_offs, 0)) { 458 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + 4); 459 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 460 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 461 reg &= ~PCI_PMCSR_STATE_MASK; 462 reg |= PCI_PMCSR_STATE_D0; 463 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 464 pci_conf_write(pc, pa->pa_tag, pwrmgt_offs + 4, reg); 465 } 466 467 sc->sc_pwrmgt_offs = pwrmgt_offs; 468 } 469 470 /* 471 * MAP socket registers and ExCA registers on memory-space 472 * When no valid address is set on socket base registers (on pci 473 * config space), get it not polite way. 474 */ 475 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 476 477 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 478 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 479 /* The address must be valid. */ 480 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 481 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 482 printf("%s: can't map socket base address 0x%x\n", 483 sc->sc_dev.dv_xname, sock_base); 484 /* 485 * I think it's funny: socket base registers must be 486 * mapped on memory space, but ... 487 */ 488 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 489 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 490 NULL)) { 491 printf("%s: can't map socket base address" 492 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 493 (unsigned long)sockbase); 494 /* give up... allocate reg space via rbus. */ 495 sc->sc_base_memh = 0; 496 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 497 } 498 } else { 499 DPRINTF(("%s: socket base address 0x%lx\n", 500 sc->sc_dev.dv_xname, sockbase)); 501 } 502 } 503 504 sc->sc_mem_start = 0; /* XXX */ 505 sc->sc_mem_end = 0xffffffff; /* XXX */ 506 507 /* 508 * When interrupt isn't routed correctly, give up probing cbb and do 509 * not kill pcic-compatible port. 510 */ 511 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 512 printf("%s: NOT USED because of unconfigured interrupt\n", 513 sc->sc_dev.dv_xname); 514 return; 515 } 516 517 /* 518 * When bus number isn't set correctly, give up using 32-bit CardBus 519 * mode. 520 */ 521 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 522 #if notyet 523 if (((busreg >> 8) & 0xff) == 0) { 524 printf("%s: CardBus support disabled because of unconfigured bus number\n", 525 sc->sc_dev.dv_xname); 526 flags |= PCCBB_PCMCIA_16BITONLY; 527 } 528 #endif 529 530 /* pccbb_machdep.c end */ 531 532 #if defined CBB_DEBUG 533 { 534 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 535 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 536 intrname[pa->pa_intrpin], pa->pa_intrline); 537 } 538 #endif 539 540 /* setup softc */ 541 sc->sc_pc = pc; 542 sc->sc_iot = pa->pa_iot; 543 sc->sc_memt = pa->pa_memt; 544 sc->sc_dmat = pa->pa_dmat; 545 sc->sc_tag = pa->pa_tag; 546 sc->sc_function = pa->pa_function; 547 sc->sc_sockbase = sock_base; 548 sc->sc_busnum = busreg; 549 550 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 551 552 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 553 554 shutdownhook_establish(pccbb_shutdown, sc); 555 556 /* Disable legacy register mapping. */ 557 switch (sc->sc_chipset) { 558 case CB_RX5C46X: /* fallthrough */ 559 #if 0 560 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 561 case CB_RX5C47X: 562 #endif 563 /* 564 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 565 * cannot be disabled by substituting 0 into PCI_LEGACY 566 * register. Ricoh CardBus bridges have special bits on Bridge 567 * control reg (addr 0x3e on PCI config space). 568 */ 569 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 570 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 571 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 572 break; 573 574 default: 575 /* XXX I don't know proper way to kill legacy I/O. */ 576 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 577 break; 578 } 579 580 config_defer(self, pccbb_pci_callback); 581 } 582 583 584 585 586 /* 587 * static void pccbb_pci_callback(struct device *self) 588 * 589 * The actual attach routine: get memory space for YENTA register 590 * space, setup YENTA register and route interrupt. 591 * 592 * This function should be deferred because this device may obtain 593 * memory space dynamically. This function must avoid obtaining 594 * memory area which has already kept for another device. 595 */ 596 static void 597 pccbb_pci_callback(self) 598 struct device *self; 599 { 600 struct pccbb_softc *sc = (void *)self; 601 pci_chipset_tag_t pc = sc->sc_pc; 602 pci_intr_handle_t ih; 603 const char *intrstr = NULL; 604 bus_addr_t sockbase; 605 struct cbslot_attach_args cba; 606 struct pcmciabus_attach_args paa; 607 struct cardslot_attach_args caa; 608 struct cardslot_softc *csc; 609 610 if (0 == sc->sc_base_memh) { 611 /* The socket registers aren't mapped correctly. */ 612 #if rbus 613 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 614 (sc->sc_chipset == CB_RX5C47X 615 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 616 0, &sockbase, &sc->sc_base_memh)) { 617 return; 618 } 619 sc->sc_base_memt = sc->sc_memt; 620 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 621 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 622 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 623 PCI_SOCKBASE))); 624 #else 625 sc->sc_base_memt = sc->sc_memt; 626 #if !defined CBB_PCI_BASE 627 #define CBB_PCI_BASE 0x20000000 628 #endif 629 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 630 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 631 /* cannot allocate memory space */ 632 return; 633 } 634 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 635 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 636 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 637 sc->sc_tag, PCI_SOCKBASE))); 638 sc->sc_sockbase = sockbase; 639 #endif 640 } 641 642 /* bus bridge initialization */ 643 pccbb_chipinit(sc); 644 645 /* clear data structure for child device interrupt handlers */ 646 sc->sc_pil = NULL; 647 sc->sc_pil_intr_enable = 1; 648 649 /* Map and establish the interrupt. */ 650 if (pci_intr_map(&sc->sc_pa, &ih)) { 651 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 652 return; 653 } 654 intrstr = pci_intr_string(pc, ih); 655 656 /* 657 * XXX pccbbintr should be called under the priority lower 658 * than any other hard interrputs. 659 */ 660 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 661 662 if (sc->sc_ih == NULL) { 663 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 664 if (intrstr != NULL) { 665 printf(" at %s", intrstr); 666 } 667 printf("\n"); 668 return; 669 } 670 671 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 672 powerhook_establish(pccbb_powerhook, sc); 673 674 { 675 u_int32_t sockstat; 676 677 sockstat = bus_space_read_4(sc->sc_base_memt, 678 sc->sc_base_memh, CB_SOCKET_STAT); 679 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 680 sc->sc_flags |= CBB_CARDEXIST; 681 } 682 } 683 684 /* 685 * attach cardbus 686 */ 687 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 688 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 689 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 690 691 /* initialize cbslot_attach */ 692 cba.cba_busname = "cardbus"; 693 cba.cba_iot = sc->sc_iot; 694 cba.cba_memt = sc->sc_memt; 695 cba.cba_dmat = sc->sc_dmat; 696 cba.cba_bus = (busreg >> 8) & 0x0ff; 697 cba.cba_cc = (void *)sc; 698 cba.cba_cf = &pccbb_funcs; 699 cba.cba_intrline = sc->sc_pa.pa_intrline; 700 701 #if rbus 702 cba.cba_rbus_iot = sc->sc_rbus_iot; 703 cba.cba_rbus_memt = sc->sc_rbus_memt; 704 #endif 705 706 cba.cba_cacheline = PCI_CACHELINE(bhlc); 707 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 708 709 if (bootverbose) { 710 printf("%s: cacheline 0x%x lattimer 0x%x\n", 711 sc->sc_dev.dv_xname, cba.cba_cacheline, 712 cba.cba_lattimer); 713 printf("%s: bhlc 0x%x lscp 0x%x\n", 714 sc->sc_dev.dv_xname, bhlc, busreg); 715 } 716 #if defined SHOW_REGS 717 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 718 sc->sc_base_memh); 719 #endif 720 } 721 722 pccbb_pcmcia_attach_setup(sc, &paa); 723 caa.caa_cb_attach = NULL; 724 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 725 caa.caa_cb_attach = &cba; 726 } 727 caa.caa_16_attach = &paa; 728 caa.caa_ph = &sc->sc_pcmcia_h; 729 730 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 731 DPRINTF(("pccbbattach: found cardslot\n")); 732 sc->sc_csc = csc; 733 } 734 735 return; 736 } 737 738 739 740 741 742 /* 743 * static void pccbb_chipinit(struct pccbb_softc *sc) 744 * 745 * This function initialize YENTA chip registers listed below: 746 * 1) PCI command reg, 747 * 2) PCI and CardBus latency timer, 748 * 3) route PCI interrupt, 749 * 4) close all memory and io windows. 750 * 5) turn off bus power. 751 * 6) card detect interrupt on. 752 * 7) clear interrupt 753 */ 754 static void 755 pccbb_chipinit(sc) 756 struct pccbb_softc *sc; 757 { 758 pci_chipset_tag_t pc = sc->sc_pc; 759 pcitag_t tag = sc->sc_tag; 760 bus_space_tag_t bmt = sc->sc_base_memt; 761 bus_space_handle_t bmh = sc->sc_base_memh; 762 pcireg_t reg; 763 764 /* 765 * Set PCI command reg. 766 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 767 */ 768 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 769 /* I believe it is harmless. */ 770 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 771 PCI_COMMAND_MASTER_ENABLE); 772 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 773 774 /* 775 * Set CardBus latency timer. 776 */ 777 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 778 if (PCI_CB_LATENCY(reg) < 0x20) { 779 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 780 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 781 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 782 } 783 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 784 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 785 786 /* 787 * Set PCI latency timer. 788 */ 789 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 790 if (PCI_LATTIMER(reg) < 0x10) { 791 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 792 reg |= (0x10 << PCI_LATTIMER_SHIFT); 793 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 794 } 795 DPRINTF(("PCI latency timer 0x%x (%x)\n", 796 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 797 798 799 /* Route functional interrupts to PCI. */ 800 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 801 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 802 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 803 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 804 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 805 806 switch (sc->sc_chipset) { 807 case CB_TI113X: 808 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 809 /* This bit is shared, but may read as 0 on some chips, so set 810 it explicitly on both functions. */ 811 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 812 /* CSC intr enable */ 813 reg |= PCI113X_CBCTRL_PCI_CSC; 814 /* functional intr prohibit | prohibit ISA routing */ 815 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 816 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 817 break; 818 819 case CB_TI12XX: 820 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 821 reg |= PCI12XX_SYSCTRL_VCCPROT; 822 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 823 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 824 reg |= PCI12XX_CBCTRL_CSC; 825 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 826 break; 827 828 case CB_TOPIC95B: 829 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 830 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 831 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 832 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 833 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 834 sc->sc_dev.dv_xname, reg)); 835 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 836 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 837 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 838 DPRINTF(("0x%x\n", reg)); 839 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 840 break; 841 842 case CB_TOPIC97: 843 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 844 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 845 sc->sc_dev.dv_xname, reg)); 846 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 847 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 848 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 849 reg |= TOPIC97_SLOT_CTRL_PCIINT; 850 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 851 DPRINTF(("0x%x\n", reg)); 852 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 853 /* make sure to assert LV card support bits */ 854 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 855 0x800 + 0x3e, 856 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 857 0x800 + 0x3e) | 0x03); 858 break; 859 } 860 861 /* Close all memory and I/O windows. */ 862 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 863 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 864 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 865 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 866 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 867 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 868 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 869 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 870 871 /* reset 16-bit pcmcia bus */ 872 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 873 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 874 875 /* turn off power */ 876 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 877 878 /* CSC Interrupt: Card detect interrupt on */ 879 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 880 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 881 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 882 /* reset interrupt */ 883 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 884 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 885 } 886 887 888 889 890 /* 891 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 892 * struct pcmciabus_attach_args *paa) 893 * 894 * This function attaches 16-bit PCcard bus. 895 */ 896 STATIC void 897 pccbb_pcmcia_attach_setup(sc, paa) 898 struct pccbb_softc *sc; 899 struct pcmciabus_attach_args *paa; 900 { 901 struct pcic_handle *ph = &sc->sc_pcmcia_h; 902 #if rbus 903 rbus_tag_t rb; 904 #endif 905 906 /* initialize pcmcia part in pccbb_softc */ 907 ph->ph_parent = (struct device *)sc; 908 ph->sock = sc->sc_function; 909 ph->flags = 0; 910 ph->shutdown = 0; 911 ph->ih_irq = sc->sc_pa.pa_intrline; 912 ph->ph_bus_t = sc->sc_base_memt; 913 ph->ph_bus_h = sc->sc_base_memh; 914 ph->ph_read = pccbb_pcmcia_read; 915 ph->ph_write = pccbb_pcmcia_write; 916 sc->sc_pct = &pccbb_pcmcia_funcs; 917 918 /* 919 * We need to do a few things here: 920 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 921 * setting the IRQ numbers to 0. 922 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 923 * routing of CSC interrupts (e.g. card removal) to PCI while in 924 * PCMCIA mode. We just leave this set all the time. 925 * 3) Enable card insertion/removal interrupts in case the chip also 926 * needs that while in PCMCIA mode. 927 * 4) Clear any pending CSC interrupt. 928 */ 929 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 930 if (sc->sc_chipset == CB_TI113X) { 931 Pcic_write(ph, PCIC_CSC_INTR, 0); 932 } else { 933 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 934 Pcic_read(ph, PCIC_CSC); 935 } 936 937 /* initialize pcmcia bus attachment */ 938 paa->paa_busname = "pcmcia"; 939 paa->pct = sc->sc_pct; 940 paa->pch = ph; 941 paa->iobase = 0; /* I don't use them */ 942 paa->iosize = 0; 943 #if rbus 944 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 945 paa->iobase = rb->rb_start + rb->rb_offset; 946 paa->iosize = rb->rb_end - rb->rb_start; 947 #endif 948 949 return; 950 } 951 952 #if 0 953 STATIC void 954 pccbb_pcmcia_attach_card(ph) 955 struct pcic_handle *ph; 956 { 957 if (ph->flags & PCIC_FLAG_CARDP) { 958 panic("pccbb_pcmcia_attach_card: already attached"); 959 } 960 961 /* call the MI attach function */ 962 pcmcia_card_attach(ph->pcmcia); 963 964 ph->flags |= PCIC_FLAG_CARDP; 965 } 966 967 STATIC void 968 pccbb_pcmcia_detach_card(ph, flags) 969 struct pcic_handle *ph; 970 int flags; 971 { 972 if (!(ph->flags & PCIC_FLAG_CARDP)) { 973 panic("pccbb_pcmcia_detach_card: already detached"); 974 } 975 976 ph->flags &= ~PCIC_FLAG_CARDP; 977 978 /* call the MI detach function */ 979 pcmcia_card_detach(ph->pcmcia, flags); 980 } 981 #endif 982 983 /* 984 * int pccbbintr(arg) 985 * void *arg; 986 * This routine handles the interrupt from Yenta PCI-CardBus bridge 987 * itself. 988 */ 989 int 990 pccbbintr(arg) 991 void *arg; 992 { 993 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 994 u_int32_t sockevent, sockstate; 995 bus_space_tag_t memt = sc->sc_base_memt; 996 bus_space_handle_t memh = sc->sc_base_memh; 997 struct pcic_handle *ph = &sc->sc_pcmcia_h; 998 999 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1000 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1001 Pcic_read(ph, PCIC_CSC); 1002 1003 if (sockevent == 0) { 1004 /* This intr is not for me: it may be for my child devices. */ 1005 if (sc->sc_pil_intr_enable) { 1006 return pccbbintr_function(sc); 1007 } else { 1008 return 0; 1009 } 1010 } 1011 1012 if (sockevent & CB_SOCKET_EVENT_CD) { 1013 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1014 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 1015 /* A card should be removed. */ 1016 if (sc->sc_flags & CBB_CARDEXIST) { 1017 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1018 sockevent)); 1019 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1020 sc->sc_flags &= ~CBB_CARDEXIST; 1021 if (sc->sc_csc->sc_status & 1022 CARDSLOT_STATUS_CARD_16) { 1023 #if 0 1024 struct pcic_handle *ph = 1025 &sc->sc_pcmcia_h; 1026 1027 pcmcia_card_deactivate(ph->pcmcia); 1028 pccbb_pcmcia_socket_disable(ph); 1029 pccbb_pcmcia_detach_card(ph, 1030 DETACH_FORCE); 1031 #endif 1032 cardslot_event_throw(sc->sc_csc, 1033 CARDSLOT_EVENT_REMOVAL_16); 1034 } else if (sc->sc_csc->sc_status & 1035 CARDSLOT_STATUS_CARD_CB) { 1036 /* Cardbus intr removed */ 1037 cardslot_event_throw(sc->sc_csc, 1038 CARDSLOT_EVENT_REMOVAL_CB); 1039 } 1040 } 1041 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1042 /* 1043 * The pccbbintr may called from powerdown hook when 1044 * the system resumed, to detect the card 1045 * insertion/removal during suspension. 1046 */ 1047 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1048 if (sc->sc_flags & CBB_INSERTING) { 1049 callout_stop(&sc->sc_insert_ch); 1050 } 1051 callout_reset(&sc->sc_insert_ch, hz / 10, 1052 pci113x_insert, sc); 1053 sc->sc_flags |= CBB_INSERTING; 1054 } 1055 } 1056 1057 return (1); 1058 } 1059 1060 /* 1061 * static int pccbbintr_function(struct pccbb_softc *sc) 1062 * 1063 * This function calls each interrupt handler registered at the 1064 * bridge. The interrupt handlers are called in registered order. 1065 */ 1066 static int 1067 pccbbintr_function(sc) 1068 struct pccbb_softc *sc; 1069 { 1070 int retval = 0, val; 1071 struct pccbb_intrhand_list *pil; 1072 int s, splchanged; 1073 1074 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1075 /* 1076 * XXX priority change. gross. I use if-else 1077 * sentense instead of switch-case sentense because of 1078 * avoiding duplicate case value error. More than one 1079 * IPL_XXX use same value. It depends on 1080 * implimentation. 1081 */ 1082 splchanged = 1; 1083 if (pil->pil_level == IPL_SERIAL) { 1084 s = splserial(); 1085 } else if (pil->pil_level == IPL_HIGH) { 1086 s = splhigh(); 1087 } else if (pil->pil_level == IPL_CLOCK) { 1088 s = splclock(); 1089 } else if (pil->pil_level == IPL_AUDIO) { 1090 s = splaudio(); 1091 } else if (pil->pil_level == IPL_IMP) { 1092 s = splvm(); /* XXX */ 1093 } else if (pil->pil_level == IPL_TTY) { 1094 s = spltty(); 1095 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1096 s = splsoftserial(); 1097 } else if (pil->pil_level == IPL_NET) { 1098 s = splnet(); 1099 } else { 1100 splchanged = 0; 1101 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1102 } 1103 1104 val = (*pil->pil_func)(pil->pil_arg); 1105 1106 if (splchanged != 0) { 1107 splx(s); 1108 } 1109 1110 retval = retval == 1 ? 1 : 1111 retval == 0 ? val : val != 0 ? val : retval; 1112 } 1113 1114 return retval; 1115 } 1116 1117 static void 1118 pci113x_insert(arg) 1119 void *arg; 1120 { 1121 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1122 u_int32_t sockevent, sockstate; 1123 1124 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1125 CB_SOCKET_EVENT); 1126 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1127 CB_SOCKET_STAT); 1128 1129 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1130 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1131 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1132 sc->sc_flags |= CBB_CARDEXIST; 1133 /* call pccard interrupt handler here */ 1134 if (sockstate & CB_SOCKET_STAT_16BIT) { 1135 /* 16-bit card found */ 1136 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1137 cardslot_event_throw(sc->sc_csc, 1138 CARDSLOT_EVENT_INSERTION_16); 1139 } else if (sockstate & CB_SOCKET_STAT_CB) { 1140 /* cardbus card found */ 1141 /* cardbus_attach_card(sc->sc_csc); */ 1142 cardslot_event_throw(sc->sc_csc, 1143 CARDSLOT_EVENT_INSERTION_CB); 1144 } else { 1145 /* who are you? */ 1146 } 1147 } else { 1148 callout_reset(&sc->sc_insert_ch, hz / 10, 1149 pci113x_insert, sc); 1150 } 1151 } 1152 1153 #define PCCBB_PCMCIA_OFFSET 0x800 1154 static u_int8_t 1155 pccbb_pcmcia_read(ph, reg) 1156 struct pcic_handle *ph; 1157 int reg; 1158 { 1159 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1160 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1161 1162 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1163 PCCBB_PCMCIA_OFFSET + reg); 1164 } 1165 1166 static void 1167 pccbb_pcmcia_write(ph, reg, val) 1168 struct pcic_handle *ph; 1169 int reg; 1170 u_int8_t val; 1171 { 1172 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1173 val); 1174 1175 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1176 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1177 } 1178 1179 /* 1180 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1181 */ 1182 STATIC int 1183 pccbb_ctrl(ct, command) 1184 cardbus_chipset_tag_t ct; 1185 int command; 1186 { 1187 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1188 1189 switch (command) { 1190 case CARDBUS_CD: 1191 if (2 == pccbb_detect_card(sc)) { 1192 int retval = 0; 1193 int status = cb_detect_voltage(sc); 1194 if (PCCARD_VCC_5V & status) { 1195 retval |= CARDBUS_5V_CARD; 1196 } 1197 if (PCCARD_VCC_3V & status) { 1198 retval |= CARDBUS_3V_CARD; 1199 } 1200 if (PCCARD_VCC_XV & status) { 1201 retval |= CARDBUS_XV_CARD; 1202 } 1203 if (PCCARD_VCC_YV & status) { 1204 retval |= CARDBUS_YV_CARD; 1205 } 1206 return retval; 1207 } else { 1208 return 0; 1209 } 1210 break; 1211 case CARDBUS_RESET: 1212 return cb_reset(sc); 1213 break; 1214 case CARDBUS_IO_ENABLE: /* fallthrough */ 1215 case CARDBUS_IO_DISABLE: /* fallthrough */ 1216 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1217 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1218 case CARDBUS_BM_ENABLE: /* fallthrough */ 1219 case CARDBUS_BM_DISABLE: /* fallthrough */ 1220 /* XXX: I think we don't need to call this function below. */ 1221 return pccbb_cardenable(sc, command); 1222 break; 1223 } 1224 1225 return 0; 1226 } 1227 1228 /* 1229 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1230 * This function returns true when it succeeds and returns false when 1231 * it fails. 1232 */ 1233 STATIC int 1234 pccbb_power(ct, command) 1235 cardbus_chipset_tag_t ct; 1236 int command; 1237 { 1238 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1239 1240 u_int32_t status, sock_ctrl; 1241 bus_space_tag_t memt = sc->sc_base_memt; 1242 bus_space_handle_t memh = sc->sc_base_memh; 1243 1244 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1245 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1246 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1247 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1248 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1249 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1250 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1251 "UNKNOWN", 1252 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1253 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1254 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1255 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1256 "UNKNOWN", command)); 1257 1258 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1259 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1260 1261 switch (command & CARDBUS_VCCMASK) { 1262 case CARDBUS_VCC_UC: 1263 break; 1264 case CARDBUS_VCC_5V: 1265 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1266 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1267 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1268 } else { 1269 printf("%s: BAD voltage request: no 5 V card\n", 1270 sc->sc_dev.dv_xname); 1271 } 1272 break; 1273 case CARDBUS_VCC_3V: 1274 if (CB_SOCKET_STAT_3VCARD & status) { 1275 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1276 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1277 } else { 1278 printf("%s: BAD voltage request: no 3.3 V card\n", 1279 sc->sc_dev.dv_xname); 1280 } 1281 break; 1282 case CARDBUS_VCC_0V: 1283 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1284 break; 1285 default: 1286 return 0; /* power NEVER changed */ 1287 break; 1288 } 1289 1290 switch (command & CARDBUS_VPPMASK) { 1291 case CARDBUS_VPP_UC: 1292 break; 1293 case CARDBUS_VPP_0V: 1294 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1295 break; 1296 case CARDBUS_VPP_VCC: 1297 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1298 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1299 break; 1300 case CARDBUS_VPP_12V: 1301 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1302 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1303 break; 1304 } 1305 1306 #if 0 1307 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1308 #endif 1309 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1310 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1311 1312 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1313 printf 1314 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1315 sc->sc_dev.dv_xname, sock_ctrl, status); 1316 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1317 (command & CARDBUS_VCCMASK) == 1318 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1319 CARDBUS_VCCMASK) == 1320 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1321 CARDBUS_VCCMASK) == 1322 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1323 CARDBUS_VCCMASK) == 1324 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1325 CARDBUS_VCCMASK) == 1326 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1327 CARDBUS_VCCMASK) == 1328 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1329 (command & CARDBUS_VPPMASK) == 1330 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1331 CARDBUS_VPPMASK) == 1332 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1333 CARDBUS_VPPMASK) == 1334 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1335 CARDBUS_VPPMASK) == 1336 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1337 #if 0 1338 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1339 u_int32_t force = 1340 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1341 /* Reset Bad Vcc request */ 1342 force &= ~CB_SOCKET_FORCE_BADVCC; 1343 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1344 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1345 CB_SOCKET_STAT)); 1346 return 1; 1347 } 1348 #endif 1349 return 0; 1350 } 1351 1352 /* 1353 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1354 * time is 20 ms, some PC-Card bridge requires longer duration. 1355 */ 1356 #if 0 /* XXX called on interrupt context */ 1357 DELAY_MS(300, sc); 1358 #else 1359 delay(300 * 1000); 1360 #endif 1361 1362 return 1; /* power changed correctly */ 1363 } 1364 1365 #if defined CB_PCMCIA_POLL 1366 struct cb_poll_str { 1367 void *arg; 1368 int (*func) __P((void *)); 1369 int level; 1370 pccard_chipset_tag_t ct; 1371 int count; 1372 struct callout poll_ch; 1373 }; 1374 1375 static struct cb_poll_str cb_poll[10]; 1376 static int cb_poll_n = 0; 1377 1378 static void cb_pcmcia_poll __P((void *arg)); 1379 1380 static void 1381 cb_pcmcia_poll(arg) 1382 void *arg; 1383 { 1384 struct cb_poll_str *poll = arg; 1385 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1386 struct pccbb_softc *sc = psc->cpc_parent; 1387 int s; 1388 u_int32_t spsr; /* socket present-state reg */ 1389 1390 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1391 switch (poll->level) { 1392 case IPL_NET: 1393 s = splnet(); 1394 break; 1395 case IPL_BIO: 1396 s = splbio(); 1397 break; 1398 case IPL_TTY: /* fallthrough */ 1399 default: 1400 s = spltty(); 1401 break; 1402 } 1403 1404 spsr = 1405 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1406 CB_SOCKET_STAT); 1407 1408 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1409 if (!(spsr & 0x40)) { /* CINT low */ 1410 #else 1411 if (1) { 1412 #endif 1413 if ((*poll->func) (poll->arg) == 1) { 1414 ++poll->count; 1415 printf("intr: reported from poller, 0x%x\n", spsr); 1416 #if defined LEVEL2 1417 } else { 1418 printf("intr: miss! 0x%x\n", spsr); 1419 #endif 1420 } 1421 } 1422 splx(s); 1423 } 1424 #endif /* defined CB_PCMCIA_POLL */ 1425 1426 /* 1427 * static int pccbb_detect_card(struct pccbb_softc *sc) 1428 * return value: 0 if no card exists. 1429 * 1 if 16-bit card exists. 1430 * 2 if cardbus card exists. 1431 */ 1432 static int 1433 pccbb_detect_card(sc) 1434 struct pccbb_softc *sc; 1435 { 1436 bus_space_handle_t base_memh = sc->sc_base_memh; 1437 bus_space_tag_t base_memt = sc->sc_base_memt; 1438 u_int32_t sockstat = 1439 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1440 int retval = 0; 1441 1442 /* CD1 and CD2 asserted */ 1443 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1444 /* card must be present */ 1445 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1446 /* NOTACARD DEASSERTED */ 1447 if (CB_SOCKET_STAT_CB & sockstat) { 1448 /* CardBus mode */ 1449 retval = 2; 1450 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1451 /* 16-bit mode */ 1452 retval = 1; 1453 } 1454 } 1455 } 1456 return retval; 1457 } 1458 1459 /* 1460 * STATIC int cb_reset(struct pccbb_softc *sc) 1461 * This function resets CardBus card. 1462 */ 1463 STATIC int 1464 cb_reset(sc) 1465 struct pccbb_softc *sc; 1466 { 1467 /* 1468 * Reset Assert at least 20 ms 1469 * Some machines request longer duration. 1470 */ 1471 int reset_duration = 1472 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1473 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1474 1475 /* Reset bit Assert (bit 6 at 0x3E) */ 1476 bcr |= CB_BCR_RESET_ENABLE; 1477 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1478 DELAY_MS(reset_duration, sc); 1479 1480 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1481 /* Reset bit Deassert (bit 6 at 0x3E) */ 1482 bcr &= ~CB_BCR_RESET_ENABLE; 1483 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1484 DELAY_MS(reset_duration, sc); 1485 } 1486 /* No card found on the slot. Keep Reset. */ 1487 return 1; 1488 } 1489 1490 /* 1491 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1492 * This function detect card Voltage. 1493 */ 1494 STATIC int 1495 cb_detect_voltage(sc) 1496 struct pccbb_softc *sc; 1497 { 1498 u_int32_t psr; /* socket present-state reg */ 1499 bus_space_tag_t iot = sc->sc_base_memt; 1500 bus_space_handle_t ioh = sc->sc_base_memh; 1501 int vol = PCCARD_VCC_UKN; /* set 0 */ 1502 1503 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1504 1505 if (0x400u & psr) { 1506 vol |= PCCARD_VCC_5V; 1507 } 1508 if (0x800u & psr) { 1509 vol |= PCCARD_VCC_3V; 1510 } 1511 1512 return vol; 1513 } 1514 1515 STATIC int 1516 cbbprint(aux, pcic) 1517 void *aux; 1518 const char *pcic; 1519 { 1520 /* 1521 struct cbslot_attach_args *cba = aux; 1522 1523 if (cba->cba_slot >= 0) { 1524 printf(" slot %d", cba->cba_slot); 1525 } 1526 */ 1527 return UNCONF; 1528 } 1529 1530 /* 1531 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1532 * This function enables and disables the card 1533 */ 1534 STATIC int 1535 pccbb_cardenable(sc, function) 1536 struct pccbb_softc *sc; 1537 int function; 1538 { 1539 u_int32_t command = 1540 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1541 1542 DPRINTF(("pccbb_cardenable:")); 1543 switch (function) { 1544 case CARDBUS_IO_ENABLE: 1545 command |= PCI_COMMAND_IO_ENABLE; 1546 break; 1547 case CARDBUS_IO_DISABLE: 1548 command &= ~PCI_COMMAND_IO_ENABLE; 1549 break; 1550 case CARDBUS_MEM_ENABLE: 1551 command |= PCI_COMMAND_MEM_ENABLE; 1552 break; 1553 case CARDBUS_MEM_DISABLE: 1554 command &= ~PCI_COMMAND_MEM_ENABLE; 1555 break; 1556 case CARDBUS_BM_ENABLE: 1557 command |= PCI_COMMAND_MASTER_ENABLE; 1558 break; 1559 case CARDBUS_BM_DISABLE: 1560 command &= ~PCI_COMMAND_MASTER_ENABLE; 1561 break; 1562 default: 1563 return 0; 1564 } 1565 1566 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1567 DPRINTF((" command reg 0x%x\n", command)); 1568 return 1; 1569 } 1570 1571 #if !rbus 1572 /* 1573 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1574 */ 1575 static int 1576 pccbb_io_open(ct, win, start, end) 1577 cardbus_chipset_tag_t ct; 1578 int win; 1579 u_int32_t start, end; 1580 { 1581 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1582 int basereg; 1583 int limitreg; 1584 1585 if ((win < 0) || (win > 2)) { 1586 #if defined DIAGNOSTIC 1587 printf("cardbus_io_open: window out of range %d\n", win); 1588 #endif 1589 return 0; 1590 } 1591 1592 basereg = win * 8 + 0x2c; 1593 limitreg = win * 8 + 0x30; 1594 1595 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1596 start, basereg, end, limitreg)); 1597 1598 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1599 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1600 return 1; 1601 } 1602 1603 /* 1604 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1605 */ 1606 static int 1607 pccbb_io_close(ct, win) 1608 cardbus_chipset_tag_t ct; 1609 int win; 1610 { 1611 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1612 int basereg; 1613 int limitreg; 1614 1615 if ((win < 0) || (win > 2)) { 1616 #if defined DIAGNOSTIC 1617 printf("cardbus_io_close: window out of range %d\n", win); 1618 #endif 1619 return 0; 1620 } 1621 1622 basereg = win * 8 + 0x2c; 1623 limitreg = win * 8 + 0x30; 1624 1625 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1626 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1627 return 1; 1628 } 1629 1630 /* 1631 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1632 */ 1633 static int 1634 pccbb_mem_open(ct, win, start, end) 1635 cardbus_chipset_tag_t ct; 1636 int win; 1637 u_int32_t start, end; 1638 { 1639 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1640 int basereg; 1641 int limitreg; 1642 1643 if ((win < 0) || (win > 2)) { 1644 #if defined DIAGNOSTIC 1645 printf("cardbus_mem_open: window out of range %d\n", win); 1646 #endif 1647 return 0; 1648 } 1649 1650 basereg = win * 8 + 0x1c; 1651 limitreg = win * 8 + 0x20; 1652 1653 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1654 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1655 return 1; 1656 } 1657 1658 /* 1659 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1660 */ 1661 static int 1662 pccbb_mem_close(ct, win) 1663 cardbus_chipset_tag_t ct; 1664 int win; 1665 { 1666 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1667 int basereg; 1668 int limitreg; 1669 1670 if ((win < 0) || (win > 2)) { 1671 #if defined DIAGNOSTIC 1672 printf("cardbus_mem_close: window out of range %d\n", win); 1673 #endif 1674 return 0; 1675 } 1676 1677 basereg = win * 8 + 0x1c; 1678 limitreg = win * 8 + 0x20; 1679 1680 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1681 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1682 return 1; 1683 } 1684 #endif 1685 1686 /* 1687 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1688 * int irq, 1689 * int level, 1690 * int (* func) __P((void *)), 1691 * void *arg) 1692 * 1693 * This function registers an interrupt handler at the bridge, in 1694 * order not to call the interrupt handlers of child devices when 1695 * a card-deletion interrupt occurs. 1696 * 1697 * The arguments irq and level are not used. 1698 */ 1699 static void * 1700 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1701 cardbus_chipset_tag_t ct; 1702 int irq, level; 1703 int (*func) __P((void *)); 1704 void *arg; 1705 { 1706 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1707 1708 return pccbb_intr_establish(sc, irq, level, func, arg); 1709 } 1710 1711 1712 /* 1713 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1714 * void *ih) 1715 * 1716 * This function removes an interrupt handler pointed by ih. 1717 */ 1718 static void 1719 pccbb_cb_intr_disestablish(ct, ih) 1720 cardbus_chipset_tag_t ct; 1721 void *ih; 1722 { 1723 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1724 1725 pccbb_intr_disestablish(sc, ih); 1726 } 1727 1728 1729 void 1730 pccbb_intr_route(sc) 1731 struct pccbb_softc *sc; 1732 { 1733 pcireg_t reg; 1734 1735 /* initialize bridge intr routing */ 1736 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1737 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1738 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1739 1740 switch (sc->sc_chipset) { 1741 case CB_TI113X: 1742 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1743 /* functional intr enabled */ 1744 reg |= PCI113X_CBCTRL_PCI_INTR; 1745 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1746 break; 1747 default: 1748 break; 1749 } 1750 } 1751 1752 /* 1753 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1754 * int irq, 1755 * int level, 1756 * int (* func) __P((void *)), 1757 * void *arg) 1758 * 1759 * This function registers an interrupt handler at the bridge, in 1760 * order not to call the interrupt handlers of child devices when 1761 * a card-deletion interrupt occurs. 1762 * 1763 * The arguments irq is not used because pccbb selects intr vector. 1764 */ 1765 static void * 1766 pccbb_intr_establish(sc, irq, level, func, arg) 1767 struct pccbb_softc *sc; 1768 int irq, level; 1769 int (*func) __P((void *)); 1770 void *arg; 1771 { 1772 struct pccbb_intrhand_list *pil, *newpil; 1773 1774 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1775 1776 if (sc->sc_pil == NULL) { 1777 pccbb_intr_route(sc); 1778 1779 } 1780 1781 /* 1782 * Allocate a room for interrupt handler structure. 1783 */ 1784 if (NULL == (newpil = 1785 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1786 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1787 return NULL; 1788 } 1789 1790 newpil->pil_func = func; 1791 newpil->pil_arg = arg; 1792 newpil->pil_level = level; 1793 newpil->pil_next = NULL; 1794 1795 if (sc->sc_pil == NULL) { 1796 sc->sc_pil = newpil; 1797 } else { 1798 for (pil = sc->sc_pil; pil->pil_next != NULL; 1799 pil = pil->pil_next); 1800 pil->pil_next = newpil; 1801 } 1802 1803 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1804 1805 return newpil; 1806 } 1807 1808 /* 1809 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1810 * void *ih) 1811 * 1812 * This function removes an interrupt handler pointed by ih. 1813 */ 1814 static void 1815 pccbb_intr_disestablish(sc, ih) 1816 struct pccbb_softc *sc; 1817 void *ih; 1818 { 1819 struct pccbb_intrhand_list *pil, **pil_prev; 1820 pcireg_t reg; 1821 1822 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1823 1824 pil_prev = &sc->sc_pil; 1825 1826 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1827 if (pil == ih) { 1828 *pil_prev = pil->pil_next; 1829 free(pil, M_DEVBUF); 1830 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1831 break; 1832 } 1833 pil_prev = &pil->pil_next; 1834 } 1835 1836 if (sc->sc_pil == NULL) { 1837 /* No interrupt handlers */ 1838 1839 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1840 1841 /* stop routing PCI intr */ 1842 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1843 reg |= CB_BCR_INTR_IREQ_ENABLE; 1844 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1845 1846 switch (sc->sc_chipset) { 1847 case CB_TI113X: 1848 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1849 /* functional intr disabled */ 1850 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1851 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1852 break; 1853 default: 1854 break; 1855 } 1856 } 1857 } 1858 1859 #if defined SHOW_REGS 1860 static void 1861 cb_show_regs(pc, tag, memt, memh) 1862 pci_chipset_tag_t pc; 1863 pcitag_t tag; 1864 bus_space_tag_t memt; 1865 bus_space_handle_t memh; 1866 { 1867 int i; 1868 printf("PCI config regs:"); 1869 for (i = 0; i < 0x50; i += 4) { 1870 if (i % 16 == 0) { 1871 printf("\n 0x%02x:", i); 1872 } 1873 printf(" %08x", pci_conf_read(pc, tag, i)); 1874 } 1875 for (i = 0x80; i < 0xb0; i += 4) { 1876 if (i % 16 == 0) { 1877 printf("\n 0x%02x:", i); 1878 } 1879 printf(" %08x", pci_conf_read(pc, tag, i)); 1880 } 1881 1882 if (memh == 0) { 1883 printf("\n"); 1884 return; 1885 } 1886 1887 printf("\nsocket regs:"); 1888 for (i = 0; i <= 0x10; i += 0x04) { 1889 printf(" %08x", bus_space_read_4(memt, memh, i)); 1890 } 1891 printf("\nExCA regs:"); 1892 for (i = 0; i < 0x08; ++i) { 1893 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1894 } 1895 printf("\n"); 1896 return; 1897 } 1898 #endif 1899 1900 /* 1901 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1902 * int busno, int devno, int function) 1903 * This is the function to make a tag to access config space of 1904 * a CardBus Card. It works same as pci_conf_read. 1905 */ 1906 static cardbustag_t 1907 pccbb_make_tag(cc, busno, devno, function) 1908 cardbus_chipset_tag_t cc; 1909 int busno, devno, function; 1910 { 1911 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1912 1913 return pci_make_tag(sc->sc_pc, busno, devno, function); 1914 } 1915 1916 static void 1917 pccbb_free_tag(cc, tag) 1918 cardbus_chipset_tag_t cc; 1919 cardbustag_t tag; 1920 { 1921 } 1922 1923 /* 1924 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1925 * cardbustag_t tag, int offset) 1926 * This is the function to read the config space of a CardBus Card. 1927 * It works same as pci_conf_read. 1928 */ 1929 static cardbusreg_t 1930 pccbb_conf_read(cc, tag, offset) 1931 cardbus_chipset_tag_t cc; 1932 cardbustag_t tag; 1933 int offset; /* register offset */ 1934 { 1935 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1936 1937 return pci_conf_read(sc->sc_pc, tag, offset); 1938 } 1939 1940 /* 1941 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1942 * int offs, cardbusreg_t val) 1943 * This is the function to write the config space of a CardBus Card. 1944 * It works same as pci_conf_write. 1945 */ 1946 static void 1947 pccbb_conf_write(cc, tag, reg, val) 1948 cardbus_chipset_tag_t cc; 1949 cardbustag_t tag; 1950 int reg; /* register offset */ 1951 cardbusreg_t val; 1952 { 1953 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1954 1955 pci_conf_write(sc->sc_pc, tag, reg, val); 1956 } 1957 1958 #if 0 1959 STATIC int 1960 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1961 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1962 int speed, int flags, 1963 bus_space_handle_t * iohp) 1964 #endif 1965 /* 1966 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1967 * bus_addr_t start, bus_size_t size, 1968 * bus_size_t align, 1969 * struct pcmcia_io_handle *pcihp 1970 * 1971 * This function only allocates I/O region for pccard. This function 1972 * never maps the allocated region to pccard I/O area. 1973 * 1974 * XXX: The interface of this function is not very good, I believe. 1975 */ 1976 STATIC int 1977 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1978 pcmcia_chipset_handle_t pch; 1979 bus_addr_t start; /* start address */ 1980 bus_size_t size; 1981 bus_size_t align; 1982 struct pcmcia_io_handle *pcihp; 1983 { 1984 struct pcic_handle *ph = (struct pcic_handle *)pch; 1985 bus_addr_t ioaddr; 1986 int flags = 0; 1987 bus_space_tag_t iot; 1988 bus_space_handle_t ioh; 1989 bus_addr_t mask; 1990 #if rbus 1991 rbus_tag_t rb; 1992 #endif 1993 if (align == 0) { 1994 align = size; /* XXX: funny??? */ 1995 } 1996 1997 if (start != 0) { 1998 /* XXX: assume all card decode lower 10 bits by its hardware */ 1999 mask = 0x3ff; 2000 } else { 2001 /* 2002 * calculate mask: 2003 * 1. get the most significant bit of size (call it msb). 2004 * 2. compare msb with the value of size. 2005 * 3. if size is larger, shift msb left once. 2006 * 4. obtain mask value to decrement msb. 2007 */ 2008 bus_size_t size_tmp = size; 2009 int shifts = 0; 2010 2011 mask = 1; 2012 while (size_tmp) { 2013 ++shifts; 2014 size_tmp >>= 1; 2015 } 2016 mask = (1 << shifts); 2017 if (mask < size) { 2018 mask <<= 1; 2019 } 2020 --mask; 2021 } 2022 2023 /* 2024 * Allocate some arbitrary I/O space. 2025 */ 2026 2027 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2028 2029 #if rbus 2030 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2031 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2032 return 1; 2033 } 2034 #else 2035 if (start) { 2036 ioaddr = start; 2037 if (bus_space_map(iot, start, size, 0, &ioh)) { 2038 return 1; 2039 } 2040 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2041 (u_long) ioaddr, (u_long) size)); 2042 } else { 2043 flags |= PCMCIA_IO_ALLOCATED; 2044 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2045 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2046 size, align, 0, 0, &ioaddr, &ioh)) { 2047 /* No room be able to be get. */ 2048 return 1; 2049 } 2050 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2051 (u_long) ioaddr, (u_long) size)); 2052 } 2053 #endif 2054 2055 pcihp->iot = iot; 2056 pcihp->ioh = ioh; 2057 pcihp->addr = ioaddr; 2058 pcihp->size = size; 2059 pcihp->flags = flags; 2060 2061 return 0; 2062 } 2063 2064 /* 2065 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2066 * struct pcmcia_io_handle *pcihp) 2067 * 2068 * This function only frees I/O region for pccard. 2069 * 2070 * XXX: The interface of this function is not very good, I believe. 2071 */ 2072 void 2073 pccbb_pcmcia_io_free(pch, pcihp) 2074 pcmcia_chipset_handle_t pch; 2075 struct pcmcia_io_handle *pcihp; 2076 { 2077 #if !rbus 2078 bus_space_tag_t iot = pcihp->iot; 2079 #endif 2080 bus_space_handle_t ioh = pcihp->ioh; 2081 bus_size_t size = pcihp->size; 2082 2083 #if rbus 2084 struct pccbb_softc *sc = 2085 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2086 rbus_tag_t rb = sc->sc_rbus_iot; 2087 2088 rbus_space_free(rb, ioh, size, NULL); 2089 #else 2090 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2091 bus_space_free(iot, ioh, size); 2092 else 2093 bus_space_unmap(iot, ioh, size); 2094 #endif 2095 } 2096 2097 /* 2098 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2099 * bus_addr_t offset, bus_size_t size, 2100 * struct pcmcia_io_handle *pcihp, 2101 * int *windowp) 2102 * 2103 * This function maps the allocated I/O region to pccard. This function 2104 * never allocates any I/O region for pccard I/O area. I don't 2105 * understand why the original authors of pcmciabus separated alloc and 2106 * map. I believe the two must be unite. 2107 * 2108 * XXX: no wait timing control? 2109 */ 2110 int 2111 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2112 pcmcia_chipset_handle_t pch; 2113 int width; 2114 bus_addr_t offset; 2115 bus_size_t size; 2116 struct pcmcia_io_handle *pcihp; 2117 int *windowp; 2118 { 2119 struct pcic_handle *ph = (struct pcic_handle *)pch; 2120 bus_addr_t ioaddr = pcihp->addr + offset; 2121 int i, win; 2122 #if defined CBB_DEBUG 2123 static char *width_names[] = { "dynamic", "io8", "io16" }; 2124 #endif 2125 2126 /* Sanity check I/O handle. */ 2127 2128 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2129 panic("pccbb_pcmcia_io_map iot is bogus"); 2130 } 2131 2132 /* XXX Sanity check offset/size. */ 2133 2134 win = -1; 2135 for (i = 0; i < PCIC_IO_WINS; i++) { 2136 if ((ph->ioalloc & (1 << i)) == 0) { 2137 win = i; 2138 ph->ioalloc |= (1 << i); 2139 break; 2140 } 2141 } 2142 2143 if (win == -1) { 2144 return 1; 2145 } 2146 2147 *windowp = win; 2148 2149 /* XXX this is pretty gross */ 2150 2151 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2152 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2153 2154 /* XXX wtf is this doing here? */ 2155 2156 #if 0 2157 printf(" port 0x%lx", (u_long) ioaddr); 2158 if (size > 1) { 2159 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2160 } 2161 #endif 2162 2163 ph->io[win].addr = ioaddr; 2164 ph->io[win].size = size; 2165 ph->io[win].width = width; 2166 2167 /* actual dirty register-value changing in the function below. */ 2168 pccbb_pcmcia_do_io_map(ph, win); 2169 2170 return 0; 2171 } 2172 2173 /* 2174 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2175 * 2176 * This function changes register-value to map I/O region for pccard. 2177 */ 2178 static void 2179 pccbb_pcmcia_do_io_map(ph, win) 2180 struct pcic_handle *ph; 2181 int win; 2182 { 2183 static u_int8_t pcic_iowidth[3] = { 2184 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2185 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2186 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2187 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2188 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2189 }; 2190 2191 #define PCIC_SIA_START_LOW 0 2192 #define PCIC_SIA_START_HIGH 1 2193 #define PCIC_SIA_STOP_LOW 2 2194 #define PCIC_SIA_STOP_HIGH 3 2195 2196 int regbase_win = 0x8 + win * 0x04; 2197 u_int8_t ioctl, enable; 2198 2199 DPRINTF( 2200 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2201 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2202 ph->io[win].width * 8)); 2203 2204 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2205 ph->io[win].addr & 0xff); 2206 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2207 (ph->io[win].addr >> 8) & 0xff); 2208 2209 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2210 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2211 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2212 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2213 2214 ioctl = Pcic_read(ph, PCIC_IOCTL); 2215 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2216 switch (win) { 2217 case 0: 2218 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2219 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2220 PCIC_IOCTL_IO0_DATASIZE_MASK); 2221 ioctl |= pcic_iowidth[ph->io[win].width]; 2222 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2223 break; 2224 case 1: 2225 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2226 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2227 PCIC_IOCTL_IO1_DATASIZE_MASK); 2228 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2229 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2230 break; 2231 } 2232 Pcic_write(ph, PCIC_IOCTL, ioctl); 2233 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2234 #if defined CBB_DEBUG 2235 { 2236 u_int8_t start_low = 2237 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2238 u_int8_t start_high = 2239 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2240 u_int8_t stop_low = 2241 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2242 u_int8_t stop_high = 2243 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2244 printf 2245 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2246 start_low, start_high, stop_low, stop_high, ioctl, enable); 2247 } 2248 #endif 2249 } 2250 2251 /* 2252 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2253 * 2254 * This function unmaps I/O region. No return value. 2255 */ 2256 STATIC void 2257 pccbb_pcmcia_io_unmap(pch, win) 2258 pcmcia_chipset_handle_t pch; 2259 int win; 2260 { 2261 struct pcic_handle *ph = (struct pcic_handle *)pch; 2262 int reg; 2263 2264 if (win >= PCIC_IO_WINS || win < 0) { 2265 panic("pccbb_pcmcia_io_unmap: window out of range"); 2266 } 2267 2268 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2269 switch (win) { 2270 case 0: 2271 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2272 break; 2273 case 1: 2274 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2275 break; 2276 } 2277 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2278 2279 ph->ioalloc &= ~(1 << win); 2280 } 2281 2282 /* 2283 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2284 * 2285 * This function enables the card. All information is stored in 2286 * the first argument, pcmcia_chipset_handle_t. 2287 */ 2288 static void 2289 pccbb_pcmcia_wait_ready(ph) 2290 struct pcic_handle *ph; 2291 { 2292 int i; 2293 2294 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2295 Pcic_read(ph, PCIC_IF_STATUS))); 2296 2297 for (i = 0; i < 2000; i++) { 2298 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2299 return; 2300 } 2301 DELAY_MS(2, ph->ph_parent); 2302 #ifdef CBB_DEBUG 2303 if ((i > 1000) && (i % 25 == 24)) 2304 printf("."); 2305 #endif 2306 } 2307 2308 #ifdef DIAGNOSTIC 2309 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2310 Pcic_read(ph, PCIC_IF_STATUS)); 2311 #endif 2312 } 2313 2314 /* 2315 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2316 * 2317 * This function enables the card. All information is stored in 2318 * the first argument, pcmcia_chipset_handle_t. 2319 */ 2320 STATIC void 2321 pccbb_pcmcia_socket_enable(pch) 2322 pcmcia_chipset_handle_t pch; 2323 { 2324 struct pcic_handle *ph = (struct pcic_handle *)pch; 2325 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2326 int cardtype, win; 2327 u_int8_t power, intr; 2328 pcireg_t spsr; 2329 int voltage; 2330 2331 /* this bit is mostly stolen from pcic_attach_card */ 2332 2333 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2334 2335 /* get card Vcc info */ 2336 2337 spsr = 2338 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2339 CB_SOCKET_STAT); 2340 if (spsr & CB_SOCKET_STAT_5VCARD) { 2341 DPRINTF(("5V card\n")); 2342 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2343 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2344 DPRINTF(("3V card\n")); 2345 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2346 } else { 2347 printf("?V card, 0x%x\n", spsr); /* XXX */ 2348 return; 2349 } 2350 2351 /* disable socket: negate output enable bit and power off */ 2352 2353 power = 0; 2354 Pcic_write(ph, PCIC_PWRCTL, power); 2355 2356 /* power down the socket to reset it, clear the card reset pin */ 2357 2358 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2359 2360 /* 2361 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2362 * we are changing Vcc (Toff). 2363 */ 2364 /* delay(300*1000); too much */ 2365 2366 /* assert reset bit */ 2367 intr = Pcic_read(ph, PCIC_INTR); 2368 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2369 Pcic_write(ph, PCIC_INTR, intr); 2370 2371 /* power up the socket and output enable */ 2372 power = Pcic_read(ph, PCIC_PWRCTL); 2373 power |= PCIC_PWRCTL_OE; 2374 Pcic_write(ph, PCIC_PWRCTL, power); 2375 pccbb_power(sc, voltage); 2376 2377 /* 2378 * hold RESET at least 20 ms: the spec says only 10 us is 2379 * enough, but TI1130 requires at least 20 ms. 2380 */ 2381 #if 0 /* XXX called on interrupt context */ 2382 DELAY_MS(20, sc); 2383 #else 2384 delay(20 * 1000); 2385 #endif 2386 2387 /* clear the reset flag */ 2388 2389 intr |= PCIC_INTR_RESET; 2390 Pcic_write(ph, PCIC_INTR, intr); 2391 2392 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2393 2394 #if 0 /* XXX called on interrupt context */ 2395 DELAY_MS(20, sc); 2396 #else 2397 delay(20 * 1000); 2398 #endif 2399 2400 /* wait for the chip to finish initializing */ 2401 2402 pccbb_pcmcia_wait_ready(ph); 2403 2404 /* zero out the address windows */ 2405 2406 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2407 2408 /* set the card type */ 2409 2410 cardtype = pcmcia_card_gettype(ph->pcmcia); 2411 2412 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2413 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2414 Pcic_write(ph, PCIC_INTR, intr); 2415 2416 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2417 ph->ph_parent->dv_xname, ph->sock, 2418 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2419 2420 /* reinstall all the memory and io mappings */ 2421 2422 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2423 if (ph->memalloc & (1 << win)) { 2424 pccbb_pcmcia_do_mem_map(ph, win); 2425 } 2426 } 2427 2428 for (win = 0; win < PCIC_IO_WINS; ++win) { 2429 if (ph->ioalloc & (1 << win)) { 2430 pccbb_pcmcia_do_io_map(ph, win); 2431 } 2432 } 2433 } 2434 2435 /* 2436 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2437 * 2438 * This function disables the card. All information is stored in 2439 * the first argument, pcmcia_chipset_handle_t. 2440 */ 2441 STATIC void 2442 pccbb_pcmcia_socket_disable(pch) 2443 pcmcia_chipset_handle_t pch; 2444 { 2445 struct pcic_handle *ph = (struct pcic_handle *)pch; 2446 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2447 u_int8_t power, intr; 2448 2449 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2450 2451 /* reset signal asserting... */ 2452 2453 intr = Pcic_read(ph, PCIC_INTR); 2454 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2455 Pcic_write(ph, PCIC_INTR, intr); 2456 delay(2 * 1000); 2457 2458 /* power down the socket */ 2459 power = Pcic_read(ph, PCIC_PWRCTL); 2460 power &= ~PCIC_PWRCTL_OE; 2461 Pcic_write(ph, PCIC_PWRCTL, power); 2462 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2463 /* 2464 * wait 300ms until power fails (Tpf). 2465 */ 2466 #if 0 /* XXX called on interrupt context */ 2467 DELAY_MS(300, sc); 2468 #else 2469 delay(300 * 1000); 2470 #endif 2471 } 2472 2473 /* 2474 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2475 * 2476 * This function detects whether a card is in the slot or not. 2477 * If a card is inserted, return 1. Otherwise, return 0. 2478 */ 2479 STATIC int 2480 pccbb_pcmcia_card_detect(pch) 2481 pcmcia_chipset_handle_t pch; 2482 { 2483 struct pcic_handle *ph = (struct pcic_handle *)pch; 2484 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2485 2486 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2487 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2488 } 2489 2490 #if 0 2491 STATIC int 2492 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2493 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2494 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2495 #endif 2496 /* 2497 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2498 * bus_size_t size, 2499 * struct pcmcia_mem_handle *pcmhp) 2500 * 2501 * This function only allocates memory region for pccard. This 2502 * function never maps the allocated region to pccard memory area. 2503 * 2504 * XXX: Why the argument of start address is not in? 2505 */ 2506 STATIC int 2507 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2508 pcmcia_chipset_handle_t pch; 2509 bus_size_t size; 2510 struct pcmcia_mem_handle *pcmhp; 2511 { 2512 struct pcic_handle *ph = (struct pcic_handle *)pch; 2513 bus_space_handle_t memh; 2514 bus_addr_t addr; 2515 bus_size_t sizepg; 2516 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2517 #if rbus 2518 rbus_tag_t rb; 2519 #endif 2520 2521 /* out of sc->memh, allocate as many pages as necessary */ 2522 2523 /* convert size to PCIC pages */ 2524 /* 2525 * This is not enough; when the requested region is on the page 2526 * boundaries, this may calculate wrong result. 2527 */ 2528 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2529 #if 0 2530 if (sizepg > PCIC_MAX_MEM_PAGES) { 2531 return 1; 2532 } 2533 #endif 2534 2535 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2536 return 1; 2537 } 2538 2539 addr = 0; /* XXX gcc -Wuninitialized */ 2540 2541 #if rbus 2542 rb = sc->sc_rbus_memt; 2543 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2544 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2545 &addr, &memh)) { 2546 return 1; 2547 } 2548 #else 2549 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2550 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2551 0, /* boundary */ 2552 0, /* flags */ 2553 &addr, &memh)) { 2554 return 1; 2555 } 2556 #endif 2557 2558 DPRINTF( 2559 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2560 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2561 2562 pcmhp->memt = sc->sc_memt; 2563 pcmhp->memh = memh; 2564 pcmhp->addr = addr; 2565 pcmhp->size = size; 2566 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2567 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2568 pcmhp->mhandle = 0; 2569 /* No offset??? Funny. */ 2570 2571 return 0; 2572 } 2573 2574 /* 2575 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2576 * struct pcmcia_mem_handle *pcmhp) 2577 * 2578 * This function release the memory space allocated by the function 2579 * pccbb_pcmcia_mem_alloc(). 2580 */ 2581 STATIC void 2582 pccbb_pcmcia_mem_free(pch, pcmhp) 2583 pcmcia_chipset_handle_t pch; 2584 struct pcmcia_mem_handle *pcmhp; 2585 { 2586 #if rbus 2587 struct pcic_handle *ph = (struct pcic_handle *)pch; 2588 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2589 2590 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2591 #else 2592 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2593 #endif 2594 } 2595 2596 /* 2597 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2598 * 2599 * This function release the memory space allocated by the function 2600 * pccbb_pcmcia_mem_alloc(). 2601 */ 2602 STATIC void 2603 pccbb_pcmcia_do_mem_map(ph, win) 2604 struct pcic_handle *ph; 2605 int win; 2606 { 2607 int regbase_win; 2608 bus_addr_t phys_addr; 2609 bus_addr_t phys_end; 2610 2611 #define PCIC_SMM_START_LOW 0 2612 #define PCIC_SMM_START_HIGH 1 2613 #define PCIC_SMM_STOP_LOW 2 2614 #define PCIC_SMM_STOP_HIGH 3 2615 #define PCIC_CMA_LOW 4 2616 #define PCIC_CMA_HIGH 5 2617 2618 u_int8_t start_low, start_high = 0; 2619 u_int8_t stop_low, stop_high; 2620 u_int8_t off_low, off_high; 2621 u_int8_t mem_window; 2622 int reg; 2623 2624 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2625 int mem8 = 2626 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2627 || (kind == PCMCIA_MEM_ATTR); 2628 2629 regbase_win = 0x10 + win * 0x08; 2630 2631 phys_addr = ph->mem[win].addr; 2632 phys_end = phys_addr + ph->mem[win].size; 2633 2634 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2635 phys_addr, phys_end, ph->mem[win].offset)); 2636 2637 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2638 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2639 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2640 2641 /* bit 19:12 */ 2642 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2643 /* bit 23:20 and bit 7 on */ 2644 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2645 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2646 /* bit 31:24, for 32-bit address */ 2647 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2648 2649 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2650 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2651 2652 if (((struct pccbb_softc *)ph-> 2653 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2654 Pcic_write(ph, 0x40 + win, mem_window); 2655 } 2656 2657 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2658 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2659 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2660 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2661 2662 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2663 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2664 2665 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2666 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2667 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2668 | ((kind == PCMCIA_MEM_ATTR) ? 2669 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2670 2671 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2672 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2673 2674 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2675 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2676 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2677 2678 #if defined CBB_DEBUG 2679 { 2680 int r1, r2, r3, r4, r5, r6, r7 = 0; 2681 2682 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2683 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2684 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2685 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2686 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2687 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2688 if (((struct pccbb_softc *)(ph-> 2689 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2690 r7 = Pcic_read(ph, 0x40 + win); 2691 } 2692 2693 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2694 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2695 if (((struct pccbb_softc *)(ph-> 2696 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2697 DPRINTF((" %02x", r7)); 2698 } 2699 DPRINTF(("\n")); 2700 } 2701 #endif 2702 } 2703 2704 /* 2705 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2706 * bus_addr_t card_addr, bus_size_t size, 2707 * struct pcmcia_mem_handle *pcmhp, 2708 * bus_addr_t *offsetp, int *windowp) 2709 * 2710 * This function maps memory space allocated by the function 2711 * pccbb_pcmcia_mem_alloc(). 2712 */ 2713 STATIC int 2714 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2715 pcmcia_chipset_handle_t pch; 2716 int kind; 2717 bus_addr_t card_addr; 2718 bus_size_t size; 2719 struct pcmcia_mem_handle *pcmhp; 2720 bus_addr_t *offsetp; 2721 int *windowp; 2722 { 2723 struct pcic_handle *ph = (struct pcic_handle *)pch; 2724 bus_addr_t busaddr; 2725 long card_offset; 2726 int win; 2727 2728 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2729 if ((ph->memalloc & (1 << win)) == 0) { 2730 ph->memalloc |= (1 << win); 2731 break; 2732 } 2733 } 2734 2735 if (win == PCIC_MEM_WINS) { 2736 return 1; 2737 } 2738 2739 *windowp = win; 2740 2741 /* XXX this is pretty gross */ 2742 2743 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2744 panic("pccbb_pcmcia_mem_map memt is bogus"); 2745 } 2746 2747 busaddr = pcmhp->addr; 2748 2749 /* 2750 * compute the address offset to the pcmcia address space for the 2751 * pcic. this is intentionally signed. The masks and shifts below 2752 * will cause TRT to happen in the pcic registers. Deal with making 2753 * sure the address is aligned, and return the alignment offset. 2754 */ 2755 2756 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2757 card_addr -= *offsetp; 2758 2759 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2760 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2761 (u_long) card_addr)); 2762 2763 /* 2764 * include the offset in the size, and decrement size by one, since 2765 * the hw wants start/stop 2766 */ 2767 size += *offsetp - 1; 2768 2769 card_offset = (((long)card_addr) - ((long)busaddr)); 2770 2771 ph->mem[win].addr = busaddr; 2772 ph->mem[win].size = size; 2773 ph->mem[win].offset = card_offset; 2774 ph->mem[win].kind = kind; 2775 2776 pccbb_pcmcia_do_mem_map(ph, win); 2777 2778 return 0; 2779 } 2780 2781 /* 2782 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2783 * int window) 2784 * 2785 * This function unmaps memory space which mapped by the function 2786 * pccbb_pcmcia_mem_map(). 2787 */ 2788 STATIC void 2789 pccbb_pcmcia_mem_unmap(pch, window) 2790 pcmcia_chipset_handle_t pch; 2791 int window; 2792 { 2793 struct pcic_handle *ph = (struct pcic_handle *)pch; 2794 int reg; 2795 2796 if (window >= PCIC_MEM_WINS) { 2797 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2798 } 2799 2800 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2801 reg &= ~(1 << window); 2802 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2803 2804 ph->memalloc &= ~(1 << window); 2805 } 2806 2807 #if defined PCCBB_PCMCIA_POLL 2808 struct pccbb_poll_str { 2809 void *arg; 2810 int (*func) __P((void *)); 2811 int level; 2812 struct pcic_handle *ph; 2813 int count; 2814 int num; 2815 struct callout poll_ch; 2816 }; 2817 2818 static struct pccbb_poll_str pccbb_poll[10]; 2819 static int pccbb_poll_n = 0; 2820 2821 static void pccbb_pcmcia_poll __P((void *arg)); 2822 2823 static void 2824 pccbb_pcmcia_poll(arg) 2825 void *arg; 2826 { 2827 struct pccbb_poll_str *poll = arg; 2828 struct pcic_handle *ph = poll->ph; 2829 struct pccbb_softc *sc = ph->sc; 2830 int s; 2831 u_int32_t spsr; /* socket present-state reg */ 2832 2833 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2834 switch (poll->level) { 2835 case IPL_NET: 2836 s = splnet(); 2837 break; 2838 case IPL_BIO: 2839 s = splbio(); 2840 break; 2841 case IPL_TTY: /* fallthrough */ 2842 default: 2843 s = spltty(); 2844 break; 2845 } 2846 2847 spsr = 2848 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2849 CB_SOCKET_STAT); 2850 2851 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2852 if (!(spsr & 0x40)) /* CINT low */ 2853 #else 2854 if (1) 2855 #endif 2856 { 2857 if ((*poll->func) (poll->arg) > 0) { 2858 ++poll->count; 2859 // printf("intr: reported from poller, 0x%x\n", spsr); 2860 #if defined LEVEL2 2861 } else { 2862 printf("intr: miss! 0x%x\n", spsr); 2863 #endif 2864 } 2865 } 2866 splx(s); 2867 } 2868 #endif /* defined CB_PCMCIA_POLL */ 2869 2870 /* 2871 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2872 * struct pcmcia_function *pf, 2873 * int ipl, 2874 * int (*func)(void *), 2875 * void *arg); 2876 * 2877 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2878 */ 2879 STATIC void * 2880 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2881 pcmcia_chipset_handle_t pch; 2882 struct pcmcia_function *pf; 2883 int ipl; 2884 int (*func) __P((void *)); 2885 void *arg; 2886 { 2887 struct pcic_handle *ph = (struct pcic_handle *)pch; 2888 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2889 2890 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2891 /* what should I do? */ 2892 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2893 DPRINTF( 2894 ("%s does not provide edge nor pulse interrupt\n", 2895 sc->sc_dev.dv_xname)); 2896 return NULL; 2897 } 2898 /* 2899 * XXX Noooooo! The interrupt flag must set properly!! 2900 * dumb pcmcia driver!! 2901 */ 2902 } 2903 2904 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2905 } 2906 2907 /* 2908 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2909 * void *ih) 2910 * 2911 * This function disables PC-Card interrupt. 2912 */ 2913 STATIC void 2914 pccbb_pcmcia_intr_disestablish(pch, ih) 2915 pcmcia_chipset_handle_t pch; 2916 void *ih; 2917 { 2918 struct pcic_handle *ph = (struct pcic_handle *)pch; 2919 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2920 2921 pccbb_intr_disestablish(sc, ih); 2922 } 2923 2924 #if rbus 2925 /* 2926 * static int 2927 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2928 * bus_addr_t addr, bus_size_t size, 2929 * bus_addr_t mask, bus_size_t align, 2930 * int flags, bus_addr_t *addrp; 2931 * bus_space_handle_t *bshp) 2932 * 2933 * This function allocates a portion of memory or io space for 2934 * clients. This function is called from CardBus card drivers. 2935 */ 2936 static int 2937 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2938 cardbus_chipset_tag_t ct; 2939 rbus_tag_t rb; 2940 bus_addr_t addr; 2941 bus_size_t size; 2942 bus_addr_t mask; 2943 bus_size_t align; 2944 int flags; 2945 bus_addr_t *addrp; 2946 bus_space_handle_t *bshp; 2947 { 2948 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2949 2950 DPRINTF( 2951 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2952 addr, size, mask, align)); 2953 2954 if (align == 0) { 2955 align = size; 2956 } 2957 2958 if (rb->rb_bt == sc->sc_memt) { 2959 if (align < 16) { 2960 return 1; 2961 } 2962 if (align < 0x1000) { 2963 align = 0x1000; 2964 } 2965 } else if (rb->rb_bt == sc->sc_iot) { 2966 if (align < 4) { 2967 return 1; 2968 } 2969 /* XXX: hack for avoiding ISA image */ 2970 if (mask < 0x0100) { 2971 mask = 0x3ff; 2972 addr = 0x300; 2973 } 2974 2975 } else { 2976 DPRINTF( 2977 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 2978 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 2979 return 1; 2980 /* XXX: panic here? */ 2981 } 2982 2983 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2984 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2985 return 1; 2986 } 2987 2988 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2989 2990 return 0; 2991 } 2992 2993 /* 2994 * static int 2995 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2996 * bus_space_handle_t *bshp, bus_size_t size); 2997 * 2998 * This function is called from CardBus card drivers. 2999 */ 3000 static int 3001 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3002 cardbus_chipset_tag_t ct; 3003 rbus_tag_t rb; 3004 bus_space_handle_t bsh; 3005 bus_size_t size; 3006 { 3007 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3008 bus_space_tag_t bt = rb->rb_bt; 3009 3010 pccbb_close_win(sc, bt, bsh, size); 3011 3012 if (bt == sc->sc_memt) { 3013 } else if (bt == sc->sc_iot) { 3014 } else { 3015 return 1; 3016 /* XXX: panic here? */ 3017 } 3018 3019 return rbus_space_free(rb, bsh, size, NULL); 3020 } 3021 #endif /* rbus */ 3022 3023 #if rbus 3024 3025 static int 3026 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3027 struct pccbb_softc *sc; 3028 bus_space_tag_t bst; 3029 bus_addr_t addr; 3030 bus_size_t size; 3031 bus_space_handle_t bsh; 3032 int flags; 3033 { 3034 struct pccbb_win_chain_head *head; 3035 bus_addr_t align; 3036 3037 head = &sc->sc_iowindow; 3038 align = 0x04; 3039 if (sc->sc_memt == bst) { 3040 head = &sc->sc_memwindow; 3041 align = 0x1000; 3042 DPRINTF(("using memory window, %x %x %x\n\n", 3043 sc->sc_iot, sc->sc_memt, bst)); 3044 } 3045 3046 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3047 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3048 sc->sc_dev.dv_xname, 3049 (head == &sc->sc_memwindow) ? "mem" : "io"); 3050 } 3051 pccbb_winset(align, sc, bst); 3052 3053 return 0; 3054 } 3055 3056 static int 3057 pccbb_close_win(sc, bst, bsh, size) 3058 struct pccbb_softc *sc; 3059 bus_space_tag_t bst; 3060 bus_space_handle_t bsh; 3061 bus_size_t size; 3062 { 3063 struct pccbb_win_chain_head *head; 3064 bus_addr_t align; 3065 3066 head = &sc->sc_iowindow; 3067 align = 0x04; 3068 if (sc->sc_memt == bst) { 3069 head = &sc->sc_memwindow; 3070 align = 0x1000; 3071 } 3072 3073 if (pccbb_winlist_delete(head, bsh, size)) { 3074 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3075 sc->sc_dev.dv_xname, 3076 (head == &sc->sc_memwindow) ? "mem" : "io"); 3077 } 3078 pccbb_winset(align, sc, bst); 3079 3080 return 0; 3081 } 3082 3083 static int 3084 pccbb_winlist_insert(head, start, size, bsh, flags) 3085 struct pccbb_win_chain_head *head; 3086 bus_addr_t start; 3087 bus_size_t size; 3088 bus_space_handle_t bsh; 3089 int flags; 3090 { 3091 struct pccbb_win_chain *chainp, *elem; 3092 3093 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3094 M_NOWAIT)) == NULL) 3095 return (1); /* fail */ 3096 3097 elem->wc_start = start; 3098 elem->wc_end = start + (size - 1); 3099 elem->wc_handle = bsh; 3100 elem->wc_flags = flags; 3101 3102 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3103 chainp = TAILQ_NEXT(chainp, wc_list)) { 3104 if (chainp->wc_end < start) 3105 continue; 3106 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3107 return (0); 3108 } 3109 3110 TAILQ_INSERT_TAIL(head, elem, wc_list); 3111 return (0); 3112 } 3113 3114 static int 3115 pccbb_winlist_delete(head, bsh, size) 3116 struct pccbb_win_chain_head *head; 3117 bus_space_handle_t bsh; 3118 bus_size_t size; 3119 { 3120 struct pccbb_win_chain *chainp; 3121 3122 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3123 chainp = TAILQ_NEXT(chainp, wc_list)) { 3124 if (chainp->wc_handle != bsh) 3125 continue; 3126 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3127 printf("pccbb_winlist_delete: window 0x%lx size " 3128 "inconsistent: 0x%lx, 0x%lx\n", 3129 (unsigned long)chainp->wc_start, 3130 (unsigned long)(chainp->wc_end - chainp->wc_start), 3131 (unsigned long)(size - 1)); 3132 return 1; 3133 } 3134 3135 TAILQ_REMOVE(head, chainp, wc_list); 3136 free(chainp, M_DEVBUF); 3137 3138 return 0; 3139 } 3140 3141 return 1; /* fail: no candidate to remove */ 3142 } 3143 3144 static void 3145 pccbb_winset(align, sc, bst) 3146 bus_addr_t align; 3147 struct pccbb_softc *sc; 3148 bus_space_tag_t bst; 3149 { 3150 pci_chipset_tag_t pc; 3151 pcitag_t tag; 3152 bus_addr_t mask = ~(align - 1); 3153 struct { 3154 cardbusreg_t win_start; 3155 cardbusreg_t win_limit; 3156 int win_flags; 3157 } win[2]; 3158 struct pccbb_win_chain *chainp; 3159 int offs; 3160 3161 win[0].win_start = win[1].win_start = 0xffffffff; 3162 win[0].win_limit = win[1].win_limit = 0; 3163 win[0].win_flags = win[1].win_flags = 0; 3164 3165 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3166 offs = 0x2c; 3167 if (sc->sc_memt == bst) { 3168 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3169 offs = 0x1c; 3170 } 3171 3172 if (chainp != NULL) { 3173 win[0].win_start = chainp->wc_start & mask; 3174 win[0].win_limit = chainp->wc_end & mask; 3175 win[0].win_flags = chainp->wc_flags; 3176 chainp = TAILQ_NEXT(chainp, wc_list); 3177 } 3178 3179 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3180 if (win[1].win_start == 0xffffffff) { 3181 /* window 1 is not used */ 3182 if ((win[0].win_flags == chainp->wc_flags) && 3183 (win[0].win_limit + align >= 3184 (chainp->wc_start & mask))) { 3185 /* concatenate */ 3186 win[0].win_limit = chainp->wc_end & mask; 3187 } else { 3188 /* make new window */ 3189 win[1].win_start = chainp->wc_start & mask; 3190 win[1].win_limit = chainp->wc_end & mask; 3191 win[1].win_flags = chainp->wc_flags; 3192 } 3193 continue; 3194 } 3195 3196 /* Both windows are engaged. */ 3197 if (win[0].win_flags == win[1].win_flags) { 3198 /* same flags */ 3199 if (win[0].win_flags == chainp->wc_flags) { 3200 if (win[1].win_start - (win[0].win_limit + 3201 align) < 3202 (chainp->wc_start & mask) - 3203 ((chainp->wc_end & mask) + align)) { 3204 /* 3205 * merge window 0 and 1, and set win1 3206 * to chainp 3207 */ 3208 win[0].win_limit = win[1].win_limit; 3209 win[1].win_start = 3210 chainp->wc_start & mask; 3211 win[1].win_limit = 3212 chainp->wc_end & mask; 3213 } else { 3214 win[1].win_limit = 3215 chainp->wc_end & mask; 3216 } 3217 } else { 3218 /* different flags */ 3219 3220 /* concatenate win0 and win1 */ 3221 win[0].win_limit = win[1].win_limit; 3222 /* allocate win[1] to new space */ 3223 win[1].win_start = chainp->wc_start & mask; 3224 win[1].win_limit = chainp->wc_end & mask; 3225 win[1].win_flags = chainp->wc_flags; 3226 } 3227 } else { 3228 /* the flags of win[0] and win[1] is different */ 3229 if (win[0].win_flags == chainp->wc_flags) { 3230 win[0].win_limit = chainp->wc_end & mask; 3231 /* 3232 * XXX this creates overlapping windows, so 3233 * what should the poor bridge do if one is 3234 * cachable, and the other is not? 3235 */ 3236 printf("%s: overlapping windows\n", 3237 sc->sc_dev.dv_xname); 3238 } else { 3239 win[1].win_limit = chainp->wc_end & mask; 3240 } 3241 } 3242 } 3243 3244 pc = sc->sc_pc; 3245 tag = sc->sc_tag; 3246 pci_conf_write(pc, tag, offs, win[0].win_start); 3247 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3248 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3249 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3250 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3251 pci_conf_read(pc, tag, offs), 3252 pci_conf_read(pc, tag, offs + 4) + align, 3253 pci_conf_read(pc, tag, offs + 8), 3254 pci_conf_read(pc, tag, offs + 12) + align)); 3255 3256 if (bst == sc->sc_memt) { 3257 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3258 3259 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3260 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3261 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3262 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3263 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3264 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3265 } 3266 } 3267 3268 #endif /* rbus */ 3269 3270 static void 3271 pccbb_powerhook(why, arg) 3272 int why; 3273 void *arg; 3274 { 3275 struct pccbb_softc *sc = arg; 3276 pcireg_t reg; 3277 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3278 bus_space_handle_t base_memh = sc->sc_base_memh; 3279 3280 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3281 3282 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3283 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3284 if (sc->sc_pil_intr_enable) { 3285 (void)pccbbintr_function(sc); 3286 } 3287 sc->sc_pil_intr_enable = 0; 3288 3289 /* ToDo: deactivate or suspend child devices */ 3290 3291 } 3292 3293 if (why == PWR_RESUME) { 3294 if (sc->sc_pwrmgt_offs != 0) { 3295 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3296 sc->sc_pwrmgt_offs + 4); 3297 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3298 reg & 0x100) { 3299 /* powrstate != D0 */ 3300 3301 printf("%s going back to D0 mode\n", 3302 sc->sc_dev.dv_xname); 3303 reg &= ~PCI_PMCSR_STATE_MASK; 3304 reg |= PCI_PMCSR_STATE_D0; 3305 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3306 pci_conf_write(sc->sc_pc, sc->sc_tag, 3307 sc->sc_pwrmgt_offs + 4, reg); 3308 3309 pci_conf_write(sc->sc_pc, sc->sc_tag, 3310 PCI_SOCKBASE, sc->sc_sockbase); 3311 pci_conf_write(sc->sc_pc, sc->sc_tag, 3312 PCI_BUSNUM, sc->sc_busnum); 3313 pccbb_chipinit(sc); 3314 /* setup memory and io space window for CB */ 3315 pccbb_winset(0x1000, sc, sc->sc_memt); 3316 pccbb_winset(0x04, sc, sc->sc_iot); 3317 } 3318 } 3319 3320 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3321 /* BIOS did not recover this register */ 3322 pci_conf_write (sc->sc_pc, sc->sc_tag, 3323 PCI_SOCKBASE, sc->sc_sockbase); 3324 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3325 /* BIOS did not recover this register */ 3326 pci_conf_write (sc->sc_pc, sc->sc_tag, 3327 PCI_BUSNUM, sc->sc_busnum); 3328 /* CSC Interrupt: Card detect interrupt on */ 3329 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3330 /* Card detect intr is turned on. */ 3331 reg |= CB_SOCKET_MASK_CD; 3332 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3333 /* reset interrupt */ 3334 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3335 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3336 3337 /* 3338 * check for card insertion or removal during suspend period. 3339 * XXX: the code can't cope with card swap (remove then 3340 * insert). how can we detect such situation? 3341 */ 3342 (void)pccbbintr(sc); 3343 3344 sc->sc_pil_intr_enable = 1; 3345 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3346 3347 /* ToDo: activate or wakeup child devices */ 3348 } 3349 } 3350
Indexes created Sat Sep 27 14:09:57 GMT 2025