pccbb.c revision 1.73
1 /* $NetBSD: pccbb.c,v 1.73 2001/12/24 09:41:34 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.73 2001/12/24 09:41:34 christos Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 struct cfattach cbb_pci_ca = { 230 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 231 }; 232 233 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 234 pccbb_pcmcia_mem_alloc, 235 pccbb_pcmcia_mem_free, 236 pccbb_pcmcia_mem_map, 237 pccbb_pcmcia_mem_unmap, 238 pccbb_pcmcia_io_alloc, 239 pccbb_pcmcia_io_free, 240 pccbb_pcmcia_io_map, 241 pccbb_pcmcia_io_unmap, 242 pccbb_pcmcia_intr_establish, 243 pccbb_pcmcia_intr_disestablish, 244 pccbb_pcmcia_socket_enable, 245 pccbb_pcmcia_socket_disable, 246 pccbb_pcmcia_card_detect 247 }; 248 249 #if rbus 250 static struct cardbus_functions pccbb_funcs = { 251 pccbb_rbus_cb_space_alloc, 252 pccbb_rbus_cb_space_free, 253 pccbb_cb_intr_establish, 254 pccbb_cb_intr_disestablish, 255 pccbb_ctrl, 256 pccbb_power, 257 pccbb_make_tag, 258 pccbb_free_tag, 259 pccbb_conf_read, 260 pccbb_conf_write, 261 }; 262 #else 263 static struct cardbus_functions pccbb_funcs = { 264 pccbb_ctrl, 265 pccbb_power, 266 pccbb_mem_open, 267 pccbb_mem_close, 268 pccbb_io_open, 269 pccbb_io_close, 270 pccbb_cb_intr_establish, 271 pccbb_cb_intr_disestablish, 272 pccbb_make_tag, 273 pccbb_conf_read, 274 pccbb_conf_write, 275 }; 276 #endif 277 278 int 279 pcicbbmatch(parent, match, aux) 280 struct device *parent; 281 struct cfdata *match; 282 void *aux; 283 { 284 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 285 286 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 287 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 288 PCI_INTERFACE(pa->pa_class) == 0) { 289 return 1; 290 } 291 292 return 0; 293 } 294 295 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 296 | ((prod) << PCI_PRODUCT_SHIFT)) 297 298 const struct yenta_chipinfo { 299 pcireg_t yc_id; /* vendor tag | product tag */ 300 int yc_chiptype; 301 int yc_flags; 302 } yc_chipsets[] = { 303 /* Texas Instruments chips */ 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 331 /* Ricoh chips */ 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 345 /* Toshiba products */ 346 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 347 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 349 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 351 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 355 /* Cirrus Logic products */ 356 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 357 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 361 /* sentinel, or Generic chip */ 362 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 363 }; 364 365 static int 366 cb_chipset(pci_id, flagp) 367 u_int32_t pci_id; 368 int *flagp; 369 { 370 const struct yenta_chipinfo *yc; 371 372 /* Loop over except the last default entry. */ 373 for (yc = yc_chipsets; yc < yc_chipsets + 374 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 375 if (pci_id == yc->yc_id) 376 break; 377 378 if (flagp != NULL) 379 *flagp = yc->yc_flags; 380 381 return (yc->yc_chiptype); 382 } 383 384 static void 385 pccbb_shutdown(void *arg) 386 { 387 struct pccbb_softc *sc = arg; 388 pcireg_t command; 389 390 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 391 392 /* 393 * turn off power 394 * 395 * XXX - do not turn off power if chipset is TI 113X because 396 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 397 */ 398 if (sc->sc_chipset != CB_TI113X) { 399 pccbb_power((cardbus_chipset_tag_t)sc, 400 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 401 } 402 403 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 404 0); 405 406 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 407 408 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 409 PCI_COMMAND_MASTER_ENABLE); 410 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 411 412 } 413 414 void 415 pccbbattach(parent, self, aux) 416 struct device *parent; 417 struct device *self; 418 void *aux; 419 { 420 struct pccbb_softc *sc = (void *)self; 421 struct pci_attach_args *pa = aux; 422 pci_chipset_tag_t pc = pa->pa_pc; 423 pcireg_t busreg, reg, sock_base; 424 bus_addr_t sockbase; 425 char devinfo[256]; 426 int flags; 427 int pwrmgt_offs; 428 429 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 430 431 pci_devinfo(pa->pa_id, 0, 0, devinfo); 432 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 433 #ifdef CBB_DEBUG 434 printf(" (chipflags %x)", flags); 435 #endif 436 printf("\n"); 437 438 TAILQ_INIT(&sc->sc_memwindow); 439 TAILQ_INIT(&sc->sc_iowindow); 440 441 #if rbus 442 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 443 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 444 445 #if 0 446 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 447 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 448 #endif 449 #endif /* rbus */ 450 451 sc->sc_base_memh = 0; 452 453 /* power management: set D0 state */ 454 sc->sc_pwrmgt_offs = 0; 455 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 456 &pwrmgt_offs, 0)) { 457 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + 4); 458 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 459 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 460 reg &= ~PCI_PMCSR_STATE_MASK; 461 reg |= PCI_PMCSR_STATE_D0; 462 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 463 pci_conf_write(pc, pa->pa_tag, pwrmgt_offs + 4, reg); 464 } 465 466 sc->sc_pwrmgt_offs = pwrmgt_offs; 467 } 468 469 /* 470 * MAP socket registers and ExCA registers on memory-space 471 * When no valid address is set on socket base registers (on pci 472 * config space), get it not polite way. 473 */ 474 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 475 476 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 477 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 478 /* The address must be valid. */ 479 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 480 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 481 printf("%s: can't map socket base address 0x%x\n", 482 sc->sc_dev.dv_xname, sock_base); 483 /* 484 * I think it's funny: socket base registers must be 485 * mapped on memory space, but ... 486 */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 488 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 489 NULL)) { 490 printf("%s: can't map socket base address" 491 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 492 (unsigned long)sockbase); 493 /* give up... allocate reg space via rbus. */ 494 sc->sc_base_memh = 0; 495 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 496 } 497 } else { 498 DPRINTF(("%s: socket base address 0x%lx\n", 499 sc->sc_dev.dv_xname, sockbase)); 500 } 501 } 502 503 sc->sc_mem_start = 0; /* XXX */ 504 sc->sc_mem_end = 0xffffffff; /* XXX */ 505 506 /* 507 * When interrupt isn't routed correctly, give up probing cbb and do 508 * not kill pcic-compatible port. 509 */ 510 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 511 printf("%s: NOT USED because of unconfigured interrupt\n", 512 sc->sc_dev.dv_xname); 513 return; 514 } 515 516 /* 517 * When bus number isn't set correctly, give up using 32-bit CardBus 518 * mode. 519 */ 520 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 521 #if notyet 522 if (((busreg >> 8) & 0xff) == 0) { 523 printf("%s: CardBus support disabled because of unconfigured bus number\n", 524 sc->sc_dev.dv_xname); 525 flags |= PCCBB_PCMCIA_16BITONLY; 526 } 527 #endif 528 529 /* pccbb_machdep.c end */ 530 531 #if defined CBB_DEBUG 532 { 533 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 534 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 535 intrname[pa->pa_intrpin], pa->pa_intrline); 536 } 537 #endif 538 539 /* setup softc */ 540 sc->sc_pc = pc; 541 sc->sc_iot = pa->pa_iot; 542 sc->sc_memt = pa->pa_memt; 543 sc->sc_dmat = pa->pa_dmat; 544 sc->sc_tag = pa->pa_tag; 545 sc->sc_function = pa->pa_function; 546 sc->sc_sockbase = sock_base; 547 sc->sc_busnum = busreg; 548 549 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 550 551 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 552 553 shutdownhook_establish(pccbb_shutdown, sc); 554 555 /* Disable legacy register mapping. */ 556 switch (sc->sc_chipset) { 557 case CB_RX5C46X: /* fallthrough */ 558 #if 0 559 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 560 case CB_RX5C47X: 561 #endif 562 /* 563 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 564 * cannot be disabled by substituting 0 into PCI_LEGACY 565 * register. Ricoh CardBus bridges have special bits on Bridge 566 * control reg (addr 0x3e on PCI config space). 567 */ 568 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 569 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 570 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 571 break; 572 573 default: 574 /* XXX I don't know proper way to kill legacy I/O. */ 575 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 576 break; 577 } 578 579 config_defer(self, pccbb_pci_callback); 580 } 581 582 583 584 585 /* 586 * static void pccbb_pci_callback(struct device *self) 587 * 588 * The actual attach routine: get memory space for YENTA register 589 * space, setup YENTA register and route interrupt. 590 * 591 * This function should be deferred because this device may obtain 592 * memory space dynamically. This function must avoid obtaining 593 * memory area which has already kept for another device. 594 */ 595 static void 596 pccbb_pci_callback(self) 597 struct device *self; 598 { 599 struct pccbb_softc *sc = (void *)self; 600 pci_chipset_tag_t pc = sc->sc_pc; 601 pci_intr_handle_t ih; 602 const char *intrstr = NULL; 603 bus_addr_t sockbase; 604 struct cbslot_attach_args cba; 605 struct pcmciabus_attach_args paa; 606 struct cardslot_attach_args caa; 607 struct cardslot_softc *csc; 608 609 if (0 == sc->sc_base_memh) { 610 /* The socket registers aren't mapped correctly. */ 611 #if rbus 612 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 613 (sc->sc_chipset == CB_RX5C47X 614 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 615 0, &sockbase, &sc->sc_base_memh)) { 616 return; 617 } 618 sc->sc_base_memt = sc->sc_memt; 619 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 620 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 621 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 622 PCI_SOCKBASE))); 623 #else 624 sc->sc_base_memt = sc->sc_memt; 625 #if !defined CBB_PCI_BASE 626 #define CBB_PCI_BASE 0x20000000 627 #endif 628 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 629 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 630 /* cannot allocate memory space */ 631 return; 632 } 633 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 634 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 635 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 636 sc->sc_tag, PCI_SOCKBASE))); 637 sc->sc_sockbase = sockbase; 638 #endif 639 } 640 641 /* bus bridge initialization */ 642 pccbb_chipinit(sc); 643 644 /* clear data structure for child device interrupt handlers */ 645 sc->sc_pil = NULL; 646 sc->sc_pil_intr_enable = 1; 647 648 /* Map and establish the interrupt. */ 649 if (pci_intr_map(&sc->sc_pa, &ih)) { 650 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 651 return; 652 } 653 intrstr = pci_intr_string(pc, ih); 654 655 /* 656 * XXX pccbbintr should be called under the priority lower 657 * than any other hard interrputs. 658 */ 659 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 660 661 if (sc->sc_ih == NULL) { 662 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 663 if (intrstr != NULL) { 664 printf(" at %s", intrstr); 665 } 666 printf("\n"); 667 return; 668 } 669 670 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 671 powerhook_establish(pccbb_powerhook, sc); 672 673 { 674 u_int32_t sockstat; 675 676 sockstat = bus_space_read_4(sc->sc_base_memt, 677 sc->sc_base_memh, CB_SOCKET_STAT); 678 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 679 sc->sc_flags |= CBB_CARDEXIST; 680 } 681 } 682 683 /* 684 * attach cardbus 685 */ 686 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 687 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 688 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 689 690 /* initialize cbslot_attach */ 691 cba.cba_busname = "cardbus"; 692 cba.cba_iot = sc->sc_iot; 693 cba.cba_memt = sc->sc_memt; 694 cba.cba_dmat = sc->sc_dmat; 695 cba.cba_bus = (busreg >> 8) & 0x0ff; 696 cba.cba_cc = (void *)sc; 697 cba.cba_cf = &pccbb_funcs; 698 cba.cba_intrline = sc->sc_pa.pa_intrline; 699 700 #if rbus 701 cba.cba_rbus_iot = sc->sc_rbus_iot; 702 cba.cba_rbus_memt = sc->sc_rbus_memt; 703 #endif 704 705 cba.cba_cacheline = PCI_CACHELINE(bhlc); 706 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 707 708 if (bootverbose) { 709 printf("%s: cacheline 0x%x lattimer 0x%x\n", 710 sc->sc_dev.dv_xname, cba.cba_cacheline, 711 cba.cba_lattimer); 712 printf("%s: bhlc 0x%x lscp 0x%x\n", 713 sc->sc_dev.dv_xname, bhlc, busreg); 714 } 715 #if defined SHOW_REGS 716 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 717 sc->sc_base_memh); 718 #endif 719 } 720 721 pccbb_pcmcia_attach_setup(sc, &paa); 722 caa.caa_cb_attach = NULL; 723 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 724 caa.caa_cb_attach = &cba; 725 } 726 caa.caa_16_attach = &paa; 727 caa.caa_ph = &sc->sc_pcmcia_h; 728 729 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 730 DPRINTF(("pccbbattach: found cardslot\n")); 731 sc->sc_csc = csc; 732 } 733 734 return; 735 } 736 737 738 739 740 741 /* 742 * static void pccbb_chipinit(struct pccbb_softc *sc) 743 * 744 * This function initialize YENTA chip registers listed below: 745 * 1) PCI command reg, 746 * 2) PCI and CardBus latency timer, 747 * 3) route PCI interrupt, 748 * 4) close all memory and io windows. 749 * 5) turn off bus power. 750 * 6) card detect interrupt on. 751 * 7) clear interrupt 752 */ 753 static void 754 pccbb_chipinit(sc) 755 struct pccbb_softc *sc; 756 { 757 pci_chipset_tag_t pc = sc->sc_pc; 758 pcitag_t tag = sc->sc_tag; 759 bus_space_tag_t bmt = sc->sc_base_memt; 760 bus_space_handle_t bmh = sc->sc_base_memh; 761 pcireg_t reg; 762 763 /* 764 * Set PCI command reg. 765 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 766 */ 767 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 768 /* I believe it is harmless. */ 769 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 770 PCI_COMMAND_MASTER_ENABLE); 771 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 772 773 /* 774 * Set CardBus latency timer. 775 */ 776 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 777 if (PCI_CB_LATENCY(reg) < 0x20) { 778 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 779 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 780 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 781 } 782 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 783 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 784 785 /* 786 * Set PCI latency timer. 787 */ 788 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 789 if (PCI_LATTIMER(reg) < 0x10) { 790 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 791 reg |= (0x10 << PCI_LATTIMER_SHIFT); 792 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 793 } 794 DPRINTF(("PCI latency timer 0x%x (%x)\n", 795 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 796 797 798 /* Route functional interrupts to PCI. */ 799 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 800 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 801 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 802 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 803 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 804 805 switch (sc->sc_chipset) { 806 case CB_TI113X: 807 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 808 /* This bit is shared, but may read as 0 on some chips, so set 809 it explicitly on both functions. */ 810 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 811 /* CSC intr enable */ 812 reg |= PCI113X_CBCTRL_PCI_CSC; 813 /* functional intr prohibit | prohibit ISA routing */ 814 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 815 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 816 break; 817 818 case CB_TI12XX: 819 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 820 reg |= PCI12XX_SYSCTRL_VCCPROT; 821 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 822 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 823 reg |= PCI12XX_CBCTRL_CSC; 824 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 825 break; 826 827 case CB_TOPIC95B: 828 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 829 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 830 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 831 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 832 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 833 sc->sc_dev.dv_xname, reg)); 834 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 835 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 836 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 837 DPRINTF(("0x%x\n", reg)); 838 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 839 break; 840 841 case CB_TOPIC97: 842 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 843 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 844 sc->sc_dev.dv_xname, reg)); 845 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 846 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 847 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 848 reg |= TOPIC97_SLOT_CTRL_PCIINT; 849 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 850 DPRINTF(("0x%x\n", reg)); 851 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 852 /* make sure to assert LV card support bits */ 853 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 854 0x800 + 0x3e, 855 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 856 0x800 + 0x3e) | 0x03); 857 break; 858 } 859 860 /* Close all memory and I/O windows. */ 861 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 862 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 863 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 864 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 865 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 866 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 867 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 868 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 869 870 /* reset 16-bit pcmcia bus */ 871 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 872 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 873 874 /* turn off power */ 875 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 876 877 /* CSC Interrupt: Card detect interrupt on */ 878 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 879 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 880 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 881 /* reset interrupt */ 882 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 883 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 884 } 885 886 887 888 889 /* 890 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 891 * struct pcmciabus_attach_args *paa) 892 * 893 * This function attaches 16-bit PCcard bus. 894 */ 895 STATIC void 896 pccbb_pcmcia_attach_setup(sc, paa) 897 struct pccbb_softc *sc; 898 struct pcmciabus_attach_args *paa; 899 { 900 struct pcic_handle *ph = &sc->sc_pcmcia_h; 901 #if rbus 902 rbus_tag_t rb; 903 #endif 904 905 /* initialize pcmcia part in pccbb_softc */ 906 ph->ph_parent = (struct device *)sc; 907 ph->sock = sc->sc_function; 908 ph->flags = 0; 909 ph->shutdown = 0; 910 ph->ih_irq = sc->sc_pa.pa_intrline; 911 ph->ph_bus_t = sc->sc_base_memt; 912 ph->ph_bus_h = sc->sc_base_memh; 913 ph->ph_read = pccbb_pcmcia_read; 914 ph->ph_write = pccbb_pcmcia_write; 915 sc->sc_pct = &pccbb_pcmcia_funcs; 916 917 /* 918 * We need to do a few things here: 919 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 920 * setting the IRQ numbers to 0. 921 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 922 * routing of CSC interrupts (e.g. card removal) to PCI while in 923 * PCMCIA mode. We just leave this set all the time. 924 * 3) Enable card insertion/removal interrupts in case the chip also 925 * needs that while in PCMCIA mode. 926 * 4) Clear any pending CSC interrupt. 927 */ 928 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 929 if (sc->sc_chipset == CB_TI113X) { 930 Pcic_write(ph, PCIC_CSC_INTR, 0); 931 } else { 932 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 933 Pcic_read(ph, PCIC_CSC); 934 } 935 936 /* initialize pcmcia bus attachment */ 937 paa->paa_busname = "pcmcia"; 938 paa->pct = sc->sc_pct; 939 paa->pch = ph; 940 paa->iobase = 0; /* I don't use them */ 941 paa->iosize = 0; 942 #if rbus 943 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 944 paa->iobase = rb->rb_start + rb->rb_offset; 945 paa->iosize = rb->rb_end - rb->rb_start; 946 #endif 947 948 return; 949 } 950 951 #if 0 952 STATIC void 953 pccbb_pcmcia_attach_card(ph) 954 struct pcic_handle *ph; 955 { 956 if (ph->flags & PCIC_FLAG_CARDP) { 957 panic("pccbb_pcmcia_attach_card: already attached"); 958 } 959 960 /* call the MI attach function */ 961 pcmcia_card_attach(ph->pcmcia); 962 963 ph->flags |= PCIC_FLAG_CARDP; 964 } 965 966 STATIC void 967 pccbb_pcmcia_detach_card(ph, flags) 968 struct pcic_handle *ph; 969 int flags; 970 { 971 if (!(ph->flags & PCIC_FLAG_CARDP)) { 972 panic("pccbb_pcmcia_detach_card: already detached"); 973 } 974 975 ph->flags &= ~PCIC_FLAG_CARDP; 976 977 /* call the MI detach function */ 978 pcmcia_card_detach(ph->pcmcia, flags); 979 } 980 #endif 981 982 /* 983 * int pccbbintr(arg) 984 * void *arg; 985 * This routine handles the interrupt from Yenta PCI-CardBus bridge 986 * itself. 987 */ 988 int 989 pccbbintr(arg) 990 void *arg; 991 { 992 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 993 u_int32_t sockevent, sockstate; 994 bus_space_tag_t memt = sc->sc_base_memt; 995 bus_space_handle_t memh = sc->sc_base_memh; 996 struct pcic_handle *ph = &sc->sc_pcmcia_h; 997 998 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 999 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1000 Pcic_read(ph, PCIC_CSC); 1001 1002 if (sockevent == 0) { 1003 /* This intr is not for me: it may be for my child devices. */ 1004 if (sc->sc_pil_intr_enable) { 1005 return pccbbintr_function(sc); 1006 } else { 1007 return 0; 1008 } 1009 } 1010 1011 if (sockevent & CB_SOCKET_EVENT_CD) { 1012 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1013 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 1014 /* A card should be removed. */ 1015 if (sc->sc_flags & CBB_CARDEXIST) { 1016 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1017 sockevent)); 1018 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1019 sc->sc_flags &= ~CBB_CARDEXIST; 1020 if (sc->sc_csc->sc_status & 1021 CARDSLOT_STATUS_CARD_16) { 1022 #if 0 1023 struct pcic_handle *ph = 1024 &sc->sc_pcmcia_h; 1025 1026 pcmcia_card_deactivate(ph->pcmcia); 1027 pccbb_pcmcia_socket_disable(ph); 1028 pccbb_pcmcia_detach_card(ph, 1029 DETACH_FORCE); 1030 #endif 1031 cardslot_event_throw(sc->sc_csc, 1032 CARDSLOT_EVENT_REMOVAL_16); 1033 } else if (sc->sc_csc->sc_status & 1034 CARDSLOT_STATUS_CARD_CB) { 1035 /* Cardbus intr removed */ 1036 cardslot_event_throw(sc->sc_csc, 1037 CARDSLOT_EVENT_REMOVAL_CB); 1038 } 1039 } 1040 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1041 /* 1042 * The pccbbintr may called from powerdown hook when 1043 * the system resumed, to detect the card 1044 * insertion/removal during suspension. 1045 */ 1046 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1047 if (sc->sc_flags & CBB_INSERTING) { 1048 callout_stop(&sc->sc_insert_ch); 1049 } 1050 callout_reset(&sc->sc_insert_ch, hz / 10, 1051 pci113x_insert, sc); 1052 sc->sc_flags |= CBB_INSERTING; 1053 } 1054 } 1055 1056 return (1); 1057 } 1058 1059 /* 1060 * static int pccbbintr_function(struct pccbb_softc *sc) 1061 * 1062 * This function calls each interrupt handler registered at the 1063 * bridge. The interrupt handlers are called in registered order. 1064 */ 1065 static int 1066 pccbbintr_function(sc) 1067 struct pccbb_softc *sc; 1068 { 1069 int retval = 0, val; 1070 struct pccbb_intrhand_list *pil; 1071 int s, splchanged; 1072 1073 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1074 /* 1075 * XXX priority change. gross. I use if-else 1076 * sentense instead of switch-case sentense because of 1077 * avoiding duplicate case value error. More than one 1078 * IPL_XXX use same value. It depends on 1079 * implimentation. 1080 */ 1081 splchanged = 1; 1082 if (pil->pil_level == IPL_SERIAL) { 1083 s = splserial(); 1084 } else if (pil->pil_level == IPL_HIGH) { 1085 s = splhigh(); 1086 } else if (pil->pil_level == IPL_CLOCK) { 1087 s = splclock(); 1088 } else if (pil->pil_level == IPL_AUDIO) { 1089 s = splaudio(); 1090 } else if (pil->pil_level == IPL_IMP) { 1091 s = splvm(); /* XXX */ 1092 } else if (pil->pil_level == IPL_TTY) { 1093 s = spltty(); 1094 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1095 s = splsoftserial(); 1096 } else if (pil->pil_level == IPL_NET) { 1097 s = splnet(); 1098 } else { 1099 splchanged = 0; 1100 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1101 } 1102 1103 val = (*pil->pil_func)(pil->pil_arg); 1104 1105 if (splchanged != 0) { 1106 splx(s); 1107 } 1108 1109 retval = retval == 1 ? 1 : 1110 retval == 0 ? val : val != 0 ? val : retval; 1111 } 1112 1113 return retval; 1114 } 1115 1116 static void 1117 pci113x_insert(arg) 1118 void *arg; 1119 { 1120 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1121 u_int32_t sockevent, sockstate; 1122 1123 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1124 CB_SOCKET_EVENT); 1125 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1126 CB_SOCKET_STAT); 1127 1128 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1129 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1130 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1131 sc->sc_flags |= CBB_CARDEXIST; 1132 /* call pccard interrupt handler here */ 1133 if (sockstate & CB_SOCKET_STAT_16BIT) { 1134 /* 16-bit card found */ 1135 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1136 cardslot_event_throw(sc->sc_csc, 1137 CARDSLOT_EVENT_INSERTION_16); 1138 } else if (sockstate & CB_SOCKET_STAT_CB) { 1139 /* cardbus card found */ 1140 /* cardbus_attach_card(sc->sc_csc); */ 1141 cardslot_event_throw(sc->sc_csc, 1142 CARDSLOT_EVENT_INSERTION_CB); 1143 } else { 1144 /* who are you? */ 1145 } 1146 } else { 1147 callout_reset(&sc->sc_insert_ch, hz / 10, 1148 pci113x_insert, sc); 1149 } 1150 } 1151 1152 #define PCCBB_PCMCIA_OFFSET 0x800 1153 static u_int8_t 1154 pccbb_pcmcia_read(ph, reg) 1155 struct pcic_handle *ph; 1156 int reg; 1157 { 1158 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1159 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1160 1161 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1162 PCCBB_PCMCIA_OFFSET + reg); 1163 } 1164 1165 static void 1166 pccbb_pcmcia_write(ph, reg, val) 1167 struct pcic_handle *ph; 1168 int reg; 1169 u_int8_t val; 1170 { 1171 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1172 val); 1173 1174 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1175 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1176 } 1177 1178 /* 1179 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1180 */ 1181 STATIC int 1182 pccbb_ctrl(ct, command) 1183 cardbus_chipset_tag_t ct; 1184 int command; 1185 { 1186 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1187 1188 switch (command) { 1189 case CARDBUS_CD: 1190 if (2 == pccbb_detect_card(sc)) { 1191 int retval = 0; 1192 int status = cb_detect_voltage(sc); 1193 if (PCCARD_VCC_5V & status) { 1194 retval |= CARDBUS_5V_CARD; 1195 } 1196 if (PCCARD_VCC_3V & status) { 1197 retval |= CARDBUS_3V_CARD; 1198 } 1199 if (PCCARD_VCC_XV & status) { 1200 retval |= CARDBUS_XV_CARD; 1201 } 1202 if (PCCARD_VCC_YV & status) { 1203 retval |= CARDBUS_YV_CARD; 1204 } 1205 return retval; 1206 } else { 1207 return 0; 1208 } 1209 break; 1210 case CARDBUS_RESET: 1211 return cb_reset(sc); 1212 break; 1213 case CARDBUS_IO_ENABLE: /* fallthrough */ 1214 case CARDBUS_IO_DISABLE: /* fallthrough */ 1215 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1216 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1217 case CARDBUS_BM_ENABLE: /* fallthrough */ 1218 case CARDBUS_BM_DISABLE: /* fallthrough */ 1219 /* XXX: I think we don't need to call this function below. */ 1220 return pccbb_cardenable(sc, command); 1221 break; 1222 } 1223 1224 return 0; 1225 } 1226 1227 /* 1228 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1229 * This function returns true when it succeeds and returns false when 1230 * it fails. 1231 */ 1232 STATIC int 1233 pccbb_power(ct, command) 1234 cardbus_chipset_tag_t ct; 1235 int command; 1236 { 1237 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1238 1239 u_int32_t status, sock_ctrl; 1240 bus_space_tag_t memt = sc->sc_base_memt; 1241 bus_space_handle_t memh = sc->sc_base_memh; 1242 1243 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1244 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1245 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1246 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1247 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1248 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1249 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1250 "UNKNOWN", 1251 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1252 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1253 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1254 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1255 "UNKNOWN", command)); 1256 1257 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1258 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1259 1260 switch (command & CARDBUS_VCCMASK) { 1261 case CARDBUS_VCC_UC: 1262 break; 1263 case CARDBUS_VCC_5V: 1264 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1265 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1266 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1267 } else { 1268 printf("%s: BAD voltage request: no 5 V card\n", 1269 sc->sc_dev.dv_xname); 1270 } 1271 break; 1272 case CARDBUS_VCC_3V: 1273 if (CB_SOCKET_STAT_3VCARD & status) { 1274 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1275 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1276 } else { 1277 printf("%s: BAD voltage request: no 3.3 V card\n", 1278 sc->sc_dev.dv_xname); 1279 } 1280 break; 1281 case CARDBUS_VCC_0V: 1282 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1283 break; 1284 default: 1285 return 0; /* power NEVER changed */ 1286 break; 1287 } 1288 1289 switch (command & CARDBUS_VPPMASK) { 1290 case CARDBUS_VPP_UC: 1291 break; 1292 case CARDBUS_VPP_0V: 1293 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1294 break; 1295 case CARDBUS_VPP_VCC: 1296 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1297 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1298 break; 1299 case CARDBUS_VPP_12V: 1300 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1301 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1302 break; 1303 } 1304 1305 #if 0 1306 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1307 #endif 1308 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1309 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1310 1311 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1312 printf 1313 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1314 sc->sc_dev.dv_xname, sock_ctrl, status); 1315 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1316 (command & CARDBUS_VCCMASK) == 1317 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1318 CARDBUS_VCCMASK) == 1319 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1320 CARDBUS_VCCMASK) == 1321 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1322 CARDBUS_VCCMASK) == 1323 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1324 CARDBUS_VCCMASK) == 1325 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1326 CARDBUS_VCCMASK) == 1327 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1328 (command & CARDBUS_VPPMASK) == 1329 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1330 CARDBUS_VPPMASK) == 1331 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1332 CARDBUS_VPPMASK) == 1333 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1334 CARDBUS_VPPMASK) == 1335 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1336 #if 0 1337 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1338 u_int32_t force = 1339 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1340 /* Reset Bad Vcc request */ 1341 force &= ~CB_SOCKET_FORCE_BADVCC; 1342 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1343 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1344 CB_SOCKET_STAT)); 1345 return 1; 1346 } 1347 #endif 1348 return 0; 1349 } 1350 1351 /* 1352 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1353 * time is 20 ms, some PC-Card bridge requires longer duration. 1354 */ 1355 #if 0 /* XXX called on interrupt context */ 1356 DELAY_MS(300, sc); 1357 #else 1358 delay(300 * 1000); 1359 #endif 1360 1361 return 1; /* power changed correctly */ 1362 } 1363 1364 #if defined CB_PCMCIA_POLL 1365 struct cb_poll_str { 1366 void *arg; 1367 int (*func) __P((void *)); 1368 int level; 1369 pccard_chipset_tag_t ct; 1370 int count; 1371 struct callout poll_ch; 1372 }; 1373 1374 static struct cb_poll_str cb_poll[10]; 1375 static int cb_poll_n = 0; 1376 1377 static void cb_pcmcia_poll __P((void *arg)); 1378 1379 static void 1380 cb_pcmcia_poll(arg) 1381 void *arg; 1382 { 1383 struct cb_poll_str *poll = arg; 1384 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1385 struct pccbb_softc *sc = psc->cpc_parent; 1386 int s; 1387 u_int32_t spsr; /* socket present-state reg */ 1388 1389 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1390 switch (poll->level) { 1391 case IPL_NET: 1392 s = splnet(); 1393 break; 1394 case IPL_BIO: 1395 s = splbio(); 1396 break; 1397 case IPL_TTY: /* fallthrough */ 1398 default: 1399 s = spltty(); 1400 break; 1401 } 1402 1403 spsr = 1404 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1405 CB_SOCKET_STAT); 1406 1407 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1408 if (!(spsr & 0x40)) { /* CINT low */ 1409 #else 1410 if (1) { 1411 #endif 1412 if ((*poll->func) (poll->arg) == 1) { 1413 ++poll->count; 1414 printf("intr: reported from poller, 0x%x\n", spsr); 1415 #if defined LEVEL2 1416 } else { 1417 printf("intr: miss! 0x%x\n", spsr); 1418 #endif 1419 } 1420 } 1421 splx(s); 1422 } 1423 #endif /* defined CB_PCMCIA_POLL */ 1424 1425 /* 1426 * static int pccbb_detect_card(struct pccbb_softc *sc) 1427 * return value: 0 if no card exists. 1428 * 1 if 16-bit card exists. 1429 * 2 if cardbus card exists. 1430 */ 1431 static int 1432 pccbb_detect_card(sc) 1433 struct pccbb_softc *sc; 1434 { 1435 bus_space_handle_t base_memh = sc->sc_base_memh; 1436 bus_space_tag_t base_memt = sc->sc_base_memt; 1437 u_int32_t sockstat = 1438 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1439 int retval = 0; 1440 1441 /* CD1 and CD2 asserted */ 1442 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1443 /* card must be present */ 1444 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1445 /* NOTACARD DEASSERTED */ 1446 if (CB_SOCKET_STAT_CB & sockstat) { 1447 /* CardBus mode */ 1448 retval = 2; 1449 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1450 /* 16-bit mode */ 1451 retval = 1; 1452 } 1453 } 1454 } 1455 return retval; 1456 } 1457 1458 /* 1459 * STATIC int cb_reset(struct pccbb_softc *sc) 1460 * This function resets CardBus card. 1461 */ 1462 STATIC int 1463 cb_reset(sc) 1464 struct pccbb_softc *sc; 1465 { 1466 /* 1467 * Reset Assert at least 20 ms 1468 * Some machines request longer duration. 1469 */ 1470 int reset_duration = 1471 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1472 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1473 1474 /* Reset bit Assert (bit 6 at 0x3E) */ 1475 bcr |= CB_BCR_RESET_ENABLE; 1476 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1477 DELAY_MS(reset_duration, sc); 1478 1479 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1480 /* Reset bit Deassert (bit 6 at 0x3E) */ 1481 bcr &= ~CB_BCR_RESET_ENABLE; 1482 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1483 DELAY_MS(reset_duration, sc); 1484 } 1485 /* No card found on the slot. Keep Reset. */ 1486 return 1; 1487 } 1488 1489 /* 1490 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1491 * This function detect card Voltage. 1492 */ 1493 STATIC int 1494 cb_detect_voltage(sc) 1495 struct pccbb_softc *sc; 1496 { 1497 u_int32_t psr; /* socket present-state reg */ 1498 bus_space_tag_t iot = sc->sc_base_memt; 1499 bus_space_handle_t ioh = sc->sc_base_memh; 1500 int vol = PCCARD_VCC_UKN; /* set 0 */ 1501 1502 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1503 1504 if (0x400u & psr) { 1505 vol |= PCCARD_VCC_5V; 1506 } 1507 if (0x800u & psr) { 1508 vol |= PCCARD_VCC_3V; 1509 } 1510 1511 return vol; 1512 } 1513 1514 STATIC int 1515 cbbprint(aux, pcic) 1516 void *aux; 1517 const char *pcic; 1518 { 1519 /* 1520 struct cbslot_attach_args *cba = aux; 1521 1522 if (cba->cba_slot >= 0) { 1523 printf(" slot %d", cba->cba_slot); 1524 } 1525 */ 1526 return UNCONF; 1527 } 1528 1529 /* 1530 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1531 * This function enables and disables the card 1532 */ 1533 STATIC int 1534 pccbb_cardenable(sc, function) 1535 struct pccbb_softc *sc; 1536 int function; 1537 { 1538 u_int32_t command = 1539 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1540 1541 DPRINTF(("pccbb_cardenable:")); 1542 switch (function) { 1543 case CARDBUS_IO_ENABLE: 1544 command |= PCI_COMMAND_IO_ENABLE; 1545 break; 1546 case CARDBUS_IO_DISABLE: 1547 command &= ~PCI_COMMAND_IO_ENABLE; 1548 break; 1549 case CARDBUS_MEM_ENABLE: 1550 command |= PCI_COMMAND_MEM_ENABLE; 1551 break; 1552 case CARDBUS_MEM_DISABLE: 1553 command &= ~PCI_COMMAND_MEM_ENABLE; 1554 break; 1555 case CARDBUS_BM_ENABLE: 1556 command |= PCI_COMMAND_MASTER_ENABLE; 1557 break; 1558 case CARDBUS_BM_DISABLE: 1559 command &= ~PCI_COMMAND_MASTER_ENABLE; 1560 break; 1561 default: 1562 return 0; 1563 } 1564 1565 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1566 DPRINTF((" command reg 0x%x\n", command)); 1567 return 1; 1568 } 1569 1570 #if !rbus 1571 /* 1572 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1573 */ 1574 static int 1575 pccbb_io_open(ct, win, start, end) 1576 cardbus_chipset_tag_t ct; 1577 int win; 1578 u_int32_t start, end; 1579 { 1580 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1581 int basereg; 1582 int limitreg; 1583 1584 if ((win < 0) || (win > 2)) { 1585 #if defined DIAGNOSTIC 1586 printf("cardbus_io_open: window out of range %d\n", win); 1587 #endif 1588 return 0; 1589 } 1590 1591 basereg = win * 8 + 0x2c; 1592 limitreg = win * 8 + 0x30; 1593 1594 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1595 start, basereg, end, limitreg)); 1596 1597 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1598 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1599 return 1; 1600 } 1601 1602 /* 1603 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1604 */ 1605 static int 1606 pccbb_io_close(ct, win) 1607 cardbus_chipset_tag_t ct; 1608 int win; 1609 { 1610 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1611 int basereg; 1612 int limitreg; 1613 1614 if ((win < 0) || (win > 2)) { 1615 #if defined DIAGNOSTIC 1616 printf("cardbus_io_close: window out of range %d\n", win); 1617 #endif 1618 return 0; 1619 } 1620 1621 basereg = win * 8 + 0x2c; 1622 limitreg = win * 8 + 0x30; 1623 1624 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1625 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1626 return 1; 1627 } 1628 1629 /* 1630 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1631 */ 1632 static int 1633 pccbb_mem_open(ct, win, start, end) 1634 cardbus_chipset_tag_t ct; 1635 int win; 1636 u_int32_t start, end; 1637 { 1638 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1639 int basereg; 1640 int limitreg; 1641 1642 if ((win < 0) || (win > 2)) { 1643 #if defined DIAGNOSTIC 1644 printf("cardbus_mem_open: window out of range %d\n", win); 1645 #endif 1646 return 0; 1647 } 1648 1649 basereg = win * 8 + 0x1c; 1650 limitreg = win * 8 + 0x20; 1651 1652 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1653 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1654 return 1; 1655 } 1656 1657 /* 1658 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1659 */ 1660 static int 1661 pccbb_mem_close(ct, win) 1662 cardbus_chipset_tag_t ct; 1663 int win; 1664 { 1665 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1666 int basereg; 1667 int limitreg; 1668 1669 if ((win < 0) || (win > 2)) { 1670 #if defined DIAGNOSTIC 1671 printf("cardbus_mem_close: window out of range %d\n", win); 1672 #endif 1673 return 0; 1674 } 1675 1676 basereg = win * 8 + 0x1c; 1677 limitreg = win * 8 + 0x20; 1678 1679 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1680 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1681 return 1; 1682 } 1683 #endif 1684 1685 /* 1686 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1687 * int irq, 1688 * int level, 1689 * int (* func) __P((void *)), 1690 * void *arg) 1691 * 1692 * This function registers an interrupt handler at the bridge, in 1693 * order not to call the interrupt handlers of child devices when 1694 * a card-deletion interrupt occurs. 1695 * 1696 * The arguments irq and level are not used. 1697 */ 1698 static void * 1699 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1700 cardbus_chipset_tag_t ct; 1701 int irq, level; 1702 int (*func) __P((void *)); 1703 void *arg; 1704 { 1705 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1706 1707 return pccbb_intr_establish(sc, irq, level, func, arg); 1708 } 1709 1710 1711 /* 1712 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1713 * void *ih) 1714 * 1715 * This function removes an interrupt handler pointed by ih. 1716 */ 1717 static void 1718 pccbb_cb_intr_disestablish(ct, ih) 1719 cardbus_chipset_tag_t ct; 1720 void *ih; 1721 { 1722 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1723 1724 pccbb_intr_disestablish(sc, ih); 1725 } 1726 1727 1728 void 1729 pccbb_intr_route(sc) 1730 struct pccbb_softc *sc; 1731 { 1732 pcireg_t reg; 1733 1734 /* initialize bridge intr routing */ 1735 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1736 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1737 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1738 1739 switch (sc->sc_chipset) { 1740 case CB_TI113X: 1741 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1742 /* functional intr enabled */ 1743 reg |= PCI113X_CBCTRL_PCI_INTR; 1744 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1745 break; 1746 default: 1747 break; 1748 } 1749 } 1750 1751 /* 1752 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1753 * int irq, 1754 * int level, 1755 * int (* func) __P((void *)), 1756 * void *arg) 1757 * 1758 * This function registers an interrupt handler at the bridge, in 1759 * order not to call the interrupt handlers of child devices when 1760 * a card-deletion interrupt occurs. 1761 * 1762 * The arguments irq is not used because pccbb selects intr vector. 1763 */ 1764 static void * 1765 pccbb_intr_establish(sc, irq, level, func, arg) 1766 struct pccbb_softc *sc; 1767 int irq, level; 1768 int (*func) __P((void *)); 1769 void *arg; 1770 { 1771 struct pccbb_intrhand_list *pil, *newpil; 1772 1773 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1774 1775 if (sc->sc_pil == NULL) { 1776 pccbb_intr_route(sc); 1777 1778 } 1779 1780 /* 1781 * Allocate a room for interrupt handler structure. 1782 */ 1783 if (NULL == (newpil = 1784 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1785 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1786 return NULL; 1787 } 1788 1789 newpil->pil_func = func; 1790 newpil->pil_arg = arg; 1791 newpil->pil_level = level; 1792 newpil->pil_next = NULL; 1793 1794 if (sc->sc_pil == NULL) { 1795 sc->sc_pil = newpil; 1796 } else { 1797 for (pil = sc->sc_pil; pil->pil_next != NULL; 1798 pil = pil->pil_next); 1799 pil->pil_next = newpil; 1800 } 1801 1802 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1803 1804 return newpil; 1805 } 1806 1807 /* 1808 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1809 * void *ih) 1810 * 1811 * This function removes an interrupt handler pointed by ih. 1812 */ 1813 static void 1814 pccbb_intr_disestablish(sc, ih) 1815 struct pccbb_softc *sc; 1816 void *ih; 1817 { 1818 struct pccbb_intrhand_list *pil, **pil_prev; 1819 pcireg_t reg; 1820 1821 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1822 1823 pil_prev = &sc->sc_pil; 1824 1825 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1826 if (pil == ih) { 1827 *pil_prev = pil->pil_next; 1828 free(pil, M_DEVBUF); 1829 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1830 break; 1831 } 1832 pil_prev = &pil->pil_next; 1833 } 1834 1835 if (sc->sc_pil == NULL) { 1836 /* No interrupt handlers */ 1837 1838 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1839 1840 /* stop routing PCI intr */ 1841 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1842 reg |= CB_BCR_INTR_IREQ_ENABLE; 1843 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1844 1845 switch (sc->sc_chipset) { 1846 case CB_TI113X: 1847 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1848 /* functional intr disabled */ 1849 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1850 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1851 break; 1852 default: 1853 break; 1854 } 1855 } 1856 } 1857 1858 #if defined SHOW_REGS 1859 static void 1860 cb_show_regs(pc, tag, memt, memh) 1861 pci_chipset_tag_t pc; 1862 pcitag_t tag; 1863 bus_space_tag_t memt; 1864 bus_space_handle_t memh; 1865 { 1866 int i; 1867 printf("PCI config regs:"); 1868 for (i = 0; i < 0x50; i += 4) { 1869 if (i % 16 == 0) { 1870 printf("\n 0x%02x:", i); 1871 } 1872 printf(" %08x", pci_conf_read(pc, tag, i)); 1873 } 1874 for (i = 0x80; i < 0xb0; i += 4) { 1875 if (i % 16 == 0) { 1876 printf("\n 0x%02x:", i); 1877 } 1878 printf(" %08x", pci_conf_read(pc, tag, i)); 1879 } 1880 1881 if (memh == 0) { 1882 printf("\n"); 1883 return; 1884 } 1885 1886 printf("\nsocket regs:"); 1887 for (i = 0; i <= 0x10; i += 0x04) { 1888 printf(" %08x", bus_space_read_4(memt, memh, i)); 1889 } 1890 printf("\nExCA regs:"); 1891 for (i = 0; i < 0x08; ++i) { 1892 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1893 } 1894 printf("\n"); 1895 return; 1896 } 1897 #endif 1898 1899 /* 1900 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1901 * int busno, int devno, int function) 1902 * This is the function to make a tag to access config space of 1903 * a CardBus Card. It works same as pci_conf_read. 1904 */ 1905 static cardbustag_t 1906 pccbb_make_tag(cc, busno, devno, function) 1907 cardbus_chipset_tag_t cc; 1908 int busno, devno, function; 1909 { 1910 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1911 1912 return pci_make_tag(sc->sc_pc, busno, devno, function); 1913 } 1914 1915 static void 1916 pccbb_free_tag(cc, tag) 1917 cardbus_chipset_tag_t cc; 1918 cardbustag_t tag; 1919 { 1920 } 1921 1922 /* 1923 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1924 * cardbustag_t tag, int offset) 1925 * This is the function to read the config space of a CardBus Card. 1926 * It works same as pci_conf_read. 1927 */ 1928 static cardbusreg_t 1929 pccbb_conf_read(cc, tag, offset) 1930 cardbus_chipset_tag_t cc; 1931 cardbustag_t tag; 1932 int offset; /* register offset */ 1933 { 1934 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1935 1936 return pci_conf_read(sc->sc_pc, tag, offset); 1937 } 1938 1939 /* 1940 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1941 * int offs, cardbusreg_t val) 1942 * This is the function to write the config space of a CardBus Card. 1943 * It works same as pci_conf_write. 1944 */ 1945 static void 1946 pccbb_conf_write(cc, tag, reg, val) 1947 cardbus_chipset_tag_t cc; 1948 cardbustag_t tag; 1949 int reg; /* register offset */ 1950 cardbusreg_t val; 1951 { 1952 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1953 1954 pci_conf_write(sc->sc_pc, tag, reg, val); 1955 } 1956 1957 #if 0 1958 STATIC int 1959 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1960 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1961 int speed, int flags, 1962 bus_space_handle_t * iohp) 1963 #endif 1964 /* 1965 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1966 * bus_addr_t start, bus_size_t size, 1967 * bus_size_t align, 1968 * struct pcmcia_io_handle *pcihp 1969 * 1970 * This function only allocates I/O region for pccard. This function 1971 * never maps the allocated region to pccard I/O area. 1972 * 1973 * XXX: The interface of this function is not very good, I believe. 1974 */ 1975 STATIC int 1976 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1977 pcmcia_chipset_handle_t pch; 1978 bus_addr_t start; /* start address */ 1979 bus_size_t size; 1980 bus_size_t align; 1981 struct pcmcia_io_handle *pcihp; 1982 { 1983 struct pcic_handle *ph = (struct pcic_handle *)pch; 1984 bus_addr_t ioaddr; 1985 int flags = 0; 1986 bus_space_tag_t iot; 1987 bus_space_handle_t ioh; 1988 bus_addr_t mask; 1989 #if rbus 1990 rbus_tag_t rb; 1991 #endif 1992 if (align == 0) { 1993 align = size; /* XXX: funny??? */ 1994 } 1995 1996 if (start != 0) { 1997 /* XXX: assume all card decode lower 10 bits by its hardware */ 1998 mask = 0x3ff; 1999 } else { 2000 /* 2001 * calculate mask: 2002 * 1. get the most significant bit of size (call it msb). 2003 * 2. compare msb with the value of size. 2004 * 3. if size is larger, shift msb left once. 2005 * 4. obtain mask value to decrement msb. 2006 */ 2007 bus_size_t size_tmp = size; 2008 int shifts = 0; 2009 2010 mask = 1; 2011 while (size_tmp) { 2012 ++shifts; 2013 size_tmp >>= 1; 2014 } 2015 mask = (1 << shifts); 2016 if (mask < size) { 2017 mask <<= 1; 2018 } 2019 --mask; 2020 } 2021 2022 /* 2023 * Allocate some arbitrary I/O space. 2024 */ 2025 2026 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2027 2028 #if rbus 2029 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2030 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2031 return 1; 2032 } 2033 #else 2034 if (start) { 2035 ioaddr = start; 2036 if (bus_space_map(iot, start, size, 0, &ioh)) { 2037 return 1; 2038 } 2039 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2040 (u_long) ioaddr, (u_long) size)); 2041 } else { 2042 flags |= PCMCIA_IO_ALLOCATED; 2043 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2044 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2045 size, align, 0, 0, &ioaddr, &ioh)) { 2046 /* No room be able to be get. */ 2047 return 1; 2048 } 2049 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2050 (u_long) ioaddr, (u_long) size)); 2051 } 2052 #endif 2053 2054 pcihp->iot = iot; 2055 pcihp->ioh = ioh; 2056 pcihp->addr = ioaddr; 2057 pcihp->size = size; 2058 pcihp->flags = flags; 2059 2060 return 0; 2061 } 2062 2063 /* 2064 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2065 * struct pcmcia_io_handle *pcihp) 2066 * 2067 * This function only frees I/O region for pccard. 2068 * 2069 * XXX: The interface of this function is not very good, I believe. 2070 */ 2071 void 2072 pccbb_pcmcia_io_free(pch, pcihp) 2073 pcmcia_chipset_handle_t pch; 2074 struct pcmcia_io_handle *pcihp; 2075 { 2076 #if !rbus 2077 bus_space_tag_t iot = pcihp->iot; 2078 #endif 2079 bus_space_handle_t ioh = pcihp->ioh; 2080 bus_size_t size = pcihp->size; 2081 2082 #if rbus 2083 struct pccbb_softc *sc = 2084 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2085 rbus_tag_t rb = sc->sc_rbus_iot; 2086 2087 rbus_space_free(rb, ioh, size, NULL); 2088 #else 2089 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2090 bus_space_free(iot, ioh, size); 2091 else 2092 bus_space_unmap(iot, ioh, size); 2093 #endif 2094 } 2095 2096 /* 2097 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2098 * bus_addr_t offset, bus_size_t size, 2099 * struct pcmcia_io_handle *pcihp, 2100 * int *windowp) 2101 * 2102 * This function maps the allocated I/O region to pccard. This function 2103 * never allocates any I/O region for pccard I/O area. I don't 2104 * understand why the original authors of pcmciabus separated alloc and 2105 * map. I believe the two must be unite. 2106 * 2107 * XXX: no wait timing control? 2108 */ 2109 int 2110 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2111 pcmcia_chipset_handle_t pch; 2112 int width; 2113 bus_addr_t offset; 2114 bus_size_t size; 2115 struct pcmcia_io_handle *pcihp; 2116 int *windowp; 2117 { 2118 struct pcic_handle *ph = (struct pcic_handle *)pch; 2119 bus_addr_t ioaddr = pcihp->addr + offset; 2120 int i, win; 2121 #if defined CBB_DEBUG 2122 static char *width_names[] = { "dynamic", "io8", "io16" }; 2123 #endif 2124 2125 /* Sanity check I/O handle. */ 2126 2127 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2128 panic("pccbb_pcmcia_io_map iot is bogus"); 2129 } 2130 2131 /* XXX Sanity check offset/size. */ 2132 2133 win = -1; 2134 for (i = 0; i < PCIC_IO_WINS; i++) { 2135 if ((ph->ioalloc & (1 << i)) == 0) { 2136 win = i; 2137 ph->ioalloc |= (1 << i); 2138 break; 2139 } 2140 } 2141 2142 if (win == -1) { 2143 return 1; 2144 } 2145 2146 *windowp = win; 2147 2148 /* XXX this is pretty gross */ 2149 2150 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2151 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2152 2153 /* XXX wtf is this doing here? */ 2154 2155 #if 0 2156 printf(" port 0x%lx", (u_long) ioaddr); 2157 if (size > 1) { 2158 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2159 } 2160 #endif 2161 2162 ph->io[win].addr = ioaddr; 2163 ph->io[win].size = size; 2164 ph->io[win].width = width; 2165 2166 /* actual dirty register-value changing in the function below. */ 2167 pccbb_pcmcia_do_io_map(ph, win); 2168 2169 return 0; 2170 } 2171 2172 /* 2173 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2174 * 2175 * This function changes register-value to map I/O region for pccard. 2176 */ 2177 static void 2178 pccbb_pcmcia_do_io_map(ph, win) 2179 struct pcic_handle *ph; 2180 int win; 2181 { 2182 static u_int8_t pcic_iowidth[3] = { 2183 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2184 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2185 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2186 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2187 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2188 }; 2189 2190 #define PCIC_SIA_START_LOW 0 2191 #define PCIC_SIA_START_HIGH 1 2192 #define PCIC_SIA_STOP_LOW 2 2193 #define PCIC_SIA_STOP_HIGH 3 2194 2195 int regbase_win = 0x8 + win * 0x04; 2196 u_int8_t ioctl, enable; 2197 2198 DPRINTF( 2199 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2200 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2201 ph->io[win].width * 8)); 2202 2203 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2204 ph->io[win].addr & 0xff); 2205 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2206 (ph->io[win].addr >> 8) & 0xff); 2207 2208 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2209 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2210 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2211 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2212 2213 ioctl = Pcic_read(ph, PCIC_IOCTL); 2214 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2215 switch (win) { 2216 case 0: 2217 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2218 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2219 PCIC_IOCTL_IO0_DATASIZE_MASK); 2220 ioctl |= pcic_iowidth[ph->io[win].width]; 2221 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2222 break; 2223 case 1: 2224 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2225 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2226 PCIC_IOCTL_IO1_DATASIZE_MASK); 2227 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2228 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2229 break; 2230 } 2231 Pcic_write(ph, PCIC_IOCTL, ioctl); 2232 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2233 #if defined CBB_DEBUG 2234 { 2235 u_int8_t start_low = 2236 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2237 u_int8_t start_high = 2238 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2239 u_int8_t stop_low = 2240 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2241 u_int8_t stop_high = 2242 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2243 printf 2244 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2245 start_low, start_high, stop_low, stop_high, ioctl, enable); 2246 } 2247 #endif 2248 } 2249 2250 /* 2251 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2252 * 2253 * This function unmaps I/O region. No return value. 2254 */ 2255 STATIC void 2256 pccbb_pcmcia_io_unmap(pch, win) 2257 pcmcia_chipset_handle_t pch; 2258 int win; 2259 { 2260 struct pcic_handle *ph = (struct pcic_handle *)pch; 2261 int reg; 2262 2263 if (win >= PCIC_IO_WINS || win < 0) { 2264 panic("pccbb_pcmcia_io_unmap: window out of range"); 2265 } 2266 2267 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2268 switch (win) { 2269 case 0: 2270 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2271 break; 2272 case 1: 2273 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2274 break; 2275 } 2276 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2277 2278 ph->ioalloc &= ~(1 << win); 2279 } 2280 2281 /* 2282 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2283 * 2284 * This function enables the card. All information is stored in 2285 * the first argument, pcmcia_chipset_handle_t. 2286 */ 2287 static void 2288 pccbb_pcmcia_wait_ready(ph) 2289 struct pcic_handle *ph; 2290 { 2291 int i; 2292 2293 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2294 Pcic_read(ph, PCIC_IF_STATUS))); 2295 2296 for (i = 0; i < 2000; i++) { 2297 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2298 return; 2299 } 2300 DELAY_MS(2, ph->ph_parent); 2301 #ifdef CBB_DEBUG 2302 if ((i > 1000) && (i % 25 == 24)) 2303 printf("."); 2304 #endif 2305 } 2306 2307 #ifdef DIAGNOSTIC 2308 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2309 Pcic_read(ph, PCIC_IF_STATUS)); 2310 #endif 2311 } 2312 2313 /* 2314 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2315 * 2316 * This function enables the card. All information is stored in 2317 * the first argument, pcmcia_chipset_handle_t. 2318 */ 2319 STATIC void 2320 pccbb_pcmcia_socket_enable(pch) 2321 pcmcia_chipset_handle_t pch; 2322 { 2323 struct pcic_handle *ph = (struct pcic_handle *)pch; 2324 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2325 int cardtype, win; 2326 u_int8_t power, intr; 2327 pcireg_t spsr; 2328 int voltage; 2329 2330 /* this bit is mostly stolen from pcic_attach_card */ 2331 2332 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2333 2334 /* get card Vcc info */ 2335 2336 spsr = 2337 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2338 CB_SOCKET_STAT); 2339 if (spsr & CB_SOCKET_STAT_5VCARD) { 2340 DPRINTF(("5V card\n")); 2341 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2342 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2343 DPRINTF(("3V card\n")); 2344 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2345 } else { 2346 printf("?V card, 0x%x\n", spsr); /* XXX */ 2347 return; 2348 } 2349 2350 /* disable socket: negate output enable bit and power off */ 2351 2352 power = 0; 2353 Pcic_write(ph, PCIC_PWRCTL, power); 2354 2355 /* power down the socket to reset it, clear the card reset pin */ 2356 2357 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2358 2359 /* 2360 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2361 * we are changing Vcc (Toff). 2362 */ 2363 /* delay(300*1000); too much */ 2364 2365 /* assert reset bit */ 2366 intr = Pcic_read(ph, PCIC_INTR); 2367 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2368 Pcic_write(ph, PCIC_INTR, intr); 2369 2370 /* power up the socket and output enable */ 2371 power = Pcic_read(ph, PCIC_PWRCTL); 2372 power |= PCIC_PWRCTL_OE; 2373 Pcic_write(ph, PCIC_PWRCTL, power); 2374 pccbb_power(sc, voltage); 2375 2376 /* 2377 * hold RESET at least 20 ms: the spec says only 10 us is 2378 * enough, but TI1130 requires at least 20 ms. 2379 */ 2380 #if 0 /* XXX called on interrupt context */ 2381 DELAY_MS(20, sc); 2382 #else 2383 delay(20 * 1000); 2384 #endif 2385 2386 /* clear the reset flag */ 2387 2388 intr |= PCIC_INTR_RESET; 2389 Pcic_write(ph, PCIC_INTR, intr); 2390 2391 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2392 2393 #if 0 /* XXX called on interrupt context */ 2394 DELAY_MS(20, sc); 2395 #else 2396 delay(20 * 1000); 2397 #endif 2398 2399 /* wait for the chip to finish initializing */ 2400 2401 pccbb_pcmcia_wait_ready(ph); 2402 2403 /* zero out the address windows */ 2404 2405 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2406 2407 /* set the card type */ 2408 2409 cardtype = pcmcia_card_gettype(ph->pcmcia); 2410 2411 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2412 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2413 Pcic_write(ph, PCIC_INTR, intr); 2414 2415 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2416 ph->ph_parent->dv_xname, ph->sock, 2417 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2418 2419 /* reinstall all the memory and io mappings */ 2420 2421 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2422 if (ph->memalloc & (1 << win)) { 2423 pccbb_pcmcia_do_mem_map(ph, win); 2424 } 2425 } 2426 2427 for (win = 0; win < PCIC_IO_WINS; ++win) { 2428 if (ph->ioalloc & (1 << win)) { 2429 pccbb_pcmcia_do_io_map(ph, win); 2430 } 2431 } 2432 } 2433 2434 /* 2435 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2436 * 2437 * This function disables the card. All information is stored in 2438 * the first argument, pcmcia_chipset_handle_t. 2439 */ 2440 STATIC void 2441 pccbb_pcmcia_socket_disable(pch) 2442 pcmcia_chipset_handle_t pch; 2443 { 2444 struct pcic_handle *ph = (struct pcic_handle *)pch; 2445 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2446 u_int8_t power, intr; 2447 2448 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2449 2450 /* reset signal asserting... */ 2451 2452 intr = Pcic_read(ph, PCIC_INTR); 2453 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2454 Pcic_write(ph, PCIC_INTR, intr); 2455 delay(2 * 1000); 2456 2457 /* power down the socket */ 2458 power = Pcic_read(ph, PCIC_PWRCTL); 2459 power &= ~PCIC_PWRCTL_OE; 2460 Pcic_write(ph, PCIC_PWRCTL, power); 2461 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2462 /* 2463 * wait 300ms until power fails (Tpf). 2464 */ 2465 #if 0 /* XXX called on interrupt context */ 2466 DELAY_MS(300, sc); 2467 #else 2468 delay(300 * 1000); 2469 #endif 2470 } 2471 2472 /* 2473 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2474 * 2475 * This function detects whether a card is in the slot or not. 2476 * If a card is inserted, return 1. Otherwise, return 0. 2477 */ 2478 STATIC int 2479 pccbb_pcmcia_card_detect(pch) 2480 pcmcia_chipset_handle_t pch; 2481 { 2482 struct pcic_handle *ph = (struct pcic_handle *)pch; 2483 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2484 2485 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2486 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2487 } 2488 2489 #if 0 2490 STATIC int 2491 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2492 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2493 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2494 #endif 2495 /* 2496 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2497 * bus_size_t size, 2498 * struct pcmcia_mem_handle *pcmhp) 2499 * 2500 * This function only allocates memory region for pccard. This 2501 * function never maps the allocated region to pccard memory area. 2502 * 2503 * XXX: Why the argument of start address is not in? 2504 */ 2505 STATIC int 2506 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2507 pcmcia_chipset_handle_t pch; 2508 bus_size_t size; 2509 struct pcmcia_mem_handle *pcmhp; 2510 { 2511 struct pcic_handle *ph = (struct pcic_handle *)pch; 2512 bus_space_handle_t memh; 2513 bus_addr_t addr; 2514 bus_size_t sizepg; 2515 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2516 #if rbus 2517 rbus_tag_t rb; 2518 #endif 2519 2520 /* out of sc->memh, allocate as many pages as necessary */ 2521 2522 /* convert size to PCIC pages */ 2523 /* 2524 * This is not enough; when the requested region is on the page 2525 * boundaries, this may calculate wrong result. 2526 */ 2527 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2528 #if 0 2529 if (sizepg > PCIC_MAX_MEM_PAGES) { 2530 return 1; 2531 } 2532 #endif 2533 2534 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2535 return 1; 2536 } 2537 2538 addr = 0; /* XXX gcc -Wuninitialized */ 2539 2540 #if rbus 2541 rb = sc->sc_rbus_memt; 2542 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2543 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2544 &addr, &memh)) { 2545 return 1; 2546 } 2547 #else 2548 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2549 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2550 0, /* boundary */ 2551 0, /* flags */ 2552 &addr, &memh)) { 2553 return 1; 2554 } 2555 #endif 2556 2557 DPRINTF( 2558 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2559 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2560 2561 pcmhp->memt = sc->sc_memt; 2562 pcmhp->memh = memh; 2563 pcmhp->addr = addr; 2564 pcmhp->size = size; 2565 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2566 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2567 pcmhp->mhandle = 0; 2568 /* No offset??? Funny. */ 2569 2570 return 0; 2571 } 2572 2573 /* 2574 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2575 * struct pcmcia_mem_handle *pcmhp) 2576 * 2577 * This function release the memory space allocated by the function 2578 * pccbb_pcmcia_mem_alloc(). 2579 */ 2580 STATIC void 2581 pccbb_pcmcia_mem_free(pch, pcmhp) 2582 pcmcia_chipset_handle_t pch; 2583 struct pcmcia_mem_handle *pcmhp; 2584 { 2585 #if rbus 2586 struct pcic_handle *ph = (struct pcic_handle *)pch; 2587 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2588 2589 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2590 #else 2591 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2592 #endif 2593 } 2594 2595 /* 2596 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2597 * 2598 * This function release the memory space allocated by the function 2599 * pccbb_pcmcia_mem_alloc(). 2600 */ 2601 STATIC void 2602 pccbb_pcmcia_do_mem_map(ph, win) 2603 struct pcic_handle *ph; 2604 int win; 2605 { 2606 int regbase_win; 2607 bus_addr_t phys_addr; 2608 bus_addr_t phys_end; 2609 2610 #define PCIC_SMM_START_LOW 0 2611 #define PCIC_SMM_START_HIGH 1 2612 #define PCIC_SMM_STOP_LOW 2 2613 #define PCIC_SMM_STOP_HIGH 3 2614 #define PCIC_CMA_LOW 4 2615 #define PCIC_CMA_HIGH 5 2616 2617 u_int8_t start_low, start_high = 0; 2618 u_int8_t stop_low, stop_high; 2619 u_int8_t off_low, off_high; 2620 u_int8_t mem_window; 2621 int reg; 2622 2623 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2624 int mem8 = 2625 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2626 || (kind == PCMCIA_MEM_ATTR); 2627 2628 regbase_win = 0x10 + win * 0x08; 2629 2630 phys_addr = ph->mem[win].addr; 2631 phys_end = phys_addr + ph->mem[win].size; 2632 2633 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2634 phys_addr, phys_end, ph->mem[win].offset)); 2635 2636 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2637 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2638 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2639 2640 /* bit 19:12 */ 2641 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2642 /* bit 23:20 and bit 7 on */ 2643 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2644 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2645 /* bit 31:24, for 32-bit address */ 2646 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2647 2648 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2649 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2650 2651 if (((struct pccbb_softc *)ph-> 2652 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2653 Pcic_write(ph, 0x40 + win, mem_window); 2654 } 2655 2656 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2657 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2658 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2659 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2660 2661 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2662 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2663 2664 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2665 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2666 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2667 | ((kind == PCMCIA_MEM_ATTR) ? 2668 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2669 2670 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2671 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2672 2673 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2674 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2675 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2676 2677 #if defined CBB_DEBUG 2678 { 2679 int r1, r2, r3, r4, r5, r6, r7 = 0; 2680 2681 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2682 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2683 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2684 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2685 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2686 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2687 if (((struct pccbb_softc *)(ph-> 2688 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2689 r7 = Pcic_read(ph, 0x40 + win); 2690 } 2691 2692 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2693 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2694 if (((struct pccbb_softc *)(ph-> 2695 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2696 DPRINTF((" %02x", r7)); 2697 } 2698 DPRINTF(("\n")); 2699 } 2700 #endif 2701 } 2702 2703 /* 2704 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2705 * bus_addr_t card_addr, bus_size_t size, 2706 * struct pcmcia_mem_handle *pcmhp, 2707 * bus_addr_t *offsetp, int *windowp) 2708 * 2709 * This function maps memory space allocated by the function 2710 * pccbb_pcmcia_mem_alloc(). 2711 */ 2712 STATIC int 2713 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2714 pcmcia_chipset_handle_t pch; 2715 int kind; 2716 bus_addr_t card_addr; 2717 bus_size_t size; 2718 struct pcmcia_mem_handle *pcmhp; 2719 bus_addr_t *offsetp; 2720 int *windowp; 2721 { 2722 struct pcic_handle *ph = (struct pcic_handle *)pch; 2723 bus_addr_t busaddr; 2724 long card_offset; 2725 int win; 2726 2727 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2728 if ((ph->memalloc & (1 << win)) == 0) { 2729 ph->memalloc |= (1 << win); 2730 break; 2731 } 2732 } 2733 2734 if (win == PCIC_MEM_WINS) { 2735 return 1; 2736 } 2737 2738 *windowp = win; 2739 2740 /* XXX this is pretty gross */ 2741 2742 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2743 panic("pccbb_pcmcia_mem_map memt is bogus"); 2744 } 2745 2746 busaddr = pcmhp->addr; 2747 2748 /* 2749 * compute the address offset to the pcmcia address space for the 2750 * pcic. this is intentionally signed. The masks and shifts below 2751 * will cause TRT to happen in the pcic registers. Deal with making 2752 * sure the address is aligned, and return the alignment offset. 2753 */ 2754 2755 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2756 card_addr -= *offsetp; 2757 2758 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2759 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2760 (u_long) card_addr)); 2761 2762 /* 2763 * include the offset in the size, and decrement size by one, since 2764 * the hw wants start/stop 2765 */ 2766 size += *offsetp - 1; 2767 2768 card_offset = (((long)card_addr) - ((long)busaddr)); 2769 2770 ph->mem[win].addr = busaddr; 2771 ph->mem[win].size = size; 2772 ph->mem[win].offset = card_offset; 2773 ph->mem[win].kind = kind; 2774 2775 pccbb_pcmcia_do_mem_map(ph, win); 2776 2777 return 0; 2778 } 2779 2780 /* 2781 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2782 * int window) 2783 * 2784 * This function unmaps memory space which mapped by the function 2785 * pccbb_pcmcia_mem_map(). 2786 */ 2787 STATIC void 2788 pccbb_pcmcia_mem_unmap(pch, window) 2789 pcmcia_chipset_handle_t pch; 2790 int window; 2791 { 2792 struct pcic_handle *ph = (struct pcic_handle *)pch; 2793 int reg; 2794 2795 if (window >= PCIC_MEM_WINS) { 2796 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2797 } 2798 2799 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2800 reg &= ~(1 << window); 2801 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2802 2803 ph->memalloc &= ~(1 << window); 2804 } 2805 2806 #if defined PCCBB_PCMCIA_POLL 2807 struct pccbb_poll_str { 2808 void *arg; 2809 int (*func) __P((void *)); 2810 int level; 2811 struct pcic_handle *ph; 2812 int count; 2813 int num; 2814 struct callout poll_ch; 2815 }; 2816 2817 static struct pccbb_poll_str pccbb_poll[10]; 2818 static int pccbb_poll_n = 0; 2819 2820 static void pccbb_pcmcia_poll __P((void *arg)); 2821 2822 static void 2823 pccbb_pcmcia_poll(arg) 2824 void *arg; 2825 { 2826 struct pccbb_poll_str *poll = arg; 2827 struct pcic_handle *ph = poll->ph; 2828 struct pccbb_softc *sc = ph->sc; 2829 int s; 2830 u_int32_t spsr; /* socket present-state reg */ 2831 2832 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2833 switch (poll->level) { 2834 case IPL_NET: 2835 s = splnet(); 2836 break; 2837 case IPL_BIO: 2838 s = splbio(); 2839 break; 2840 case IPL_TTY: /* fallthrough */ 2841 default: 2842 s = spltty(); 2843 break; 2844 } 2845 2846 spsr = 2847 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2848 CB_SOCKET_STAT); 2849 2850 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2851 if (!(spsr & 0x40)) /* CINT low */ 2852 #else 2853 if (1) 2854 #endif 2855 { 2856 if ((*poll->func) (poll->arg) > 0) { 2857 ++poll->count; 2858 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2859 #if defined LEVEL2 2860 } else { 2861 printf("intr: miss! 0x%x\n", spsr); 2862 #endif 2863 } 2864 } 2865 splx(s); 2866 } 2867 #endif /* defined CB_PCMCIA_POLL */ 2868 2869 /* 2870 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2871 * struct pcmcia_function *pf, 2872 * int ipl, 2873 * int (*func)(void *), 2874 * void *arg); 2875 * 2876 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2877 */ 2878 STATIC void * 2879 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2880 pcmcia_chipset_handle_t pch; 2881 struct pcmcia_function *pf; 2882 int ipl; 2883 int (*func) __P((void *)); 2884 void *arg; 2885 { 2886 struct pcic_handle *ph = (struct pcic_handle *)pch; 2887 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2888 2889 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2890 /* what should I do? */ 2891 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2892 DPRINTF( 2893 ("%s does not provide edge nor pulse interrupt\n", 2894 sc->sc_dev.dv_xname)); 2895 return NULL; 2896 } 2897 /* 2898 * XXX Noooooo! The interrupt flag must set properly!! 2899 * dumb pcmcia driver!! 2900 */ 2901 } 2902 2903 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2904 } 2905 2906 /* 2907 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2908 * void *ih) 2909 * 2910 * This function disables PC-Card interrupt. 2911 */ 2912 STATIC void 2913 pccbb_pcmcia_intr_disestablish(pch, ih) 2914 pcmcia_chipset_handle_t pch; 2915 void *ih; 2916 { 2917 struct pcic_handle *ph = (struct pcic_handle *)pch; 2918 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2919 2920 pccbb_intr_disestablish(sc, ih); 2921 } 2922 2923 #if rbus 2924 /* 2925 * static int 2926 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2927 * bus_addr_t addr, bus_size_t size, 2928 * bus_addr_t mask, bus_size_t align, 2929 * int flags, bus_addr_t *addrp; 2930 * bus_space_handle_t *bshp) 2931 * 2932 * This function allocates a portion of memory or io space for 2933 * clients. This function is called from CardBus card drivers. 2934 */ 2935 static int 2936 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2937 cardbus_chipset_tag_t ct; 2938 rbus_tag_t rb; 2939 bus_addr_t addr; 2940 bus_size_t size; 2941 bus_addr_t mask; 2942 bus_size_t align; 2943 int flags; 2944 bus_addr_t *addrp; 2945 bus_space_handle_t *bshp; 2946 { 2947 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2948 2949 DPRINTF( 2950 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2951 addr, size, mask, align)); 2952 2953 if (align == 0) { 2954 align = size; 2955 } 2956 2957 if (rb->rb_bt == sc->sc_memt) { 2958 if (align < 16) { 2959 return 1; 2960 } 2961 if (align < 0x1000) { 2962 align = 0x1000; 2963 } 2964 } else if (rb->rb_bt == sc->sc_iot) { 2965 if (align < 4) { 2966 return 1; 2967 } 2968 /* XXX: hack for avoiding ISA image */ 2969 if (mask < 0x0100) { 2970 mask = 0x3ff; 2971 addr = 0x300; 2972 } 2973 2974 } else { 2975 DPRINTF( 2976 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 2977 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 2978 return 1; 2979 /* XXX: panic here? */ 2980 } 2981 2982 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2983 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2984 return 1; 2985 } 2986 2987 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2988 2989 return 0; 2990 } 2991 2992 /* 2993 * static int 2994 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2995 * bus_space_handle_t *bshp, bus_size_t size); 2996 * 2997 * This function is called from CardBus card drivers. 2998 */ 2999 static int 3000 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3001 cardbus_chipset_tag_t ct; 3002 rbus_tag_t rb; 3003 bus_space_handle_t bsh; 3004 bus_size_t size; 3005 { 3006 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3007 bus_space_tag_t bt = rb->rb_bt; 3008 3009 pccbb_close_win(sc, bt, bsh, size); 3010 3011 if (bt == sc->sc_memt) { 3012 } else if (bt == sc->sc_iot) { 3013 } else { 3014 return 1; 3015 /* XXX: panic here? */ 3016 } 3017 3018 return rbus_space_free(rb, bsh, size, NULL); 3019 } 3020 #endif /* rbus */ 3021 3022 #if rbus 3023 3024 static int 3025 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3026 struct pccbb_softc *sc; 3027 bus_space_tag_t bst; 3028 bus_addr_t addr; 3029 bus_size_t size; 3030 bus_space_handle_t bsh; 3031 int flags; 3032 { 3033 struct pccbb_win_chain_head *head; 3034 bus_addr_t align; 3035 3036 head = &sc->sc_iowindow; 3037 align = 0x04; 3038 if (sc->sc_memt == bst) { 3039 head = &sc->sc_memwindow; 3040 align = 0x1000; 3041 DPRINTF(("using memory window, %x %x %x\n\n", 3042 sc->sc_iot, sc->sc_memt, bst)); 3043 } 3044 3045 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3046 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3047 sc->sc_dev.dv_xname, 3048 (head == &sc->sc_memwindow) ? "mem" : "io"); 3049 } 3050 pccbb_winset(align, sc, bst); 3051 3052 return 0; 3053 } 3054 3055 static int 3056 pccbb_close_win(sc, bst, bsh, size) 3057 struct pccbb_softc *sc; 3058 bus_space_tag_t bst; 3059 bus_space_handle_t bsh; 3060 bus_size_t size; 3061 { 3062 struct pccbb_win_chain_head *head; 3063 bus_addr_t align; 3064 3065 head = &sc->sc_iowindow; 3066 align = 0x04; 3067 if (sc->sc_memt == bst) { 3068 head = &sc->sc_memwindow; 3069 align = 0x1000; 3070 } 3071 3072 if (pccbb_winlist_delete(head, bsh, size)) { 3073 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3074 sc->sc_dev.dv_xname, 3075 (head == &sc->sc_memwindow) ? "mem" : "io"); 3076 } 3077 pccbb_winset(align, sc, bst); 3078 3079 return 0; 3080 } 3081 3082 static int 3083 pccbb_winlist_insert(head, start, size, bsh, flags) 3084 struct pccbb_win_chain_head *head; 3085 bus_addr_t start; 3086 bus_size_t size; 3087 bus_space_handle_t bsh; 3088 int flags; 3089 { 3090 struct pccbb_win_chain *chainp, *elem; 3091 3092 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3093 M_NOWAIT)) == NULL) 3094 return (1); /* fail */ 3095 3096 elem->wc_start = start; 3097 elem->wc_end = start + (size - 1); 3098 elem->wc_handle = bsh; 3099 elem->wc_flags = flags; 3100 3101 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3102 chainp = TAILQ_NEXT(chainp, wc_list)) { 3103 if (chainp->wc_end < start) 3104 continue; 3105 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3106 return (0); 3107 } 3108 3109 TAILQ_INSERT_TAIL(head, elem, wc_list); 3110 return (0); 3111 } 3112 3113 static int 3114 pccbb_winlist_delete(head, bsh, size) 3115 struct pccbb_win_chain_head *head; 3116 bus_space_handle_t bsh; 3117 bus_size_t size; 3118 { 3119 struct pccbb_win_chain *chainp; 3120 3121 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3122 chainp = TAILQ_NEXT(chainp, wc_list)) { 3123 if (chainp->wc_handle != bsh) 3124 continue; 3125 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3126 printf("pccbb_winlist_delete: window 0x%lx size " 3127 "inconsistent: 0x%lx, 0x%lx\n", 3128 (unsigned long)chainp->wc_start, 3129 (unsigned long)(chainp->wc_end - chainp->wc_start), 3130 (unsigned long)(size - 1)); 3131 return 1; 3132 } 3133 3134 TAILQ_REMOVE(head, chainp, wc_list); 3135 free(chainp, M_DEVBUF); 3136 3137 return 0; 3138 } 3139 3140 return 1; /* fail: no candidate to remove */ 3141 } 3142 3143 static void 3144 pccbb_winset(align, sc, bst) 3145 bus_addr_t align; 3146 struct pccbb_softc *sc; 3147 bus_space_tag_t bst; 3148 { 3149 pci_chipset_tag_t pc; 3150 pcitag_t tag; 3151 bus_addr_t mask = ~(align - 1); 3152 struct { 3153 cardbusreg_t win_start; 3154 cardbusreg_t win_limit; 3155 int win_flags; 3156 } win[2]; 3157 struct pccbb_win_chain *chainp; 3158 int offs; 3159 3160 win[0].win_start = win[1].win_start = 0xffffffff; 3161 win[0].win_limit = win[1].win_limit = 0; 3162 win[0].win_flags = win[1].win_flags = 0; 3163 3164 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3165 offs = 0x2c; 3166 if (sc->sc_memt == bst) { 3167 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3168 offs = 0x1c; 3169 } 3170 3171 if (chainp != NULL) { 3172 win[0].win_start = chainp->wc_start & mask; 3173 win[0].win_limit = chainp->wc_end & mask; 3174 win[0].win_flags = chainp->wc_flags; 3175 chainp = TAILQ_NEXT(chainp, wc_list); 3176 } 3177 3178 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3179 if (win[1].win_start == 0xffffffff) { 3180 /* window 1 is not used */ 3181 if ((win[0].win_flags == chainp->wc_flags) && 3182 (win[0].win_limit + align >= 3183 (chainp->wc_start & mask))) { 3184 /* concatenate */ 3185 win[0].win_limit = chainp->wc_end & mask; 3186 } else { 3187 /* make new window */ 3188 win[1].win_start = chainp->wc_start & mask; 3189 win[1].win_limit = chainp->wc_end & mask; 3190 win[1].win_flags = chainp->wc_flags; 3191 } 3192 continue; 3193 } 3194 3195 /* Both windows are engaged. */ 3196 if (win[0].win_flags == win[1].win_flags) { 3197 /* same flags */ 3198 if (win[0].win_flags == chainp->wc_flags) { 3199 if (win[1].win_start - (win[0].win_limit + 3200 align) < 3201 (chainp->wc_start & mask) - 3202 ((chainp->wc_end & mask) + align)) { 3203 /* 3204 * merge window 0 and 1, and set win1 3205 * to chainp 3206 */ 3207 win[0].win_limit = win[1].win_limit; 3208 win[1].win_start = 3209 chainp->wc_start & mask; 3210 win[1].win_limit = 3211 chainp->wc_end & mask; 3212 } else { 3213 win[1].win_limit = 3214 chainp->wc_end & mask; 3215 } 3216 } else { 3217 /* different flags */ 3218 3219 /* concatenate win0 and win1 */ 3220 win[0].win_limit = win[1].win_limit; 3221 /* allocate win[1] to new space */ 3222 win[1].win_start = chainp->wc_start & mask; 3223 win[1].win_limit = chainp->wc_end & mask; 3224 win[1].win_flags = chainp->wc_flags; 3225 } 3226 } else { 3227 /* the flags of win[0] and win[1] is different */ 3228 if (win[0].win_flags == chainp->wc_flags) { 3229 win[0].win_limit = chainp->wc_end & mask; 3230 /* 3231 * XXX this creates overlapping windows, so 3232 * what should the poor bridge do if one is 3233 * cachable, and the other is not? 3234 */ 3235 printf("%s: overlapping windows\n", 3236 sc->sc_dev.dv_xname); 3237 } else { 3238 win[1].win_limit = chainp->wc_end & mask; 3239 } 3240 } 3241 } 3242 3243 pc = sc->sc_pc; 3244 tag = sc->sc_tag; 3245 pci_conf_write(pc, tag, offs, win[0].win_start); 3246 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3247 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3248 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3249 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3250 pci_conf_read(pc, tag, offs), 3251 pci_conf_read(pc, tag, offs + 4) + align, 3252 pci_conf_read(pc, tag, offs + 8), 3253 pci_conf_read(pc, tag, offs + 12) + align)); 3254 3255 if (bst == sc->sc_memt) { 3256 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3257 3258 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3259 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3260 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3261 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3262 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3263 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3264 } 3265 } 3266 3267 #endif /* rbus */ 3268 3269 static void 3270 pccbb_powerhook(why, arg) 3271 int why; 3272 void *arg; 3273 { 3274 struct pccbb_softc *sc = arg; 3275 pcireg_t reg; 3276 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3277 bus_space_handle_t base_memh = sc->sc_base_memh; 3278 3279 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3280 3281 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3282 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3283 if (sc->sc_pil_intr_enable) { 3284 (void)pccbbintr_function(sc); 3285 } 3286 sc->sc_pil_intr_enable = 0; 3287 3288 /* ToDo: deactivate or suspend child devices */ 3289 3290 } 3291 3292 if (why == PWR_RESUME) { 3293 if (sc->sc_pwrmgt_offs != 0) { 3294 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3295 sc->sc_pwrmgt_offs + 4); 3296 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3297 reg & 0x100) { 3298 /* powrstate != D0 */ 3299 3300 printf("%s going back to D0 mode\n", 3301 sc->sc_dev.dv_xname); 3302 reg &= ~PCI_PMCSR_STATE_MASK; 3303 reg |= PCI_PMCSR_STATE_D0; 3304 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3305 pci_conf_write(sc->sc_pc, sc->sc_tag, 3306 sc->sc_pwrmgt_offs + 4, reg); 3307 3308 pci_conf_write(sc->sc_pc, sc->sc_tag, 3309 PCI_SOCKBASE, sc->sc_sockbase); 3310 pci_conf_write(sc->sc_pc, sc->sc_tag, 3311 PCI_BUSNUM, sc->sc_busnum); 3312 pccbb_chipinit(sc); 3313 /* setup memory and io space window for CB */ 3314 pccbb_winset(0x1000, sc, sc->sc_memt); 3315 pccbb_winset(0x04, sc, sc->sc_iot); 3316 } 3317 } 3318 3319 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3320 /* BIOS did not recover this register */ 3321 pci_conf_write (sc->sc_pc, sc->sc_tag, 3322 PCI_SOCKBASE, sc->sc_sockbase); 3323 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3324 /* BIOS did not recover this register */ 3325 pci_conf_write (sc->sc_pc, sc->sc_tag, 3326 PCI_BUSNUM, sc->sc_busnum); 3327 /* CSC Interrupt: Card detect interrupt on */ 3328 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3329 /* Card detect intr is turned on. */ 3330 reg |= CB_SOCKET_MASK_CD; 3331 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3332 /* reset interrupt */ 3333 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3334 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3335 3336 /* 3337 * check for card insertion or removal during suspend period. 3338 * XXX: the code can't cope with card swap (remove then 3339 * insert). how can we detect such situation? 3340 */ 3341 (void)pccbbintr(sc); 3342 3343 sc->sc_pil_intr_enable = 1; 3344 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3345 3346 /* ToDo: activate or wakeup child devices */ 3347 } 3348 } 3349
Indexes created Thu Sep 25 16:09:42 GMT 2025