pccbb.c revision 1.75
1 /* $NetBSD: pccbb.c,v 1.75 2002/03/05 11:56:33 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.75 2002/03/05 11:56:33 haya Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 struct cfattach cbb_pci_ca = { 230 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 231 }; 232 233 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 234 pccbb_pcmcia_mem_alloc, 235 pccbb_pcmcia_mem_free, 236 pccbb_pcmcia_mem_map, 237 pccbb_pcmcia_mem_unmap, 238 pccbb_pcmcia_io_alloc, 239 pccbb_pcmcia_io_free, 240 pccbb_pcmcia_io_map, 241 pccbb_pcmcia_io_unmap, 242 pccbb_pcmcia_intr_establish, 243 pccbb_pcmcia_intr_disestablish, 244 pccbb_pcmcia_socket_enable, 245 pccbb_pcmcia_socket_disable, 246 pccbb_pcmcia_card_detect 247 }; 248 249 #if rbus 250 static struct cardbus_functions pccbb_funcs = { 251 pccbb_rbus_cb_space_alloc, 252 pccbb_rbus_cb_space_free, 253 pccbb_cb_intr_establish, 254 pccbb_cb_intr_disestablish, 255 pccbb_ctrl, 256 pccbb_power, 257 pccbb_make_tag, 258 pccbb_free_tag, 259 pccbb_conf_read, 260 pccbb_conf_write, 261 }; 262 #else 263 static struct cardbus_functions pccbb_funcs = { 264 pccbb_ctrl, 265 pccbb_power, 266 pccbb_mem_open, 267 pccbb_mem_close, 268 pccbb_io_open, 269 pccbb_io_close, 270 pccbb_cb_intr_establish, 271 pccbb_cb_intr_disestablish, 272 pccbb_make_tag, 273 pccbb_conf_read, 274 pccbb_conf_write, 275 }; 276 #endif 277 278 int 279 pcicbbmatch(parent, match, aux) 280 struct device *parent; 281 struct cfdata *match; 282 void *aux; 283 { 284 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 285 286 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 287 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 288 PCI_INTERFACE(pa->pa_class) == 0) { 289 return 1; 290 } 291 292 return 0; 293 } 294 295 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 296 | ((prod) << PCI_PRODUCT_SHIFT)) 297 298 const struct yenta_chipinfo { 299 pcireg_t yc_id; /* vendor tag | product tag */ 300 int yc_chiptype; 301 int yc_flags; 302 } yc_chipsets[] = { 303 /* Texas Instruments chips */ 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 331 /* Ricoh chips */ 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 345 /* Toshiba products */ 346 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 347 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 349 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 351 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 355 /* Cirrus Logic products */ 356 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 357 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 361 /* sentinel, or Generic chip */ 362 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 363 }; 364 365 static int 366 cb_chipset(pci_id, flagp) 367 u_int32_t pci_id; 368 int *flagp; 369 { 370 const struct yenta_chipinfo *yc; 371 372 /* Loop over except the last default entry. */ 373 for (yc = yc_chipsets; yc < yc_chipsets + 374 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 375 if (pci_id == yc->yc_id) 376 break; 377 378 if (flagp != NULL) 379 *flagp = yc->yc_flags; 380 381 return (yc->yc_chiptype); 382 } 383 384 static void 385 pccbb_shutdown(void *arg) 386 { 387 struct pccbb_softc *sc = arg; 388 pcireg_t command; 389 390 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 391 392 /* 393 * turn off power 394 * 395 * XXX - do not turn off power if chipset is TI 113X because 396 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 397 */ 398 if (sc->sc_chipset != CB_TI113X) { 399 pccbb_power((cardbus_chipset_tag_t)sc, 400 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 401 } 402 403 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 404 0); 405 406 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 407 408 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 409 PCI_COMMAND_MASTER_ENABLE); 410 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 411 412 } 413 414 void 415 pccbbattach(parent, self, aux) 416 struct device *parent; 417 struct device *self; 418 void *aux; 419 { 420 struct pccbb_softc *sc = (void *)self; 421 struct pci_attach_args *pa = aux; 422 pci_chipset_tag_t pc = pa->pa_pc; 423 pcireg_t busreg, reg, sock_base; 424 bus_addr_t sockbase; 425 char devinfo[256]; 426 int flags; 427 int pwrmgt_offs; 428 429 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 430 431 pci_devinfo(pa->pa_id, 0, 0, devinfo); 432 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 433 #ifdef CBB_DEBUG 434 printf(" (chipflags %x)", flags); 435 #endif 436 printf("\n"); 437 438 TAILQ_INIT(&sc->sc_memwindow); 439 TAILQ_INIT(&sc->sc_iowindow); 440 441 #if rbus 442 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 443 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 444 445 #if 0 446 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 447 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 448 #endif 449 #endif /* rbus */ 450 451 sc->sc_base_memh = 0; 452 453 /* power management: set D0 state */ 454 sc->sc_pwrmgt_offs = 0; 455 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 456 &pwrmgt_offs, 0)) { 457 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + 4); 458 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 459 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 460 reg &= ~PCI_PMCSR_STATE_MASK; 461 reg |= PCI_PMCSR_STATE_D0; 462 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 463 pci_conf_write(pc, pa->pa_tag, pwrmgt_offs + 4, reg); 464 } 465 466 sc->sc_pwrmgt_offs = pwrmgt_offs; 467 } 468 469 /* 470 * MAP socket registers and ExCA registers on memory-space 471 * When no valid address is set on socket base registers (on pci 472 * config space), get it not polite way. 473 */ 474 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 475 476 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 477 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 478 /* The address must be valid. */ 479 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 480 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 481 printf("%s: can't map socket base address 0x%x\n", 482 sc->sc_dev.dv_xname, sock_base); 483 /* 484 * I think it's funny: socket base registers must be 485 * mapped on memory space, but ... 486 */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 488 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 489 NULL)) { 490 printf("%s: can't map socket base address" 491 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 492 (unsigned long)sockbase); 493 /* give up... allocate reg space via rbus. */ 494 sc->sc_base_memh = 0; 495 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 496 } 497 } else { 498 DPRINTF(("%s: socket base address 0x%lx\n", 499 sc->sc_dev.dv_xname, sockbase)); 500 } 501 } 502 503 sc->sc_mem_start = 0; /* XXX */ 504 sc->sc_mem_end = 0xffffffff; /* XXX */ 505 506 /* 507 * When interrupt isn't routed correctly, give up probing cbb and do 508 * not kill pcic-compatible port. 509 */ 510 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 511 printf("%s: NOT USED because of unconfigured interrupt\n", 512 sc->sc_dev.dv_xname); 513 return; 514 } 515 516 /* 517 * When bus number isn't set correctly, give up using 32-bit CardBus 518 * mode. 519 */ 520 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 521 #if notyet 522 if (((busreg >> 8) & 0xff) == 0) { 523 printf("%s: CardBus support disabled because of unconfigured bus number\n", 524 sc->sc_dev.dv_xname); 525 flags |= PCCBB_PCMCIA_16BITONLY; 526 } 527 #endif 528 529 /* pccbb_machdep.c end */ 530 531 #if defined CBB_DEBUG 532 { 533 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 534 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 535 intrname[pa->pa_intrpin], pa->pa_intrline); 536 } 537 #endif 538 539 /* setup softc */ 540 sc->sc_pc = pc; 541 sc->sc_iot = pa->pa_iot; 542 sc->sc_memt = pa->pa_memt; 543 sc->sc_dmat = pa->pa_dmat; 544 sc->sc_tag = pa->pa_tag; 545 sc->sc_function = pa->pa_function; 546 sc->sc_sockbase = sock_base; 547 sc->sc_busnum = busreg; 548 549 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 550 551 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 552 553 shutdownhook_establish(pccbb_shutdown, sc); 554 555 /* Disable legacy register mapping. */ 556 switch (sc->sc_chipset) { 557 case CB_RX5C46X: /* fallthrough */ 558 #if 0 559 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 560 case CB_RX5C47X: 561 #endif 562 /* 563 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 564 * cannot be disabled by substituting 0 into PCI_LEGACY 565 * register. Ricoh CardBus bridges have special bits on Bridge 566 * control reg (addr 0x3e on PCI config space). 567 */ 568 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 569 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 570 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 571 break; 572 573 default: 574 /* XXX I don't know proper way to kill legacy I/O. */ 575 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 576 break; 577 } 578 579 config_defer(self, pccbb_pci_callback); 580 } 581 582 583 584 585 /* 586 * static void pccbb_pci_callback(struct device *self) 587 * 588 * The actual attach routine: get memory space for YENTA register 589 * space, setup YENTA register and route interrupt. 590 * 591 * This function should be deferred because this device may obtain 592 * memory space dynamically. This function must avoid obtaining 593 * memory area which has already kept for another device. 594 */ 595 static void 596 pccbb_pci_callback(self) 597 struct device *self; 598 { 599 struct pccbb_softc *sc = (void *)self; 600 pci_chipset_tag_t pc = sc->sc_pc; 601 pci_intr_handle_t ih; 602 const char *intrstr = NULL; 603 bus_addr_t sockbase; 604 struct cbslot_attach_args cba; 605 struct pcmciabus_attach_args paa; 606 struct cardslot_attach_args caa; 607 struct cardslot_softc *csc; 608 609 if (0 == sc->sc_base_memh) { 610 /* The socket registers aren't mapped correctly. */ 611 #if rbus 612 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 613 (sc->sc_chipset == CB_RX5C47X 614 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 615 0, &sockbase, &sc->sc_base_memh)) { 616 return; 617 } 618 sc->sc_base_memt = sc->sc_memt; 619 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 620 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 621 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 622 PCI_SOCKBASE))); 623 #else 624 sc->sc_base_memt = sc->sc_memt; 625 #if !defined CBB_PCI_BASE 626 #define CBB_PCI_BASE 0x20000000 627 #endif 628 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 629 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 630 /* cannot allocate memory space */ 631 return; 632 } 633 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 634 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 635 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 636 sc->sc_tag, PCI_SOCKBASE))); 637 sc->sc_sockbase = sockbase; 638 #endif 639 } 640 641 /* bus bridge initialization */ 642 pccbb_chipinit(sc); 643 644 /* clear data structure for child device interrupt handlers */ 645 sc->sc_pil = NULL; 646 sc->sc_pil_intr_enable = 1; 647 648 /* Map and establish the interrupt. */ 649 if (pci_intr_map(&sc->sc_pa, &ih)) { 650 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 651 return; 652 } 653 intrstr = pci_intr_string(pc, ih); 654 655 /* 656 * XXX pccbbintr should be called under the priority lower 657 * than any other hard interrputs. 658 */ 659 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 660 661 if (sc->sc_ih == NULL) { 662 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 663 if (intrstr != NULL) { 664 printf(" at %s", intrstr); 665 } 666 printf("\n"); 667 return; 668 } 669 670 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 671 powerhook_establish(pccbb_powerhook, sc); 672 673 { 674 u_int32_t sockstat; 675 676 sockstat = bus_space_read_4(sc->sc_base_memt, 677 sc->sc_base_memh, CB_SOCKET_STAT); 678 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 679 sc->sc_flags |= CBB_CARDEXIST; 680 } 681 } 682 683 /* 684 * attach cardbus 685 */ 686 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 687 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 688 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 689 690 /* initialize cbslot_attach */ 691 cba.cba_busname = "cardbus"; 692 cba.cba_iot = sc->sc_iot; 693 cba.cba_memt = sc->sc_memt; 694 cba.cba_dmat = sc->sc_dmat; 695 cba.cba_bus = (busreg >> 8) & 0x0ff; 696 cba.cba_cc = (void *)sc; 697 cba.cba_cf = &pccbb_funcs; 698 cba.cba_intrline = sc->sc_pa.pa_intrline; 699 700 #if rbus 701 cba.cba_rbus_iot = sc->sc_rbus_iot; 702 cba.cba_rbus_memt = sc->sc_rbus_memt; 703 #endif 704 705 cba.cba_cacheline = PCI_CACHELINE(bhlc); 706 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 707 708 if (bootverbose) { 709 printf("%s: cacheline 0x%x lattimer 0x%x\n", 710 sc->sc_dev.dv_xname, cba.cba_cacheline, 711 cba.cba_lattimer); 712 printf("%s: bhlc 0x%x lscp 0x%x\n", 713 sc->sc_dev.dv_xname, bhlc, busreg); 714 } 715 #if defined SHOW_REGS 716 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 717 sc->sc_base_memh); 718 #endif 719 } 720 721 pccbb_pcmcia_attach_setup(sc, &paa); 722 caa.caa_cb_attach = NULL; 723 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 724 caa.caa_cb_attach = &cba; 725 } 726 caa.caa_16_attach = &paa; 727 caa.caa_ph = &sc->sc_pcmcia_h; 728 729 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 730 DPRINTF(("pccbbattach: found cardslot\n")); 731 sc->sc_csc = csc; 732 } 733 734 return; 735 } 736 737 738 739 740 741 /* 742 * static void pccbb_chipinit(struct pccbb_softc *sc) 743 * 744 * This function initialize YENTA chip registers listed below: 745 * 1) PCI command reg, 746 * 2) PCI and CardBus latency timer, 747 * 3) route PCI interrupt, 748 * 4) close all memory and io windows. 749 * 5) turn off bus power. 750 * 6) card detect interrupt on. 751 * 7) clear interrupt 752 */ 753 static void 754 pccbb_chipinit(sc) 755 struct pccbb_softc *sc; 756 { 757 pci_chipset_tag_t pc = sc->sc_pc; 758 pcitag_t tag = sc->sc_tag; 759 bus_space_tag_t bmt = sc->sc_base_memt; 760 bus_space_handle_t bmh = sc->sc_base_memh; 761 pcireg_t reg; 762 763 /* 764 * Set PCI command reg. 765 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 766 */ 767 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 768 /* I believe it is harmless. */ 769 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 770 PCI_COMMAND_MASTER_ENABLE); 771 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 772 773 /* 774 * Set CardBus latency timer. 775 */ 776 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 777 if (PCI_CB_LATENCY(reg) < 0x20) { 778 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 779 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 780 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 781 } 782 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 783 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 784 785 /* 786 * Set PCI latency timer. 787 */ 788 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 789 if (PCI_LATTIMER(reg) < 0x10) { 790 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 791 reg |= (0x10 << PCI_LATTIMER_SHIFT); 792 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 793 } 794 DPRINTF(("PCI latency timer 0x%x (%x)\n", 795 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 796 797 798 /* Route functional interrupts to PCI. */ 799 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 800 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 801 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 802 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 803 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 804 805 switch (sc->sc_chipset) { 806 case CB_TI113X: 807 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 808 /* This bit is shared, but may read as 0 on some chips, so set 809 it explicitly on both functions. */ 810 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 811 /* CSC intr enable */ 812 reg |= PCI113X_CBCTRL_PCI_CSC; 813 /* functional intr prohibit | prohibit ISA routing */ 814 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 815 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 816 break; 817 818 case CB_TI12XX: 819 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 820 reg |= PCI12XX_SYSCTRL_VCCPROT; 821 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 822 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 823 reg |= PCI12XX_CBCTRL_CSC; 824 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 825 break; 826 827 case CB_TOPIC95B: 828 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 829 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 830 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 831 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 832 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 833 sc->sc_dev.dv_xname, reg)); 834 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 835 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 836 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 837 DPRINTF(("0x%x\n", reg)); 838 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 839 break; 840 841 case CB_TOPIC97: 842 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 843 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 844 sc->sc_dev.dv_xname, reg)); 845 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 846 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 847 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 848 reg |= TOPIC97_SLOT_CTRL_PCIINT; 849 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 850 DPRINTF(("0x%x\n", reg)); 851 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 852 /* make sure to assert LV card support bits */ 853 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 854 0x800 + 0x3e, 855 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 856 0x800 + 0x3e) | 0x03); 857 break; 858 } 859 860 /* Close all memory and I/O windows. */ 861 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 862 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 863 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 864 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 865 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 866 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 867 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 868 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 869 870 /* reset 16-bit pcmcia bus */ 871 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 872 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 873 874 /* turn off power */ 875 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 876 877 /* CSC Interrupt: Card detect interrupt on */ 878 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 879 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 880 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 881 /* reset interrupt */ 882 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 883 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 884 } 885 886 887 888 889 /* 890 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 891 * struct pcmciabus_attach_args *paa) 892 * 893 * This function attaches 16-bit PCcard bus. 894 */ 895 STATIC void 896 pccbb_pcmcia_attach_setup(sc, paa) 897 struct pccbb_softc *sc; 898 struct pcmciabus_attach_args *paa; 899 { 900 struct pcic_handle *ph = &sc->sc_pcmcia_h; 901 #if rbus 902 rbus_tag_t rb; 903 #endif 904 905 /* initialize pcmcia part in pccbb_softc */ 906 ph->ph_parent = (struct device *)sc; 907 ph->sock = sc->sc_function; 908 ph->flags = 0; 909 ph->shutdown = 0; 910 ph->ih_irq = sc->sc_pa.pa_intrline; 911 ph->ph_bus_t = sc->sc_base_memt; 912 ph->ph_bus_h = sc->sc_base_memh; 913 ph->ph_read = pccbb_pcmcia_read; 914 ph->ph_write = pccbb_pcmcia_write; 915 sc->sc_pct = &pccbb_pcmcia_funcs; 916 917 /* 918 * We need to do a few things here: 919 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 920 * setting the IRQ numbers to 0. 921 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 922 * routing of CSC interrupts (e.g. card removal) to PCI while in 923 * PCMCIA mode. We just leave this set all the time. 924 * 3) Enable card insertion/removal interrupts in case the chip also 925 * needs that while in PCMCIA mode. 926 * 4) Clear any pending CSC interrupt. 927 */ 928 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 929 if (sc->sc_chipset == CB_TI113X) { 930 Pcic_write(ph, PCIC_CSC_INTR, 0); 931 } else { 932 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 933 Pcic_read(ph, PCIC_CSC); 934 } 935 936 /* initialize pcmcia bus attachment */ 937 paa->paa_busname = "pcmcia"; 938 paa->pct = sc->sc_pct; 939 paa->pch = ph; 940 paa->iobase = 0; /* I don't use them */ 941 paa->iosize = 0; 942 #if rbus 943 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 944 paa->iobase = rb->rb_start + rb->rb_offset; 945 paa->iosize = rb->rb_end - rb->rb_start; 946 #endif 947 948 return; 949 } 950 951 #if 0 952 STATIC void 953 pccbb_pcmcia_attach_card(ph) 954 struct pcic_handle *ph; 955 { 956 if (ph->flags & PCIC_FLAG_CARDP) { 957 panic("pccbb_pcmcia_attach_card: already attached"); 958 } 959 960 /* call the MI attach function */ 961 pcmcia_card_attach(ph->pcmcia); 962 963 ph->flags |= PCIC_FLAG_CARDP; 964 } 965 966 STATIC void 967 pccbb_pcmcia_detach_card(ph, flags) 968 struct pcic_handle *ph; 969 int flags; 970 { 971 if (!(ph->flags & PCIC_FLAG_CARDP)) { 972 panic("pccbb_pcmcia_detach_card: already detached"); 973 } 974 975 ph->flags &= ~PCIC_FLAG_CARDP; 976 977 /* call the MI detach function */ 978 pcmcia_card_detach(ph->pcmcia, flags); 979 } 980 #endif 981 982 /* 983 * int pccbbintr(arg) 984 * void *arg; 985 * This routine handles the interrupt from Yenta PCI-CardBus bridge 986 * itself. 987 */ 988 int 989 pccbbintr(arg) 990 void *arg; 991 { 992 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 993 u_int32_t sockevent, sockstate; 994 bus_space_tag_t memt = sc->sc_base_memt; 995 bus_space_handle_t memh = sc->sc_base_memh; 996 struct pcic_handle *ph = &sc->sc_pcmcia_h; 997 998 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 999 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1000 Pcic_read(ph, PCIC_CSC); 1001 1002 if (sockevent == 0) { 1003 /* This intr is not for me: it may be for my child devices. */ 1004 if (sc->sc_pil_intr_enable) { 1005 return pccbbintr_function(sc); 1006 } else { 1007 return 0; 1008 } 1009 } 1010 1011 if (sockevent & CB_SOCKET_EVENT_CD) { 1012 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1013 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 1014 /* A card should be removed. */ 1015 if (sc->sc_flags & CBB_CARDEXIST) { 1016 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1017 sockevent)); 1018 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1019 sc->sc_flags &= ~CBB_CARDEXIST; 1020 if (sc->sc_csc->sc_status & 1021 CARDSLOT_STATUS_CARD_16) { 1022 #if 0 1023 struct pcic_handle *ph = 1024 &sc->sc_pcmcia_h; 1025 1026 pcmcia_card_deactivate(ph->pcmcia); 1027 pccbb_pcmcia_socket_disable(ph); 1028 pccbb_pcmcia_detach_card(ph, 1029 DETACH_FORCE); 1030 #endif 1031 cardslot_event_throw(sc->sc_csc, 1032 CARDSLOT_EVENT_REMOVAL_16); 1033 } else if (sc->sc_csc->sc_status & 1034 CARDSLOT_STATUS_CARD_CB) { 1035 /* Cardbus intr removed */ 1036 cardslot_event_throw(sc->sc_csc, 1037 CARDSLOT_EVENT_REMOVAL_CB); 1038 } 1039 } else if (sc->sc_flags & CBB_INSERTING) { 1040 sc->sc_flags &= ~CBB_INSERTING; 1041 callout_stop(&sc->sc_insert_ch); 1042 } 1043 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1044 /* 1045 * The pccbbintr may called from powerdown hook when 1046 * the system resumed, to detect the card 1047 * insertion/removal during suspension. 1048 */ 1049 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1050 if (sc->sc_flags & CBB_INSERTING) { 1051 callout_stop(&sc->sc_insert_ch); 1052 } 1053 callout_reset(&sc->sc_insert_ch, hz / 5, 1054 pci113x_insert, sc); 1055 sc->sc_flags |= CBB_INSERTING; 1056 } 1057 } 1058 1059 return (1); 1060 } 1061 1062 /* 1063 * static int pccbbintr_function(struct pccbb_softc *sc) 1064 * 1065 * This function calls each interrupt handler registered at the 1066 * bridge. The interrupt handlers are called in registered order. 1067 */ 1068 static int 1069 pccbbintr_function(sc) 1070 struct pccbb_softc *sc; 1071 { 1072 int retval = 0, val; 1073 struct pccbb_intrhand_list *pil; 1074 int s, splchanged; 1075 1076 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1077 /* 1078 * XXX priority change. gross. I use if-else 1079 * sentense instead of switch-case sentense because of 1080 * avoiding duplicate case value error. More than one 1081 * IPL_XXX use same value. It depends on 1082 * implimentation. 1083 */ 1084 splchanged = 1; 1085 if (pil->pil_level == IPL_SERIAL) { 1086 s = splserial(); 1087 } else if (pil->pil_level == IPL_HIGH) { 1088 s = splhigh(); 1089 } else if (pil->pil_level == IPL_CLOCK) { 1090 s = splclock(); 1091 } else if (pil->pil_level == IPL_AUDIO) { 1092 s = splaudio(); 1093 } else if (pil->pil_level == IPL_IMP) { 1094 s = splvm(); /* XXX */ 1095 } else if (pil->pil_level == IPL_TTY) { 1096 s = spltty(); 1097 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1098 s = splsoftserial(); 1099 } else if (pil->pil_level == IPL_NET) { 1100 s = splnet(); 1101 } else { 1102 splchanged = 0; 1103 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1104 } 1105 1106 val = (*pil->pil_func)(pil->pil_arg); 1107 1108 if (splchanged != 0) { 1109 splx(s); 1110 } 1111 1112 retval = retval == 1 ? 1 : 1113 retval == 0 ? val : val != 0 ? val : retval; 1114 } 1115 1116 return retval; 1117 } 1118 1119 static void 1120 pci113x_insert(arg) 1121 void *arg; 1122 { 1123 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1124 u_int32_t sockevent, sockstate; 1125 1126 if (!(sc->sc_flags & CBB_INSERTING)) { 1127 /* We add a card only under inserting state. */ 1128 return; 1129 } 1130 sc->sc_flags &= ~CBB_INSERTING; 1131 1132 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1133 CB_SOCKET_EVENT); 1134 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1135 CB_SOCKET_STAT); 1136 1137 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1138 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1139 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1140 sc->sc_flags |= CBB_CARDEXIST; 1141 /* call pccard interrupt handler here */ 1142 if (sockstate & CB_SOCKET_STAT_16BIT) { 1143 /* 16-bit card found */ 1144 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1145 cardslot_event_throw(sc->sc_csc, 1146 CARDSLOT_EVENT_INSERTION_16); 1147 } else if (sockstate & CB_SOCKET_STAT_CB) { 1148 /* cardbus card found */ 1149 /* cardbus_attach_card(sc->sc_csc); */ 1150 cardslot_event_throw(sc->sc_csc, 1151 CARDSLOT_EVENT_INSERTION_CB); 1152 } else { 1153 /* who are you? */ 1154 } 1155 } else { 1156 callout_reset(&sc->sc_insert_ch, hz / 10, 1157 pci113x_insert, sc); 1158 } 1159 } 1160 1161 #define PCCBB_PCMCIA_OFFSET 0x800 1162 static u_int8_t 1163 pccbb_pcmcia_read(ph, reg) 1164 struct pcic_handle *ph; 1165 int reg; 1166 { 1167 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1168 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1169 1170 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1171 PCCBB_PCMCIA_OFFSET + reg); 1172 } 1173 1174 static void 1175 pccbb_pcmcia_write(ph, reg, val) 1176 struct pcic_handle *ph; 1177 int reg; 1178 u_int8_t val; 1179 { 1180 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1181 val); 1182 1183 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1184 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1185 } 1186 1187 /* 1188 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1189 */ 1190 STATIC int 1191 pccbb_ctrl(ct, command) 1192 cardbus_chipset_tag_t ct; 1193 int command; 1194 { 1195 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1196 1197 switch (command) { 1198 case CARDBUS_CD: 1199 if (2 == pccbb_detect_card(sc)) { 1200 int retval = 0; 1201 int status = cb_detect_voltage(sc); 1202 if (PCCARD_VCC_5V & status) { 1203 retval |= CARDBUS_5V_CARD; 1204 } 1205 if (PCCARD_VCC_3V & status) { 1206 retval |= CARDBUS_3V_CARD; 1207 } 1208 if (PCCARD_VCC_XV & status) { 1209 retval |= CARDBUS_XV_CARD; 1210 } 1211 if (PCCARD_VCC_YV & status) { 1212 retval |= CARDBUS_YV_CARD; 1213 } 1214 return retval; 1215 } else { 1216 return 0; 1217 } 1218 break; 1219 case CARDBUS_RESET: 1220 return cb_reset(sc); 1221 break; 1222 case CARDBUS_IO_ENABLE: /* fallthrough */ 1223 case CARDBUS_IO_DISABLE: /* fallthrough */ 1224 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1225 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1226 case CARDBUS_BM_ENABLE: /* fallthrough */ 1227 case CARDBUS_BM_DISABLE: /* fallthrough */ 1228 /* XXX: I think we don't need to call this function below. */ 1229 return pccbb_cardenable(sc, command); 1230 break; 1231 } 1232 1233 return 0; 1234 } 1235 1236 /* 1237 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1238 * This function returns true when it succeeds and returns false when 1239 * it fails. 1240 */ 1241 STATIC int 1242 pccbb_power(ct, command) 1243 cardbus_chipset_tag_t ct; 1244 int command; 1245 { 1246 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1247 1248 u_int32_t status, sock_ctrl; 1249 bus_space_tag_t memt = sc->sc_base_memt; 1250 bus_space_handle_t memh = sc->sc_base_memh; 1251 1252 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1253 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1254 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1258 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1259 "UNKNOWN", 1260 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1261 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1263 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1264 "UNKNOWN", command)); 1265 1266 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1267 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1268 1269 switch (command & CARDBUS_VCCMASK) { 1270 case CARDBUS_VCC_UC: 1271 break; 1272 case CARDBUS_VCC_5V: 1273 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1274 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1275 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1276 } else { 1277 printf("%s: BAD voltage request: no 5 V card\n", 1278 sc->sc_dev.dv_xname); 1279 } 1280 break; 1281 case CARDBUS_VCC_3V: 1282 if (CB_SOCKET_STAT_3VCARD & status) { 1283 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1284 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1285 } else { 1286 printf("%s: BAD voltage request: no 3.3 V card\n", 1287 sc->sc_dev.dv_xname); 1288 } 1289 break; 1290 case CARDBUS_VCC_0V: 1291 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1292 break; 1293 default: 1294 return 0; /* power NEVER changed */ 1295 break; 1296 } 1297 1298 switch (command & CARDBUS_VPPMASK) { 1299 case CARDBUS_VPP_UC: 1300 break; 1301 case CARDBUS_VPP_0V: 1302 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1303 break; 1304 case CARDBUS_VPP_VCC: 1305 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1306 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1307 break; 1308 case CARDBUS_VPP_12V: 1309 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1310 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1311 break; 1312 } 1313 1314 #if 0 1315 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1316 #endif 1317 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1318 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1319 1320 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1321 printf 1322 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1323 sc->sc_dev.dv_xname, sock_ctrl, status); 1324 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1325 (command & CARDBUS_VCCMASK) == 1326 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1327 CARDBUS_VCCMASK) == 1328 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1329 CARDBUS_VCCMASK) == 1330 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1331 CARDBUS_VCCMASK) == 1332 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1333 CARDBUS_VCCMASK) == 1334 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1335 CARDBUS_VCCMASK) == 1336 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1337 (command & CARDBUS_VPPMASK) == 1338 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1339 CARDBUS_VPPMASK) == 1340 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1341 CARDBUS_VPPMASK) == 1342 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1343 CARDBUS_VPPMASK) == 1344 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1345 #if 0 1346 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1347 u_int32_t force = 1348 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1349 /* Reset Bad Vcc request */ 1350 force &= ~CB_SOCKET_FORCE_BADVCC; 1351 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1352 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1353 CB_SOCKET_STAT)); 1354 return 1; 1355 } 1356 #endif 1357 return 0; 1358 } 1359 1360 /* 1361 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1362 * time is 20 ms, some PC-Card bridge requires longer duration. 1363 */ 1364 #if 0 /* XXX called on interrupt context */ 1365 DELAY_MS(300, sc); 1366 #else 1367 delay(300 * 1000); 1368 #endif 1369 1370 return 1; /* power changed correctly */ 1371 } 1372 1373 #if defined CB_PCMCIA_POLL 1374 struct cb_poll_str { 1375 void *arg; 1376 int (*func) __P((void *)); 1377 int level; 1378 pccard_chipset_tag_t ct; 1379 int count; 1380 struct callout poll_ch; 1381 }; 1382 1383 static struct cb_poll_str cb_poll[10]; 1384 static int cb_poll_n = 0; 1385 1386 static void cb_pcmcia_poll __P((void *arg)); 1387 1388 static void 1389 cb_pcmcia_poll(arg) 1390 void *arg; 1391 { 1392 struct cb_poll_str *poll = arg; 1393 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1394 struct pccbb_softc *sc = psc->cpc_parent; 1395 int s; 1396 u_int32_t spsr; /* socket present-state reg */ 1397 1398 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1399 switch (poll->level) { 1400 case IPL_NET: 1401 s = splnet(); 1402 break; 1403 case IPL_BIO: 1404 s = splbio(); 1405 break; 1406 case IPL_TTY: /* fallthrough */ 1407 default: 1408 s = spltty(); 1409 break; 1410 } 1411 1412 spsr = 1413 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1414 CB_SOCKET_STAT); 1415 1416 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1417 if (!(spsr & 0x40)) { /* CINT low */ 1418 #else 1419 if (1) { 1420 #endif 1421 if ((*poll->func) (poll->arg) == 1) { 1422 ++poll->count; 1423 printf("intr: reported from poller, 0x%x\n", spsr); 1424 #if defined LEVEL2 1425 } else { 1426 printf("intr: miss! 0x%x\n", spsr); 1427 #endif 1428 } 1429 } 1430 splx(s); 1431 } 1432 #endif /* defined CB_PCMCIA_POLL */ 1433 1434 /* 1435 * static int pccbb_detect_card(struct pccbb_softc *sc) 1436 * return value: 0 if no card exists. 1437 * 1 if 16-bit card exists. 1438 * 2 if cardbus card exists. 1439 */ 1440 static int 1441 pccbb_detect_card(sc) 1442 struct pccbb_softc *sc; 1443 { 1444 bus_space_handle_t base_memh = sc->sc_base_memh; 1445 bus_space_tag_t base_memt = sc->sc_base_memt; 1446 u_int32_t sockstat = 1447 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1448 int retval = 0; 1449 1450 /* CD1 and CD2 asserted */ 1451 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1452 /* card must be present */ 1453 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1454 /* NOTACARD DEASSERTED */ 1455 if (CB_SOCKET_STAT_CB & sockstat) { 1456 /* CardBus mode */ 1457 retval = 2; 1458 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1459 /* 16-bit mode */ 1460 retval = 1; 1461 } 1462 } 1463 } 1464 return retval; 1465 } 1466 1467 /* 1468 * STATIC int cb_reset(struct pccbb_softc *sc) 1469 * This function resets CardBus card. 1470 */ 1471 STATIC int 1472 cb_reset(sc) 1473 struct pccbb_softc *sc; 1474 { 1475 /* 1476 * Reset Assert at least 20 ms 1477 * Some machines request longer duration. 1478 */ 1479 int reset_duration = 1480 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1481 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1482 1483 /* Reset bit Assert (bit 6 at 0x3E) */ 1484 bcr |= CB_BCR_RESET_ENABLE; 1485 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1486 DELAY_MS(reset_duration, sc); 1487 1488 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1489 /* Reset bit Deassert (bit 6 at 0x3E) */ 1490 bcr &= ~CB_BCR_RESET_ENABLE; 1491 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1492 DELAY_MS(reset_duration, sc); 1493 } 1494 /* No card found on the slot. Keep Reset. */ 1495 return 1; 1496 } 1497 1498 /* 1499 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1500 * This function detect card Voltage. 1501 */ 1502 STATIC int 1503 cb_detect_voltage(sc) 1504 struct pccbb_softc *sc; 1505 { 1506 u_int32_t psr; /* socket present-state reg */ 1507 bus_space_tag_t iot = sc->sc_base_memt; 1508 bus_space_handle_t ioh = sc->sc_base_memh; 1509 int vol = PCCARD_VCC_UKN; /* set 0 */ 1510 1511 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1512 1513 if (0x400u & psr) { 1514 vol |= PCCARD_VCC_5V; 1515 } 1516 if (0x800u & psr) { 1517 vol |= PCCARD_VCC_3V; 1518 } 1519 1520 return vol; 1521 } 1522 1523 STATIC int 1524 cbbprint(aux, pcic) 1525 void *aux; 1526 const char *pcic; 1527 { 1528 /* 1529 struct cbslot_attach_args *cba = aux; 1530 1531 if (cba->cba_slot >= 0) { 1532 printf(" slot %d", cba->cba_slot); 1533 } 1534 */ 1535 return UNCONF; 1536 } 1537 1538 /* 1539 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1540 * This function enables and disables the card 1541 */ 1542 STATIC int 1543 pccbb_cardenable(sc, function) 1544 struct pccbb_softc *sc; 1545 int function; 1546 { 1547 u_int32_t command = 1548 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1549 1550 DPRINTF(("pccbb_cardenable:")); 1551 switch (function) { 1552 case CARDBUS_IO_ENABLE: 1553 command |= PCI_COMMAND_IO_ENABLE; 1554 break; 1555 case CARDBUS_IO_DISABLE: 1556 command &= ~PCI_COMMAND_IO_ENABLE; 1557 break; 1558 case CARDBUS_MEM_ENABLE: 1559 command |= PCI_COMMAND_MEM_ENABLE; 1560 break; 1561 case CARDBUS_MEM_DISABLE: 1562 command &= ~PCI_COMMAND_MEM_ENABLE; 1563 break; 1564 case CARDBUS_BM_ENABLE: 1565 command |= PCI_COMMAND_MASTER_ENABLE; 1566 break; 1567 case CARDBUS_BM_DISABLE: 1568 command &= ~PCI_COMMAND_MASTER_ENABLE; 1569 break; 1570 default: 1571 return 0; 1572 } 1573 1574 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1575 DPRINTF((" command reg 0x%x\n", command)); 1576 return 1; 1577 } 1578 1579 #if !rbus 1580 /* 1581 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1582 */ 1583 static int 1584 pccbb_io_open(ct, win, start, end) 1585 cardbus_chipset_tag_t ct; 1586 int win; 1587 u_int32_t start, end; 1588 { 1589 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1590 int basereg; 1591 int limitreg; 1592 1593 if ((win < 0) || (win > 2)) { 1594 #if defined DIAGNOSTIC 1595 printf("cardbus_io_open: window out of range %d\n", win); 1596 #endif 1597 return 0; 1598 } 1599 1600 basereg = win * 8 + 0x2c; 1601 limitreg = win * 8 + 0x30; 1602 1603 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1604 start, basereg, end, limitreg)); 1605 1606 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1607 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1608 return 1; 1609 } 1610 1611 /* 1612 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1613 */ 1614 static int 1615 pccbb_io_close(ct, win) 1616 cardbus_chipset_tag_t ct; 1617 int win; 1618 { 1619 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1620 int basereg; 1621 int limitreg; 1622 1623 if ((win < 0) || (win > 2)) { 1624 #if defined DIAGNOSTIC 1625 printf("cardbus_io_close: window out of range %d\n", win); 1626 #endif 1627 return 0; 1628 } 1629 1630 basereg = win * 8 + 0x2c; 1631 limitreg = win * 8 + 0x30; 1632 1633 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1634 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1635 return 1; 1636 } 1637 1638 /* 1639 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1640 */ 1641 static int 1642 pccbb_mem_open(ct, win, start, end) 1643 cardbus_chipset_tag_t ct; 1644 int win; 1645 u_int32_t start, end; 1646 { 1647 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1648 int basereg; 1649 int limitreg; 1650 1651 if ((win < 0) || (win > 2)) { 1652 #if defined DIAGNOSTIC 1653 printf("cardbus_mem_open: window out of range %d\n", win); 1654 #endif 1655 return 0; 1656 } 1657 1658 basereg = win * 8 + 0x1c; 1659 limitreg = win * 8 + 0x20; 1660 1661 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1662 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1663 return 1; 1664 } 1665 1666 /* 1667 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1668 */ 1669 static int 1670 pccbb_mem_close(ct, win) 1671 cardbus_chipset_tag_t ct; 1672 int win; 1673 { 1674 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1675 int basereg; 1676 int limitreg; 1677 1678 if ((win < 0) || (win > 2)) { 1679 #if defined DIAGNOSTIC 1680 printf("cardbus_mem_close: window out of range %d\n", win); 1681 #endif 1682 return 0; 1683 } 1684 1685 basereg = win * 8 + 0x1c; 1686 limitreg = win * 8 + 0x20; 1687 1688 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1689 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1690 return 1; 1691 } 1692 #endif 1693 1694 /* 1695 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1696 * int irq, 1697 * int level, 1698 * int (* func) __P((void *)), 1699 * void *arg) 1700 * 1701 * This function registers an interrupt handler at the bridge, in 1702 * order not to call the interrupt handlers of child devices when 1703 * a card-deletion interrupt occurs. 1704 * 1705 * The arguments irq and level are not used. 1706 */ 1707 static void * 1708 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1709 cardbus_chipset_tag_t ct; 1710 int irq, level; 1711 int (*func) __P((void *)); 1712 void *arg; 1713 { 1714 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1715 1716 return pccbb_intr_establish(sc, irq, level, func, arg); 1717 } 1718 1719 1720 /* 1721 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1722 * void *ih) 1723 * 1724 * This function removes an interrupt handler pointed by ih. 1725 */ 1726 static void 1727 pccbb_cb_intr_disestablish(ct, ih) 1728 cardbus_chipset_tag_t ct; 1729 void *ih; 1730 { 1731 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1732 1733 pccbb_intr_disestablish(sc, ih); 1734 } 1735 1736 1737 void 1738 pccbb_intr_route(sc) 1739 struct pccbb_softc *sc; 1740 { 1741 pcireg_t reg; 1742 1743 /* initialize bridge intr routing */ 1744 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1745 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1746 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1747 1748 switch (sc->sc_chipset) { 1749 case CB_TI113X: 1750 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1751 /* functional intr enabled */ 1752 reg |= PCI113X_CBCTRL_PCI_INTR; 1753 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1754 break; 1755 default: 1756 break; 1757 } 1758 } 1759 1760 /* 1761 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1762 * int irq, 1763 * int level, 1764 * int (* func) __P((void *)), 1765 * void *arg) 1766 * 1767 * This function registers an interrupt handler at the bridge, in 1768 * order not to call the interrupt handlers of child devices when 1769 * a card-deletion interrupt occurs. 1770 * 1771 * The arguments irq is not used because pccbb selects intr vector. 1772 */ 1773 static void * 1774 pccbb_intr_establish(sc, irq, level, func, arg) 1775 struct pccbb_softc *sc; 1776 int irq, level; 1777 int (*func) __P((void *)); 1778 void *arg; 1779 { 1780 struct pccbb_intrhand_list *pil, *newpil; 1781 1782 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1783 1784 if (sc->sc_pil == NULL) { 1785 pccbb_intr_route(sc); 1786 1787 } 1788 1789 /* 1790 * Allocate a room for interrupt handler structure. 1791 */ 1792 if (NULL == (newpil = 1793 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1794 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1795 return NULL; 1796 } 1797 1798 newpil->pil_func = func; 1799 newpil->pil_arg = arg; 1800 newpil->pil_level = level; 1801 newpil->pil_next = NULL; 1802 1803 if (sc->sc_pil == NULL) { 1804 sc->sc_pil = newpil; 1805 } else { 1806 for (pil = sc->sc_pil; pil->pil_next != NULL; 1807 pil = pil->pil_next); 1808 pil->pil_next = newpil; 1809 } 1810 1811 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1812 1813 return newpil; 1814 } 1815 1816 /* 1817 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1818 * void *ih) 1819 * 1820 * This function removes an interrupt handler pointed by ih. 1821 */ 1822 static void 1823 pccbb_intr_disestablish(sc, ih) 1824 struct pccbb_softc *sc; 1825 void *ih; 1826 { 1827 struct pccbb_intrhand_list *pil, **pil_prev; 1828 pcireg_t reg; 1829 1830 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1831 1832 pil_prev = &sc->sc_pil; 1833 1834 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1835 if (pil == ih) { 1836 *pil_prev = pil->pil_next; 1837 free(pil, M_DEVBUF); 1838 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1839 break; 1840 } 1841 pil_prev = &pil->pil_next; 1842 } 1843 1844 if (sc->sc_pil == NULL) { 1845 /* No interrupt handlers */ 1846 1847 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1848 1849 /* stop routing PCI intr */ 1850 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1851 reg |= CB_BCR_INTR_IREQ_ENABLE; 1852 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1853 1854 switch (sc->sc_chipset) { 1855 case CB_TI113X: 1856 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1857 /* functional intr disabled */ 1858 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1859 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1860 break; 1861 default: 1862 break; 1863 } 1864 } 1865 } 1866 1867 #if defined SHOW_REGS 1868 static void 1869 cb_show_regs(pc, tag, memt, memh) 1870 pci_chipset_tag_t pc; 1871 pcitag_t tag; 1872 bus_space_tag_t memt; 1873 bus_space_handle_t memh; 1874 { 1875 int i; 1876 printf("PCI config regs:"); 1877 for (i = 0; i < 0x50; i += 4) { 1878 if (i % 16 == 0) { 1879 printf("\n 0x%02x:", i); 1880 } 1881 printf(" %08x", pci_conf_read(pc, tag, i)); 1882 } 1883 for (i = 0x80; i < 0xb0; i += 4) { 1884 if (i % 16 == 0) { 1885 printf("\n 0x%02x:", i); 1886 } 1887 printf(" %08x", pci_conf_read(pc, tag, i)); 1888 } 1889 1890 if (memh == 0) { 1891 printf("\n"); 1892 return; 1893 } 1894 1895 printf("\nsocket regs:"); 1896 for (i = 0; i <= 0x10; i += 0x04) { 1897 printf(" %08x", bus_space_read_4(memt, memh, i)); 1898 } 1899 printf("\nExCA regs:"); 1900 for (i = 0; i < 0x08; ++i) { 1901 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1902 } 1903 printf("\n"); 1904 return; 1905 } 1906 #endif 1907 1908 /* 1909 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1910 * int busno, int devno, int function) 1911 * This is the function to make a tag to access config space of 1912 * a CardBus Card. It works same as pci_conf_read. 1913 */ 1914 static cardbustag_t 1915 pccbb_make_tag(cc, busno, devno, function) 1916 cardbus_chipset_tag_t cc; 1917 int busno, devno, function; 1918 { 1919 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1920 1921 return pci_make_tag(sc->sc_pc, busno, devno, function); 1922 } 1923 1924 static void 1925 pccbb_free_tag(cc, tag) 1926 cardbus_chipset_tag_t cc; 1927 cardbustag_t tag; 1928 { 1929 } 1930 1931 /* 1932 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1933 * cardbustag_t tag, int offset) 1934 * This is the function to read the config space of a CardBus Card. 1935 * It works same as pci_conf_read. 1936 */ 1937 static cardbusreg_t 1938 pccbb_conf_read(cc, tag, offset) 1939 cardbus_chipset_tag_t cc; 1940 cardbustag_t tag; 1941 int offset; /* register offset */ 1942 { 1943 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1944 1945 return pci_conf_read(sc->sc_pc, tag, offset); 1946 } 1947 1948 /* 1949 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1950 * int offs, cardbusreg_t val) 1951 * This is the function to write the config space of a CardBus Card. 1952 * It works same as pci_conf_write. 1953 */ 1954 static void 1955 pccbb_conf_write(cc, tag, reg, val) 1956 cardbus_chipset_tag_t cc; 1957 cardbustag_t tag; 1958 int reg; /* register offset */ 1959 cardbusreg_t val; 1960 { 1961 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1962 1963 pci_conf_write(sc->sc_pc, tag, reg, val); 1964 } 1965 1966 #if 0 1967 STATIC int 1968 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1969 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1970 int speed, int flags, 1971 bus_space_handle_t * iohp) 1972 #endif 1973 /* 1974 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1975 * bus_addr_t start, bus_size_t size, 1976 * bus_size_t align, 1977 * struct pcmcia_io_handle *pcihp 1978 * 1979 * This function only allocates I/O region for pccard. This function 1980 * never maps the allocated region to pccard I/O area. 1981 * 1982 * XXX: The interface of this function is not very good, I believe. 1983 */ 1984 STATIC int 1985 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1986 pcmcia_chipset_handle_t pch; 1987 bus_addr_t start; /* start address */ 1988 bus_size_t size; 1989 bus_size_t align; 1990 struct pcmcia_io_handle *pcihp; 1991 { 1992 struct pcic_handle *ph = (struct pcic_handle *)pch; 1993 bus_addr_t ioaddr; 1994 int flags = 0; 1995 bus_space_tag_t iot; 1996 bus_space_handle_t ioh; 1997 bus_addr_t mask; 1998 #if rbus 1999 rbus_tag_t rb; 2000 #endif 2001 if (align == 0) { 2002 align = size; /* XXX: funny??? */ 2003 } 2004 2005 if (start != 0) { 2006 /* XXX: assume all card decode lower 10 bits by its hardware */ 2007 mask = 0x3ff; 2008 /* enforce to use only masked address */ 2009 start &= mask; 2010 } else { 2011 /* 2012 * calculate mask: 2013 * 1. get the most significant bit of size (call it msb). 2014 * 2. compare msb with the value of size. 2015 * 3. if size is larger, shift msb left once. 2016 * 4. obtain mask value to decrement msb. 2017 */ 2018 bus_size_t size_tmp = size; 2019 int shifts = 0; 2020 2021 mask = 1; 2022 while (size_tmp) { 2023 ++shifts; 2024 size_tmp >>= 1; 2025 } 2026 mask = (1 << shifts); 2027 if (mask < size) { 2028 mask <<= 1; 2029 } 2030 --mask; 2031 } 2032 2033 /* 2034 * Allocate some arbitrary I/O space. 2035 */ 2036 2037 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2038 2039 #if rbus 2040 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2041 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2042 return 1; 2043 } 2044 #else 2045 if (start) { 2046 ioaddr = start; 2047 if (bus_space_map(iot, start, size, 0, &ioh)) { 2048 return 1; 2049 } 2050 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2051 (u_long) ioaddr, (u_long) size)); 2052 } else { 2053 flags |= PCMCIA_IO_ALLOCATED; 2054 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2055 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2056 size, align, 0, 0, &ioaddr, &ioh)) { 2057 /* No room be able to be get. */ 2058 return 1; 2059 } 2060 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2061 (u_long) ioaddr, (u_long) size)); 2062 } 2063 #endif 2064 2065 pcihp->iot = iot; 2066 pcihp->ioh = ioh; 2067 pcihp->addr = ioaddr; 2068 pcihp->size = size; 2069 pcihp->flags = flags; 2070 2071 return 0; 2072 } 2073 2074 /* 2075 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2076 * struct pcmcia_io_handle *pcihp) 2077 * 2078 * This function only frees I/O region for pccard. 2079 * 2080 * XXX: The interface of this function is not very good, I believe. 2081 */ 2082 void 2083 pccbb_pcmcia_io_free(pch, pcihp) 2084 pcmcia_chipset_handle_t pch; 2085 struct pcmcia_io_handle *pcihp; 2086 { 2087 #if !rbus 2088 bus_space_tag_t iot = pcihp->iot; 2089 #endif 2090 bus_space_handle_t ioh = pcihp->ioh; 2091 bus_size_t size = pcihp->size; 2092 2093 #if rbus 2094 struct pccbb_softc *sc = 2095 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2096 rbus_tag_t rb = sc->sc_rbus_iot; 2097 2098 rbus_space_free(rb, ioh, size, NULL); 2099 #else 2100 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2101 bus_space_free(iot, ioh, size); 2102 else 2103 bus_space_unmap(iot, ioh, size); 2104 #endif 2105 } 2106 2107 /* 2108 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2109 * bus_addr_t offset, bus_size_t size, 2110 * struct pcmcia_io_handle *pcihp, 2111 * int *windowp) 2112 * 2113 * This function maps the allocated I/O region to pccard. This function 2114 * never allocates any I/O region for pccard I/O area. I don't 2115 * understand why the original authors of pcmciabus separated alloc and 2116 * map. I believe the two must be unite. 2117 * 2118 * XXX: no wait timing control? 2119 */ 2120 int 2121 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2122 pcmcia_chipset_handle_t pch; 2123 int width; 2124 bus_addr_t offset; 2125 bus_size_t size; 2126 struct pcmcia_io_handle *pcihp; 2127 int *windowp; 2128 { 2129 struct pcic_handle *ph = (struct pcic_handle *)pch; 2130 bus_addr_t ioaddr = pcihp->addr + offset; 2131 int i, win; 2132 #if defined CBB_DEBUG 2133 static char *width_names[] = { "dynamic", "io8", "io16" }; 2134 #endif 2135 2136 /* Sanity check I/O handle. */ 2137 2138 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2139 panic("pccbb_pcmcia_io_map iot is bogus"); 2140 } 2141 2142 /* XXX Sanity check offset/size. */ 2143 2144 win = -1; 2145 for (i = 0; i < PCIC_IO_WINS; i++) { 2146 if ((ph->ioalloc & (1 << i)) == 0) { 2147 win = i; 2148 ph->ioalloc |= (1 << i); 2149 break; 2150 } 2151 } 2152 2153 if (win == -1) { 2154 return 1; 2155 } 2156 2157 *windowp = win; 2158 2159 /* XXX this is pretty gross */ 2160 2161 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2162 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2163 2164 /* XXX wtf is this doing here? */ 2165 2166 #if 0 2167 printf(" port 0x%lx", (u_long) ioaddr); 2168 if (size > 1) { 2169 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2170 } 2171 #endif 2172 2173 ph->io[win].addr = ioaddr; 2174 ph->io[win].size = size; 2175 ph->io[win].width = width; 2176 2177 /* actual dirty register-value changing in the function below. */ 2178 pccbb_pcmcia_do_io_map(ph, win); 2179 2180 return 0; 2181 } 2182 2183 /* 2184 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2185 * 2186 * This function changes register-value to map I/O region for pccard. 2187 */ 2188 static void 2189 pccbb_pcmcia_do_io_map(ph, win) 2190 struct pcic_handle *ph; 2191 int win; 2192 { 2193 static u_int8_t pcic_iowidth[3] = { 2194 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2195 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2196 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2197 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2198 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2199 }; 2200 2201 #define PCIC_SIA_START_LOW 0 2202 #define PCIC_SIA_START_HIGH 1 2203 #define PCIC_SIA_STOP_LOW 2 2204 #define PCIC_SIA_STOP_HIGH 3 2205 2206 int regbase_win = 0x8 + win * 0x04; 2207 u_int8_t ioctl, enable; 2208 2209 DPRINTF( 2210 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2211 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2212 ph->io[win].width * 8)); 2213 2214 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2215 ph->io[win].addr & 0xff); 2216 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2217 (ph->io[win].addr >> 8) & 0xff); 2218 2219 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2220 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2221 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2222 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2223 2224 ioctl = Pcic_read(ph, PCIC_IOCTL); 2225 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2226 switch (win) { 2227 case 0: 2228 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2229 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2230 PCIC_IOCTL_IO0_DATASIZE_MASK); 2231 ioctl |= pcic_iowidth[ph->io[win].width]; 2232 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2233 break; 2234 case 1: 2235 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2236 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2237 PCIC_IOCTL_IO1_DATASIZE_MASK); 2238 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2239 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2240 break; 2241 } 2242 Pcic_write(ph, PCIC_IOCTL, ioctl); 2243 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2244 #if defined CBB_DEBUG 2245 { 2246 u_int8_t start_low = 2247 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2248 u_int8_t start_high = 2249 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2250 u_int8_t stop_low = 2251 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2252 u_int8_t stop_high = 2253 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2254 printf 2255 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2256 start_low, start_high, stop_low, stop_high, ioctl, enable); 2257 } 2258 #endif 2259 } 2260 2261 /* 2262 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2263 * 2264 * This function unmaps I/O region. No return value. 2265 */ 2266 STATIC void 2267 pccbb_pcmcia_io_unmap(pch, win) 2268 pcmcia_chipset_handle_t pch; 2269 int win; 2270 { 2271 struct pcic_handle *ph = (struct pcic_handle *)pch; 2272 int reg; 2273 2274 if (win >= PCIC_IO_WINS || win < 0) { 2275 panic("pccbb_pcmcia_io_unmap: window out of range"); 2276 } 2277 2278 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2279 switch (win) { 2280 case 0: 2281 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2282 break; 2283 case 1: 2284 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2285 break; 2286 } 2287 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2288 2289 ph->ioalloc &= ~(1 << win); 2290 } 2291 2292 /* 2293 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2294 * 2295 * This function enables the card. All information is stored in 2296 * the first argument, pcmcia_chipset_handle_t. 2297 */ 2298 static void 2299 pccbb_pcmcia_wait_ready(ph) 2300 struct pcic_handle *ph; 2301 { 2302 int i; 2303 2304 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2305 Pcic_read(ph, PCIC_IF_STATUS))); 2306 2307 for (i = 0; i < 2000; i++) { 2308 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2309 return; 2310 } 2311 DELAY_MS(2, ph->ph_parent); 2312 #ifdef CBB_DEBUG 2313 if ((i > 1000) && (i % 25 == 24)) 2314 printf("."); 2315 #endif 2316 } 2317 2318 #ifdef DIAGNOSTIC 2319 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2320 Pcic_read(ph, PCIC_IF_STATUS)); 2321 #endif 2322 } 2323 2324 /* 2325 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2326 * 2327 * This function enables the card. All information is stored in 2328 * the first argument, pcmcia_chipset_handle_t. 2329 */ 2330 STATIC void 2331 pccbb_pcmcia_socket_enable(pch) 2332 pcmcia_chipset_handle_t pch; 2333 { 2334 struct pcic_handle *ph = (struct pcic_handle *)pch; 2335 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2336 int cardtype, win; 2337 u_int8_t power, intr; 2338 pcireg_t spsr; 2339 int voltage; 2340 2341 /* this bit is mostly stolen from pcic_attach_card */ 2342 2343 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2344 2345 /* get card Vcc info */ 2346 2347 spsr = 2348 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2349 CB_SOCKET_STAT); 2350 if (spsr & CB_SOCKET_STAT_5VCARD) { 2351 DPRINTF(("5V card\n")); 2352 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2353 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2354 DPRINTF(("3V card\n")); 2355 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2356 } else { 2357 printf("?V card, 0x%x\n", spsr); /* XXX */ 2358 return; 2359 } 2360 2361 /* disable socket: negate output enable bit and power off */ 2362 2363 power = 0; 2364 Pcic_write(ph, PCIC_PWRCTL, power); 2365 2366 /* power down the socket to reset it, clear the card reset pin */ 2367 2368 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2369 2370 /* 2371 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2372 * we are changing Vcc (Toff). 2373 */ 2374 /* delay(300*1000); too much */ 2375 2376 /* assert reset bit */ 2377 intr = Pcic_read(ph, PCIC_INTR); 2378 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2379 Pcic_write(ph, PCIC_INTR, intr); 2380 2381 /* power up the socket and output enable */ 2382 power = Pcic_read(ph, PCIC_PWRCTL); 2383 power |= PCIC_PWRCTL_OE; 2384 Pcic_write(ph, PCIC_PWRCTL, power); 2385 pccbb_power(sc, voltage); 2386 2387 /* 2388 * hold RESET at least 20 ms: the spec says only 10 us is 2389 * enough, but TI1130 requires at least 20 ms. 2390 */ 2391 #if 0 /* XXX called on interrupt context */ 2392 DELAY_MS(20, sc); 2393 #else 2394 delay(20 * 1000); 2395 #endif 2396 2397 /* clear the reset flag */ 2398 2399 intr |= PCIC_INTR_RESET; 2400 Pcic_write(ph, PCIC_INTR, intr); 2401 2402 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2403 2404 #if 0 /* XXX called on interrupt context */ 2405 DELAY_MS(20, sc); 2406 #else 2407 delay(20 * 1000); 2408 #endif 2409 2410 /* wait for the chip to finish initializing */ 2411 2412 pccbb_pcmcia_wait_ready(ph); 2413 2414 /* zero out the address windows */ 2415 2416 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2417 2418 /* set the card type */ 2419 2420 cardtype = pcmcia_card_gettype(ph->pcmcia); 2421 2422 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2423 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2424 Pcic_write(ph, PCIC_INTR, intr); 2425 2426 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2427 ph->ph_parent->dv_xname, ph->sock, 2428 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2429 2430 /* reinstall all the memory and io mappings */ 2431 2432 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2433 if (ph->memalloc & (1 << win)) { 2434 pccbb_pcmcia_do_mem_map(ph, win); 2435 } 2436 } 2437 2438 for (win = 0; win < PCIC_IO_WINS; ++win) { 2439 if (ph->ioalloc & (1 << win)) { 2440 pccbb_pcmcia_do_io_map(ph, win); 2441 } 2442 } 2443 } 2444 2445 /* 2446 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2447 * 2448 * This function disables the card. All information is stored in 2449 * the first argument, pcmcia_chipset_handle_t. 2450 */ 2451 STATIC void 2452 pccbb_pcmcia_socket_disable(pch) 2453 pcmcia_chipset_handle_t pch; 2454 { 2455 struct pcic_handle *ph = (struct pcic_handle *)pch; 2456 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2457 u_int8_t power, intr; 2458 2459 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2460 2461 /* reset signal asserting... */ 2462 2463 intr = Pcic_read(ph, PCIC_INTR); 2464 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2465 Pcic_write(ph, PCIC_INTR, intr); 2466 delay(2 * 1000); 2467 2468 /* power down the socket */ 2469 power = Pcic_read(ph, PCIC_PWRCTL); 2470 power &= ~PCIC_PWRCTL_OE; 2471 Pcic_write(ph, PCIC_PWRCTL, power); 2472 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2473 /* 2474 * wait 300ms until power fails (Tpf). 2475 */ 2476 #if 0 /* XXX called on interrupt context */ 2477 DELAY_MS(300, sc); 2478 #else 2479 delay(300 * 1000); 2480 #endif 2481 } 2482 2483 /* 2484 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2485 * 2486 * This function detects whether a card is in the slot or not. 2487 * If a card is inserted, return 1. Otherwise, return 0. 2488 */ 2489 STATIC int 2490 pccbb_pcmcia_card_detect(pch) 2491 pcmcia_chipset_handle_t pch; 2492 { 2493 struct pcic_handle *ph = (struct pcic_handle *)pch; 2494 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2495 2496 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2497 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2498 } 2499 2500 #if 0 2501 STATIC int 2502 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2503 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2504 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2505 #endif 2506 /* 2507 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2508 * bus_size_t size, 2509 * struct pcmcia_mem_handle *pcmhp) 2510 * 2511 * This function only allocates memory region for pccard. This 2512 * function never maps the allocated region to pccard memory area. 2513 * 2514 * XXX: Why the argument of start address is not in? 2515 */ 2516 STATIC int 2517 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2518 pcmcia_chipset_handle_t pch; 2519 bus_size_t size; 2520 struct pcmcia_mem_handle *pcmhp; 2521 { 2522 struct pcic_handle *ph = (struct pcic_handle *)pch; 2523 bus_space_handle_t memh; 2524 bus_addr_t addr; 2525 bus_size_t sizepg; 2526 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2527 #if rbus 2528 rbus_tag_t rb; 2529 #endif 2530 2531 /* out of sc->memh, allocate as many pages as necessary */ 2532 2533 /* convert size to PCIC pages */ 2534 /* 2535 * This is not enough; when the requested region is on the page 2536 * boundaries, this may calculate wrong result. 2537 */ 2538 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2539 #if 0 2540 if (sizepg > PCIC_MAX_MEM_PAGES) { 2541 return 1; 2542 } 2543 #endif 2544 2545 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2546 return 1; 2547 } 2548 2549 addr = 0; /* XXX gcc -Wuninitialized */ 2550 2551 #if rbus 2552 rb = sc->sc_rbus_memt; 2553 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2554 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2555 &addr, &memh)) { 2556 return 1; 2557 } 2558 #else 2559 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2560 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2561 0, /* boundary */ 2562 0, /* flags */ 2563 &addr, &memh)) { 2564 return 1; 2565 } 2566 #endif 2567 2568 DPRINTF( 2569 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2570 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2571 2572 pcmhp->memt = sc->sc_memt; 2573 pcmhp->memh = memh; 2574 pcmhp->addr = addr; 2575 pcmhp->size = size; 2576 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2577 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2578 pcmhp->mhandle = 0; 2579 /* No offset??? Funny. */ 2580 2581 return 0; 2582 } 2583 2584 /* 2585 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2586 * struct pcmcia_mem_handle *pcmhp) 2587 * 2588 * This function release the memory space allocated by the function 2589 * pccbb_pcmcia_mem_alloc(). 2590 */ 2591 STATIC void 2592 pccbb_pcmcia_mem_free(pch, pcmhp) 2593 pcmcia_chipset_handle_t pch; 2594 struct pcmcia_mem_handle *pcmhp; 2595 { 2596 #if rbus 2597 struct pcic_handle *ph = (struct pcic_handle *)pch; 2598 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2599 2600 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2601 #else 2602 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2603 #endif 2604 } 2605 2606 /* 2607 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2608 * 2609 * This function release the memory space allocated by the function 2610 * pccbb_pcmcia_mem_alloc(). 2611 */ 2612 STATIC void 2613 pccbb_pcmcia_do_mem_map(ph, win) 2614 struct pcic_handle *ph; 2615 int win; 2616 { 2617 int regbase_win; 2618 bus_addr_t phys_addr; 2619 bus_addr_t phys_end; 2620 2621 #define PCIC_SMM_START_LOW 0 2622 #define PCIC_SMM_START_HIGH 1 2623 #define PCIC_SMM_STOP_LOW 2 2624 #define PCIC_SMM_STOP_HIGH 3 2625 #define PCIC_CMA_LOW 4 2626 #define PCIC_CMA_HIGH 5 2627 2628 u_int8_t start_low, start_high = 0; 2629 u_int8_t stop_low, stop_high; 2630 u_int8_t off_low, off_high; 2631 u_int8_t mem_window; 2632 int reg; 2633 2634 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2635 int mem8 = 2636 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2637 || (kind == PCMCIA_MEM_ATTR); 2638 2639 regbase_win = 0x10 + win * 0x08; 2640 2641 phys_addr = ph->mem[win].addr; 2642 phys_end = phys_addr + ph->mem[win].size; 2643 2644 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2645 phys_addr, phys_end, ph->mem[win].offset)); 2646 2647 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2648 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2649 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2650 2651 /* bit 19:12 */ 2652 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2653 /* bit 23:20 and bit 7 on */ 2654 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2655 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2656 /* bit 31:24, for 32-bit address */ 2657 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2658 2659 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2660 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2661 2662 if (((struct pccbb_softc *)ph-> 2663 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2664 Pcic_write(ph, 0x40 + win, mem_window); 2665 } 2666 2667 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2668 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2669 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2670 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2671 2672 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2673 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2674 2675 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2676 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2677 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2678 | ((kind == PCMCIA_MEM_ATTR) ? 2679 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2680 2681 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2682 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2683 2684 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2685 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2686 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2687 2688 #if defined CBB_DEBUG 2689 { 2690 int r1, r2, r3, r4, r5, r6, r7 = 0; 2691 2692 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2693 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2694 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2695 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2696 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2697 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2698 if (((struct pccbb_softc *)(ph-> 2699 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2700 r7 = Pcic_read(ph, 0x40 + win); 2701 } 2702 2703 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2704 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2705 if (((struct pccbb_softc *)(ph-> 2706 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2707 DPRINTF((" %02x", r7)); 2708 } 2709 DPRINTF(("\n")); 2710 } 2711 #endif 2712 } 2713 2714 /* 2715 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2716 * bus_addr_t card_addr, bus_size_t size, 2717 * struct pcmcia_mem_handle *pcmhp, 2718 * bus_addr_t *offsetp, int *windowp) 2719 * 2720 * This function maps memory space allocated by the function 2721 * pccbb_pcmcia_mem_alloc(). 2722 */ 2723 STATIC int 2724 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2725 pcmcia_chipset_handle_t pch; 2726 int kind; 2727 bus_addr_t card_addr; 2728 bus_size_t size; 2729 struct pcmcia_mem_handle *pcmhp; 2730 bus_addr_t *offsetp; 2731 int *windowp; 2732 { 2733 struct pcic_handle *ph = (struct pcic_handle *)pch; 2734 bus_addr_t busaddr; 2735 long card_offset; 2736 int win; 2737 2738 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2739 if ((ph->memalloc & (1 << win)) == 0) { 2740 ph->memalloc |= (1 << win); 2741 break; 2742 } 2743 } 2744 2745 if (win == PCIC_MEM_WINS) { 2746 return 1; 2747 } 2748 2749 *windowp = win; 2750 2751 /* XXX this is pretty gross */ 2752 2753 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2754 panic("pccbb_pcmcia_mem_map memt is bogus"); 2755 } 2756 2757 busaddr = pcmhp->addr; 2758 2759 /* 2760 * compute the address offset to the pcmcia address space for the 2761 * pcic. this is intentionally signed. The masks and shifts below 2762 * will cause TRT to happen in the pcic registers. Deal with making 2763 * sure the address is aligned, and return the alignment offset. 2764 */ 2765 2766 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2767 card_addr -= *offsetp; 2768 2769 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2770 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2771 (u_long) card_addr)); 2772 2773 /* 2774 * include the offset in the size, and decrement size by one, since 2775 * the hw wants start/stop 2776 */ 2777 size += *offsetp - 1; 2778 2779 card_offset = (((long)card_addr) - ((long)busaddr)); 2780 2781 ph->mem[win].addr = busaddr; 2782 ph->mem[win].size = size; 2783 ph->mem[win].offset = card_offset; 2784 ph->mem[win].kind = kind; 2785 2786 pccbb_pcmcia_do_mem_map(ph, win); 2787 2788 return 0; 2789 } 2790 2791 /* 2792 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2793 * int window) 2794 * 2795 * This function unmaps memory space which mapped by the function 2796 * pccbb_pcmcia_mem_map(). 2797 */ 2798 STATIC void 2799 pccbb_pcmcia_mem_unmap(pch, window) 2800 pcmcia_chipset_handle_t pch; 2801 int window; 2802 { 2803 struct pcic_handle *ph = (struct pcic_handle *)pch; 2804 int reg; 2805 2806 if (window >= PCIC_MEM_WINS) { 2807 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2808 } 2809 2810 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2811 reg &= ~(1 << window); 2812 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2813 2814 ph->memalloc &= ~(1 << window); 2815 } 2816 2817 #if defined PCCBB_PCMCIA_POLL 2818 struct pccbb_poll_str { 2819 void *arg; 2820 int (*func) __P((void *)); 2821 int level; 2822 struct pcic_handle *ph; 2823 int count; 2824 int num; 2825 struct callout poll_ch; 2826 }; 2827 2828 static struct pccbb_poll_str pccbb_poll[10]; 2829 static int pccbb_poll_n = 0; 2830 2831 static void pccbb_pcmcia_poll __P((void *arg)); 2832 2833 static void 2834 pccbb_pcmcia_poll(arg) 2835 void *arg; 2836 { 2837 struct pccbb_poll_str *poll = arg; 2838 struct pcic_handle *ph = poll->ph; 2839 struct pccbb_softc *sc = ph->sc; 2840 int s; 2841 u_int32_t spsr; /* socket present-state reg */ 2842 2843 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2844 switch (poll->level) { 2845 case IPL_NET: 2846 s = splnet(); 2847 break; 2848 case IPL_BIO: 2849 s = splbio(); 2850 break; 2851 case IPL_TTY: /* fallthrough */ 2852 default: 2853 s = spltty(); 2854 break; 2855 } 2856 2857 spsr = 2858 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2859 CB_SOCKET_STAT); 2860 2861 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2862 if (!(spsr & 0x40)) /* CINT low */ 2863 #else 2864 if (1) 2865 #endif 2866 { 2867 if ((*poll->func) (poll->arg) > 0) { 2868 ++poll->count; 2869 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2870 #if defined LEVEL2 2871 } else { 2872 printf("intr: miss! 0x%x\n", spsr); 2873 #endif 2874 } 2875 } 2876 splx(s); 2877 } 2878 #endif /* defined CB_PCMCIA_POLL */ 2879 2880 /* 2881 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2882 * struct pcmcia_function *pf, 2883 * int ipl, 2884 * int (*func)(void *), 2885 * void *arg); 2886 * 2887 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2888 */ 2889 STATIC void * 2890 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2891 pcmcia_chipset_handle_t pch; 2892 struct pcmcia_function *pf; 2893 int ipl; 2894 int (*func) __P((void *)); 2895 void *arg; 2896 { 2897 struct pcic_handle *ph = (struct pcic_handle *)pch; 2898 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2899 2900 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2901 /* what should I do? */ 2902 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2903 DPRINTF( 2904 ("%s does not provide edge nor pulse interrupt\n", 2905 sc->sc_dev.dv_xname)); 2906 return NULL; 2907 } 2908 /* 2909 * XXX Noooooo! The interrupt flag must set properly!! 2910 * dumb pcmcia driver!! 2911 */ 2912 } 2913 2914 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2915 } 2916 2917 /* 2918 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2919 * void *ih) 2920 * 2921 * This function disables PC-Card interrupt. 2922 */ 2923 STATIC void 2924 pccbb_pcmcia_intr_disestablish(pch, ih) 2925 pcmcia_chipset_handle_t pch; 2926 void *ih; 2927 { 2928 struct pcic_handle *ph = (struct pcic_handle *)pch; 2929 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2930 2931 pccbb_intr_disestablish(sc, ih); 2932 } 2933 2934 #if rbus 2935 /* 2936 * static int 2937 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2938 * bus_addr_t addr, bus_size_t size, 2939 * bus_addr_t mask, bus_size_t align, 2940 * int flags, bus_addr_t *addrp; 2941 * bus_space_handle_t *bshp) 2942 * 2943 * This function allocates a portion of memory or io space for 2944 * clients. This function is called from CardBus card drivers. 2945 */ 2946 static int 2947 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2948 cardbus_chipset_tag_t ct; 2949 rbus_tag_t rb; 2950 bus_addr_t addr; 2951 bus_size_t size; 2952 bus_addr_t mask; 2953 bus_size_t align; 2954 int flags; 2955 bus_addr_t *addrp; 2956 bus_space_handle_t *bshp; 2957 { 2958 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2959 2960 DPRINTF( 2961 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2962 addr, size, mask, align)); 2963 2964 if (align == 0) { 2965 align = size; 2966 } 2967 2968 if (rb->rb_bt == sc->sc_memt) { 2969 if (align < 16) { 2970 return 1; 2971 } 2972 if (align < 0x1000) { 2973 align = 0x1000; 2974 } 2975 } else if (rb->rb_bt == sc->sc_iot) { 2976 if (align < 4) { 2977 return 1; 2978 } 2979 /* XXX: hack for avoiding ISA image */ 2980 if (mask < 0x0100) { 2981 mask = 0x3ff; 2982 addr = 0x300; 2983 } 2984 2985 } else { 2986 DPRINTF( 2987 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 2988 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 2989 return 1; 2990 /* XXX: panic here? */ 2991 } 2992 2993 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2994 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2995 return 1; 2996 } 2997 2998 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2999 3000 return 0; 3001 } 3002 3003 /* 3004 * static int 3005 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3006 * bus_space_handle_t *bshp, bus_size_t size); 3007 * 3008 * This function is called from CardBus card drivers. 3009 */ 3010 static int 3011 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3012 cardbus_chipset_tag_t ct; 3013 rbus_tag_t rb; 3014 bus_space_handle_t bsh; 3015 bus_size_t size; 3016 { 3017 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3018 bus_space_tag_t bt = rb->rb_bt; 3019 3020 pccbb_close_win(sc, bt, bsh, size); 3021 3022 if (bt == sc->sc_memt) { 3023 } else if (bt == sc->sc_iot) { 3024 } else { 3025 return 1; 3026 /* XXX: panic here? */ 3027 } 3028 3029 return rbus_space_free(rb, bsh, size, NULL); 3030 } 3031 #endif /* rbus */ 3032 3033 #if rbus 3034 3035 static int 3036 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3037 struct pccbb_softc *sc; 3038 bus_space_tag_t bst; 3039 bus_addr_t addr; 3040 bus_size_t size; 3041 bus_space_handle_t bsh; 3042 int flags; 3043 { 3044 struct pccbb_win_chain_head *head; 3045 bus_addr_t align; 3046 3047 head = &sc->sc_iowindow; 3048 align = 0x04; 3049 if (sc->sc_memt == bst) { 3050 head = &sc->sc_memwindow; 3051 align = 0x1000; 3052 DPRINTF(("using memory window, %x %x %x\n\n", 3053 sc->sc_iot, sc->sc_memt, bst)); 3054 } 3055 3056 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3057 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3058 sc->sc_dev.dv_xname, 3059 (head == &sc->sc_memwindow) ? "mem" : "io"); 3060 } 3061 pccbb_winset(align, sc, bst); 3062 3063 return 0; 3064 } 3065 3066 static int 3067 pccbb_close_win(sc, bst, bsh, size) 3068 struct pccbb_softc *sc; 3069 bus_space_tag_t bst; 3070 bus_space_handle_t bsh; 3071 bus_size_t size; 3072 { 3073 struct pccbb_win_chain_head *head; 3074 bus_addr_t align; 3075 3076 head = &sc->sc_iowindow; 3077 align = 0x04; 3078 if (sc->sc_memt == bst) { 3079 head = &sc->sc_memwindow; 3080 align = 0x1000; 3081 } 3082 3083 if (pccbb_winlist_delete(head, bsh, size)) { 3084 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3085 sc->sc_dev.dv_xname, 3086 (head == &sc->sc_memwindow) ? "mem" : "io"); 3087 } 3088 pccbb_winset(align, sc, bst); 3089 3090 return 0; 3091 } 3092 3093 static int 3094 pccbb_winlist_insert(head, start, size, bsh, flags) 3095 struct pccbb_win_chain_head *head; 3096 bus_addr_t start; 3097 bus_size_t size; 3098 bus_space_handle_t bsh; 3099 int flags; 3100 { 3101 struct pccbb_win_chain *chainp, *elem; 3102 3103 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3104 M_NOWAIT)) == NULL) 3105 return (1); /* fail */ 3106 3107 elem->wc_start = start; 3108 elem->wc_end = start + (size - 1); 3109 elem->wc_handle = bsh; 3110 elem->wc_flags = flags; 3111 3112 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3113 chainp = TAILQ_NEXT(chainp, wc_list)) { 3114 if (chainp->wc_end < start) 3115 continue; 3116 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3117 return (0); 3118 } 3119 3120 TAILQ_INSERT_TAIL(head, elem, wc_list); 3121 return (0); 3122 } 3123 3124 static int 3125 pccbb_winlist_delete(head, bsh, size) 3126 struct pccbb_win_chain_head *head; 3127 bus_space_handle_t bsh; 3128 bus_size_t size; 3129 { 3130 struct pccbb_win_chain *chainp; 3131 3132 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3133 chainp = TAILQ_NEXT(chainp, wc_list)) { 3134 if (chainp->wc_handle != bsh) 3135 continue; 3136 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3137 printf("pccbb_winlist_delete: window 0x%lx size " 3138 "inconsistent: 0x%lx, 0x%lx\n", 3139 (unsigned long)chainp->wc_start, 3140 (unsigned long)(chainp->wc_end - chainp->wc_start), 3141 (unsigned long)(size - 1)); 3142 return 1; 3143 } 3144 3145 TAILQ_REMOVE(head, chainp, wc_list); 3146 free(chainp, M_DEVBUF); 3147 3148 return 0; 3149 } 3150 3151 return 1; /* fail: no candidate to remove */ 3152 } 3153 3154 static void 3155 pccbb_winset(align, sc, bst) 3156 bus_addr_t align; 3157 struct pccbb_softc *sc; 3158 bus_space_tag_t bst; 3159 { 3160 pci_chipset_tag_t pc; 3161 pcitag_t tag; 3162 bus_addr_t mask = ~(align - 1); 3163 struct { 3164 cardbusreg_t win_start; 3165 cardbusreg_t win_limit; 3166 int win_flags; 3167 } win[2]; 3168 struct pccbb_win_chain *chainp; 3169 int offs; 3170 3171 win[0].win_start = win[1].win_start = 0xffffffff; 3172 win[0].win_limit = win[1].win_limit = 0; 3173 win[0].win_flags = win[1].win_flags = 0; 3174 3175 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3176 offs = 0x2c; 3177 if (sc->sc_memt == bst) { 3178 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3179 offs = 0x1c; 3180 } 3181 3182 if (chainp != NULL) { 3183 win[0].win_start = chainp->wc_start & mask; 3184 win[0].win_limit = chainp->wc_end & mask; 3185 win[0].win_flags = chainp->wc_flags; 3186 chainp = TAILQ_NEXT(chainp, wc_list); 3187 } 3188 3189 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3190 if (win[1].win_start == 0xffffffff) { 3191 /* window 1 is not used */ 3192 if ((win[0].win_flags == chainp->wc_flags) && 3193 (win[0].win_limit + align >= 3194 (chainp->wc_start & mask))) { 3195 /* concatenate */ 3196 win[0].win_limit = chainp->wc_end & mask; 3197 } else { 3198 /* make new window */ 3199 win[1].win_start = chainp->wc_start & mask; 3200 win[1].win_limit = chainp->wc_end & mask; 3201 win[1].win_flags = chainp->wc_flags; 3202 } 3203 continue; 3204 } 3205 3206 /* Both windows are engaged. */ 3207 if (win[0].win_flags == win[1].win_flags) { 3208 /* same flags */ 3209 if (win[0].win_flags == chainp->wc_flags) { 3210 if (win[1].win_start - (win[0].win_limit + 3211 align) < 3212 (chainp->wc_start & mask) - 3213 ((chainp->wc_end & mask) + align)) { 3214 /* 3215 * merge window 0 and 1, and set win1 3216 * to chainp 3217 */ 3218 win[0].win_limit = win[1].win_limit; 3219 win[1].win_start = 3220 chainp->wc_start & mask; 3221 win[1].win_limit = 3222 chainp->wc_end & mask; 3223 } else { 3224 win[1].win_limit = 3225 chainp->wc_end & mask; 3226 } 3227 } else { 3228 /* different flags */ 3229 3230 /* concatenate win0 and win1 */ 3231 win[0].win_limit = win[1].win_limit; 3232 /* allocate win[1] to new space */ 3233 win[1].win_start = chainp->wc_start & mask; 3234 win[1].win_limit = chainp->wc_end & mask; 3235 win[1].win_flags = chainp->wc_flags; 3236 } 3237 } else { 3238 /* the flags of win[0] and win[1] is different */ 3239 if (win[0].win_flags == chainp->wc_flags) { 3240 win[0].win_limit = chainp->wc_end & mask; 3241 /* 3242 * XXX this creates overlapping windows, so 3243 * what should the poor bridge do if one is 3244 * cachable, and the other is not? 3245 */ 3246 printf("%s: overlapping windows\n", 3247 sc->sc_dev.dv_xname); 3248 } else { 3249 win[1].win_limit = chainp->wc_end & mask; 3250 } 3251 } 3252 } 3253 3254 pc = sc->sc_pc; 3255 tag = sc->sc_tag; 3256 pci_conf_write(pc, tag, offs, win[0].win_start); 3257 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3258 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3259 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3260 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3261 pci_conf_read(pc, tag, offs), 3262 pci_conf_read(pc, tag, offs + 4) + align, 3263 pci_conf_read(pc, tag, offs + 8), 3264 pci_conf_read(pc, tag, offs + 12) + align)); 3265 3266 if (bst == sc->sc_memt) { 3267 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3268 3269 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3270 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3271 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3272 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3273 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3274 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3275 } 3276 } 3277 3278 #endif /* rbus */ 3279 3280 static void 3281 pccbb_powerhook(why, arg) 3282 int why; 3283 void *arg; 3284 { 3285 struct pccbb_softc *sc = arg; 3286 pcireg_t reg; 3287 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3288 bus_space_handle_t base_memh = sc->sc_base_memh; 3289 3290 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3291 3292 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3293 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3294 if (sc->sc_pil_intr_enable) { 3295 (void)pccbbintr_function(sc); 3296 } 3297 sc->sc_pil_intr_enable = 0; 3298 3299 /* ToDo: deactivate or suspend child devices */ 3300 3301 } 3302 3303 if (why == PWR_RESUME) { 3304 if (sc->sc_pwrmgt_offs != 0) { 3305 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3306 sc->sc_pwrmgt_offs + 4); 3307 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3308 reg & 0x100) { 3309 /* powrstate != D0 */ 3310 3311 printf("%s going back to D0 mode\n", 3312 sc->sc_dev.dv_xname); 3313 reg &= ~PCI_PMCSR_STATE_MASK; 3314 reg |= PCI_PMCSR_STATE_D0; 3315 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3316 pci_conf_write(sc->sc_pc, sc->sc_tag, 3317 sc->sc_pwrmgt_offs + 4, reg); 3318 3319 pci_conf_write(sc->sc_pc, sc->sc_tag, 3320 PCI_SOCKBASE, sc->sc_sockbase); 3321 pci_conf_write(sc->sc_pc, sc->sc_tag, 3322 PCI_BUSNUM, sc->sc_busnum); 3323 pccbb_chipinit(sc); 3324 /* setup memory and io space window for CB */ 3325 pccbb_winset(0x1000, sc, sc->sc_memt); 3326 pccbb_winset(0x04, sc, sc->sc_iot); 3327 } 3328 } 3329 3330 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3331 /* BIOS did not recover this register */ 3332 pci_conf_write (sc->sc_pc, sc->sc_tag, 3333 PCI_SOCKBASE, sc->sc_sockbase); 3334 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3335 /* BIOS did not recover this register */ 3336 pci_conf_write (sc->sc_pc, sc->sc_tag, 3337 PCI_BUSNUM, sc->sc_busnum); 3338 /* CSC Interrupt: Card detect interrupt on */ 3339 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3340 /* Card detect intr is turned on. */ 3341 reg |= CB_SOCKET_MASK_CD; 3342 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3343 /* reset interrupt */ 3344 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3345 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3346 3347 /* 3348 * check for card insertion or removal during suspend period. 3349 * XXX: the code can't cope with card swap (remove then 3350 * insert). how can we detect such situation? 3351 */ 3352 (void)pccbbintr(sc); 3353 3354 sc->sc_pil_intr_enable = 1; 3355 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3356 3357 /* ToDo: activate or wakeup child devices */ 3358 } 3359 } 3360
Indexes created Fri Sep 26 20:09:58 GMT 2025