pccbb.c revision 1.77
1 /* $NetBSD: pccbb.c,v 1.77 2002/05/31 13:34:03 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.77 2002/05/31 13:34:03 mycroft Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 struct cfattach cbb_pci_ca = { 230 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 231 }; 232 233 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 234 pccbb_pcmcia_mem_alloc, 235 pccbb_pcmcia_mem_free, 236 pccbb_pcmcia_mem_map, 237 pccbb_pcmcia_mem_unmap, 238 pccbb_pcmcia_io_alloc, 239 pccbb_pcmcia_io_free, 240 pccbb_pcmcia_io_map, 241 pccbb_pcmcia_io_unmap, 242 pccbb_pcmcia_intr_establish, 243 pccbb_pcmcia_intr_disestablish, 244 pccbb_pcmcia_socket_enable, 245 pccbb_pcmcia_socket_disable, 246 pccbb_pcmcia_card_detect 247 }; 248 249 #if rbus 250 static struct cardbus_functions pccbb_funcs = { 251 pccbb_rbus_cb_space_alloc, 252 pccbb_rbus_cb_space_free, 253 pccbb_cb_intr_establish, 254 pccbb_cb_intr_disestablish, 255 pccbb_ctrl, 256 pccbb_power, 257 pccbb_make_tag, 258 pccbb_free_tag, 259 pccbb_conf_read, 260 pccbb_conf_write, 261 }; 262 #else 263 static struct cardbus_functions pccbb_funcs = { 264 pccbb_ctrl, 265 pccbb_power, 266 pccbb_mem_open, 267 pccbb_mem_close, 268 pccbb_io_open, 269 pccbb_io_close, 270 pccbb_cb_intr_establish, 271 pccbb_cb_intr_disestablish, 272 pccbb_make_tag, 273 pccbb_conf_read, 274 pccbb_conf_write, 275 }; 276 #endif 277 278 int 279 pcicbbmatch(parent, match, aux) 280 struct device *parent; 281 struct cfdata *match; 282 void *aux; 283 { 284 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 285 286 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 287 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 288 PCI_INTERFACE(pa->pa_class) == 0) { 289 return 1; 290 } 291 292 return 0; 293 } 294 295 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 296 | ((prod) << PCI_PRODUCT_SHIFT)) 297 298 const struct yenta_chipinfo { 299 pcireg_t yc_id; /* vendor tag | product tag */ 300 int yc_chiptype; 301 int yc_flags; 302 } yc_chipsets[] = { 303 /* Texas Instruments chips */ 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 319 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 321 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 323 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 325 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 327 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 329 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 330 331 /* Ricoh chips */ 332 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 333 PCCBB_PCMCIA_MEM_32}, 334 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 335 PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 337 PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 339 PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 341 PCCBB_PCMCIA_MEM_32}, 342 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 343 PCCBB_PCMCIA_MEM_32}, 344 345 /* Toshiba products */ 346 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 347 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 348 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 349 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 350 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 351 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 353 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 354 355 /* Cirrus Logic products */ 356 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 357 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 359 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 360 361 /* sentinel, or Generic chip */ 362 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 363 }; 364 365 static int 366 cb_chipset(pci_id, flagp) 367 u_int32_t pci_id; 368 int *flagp; 369 { 370 const struct yenta_chipinfo *yc; 371 372 /* Loop over except the last default entry. */ 373 for (yc = yc_chipsets; yc < yc_chipsets + 374 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 375 if (pci_id == yc->yc_id) 376 break; 377 378 if (flagp != NULL) 379 *flagp = yc->yc_flags; 380 381 return (yc->yc_chiptype); 382 } 383 384 static void 385 pccbb_shutdown(void *arg) 386 { 387 struct pccbb_softc *sc = arg; 388 pcireg_t command; 389 390 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 391 392 /* 393 * turn off power 394 * 395 * XXX - do not turn off power if chipset is TI 113X because 396 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 397 */ 398 if (sc->sc_chipset != CB_TI113X) { 399 pccbb_power((cardbus_chipset_tag_t)sc, 400 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 401 } 402 403 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 404 0); 405 406 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 407 408 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 409 PCI_COMMAND_MASTER_ENABLE); 410 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 411 412 } 413 414 void 415 pccbbattach(parent, self, aux) 416 struct device *parent; 417 struct device *self; 418 void *aux; 419 { 420 struct pccbb_softc *sc = (void *)self; 421 struct pci_attach_args *pa = aux; 422 pci_chipset_tag_t pc = pa->pa_pc; 423 pcireg_t busreg, reg, sock_base; 424 bus_addr_t sockbase; 425 char devinfo[256]; 426 int flags; 427 int pwrmgt_offs; 428 429 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 430 431 pci_devinfo(pa->pa_id, 0, 0, devinfo); 432 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 433 #ifdef CBB_DEBUG 434 printf(" (chipflags %x)", flags); 435 #endif 436 printf("\n"); 437 438 TAILQ_INIT(&sc->sc_memwindow); 439 TAILQ_INIT(&sc->sc_iowindow); 440 441 #if rbus 442 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 443 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 444 445 #if 0 446 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 447 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 448 #endif 449 #endif /* rbus */ 450 451 sc->sc_base_memh = 0; 452 453 /* power management: set D0 state */ 454 sc->sc_pwrmgt_offs = 0; 455 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 456 &pwrmgt_offs, 0)) { 457 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + 4); 458 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 459 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 460 reg &= ~PCI_PMCSR_STATE_MASK; 461 reg |= PCI_PMCSR_STATE_D0; 462 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 463 pci_conf_write(pc, pa->pa_tag, pwrmgt_offs + 4, reg); 464 } 465 466 sc->sc_pwrmgt_offs = pwrmgt_offs; 467 } 468 469 /* 470 * MAP socket registers and ExCA registers on memory-space 471 * When no valid address is set on socket base registers (on pci 472 * config space), get it not polite way. 473 */ 474 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 475 476 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 477 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 478 /* The address must be valid. */ 479 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 480 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 481 printf("%s: can't map socket base address 0x%x\n", 482 sc->sc_dev.dv_xname, sock_base); 483 /* 484 * I think it's funny: socket base registers must be 485 * mapped on memory space, but ... 486 */ 487 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 488 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 489 NULL)) { 490 printf("%s: can't map socket base address" 491 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 492 (unsigned long)sockbase); 493 /* give up... allocate reg space via rbus. */ 494 sc->sc_base_memh = 0; 495 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 496 } 497 } else { 498 DPRINTF(("%s: socket base address 0x%lx\n", 499 sc->sc_dev.dv_xname, sockbase)); 500 } 501 } 502 503 sc->sc_mem_start = 0; /* XXX */ 504 sc->sc_mem_end = 0xffffffff; /* XXX */ 505 506 /* 507 * When interrupt isn't routed correctly, give up probing cbb and do 508 * not kill pcic-compatible port. 509 */ 510 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 511 printf("%s: NOT USED because of unconfigured interrupt\n", 512 sc->sc_dev.dv_xname); 513 return; 514 } 515 516 /* 517 * When bus number isn't set correctly, give up using 32-bit CardBus 518 * mode. 519 */ 520 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 521 #if notyet 522 if (((busreg >> 8) & 0xff) == 0) { 523 printf("%s: CardBus support disabled because of unconfigured bus number\n", 524 sc->sc_dev.dv_xname); 525 flags |= PCCBB_PCMCIA_16BITONLY; 526 } 527 #endif 528 529 /* pccbb_machdep.c end */ 530 531 #if defined CBB_DEBUG 532 { 533 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 534 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 535 intrname[pa->pa_intrpin], pa->pa_intrline); 536 } 537 #endif 538 539 /* setup softc */ 540 sc->sc_pc = pc; 541 sc->sc_iot = pa->pa_iot; 542 sc->sc_memt = pa->pa_memt; 543 sc->sc_dmat = pa->pa_dmat; 544 sc->sc_tag = pa->pa_tag; 545 sc->sc_function = pa->pa_function; 546 sc->sc_sockbase = sock_base; 547 sc->sc_busnum = busreg; 548 549 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 550 551 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 552 553 shutdownhook_establish(pccbb_shutdown, sc); 554 555 /* Disable legacy register mapping. */ 556 switch (sc->sc_chipset) { 557 case CB_RX5C46X: /* fallthrough */ 558 #if 0 559 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 560 case CB_RX5C47X: 561 #endif 562 /* 563 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 564 * cannot be disabled by substituting 0 into PCI_LEGACY 565 * register. Ricoh CardBus bridges have special bits on Bridge 566 * control reg (addr 0x3e on PCI config space). 567 */ 568 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 569 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 570 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 571 break; 572 573 default: 574 /* XXX I don't know proper way to kill legacy I/O. */ 575 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 576 break; 577 } 578 579 config_defer(self, pccbb_pci_callback); 580 } 581 582 583 584 585 /* 586 * static void pccbb_pci_callback(struct device *self) 587 * 588 * The actual attach routine: get memory space for YENTA register 589 * space, setup YENTA register and route interrupt. 590 * 591 * This function should be deferred because this device may obtain 592 * memory space dynamically. This function must avoid obtaining 593 * memory area which has already kept for another device. 594 */ 595 static void 596 pccbb_pci_callback(self) 597 struct device *self; 598 { 599 struct pccbb_softc *sc = (void *)self; 600 pci_chipset_tag_t pc = sc->sc_pc; 601 pci_intr_handle_t ih; 602 const char *intrstr = NULL; 603 bus_addr_t sockbase; 604 struct cbslot_attach_args cba; 605 struct pcmciabus_attach_args paa; 606 struct cardslot_attach_args caa; 607 struct cardslot_softc *csc; 608 609 if (0 == sc->sc_base_memh) { 610 /* The socket registers aren't mapped correctly. */ 611 #if rbus 612 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 613 (sc->sc_chipset == CB_RX5C47X 614 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 615 0, &sockbase, &sc->sc_base_memh)) { 616 return; 617 } 618 sc->sc_base_memt = sc->sc_memt; 619 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 620 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 621 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 622 PCI_SOCKBASE))); 623 #else 624 sc->sc_base_memt = sc->sc_memt; 625 #if !defined CBB_PCI_BASE 626 #define CBB_PCI_BASE 0x20000000 627 #endif 628 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 629 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 630 /* cannot allocate memory space */ 631 return; 632 } 633 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 634 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 635 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 636 sc->sc_tag, PCI_SOCKBASE))); 637 sc->sc_sockbase = sockbase; 638 #endif 639 } 640 641 /* bus bridge initialization */ 642 pccbb_chipinit(sc); 643 644 /* clear data structure for child device interrupt handlers */ 645 sc->sc_pil = NULL; 646 sc->sc_pil_intr_enable = 1; 647 648 /* Map and establish the interrupt. */ 649 if (pci_intr_map(&sc->sc_pa, &ih)) { 650 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 651 return; 652 } 653 intrstr = pci_intr_string(pc, ih); 654 655 /* 656 * XXX pccbbintr should be called under the priority lower 657 * than any other hard interrputs. 658 */ 659 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 660 661 if (sc->sc_ih == NULL) { 662 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 663 if (intrstr != NULL) { 664 printf(" at %s", intrstr); 665 } 666 printf("\n"); 667 return; 668 } 669 670 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 671 powerhook_establish(pccbb_powerhook, sc); 672 673 { 674 u_int32_t sockstat; 675 676 sockstat = bus_space_read_4(sc->sc_base_memt, 677 sc->sc_base_memh, CB_SOCKET_STAT); 678 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 679 sc->sc_flags |= CBB_CARDEXIST; 680 } 681 } 682 683 /* 684 * attach cardbus 685 */ 686 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 687 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 688 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 689 690 /* initialize cbslot_attach */ 691 cba.cba_busname = "cardbus"; 692 cba.cba_iot = sc->sc_iot; 693 cba.cba_memt = sc->sc_memt; 694 cba.cba_dmat = sc->sc_dmat; 695 cba.cba_bus = (busreg >> 8) & 0x0ff; 696 cba.cba_cc = (void *)sc; 697 cba.cba_cf = &pccbb_funcs; 698 cba.cba_intrline = sc->sc_pa.pa_intrline; 699 700 #if rbus 701 cba.cba_rbus_iot = sc->sc_rbus_iot; 702 cba.cba_rbus_memt = sc->sc_rbus_memt; 703 #endif 704 705 cba.cba_cacheline = PCI_CACHELINE(bhlc); 706 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 707 708 if (bootverbose) { 709 printf("%s: cacheline 0x%x lattimer 0x%x\n", 710 sc->sc_dev.dv_xname, cba.cba_cacheline, 711 cba.cba_lattimer); 712 printf("%s: bhlc 0x%x lscp 0x%x\n", 713 sc->sc_dev.dv_xname, bhlc, busreg); 714 } 715 #if defined SHOW_REGS 716 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 717 sc->sc_base_memh); 718 #endif 719 } 720 721 pccbb_pcmcia_attach_setup(sc, &paa); 722 caa.caa_cb_attach = NULL; 723 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 724 caa.caa_cb_attach = &cba; 725 } 726 caa.caa_16_attach = &paa; 727 caa.caa_ph = &sc->sc_pcmcia_h; 728 729 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 730 DPRINTF(("pccbbattach: found cardslot\n")); 731 sc->sc_csc = csc; 732 } 733 734 return; 735 } 736 737 738 739 740 741 /* 742 * static void pccbb_chipinit(struct pccbb_softc *sc) 743 * 744 * This function initialize YENTA chip registers listed below: 745 * 1) PCI command reg, 746 * 2) PCI and CardBus latency timer, 747 * 3) route PCI interrupt, 748 * 4) close all memory and io windows. 749 * 5) turn off bus power. 750 * 6) card detect interrupt on. 751 * 7) clear interrupt 752 */ 753 static void 754 pccbb_chipinit(sc) 755 struct pccbb_softc *sc; 756 { 757 pci_chipset_tag_t pc = sc->sc_pc; 758 pcitag_t tag = sc->sc_tag; 759 bus_space_tag_t bmt = sc->sc_base_memt; 760 bus_space_handle_t bmh = sc->sc_base_memh; 761 pcireg_t reg; 762 763 /* 764 * Set PCI command reg. 765 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 766 */ 767 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 768 /* I believe it is harmless. */ 769 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 770 PCI_COMMAND_MASTER_ENABLE); 771 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 772 773 /* 774 * Set CardBus latency timer. 775 */ 776 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 777 if (PCI_CB_LATENCY(reg) < 0x20) { 778 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 779 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 780 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 781 } 782 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 783 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 784 785 /* 786 * Set PCI latency timer. 787 */ 788 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 789 if (PCI_LATTIMER(reg) < 0x10) { 790 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 791 reg |= (0x10 << PCI_LATTIMER_SHIFT); 792 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 793 } 794 DPRINTF(("PCI latency timer 0x%x (%x)\n", 795 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 796 797 798 /* Route functional interrupts to PCI. */ 799 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 800 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 801 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 802 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 803 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 804 805 switch (sc->sc_chipset) { 806 case CB_TI113X: 807 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 808 /* This bit is shared, but may read as 0 on some chips, so set 809 it explicitly on both functions. */ 810 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 811 /* CSC intr enable */ 812 reg |= PCI113X_CBCTRL_PCI_CSC; 813 /* functional intr prohibit | prohibit ISA routing */ 814 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 815 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 816 break; 817 818 case CB_TI12XX: 819 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 820 reg |= PCI12XX_SYSCTRL_VCCPROT; 821 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 822 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 823 reg |= PCI12XX_CBCTRL_CSC; 824 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 825 break; 826 827 case CB_TOPIC95B: 828 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 829 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 830 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 831 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 832 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 833 sc->sc_dev.dv_xname, reg)); 834 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 835 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 836 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 837 DPRINTF(("0x%x\n", reg)); 838 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 839 break; 840 841 case CB_TOPIC97: 842 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 843 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 844 sc->sc_dev.dv_xname, reg)); 845 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 846 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 847 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 848 reg |= TOPIC97_SLOT_CTRL_PCIINT; 849 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 850 DPRINTF(("0x%x\n", reg)); 851 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 852 /* make sure to assert LV card support bits */ 853 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 854 0x800 + 0x3e, 855 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 856 0x800 + 0x3e) | 0x03); 857 break; 858 } 859 860 /* Close all memory and I/O windows. */ 861 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 862 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 863 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 864 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 865 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 866 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 867 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 868 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 869 870 /* reset 16-bit pcmcia bus */ 871 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 872 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 873 874 /* turn off power */ 875 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 876 877 /* CSC Interrupt: Card detect interrupt on */ 878 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 879 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 880 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 881 /* reset interrupt */ 882 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 883 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 884 } 885 886 887 888 889 /* 890 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 891 * struct pcmciabus_attach_args *paa) 892 * 893 * This function attaches 16-bit PCcard bus. 894 */ 895 STATIC void 896 pccbb_pcmcia_attach_setup(sc, paa) 897 struct pccbb_softc *sc; 898 struct pcmciabus_attach_args *paa; 899 { 900 struct pcic_handle *ph = &sc->sc_pcmcia_h; 901 #if rbus 902 rbus_tag_t rb; 903 #endif 904 905 /* initialize pcmcia part in pccbb_softc */ 906 ph->ph_parent = (struct device *)sc; 907 ph->sock = sc->sc_function; 908 ph->flags = 0; 909 ph->shutdown = 0; 910 ph->ih_irq = sc->sc_pa.pa_intrline; 911 ph->ph_bus_t = sc->sc_base_memt; 912 ph->ph_bus_h = sc->sc_base_memh; 913 ph->ph_read = pccbb_pcmcia_read; 914 ph->ph_write = pccbb_pcmcia_write; 915 sc->sc_pct = &pccbb_pcmcia_funcs; 916 917 /* 918 * We need to do a few things here: 919 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 920 * setting the IRQ numbers to 0. 921 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 922 * routing of CSC interrupts (e.g. card removal) to PCI while in 923 * PCMCIA mode. We just leave this set all the time. 924 * 3) Enable card insertion/removal interrupts in case the chip also 925 * needs that while in PCMCIA mode. 926 * 4) Clear any pending CSC interrupt. 927 */ 928 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 929 if (sc->sc_chipset == CB_TI113X) { 930 Pcic_write(ph, PCIC_CSC_INTR, 0); 931 } else { 932 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 933 Pcic_read(ph, PCIC_CSC); 934 } 935 936 /* initialize pcmcia bus attachment */ 937 paa->paa_busname = "pcmcia"; 938 paa->pct = sc->sc_pct; 939 paa->pch = ph; 940 paa->iobase = 0; /* I don't use them */ 941 paa->iosize = 0; 942 #if rbus 943 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 944 paa->iobase = rb->rb_start + rb->rb_offset; 945 paa->iosize = rb->rb_end - rb->rb_start; 946 #endif 947 948 return; 949 } 950 951 #if 0 952 STATIC void 953 pccbb_pcmcia_attach_card(ph) 954 struct pcic_handle *ph; 955 { 956 if (ph->flags & PCIC_FLAG_CARDP) { 957 panic("pccbb_pcmcia_attach_card: already attached"); 958 } 959 960 /* call the MI attach function */ 961 pcmcia_card_attach(ph->pcmcia); 962 963 ph->flags |= PCIC_FLAG_CARDP; 964 } 965 966 STATIC void 967 pccbb_pcmcia_detach_card(ph, flags) 968 struct pcic_handle *ph; 969 int flags; 970 { 971 if (!(ph->flags & PCIC_FLAG_CARDP)) { 972 panic("pccbb_pcmcia_detach_card: already detached"); 973 } 974 975 ph->flags &= ~PCIC_FLAG_CARDP; 976 977 /* call the MI detach function */ 978 pcmcia_card_detach(ph->pcmcia, flags); 979 } 980 #endif 981 982 /* 983 * int pccbbintr(arg) 984 * void *arg; 985 * This routine handles the interrupt from Yenta PCI-CardBus bridge 986 * itself. 987 */ 988 int 989 pccbbintr(arg) 990 void *arg; 991 { 992 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 993 u_int32_t sockevent, sockstate; 994 bus_space_tag_t memt = sc->sc_base_memt; 995 bus_space_handle_t memh = sc->sc_base_memh; 996 struct pcic_handle *ph = &sc->sc_pcmcia_h; 997 998 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 999 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1000 Pcic_read(ph, PCIC_CSC); 1001 1002 if (sockevent == 0) { 1003 /* This intr is not for me: it may be for my child devices. */ 1004 if (sc->sc_pil_intr_enable) { 1005 return pccbbintr_function(sc); 1006 } else { 1007 return 0; 1008 } 1009 } 1010 1011 if (sockevent & CB_SOCKET_EVENT_CD) { 1012 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1013 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 1014 /* A card should be removed. */ 1015 if (sc->sc_flags & CBB_CARDEXIST) { 1016 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1017 sockevent)); 1018 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1019 sc->sc_flags &= ~CBB_CARDEXIST; 1020 if (sc->sc_csc->sc_status & 1021 CARDSLOT_STATUS_CARD_16) { 1022 #if 0 1023 struct pcic_handle *ph = 1024 &sc->sc_pcmcia_h; 1025 1026 pcmcia_card_deactivate(ph->pcmcia); 1027 pccbb_pcmcia_socket_disable(ph); 1028 pccbb_pcmcia_detach_card(ph, 1029 DETACH_FORCE); 1030 #endif 1031 cardslot_event_throw(sc->sc_csc, 1032 CARDSLOT_EVENT_REMOVAL_16); 1033 } else if (sc->sc_csc->sc_status & 1034 CARDSLOT_STATUS_CARD_CB) { 1035 /* Cardbus intr removed */ 1036 cardslot_event_throw(sc->sc_csc, 1037 CARDSLOT_EVENT_REMOVAL_CB); 1038 } 1039 } else if (sc->sc_flags & CBB_INSERTING) { 1040 sc->sc_flags &= ~CBB_INSERTING; 1041 callout_stop(&sc->sc_insert_ch); 1042 } 1043 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1044 /* 1045 * The pccbbintr may called from powerdown hook when 1046 * the system resumed, to detect the card 1047 * insertion/removal during suspension. 1048 */ 1049 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1050 if (sc->sc_flags & CBB_INSERTING) { 1051 callout_stop(&sc->sc_insert_ch); 1052 } 1053 callout_reset(&sc->sc_insert_ch, hz / 5, 1054 pci113x_insert, sc); 1055 sc->sc_flags |= CBB_INSERTING; 1056 } 1057 } 1058 1059 return (1); 1060 } 1061 1062 /* 1063 * static int pccbbintr_function(struct pccbb_softc *sc) 1064 * 1065 * This function calls each interrupt handler registered at the 1066 * bridge. The interrupt handlers are called in registered order. 1067 */ 1068 static int 1069 pccbbintr_function(sc) 1070 struct pccbb_softc *sc; 1071 { 1072 int retval = 0, val; 1073 struct pccbb_intrhand_list *pil; 1074 int s, splchanged; 1075 1076 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1077 /* 1078 * XXX priority change. gross. I use if-else 1079 * sentense instead of switch-case sentense because of 1080 * avoiding duplicate case value error. More than one 1081 * IPL_XXX use same value. It depends on 1082 * implimentation. 1083 */ 1084 splchanged = 1; 1085 if (pil->pil_level == IPL_SERIAL) { 1086 s = splserial(); 1087 } else if (pil->pil_level == IPL_HIGH) { 1088 s = splhigh(); 1089 } else if (pil->pil_level == IPL_CLOCK) { 1090 s = splclock(); 1091 } else if (pil->pil_level == IPL_AUDIO) { 1092 s = splaudio(); 1093 } else if (pil->pil_level == IPL_IMP) { 1094 s = splvm(); /* XXX */ 1095 } else if (pil->pil_level == IPL_TTY) { 1096 s = spltty(); 1097 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1098 s = splsoftserial(); 1099 } else if (pil->pil_level == IPL_NET) { 1100 s = splnet(); 1101 } else { 1102 splchanged = 0; 1103 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1104 } 1105 1106 val = (*pil->pil_func)(pil->pil_arg); 1107 1108 if (splchanged != 0) { 1109 splx(s); 1110 } 1111 1112 retval = retval == 1 ? 1 : 1113 retval == 0 ? val : val != 0 ? val : retval; 1114 } 1115 1116 return retval; 1117 } 1118 1119 static void 1120 pci113x_insert(arg) 1121 void *arg; 1122 { 1123 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1124 u_int32_t sockevent, sockstate; 1125 1126 if (!(sc->sc_flags & CBB_INSERTING)) { 1127 /* We add a card only under inserting state. */ 1128 return; 1129 } 1130 sc->sc_flags &= ~CBB_INSERTING; 1131 1132 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1133 CB_SOCKET_EVENT); 1134 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1135 CB_SOCKET_STAT); 1136 1137 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1138 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1139 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1140 sc->sc_flags |= CBB_CARDEXIST; 1141 /* call pccard interrupt handler here */ 1142 if (sockstate & CB_SOCKET_STAT_16BIT) { 1143 /* 16-bit card found */ 1144 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1145 cardslot_event_throw(sc->sc_csc, 1146 CARDSLOT_EVENT_INSERTION_16); 1147 } else if (sockstate & CB_SOCKET_STAT_CB) { 1148 /* cardbus card found */ 1149 /* cardbus_attach_card(sc->sc_csc); */ 1150 cardslot_event_throw(sc->sc_csc, 1151 CARDSLOT_EVENT_INSERTION_CB); 1152 } else { 1153 /* who are you? */ 1154 } 1155 } else { 1156 callout_reset(&sc->sc_insert_ch, hz / 10, 1157 pci113x_insert, sc); 1158 } 1159 } 1160 1161 #define PCCBB_PCMCIA_OFFSET 0x800 1162 static u_int8_t 1163 pccbb_pcmcia_read(ph, reg) 1164 struct pcic_handle *ph; 1165 int reg; 1166 { 1167 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1168 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1169 1170 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1171 PCCBB_PCMCIA_OFFSET + reg); 1172 } 1173 1174 static void 1175 pccbb_pcmcia_write(ph, reg, val) 1176 struct pcic_handle *ph; 1177 int reg; 1178 u_int8_t val; 1179 { 1180 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1181 val); 1182 1183 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1184 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1185 } 1186 1187 /* 1188 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1189 */ 1190 STATIC int 1191 pccbb_ctrl(ct, command) 1192 cardbus_chipset_tag_t ct; 1193 int command; 1194 { 1195 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1196 1197 switch (command) { 1198 case CARDBUS_CD: 1199 if (2 == pccbb_detect_card(sc)) { 1200 int retval = 0; 1201 int status = cb_detect_voltage(sc); 1202 if (PCCARD_VCC_5V & status) { 1203 retval |= CARDBUS_5V_CARD; 1204 } 1205 if (PCCARD_VCC_3V & status) { 1206 retval |= CARDBUS_3V_CARD; 1207 } 1208 if (PCCARD_VCC_XV & status) { 1209 retval |= CARDBUS_XV_CARD; 1210 } 1211 if (PCCARD_VCC_YV & status) { 1212 retval |= CARDBUS_YV_CARD; 1213 } 1214 return retval; 1215 } else { 1216 return 0; 1217 } 1218 break; 1219 case CARDBUS_RESET: 1220 return cb_reset(sc); 1221 break; 1222 case CARDBUS_IO_ENABLE: /* fallthrough */ 1223 case CARDBUS_IO_DISABLE: /* fallthrough */ 1224 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1225 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1226 case CARDBUS_BM_ENABLE: /* fallthrough */ 1227 case CARDBUS_BM_DISABLE: /* fallthrough */ 1228 /* XXX: I think we don't need to call this function below. */ 1229 return pccbb_cardenable(sc, command); 1230 break; 1231 } 1232 1233 return 0; 1234 } 1235 1236 /* 1237 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1238 * This function returns true when it succeeds and returns false when 1239 * it fails. 1240 */ 1241 STATIC int 1242 pccbb_power(ct, command) 1243 cardbus_chipset_tag_t ct; 1244 int command; 1245 { 1246 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1247 1248 u_int32_t status, sock_ctrl, reg_ctrl; 1249 bus_space_tag_t memt = sc->sc_base_memt; 1250 bus_space_handle_t memh = sc->sc_base_memh; 1251 1252 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1253 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1254 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1258 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1259 "UNKNOWN", 1260 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1261 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1263 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1264 "UNKNOWN", command)); 1265 1266 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1267 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1268 1269 switch (command & CARDBUS_VCCMASK) { 1270 case CARDBUS_VCC_UC: 1271 break; 1272 case CARDBUS_VCC_5V: 1273 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1274 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1275 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1276 } else { 1277 printf("%s: BAD voltage request: no 5 V card\n", 1278 sc->sc_dev.dv_xname); 1279 } 1280 break; 1281 case CARDBUS_VCC_3V: 1282 if (CB_SOCKET_STAT_3VCARD & status) { 1283 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1284 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1285 } else { 1286 printf("%s: BAD voltage request: no 3.3 V card\n", 1287 sc->sc_dev.dv_xname); 1288 } 1289 break; 1290 case CARDBUS_VCC_0V: 1291 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1292 break; 1293 default: 1294 return 0; /* power NEVER changed */ 1295 break; 1296 } 1297 1298 switch (command & CARDBUS_VPPMASK) { 1299 case CARDBUS_VPP_UC: 1300 break; 1301 case CARDBUS_VPP_0V: 1302 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1303 break; 1304 case CARDBUS_VPP_VCC: 1305 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1306 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1307 break; 1308 case CARDBUS_VPP_12V: 1309 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1310 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1311 break; 1312 } 1313 1314 #if 0 1315 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1316 #endif 1317 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1318 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1319 1320 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1321 printf 1322 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1323 sc->sc_dev.dv_xname, sock_ctrl, status); 1324 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1325 (command & CARDBUS_VCCMASK) == 1326 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1327 CARDBUS_VCCMASK) == 1328 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1329 CARDBUS_VCCMASK) == 1330 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1331 CARDBUS_VCCMASK) == 1332 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1333 CARDBUS_VCCMASK) == 1334 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1335 CARDBUS_VCCMASK) == 1336 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1337 (command & CARDBUS_VPPMASK) == 1338 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1339 CARDBUS_VPPMASK) == 1340 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1341 CARDBUS_VPPMASK) == 1342 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1343 CARDBUS_VPPMASK) == 1344 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1345 #if 0 1346 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1347 u_int32_t force = 1348 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1349 /* Reset Bad Vcc request */ 1350 force &= ~CB_SOCKET_FORCE_BADVCC; 1351 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1352 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1353 CB_SOCKET_STAT)); 1354 return 1; 1355 } 1356 #endif 1357 return 0; 1358 } 1359 1360 if (sc->sc_chipset == CB_TOPIC97) { 1361 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1362 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1363 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1364 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1365 else 1366 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1367 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1368 } 1369 1370 /* 1371 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1372 * time is 20 ms, some PC-Card bridge requires longer duration. 1373 */ 1374 #if 0 /* XXX called on interrupt context */ 1375 DELAY_MS(300, sc); 1376 #else 1377 delay(300 * 1000); 1378 #endif 1379 1380 return 1; /* power changed correctly */ 1381 } 1382 1383 #if defined CB_PCMCIA_POLL 1384 struct cb_poll_str { 1385 void *arg; 1386 int (*func) __P((void *)); 1387 int level; 1388 pccard_chipset_tag_t ct; 1389 int count; 1390 struct callout poll_ch; 1391 }; 1392 1393 static struct cb_poll_str cb_poll[10]; 1394 static int cb_poll_n = 0; 1395 1396 static void cb_pcmcia_poll __P((void *arg)); 1397 1398 static void 1399 cb_pcmcia_poll(arg) 1400 void *arg; 1401 { 1402 struct cb_poll_str *poll = arg; 1403 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1404 struct pccbb_softc *sc = psc->cpc_parent; 1405 int s; 1406 u_int32_t spsr; /* socket present-state reg */ 1407 1408 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1409 switch (poll->level) { 1410 case IPL_NET: 1411 s = splnet(); 1412 break; 1413 case IPL_BIO: 1414 s = splbio(); 1415 break; 1416 case IPL_TTY: /* fallthrough */ 1417 default: 1418 s = spltty(); 1419 break; 1420 } 1421 1422 spsr = 1423 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1424 CB_SOCKET_STAT); 1425 1426 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1427 if (!(spsr & 0x40)) { /* CINT low */ 1428 #else 1429 if (1) { 1430 #endif 1431 if ((*poll->func) (poll->arg) == 1) { 1432 ++poll->count; 1433 printf("intr: reported from poller, 0x%x\n", spsr); 1434 #if defined LEVEL2 1435 } else { 1436 printf("intr: miss! 0x%x\n", spsr); 1437 #endif 1438 } 1439 } 1440 splx(s); 1441 } 1442 #endif /* defined CB_PCMCIA_POLL */ 1443 1444 /* 1445 * static int pccbb_detect_card(struct pccbb_softc *sc) 1446 * return value: 0 if no card exists. 1447 * 1 if 16-bit card exists. 1448 * 2 if cardbus card exists. 1449 */ 1450 static int 1451 pccbb_detect_card(sc) 1452 struct pccbb_softc *sc; 1453 { 1454 bus_space_handle_t base_memh = sc->sc_base_memh; 1455 bus_space_tag_t base_memt = sc->sc_base_memt; 1456 u_int32_t sockstat = 1457 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1458 int retval = 0; 1459 1460 /* CD1 and CD2 asserted */ 1461 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1462 /* card must be present */ 1463 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1464 /* NOTACARD DEASSERTED */ 1465 if (CB_SOCKET_STAT_CB & sockstat) { 1466 /* CardBus mode */ 1467 retval = 2; 1468 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1469 /* 16-bit mode */ 1470 retval = 1; 1471 } 1472 } 1473 } 1474 return retval; 1475 } 1476 1477 /* 1478 * STATIC int cb_reset(struct pccbb_softc *sc) 1479 * This function resets CardBus card. 1480 */ 1481 STATIC int 1482 cb_reset(sc) 1483 struct pccbb_softc *sc; 1484 { 1485 /* 1486 * Reset Assert at least 20 ms 1487 * Some machines request longer duration. 1488 */ 1489 int reset_duration = 1490 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1491 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1492 1493 /* Reset bit Assert (bit 6 at 0x3E) */ 1494 bcr |= CB_BCR_RESET_ENABLE; 1495 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1496 DELAY_MS(reset_duration, sc); 1497 1498 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1499 /* Reset bit Deassert (bit 6 at 0x3E) */ 1500 bcr &= ~CB_BCR_RESET_ENABLE; 1501 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1502 DELAY_MS(reset_duration, sc); 1503 } 1504 /* No card found on the slot. Keep Reset. */ 1505 return 1; 1506 } 1507 1508 /* 1509 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1510 * This function detect card Voltage. 1511 */ 1512 STATIC int 1513 cb_detect_voltage(sc) 1514 struct pccbb_softc *sc; 1515 { 1516 u_int32_t psr; /* socket present-state reg */ 1517 bus_space_tag_t iot = sc->sc_base_memt; 1518 bus_space_handle_t ioh = sc->sc_base_memh; 1519 int vol = PCCARD_VCC_UKN; /* set 0 */ 1520 1521 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1522 1523 if (0x400u & psr) { 1524 vol |= PCCARD_VCC_5V; 1525 } 1526 if (0x800u & psr) { 1527 vol |= PCCARD_VCC_3V; 1528 } 1529 1530 return vol; 1531 } 1532 1533 STATIC int 1534 cbbprint(aux, pcic) 1535 void *aux; 1536 const char *pcic; 1537 { 1538 /* 1539 struct cbslot_attach_args *cba = aux; 1540 1541 if (cba->cba_slot >= 0) { 1542 printf(" slot %d", cba->cba_slot); 1543 } 1544 */ 1545 return UNCONF; 1546 } 1547 1548 /* 1549 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1550 * This function enables and disables the card 1551 */ 1552 STATIC int 1553 pccbb_cardenable(sc, function) 1554 struct pccbb_softc *sc; 1555 int function; 1556 { 1557 u_int32_t command = 1558 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1559 1560 DPRINTF(("pccbb_cardenable:")); 1561 switch (function) { 1562 case CARDBUS_IO_ENABLE: 1563 command |= PCI_COMMAND_IO_ENABLE; 1564 break; 1565 case CARDBUS_IO_DISABLE: 1566 command &= ~PCI_COMMAND_IO_ENABLE; 1567 break; 1568 case CARDBUS_MEM_ENABLE: 1569 command |= PCI_COMMAND_MEM_ENABLE; 1570 break; 1571 case CARDBUS_MEM_DISABLE: 1572 command &= ~PCI_COMMAND_MEM_ENABLE; 1573 break; 1574 case CARDBUS_BM_ENABLE: 1575 command |= PCI_COMMAND_MASTER_ENABLE; 1576 break; 1577 case CARDBUS_BM_DISABLE: 1578 command &= ~PCI_COMMAND_MASTER_ENABLE; 1579 break; 1580 default: 1581 return 0; 1582 } 1583 1584 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1585 DPRINTF((" command reg 0x%x\n", command)); 1586 return 1; 1587 } 1588 1589 #if !rbus 1590 /* 1591 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1592 */ 1593 static int 1594 pccbb_io_open(ct, win, start, end) 1595 cardbus_chipset_tag_t ct; 1596 int win; 1597 u_int32_t start, end; 1598 { 1599 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1600 int basereg; 1601 int limitreg; 1602 1603 if ((win < 0) || (win > 2)) { 1604 #if defined DIAGNOSTIC 1605 printf("cardbus_io_open: window out of range %d\n", win); 1606 #endif 1607 return 0; 1608 } 1609 1610 basereg = win * 8 + 0x2c; 1611 limitreg = win * 8 + 0x30; 1612 1613 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1614 start, basereg, end, limitreg)); 1615 1616 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1617 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1618 return 1; 1619 } 1620 1621 /* 1622 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1623 */ 1624 static int 1625 pccbb_io_close(ct, win) 1626 cardbus_chipset_tag_t ct; 1627 int win; 1628 { 1629 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1630 int basereg; 1631 int limitreg; 1632 1633 if ((win < 0) || (win > 2)) { 1634 #if defined DIAGNOSTIC 1635 printf("cardbus_io_close: window out of range %d\n", win); 1636 #endif 1637 return 0; 1638 } 1639 1640 basereg = win * 8 + 0x2c; 1641 limitreg = win * 8 + 0x30; 1642 1643 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1644 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1645 return 1; 1646 } 1647 1648 /* 1649 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1650 */ 1651 static int 1652 pccbb_mem_open(ct, win, start, end) 1653 cardbus_chipset_tag_t ct; 1654 int win; 1655 u_int32_t start, end; 1656 { 1657 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1658 int basereg; 1659 int limitreg; 1660 1661 if ((win < 0) || (win > 2)) { 1662 #if defined DIAGNOSTIC 1663 printf("cardbus_mem_open: window out of range %d\n", win); 1664 #endif 1665 return 0; 1666 } 1667 1668 basereg = win * 8 + 0x1c; 1669 limitreg = win * 8 + 0x20; 1670 1671 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1672 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1673 return 1; 1674 } 1675 1676 /* 1677 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1678 */ 1679 static int 1680 pccbb_mem_close(ct, win) 1681 cardbus_chipset_tag_t ct; 1682 int win; 1683 { 1684 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1685 int basereg; 1686 int limitreg; 1687 1688 if ((win < 0) || (win > 2)) { 1689 #if defined DIAGNOSTIC 1690 printf("cardbus_mem_close: window out of range %d\n", win); 1691 #endif 1692 return 0; 1693 } 1694 1695 basereg = win * 8 + 0x1c; 1696 limitreg = win * 8 + 0x20; 1697 1698 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1699 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1700 return 1; 1701 } 1702 #endif 1703 1704 /* 1705 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1706 * int irq, 1707 * int level, 1708 * int (* func) __P((void *)), 1709 * void *arg) 1710 * 1711 * This function registers an interrupt handler at the bridge, in 1712 * order not to call the interrupt handlers of child devices when 1713 * a card-deletion interrupt occurs. 1714 * 1715 * The arguments irq and level are not used. 1716 */ 1717 static void * 1718 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1719 cardbus_chipset_tag_t ct; 1720 int irq, level; 1721 int (*func) __P((void *)); 1722 void *arg; 1723 { 1724 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1725 1726 return pccbb_intr_establish(sc, irq, level, func, arg); 1727 } 1728 1729 1730 /* 1731 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1732 * void *ih) 1733 * 1734 * This function removes an interrupt handler pointed by ih. 1735 */ 1736 static void 1737 pccbb_cb_intr_disestablish(ct, ih) 1738 cardbus_chipset_tag_t ct; 1739 void *ih; 1740 { 1741 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1742 1743 pccbb_intr_disestablish(sc, ih); 1744 } 1745 1746 1747 void 1748 pccbb_intr_route(sc) 1749 struct pccbb_softc *sc; 1750 { 1751 pcireg_t reg; 1752 1753 /* initialize bridge intr routing */ 1754 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1755 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1756 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1757 1758 switch (sc->sc_chipset) { 1759 case CB_TI113X: 1760 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1761 /* functional intr enabled */ 1762 reg |= PCI113X_CBCTRL_PCI_INTR; 1763 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1764 break; 1765 default: 1766 break; 1767 } 1768 } 1769 1770 /* 1771 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1772 * int irq, 1773 * int level, 1774 * int (* func) __P((void *)), 1775 * void *arg) 1776 * 1777 * This function registers an interrupt handler at the bridge, in 1778 * order not to call the interrupt handlers of child devices when 1779 * a card-deletion interrupt occurs. 1780 * 1781 * The arguments irq is not used because pccbb selects intr vector. 1782 */ 1783 static void * 1784 pccbb_intr_establish(sc, irq, level, func, arg) 1785 struct pccbb_softc *sc; 1786 int irq, level; 1787 int (*func) __P((void *)); 1788 void *arg; 1789 { 1790 struct pccbb_intrhand_list *pil, *newpil; 1791 1792 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1793 1794 if (sc->sc_pil == NULL) { 1795 pccbb_intr_route(sc); 1796 1797 } 1798 1799 /* 1800 * Allocate a room for interrupt handler structure. 1801 */ 1802 if (NULL == (newpil = 1803 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1804 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1805 return NULL; 1806 } 1807 1808 newpil->pil_func = func; 1809 newpil->pil_arg = arg; 1810 newpil->pil_level = level; 1811 newpil->pil_next = NULL; 1812 1813 if (sc->sc_pil == NULL) { 1814 sc->sc_pil = newpil; 1815 } else { 1816 for (pil = sc->sc_pil; pil->pil_next != NULL; 1817 pil = pil->pil_next); 1818 pil->pil_next = newpil; 1819 } 1820 1821 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1822 1823 return newpil; 1824 } 1825 1826 /* 1827 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1828 * void *ih) 1829 * 1830 * This function removes an interrupt handler pointed by ih. 1831 */ 1832 static void 1833 pccbb_intr_disestablish(sc, ih) 1834 struct pccbb_softc *sc; 1835 void *ih; 1836 { 1837 struct pccbb_intrhand_list *pil, **pil_prev; 1838 pcireg_t reg; 1839 1840 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1841 1842 pil_prev = &sc->sc_pil; 1843 1844 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1845 if (pil == ih) { 1846 *pil_prev = pil->pil_next; 1847 free(pil, M_DEVBUF); 1848 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1849 break; 1850 } 1851 pil_prev = &pil->pil_next; 1852 } 1853 1854 if (sc->sc_pil == NULL) { 1855 /* No interrupt handlers */ 1856 1857 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1858 1859 /* stop routing PCI intr */ 1860 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1861 reg |= CB_BCR_INTR_IREQ_ENABLE; 1862 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1863 1864 switch (sc->sc_chipset) { 1865 case CB_TI113X: 1866 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1867 /* functional intr disabled */ 1868 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1869 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1870 break; 1871 default: 1872 break; 1873 } 1874 } 1875 } 1876 1877 #if defined SHOW_REGS 1878 static void 1879 cb_show_regs(pc, tag, memt, memh) 1880 pci_chipset_tag_t pc; 1881 pcitag_t tag; 1882 bus_space_tag_t memt; 1883 bus_space_handle_t memh; 1884 { 1885 int i; 1886 printf("PCI config regs:"); 1887 for (i = 0; i < 0x50; i += 4) { 1888 if (i % 16 == 0) { 1889 printf("\n 0x%02x:", i); 1890 } 1891 printf(" %08x", pci_conf_read(pc, tag, i)); 1892 } 1893 for (i = 0x80; i < 0xb0; i += 4) { 1894 if (i % 16 == 0) { 1895 printf("\n 0x%02x:", i); 1896 } 1897 printf(" %08x", pci_conf_read(pc, tag, i)); 1898 } 1899 1900 if (memh == 0) { 1901 printf("\n"); 1902 return; 1903 } 1904 1905 printf("\nsocket regs:"); 1906 for (i = 0; i <= 0x10; i += 0x04) { 1907 printf(" %08x", bus_space_read_4(memt, memh, i)); 1908 } 1909 printf("\nExCA regs:"); 1910 for (i = 0; i < 0x08; ++i) { 1911 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1912 } 1913 printf("\n"); 1914 return; 1915 } 1916 #endif 1917 1918 /* 1919 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1920 * int busno, int devno, int function) 1921 * This is the function to make a tag to access config space of 1922 * a CardBus Card. It works same as pci_conf_read. 1923 */ 1924 static cardbustag_t 1925 pccbb_make_tag(cc, busno, devno, function) 1926 cardbus_chipset_tag_t cc; 1927 int busno, devno, function; 1928 { 1929 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1930 1931 return pci_make_tag(sc->sc_pc, busno, devno, function); 1932 } 1933 1934 static void 1935 pccbb_free_tag(cc, tag) 1936 cardbus_chipset_tag_t cc; 1937 cardbustag_t tag; 1938 { 1939 } 1940 1941 /* 1942 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1943 * cardbustag_t tag, int offset) 1944 * This is the function to read the config space of a CardBus Card. 1945 * It works same as pci_conf_read. 1946 */ 1947 static cardbusreg_t 1948 pccbb_conf_read(cc, tag, offset) 1949 cardbus_chipset_tag_t cc; 1950 cardbustag_t tag; 1951 int offset; /* register offset */ 1952 { 1953 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1954 1955 return pci_conf_read(sc->sc_pc, tag, offset); 1956 } 1957 1958 /* 1959 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1960 * int offs, cardbusreg_t val) 1961 * This is the function to write the config space of a CardBus Card. 1962 * It works same as pci_conf_write. 1963 */ 1964 static void 1965 pccbb_conf_write(cc, tag, reg, val) 1966 cardbus_chipset_tag_t cc; 1967 cardbustag_t tag; 1968 int reg; /* register offset */ 1969 cardbusreg_t val; 1970 { 1971 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1972 1973 pci_conf_write(sc->sc_pc, tag, reg, val); 1974 } 1975 1976 #if 0 1977 STATIC int 1978 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1979 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1980 int speed, int flags, 1981 bus_space_handle_t * iohp) 1982 #endif 1983 /* 1984 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1985 * bus_addr_t start, bus_size_t size, 1986 * bus_size_t align, 1987 * struct pcmcia_io_handle *pcihp 1988 * 1989 * This function only allocates I/O region for pccard. This function 1990 * never maps the allocated region to pccard I/O area. 1991 * 1992 * XXX: The interface of this function is not very good, I believe. 1993 */ 1994 STATIC int 1995 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1996 pcmcia_chipset_handle_t pch; 1997 bus_addr_t start; /* start address */ 1998 bus_size_t size; 1999 bus_size_t align; 2000 struct pcmcia_io_handle *pcihp; 2001 { 2002 struct pcic_handle *ph = (struct pcic_handle *)pch; 2003 bus_addr_t ioaddr; 2004 int flags = 0; 2005 bus_space_tag_t iot; 2006 bus_space_handle_t ioh; 2007 bus_addr_t mask; 2008 #if rbus 2009 rbus_tag_t rb; 2010 #endif 2011 if (align == 0) { 2012 align = size; /* XXX: funny??? */ 2013 } 2014 2015 if (start != 0) { 2016 /* XXX: assume all card decode lower 10 bits by its hardware */ 2017 mask = 0x3ff; 2018 /* enforce to use only masked address */ 2019 start &= mask; 2020 } else { 2021 /* 2022 * calculate mask: 2023 * 1. get the most significant bit of size (call it msb). 2024 * 2. compare msb with the value of size. 2025 * 3. if size is larger, shift msb left once. 2026 * 4. obtain mask value to decrement msb. 2027 */ 2028 bus_size_t size_tmp = size; 2029 int shifts = 0; 2030 2031 mask = 1; 2032 while (size_tmp) { 2033 ++shifts; 2034 size_tmp >>= 1; 2035 } 2036 mask = (1 << shifts); 2037 if (mask < size) { 2038 mask <<= 1; 2039 } 2040 --mask; 2041 } 2042 2043 /* 2044 * Allocate some arbitrary I/O space. 2045 */ 2046 2047 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2048 2049 #if rbus 2050 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2051 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2052 return 1; 2053 } 2054 #else 2055 if (start) { 2056 ioaddr = start; 2057 if (bus_space_map(iot, start, size, 0, &ioh)) { 2058 return 1; 2059 } 2060 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2061 (u_long) ioaddr, (u_long) size)); 2062 } else { 2063 flags |= PCMCIA_IO_ALLOCATED; 2064 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2065 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2066 size, align, 0, 0, &ioaddr, &ioh)) { 2067 /* No room be able to be get. */ 2068 return 1; 2069 } 2070 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2071 (u_long) ioaddr, (u_long) size)); 2072 } 2073 #endif 2074 2075 pcihp->iot = iot; 2076 pcihp->ioh = ioh; 2077 pcihp->addr = ioaddr; 2078 pcihp->size = size; 2079 pcihp->flags = flags; 2080 2081 return 0; 2082 } 2083 2084 /* 2085 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2086 * struct pcmcia_io_handle *pcihp) 2087 * 2088 * This function only frees I/O region for pccard. 2089 * 2090 * XXX: The interface of this function is not very good, I believe. 2091 */ 2092 void 2093 pccbb_pcmcia_io_free(pch, pcihp) 2094 pcmcia_chipset_handle_t pch; 2095 struct pcmcia_io_handle *pcihp; 2096 { 2097 #if !rbus 2098 bus_space_tag_t iot = pcihp->iot; 2099 #endif 2100 bus_space_handle_t ioh = pcihp->ioh; 2101 bus_size_t size = pcihp->size; 2102 2103 #if rbus 2104 struct pccbb_softc *sc = 2105 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2106 rbus_tag_t rb = sc->sc_rbus_iot; 2107 2108 rbus_space_free(rb, ioh, size, NULL); 2109 #else 2110 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2111 bus_space_free(iot, ioh, size); 2112 else 2113 bus_space_unmap(iot, ioh, size); 2114 #endif 2115 } 2116 2117 /* 2118 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2119 * bus_addr_t offset, bus_size_t size, 2120 * struct pcmcia_io_handle *pcihp, 2121 * int *windowp) 2122 * 2123 * This function maps the allocated I/O region to pccard. This function 2124 * never allocates any I/O region for pccard I/O area. I don't 2125 * understand why the original authors of pcmciabus separated alloc and 2126 * map. I believe the two must be unite. 2127 * 2128 * XXX: no wait timing control? 2129 */ 2130 int 2131 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2132 pcmcia_chipset_handle_t pch; 2133 int width; 2134 bus_addr_t offset; 2135 bus_size_t size; 2136 struct pcmcia_io_handle *pcihp; 2137 int *windowp; 2138 { 2139 struct pcic_handle *ph = (struct pcic_handle *)pch; 2140 bus_addr_t ioaddr = pcihp->addr + offset; 2141 int i, win; 2142 #if defined CBB_DEBUG 2143 static char *width_names[] = { "dynamic", "io8", "io16" }; 2144 #endif 2145 2146 /* Sanity check I/O handle. */ 2147 2148 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2149 panic("pccbb_pcmcia_io_map iot is bogus"); 2150 } 2151 2152 /* XXX Sanity check offset/size. */ 2153 2154 win = -1; 2155 for (i = 0; i < PCIC_IO_WINS; i++) { 2156 if ((ph->ioalloc & (1 << i)) == 0) { 2157 win = i; 2158 ph->ioalloc |= (1 << i); 2159 break; 2160 } 2161 } 2162 2163 if (win == -1) { 2164 return 1; 2165 } 2166 2167 *windowp = win; 2168 2169 /* XXX this is pretty gross */ 2170 2171 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2172 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2173 2174 /* XXX wtf is this doing here? */ 2175 2176 #if 0 2177 printf(" port 0x%lx", (u_long) ioaddr); 2178 if (size > 1) { 2179 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2180 } 2181 #endif 2182 2183 ph->io[win].addr = ioaddr; 2184 ph->io[win].size = size; 2185 ph->io[win].width = width; 2186 2187 /* actual dirty register-value changing in the function below. */ 2188 pccbb_pcmcia_do_io_map(ph, win); 2189 2190 return 0; 2191 } 2192 2193 /* 2194 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2195 * 2196 * This function changes register-value to map I/O region for pccard. 2197 */ 2198 static void 2199 pccbb_pcmcia_do_io_map(ph, win) 2200 struct pcic_handle *ph; 2201 int win; 2202 { 2203 static u_int8_t pcic_iowidth[3] = { 2204 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2205 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2206 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2207 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2208 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2209 }; 2210 2211 #define PCIC_SIA_START_LOW 0 2212 #define PCIC_SIA_START_HIGH 1 2213 #define PCIC_SIA_STOP_LOW 2 2214 #define PCIC_SIA_STOP_HIGH 3 2215 2216 int regbase_win = 0x8 + win * 0x04; 2217 u_int8_t ioctl, enable; 2218 2219 DPRINTF( 2220 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2221 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2222 ph->io[win].width * 8)); 2223 2224 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2225 ph->io[win].addr & 0xff); 2226 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2227 (ph->io[win].addr >> 8) & 0xff); 2228 2229 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2230 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2231 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2232 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2233 2234 ioctl = Pcic_read(ph, PCIC_IOCTL); 2235 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2236 switch (win) { 2237 case 0: 2238 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2239 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2240 PCIC_IOCTL_IO0_DATASIZE_MASK); 2241 ioctl |= pcic_iowidth[ph->io[win].width]; 2242 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2243 break; 2244 case 1: 2245 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2246 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2247 PCIC_IOCTL_IO1_DATASIZE_MASK); 2248 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2249 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2250 break; 2251 } 2252 Pcic_write(ph, PCIC_IOCTL, ioctl); 2253 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2254 #if defined CBB_DEBUG 2255 { 2256 u_int8_t start_low = 2257 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2258 u_int8_t start_high = 2259 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2260 u_int8_t stop_low = 2261 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2262 u_int8_t stop_high = 2263 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2264 printf 2265 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2266 start_low, start_high, stop_low, stop_high, ioctl, enable); 2267 } 2268 #endif 2269 } 2270 2271 /* 2272 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2273 * 2274 * This function unmaps I/O region. No return value. 2275 */ 2276 STATIC void 2277 pccbb_pcmcia_io_unmap(pch, win) 2278 pcmcia_chipset_handle_t pch; 2279 int win; 2280 { 2281 struct pcic_handle *ph = (struct pcic_handle *)pch; 2282 int reg; 2283 2284 if (win >= PCIC_IO_WINS || win < 0) { 2285 panic("pccbb_pcmcia_io_unmap: window out of range"); 2286 } 2287 2288 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2289 switch (win) { 2290 case 0: 2291 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2292 break; 2293 case 1: 2294 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2295 break; 2296 } 2297 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2298 2299 ph->ioalloc &= ~(1 << win); 2300 } 2301 2302 /* 2303 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2304 * 2305 * This function enables the card. All information is stored in 2306 * the first argument, pcmcia_chipset_handle_t. 2307 */ 2308 static void 2309 pccbb_pcmcia_wait_ready(ph) 2310 struct pcic_handle *ph; 2311 { 2312 int i; 2313 2314 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2315 Pcic_read(ph, PCIC_IF_STATUS))); 2316 2317 for (i = 0; i < 2000; i++) { 2318 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2319 return; 2320 } 2321 DELAY_MS(2, ph->ph_parent); 2322 #ifdef CBB_DEBUG 2323 if ((i > 1000) && (i % 25 == 24)) 2324 printf("."); 2325 #endif 2326 } 2327 2328 #ifdef DIAGNOSTIC 2329 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2330 Pcic_read(ph, PCIC_IF_STATUS)); 2331 #endif 2332 } 2333 2334 /* 2335 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2336 * 2337 * This function enables the card. All information is stored in 2338 * the first argument, pcmcia_chipset_handle_t. 2339 */ 2340 STATIC void 2341 pccbb_pcmcia_socket_enable(pch) 2342 pcmcia_chipset_handle_t pch; 2343 { 2344 struct pcic_handle *ph = (struct pcic_handle *)pch; 2345 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2346 int cardtype, win; 2347 u_int8_t power, intr; 2348 pcireg_t spsr; 2349 int voltage; 2350 2351 /* this bit is mostly stolen from pcic_attach_card */ 2352 2353 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2354 2355 /* get card Vcc info */ 2356 2357 spsr = 2358 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2359 CB_SOCKET_STAT); 2360 if (spsr & CB_SOCKET_STAT_5VCARD) { 2361 DPRINTF(("5V card\n")); 2362 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2363 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2364 DPRINTF(("3V card\n")); 2365 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2366 } else { 2367 printf("?V card, 0x%x\n", spsr); /* XXX */ 2368 return; 2369 } 2370 2371 /* disable socket: negate output enable bit and power off */ 2372 2373 power = 0; 2374 Pcic_write(ph, PCIC_PWRCTL, power); 2375 2376 /* power down the socket to reset it, clear the card reset pin */ 2377 2378 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2379 2380 /* 2381 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2382 * we are changing Vcc (Toff). 2383 */ 2384 /* delay(300*1000); too much */ 2385 2386 /* assert reset bit */ 2387 intr = Pcic_read(ph, PCIC_INTR); 2388 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2389 Pcic_write(ph, PCIC_INTR, intr); 2390 2391 /* power up the socket and output enable */ 2392 power = Pcic_read(ph, PCIC_PWRCTL); 2393 power |= PCIC_PWRCTL_OE; 2394 Pcic_write(ph, PCIC_PWRCTL, power); 2395 pccbb_power(sc, voltage); 2396 2397 /* 2398 * hold RESET at least 20 ms: the spec says only 10 us is 2399 * enough, but TI1130 requires at least 20 ms. 2400 */ 2401 #if 0 /* XXX called on interrupt context */ 2402 DELAY_MS(20, sc); 2403 #else 2404 delay(20 * 1000); 2405 #endif 2406 2407 /* clear the reset flag */ 2408 2409 intr |= PCIC_INTR_RESET; 2410 Pcic_write(ph, PCIC_INTR, intr); 2411 2412 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2413 2414 #if 0 /* XXX called on interrupt context */ 2415 DELAY_MS(20, sc); 2416 #else 2417 delay(20 * 1000); 2418 #endif 2419 2420 /* wait for the chip to finish initializing */ 2421 2422 pccbb_pcmcia_wait_ready(ph); 2423 2424 /* zero out the address windows */ 2425 2426 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2427 2428 /* set the card type */ 2429 2430 cardtype = pcmcia_card_gettype(ph->pcmcia); 2431 2432 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2433 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2434 Pcic_write(ph, PCIC_INTR, intr); 2435 2436 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2437 ph->ph_parent->dv_xname, ph->sock, 2438 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2439 2440 /* reinstall all the memory and io mappings */ 2441 2442 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2443 if (ph->memalloc & (1 << win)) { 2444 pccbb_pcmcia_do_mem_map(ph, win); 2445 } 2446 } 2447 2448 for (win = 0; win < PCIC_IO_WINS; ++win) { 2449 if (ph->ioalloc & (1 << win)) { 2450 pccbb_pcmcia_do_io_map(ph, win); 2451 } 2452 } 2453 } 2454 2455 /* 2456 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2457 * 2458 * This function disables the card. All information is stored in 2459 * the first argument, pcmcia_chipset_handle_t. 2460 */ 2461 STATIC void 2462 pccbb_pcmcia_socket_disable(pch) 2463 pcmcia_chipset_handle_t pch; 2464 { 2465 struct pcic_handle *ph = (struct pcic_handle *)pch; 2466 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2467 u_int8_t power, intr; 2468 2469 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2470 2471 /* reset signal asserting... */ 2472 2473 intr = Pcic_read(ph, PCIC_INTR); 2474 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2475 Pcic_write(ph, PCIC_INTR, intr); 2476 delay(2 * 1000); 2477 2478 /* power down the socket */ 2479 power = Pcic_read(ph, PCIC_PWRCTL); 2480 power &= ~PCIC_PWRCTL_OE; 2481 Pcic_write(ph, PCIC_PWRCTL, power); 2482 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2483 /* 2484 * wait 300ms until power fails (Tpf). 2485 */ 2486 #if 0 /* XXX called on interrupt context */ 2487 DELAY_MS(300, sc); 2488 #else 2489 delay(300 * 1000); 2490 #endif 2491 } 2492 2493 /* 2494 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2495 * 2496 * This function detects whether a card is in the slot or not. 2497 * If a card is inserted, return 1. Otherwise, return 0. 2498 */ 2499 STATIC int 2500 pccbb_pcmcia_card_detect(pch) 2501 pcmcia_chipset_handle_t pch; 2502 { 2503 struct pcic_handle *ph = (struct pcic_handle *)pch; 2504 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2505 2506 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2507 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2508 } 2509 2510 #if 0 2511 STATIC int 2512 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2513 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2514 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2515 #endif 2516 /* 2517 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2518 * bus_size_t size, 2519 * struct pcmcia_mem_handle *pcmhp) 2520 * 2521 * This function only allocates memory region for pccard. This 2522 * function never maps the allocated region to pccard memory area. 2523 * 2524 * XXX: Why the argument of start address is not in? 2525 */ 2526 STATIC int 2527 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2528 pcmcia_chipset_handle_t pch; 2529 bus_size_t size; 2530 struct pcmcia_mem_handle *pcmhp; 2531 { 2532 struct pcic_handle *ph = (struct pcic_handle *)pch; 2533 bus_space_handle_t memh; 2534 bus_addr_t addr; 2535 bus_size_t sizepg; 2536 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2537 #if rbus 2538 rbus_tag_t rb; 2539 #endif 2540 2541 /* out of sc->memh, allocate as many pages as necessary */ 2542 2543 /* convert size to PCIC pages */ 2544 /* 2545 * This is not enough; when the requested region is on the page 2546 * boundaries, this may calculate wrong result. 2547 */ 2548 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2549 #if 0 2550 if (sizepg > PCIC_MAX_MEM_PAGES) { 2551 return 1; 2552 } 2553 #endif 2554 2555 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2556 return 1; 2557 } 2558 2559 addr = 0; /* XXX gcc -Wuninitialized */ 2560 2561 #if rbus 2562 rb = sc->sc_rbus_memt; 2563 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2564 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2565 &addr, &memh)) { 2566 return 1; 2567 } 2568 #else 2569 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2570 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2571 0, /* boundary */ 2572 0, /* flags */ 2573 &addr, &memh)) { 2574 return 1; 2575 } 2576 #endif 2577 2578 DPRINTF( 2579 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2580 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2581 2582 pcmhp->memt = sc->sc_memt; 2583 pcmhp->memh = memh; 2584 pcmhp->addr = addr; 2585 pcmhp->size = size; 2586 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2587 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2588 pcmhp->mhandle = 0; 2589 /* No offset??? Funny. */ 2590 2591 return 0; 2592 } 2593 2594 /* 2595 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2596 * struct pcmcia_mem_handle *pcmhp) 2597 * 2598 * This function release the memory space allocated by the function 2599 * pccbb_pcmcia_mem_alloc(). 2600 */ 2601 STATIC void 2602 pccbb_pcmcia_mem_free(pch, pcmhp) 2603 pcmcia_chipset_handle_t pch; 2604 struct pcmcia_mem_handle *pcmhp; 2605 { 2606 #if rbus 2607 struct pcic_handle *ph = (struct pcic_handle *)pch; 2608 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2609 2610 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2611 #else 2612 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2613 #endif 2614 } 2615 2616 /* 2617 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2618 * 2619 * This function release the memory space allocated by the function 2620 * pccbb_pcmcia_mem_alloc(). 2621 */ 2622 STATIC void 2623 pccbb_pcmcia_do_mem_map(ph, win) 2624 struct pcic_handle *ph; 2625 int win; 2626 { 2627 int regbase_win; 2628 bus_addr_t phys_addr; 2629 bus_addr_t phys_end; 2630 2631 #define PCIC_SMM_START_LOW 0 2632 #define PCIC_SMM_START_HIGH 1 2633 #define PCIC_SMM_STOP_LOW 2 2634 #define PCIC_SMM_STOP_HIGH 3 2635 #define PCIC_CMA_LOW 4 2636 #define PCIC_CMA_HIGH 5 2637 2638 u_int8_t start_low, start_high = 0; 2639 u_int8_t stop_low, stop_high; 2640 u_int8_t off_low, off_high; 2641 u_int8_t mem_window; 2642 int reg; 2643 2644 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2645 int mem8 = 2646 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2647 || (kind == PCMCIA_MEM_ATTR); 2648 2649 regbase_win = 0x10 + win * 0x08; 2650 2651 phys_addr = ph->mem[win].addr; 2652 phys_end = phys_addr + ph->mem[win].size; 2653 2654 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2655 phys_addr, phys_end, ph->mem[win].offset)); 2656 2657 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2658 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2659 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2660 2661 /* bit 19:12 */ 2662 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2663 /* bit 23:20 and bit 7 on */ 2664 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2665 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2666 /* bit 31:24, for 32-bit address */ 2667 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2668 2669 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2670 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2671 2672 if (((struct pccbb_softc *)ph-> 2673 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2674 Pcic_write(ph, 0x40 + win, mem_window); 2675 } 2676 2677 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2678 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2679 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2680 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2681 2682 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2683 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2684 2685 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2686 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2687 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2688 | ((kind == PCMCIA_MEM_ATTR) ? 2689 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2690 2691 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2692 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2693 2694 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2695 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2696 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2697 2698 #if defined CBB_DEBUG 2699 { 2700 int r1, r2, r3, r4, r5, r6, r7 = 0; 2701 2702 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2703 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2704 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2705 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2706 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2707 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2708 if (((struct pccbb_softc *)(ph-> 2709 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2710 r7 = Pcic_read(ph, 0x40 + win); 2711 } 2712 2713 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2714 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2715 if (((struct pccbb_softc *)(ph-> 2716 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2717 DPRINTF((" %02x", r7)); 2718 } 2719 DPRINTF(("\n")); 2720 } 2721 #endif 2722 } 2723 2724 /* 2725 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2726 * bus_addr_t card_addr, bus_size_t size, 2727 * struct pcmcia_mem_handle *pcmhp, 2728 * bus_addr_t *offsetp, int *windowp) 2729 * 2730 * This function maps memory space allocated by the function 2731 * pccbb_pcmcia_mem_alloc(). 2732 */ 2733 STATIC int 2734 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2735 pcmcia_chipset_handle_t pch; 2736 int kind; 2737 bus_addr_t card_addr; 2738 bus_size_t size; 2739 struct pcmcia_mem_handle *pcmhp; 2740 bus_addr_t *offsetp; 2741 int *windowp; 2742 { 2743 struct pcic_handle *ph = (struct pcic_handle *)pch; 2744 bus_addr_t busaddr; 2745 long card_offset; 2746 int win; 2747 2748 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2749 if ((ph->memalloc & (1 << win)) == 0) { 2750 ph->memalloc |= (1 << win); 2751 break; 2752 } 2753 } 2754 2755 if (win == PCIC_MEM_WINS) { 2756 return 1; 2757 } 2758 2759 *windowp = win; 2760 2761 /* XXX this is pretty gross */ 2762 2763 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2764 panic("pccbb_pcmcia_mem_map memt is bogus"); 2765 } 2766 2767 busaddr = pcmhp->addr; 2768 2769 /* 2770 * compute the address offset to the pcmcia address space for the 2771 * pcic. this is intentionally signed. The masks and shifts below 2772 * will cause TRT to happen in the pcic registers. Deal with making 2773 * sure the address is aligned, and return the alignment offset. 2774 */ 2775 2776 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2777 card_addr -= *offsetp; 2778 2779 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2780 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2781 (u_long) card_addr)); 2782 2783 /* 2784 * include the offset in the size, and decrement size by one, since 2785 * the hw wants start/stop 2786 */ 2787 size += *offsetp - 1; 2788 2789 card_offset = (((long)card_addr) - ((long)busaddr)); 2790 2791 ph->mem[win].addr = busaddr; 2792 ph->mem[win].size = size; 2793 ph->mem[win].offset = card_offset; 2794 ph->mem[win].kind = kind; 2795 2796 pccbb_pcmcia_do_mem_map(ph, win); 2797 2798 return 0; 2799 } 2800 2801 /* 2802 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2803 * int window) 2804 * 2805 * This function unmaps memory space which mapped by the function 2806 * pccbb_pcmcia_mem_map(). 2807 */ 2808 STATIC void 2809 pccbb_pcmcia_mem_unmap(pch, window) 2810 pcmcia_chipset_handle_t pch; 2811 int window; 2812 { 2813 struct pcic_handle *ph = (struct pcic_handle *)pch; 2814 int reg; 2815 2816 if (window >= PCIC_MEM_WINS) { 2817 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2818 } 2819 2820 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2821 reg &= ~(1 << window); 2822 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2823 2824 ph->memalloc &= ~(1 << window); 2825 } 2826 2827 #if defined PCCBB_PCMCIA_POLL 2828 struct pccbb_poll_str { 2829 void *arg; 2830 int (*func) __P((void *)); 2831 int level; 2832 struct pcic_handle *ph; 2833 int count; 2834 int num; 2835 struct callout poll_ch; 2836 }; 2837 2838 static struct pccbb_poll_str pccbb_poll[10]; 2839 static int pccbb_poll_n = 0; 2840 2841 static void pccbb_pcmcia_poll __P((void *arg)); 2842 2843 static void 2844 pccbb_pcmcia_poll(arg) 2845 void *arg; 2846 { 2847 struct pccbb_poll_str *poll = arg; 2848 struct pcic_handle *ph = poll->ph; 2849 struct pccbb_softc *sc = ph->sc; 2850 int s; 2851 u_int32_t spsr; /* socket present-state reg */ 2852 2853 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2854 switch (poll->level) { 2855 case IPL_NET: 2856 s = splnet(); 2857 break; 2858 case IPL_BIO: 2859 s = splbio(); 2860 break; 2861 case IPL_TTY: /* fallthrough */ 2862 default: 2863 s = spltty(); 2864 break; 2865 } 2866 2867 spsr = 2868 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2869 CB_SOCKET_STAT); 2870 2871 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2872 if (!(spsr & 0x40)) /* CINT low */ 2873 #else 2874 if (1) 2875 #endif 2876 { 2877 if ((*poll->func) (poll->arg) > 0) { 2878 ++poll->count; 2879 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2880 #if defined LEVEL2 2881 } else { 2882 printf("intr: miss! 0x%x\n", spsr); 2883 #endif 2884 } 2885 } 2886 splx(s); 2887 } 2888 #endif /* defined CB_PCMCIA_POLL */ 2889 2890 /* 2891 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2892 * struct pcmcia_function *pf, 2893 * int ipl, 2894 * int (*func)(void *), 2895 * void *arg); 2896 * 2897 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2898 */ 2899 STATIC void * 2900 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2901 pcmcia_chipset_handle_t pch; 2902 struct pcmcia_function *pf; 2903 int ipl; 2904 int (*func) __P((void *)); 2905 void *arg; 2906 { 2907 struct pcic_handle *ph = (struct pcic_handle *)pch; 2908 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2909 2910 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2911 /* what should I do? */ 2912 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2913 DPRINTF( 2914 ("%s does not provide edge nor pulse interrupt\n", 2915 sc->sc_dev.dv_xname)); 2916 return NULL; 2917 } 2918 /* 2919 * XXX Noooooo! The interrupt flag must set properly!! 2920 * dumb pcmcia driver!! 2921 */ 2922 } 2923 2924 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2925 } 2926 2927 /* 2928 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2929 * void *ih) 2930 * 2931 * This function disables PC-Card interrupt. 2932 */ 2933 STATIC void 2934 pccbb_pcmcia_intr_disestablish(pch, ih) 2935 pcmcia_chipset_handle_t pch; 2936 void *ih; 2937 { 2938 struct pcic_handle *ph = (struct pcic_handle *)pch; 2939 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2940 2941 pccbb_intr_disestablish(sc, ih); 2942 } 2943 2944 #if rbus 2945 /* 2946 * static int 2947 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2948 * bus_addr_t addr, bus_size_t size, 2949 * bus_addr_t mask, bus_size_t align, 2950 * int flags, bus_addr_t *addrp; 2951 * bus_space_handle_t *bshp) 2952 * 2953 * This function allocates a portion of memory or io space for 2954 * clients. This function is called from CardBus card drivers. 2955 */ 2956 static int 2957 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2958 cardbus_chipset_tag_t ct; 2959 rbus_tag_t rb; 2960 bus_addr_t addr; 2961 bus_size_t size; 2962 bus_addr_t mask; 2963 bus_size_t align; 2964 int flags; 2965 bus_addr_t *addrp; 2966 bus_space_handle_t *bshp; 2967 { 2968 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2969 2970 DPRINTF( 2971 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2972 addr, size, mask, align)); 2973 2974 if (align == 0) { 2975 align = size; 2976 } 2977 2978 if (rb->rb_bt == sc->sc_memt) { 2979 if (align < 16) { 2980 return 1; 2981 } 2982 /* 2983 * XXX: align more than 0x1000 to avoid overwrapping 2984 * memory windows for two or more devices. 0x1000 2985 * means memory window's granularity. 2986 * 2987 * Two or more devices should be able to share same 2988 * memory window region. However, overrapping memory 2989 * window is not good because some devices, such as 2990 * 3Com 3C575[BC], have a broken address decoder and 2991 * intrude other's memory region. 2992 */ 2993 if (align < 0x1000) { 2994 align = 0x1000; 2995 } 2996 } else if (rb->rb_bt == sc->sc_iot) { 2997 if (align < 4) { 2998 return 1; 2999 } 3000 /* XXX: hack for avoiding ISA image */ 3001 if (mask < 0x0100) { 3002 mask = 0x3ff; 3003 addr = 0x300; 3004 } 3005 3006 } else { 3007 DPRINTF( 3008 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 3009 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 3010 return 1; 3011 /* XXX: panic here? */ 3012 } 3013 3014 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3015 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3016 return 1; 3017 } 3018 3019 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3020 3021 return 0; 3022 } 3023 3024 /* 3025 * static int 3026 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3027 * bus_space_handle_t *bshp, bus_size_t size); 3028 * 3029 * This function is called from CardBus card drivers. 3030 */ 3031 static int 3032 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3033 cardbus_chipset_tag_t ct; 3034 rbus_tag_t rb; 3035 bus_space_handle_t bsh; 3036 bus_size_t size; 3037 { 3038 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3039 bus_space_tag_t bt = rb->rb_bt; 3040 3041 pccbb_close_win(sc, bt, bsh, size); 3042 3043 if (bt == sc->sc_memt) { 3044 } else if (bt == sc->sc_iot) { 3045 } else { 3046 return 1; 3047 /* XXX: panic here? */ 3048 } 3049 3050 return rbus_space_free(rb, bsh, size, NULL); 3051 } 3052 #endif /* rbus */ 3053 3054 #if rbus 3055 3056 static int 3057 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3058 struct pccbb_softc *sc; 3059 bus_space_tag_t bst; 3060 bus_addr_t addr; 3061 bus_size_t size; 3062 bus_space_handle_t bsh; 3063 int flags; 3064 { 3065 struct pccbb_win_chain_head *head; 3066 bus_addr_t align; 3067 3068 head = &sc->sc_iowindow; 3069 align = 0x04; 3070 if (sc->sc_memt == bst) { 3071 head = &sc->sc_memwindow; 3072 align = 0x1000; 3073 DPRINTF(("using memory window, %x %x %x\n\n", 3074 sc->sc_iot, sc->sc_memt, bst)); 3075 } 3076 3077 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3078 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3079 sc->sc_dev.dv_xname, 3080 (head == &sc->sc_memwindow) ? "mem" : "io"); 3081 } 3082 pccbb_winset(align, sc, bst); 3083 3084 return 0; 3085 } 3086 3087 static int 3088 pccbb_close_win(sc, bst, bsh, size) 3089 struct pccbb_softc *sc; 3090 bus_space_tag_t bst; 3091 bus_space_handle_t bsh; 3092 bus_size_t size; 3093 { 3094 struct pccbb_win_chain_head *head; 3095 bus_addr_t align; 3096 3097 head = &sc->sc_iowindow; 3098 align = 0x04; 3099 if (sc->sc_memt == bst) { 3100 head = &sc->sc_memwindow; 3101 align = 0x1000; 3102 } 3103 3104 if (pccbb_winlist_delete(head, bsh, size)) { 3105 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3106 sc->sc_dev.dv_xname, 3107 (head == &sc->sc_memwindow) ? "mem" : "io"); 3108 } 3109 pccbb_winset(align, sc, bst); 3110 3111 return 0; 3112 } 3113 3114 static int 3115 pccbb_winlist_insert(head, start, size, bsh, flags) 3116 struct pccbb_win_chain_head *head; 3117 bus_addr_t start; 3118 bus_size_t size; 3119 bus_space_handle_t bsh; 3120 int flags; 3121 { 3122 struct pccbb_win_chain *chainp, *elem; 3123 3124 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3125 M_NOWAIT)) == NULL) 3126 return (1); /* fail */ 3127 3128 elem->wc_start = start; 3129 elem->wc_end = start + (size - 1); 3130 elem->wc_handle = bsh; 3131 elem->wc_flags = flags; 3132 3133 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3134 chainp = TAILQ_NEXT(chainp, wc_list)) { 3135 if (chainp->wc_end < start) 3136 continue; 3137 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3138 return (0); 3139 } 3140 3141 TAILQ_INSERT_TAIL(head, elem, wc_list); 3142 return (0); 3143 } 3144 3145 static int 3146 pccbb_winlist_delete(head, bsh, size) 3147 struct pccbb_win_chain_head *head; 3148 bus_space_handle_t bsh; 3149 bus_size_t size; 3150 { 3151 struct pccbb_win_chain *chainp; 3152 3153 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3154 chainp = TAILQ_NEXT(chainp, wc_list)) { 3155 if (chainp->wc_handle != bsh) 3156 continue; 3157 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3158 printf("pccbb_winlist_delete: window 0x%lx size " 3159 "inconsistent: 0x%lx, 0x%lx\n", 3160 (unsigned long)chainp->wc_start, 3161 (unsigned long)(chainp->wc_end - chainp->wc_start), 3162 (unsigned long)(size - 1)); 3163 return 1; 3164 } 3165 3166 TAILQ_REMOVE(head, chainp, wc_list); 3167 free(chainp, M_DEVBUF); 3168 3169 return 0; 3170 } 3171 3172 return 1; /* fail: no candidate to remove */ 3173 } 3174 3175 static void 3176 pccbb_winset(align, sc, bst) 3177 bus_addr_t align; 3178 struct pccbb_softc *sc; 3179 bus_space_tag_t bst; 3180 { 3181 pci_chipset_tag_t pc; 3182 pcitag_t tag; 3183 bus_addr_t mask = ~(align - 1); 3184 struct { 3185 cardbusreg_t win_start; 3186 cardbusreg_t win_limit; 3187 int win_flags; 3188 } win[2]; 3189 struct pccbb_win_chain *chainp; 3190 int offs; 3191 3192 win[0].win_start = win[1].win_start = 0xffffffff; 3193 win[0].win_limit = win[1].win_limit = 0; 3194 win[0].win_flags = win[1].win_flags = 0; 3195 3196 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3197 offs = 0x2c; 3198 if (sc->sc_memt == bst) { 3199 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3200 offs = 0x1c; 3201 } 3202 3203 if (chainp != NULL) { 3204 win[0].win_start = chainp->wc_start & mask; 3205 win[0].win_limit = chainp->wc_end & mask; 3206 win[0].win_flags = chainp->wc_flags; 3207 chainp = TAILQ_NEXT(chainp, wc_list); 3208 } 3209 3210 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3211 if (win[1].win_start == 0xffffffff) { 3212 /* window 1 is not used */ 3213 if ((win[0].win_flags == chainp->wc_flags) && 3214 (win[0].win_limit + align >= 3215 (chainp->wc_start & mask))) { 3216 /* concatenate */ 3217 win[0].win_limit = chainp->wc_end & mask; 3218 } else { 3219 /* make new window */ 3220 win[1].win_start = chainp->wc_start & mask; 3221 win[1].win_limit = chainp->wc_end & mask; 3222 win[1].win_flags = chainp->wc_flags; 3223 } 3224 continue; 3225 } 3226 3227 /* Both windows are engaged. */ 3228 if (win[0].win_flags == win[1].win_flags) { 3229 /* same flags */ 3230 if (win[0].win_flags == chainp->wc_flags) { 3231 if (win[1].win_start - (win[0].win_limit + 3232 align) < 3233 (chainp->wc_start & mask) - 3234 ((chainp->wc_end & mask) + align)) { 3235 /* 3236 * merge window 0 and 1, and set win1 3237 * to chainp 3238 */ 3239 win[0].win_limit = win[1].win_limit; 3240 win[1].win_start = 3241 chainp->wc_start & mask; 3242 win[1].win_limit = 3243 chainp->wc_end & mask; 3244 } else { 3245 win[1].win_limit = 3246 chainp->wc_end & mask; 3247 } 3248 } else { 3249 /* different flags */ 3250 3251 /* concatenate win0 and win1 */ 3252 win[0].win_limit = win[1].win_limit; 3253 /* allocate win[1] to new space */ 3254 win[1].win_start = chainp->wc_start & mask; 3255 win[1].win_limit = chainp->wc_end & mask; 3256 win[1].win_flags = chainp->wc_flags; 3257 } 3258 } else { 3259 /* the flags of win[0] and win[1] is different */ 3260 if (win[0].win_flags == chainp->wc_flags) { 3261 win[0].win_limit = chainp->wc_end & mask; 3262 /* 3263 * XXX this creates overlapping windows, so 3264 * what should the poor bridge do if one is 3265 * cachable, and the other is not? 3266 */ 3267 printf("%s: overlapping windows\n", 3268 sc->sc_dev.dv_xname); 3269 } else { 3270 win[1].win_limit = chainp->wc_end & mask; 3271 } 3272 } 3273 } 3274 3275 pc = sc->sc_pc; 3276 tag = sc->sc_tag; 3277 pci_conf_write(pc, tag, offs, win[0].win_start); 3278 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3279 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3280 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3281 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3282 pci_conf_read(pc, tag, offs), 3283 pci_conf_read(pc, tag, offs + 4) + align, 3284 pci_conf_read(pc, tag, offs + 8), 3285 pci_conf_read(pc, tag, offs + 12) + align)); 3286 3287 if (bst == sc->sc_memt) { 3288 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3289 3290 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3291 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3292 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3293 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3294 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3295 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3296 } 3297 } 3298 3299 #endif /* rbus */ 3300 3301 static void 3302 pccbb_powerhook(why, arg) 3303 int why; 3304 void *arg; 3305 { 3306 struct pccbb_softc *sc = arg; 3307 pcireg_t reg; 3308 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3309 bus_space_handle_t base_memh = sc->sc_base_memh; 3310 3311 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3312 3313 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3314 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3315 if (sc->sc_pil_intr_enable) { 3316 (void)pccbbintr_function(sc); 3317 } 3318 sc->sc_pil_intr_enable = 0; 3319 3320 /* ToDo: deactivate or suspend child devices */ 3321 3322 } 3323 3324 if (why == PWR_RESUME) { 3325 if (sc->sc_pwrmgt_offs != 0) { 3326 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3327 sc->sc_pwrmgt_offs + 4); 3328 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3329 reg & 0x100) { 3330 /* powrstate != D0 */ 3331 3332 printf("%s going back to D0 mode\n", 3333 sc->sc_dev.dv_xname); 3334 reg &= ~PCI_PMCSR_STATE_MASK; 3335 reg |= PCI_PMCSR_STATE_D0; 3336 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3337 pci_conf_write(sc->sc_pc, sc->sc_tag, 3338 sc->sc_pwrmgt_offs + 4, reg); 3339 3340 pci_conf_write(sc->sc_pc, sc->sc_tag, 3341 PCI_SOCKBASE, sc->sc_sockbase); 3342 pci_conf_write(sc->sc_pc, sc->sc_tag, 3343 PCI_BUSNUM, sc->sc_busnum); 3344 pccbb_chipinit(sc); 3345 /* setup memory and io space window for CB */ 3346 pccbb_winset(0x1000, sc, sc->sc_memt); 3347 pccbb_winset(0x04, sc, sc->sc_iot); 3348 } 3349 } 3350 3351 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3352 /* BIOS did not recover this register */ 3353 pci_conf_write (sc->sc_pc, sc->sc_tag, 3354 PCI_SOCKBASE, sc->sc_sockbase); 3355 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3356 /* BIOS did not recover this register */ 3357 pci_conf_write (sc->sc_pc, sc->sc_tag, 3358 PCI_BUSNUM, sc->sc_busnum); 3359 /* CSC Interrupt: Card detect interrupt on */ 3360 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3361 /* Card detect intr is turned on. */ 3362 reg |= CB_SOCKET_MASK_CD; 3363 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3364 /* reset interrupt */ 3365 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3366 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3367 3368 /* 3369 * check for card insertion or removal during suspend period. 3370 * XXX: the code can't cope with card swap (remove then 3371 * insert). how can we detect such situation? 3372 */ 3373 (void)pccbbintr(sc); 3374 3375 sc->sc_pil_intr_enable = 1; 3376 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3377 3378 /* ToDo: activate or wakeup child devices */ 3379 } 3380 } 3381
Indexes created Fri Sep 26 20:09:58 GMT 2025