pccbb.c revision 1.79
1 /* $NetBSD: pccbb.c,v 1.79 2002/09/30 20:37:56 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.79 2002/09/30 20:37:56 thorpej Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, NULL, NULL) 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 330 /* Ricoh chips */ 331 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 332 PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 344 /* Toshiba products */ 345 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 346 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 348 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 350 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 354 /* Cirrus Logic products */ 355 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 356 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 360 /* sentinel, or Generic chip */ 361 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 362 }; 363 364 static int 365 cb_chipset(pci_id, flagp) 366 u_int32_t pci_id; 367 int *flagp; 368 { 369 const struct yenta_chipinfo *yc; 370 371 /* Loop over except the last default entry. */ 372 for (yc = yc_chipsets; yc < yc_chipsets + 373 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 374 if (pci_id == yc->yc_id) 375 break; 376 377 if (flagp != NULL) 378 *flagp = yc->yc_flags; 379 380 return (yc->yc_chiptype); 381 } 382 383 static void 384 pccbb_shutdown(void *arg) 385 { 386 struct pccbb_softc *sc = arg; 387 pcireg_t command; 388 389 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 390 391 /* 392 * turn off power 393 * 394 * XXX - do not turn off power if chipset is TI 113X because 395 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 396 */ 397 if (sc->sc_chipset != CB_TI113X) { 398 pccbb_power((cardbus_chipset_tag_t)sc, 399 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 400 } 401 402 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 403 0); 404 405 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 406 407 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 408 PCI_COMMAND_MASTER_ENABLE); 409 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 410 411 } 412 413 void 414 pccbbattach(parent, self, aux) 415 struct device *parent; 416 struct device *self; 417 void *aux; 418 { 419 struct pccbb_softc *sc = (void *)self; 420 struct pci_attach_args *pa = aux; 421 pci_chipset_tag_t pc = pa->pa_pc; 422 pcireg_t busreg, reg, sock_base; 423 bus_addr_t sockbase; 424 char devinfo[256]; 425 int flags; 426 int pwrmgt_offs; 427 428 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 429 430 pci_devinfo(pa->pa_id, 0, 0, devinfo); 431 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 432 #ifdef CBB_DEBUG 433 printf(" (chipflags %x)", flags); 434 #endif 435 printf("\n"); 436 437 TAILQ_INIT(&sc->sc_memwindow); 438 TAILQ_INIT(&sc->sc_iowindow); 439 440 #if rbus 441 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 442 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 443 444 #if 0 445 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 446 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 447 #endif 448 #endif /* rbus */ 449 450 sc->sc_base_memh = 0; 451 452 /* power management: set D0 state */ 453 sc->sc_pwrmgt_offs = 0; 454 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 455 &pwrmgt_offs, 0)) { 456 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + 4); 457 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 458 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 459 reg &= ~PCI_PMCSR_STATE_MASK; 460 reg |= PCI_PMCSR_STATE_D0; 461 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 462 pci_conf_write(pc, pa->pa_tag, pwrmgt_offs + 4, reg); 463 } 464 465 sc->sc_pwrmgt_offs = pwrmgt_offs; 466 } 467 468 /* 469 * MAP socket registers and ExCA registers on memory-space 470 * When no valid address is set on socket base registers (on pci 471 * config space), get it not polite way. 472 */ 473 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 474 475 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 476 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 477 /* The address must be valid. */ 478 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 479 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 480 printf("%s: can't map socket base address 0x%x\n", 481 sc->sc_dev.dv_xname, sock_base); 482 /* 483 * I think it's funny: socket base registers must be 484 * mapped on memory space, but ... 485 */ 486 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 487 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 488 NULL)) { 489 printf("%s: can't map socket base address" 490 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 491 (unsigned long)sockbase); 492 /* give up... allocate reg space via rbus. */ 493 sc->sc_base_memh = 0; 494 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 495 } 496 } else { 497 DPRINTF(("%s: socket base address 0x%lx\n", 498 sc->sc_dev.dv_xname, sockbase)); 499 } 500 } 501 502 sc->sc_mem_start = 0; /* XXX */ 503 sc->sc_mem_end = 0xffffffff; /* XXX */ 504 505 /* 506 * When interrupt isn't routed correctly, give up probing cbb and do 507 * not kill pcic-compatible port. 508 */ 509 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 510 printf("%s: NOT USED because of unconfigured interrupt\n", 511 sc->sc_dev.dv_xname); 512 return; 513 } 514 515 /* 516 * When bus number isn't set correctly, give up using 32-bit CardBus 517 * mode. 518 */ 519 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 520 #if notyet 521 if (((busreg >> 8) & 0xff) == 0) { 522 printf("%s: CardBus support disabled because of unconfigured bus number\n", 523 sc->sc_dev.dv_xname); 524 flags |= PCCBB_PCMCIA_16BITONLY; 525 } 526 #endif 527 528 /* pccbb_machdep.c end */ 529 530 #if defined CBB_DEBUG 531 { 532 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 533 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 534 intrname[pa->pa_intrpin], pa->pa_intrline); 535 } 536 #endif 537 538 /* setup softc */ 539 sc->sc_pc = pc; 540 sc->sc_iot = pa->pa_iot; 541 sc->sc_memt = pa->pa_memt; 542 sc->sc_dmat = pa->pa_dmat; 543 sc->sc_tag = pa->pa_tag; 544 sc->sc_function = pa->pa_function; 545 sc->sc_sockbase = sock_base; 546 sc->sc_busnum = busreg; 547 548 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 549 550 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 551 552 shutdownhook_establish(pccbb_shutdown, sc); 553 554 /* Disable legacy register mapping. */ 555 switch (sc->sc_chipset) { 556 case CB_RX5C46X: /* fallthrough */ 557 #if 0 558 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 559 case CB_RX5C47X: 560 #endif 561 /* 562 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 563 * cannot be disabled by substituting 0 into PCI_LEGACY 564 * register. Ricoh CardBus bridges have special bits on Bridge 565 * control reg (addr 0x3e on PCI config space). 566 */ 567 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 568 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 569 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 570 break; 571 572 default: 573 /* XXX I don't know proper way to kill legacy I/O. */ 574 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 575 break; 576 } 577 578 config_defer(self, pccbb_pci_callback); 579 } 580 581 582 583 584 /* 585 * static void pccbb_pci_callback(struct device *self) 586 * 587 * The actual attach routine: get memory space for YENTA register 588 * space, setup YENTA register and route interrupt. 589 * 590 * This function should be deferred because this device may obtain 591 * memory space dynamically. This function must avoid obtaining 592 * memory area which has already kept for another device. 593 */ 594 static void 595 pccbb_pci_callback(self) 596 struct device *self; 597 { 598 struct pccbb_softc *sc = (void *)self; 599 pci_chipset_tag_t pc = sc->sc_pc; 600 pci_intr_handle_t ih; 601 const char *intrstr = NULL; 602 bus_addr_t sockbase; 603 struct cbslot_attach_args cba; 604 struct pcmciabus_attach_args paa; 605 struct cardslot_attach_args caa; 606 struct cardslot_softc *csc; 607 608 if (0 == sc->sc_base_memh) { 609 /* The socket registers aren't mapped correctly. */ 610 #if rbus 611 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 612 (sc->sc_chipset == CB_RX5C47X 613 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 614 0, &sockbase, &sc->sc_base_memh)) { 615 return; 616 } 617 sc->sc_base_memt = sc->sc_memt; 618 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 619 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 620 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 621 PCI_SOCKBASE))); 622 #else 623 sc->sc_base_memt = sc->sc_memt; 624 #if !defined CBB_PCI_BASE 625 #define CBB_PCI_BASE 0x20000000 626 #endif 627 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 628 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 629 /* cannot allocate memory space */ 630 return; 631 } 632 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 633 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 634 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 635 sc->sc_tag, PCI_SOCKBASE))); 636 sc->sc_sockbase = sockbase; 637 #endif 638 } 639 640 /* bus bridge initialization */ 641 pccbb_chipinit(sc); 642 643 /* clear data structure for child device interrupt handlers */ 644 sc->sc_pil = NULL; 645 sc->sc_pil_intr_enable = 1; 646 647 /* Map and establish the interrupt. */ 648 if (pci_intr_map(&sc->sc_pa, &ih)) { 649 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 650 return; 651 } 652 intrstr = pci_intr_string(pc, ih); 653 654 /* 655 * XXX pccbbintr should be called under the priority lower 656 * than any other hard interrputs. 657 */ 658 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 659 660 if (sc->sc_ih == NULL) { 661 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 662 if (intrstr != NULL) { 663 printf(" at %s", intrstr); 664 } 665 printf("\n"); 666 return; 667 } 668 669 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 670 powerhook_establish(pccbb_powerhook, sc); 671 672 { 673 u_int32_t sockstat; 674 675 sockstat = bus_space_read_4(sc->sc_base_memt, 676 sc->sc_base_memh, CB_SOCKET_STAT); 677 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 678 sc->sc_flags |= CBB_CARDEXIST; 679 } 680 } 681 682 /* 683 * attach cardbus 684 */ 685 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 686 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 687 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 688 689 /* initialize cbslot_attach */ 690 cba.cba_busname = "cardbus"; 691 cba.cba_iot = sc->sc_iot; 692 cba.cba_memt = sc->sc_memt; 693 cba.cba_dmat = sc->sc_dmat; 694 cba.cba_bus = (busreg >> 8) & 0x0ff; 695 cba.cba_cc = (void *)sc; 696 cba.cba_cf = &pccbb_funcs; 697 cba.cba_intrline = sc->sc_pa.pa_intrline; 698 699 #if rbus 700 cba.cba_rbus_iot = sc->sc_rbus_iot; 701 cba.cba_rbus_memt = sc->sc_rbus_memt; 702 #endif 703 704 cba.cba_cacheline = PCI_CACHELINE(bhlc); 705 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 706 707 if (bootverbose) { 708 printf("%s: cacheline 0x%x lattimer 0x%x\n", 709 sc->sc_dev.dv_xname, cba.cba_cacheline, 710 cba.cba_lattimer); 711 printf("%s: bhlc 0x%x lscp 0x%x\n", 712 sc->sc_dev.dv_xname, bhlc, busreg); 713 } 714 #if defined SHOW_REGS 715 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 716 sc->sc_base_memh); 717 #endif 718 } 719 720 pccbb_pcmcia_attach_setup(sc, &paa); 721 caa.caa_cb_attach = NULL; 722 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 723 caa.caa_cb_attach = &cba; 724 } 725 caa.caa_16_attach = &paa; 726 caa.caa_ph = &sc->sc_pcmcia_h; 727 728 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 729 DPRINTF(("pccbbattach: found cardslot\n")); 730 sc->sc_csc = csc; 731 } 732 733 return; 734 } 735 736 737 738 739 740 /* 741 * static void pccbb_chipinit(struct pccbb_softc *sc) 742 * 743 * This function initialize YENTA chip registers listed below: 744 * 1) PCI command reg, 745 * 2) PCI and CardBus latency timer, 746 * 3) route PCI interrupt, 747 * 4) close all memory and io windows. 748 * 5) turn off bus power. 749 * 6) card detect interrupt on. 750 * 7) clear interrupt 751 */ 752 static void 753 pccbb_chipinit(sc) 754 struct pccbb_softc *sc; 755 { 756 pci_chipset_tag_t pc = sc->sc_pc; 757 pcitag_t tag = sc->sc_tag; 758 bus_space_tag_t bmt = sc->sc_base_memt; 759 bus_space_handle_t bmh = sc->sc_base_memh; 760 pcireg_t reg; 761 762 /* 763 * Set PCI command reg. 764 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 765 */ 766 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 767 /* I believe it is harmless. */ 768 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 769 PCI_COMMAND_MASTER_ENABLE); 770 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 771 772 /* 773 * Set CardBus latency timer. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 776 if (PCI_CB_LATENCY(reg) < 0x20) { 777 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 778 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 779 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 780 } 781 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 782 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 783 784 /* 785 * Set PCI latency timer. 786 */ 787 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 788 if (PCI_LATTIMER(reg) < 0x10) { 789 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 790 reg |= (0x10 << PCI_LATTIMER_SHIFT); 791 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 792 } 793 DPRINTF(("PCI latency timer 0x%x (%x)\n", 794 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 795 796 797 /* Route functional interrupts to PCI. */ 798 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 799 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 800 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 801 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 802 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 803 804 switch (sc->sc_chipset) { 805 case CB_TI113X: 806 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 807 /* This bit is shared, but may read as 0 on some chips, so set 808 it explicitly on both functions. */ 809 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 810 /* CSC intr enable */ 811 reg |= PCI113X_CBCTRL_PCI_CSC; 812 /* functional intr prohibit | prohibit ISA routing */ 813 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 814 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 815 break; 816 817 case CB_TI12XX: 818 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 819 reg |= PCI12XX_SYSCTRL_VCCPROT; 820 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 821 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 822 reg |= PCI12XX_CBCTRL_CSC; 823 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 824 break; 825 826 case CB_TOPIC95B: 827 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 828 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 829 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 830 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 831 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 832 sc->sc_dev.dv_xname, reg)); 833 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 834 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 835 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 836 DPRINTF(("0x%x\n", reg)); 837 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 838 break; 839 840 case CB_TOPIC97: 841 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 842 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 843 sc->sc_dev.dv_xname, reg)); 844 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 845 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 846 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 847 reg |= TOPIC97_SLOT_CTRL_PCIINT; 848 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 849 DPRINTF(("0x%x\n", reg)); 850 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 851 /* make sure to assert LV card support bits */ 852 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 853 0x800 + 0x3e, 854 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 855 0x800 + 0x3e) | 0x03); 856 break; 857 } 858 859 /* Close all memory and I/O windows. */ 860 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 861 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 862 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 863 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 864 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 865 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 866 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 867 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 868 869 /* reset 16-bit pcmcia bus */ 870 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 871 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 872 873 /* turn off power */ 874 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 875 876 /* CSC Interrupt: Card detect interrupt on */ 877 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 878 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 879 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 880 /* reset interrupt */ 881 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 882 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 883 } 884 885 886 887 888 /* 889 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 890 * struct pcmciabus_attach_args *paa) 891 * 892 * This function attaches 16-bit PCcard bus. 893 */ 894 STATIC void 895 pccbb_pcmcia_attach_setup(sc, paa) 896 struct pccbb_softc *sc; 897 struct pcmciabus_attach_args *paa; 898 { 899 struct pcic_handle *ph = &sc->sc_pcmcia_h; 900 #if rbus 901 rbus_tag_t rb; 902 #endif 903 904 /* initialize pcmcia part in pccbb_softc */ 905 ph->ph_parent = (struct device *)sc; 906 ph->sock = sc->sc_function; 907 ph->flags = 0; 908 ph->shutdown = 0; 909 ph->ih_irq = sc->sc_pa.pa_intrline; 910 ph->ph_bus_t = sc->sc_base_memt; 911 ph->ph_bus_h = sc->sc_base_memh; 912 ph->ph_read = pccbb_pcmcia_read; 913 ph->ph_write = pccbb_pcmcia_write; 914 sc->sc_pct = &pccbb_pcmcia_funcs; 915 916 /* 917 * We need to do a few things here: 918 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 919 * setting the IRQ numbers to 0. 920 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 921 * routing of CSC interrupts (e.g. card removal) to PCI while in 922 * PCMCIA mode. We just leave this set all the time. 923 * 3) Enable card insertion/removal interrupts in case the chip also 924 * needs that while in PCMCIA mode. 925 * 4) Clear any pending CSC interrupt. 926 */ 927 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 928 if (sc->sc_chipset == CB_TI113X) { 929 Pcic_write(ph, PCIC_CSC_INTR, 0); 930 } else { 931 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 932 Pcic_read(ph, PCIC_CSC); 933 } 934 935 /* initialize pcmcia bus attachment */ 936 paa->paa_busname = "pcmcia"; 937 paa->pct = sc->sc_pct; 938 paa->pch = ph; 939 paa->iobase = 0; /* I don't use them */ 940 paa->iosize = 0; 941 #if rbus 942 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 943 paa->iobase = rb->rb_start + rb->rb_offset; 944 paa->iosize = rb->rb_end - rb->rb_start; 945 #endif 946 947 return; 948 } 949 950 #if 0 951 STATIC void 952 pccbb_pcmcia_attach_card(ph) 953 struct pcic_handle *ph; 954 { 955 if (ph->flags & PCIC_FLAG_CARDP) { 956 panic("pccbb_pcmcia_attach_card: already attached"); 957 } 958 959 /* call the MI attach function */ 960 pcmcia_card_attach(ph->pcmcia); 961 962 ph->flags |= PCIC_FLAG_CARDP; 963 } 964 965 STATIC void 966 pccbb_pcmcia_detach_card(ph, flags) 967 struct pcic_handle *ph; 968 int flags; 969 { 970 if (!(ph->flags & PCIC_FLAG_CARDP)) { 971 panic("pccbb_pcmcia_detach_card: already detached"); 972 } 973 974 ph->flags &= ~PCIC_FLAG_CARDP; 975 976 /* call the MI detach function */ 977 pcmcia_card_detach(ph->pcmcia, flags); 978 } 979 #endif 980 981 /* 982 * int pccbbintr(arg) 983 * void *arg; 984 * This routine handles the interrupt from Yenta PCI-CardBus bridge 985 * itself. 986 */ 987 int 988 pccbbintr(arg) 989 void *arg; 990 { 991 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 992 u_int32_t sockevent, sockstate; 993 bus_space_tag_t memt = sc->sc_base_memt; 994 bus_space_handle_t memh = sc->sc_base_memh; 995 struct pcic_handle *ph = &sc->sc_pcmcia_h; 996 997 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 998 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 999 Pcic_read(ph, PCIC_CSC); 1000 1001 if (sockevent == 0) { 1002 /* This intr is not for me: it may be for my child devices. */ 1003 if (sc->sc_pil_intr_enable) { 1004 return pccbbintr_function(sc); 1005 } else { 1006 return 0; 1007 } 1008 } 1009 1010 if (sockevent & CB_SOCKET_EVENT_CD) { 1011 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1012 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 1013 /* A card should be removed. */ 1014 if (sc->sc_flags & CBB_CARDEXIST) { 1015 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1016 sockevent)); 1017 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1018 sc->sc_flags &= ~CBB_CARDEXIST; 1019 if (sc->sc_csc->sc_status & 1020 CARDSLOT_STATUS_CARD_16) { 1021 #if 0 1022 struct pcic_handle *ph = 1023 &sc->sc_pcmcia_h; 1024 1025 pcmcia_card_deactivate(ph->pcmcia); 1026 pccbb_pcmcia_socket_disable(ph); 1027 pccbb_pcmcia_detach_card(ph, 1028 DETACH_FORCE); 1029 #endif 1030 cardslot_event_throw(sc->sc_csc, 1031 CARDSLOT_EVENT_REMOVAL_16); 1032 } else if (sc->sc_csc->sc_status & 1033 CARDSLOT_STATUS_CARD_CB) { 1034 /* Cardbus intr removed */ 1035 cardslot_event_throw(sc->sc_csc, 1036 CARDSLOT_EVENT_REMOVAL_CB); 1037 } 1038 } else if (sc->sc_flags & CBB_INSERTING) { 1039 sc->sc_flags &= ~CBB_INSERTING; 1040 callout_stop(&sc->sc_insert_ch); 1041 } 1042 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1043 /* 1044 * The pccbbintr may called from powerdown hook when 1045 * the system resumed, to detect the card 1046 * insertion/removal during suspension. 1047 */ 1048 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1049 if (sc->sc_flags & CBB_INSERTING) { 1050 callout_stop(&sc->sc_insert_ch); 1051 } 1052 callout_reset(&sc->sc_insert_ch, hz / 5, 1053 pci113x_insert, sc); 1054 sc->sc_flags |= CBB_INSERTING; 1055 } 1056 } 1057 1058 return (1); 1059 } 1060 1061 /* 1062 * static int pccbbintr_function(struct pccbb_softc *sc) 1063 * 1064 * This function calls each interrupt handler registered at the 1065 * bridge. The interrupt handlers are called in registered order. 1066 */ 1067 static int 1068 pccbbintr_function(sc) 1069 struct pccbb_softc *sc; 1070 { 1071 int retval = 0, val; 1072 struct pccbb_intrhand_list *pil; 1073 int s, splchanged; 1074 1075 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1076 /* 1077 * XXX priority change. gross. I use if-else 1078 * sentense instead of switch-case sentense because of 1079 * avoiding duplicate case value error. More than one 1080 * IPL_XXX use same value. It depends on 1081 * implimentation. 1082 */ 1083 splchanged = 1; 1084 if (pil->pil_level == IPL_SERIAL) { 1085 s = splserial(); 1086 } else if (pil->pil_level == IPL_HIGH) { 1087 s = splhigh(); 1088 } else if (pil->pil_level == IPL_CLOCK) { 1089 s = splclock(); 1090 } else if (pil->pil_level == IPL_AUDIO) { 1091 s = splaudio(); 1092 } else if (pil->pil_level == IPL_IMP) { 1093 s = splvm(); /* XXX */ 1094 } else if (pil->pil_level == IPL_TTY) { 1095 s = spltty(); 1096 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1097 s = splsoftserial(); 1098 } else if (pil->pil_level == IPL_NET) { 1099 s = splnet(); 1100 } else { 1101 splchanged = 0; 1102 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1103 } 1104 1105 val = (*pil->pil_func)(pil->pil_arg); 1106 1107 if (splchanged != 0) { 1108 splx(s); 1109 } 1110 1111 retval = retval == 1 ? 1 : 1112 retval == 0 ? val : val != 0 ? val : retval; 1113 } 1114 1115 return retval; 1116 } 1117 1118 static void 1119 pci113x_insert(arg) 1120 void *arg; 1121 { 1122 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1123 u_int32_t sockevent, sockstate; 1124 1125 if (!(sc->sc_flags & CBB_INSERTING)) { 1126 /* We add a card only under inserting state. */ 1127 return; 1128 } 1129 sc->sc_flags &= ~CBB_INSERTING; 1130 1131 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1132 CB_SOCKET_EVENT); 1133 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1134 CB_SOCKET_STAT); 1135 1136 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1137 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1138 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1139 sc->sc_flags |= CBB_CARDEXIST; 1140 /* call pccard interrupt handler here */ 1141 if (sockstate & CB_SOCKET_STAT_16BIT) { 1142 /* 16-bit card found */ 1143 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1144 cardslot_event_throw(sc->sc_csc, 1145 CARDSLOT_EVENT_INSERTION_16); 1146 } else if (sockstate & CB_SOCKET_STAT_CB) { 1147 /* cardbus card found */ 1148 /* cardbus_attach_card(sc->sc_csc); */ 1149 cardslot_event_throw(sc->sc_csc, 1150 CARDSLOT_EVENT_INSERTION_CB); 1151 } else { 1152 /* who are you? */ 1153 } 1154 } else { 1155 callout_reset(&sc->sc_insert_ch, hz / 10, 1156 pci113x_insert, sc); 1157 } 1158 } 1159 1160 #define PCCBB_PCMCIA_OFFSET 0x800 1161 static u_int8_t 1162 pccbb_pcmcia_read(ph, reg) 1163 struct pcic_handle *ph; 1164 int reg; 1165 { 1166 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1167 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1168 1169 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1170 PCCBB_PCMCIA_OFFSET + reg); 1171 } 1172 1173 static void 1174 pccbb_pcmcia_write(ph, reg, val) 1175 struct pcic_handle *ph; 1176 int reg; 1177 u_int8_t val; 1178 { 1179 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1180 val); 1181 1182 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1183 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1184 } 1185 1186 /* 1187 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1188 */ 1189 STATIC int 1190 pccbb_ctrl(ct, command) 1191 cardbus_chipset_tag_t ct; 1192 int command; 1193 { 1194 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1195 1196 switch (command) { 1197 case CARDBUS_CD: 1198 if (2 == pccbb_detect_card(sc)) { 1199 int retval = 0; 1200 int status = cb_detect_voltage(sc); 1201 if (PCCARD_VCC_5V & status) { 1202 retval |= CARDBUS_5V_CARD; 1203 } 1204 if (PCCARD_VCC_3V & status) { 1205 retval |= CARDBUS_3V_CARD; 1206 } 1207 if (PCCARD_VCC_XV & status) { 1208 retval |= CARDBUS_XV_CARD; 1209 } 1210 if (PCCARD_VCC_YV & status) { 1211 retval |= CARDBUS_YV_CARD; 1212 } 1213 return retval; 1214 } else { 1215 return 0; 1216 } 1217 break; 1218 case CARDBUS_RESET: 1219 return cb_reset(sc); 1220 break; 1221 case CARDBUS_IO_ENABLE: /* fallthrough */ 1222 case CARDBUS_IO_DISABLE: /* fallthrough */ 1223 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1224 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1225 case CARDBUS_BM_ENABLE: /* fallthrough */ 1226 case CARDBUS_BM_DISABLE: /* fallthrough */ 1227 /* XXX: I think we don't need to call this function below. */ 1228 return pccbb_cardenable(sc, command); 1229 break; 1230 } 1231 1232 return 0; 1233 } 1234 1235 /* 1236 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1237 * This function returns true when it succeeds and returns false when 1238 * it fails. 1239 */ 1240 STATIC int 1241 pccbb_power(ct, command) 1242 cardbus_chipset_tag_t ct; 1243 int command; 1244 { 1245 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1246 1247 u_int32_t status, sock_ctrl, reg_ctrl; 1248 bus_space_tag_t memt = sc->sc_base_memt; 1249 bus_space_handle_t memh = sc->sc_base_memh; 1250 1251 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1252 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1253 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1254 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1258 "UNKNOWN", 1259 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1260 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1261 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1263 "UNKNOWN", command)); 1264 1265 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1266 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1267 1268 switch (command & CARDBUS_VCCMASK) { 1269 case CARDBUS_VCC_UC: 1270 break; 1271 case CARDBUS_VCC_5V: 1272 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1273 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1274 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1275 } else { 1276 printf("%s: BAD voltage request: no 5 V card\n", 1277 sc->sc_dev.dv_xname); 1278 } 1279 break; 1280 case CARDBUS_VCC_3V: 1281 if (CB_SOCKET_STAT_3VCARD & status) { 1282 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1283 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1284 } else { 1285 printf("%s: BAD voltage request: no 3.3 V card\n", 1286 sc->sc_dev.dv_xname); 1287 } 1288 break; 1289 case CARDBUS_VCC_0V: 1290 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1291 break; 1292 default: 1293 return 0; /* power NEVER changed */ 1294 break; 1295 } 1296 1297 switch (command & CARDBUS_VPPMASK) { 1298 case CARDBUS_VPP_UC: 1299 break; 1300 case CARDBUS_VPP_0V: 1301 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1302 break; 1303 case CARDBUS_VPP_VCC: 1304 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1305 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1306 break; 1307 case CARDBUS_VPP_12V: 1308 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1309 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1310 break; 1311 } 1312 1313 #if 0 1314 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1315 #endif 1316 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1317 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1318 1319 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1320 printf 1321 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1322 sc->sc_dev.dv_xname, sock_ctrl, status); 1323 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1324 (command & CARDBUS_VCCMASK) == 1325 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1326 CARDBUS_VCCMASK) == 1327 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1328 CARDBUS_VCCMASK) == 1329 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1330 CARDBUS_VCCMASK) == 1331 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1332 CARDBUS_VCCMASK) == 1333 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1334 CARDBUS_VCCMASK) == 1335 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1336 (command & CARDBUS_VPPMASK) == 1337 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1338 CARDBUS_VPPMASK) == 1339 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1340 CARDBUS_VPPMASK) == 1341 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1342 CARDBUS_VPPMASK) == 1343 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1344 #if 0 1345 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1346 u_int32_t force = 1347 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1348 /* Reset Bad Vcc request */ 1349 force &= ~CB_SOCKET_FORCE_BADVCC; 1350 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1351 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1352 CB_SOCKET_STAT)); 1353 return 1; 1354 } 1355 #endif 1356 return 0; 1357 } 1358 1359 if (sc->sc_chipset == CB_TOPIC97) { 1360 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1361 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1362 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1363 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1364 else 1365 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1366 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1367 } 1368 1369 /* 1370 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1371 * time is 20 ms, some PC-Card bridge requires longer duration. 1372 */ 1373 #if 0 /* XXX called on interrupt context */ 1374 DELAY_MS(300, sc); 1375 #else 1376 delay(300 * 1000); 1377 #endif 1378 1379 return 1; /* power changed correctly */ 1380 } 1381 1382 #if defined CB_PCMCIA_POLL 1383 struct cb_poll_str { 1384 void *arg; 1385 int (*func) __P((void *)); 1386 int level; 1387 pccard_chipset_tag_t ct; 1388 int count; 1389 struct callout poll_ch; 1390 }; 1391 1392 static struct cb_poll_str cb_poll[10]; 1393 static int cb_poll_n = 0; 1394 1395 static void cb_pcmcia_poll __P((void *arg)); 1396 1397 static void 1398 cb_pcmcia_poll(arg) 1399 void *arg; 1400 { 1401 struct cb_poll_str *poll = arg; 1402 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1403 struct pccbb_softc *sc = psc->cpc_parent; 1404 int s; 1405 u_int32_t spsr; /* socket present-state reg */ 1406 1407 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1408 switch (poll->level) { 1409 case IPL_NET: 1410 s = splnet(); 1411 break; 1412 case IPL_BIO: 1413 s = splbio(); 1414 break; 1415 case IPL_TTY: /* fallthrough */ 1416 default: 1417 s = spltty(); 1418 break; 1419 } 1420 1421 spsr = 1422 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1423 CB_SOCKET_STAT); 1424 1425 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1426 if (!(spsr & 0x40)) { /* CINT low */ 1427 #else 1428 if (1) { 1429 #endif 1430 if ((*poll->func) (poll->arg) == 1) { 1431 ++poll->count; 1432 printf("intr: reported from poller, 0x%x\n", spsr); 1433 #if defined LEVEL2 1434 } else { 1435 printf("intr: miss! 0x%x\n", spsr); 1436 #endif 1437 } 1438 } 1439 splx(s); 1440 } 1441 #endif /* defined CB_PCMCIA_POLL */ 1442 1443 /* 1444 * static int pccbb_detect_card(struct pccbb_softc *sc) 1445 * return value: 0 if no card exists. 1446 * 1 if 16-bit card exists. 1447 * 2 if cardbus card exists. 1448 */ 1449 static int 1450 pccbb_detect_card(sc) 1451 struct pccbb_softc *sc; 1452 { 1453 bus_space_handle_t base_memh = sc->sc_base_memh; 1454 bus_space_tag_t base_memt = sc->sc_base_memt; 1455 u_int32_t sockstat = 1456 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1457 int retval = 0; 1458 1459 /* CD1 and CD2 asserted */ 1460 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1461 /* card must be present */ 1462 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1463 /* NOTACARD DEASSERTED */ 1464 if (CB_SOCKET_STAT_CB & sockstat) { 1465 /* CardBus mode */ 1466 retval = 2; 1467 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1468 /* 16-bit mode */ 1469 retval = 1; 1470 } 1471 } 1472 } 1473 return retval; 1474 } 1475 1476 /* 1477 * STATIC int cb_reset(struct pccbb_softc *sc) 1478 * This function resets CardBus card. 1479 */ 1480 STATIC int 1481 cb_reset(sc) 1482 struct pccbb_softc *sc; 1483 { 1484 /* 1485 * Reset Assert at least 20 ms 1486 * Some machines request longer duration. 1487 */ 1488 int reset_duration = 1489 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1490 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1491 1492 /* Reset bit Assert (bit 6 at 0x3E) */ 1493 bcr |= CB_BCR_RESET_ENABLE; 1494 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1495 DELAY_MS(reset_duration, sc); 1496 1497 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1498 /* Reset bit Deassert (bit 6 at 0x3E) */ 1499 bcr &= ~CB_BCR_RESET_ENABLE; 1500 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1501 DELAY_MS(reset_duration, sc); 1502 } 1503 /* No card found on the slot. Keep Reset. */ 1504 return 1; 1505 } 1506 1507 /* 1508 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1509 * This function detect card Voltage. 1510 */ 1511 STATIC int 1512 cb_detect_voltage(sc) 1513 struct pccbb_softc *sc; 1514 { 1515 u_int32_t psr; /* socket present-state reg */ 1516 bus_space_tag_t iot = sc->sc_base_memt; 1517 bus_space_handle_t ioh = sc->sc_base_memh; 1518 int vol = PCCARD_VCC_UKN; /* set 0 */ 1519 1520 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1521 1522 if (0x400u & psr) { 1523 vol |= PCCARD_VCC_5V; 1524 } 1525 if (0x800u & psr) { 1526 vol |= PCCARD_VCC_3V; 1527 } 1528 1529 return vol; 1530 } 1531 1532 STATIC int 1533 cbbprint(aux, pcic) 1534 void *aux; 1535 const char *pcic; 1536 { 1537 /* 1538 struct cbslot_attach_args *cba = aux; 1539 1540 if (cba->cba_slot >= 0) { 1541 printf(" slot %d", cba->cba_slot); 1542 } 1543 */ 1544 return UNCONF; 1545 } 1546 1547 /* 1548 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1549 * This function enables and disables the card 1550 */ 1551 STATIC int 1552 pccbb_cardenable(sc, function) 1553 struct pccbb_softc *sc; 1554 int function; 1555 { 1556 u_int32_t command = 1557 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1558 1559 DPRINTF(("pccbb_cardenable:")); 1560 switch (function) { 1561 case CARDBUS_IO_ENABLE: 1562 command |= PCI_COMMAND_IO_ENABLE; 1563 break; 1564 case CARDBUS_IO_DISABLE: 1565 command &= ~PCI_COMMAND_IO_ENABLE; 1566 break; 1567 case CARDBUS_MEM_ENABLE: 1568 command |= PCI_COMMAND_MEM_ENABLE; 1569 break; 1570 case CARDBUS_MEM_DISABLE: 1571 command &= ~PCI_COMMAND_MEM_ENABLE; 1572 break; 1573 case CARDBUS_BM_ENABLE: 1574 command |= PCI_COMMAND_MASTER_ENABLE; 1575 break; 1576 case CARDBUS_BM_DISABLE: 1577 command &= ~PCI_COMMAND_MASTER_ENABLE; 1578 break; 1579 default: 1580 return 0; 1581 } 1582 1583 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1584 DPRINTF((" command reg 0x%x\n", command)); 1585 return 1; 1586 } 1587 1588 #if !rbus 1589 /* 1590 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1591 */ 1592 static int 1593 pccbb_io_open(ct, win, start, end) 1594 cardbus_chipset_tag_t ct; 1595 int win; 1596 u_int32_t start, end; 1597 { 1598 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1599 int basereg; 1600 int limitreg; 1601 1602 if ((win < 0) || (win > 2)) { 1603 #if defined DIAGNOSTIC 1604 printf("cardbus_io_open: window out of range %d\n", win); 1605 #endif 1606 return 0; 1607 } 1608 1609 basereg = win * 8 + 0x2c; 1610 limitreg = win * 8 + 0x30; 1611 1612 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1613 start, basereg, end, limitreg)); 1614 1615 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1616 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1617 return 1; 1618 } 1619 1620 /* 1621 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1622 */ 1623 static int 1624 pccbb_io_close(ct, win) 1625 cardbus_chipset_tag_t ct; 1626 int win; 1627 { 1628 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1629 int basereg; 1630 int limitreg; 1631 1632 if ((win < 0) || (win > 2)) { 1633 #if defined DIAGNOSTIC 1634 printf("cardbus_io_close: window out of range %d\n", win); 1635 #endif 1636 return 0; 1637 } 1638 1639 basereg = win * 8 + 0x2c; 1640 limitreg = win * 8 + 0x30; 1641 1642 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1643 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1644 return 1; 1645 } 1646 1647 /* 1648 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1649 */ 1650 static int 1651 pccbb_mem_open(ct, win, start, end) 1652 cardbus_chipset_tag_t ct; 1653 int win; 1654 u_int32_t start, end; 1655 { 1656 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1657 int basereg; 1658 int limitreg; 1659 1660 if ((win < 0) || (win > 2)) { 1661 #if defined DIAGNOSTIC 1662 printf("cardbus_mem_open: window out of range %d\n", win); 1663 #endif 1664 return 0; 1665 } 1666 1667 basereg = win * 8 + 0x1c; 1668 limitreg = win * 8 + 0x20; 1669 1670 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1671 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1672 return 1; 1673 } 1674 1675 /* 1676 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1677 */ 1678 static int 1679 pccbb_mem_close(ct, win) 1680 cardbus_chipset_tag_t ct; 1681 int win; 1682 { 1683 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1684 int basereg; 1685 int limitreg; 1686 1687 if ((win < 0) || (win > 2)) { 1688 #if defined DIAGNOSTIC 1689 printf("cardbus_mem_close: window out of range %d\n", win); 1690 #endif 1691 return 0; 1692 } 1693 1694 basereg = win * 8 + 0x1c; 1695 limitreg = win * 8 + 0x20; 1696 1697 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1698 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1699 return 1; 1700 } 1701 #endif 1702 1703 /* 1704 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1705 * int irq, 1706 * int level, 1707 * int (* func) __P((void *)), 1708 * void *arg) 1709 * 1710 * This function registers an interrupt handler at the bridge, in 1711 * order not to call the interrupt handlers of child devices when 1712 * a card-deletion interrupt occurs. 1713 * 1714 * The arguments irq and level are not used. 1715 */ 1716 static void * 1717 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1718 cardbus_chipset_tag_t ct; 1719 int irq, level; 1720 int (*func) __P((void *)); 1721 void *arg; 1722 { 1723 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1724 1725 return pccbb_intr_establish(sc, irq, level, func, arg); 1726 } 1727 1728 1729 /* 1730 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1731 * void *ih) 1732 * 1733 * This function removes an interrupt handler pointed by ih. 1734 */ 1735 static void 1736 pccbb_cb_intr_disestablish(ct, ih) 1737 cardbus_chipset_tag_t ct; 1738 void *ih; 1739 { 1740 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1741 1742 pccbb_intr_disestablish(sc, ih); 1743 } 1744 1745 1746 void 1747 pccbb_intr_route(sc) 1748 struct pccbb_softc *sc; 1749 { 1750 pcireg_t reg; 1751 1752 /* initialize bridge intr routing */ 1753 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1754 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1755 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1756 1757 switch (sc->sc_chipset) { 1758 case CB_TI113X: 1759 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1760 /* functional intr enabled */ 1761 reg |= PCI113X_CBCTRL_PCI_INTR; 1762 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1763 break; 1764 default: 1765 break; 1766 } 1767 } 1768 1769 /* 1770 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1771 * int irq, 1772 * int level, 1773 * int (* func) __P((void *)), 1774 * void *arg) 1775 * 1776 * This function registers an interrupt handler at the bridge, in 1777 * order not to call the interrupt handlers of child devices when 1778 * a card-deletion interrupt occurs. 1779 * 1780 * The arguments irq is not used because pccbb selects intr vector. 1781 */ 1782 static void * 1783 pccbb_intr_establish(sc, irq, level, func, arg) 1784 struct pccbb_softc *sc; 1785 int irq, level; 1786 int (*func) __P((void *)); 1787 void *arg; 1788 { 1789 struct pccbb_intrhand_list *pil, *newpil; 1790 1791 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1792 1793 if (sc->sc_pil == NULL) { 1794 pccbb_intr_route(sc); 1795 1796 } 1797 1798 /* 1799 * Allocate a room for interrupt handler structure. 1800 */ 1801 if (NULL == (newpil = 1802 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1803 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1804 return NULL; 1805 } 1806 1807 newpil->pil_func = func; 1808 newpil->pil_arg = arg; 1809 newpil->pil_level = level; 1810 newpil->pil_next = NULL; 1811 1812 if (sc->sc_pil == NULL) { 1813 sc->sc_pil = newpil; 1814 } else { 1815 for (pil = sc->sc_pil; pil->pil_next != NULL; 1816 pil = pil->pil_next); 1817 pil->pil_next = newpil; 1818 } 1819 1820 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1821 1822 return newpil; 1823 } 1824 1825 /* 1826 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1827 * void *ih) 1828 * 1829 * This function removes an interrupt handler pointed by ih. 1830 */ 1831 static void 1832 pccbb_intr_disestablish(sc, ih) 1833 struct pccbb_softc *sc; 1834 void *ih; 1835 { 1836 struct pccbb_intrhand_list *pil, **pil_prev; 1837 pcireg_t reg; 1838 1839 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1840 1841 pil_prev = &sc->sc_pil; 1842 1843 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1844 if (pil == ih) { 1845 *pil_prev = pil->pil_next; 1846 free(pil, M_DEVBUF); 1847 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1848 break; 1849 } 1850 pil_prev = &pil->pil_next; 1851 } 1852 1853 if (sc->sc_pil == NULL) { 1854 /* No interrupt handlers */ 1855 1856 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1857 1858 /* stop routing PCI intr */ 1859 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1860 reg |= CB_BCR_INTR_IREQ_ENABLE; 1861 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1862 1863 switch (sc->sc_chipset) { 1864 case CB_TI113X: 1865 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1866 /* functional intr disabled */ 1867 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1868 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1869 break; 1870 default: 1871 break; 1872 } 1873 } 1874 } 1875 1876 #if defined SHOW_REGS 1877 static void 1878 cb_show_regs(pc, tag, memt, memh) 1879 pci_chipset_tag_t pc; 1880 pcitag_t tag; 1881 bus_space_tag_t memt; 1882 bus_space_handle_t memh; 1883 { 1884 int i; 1885 printf("PCI config regs:"); 1886 for (i = 0; i < 0x50; i += 4) { 1887 if (i % 16 == 0) { 1888 printf("\n 0x%02x:", i); 1889 } 1890 printf(" %08x", pci_conf_read(pc, tag, i)); 1891 } 1892 for (i = 0x80; i < 0xb0; i += 4) { 1893 if (i % 16 == 0) { 1894 printf("\n 0x%02x:", i); 1895 } 1896 printf(" %08x", pci_conf_read(pc, tag, i)); 1897 } 1898 1899 if (memh == 0) { 1900 printf("\n"); 1901 return; 1902 } 1903 1904 printf("\nsocket regs:"); 1905 for (i = 0; i <= 0x10; i += 0x04) { 1906 printf(" %08x", bus_space_read_4(memt, memh, i)); 1907 } 1908 printf("\nExCA regs:"); 1909 for (i = 0; i < 0x08; ++i) { 1910 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1911 } 1912 printf("\n"); 1913 return; 1914 } 1915 #endif 1916 1917 /* 1918 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1919 * int busno, int devno, int function) 1920 * This is the function to make a tag to access config space of 1921 * a CardBus Card. It works same as pci_conf_read. 1922 */ 1923 static cardbustag_t 1924 pccbb_make_tag(cc, busno, devno, function) 1925 cardbus_chipset_tag_t cc; 1926 int busno, devno, function; 1927 { 1928 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1929 1930 return pci_make_tag(sc->sc_pc, busno, devno, function); 1931 } 1932 1933 static void 1934 pccbb_free_tag(cc, tag) 1935 cardbus_chipset_tag_t cc; 1936 cardbustag_t tag; 1937 { 1938 } 1939 1940 /* 1941 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1942 * cardbustag_t tag, int offset) 1943 * This is the function to read the config space of a CardBus Card. 1944 * It works same as pci_conf_read. 1945 */ 1946 static cardbusreg_t 1947 pccbb_conf_read(cc, tag, offset) 1948 cardbus_chipset_tag_t cc; 1949 cardbustag_t tag; 1950 int offset; /* register offset */ 1951 { 1952 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1953 1954 return pci_conf_read(sc->sc_pc, tag, offset); 1955 } 1956 1957 /* 1958 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1959 * int offs, cardbusreg_t val) 1960 * This is the function to write the config space of a CardBus Card. 1961 * It works same as pci_conf_write. 1962 */ 1963 static void 1964 pccbb_conf_write(cc, tag, reg, val) 1965 cardbus_chipset_tag_t cc; 1966 cardbustag_t tag; 1967 int reg; /* register offset */ 1968 cardbusreg_t val; 1969 { 1970 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1971 1972 pci_conf_write(sc->sc_pc, tag, reg, val); 1973 } 1974 1975 #if 0 1976 STATIC int 1977 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1978 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1979 int speed, int flags, 1980 bus_space_handle_t * iohp) 1981 #endif 1982 /* 1983 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1984 * bus_addr_t start, bus_size_t size, 1985 * bus_size_t align, 1986 * struct pcmcia_io_handle *pcihp 1987 * 1988 * This function only allocates I/O region for pccard. This function 1989 * never maps the allocated region to pccard I/O area. 1990 * 1991 * XXX: The interface of this function is not very good, I believe. 1992 */ 1993 STATIC int 1994 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1995 pcmcia_chipset_handle_t pch; 1996 bus_addr_t start; /* start address */ 1997 bus_size_t size; 1998 bus_size_t align; 1999 struct pcmcia_io_handle *pcihp; 2000 { 2001 struct pcic_handle *ph = (struct pcic_handle *)pch; 2002 bus_addr_t ioaddr; 2003 int flags = 0; 2004 bus_space_tag_t iot; 2005 bus_space_handle_t ioh; 2006 bus_addr_t mask; 2007 #if rbus 2008 rbus_tag_t rb; 2009 #endif 2010 if (align == 0) { 2011 align = size; /* XXX: funny??? */ 2012 } 2013 2014 if (start != 0) { 2015 /* XXX: assume all card decode lower 10 bits by its hardware */ 2016 mask = 0x3ff; 2017 /* enforce to use only masked address */ 2018 start &= mask; 2019 } else { 2020 /* 2021 * calculate mask: 2022 * 1. get the most significant bit of size (call it msb). 2023 * 2. compare msb with the value of size. 2024 * 3. if size is larger, shift msb left once. 2025 * 4. obtain mask value to decrement msb. 2026 */ 2027 bus_size_t size_tmp = size; 2028 int shifts = 0; 2029 2030 mask = 1; 2031 while (size_tmp) { 2032 ++shifts; 2033 size_tmp >>= 1; 2034 } 2035 mask = (1 << shifts); 2036 if (mask < size) { 2037 mask <<= 1; 2038 } 2039 --mask; 2040 } 2041 2042 /* 2043 * Allocate some arbitrary I/O space. 2044 */ 2045 2046 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2047 2048 #if rbus 2049 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2050 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2051 return 1; 2052 } 2053 #else 2054 if (start) { 2055 ioaddr = start; 2056 if (bus_space_map(iot, start, size, 0, &ioh)) { 2057 return 1; 2058 } 2059 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2060 (u_long) ioaddr, (u_long) size)); 2061 } else { 2062 flags |= PCMCIA_IO_ALLOCATED; 2063 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2064 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2065 size, align, 0, 0, &ioaddr, &ioh)) { 2066 /* No room be able to be get. */ 2067 return 1; 2068 } 2069 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2070 (u_long) ioaddr, (u_long) size)); 2071 } 2072 #endif 2073 2074 pcihp->iot = iot; 2075 pcihp->ioh = ioh; 2076 pcihp->addr = ioaddr; 2077 pcihp->size = size; 2078 pcihp->flags = flags; 2079 2080 return 0; 2081 } 2082 2083 /* 2084 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2085 * struct pcmcia_io_handle *pcihp) 2086 * 2087 * This function only frees I/O region for pccard. 2088 * 2089 * XXX: The interface of this function is not very good, I believe. 2090 */ 2091 void 2092 pccbb_pcmcia_io_free(pch, pcihp) 2093 pcmcia_chipset_handle_t pch; 2094 struct pcmcia_io_handle *pcihp; 2095 { 2096 #if !rbus 2097 bus_space_tag_t iot = pcihp->iot; 2098 #endif 2099 bus_space_handle_t ioh = pcihp->ioh; 2100 bus_size_t size = pcihp->size; 2101 2102 #if rbus 2103 struct pccbb_softc *sc = 2104 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2105 rbus_tag_t rb = sc->sc_rbus_iot; 2106 2107 rbus_space_free(rb, ioh, size, NULL); 2108 #else 2109 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2110 bus_space_free(iot, ioh, size); 2111 else 2112 bus_space_unmap(iot, ioh, size); 2113 #endif 2114 } 2115 2116 /* 2117 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2118 * bus_addr_t offset, bus_size_t size, 2119 * struct pcmcia_io_handle *pcihp, 2120 * int *windowp) 2121 * 2122 * This function maps the allocated I/O region to pccard. This function 2123 * never allocates any I/O region for pccard I/O area. I don't 2124 * understand why the original authors of pcmciabus separated alloc and 2125 * map. I believe the two must be unite. 2126 * 2127 * XXX: no wait timing control? 2128 */ 2129 int 2130 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2131 pcmcia_chipset_handle_t pch; 2132 int width; 2133 bus_addr_t offset; 2134 bus_size_t size; 2135 struct pcmcia_io_handle *pcihp; 2136 int *windowp; 2137 { 2138 struct pcic_handle *ph = (struct pcic_handle *)pch; 2139 bus_addr_t ioaddr = pcihp->addr + offset; 2140 int i, win; 2141 #if defined CBB_DEBUG 2142 static char *width_names[] = { "dynamic", "io8", "io16" }; 2143 #endif 2144 2145 /* Sanity check I/O handle. */ 2146 2147 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2148 panic("pccbb_pcmcia_io_map iot is bogus"); 2149 } 2150 2151 /* XXX Sanity check offset/size. */ 2152 2153 win = -1; 2154 for (i = 0; i < PCIC_IO_WINS; i++) { 2155 if ((ph->ioalloc & (1 << i)) == 0) { 2156 win = i; 2157 ph->ioalloc |= (1 << i); 2158 break; 2159 } 2160 } 2161 2162 if (win == -1) { 2163 return 1; 2164 } 2165 2166 *windowp = win; 2167 2168 /* XXX this is pretty gross */ 2169 2170 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2171 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2172 2173 /* XXX wtf is this doing here? */ 2174 2175 #if 0 2176 printf(" port 0x%lx", (u_long) ioaddr); 2177 if (size > 1) { 2178 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2179 } 2180 #endif 2181 2182 ph->io[win].addr = ioaddr; 2183 ph->io[win].size = size; 2184 ph->io[win].width = width; 2185 2186 /* actual dirty register-value changing in the function below. */ 2187 pccbb_pcmcia_do_io_map(ph, win); 2188 2189 return 0; 2190 } 2191 2192 /* 2193 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2194 * 2195 * This function changes register-value to map I/O region for pccard. 2196 */ 2197 static void 2198 pccbb_pcmcia_do_io_map(ph, win) 2199 struct pcic_handle *ph; 2200 int win; 2201 { 2202 static u_int8_t pcic_iowidth[3] = { 2203 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2204 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2205 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2206 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2207 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2208 }; 2209 2210 #define PCIC_SIA_START_LOW 0 2211 #define PCIC_SIA_START_HIGH 1 2212 #define PCIC_SIA_STOP_LOW 2 2213 #define PCIC_SIA_STOP_HIGH 3 2214 2215 int regbase_win = 0x8 + win * 0x04; 2216 u_int8_t ioctl, enable; 2217 2218 DPRINTF( 2219 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2220 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2221 ph->io[win].width * 8)); 2222 2223 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2224 ph->io[win].addr & 0xff); 2225 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2226 (ph->io[win].addr >> 8) & 0xff); 2227 2228 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2229 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2230 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2231 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2232 2233 ioctl = Pcic_read(ph, PCIC_IOCTL); 2234 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2235 switch (win) { 2236 case 0: 2237 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2238 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2239 PCIC_IOCTL_IO0_DATASIZE_MASK); 2240 ioctl |= pcic_iowidth[ph->io[win].width]; 2241 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2242 break; 2243 case 1: 2244 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2245 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2246 PCIC_IOCTL_IO1_DATASIZE_MASK); 2247 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2248 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2249 break; 2250 } 2251 Pcic_write(ph, PCIC_IOCTL, ioctl); 2252 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2253 #if defined CBB_DEBUG 2254 { 2255 u_int8_t start_low = 2256 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2257 u_int8_t start_high = 2258 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2259 u_int8_t stop_low = 2260 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2261 u_int8_t stop_high = 2262 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2263 printf 2264 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2265 start_low, start_high, stop_low, stop_high, ioctl, enable); 2266 } 2267 #endif 2268 } 2269 2270 /* 2271 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2272 * 2273 * This function unmaps I/O region. No return value. 2274 */ 2275 STATIC void 2276 pccbb_pcmcia_io_unmap(pch, win) 2277 pcmcia_chipset_handle_t pch; 2278 int win; 2279 { 2280 struct pcic_handle *ph = (struct pcic_handle *)pch; 2281 int reg; 2282 2283 if (win >= PCIC_IO_WINS || win < 0) { 2284 panic("pccbb_pcmcia_io_unmap: window out of range"); 2285 } 2286 2287 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2288 switch (win) { 2289 case 0: 2290 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2291 break; 2292 case 1: 2293 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2294 break; 2295 } 2296 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2297 2298 ph->ioalloc &= ~(1 << win); 2299 } 2300 2301 /* 2302 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2303 * 2304 * This function enables the card. All information is stored in 2305 * the first argument, pcmcia_chipset_handle_t. 2306 */ 2307 static void 2308 pccbb_pcmcia_wait_ready(ph) 2309 struct pcic_handle *ph; 2310 { 2311 int i; 2312 2313 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2314 Pcic_read(ph, PCIC_IF_STATUS))); 2315 2316 for (i = 0; i < 2000; i++) { 2317 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2318 return; 2319 } 2320 DELAY_MS(2, ph->ph_parent); 2321 #ifdef CBB_DEBUG 2322 if ((i > 1000) && (i % 25 == 24)) 2323 printf("."); 2324 #endif 2325 } 2326 2327 #ifdef DIAGNOSTIC 2328 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2329 Pcic_read(ph, PCIC_IF_STATUS)); 2330 #endif 2331 } 2332 2333 /* 2334 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2335 * 2336 * This function enables the card. All information is stored in 2337 * the first argument, pcmcia_chipset_handle_t. 2338 */ 2339 STATIC void 2340 pccbb_pcmcia_socket_enable(pch) 2341 pcmcia_chipset_handle_t pch; 2342 { 2343 struct pcic_handle *ph = (struct pcic_handle *)pch; 2344 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2345 int cardtype, win; 2346 u_int8_t power, intr; 2347 pcireg_t spsr; 2348 int voltage; 2349 2350 /* this bit is mostly stolen from pcic_attach_card */ 2351 2352 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2353 2354 /* get card Vcc info */ 2355 2356 spsr = 2357 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2358 CB_SOCKET_STAT); 2359 if (spsr & CB_SOCKET_STAT_5VCARD) { 2360 DPRINTF(("5V card\n")); 2361 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2362 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2363 DPRINTF(("3V card\n")); 2364 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2365 } else { 2366 printf("?V card, 0x%x\n", spsr); /* XXX */ 2367 return; 2368 } 2369 2370 /* disable socket: negate output enable bit and power off */ 2371 2372 power = 0; 2373 Pcic_write(ph, PCIC_PWRCTL, power); 2374 2375 /* power down the socket to reset it, clear the card reset pin */ 2376 2377 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2378 2379 /* 2380 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2381 * we are changing Vcc (Toff). 2382 */ 2383 /* delay(300*1000); too much */ 2384 2385 /* assert reset bit */ 2386 intr = Pcic_read(ph, PCIC_INTR); 2387 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2388 Pcic_write(ph, PCIC_INTR, intr); 2389 2390 /* power up the socket and output enable */ 2391 power = Pcic_read(ph, PCIC_PWRCTL); 2392 power |= PCIC_PWRCTL_OE; 2393 Pcic_write(ph, PCIC_PWRCTL, power); 2394 pccbb_power(sc, voltage); 2395 2396 /* 2397 * hold RESET at least 20 ms: the spec says only 10 us is 2398 * enough, but TI1130 requires at least 20 ms. 2399 */ 2400 #if 0 /* XXX called on interrupt context */ 2401 DELAY_MS(20, sc); 2402 #else 2403 delay(20 * 1000); 2404 #endif 2405 2406 /* clear the reset flag */ 2407 2408 intr |= PCIC_INTR_RESET; 2409 Pcic_write(ph, PCIC_INTR, intr); 2410 2411 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2412 2413 #if 0 /* XXX called on interrupt context */ 2414 DELAY_MS(20, sc); 2415 #else 2416 delay(20 * 1000); 2417 #endif 2418 2419 /* wait for the chip to finish initializing */ 2420 2421 pccbb_pcmcia_wait_ready(ph); 2422 2423 /* zero out the address windows */ 2424 2425 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2426 2427 /* set the card type */ 2428 2429 cardtype = pcmcia_card_gettype(ph->pcmcia); 2430 2431 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2432 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2433 Pcic_write(ph, PCIC_INTR, intr); 2434 2435 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2436 ph->ph_parent->dv_xname, ph->sock, 2437 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2438 2439 /* reinstall all the memory and io mappings */ 2440 2441 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2442 if (ph->memalloc & (1 << win)) { 2443 pccbb_pcmcia_do_mem_map(ph, win); 2444 } 2445 } 2446 2447 for (win = 0; win < PCIC_IO_WINS; ++win) { 2448 if (ph->ioalloc & (1 << win)) { 2449 pccbb_pcmcia_do_io_map(ph, win); 2450 } 2451 } 2452 } 2453 2454 /* 2455 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2456 * 2457 * This function disables the card. All information is stored in 2458 * the first argument, pcmcia_chipset_handle_t. 2459 */ 2460 STATIC void 2461 pccbb_pcmcia_socket_disable(pch) 2462 pcmcia_chipset_handle_t pch; 2463 { 2464 struct pcic_handle *ph = (struct pcic_handle *)pch; 2465 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2466 u_int8_t power, intr; 2467 2468 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2469 2470 /* reset signal asserting... */ 2471 2472 intr = Pcic_read(ph, PCIC_INTR); 2473 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2474 Pcic_write(ph, PCIC_INTR, intr); 2475 delay(2 * 1000); 2476 2477 /* power down the socket */ 2478 power = Pcic_read(ph, PCIC_PWRCTL); 2479 power &= ~PCIC_PWRCTL_OE; 2480 Pcic_write(ph, PCIC_PWRCTL, power); 2481 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2482 /* 2483 * wait 300ms until power fails (Tpf). 2484 */ 2485 #if 0 /* XXX called on interrupt context */ 2486 DELAY_MS(300, sc); 2487 #else 2488 delay(300 * 1000); 2489 #endif 2490 } 2491 2492 /* 2493 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2494 * 2495 * This function detects whether a card is in the slot or not. 2496 * If a card is inserted, return 1. Otherwise, return 0. 2497 */ 2498 STATIC int 2499 pccbb_pcmcia_card_detect(pch) 2500 pcmcia_chipset_handle_t pch; 2501 { 2502 struct pcic_handle *ph = (struct pcic_handle *)pch; 2503 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2504 2505 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2506 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2507 } 2508 2509 #if 0 2510 STATIC int 2511 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2512 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2513 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2514 #endif 2515 /* 2516 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2517 * bus_size_t size, 2518 * struct pcmcia_mem_handle *pcmhp) 2519 * 2520 * This function only allocates memory region for pccard. This 2521 * function never maps the allocated region to pccard memory area. 2522 * 2523 * XXX: Why the argument of start address is not in? 2524 */ 2525 STATIC int 2526 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2527 pcmcia_chipset_handle_t pch; 2528 bus_size_t size; 2529 struct pcmcia_mem_handle *pcmhp; 2530 { 2531 struct pcic_handle *ph = (struct pcic_handle *)pch; 2532 bus_space_handle_t memh; 2533 bus_addr_t addr; 2534 bus_size_t sizepg; 2535 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2536 #if rbus 2537 rbus_tag_t rb; 2538 #endif 2539 2540 /* out of sc->memh, allocate as many pages as necessary */ 2541 2542 /* convert size to PCIC pages */ 2543 /* 2544 * This is not enough; when the requested region is on the page 2545 * boundaries, this may calculate wrong result. 2546 */ 2547 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2548 #if 0 2549 if (sizepg > PCIC_MAX_MEM_PAGES) { 2550 return 1; 2551 } 2552 #endif 2553 2554 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2555 return 1; 2556 } 2557 2558 addr = 0; /* XXX gcc -Wuninitialized */ 2559 2560 #if rbus 2561 rb = sc->sc_rbus_memt; 2562 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2563 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2564 &addr, &memh)) { 2565 return 1; 2566 } 2567 #else 2568 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2569 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2570 0, /* boundary */ 2571 0, /* flags */ 2572 &addr, &memh)) { 2573 return 1; 2574 } 2575 #endif 2576 2577 DPRINTF( 2578 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2579 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2580 2581 pcmhp->memt = sc->sc_memt; 2582 pcmhp->memh = memh; 2583 pcmhp->addr = addr; 2584 pcmhp->size = size; 2585 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2586 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2587 pcmhp->mhandle = 0; 2588 /* No offset??? Funny. */ 2589 2590 return 0; 2591 } 2592 2593 /* 2594 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2595 * struct pcmcia_mem_handle *pcmhp) 2596 * 2597 * This function release the memory space allocated by the function 2598 * pccbb_pcmcia_mem_alloc(). 2599 */ 2600 STATIC void 2601 pccbb_pcmcia_mem_free(pch, pcmhp) 2602 pcmcia_chipset_handle_t pch; 2603 struct pcmcia_mem_handle *pcmhp; 2604 { 2605 #if rbus 2606 struct pcic_handle *ph = (struct pcic_handle *)pch; 2607 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2608 2609 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2610 #else 2611 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2612 #endif 2613 } 2614 2615 /* 2616 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2617 * 2618 * This function release the memory space allocated by the function 2619 * pccbb_pcmcia_mem_alloc(). 2620 */ 2621 STATIC void 2622 pccbb_pcmcia_do_mem_map(ph, win) 2623 struct pcic_handle *ph; 2624 int win; 2625 { 2626 int regbase_win; 2627 bus_addr_t phys_addr; 2628 bus_addr_t phys_end; 2629 2630 #define PCIC_SMM_START_LOW 0 2631 #define PCIC_SMM_START_HIGH 1 2632 #define PCIC_SMM_STOP_LOW 2 2633 #define PCIC_SMM_STOP_HIGH 3 2634 #define PCIC_CMA_LOW 4 2635 #define PCIC_CMA_HIGH 5 2636 2637 u_int8_t start_low, start_high = 0; 2638 u_int8_t stop_low, stop_high; 2639 u_int8_t off_low, off_high; 2640 u_int8_t mem_window; 2641 int reg; 2642 2643 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2644 int mem8 = 2645 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2646 || (kind == PCMCIA_MEM_ATTR); 2647 2648 regbase_win = 0x10 + win * 0x08; 2649 2650 phys_addr = ph->mem[win].addr; 2651 phys_end = phys_addr + ph->mem[win].size; 2652 2653 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2654 phys_addr, phys_end, ph->mem[win].offset)); 2655 2656 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2657 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2658 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2659 2660 /* bit 19:12 */ 2661 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2662 /* bit 23:20 and bit 7 on */ 2663 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2664 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2665 /* bit 31:24, for 32-bit address */ 2666 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2667 2668 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2669 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2670 2671 if (((struct pccbb_softc *)ph-> 2672 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2673 Pcic_write(ph, 0x40 + win, mem_window); 2674 } 2675 2676 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2677 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2678 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2679 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2680 2681 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2682 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2683 2684 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2685 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2686 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2687 | ((kind == PCMCIA_MEM_ATTR) ? 2688 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2689 2690 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2691 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2692 2693 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2694 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2695 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2696 2697 #if defined CBB_DEBUG 2698 { 2699 int r1, r2, r3, r4, r5, r6, r7 = 0; 2700 2701 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2702 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2703 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2704 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2705 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2706 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2707 if (((struct pccbb_softc *)(ph-> 2708 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2709 r7 = Pcic_read(ph, 0x40 + win); 2710 } 2711 2712 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2713 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2714 if (((struct pccbb_softc *)(ph-> 2715 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2716 DPRINTF((" %02x", r7)); 2717 } 2718 DPRINTF(("\n")); 2719 } 2720 #endif 2721 } 2722 2723 /* 2724 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2725 * bus_addr_t card_addr, bus_size_t size, 2726 * struct pcmcia_mem_handle *pcmhp, 2727 * bus_addr_t *offsetp, int *windowp) 2728 * 2729 * This function maps memory space allocated by the function 2730 * pccbb_pcmcia_mem_alloc(). 2731 */ 2732 STATIC int 2733 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2734 pcmcia_chipset_handle_t pch; 2735 int kind; 2736 bus_addr_t card_addr; 2737 bus_size_t size; 2738 struct pcmcia_mem_handle *pcmhp; 2739 bus_addr_t *offsetp; 2740 int *windowp; 2741 { 2742 struct pcic_handle *ph = (struct pcic_handle *)pch; 2743 bus_addr_t busaddr; 2744 long card_offset; 2745 int win; 2746 2747 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2748 if ((ph->memalloc & (1 << win)) == 0) { 2749 ph->memalloc |= (1 << win); 2750 break; 2751 } 2752 } 2753 2754 if (win == PCIC_MEM_WINS) { 2755 return 1; 2756 } 2757 2758 *windowp = win; 2759 2760 /* XXX this is pretty gross */ 2761 2762 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2763 panic("pccbb_pcmcia_mem_map memt is bogus"); 2764 } 2765 2766 busaddr = pcmhp->addr; 2767 2768 /* 2769 * compute the address offset to the pcmcia address space for the 2770 * pcic. this is intentionally signed. The masks and shifts below 2771 * will cause TRT to happen in the pcic registers. Deal with making 2772 * sure the address is aligned, and return the alignment offset. 2773 */ 2774 2775 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2776 card_addr -= *offsetp; 2777 2778 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2779 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2780 (u_long) card_addr)); 2781 2782 /* 2783 * include the offset in the size, and decrement size by one, since 2784 * the hw wants start/stop 2785 */ 2786 size += *offsetp - 1; 2787 2788 card_offset = (((long)card_addr) - ((long)busaddr)); 2789 2790 ph->mem[win].addr = busaddr; 2791 ph->mem[win].size = size; 2792 ph->mem[win].offset = card_offset; 2793 ph->mem[win].kind = kind; 2794 2795 pccbb_pcmcia_do_mem_map(ph, win); 2796 2797 return 0; 2798 } 2799 2800 /* 2801 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2802 * int window) 2803 * 2804 * This function unmaps memory space which mapped by the function 2805 * pccbb_pcmcia_mem_map(). 2806 */ 2807 STATIC void 2808 pccbb_pcmcia_mem_unmap(pch, window) 2809 pcmcia_chipset_handle_t pch; 2810 int window; 2811 { 2812 struct pcic_handle *ph = (struct pcic_handle *)pch; 2813 int reg; 2814 2815 if (window >= PCIC_MEM_WINS) { 2816 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2817 } 2818 2819 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2820 reg &= ~(1 << window); 2821 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2822 2823 ph->memalloc &= ~(1 << window); 2824 } 2825 2826 #if defined PCCBB_PCMCIA_POLL 2827 struct pccbb_poll_str { 2828 void *arg; 2829 int (*func) __P((void *)); 2830 int level; 2831 struct pcic_handle *ph; 2832 int count; 2833 int num; 2834 struct callout poll_ch; 2835 }; 2836 2837 static struct pccbb_poll_str pccbb_poll[10]; 2838 static int pccbb_poll_n = 0; 2839 2840 static void pccbb_pcmcia_poll __P((void *arg)); 2841 2842 static void 2843 pccbb_pcmcia_poll(arg) 2844 void *arg; 2845 { 2846 struct pccbb_poll_str *poll = arg; 2847 struct pcic_handle *ph = poll->ph; 2848 struct pccbb_softc *sc = ph->sc; 2849 int s; 2850 u_int32_t spsr; /* socket present-state reg */ 2851 2852 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2853 switch (poll->level) { 2854 case IPL_NET: 2855 s = splnet(); 2856 break; 2857 case IPL_BIO: 2858 s = splbio(); 2859 break; 2860 case IPL_TTY: /* fallthrough */ 2861 default: 2862 s = spltty(); 2863 break; 2864 } 2865 2866 spsr = 2867 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2868 CB_SOCKET_STAT); 2869 2870 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2871 if (!(spsr & 0x40)) /* CINT low */ 2872 #else 2873 if (1) 2874 #endif 2875 { 2876 if ((*poll->func) (poll->arg) > 0) { 2877 ++poll->count; 2878 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2879 #if defined LEVEL2 2880 } else { 2881 printf("intr: miss! 0x%x\n", spsr); 2882 #endif 2883 } 2884 } 2885 splx(s); 2886 } 2887 #endif /* defined CB_PCMCIA_POLL */ 2888 2889 /* 2890 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2891 * struct pcmcia_function *pf, 2892 * int ipl, 2893 * int (*func)(void *), 2894 * void *arg); 2895 * 2896 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2897 */ 2898 STATIC void * 2899 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2900 pcmcia_chipset_handle_t pch; 2901 struct pcmcia_function *pf; 2902 int ipl; 2903 int (*func) __P((void *)); 2904 void *arg; 2905 { 2906 struct pcic_handle *ph = (struct pcic_handle *)pch; 2907 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2908 2909 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2910 /* what should I do? */ 2911 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2912 DPRINTF( 2913 ("%s does not provide edge nor pulse interrupt\n", 2914 sc->sc_dev.dv_xname)); 2915 return NULL; 2916 } 2917 /* 2918 * XXX Noooooo! The interrupt flag must set properly!! 2919 * dumb pcmcia driver!! 2920 */ 2921 } 2922 2923 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2924 } 2925 2926 /* 2927 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2928 * void *ih) 2929 * 2930 * This function disables PC-Card interrupt. 2931 */ 2932 STATIC void 2933 pccbb_pcmcia_intr_disestablish(pch, ih) 2934 pcmcia_chipset_handle_t pch; 2935 void *ih; 2936 { 2937 struct pcic_handle *ph = (struct pcic_handle *)pch; 2938 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2939 2940 pccbb_intr_disestablish(sc, ih); 2941 } 2942 2943 #if rbus 2944 /* 2945 * static int 2946 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2947 * bus_addr_t addr, bus_size_t size, 2948 * bus_addr_t mask, bus_size_t align, 2949 * int flags, bus_addr_t *addrp; 2950 * bus_space_handle_t *bshp) 2951 * 2952 * This function allocates a portion of memory or io space for 2953 * clients. This function is called from CardBus card drivers. 2954 */ 2955 static int 2956 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2957 cardbus_chipset_tag_t ct; 2958 rbus_tag_t rb; 2959 bus_addr_t addr; 2960 bus_size_t size; 2961 bus_addr_t mask; 2962 bus_size_t align; 2963 int flags; 2964 bus_addr_t *addrp; 2965 bus_space_handle_t *bshp; 2966 { 2967 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2968 2969 DPRINTF( 2970 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2971 addr, size, mask, align)); 2972 2973 if (align == 0) { 2974 align = size; 2975 } 2976 2977 if (rb->rb_bt == sc->sc_memt) { 2978 if (align < 16) { 2979 return 1; 2980 } 2981 /* 2982 * XXX: align more than 0x1000 to avoid overwrapping 2983 * memory windows for two or more devices. 0x1000 2984 * means memory window's granularity. 2985 * 2986 * Two or more devices should be able to share same 2987 * memory window region. However, overrapping memory 2988 * window is not good because some devices, such as 2989 * 3Com 3C575[BC], have a broken address decoder and 2990 * intrude other's memory region. 2991 */ 2992 if (align < 0x1000) { 2993 align = 0x1000; 2994 } 2995 } else if (rb->rb_bt == sc->sc_iot) { 2996 if (align < 4) { 2997 return 1; 2998 } 2999 /* XXX: hack for avoiding ISA image */ 3000 if (mask < 0x0100) { 3001 mask = 0x3ff; 3002 addr = 0x300; 3003 } 3004 3005 } else { 3006 DPRINTF( 3007 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 3008 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 3009 return 1; 3010 /* XXX: panic here? */ 3011 } 3012 3013 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3014 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3015 return 1; 3016 } 3017 3018 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3019 3020 return 0; 3021 } 3022 3023 /* 3024 * static int 3025 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3026 * bus_space_handle_t *bshp, bus_size_t size); 3027 * 3028 * This function is called from CardBus card drivers. 3029 */ 3030 static int 3031 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3032 cardbus_chipset_tag_t ct; 3033 rbus_tag_t rb; 3034 bus_space_handle_t bsh; 3035 bus_size_t size; 3036 { 3037 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3038 bus_space_tag_t bt = rb->rb_bt; 3039 3040 pccbb_close_win(sc, bt, bsh, size); 3041 3042 if (bt == sc->sc_memt) { 3043 } else if (bt == sc->sc_iot) { 3044 } else { 3045 return 1; 3046 /* XXX: panic here? */ 3047 } 3048 3049 return rbus_space_free(rb, bsh, size, NULL); 3050 } 3051 #endif /* rbus */ 3052 3053 #if rbus 3054 3055 static int 3056 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3057 struct pccbb_softc *sc; 3058 bus_space_tag_t bst; 3059 bus_addr_t addr; 3060 bus_size_t size; 3061 bus_space_handle_t bsh; 3062 int flags; 3063 { 3064 struct pccbb_win_chain_head *head; 3065 bus_addr_t align; 3066 3067 head = &sc->sc_iowindow; 3068 align = 0x04; 3069 if (sc->sc_memt == bst) { 3070 head = &sc->sc_memwindow; 3071 align = 0x1000; 3072 DPRINTF(("using memory window, %x %x %x\n\n", 3073 sc->sc_iot, sc->sc_memt, bst)); 3074 } 3075 3076 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3077 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3078 sc->sc_dev.dv_xname, 3079 (head == &sc->sc_memwindow) ? "mem" : "io"); 3080 } 3081 pccbb_winset(align, sc, bst); 3082 3083 return 0; 3084 } 3085 3086 static int 3087 pccbb_close_win(sc, bst, bsh, size) 3088 struct pccbb_softc *sc; 3089 bus_space_tag_t bst; 3090 bus_space_handle_t bsh; 3091 bus_size_t size; 3092 { 3093 struct pccbb_win_chain_head *head; 3094 bus_addr_t align; 3095 3096 head = &sc->sc_iowindow; 3097 align = 0x04; 3098 if (sc->sc_memt == bst) { 3099 head = &sc->sc_memwindow; 3100 align = 0x1000; 3101 } 3102 3103 if (pccbb_winlist_delete(head, bsh, size)) { 3104 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3105 sc->sc_dev.dv_xname, 3106 (head == &sc->sc_memwindow) ? "mem" : "io"); 3107 } 3108 pccbb_winset(align, sc, bst); 3109 3110 return 0; 3111 } 3112 3113 static int 3114 pccbb_winlist_insert(head, start, size, bsh, flags) 3115 struct pccbb_win_chain_head *head; 3116 bus_addr_t start; 3117 bus_size_t size; 3118 bus_space_handle_t bsh; 3119 int flags; 3120 { 3121 struct pccbb_win_chain *chainp, *elem; 3122 3123 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3124 M_NOWAIT)) == NULL) 3125 return (1); /* fail */ 3126 3127 elem->wc_start = start; 3128 elem->wc_end = start + (size - 1); 3129 elem->wc_handle = bsh; 3130 elem->wc_flags = flags; 3131 3132 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3133 chainp = TAILQ_NEXT(chainp, wc_list)) { 3134 if (chainp->wc_end < start) 3135 continue; 3136 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3137 return (0); 3138 } 3139 3140 TAILQ_INSERT_TAIL(head, elem, wc_list); 3141 return (0); 3142 } 3143 3144 static int 3145 pccbb_winlist_delete(head, bsh, size) 3146 struct pccbb_win_chain_head *head; 3147 bus_space_handle_t bsh; 3148 bus_size_t size; 3149 { 3150 struct pccbb_win_chain *chainp; 3151 3152 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3153 chainp = TAILQ_NEXT(chainp, wc_list)) { 3154 if (chainp->wc_handle != bsh) 3155 continue; 3156 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3157 printf("pccbb_winlist_delete: window 0x%lx size " 3158 "inconsistent: 0x%lx, 0x%lx\n", 3159 (unsigned long)chainp->wc_start, 3160 (unsigned long)(chainp->wc_end - chainp->wc_start), 3161 (unsigned long)(size - 1)); 3162 return 1; 3163 } 3164 3165 TAILQ_REMOVE(head, chainp, wc_list); 3166 free(chainp, M_DEVBUF); 3167 3168 return 0; 3169 } 3170 3171 return 1; /* fail: no candidate to remove */ 3172 } 3173 3174 static void 3175 pccbb_winset(align, sc, bst) 3176 bus_addr_t align; 3177 struct pccbb_softc *sc; 3178 bus_space_tag_t bst; 3179 { 3180 pci_chipset_tag_t pc; 3181 pcitag_t tag; 3182 bus_addr_t mask = ~(align - 1); 3183 struct { 3184 cardbusreg_t win_start; 3185 cardbusreg_t win_limit; 3186 int win_flags; 3187 } win[2]; 3188 struct pccbb_win_chain *chainp; 3189 int offs; 3190 3191 win[0].win_start = win[1].win_start = 0xffffffff; 3192 win[0].win_limit = win[1].win_limit = 0; 3193 win[0].win_flags = win[1].win_flags = 0; 3194 3195 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3196 offs = 0x2c; 3197 if (sc->sc_memt == bst) { 3198 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3199 offs = 0x1c; 3200 } 3201 3202 if (chainp != NULL) { 3203 win[0].win_start = chainp->wc_start & mask; 3204 win[0].win_limit = chainp->wc_end & mask; 3205 win[0].win_flags = chainp->wc_flags; 3206 chainp = TAILQ_NEXT(chainp, wc_list); 3207 } 3208 3209 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3210 if (win[1].win_start == 0xffffffff) { 3211 /* window 1 is not used */ 3212 if ((win[0].win_flags == chainp->wc_flags) && 3213 (win[0].win_limit + align >= 3214 (chainp->wc_start & mask))) { 3215 /* concatenate */ 3216 win[0].win_limit = chainp->wc_end & mask; 3217 } else { 3218 /* make new window */ 3219 win[1].win_start = chainp->wc_start & mask; 3220 win[1].win_limit = chainp->wc_end & mask; 3221 win[1].win_flags = chainp->wc_flags; 3222 } 3223 continue; 3224 } 3225 3226 /* Both windows are engaged. */ 3227 if (win[0].win_flags == win[1].win_flags) { 3228 /* same flags */ 3229 if (win[0].win_flags == chainp->wc_flags) { 3230 if (win[1].win_start - (win[0].win_limit + 3231 align) < 3232 (chainp->wc_start & mask) - 3233 ((chainp->wc_end & mask) + align)) { 3234 /* 3235 * merge window 0 and 1, and set win1 3236 * to chainp 3237 */ 3238 win[0].win_limit = win[1].win_limit; 3239 win[1].win_start = 3240 chainp->wc_start & mask; 3241 win[1].win_limit = 3242 chainp->wc_end & mask; 3243 } else { 3244 win[1].win_limit = 3245 chainp->wc_end & mask; 3246 } 3247 } else { 3248 /* different flags */ 3249 3250 /* concatenate win0 and win1 */ 3251 win[0].win_limit = win[1].win_limit; 3252 /* allocate win[1] to new space */ 3253 win[1].win_start = chainp->wc_start & mask; 3254 win[1].win_limit = chainp->wc_end & mask; 3255 win[1].win_flags = chainp->wc_flags; 3256 } 3257 } else { 3258 /* the flags of win[0] and win[1] is different */ 3259 if (win[0].win_flags == chainp->wc_flags) { 3260 win[0].win_limit = chainp->wc_end & mask; 3261 /* 3262 * XXX this creates overlapping windows, so 3263 * what should the poor bridge do if one is 3264 * cachable, and the other is not? 3265 */ 3266 printf("%s: overlapping windows\n", 3267 sc->sc_dev.dv_xname); 3268 } else { 3269 win[1].win_limit = chainp->wc_end & mask; 3270 } 3271 } 3272 } 3273 3274 pc = sc->sc_pc; 3275 tag = sc->sc_tag; 3276 pci_conf_write(pc, tag, offs, win[0].win_start); 3277 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3278 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3279 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3280 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3281 pci_conf_read(pc, tag, offs), 3282 pci_conf_read(pc, tag, offs + 4) + align, 3283 pci_conf_read(pc, tag, offs + 8), 3284 pci_conf_read(pc, tag, offs + 12) + align)); 3285 3286 if (bst == sc->sc_memt) { 3287 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3288 3289 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3290 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3291 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3292 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3293 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3294 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3295 } 3296 } 3297 3298 #endif /* rbus */ 3299 3300 static void 3301 pccbb_powerhook(why, arg) 3302 int why; 3303 void *arg; 3304 { 3305 struct pccbb_softc *sc = arg; 3306 pcireg_t reg; 3307 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3308 bus_space_handle_t base_memh = sc->sc_base_memh; 3309 3310 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3311 3312 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3313 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3314 if (sc->sc_pil_intr_enable) { 3315 (void)pccbbintr_function(sc); 3316 } 3317 sc->sc_pil_intr_enable = 0; 3318 3319 /* ToDo: deactivate or suspend child devices */ 3320 3321 } 3322 3323 if (why == PWR_RESUME) { 3324 if (sc->sc_pwrmgt_offs != 0) { 3325 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3326 sc->sc_pwrmgt_offs + 4); 3327 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3328 reg & 0x100) { 3329 /* powrstate != D0 */ 3330 3331 printf("%s going back to D0 mode\n", 3332 sc->sc_dev.dv_xname); 3333 reg &= ~PCI_PMCSR_STATE_MASK; 3334 reg |= PCI_PMCSR_STATE_D0; 3335 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3336 pci_conf_write(sc->sc_pc, sc->sc_tag, 3337 sc->sc_pwrmgt_offs + 4, reg); 3338 3339 pci_conf_write(sc->sc_pc, sc->sc_tag, 3340 PCI_SOCKBASE, sc->sc_sockbase); 3341 pci_conf_write(sc->sc_pc, sc->sc_tag, 3342 PCI_BUSNUM, sc->sc_busnum); 3343 pccbb_chipinit(sc); 3344 /* setup memory and io space window for CB */ 3345 pccbb_winset(0x1000, sc, sc->sc_memt); 3346 pccbb_winset(0x04, sc, sc->sc_iot); 3347 } 3348 } 3349 3350 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3351 /* BIOS did not recover this register */ 3352 pci_conf_write (sc->sc_pc, sc->sc_tag, 3353 PCI_SOCKBASE, sc->sc_sockbase); 3354 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3355 /* BIOS did not recover this register */ 3356 pci_conf_write (sc->sc_pc, sc->sc_tag, 3357 PCI_BUSNUM, sc->sc_busnum); 3358 /* CSC Interrupt: Card detect interrupt on */ 3359 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3360 /* Card detect intr is turned on. */ 3361 reg |= CB_SOCKET_MASK_CD; 3362 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3363 /* reset interrupt */ 3364 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3365 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3366 3367 /* 3368 * check for card insertion or removal during suspend period. 3369 * XXX: the code can't cope with card swap (remove then 3370 * insert). how can we detect such situation? 3371 */ 3372 (void)pccbbintr(sc); 3373 3374 sc->sc_pil_intr_enable = 1; 3375 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3376 3377 /* ToDo: activate or wakeup child devices */ 3378 } 3379 } 3380
Indexes created Fri Sep 26 08:10:20 GMT 2025