pccbb.c revision 1.8
1 /* $NetBSD: pccbb.c,v 1.8 1999/11/15 16:19:03 joda Exp $ */ 2 3 /* 4 * Copyright (c) 1998 and 1999 HAYAKAWA Koichi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by HAYAKAWA Koichi. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 #define CBB_DEBUG 34 #define SHOW_REGS 35 #define PCCBB_PCMCIA_POLL 36 */ 37 /* #define CBB_DEBUG */ 38 39 /* 40 #define CB_PCMCIA_POLL 41 #define CB_PCMCIA_POLL_ONLY 42 #define LEVEL2 43 */ 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/ioctl.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 55 #include <machine/intr.h> 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/pccbbreg.h> 63 64 #include <dev/cardbus/cardslotvar.h> 65 66 #include <dev/cardbus/cardbusvar.h> 67 68 #include <dev/pcmcia/pcmciareg.h> 69 #include <dev/pcmcia/pcmciavar.h> 70 71 #include <dev/ic/i82365reg.h> 72 #include <dev/ic/i82365var.h> 73 #include <dev/pci/pccbbvar.h> 74 75 #include "locators.h" 76 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #define STATIC 87 #else 88 #define DPRINTF(x) 89 #define STATIC static 90 #endif 91 92 93 #ifdef __BROKEN_INDIRECT_CONFIG 94 int pcicbbmatch __P((struct device *, void *, void *)); 95 #else 96 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 97 #endif 98 void pccbbattach __P((struct device *, struct device *, void *)); 99 int pccbbintr __P((void *)); 100 static void pci113x_insert __P((void *)); 101 102 static int pccbb_detect_card __P((struct pccbb_softc *)); 103 104 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 105 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 106 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 107 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 108 109 110 STATIC int cb_reset __P((struct pccbb_softc *)); 111 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 112 STATIC int cbbprint __P((void *, const char *)); 113 114 static int cb_chipset __P((u_int32_t, char const **, int *)); 115 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, struct pcmciabus_attach_args *)); 116 #if 0 117 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 118 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 119 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 120 #endif 121 122 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 123 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 124 STATIC int pccbb_cardenable __P((struct pccbb_softc *sc, int function)); 125 #if !rbus 126 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 127 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 128 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 129 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 130 #endif /* !rbus */ 131 static void *pccbb_intr_establish __P((cardbus_chipset_tag_t, int irq, int level, int (* ih)(void *), void *sc)); 132 static void pccbb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 133 134 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 135 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 136 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, int)); 137 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, cardbusreg_t)); 138 static void pccbb_chipinit __P((struct pccbb_softc *)); 139 140 141 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 142 struct pcmcia_mem_handle *)); 143 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 144 struct pcmcia_mem_handle *)); 145 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 146 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 147 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 148 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 149 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 150 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 151 struct pcmcia_io_handle *)); 152 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_io_handle *, int *)); 154 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 155 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 156 struct pcmcia_function *, int, int (*) (void *), void *)); 157 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, void *)); 158 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 159 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 160 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 161 162 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 163 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 164 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 165 166 /* bus-space allocation and disallocation functions */ 167 #if rbus 168 169 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 170 bus_addr_t addr, bus_size_t size, 171 bus_addr_t mask, bus_size_t align, 172 int flags, bus_addr_t *addrp, 173 bus_space_handle_t *bshp)); 174 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 175 bus_space_handle_t, bus_size_t)); 176 177 #endif /* rbus */ 178 179 #if rbus 180 181 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 182 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, bus_space_handle_t, bus_size_t)); 183 static int pccbb_winlist_insert __P((struct pccbb_win_chain **, bus_addr_t, 184 bus_size_t, bus_space_handle_t, int)); 185 static int pccbb_winlist_delete __P((struct pccbb_win_chain **, 186 bus_space_handle_t, bus_size_t)); 187 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 188 bus_space_tag_t)); 189 void pccbb_winlist_show(struct pccbb_win_chain *); 190 191 #endif /* rbus */ 192 193 /* for config_defer */ 194 static void pccbb_pci_callback __P((struct device *)); 195 196 197 #if defined SHOW_REGS 198 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, bus_space_handle_t memh)); 199 #endif 200 201 202 203 struct cfattach cbb_pci_ca = { 204 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 205 }; 206 207 208 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 209 pccbb_pcmcia_mem_alloc, 210 pccbb_pcmcia_mem_free, 211 pccbb_pcmcia_mem_map, 212 pccbb_pcmcia_mem_unmap, 213 pccbb_pcmcia_io_alloc, 214 pccbb_pcmcia_io_free, 215 pccbb_pcmcia_io_map, 216 pccbb_pcmcia_io_unmap, 217 pccbb_pcmcia_intr_establish, 218 pccbb_pcmcia_intr_disestablish, 219 pccbb_pcmcia_socket_enable, 220 pccbb_pcmcia_socket_disable, 221 pccbb_pcmcia_card_detect 222 }; 223 224 #if rbus 225 static struct cardbus_functions pccbb_funcs = { 226 pccbb_rbus_cb_space_alloc, 227 pccbb_rbus_cb_space_free, 228 pccbb_intr_establish, 229 pccbb_intr_disestablish, 230 pccbb_ctrl, 231 pccbb_power, 232 pccbb_make_tag, 233 pccbb_free_tag, 234 pccbb_conf_read, 235 pccbb_conf_write, 236 }; 237 #else 238 static struct cardbus_functions pccbb_funcs = { 239 pccbb_ctrl, 240 pccbb_power, 241 pccbb_mem_open, 242 pccbb_mem_close, 243 pccbb_io_open, 244 pccbb_io_close, 245 pccbb_intr_establish, 246 pccbb_intr_disestablish, 247 pccbb_make_tag, 248 pccbb_conf_read, 249 pccbb_conf_write, 250 }; 251 #endif 252 253 254 255 256 int 257 pcicbbmatch(parent, match, aux) 258 struct device *parent; 259 #ifdef __BROKEN_INDIRECT_CONFIG 260 void *match; 261 #else 262 struct cfdata *match; 263 #endif 264 void *aux; 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if ((pa->pa_class & PCI_CLASS_INTERFACE_MASK) == PCI_CLASS_INTERFACE_YENTA) { 269 /* OK, It must be YENTA PCI-CardBus bridge */ 270 271 return 1; 272 } 273 274 return 0; 275 } 276 277 278 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 279 | ((prod) << PCI_PRODUCT_SHIFT)) 280 281 282 struct yenta_chipinfo { 283 pcireg_t yc_id; /* vendor tag | product tag */ 284 const char *yc_name; 285 int yc_chiptype; 286 int yc_flags; 287 } yc_chipsets[] = { 288 /* Texas Instruments chips */ 289 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), "TI1130", CB_TI113X, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), "TI1131", CB_TI113X, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 294 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), "TI1250", CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), "TI1220", CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), "TI1221", CB_TI12XX, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), "TI1225", CB_TI12XX, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), "TI1251", CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), "TI1251B", CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), "TI1211", CB_TI12XX, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), "TI1420", CB_TI12XX, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), "TI1450", CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 {MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI2030), "TI2030", CB_UNKNOWN, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 315 /* Ricoh chips */ 316 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), "Rx5C475", 317 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 318 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), "RL5C476", 319 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 320 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), "Rx5C477", 321 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 322 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), "Rx5C478", 323 CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, 324 325 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), "Rx5C465", 326 CB_RX5C46X, PCCBB_PCMCIA_MEM_32}, 327 {MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), "Rx5C466", 328 CB_RX5C46X, PCCBB_PCMCIA_MEM_32}, 329 330 /* Toshiba products */ 331 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), "ToPIC95", 332 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 333 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), "ToPIC95B", 334 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 335 {MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), "ToPIC97", 336 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 337 338 /* Cirrus Logic products */ 339 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), "CL-PD683X", 340 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 341 {MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), "CL-PD683X", 342 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 343 344 /* sentinel, or Generic chip */ 345 {0 /* null id */, "unknown", CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 346 }; 347 348 349 350 static int 351 cb_chipset(pci_id, namep, flagp) 352 u_int32_t pci_id; 353 char const **namep; 354 int *flagp; 355 { 356 int loopend = sizeof(yc_chipsets)/sizeof(yc_chipsets[0]); 357 struct yenta_chipinfo *ycp, *ycend; 358 359 ycend = yc_chipsets + loopend; 360 361 for (ycp =yc_chipsets; ycp < ycend && pci_id != ycp->yc_id; ++ycp); 362 363 if (ycp == ycend) { 364 /* not found */ 365 ycp = yc_chipsets + loopend - 1; /* to point the sentinel */ 366 } 367 368 if (namep != NULL) { 369 *namep = ycp->yc_name; 370 } 371 372 if (flagp != NULL) { 373 *flagp = ycp->yc_flags; 374 } 375 376 return ycp->yc_chiptype; 377 } 378 379 380 381 382 383 void 384 pccbbattach(parent, self, aux) 385 struct device *parent; 386 struct device *self; 387 void *aux; 388 { 389 struct pccbb_softc *sc = (void *)self; 390 struct pci_attach_args *pa = aux; 391 pci_chipset_tag_t pc = pa->pa_pc; 392 pcireg_t sock_base, busreg; 393 bus_addr_t sockbase; 394 char const *name; 395 int flags; 396 397 sc->sc_chipset = cb_chipset(pa->pa_id, &name, &flags); 398 printf(" (%s), chipflags %d\n", name, flags); 399 400 #if rbus 401 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 402 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 403 #endif /* rbus */ 404 405 sc->sc_base_memh = 0; 406 407 /* 408 * MAP socket registers and ExCA registers on memory-space 409 * When no valid address is set on socket base registers (on pci 410 * config space), get it not polite way. 411 */ 412 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 413 414 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 415 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 416 /* The address must be valid. */ 417 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 418 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 419 NULL)) { 420 printf("%s: can't map socket base address 0x%x\n", sc->sc_dev.dv_xname, 421 sock_base); 422 /* I think it's funny: socket base registers must be mapped on 423 memory space, but ... */ 424 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 0, 425 &sc->sc_base_memt, &sc->sc_base_memh, 426 &sockbase, NULL)) { 427 printf("%s: can't map socket base address 0x%lx: io mode\n", 428 sc->sc_dev.dv_xname, sockbase); 429 /* give up... allocate register space via rbus. */ 430 sc->sc_base_memh = 0; 431 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 432 } 433 } else { 434 DPRINTF(("%s: socket base address 0x%lx",sc->sc_dev.dv_xname, sockbase)); 435 } 436 } 437 438 439 sc->sc_mem_start = 0; /* XXX */ 440 sc->sc_mem_end = 0xffffffff; /* XXX */ 441 442 /* 443 * When interrupt isn't routed correctly, give up probing cbb and do 444 * not kill pcic-compatible port. 445 */ 446 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 447 printf(" Do not use %s because of intr unconfig.\n", sc->sc_dev.dv_xname); 448 return; 449 } 450 451 /* 452 * When bus number isn't set correctly, give up using 32-bit CardBus 453 * mode. 454 */ 455 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 456 #if notyet 457 if (((busreg >> 8) & 0xff) == 0) { 458 printf(" CardBus on %s will not be configured, because of bus no unconfig.\n", sc->sc_dev.dv_xname); 459 flags |= PCCBB_PCMCIA_16BITONLY; 460 } 461 #endif 462 463 /* pccbb_machdep.c end */ 464 465 466 #if defined CBB_DEBUG 467 { 468 static char *intrname[5] = {"NON", "A", "B", "C", "D"}; 469 printf(" intrpin %s, intrtag %d\n", intrname[pa->pa_intrpin], 470 pa->pa_intrline); 471 } 472 #endif 473 474 475 /* setup softc */ 476 sc->sc_pc = pc; 477 sc->sc_iot = pa->pa_iot; 478 sc->sc_memt = pa->pa_memt; 479 sc->sc_dmat = pa->pa_dmat; 480 sc->sc_tag = pa->pa_tag; 481 sc->sc_function = pa->pa_function; 482 483 sc->sc_intrline = pa->pa_intrline; 484 sc->sc_intrtag = pa->pa_intrtag; 485 sc->sc_intrpin = pa->pa_intrpin; 486 487 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 488 489 /* bus bridge initialisation */ 490 pccbb_chipinit(sc); 491 492 #if __NetBSD_Version__ > 103060000 493 config_defer(self, pccbb_pci_callback); 494 #else 495 pccbb_pci_callback(self); 496 #endif 497 } 498 499 500 501 502 static void 503 pccbb_pci_callback(self) 504 struct device *self; 505 { 506 struct pccbb_softc *sc = (void *)self; 507 pci_chipset_tag_t pc = sc->sc_pc; 508 bus_space_tag_t base_memt; 509 bus_space_handle_t base_memh; 510 u_int32_t maskreg; 511 pci_intr_handle_t ih; 512 const char *intrstr = NULL; 513 bus_addr_t sockbase; 514 struct cbslot_attach_args cba; 515 struct pcmciabus_attach_args paa; 516 struct cardslot_attach_args caa; 517 struct cardslot_softc *csc; 518 519 if (0 == sc->sc_base_memh) { 520 /* The socket registers aren't mapped correctly. */ 521 #if rbus 522 if (rbus_space_alloc(sc->sc_rbus_memt, 523 0, /* address: I don't mind where it is mapped */ 524 0x1000, /* size */ 525 0x0fff, /* mask */ 526 0x1000, /* align */ 527 0, /* flags */ 528 &sockbase, &sc->sc_base_memh)) { 529 return; 530 } 531 sc->sc_base_memt = sc->sc_memt; 532 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 533 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 534 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 535 #else 536 sc->sc_base_memt = sc->sc_memt; 537 #if !defined CBB_PCI_BASE 538 #define CBB_PCI_BASE 0x20000000 539 #endif 540 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 541 0x1000, /* size */ 542 0x1000, /* alignment */ 543 0, /* boundary */ 544 0, /* flags */ 545 &sockbase, &sc->sc_base_memh)) { 546 /* cannot allocate memory space */ 547 return; 548 } 549 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 550 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n",sc->sc_dev.dv_xname, 551 sock_base, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); 552 #endif 553 } 554 555 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 556 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 557 558 559 /* CSC Interrupt: Card detect interrupt on */ 560 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 561 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 562 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 563 /* reset interrupt */ 564 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 565 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 566 567 568 /* Map and establish the interrupt. */ 569 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 570 sc->sc_intrline, &ih)) { 571 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 572 return; 573 } 574 intrstr = pci_intr_string(pc, ih); 575 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 576 577 if (sc->sc_ih == NULL) { 578 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 579 if (intrstr != NULL) { 580 printf(" at %s", intrstr); 581 } 582 printf("\n"); 583 return; 584 } 585 586 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 587 588 { 589 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 590 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { /* card exist */ 591 sc->sc_flags |= CBB_CARDEXIST; 592 } 593 } 594 595 /* 596 * attach cardbus 597 */ 598 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 599 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 600 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 601 602 /* initialise cbslot_attach */ 603 cba.cba_busname = "cardbus"; 604 cba.cba_iot = sc->sc_iot; 605 cba.cba_memt = sc->sc_memt; 606 cba.cba_dmat = sc->sc_dmat; 607 cba.cba_function = 0; 608 cba.cba_bus = (busreg >> 8) & 0x0ff; 609 cba.cba_cc = (void *)sc; 610 cba.cba_cf = &pccbb_funcs; 611 cba.cba_intrline = sc->sc_intrline; 612 613 #if rbus 614 cba.cba_rbus_iot = sc->sc_rbus_iot; 615 cba.cba_rbus_memt = sc->sc_rbus_memt; 616 #endif 617 618 cba.cba_cacheline = PCI_CACHELINE(bhlc); 619 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 620 621 printf("%s: cacheline 0x%x lattimer 0x%x\n", sc->sc_dev.dv_xname, 622 cba.cba_cacheline, cba.cba_lattimer); 623 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, 624 bhlc, busreg); 625 #if defined SHOW_REGS 626 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 627 #endif 628 } 629 630 pccbb_pcmcia_attach_setup(sc, &paa); 631 caa.caa_cb_attach = NULL; 632 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 633 caa.caa_cb_attach = &cba; 634 } 635 caa.caa_16_attach = &paa; 636 caa.caa_ph = &sc->sc_pcmcia_h; 637 638 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 639 DPRINTF(("pccbbattach: found cardslot\n")); 640 sc->sc_csc = csc; 641 } 642 643 return; 644 } 645 646 647 648 static void 649 pccbb_chipinit(sc) 650 struct pccbb_softc *sc; 651 { 652 pci_chipset_tag_t pc = sc->sc_pc; 653 pcitag_t tag = sc->sc_tag; 654 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory tag */ 655 bus_space_handle_t base_memh = sc->sc_base_memh; /* socket regs memory handle */ 656 pcireg_t cbctrl; 657 658 /* 659 * Set PCI command reg. 660 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 661 */ 662 { 663 pcireg_t command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 664 665 /* I believe it is harmless. */ 666 command |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 667 PCI_COMMAND_MASTER_ENABLE); 668 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 669 } 670 671 /* 672 * Set CardBus latency timer 673 */ 674 { 675 pcireg_t pci_lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 676 if (PCI_CB_LATENCY(pci_lscp) < 0x20) { 677 pci_lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 678 pci_lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 679 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, pci_lscp); 680 } 681 DPRINTF(("CardBus latency timer 0x%x (%x)\n", PCI_CB_LATENCY(pci_lscp), 682 pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 683 } 684 685 /* 686 * Set PCI latency timer 687 */ 688 { 689 pcireg_t pci_bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 690 if (PCI_LATTIMER(pci_bhlc) < 0x10) { 691 pci_bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 692 pci_bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 693 pci_conf_write(pc, tag, PCI_BHLC_REG, pci_bhlc); 694 } 695 DPRINTF(("PCI latency timer 0x%x (%x)\n", PCI_LATTIMER(pci_bhlc), 696 pci_conf_read(pc, tag, PCI_BHLC_REG))); 697 } 698 699 /* disable Legacy IO */ 700 701 switch (sc->sc_chipset) { 702 case CB_RX5C46X: /* fallthrogh */ 703 case CB_RX5C47X: 704 /* 705 * The legacy pcic io-port on Ricoh CardBus bridges cannot be 706 * disabled by substituting 0 into PCI_LEGACY register. Ricoh 707 * CardBus bridges have special bits on Bridge control reg (addr 708 * 0x3e on PCI config space). 709 */ 710 { 711 pcireg_t bcri = pci_conf_read(pc, tag, PCI_BCR_INTR); 712 bcri &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 713 pci_conf_write(pc, tag, PCI_BCR_INTR, bcri); 714 } 715 break; 716 default: 717 /* XXX: I don't know proper way to kill Legacy IO properly. */ 718 pci_conf_write(pc, tag, PCI_LEGACY, 0x0); 719 break; 720 } 721 722 723 724 /* 725 * Interrupt routing: use PCI interrupt 726 */ 727 { 728 u_int32_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 729 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */ 730 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 731 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 732 } 733 734 if (CB_TI113X == sc->sc_chipset) { 735 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 736 if (0 == sc->sc_function) { 737 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 738 } 739 cbctrl |= PCI113X_CBCTRL_PCI_IRQ_ENA; /* XXX: bug in PCI113X */ 740 cbctrl |= PCI113X_CBCTRL_PCI_CSC; /* CSC intr enable */ 741 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr prohibit */ 742 cbctrl &= ~PCI113X_CBCTRL_INT_MASK; /* prohibit ISA routing */ 743 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 744 745 /* set ExCA regs: PCI113X required to be set bit 4 at Interrupt 746 and General Register, which is IRQ Enable Register, and clear 747 bit 3:0 to zero in order to route CSC interrupt to PCI 748 interrupt pin. */ 749 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 750 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 751 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 752 #if 1 753 DPRINTF(("ExCA regs:")); 754 DPRINTF((" 0x803: %02x", bus_space_read_1(base_memt, base_memh, 0x803))); 755 DPRINTF((" 0x805: %02x", bus_space_read_1(base_memt, base_memh, 0x805))); 756 DPRINTF((" 0x81e: %02x\n", bus_space_read_1(base_memt,base_memh,0x81e))); 757 #endif 758 } else if (sc->sc_chipset == CB_TI12XX) { 759 cbctrl = pci_conf_read(pc, tag, PCI_CBCTRL); 760 cbctrl &= ~PCI12XX_CBCTRL_INT_MASK; /* intr routing reset */ 761 pci_conf_write(pc, tag, PCI_CBCTRL, cbctrl); 762 /* 763 * set ExCA regs: PCI12XX required to be set bit 4 at Interrupt 764 * and General Register, which is IRQ Enable Register, and clear 765 * bit 3:0 to zero in order to route CSC interrupt to PCI 766 * interrupt pin. 767 */ 768 bus_space_write_1(base_memt, base_memh, 0x0803, 0x10); 769 /* set ExCA regs: prohibit all pcmcia-style CSC intr. */ 770 bus_space_write_1(base_memt, base_memh, 0x0805, 0x00); 771 } else if (sc->sc_chipset == CB_TOPIC95B) { 772 cardbusreg_t sock_ctrl, slot_ctrl; 773 774 sock_ctrl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 775 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, 776 sock_ctrl | TOPIC_SOCKET_CTRL_SCR_IRQSEL); 777 778 slot_ctrl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 779 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", sc->sc_dev.dv_xname, 780 slot_ctrl)); 781 slot_ctrl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 782 TOPIC_SLOT_CTRL_ID_LOCK); 783 slot_ctrl |= TOPIC_SLOT_CTRL_CARDBUS; 784 slot_ctrl &= ~TOPIC_SLOT_CTRL_SWDETECT; 785 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slot_ctrl); 786 DPRINTF(("0x%x\n", slot_ctrl)); 787 } 788 789 /* close all memory and io windows */ 790 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 791 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 792 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 793 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 794 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 795 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 796 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 797 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 798 799 return; 800 } 801 802 803 804 /* 805 * attach pccard bus 806 */ 807 STATIC void 808 pccbb_pcmcia_attach_setup(sc, paa) 809 struct pccbb_softc *sc; 810 struct pcmciabus_attach_args *paa; 811 { 812 struct pcic_handle *ph = &sc->sc_pcmcia_h; 813 814 /* initialise pcmcia part in pccbb_softc */ 815 ph->ph_parent = (struct device *)sc; 816 ph->sock = sc->sc_function; 817 ph->flags = 0; 818 ph->shutdown = 0; 819 ph->ih_irq = sc->sc_intrline; 820 ph->ph_bus_t = sc->sc_base_memt; 821 ph->ph_bus_h = sc->sc_base_memh; 822 ph->ph_read = pccbb_pcmcia_read; 823 ph->ph_write = pccbb_pcmcia_write; 824 sc->sc_pct = &pccbb_pcmcia_funcs; 825 826 Pcic_write(ph, PCIC_CSC_INTR, 0); 827 Pcic_read(ph, PCIC_CSC); 828 829 /* initialise pcmcia bus attachment */ 830 paa->paa_busname = "pcmcia"; 831 paa->pct = sc->sc_pct; 832 paa->pch = ph; 833 paa->iobase = 0; /* I don't use them */ 834 paa->iosize = 0; 835 836 return; 837 } 838 839 840 #if 0 841 STATIC void 842 pccbb_pcmcia_attach_card(ph) 843 struct pcic_handle *ph; 844 { 845 if (ph->flags & PCIC_FLAG_CARDP) { 846 panic("pccbb_pcmcia_attach_card: already attached"); 847 } 848 849 /* call the MI attach function */ 850 pcmcia_card_attach(ph->pcmcia); 851 852 ph->flags |= PCIC_FLAG_CARDP; 853 } 854 855 856 STATIC void 857 pccbb_pcmcia_detach_card(ph, flags) 858 struct pcic_handle *ph; 859 int flags; 860 { 861 if (!(ph->flags & PCIC_FLAG_CARDP)) { 862 panic("pccbb_pcmcia_detach_card: already detached"); 863 } 864 865 ph->flags &= ~PCIC_FLAG_CARDP; 866 867 /* call the MI detach function */ 868 pcmcia_card_detach(ph->pcmcia, flags); 869 } 870 #endif 871 872 873 874 875 /* 876 * int pccbbintr(arg) 877 * void *arg; 878 * This routine handles the interrupt from Yenta PCI-CardBus bridge 879 * itself. 880 */ 881 int 882 pccbbintr(arg) 883 void *arg; 884 { 885 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 886 u_int32_t sockevent; 887 bus_space_tag_t memt = sc->sc_base_memt; 888 bus_space_handle_t memh = sc->sc_base_memh; 889 u_int32_t sockstate; 890 891 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 892 if (0 == sockevent) { /* not for me */ 893 return 0; 894 } else { 895 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); /* reset bit */ 896 } 897 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 898 899 if (sockevent & CB_SOCKET_EVENT_CD) { 900 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 901 /* A card should be removed. */ 902 if (sc->sc_flags & CBB_CARDEXIST) { 903 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 904 DPRINTF((" card removed, 0x%08x\n", sockstate)); 905 sc->sc_flags &= ~CBB_CARDEXIST; 906 if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { 907 #if 0 908 struct pcic_handle *ph = &sc->sc_pcmcia_h; 909 910 pcmcia_card_deactivate(ph->pcmcia); 911 pccbb_pcmcia_socket_disable(ph); 912 pccbb_pcmcia_detach_card(ph, DETACH_FORCE); 913 #endif 914 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_16); 915 } else if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) { 916 /* Cardbus intr removed */ 917 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_CB); 918 } 919 } 920 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD)) { 921 if (sc->sc_flags & CBB_INSERTING) { 922 untimeout(pci113x_insert, sc); 923 } 924 timeout(pci113x_insert, sc, hz/10); 925 sc->sc_flags |= CBB_INSERTING; 926 } 927 } else { 928 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 929 if (sockevent & CB_SOCKET_EVENT_CSTS) { 930 DPRINTF((" cstsevent occures, 0x%08x\n", sockstate)); 931 } 932 if (sockevent & CB_SOCKET_EVENT_POWER) { 933 DPRINTF((" pwrevent occures, 0x%08x\n", sockstate)); 934 } 935 } 936 937 return 1; 938 } 939 940 941 942 static void 943 pci113x_insert(arg) 944 void *arg; 945 { 946 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 947 u_int32_t sockevent, sockstate; 948 949 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 950 CB_SOCKET_EVENT); 951 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 952 CB_SOCKET_STAT); 953 954 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 955 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 956 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 957 sc->sc_flags |= CBB_CARDEXIST; 958 /* call pccard intterupt handler here */ 959 if (sockstate & CB_SOCKET_STAT_16BIT) { 960 /* 16-bit card found */ 961 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 962 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_16); 963 } else if (sockstate & CB_SOCKET_STAT_CB) { 964 /* cardbus card fuond */ 965 /* cardbus_attach_card(sc->sc_csc); */ 966 cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_CB); 967 } else { 968 /* who are you? */ 969 } 970 } else { 971 timeout(pci113x_insert, sc, hz/10); 972 } 973 } 974 975 976 977 978 #define PCCBB_PCMCIA_OFFSET 0x800 979 static u_int8_t 980 pccbb_pcmcia_read(ph, reg) 981 struct pcic_handle *ph; 982 int reg; 983 { 984 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg); 985 } 986 987 988 989 static void 990 pccbb_pcmcia_write(ph, reg, val) 991 struct pcic_handle *ph; 992 int reg; 993 u_int8_t val; 994 { 995 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, val); 996 997 return; 998 } 999 1000 1001 1002 1003 /* 1004 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1005 */ 1006 STATIC int 1007 pccbb_ctrl(ct, command) 1008 cardbus_chipset_tag_t ct; 1009 int command; 1010 { 1011 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1012 1013 switch(command) { 1014 case CARDBUS_CD: 1015 if (2 == pccbb_detect_card(sc)) { 1016 int retval = 0; 1017 int status = cb_detect_voltage(sc); 1018 if (PCCARD_VCC_5V & status) { 1019 retval |= CARDBUS_5V_CARD; 1020 } 1021 if (PCCARD_VCC_3V & status) { 1022 retval |= CARDBUS_3V_CARD; 1023 } 1024 if (PCCARD_VCC_XV & status) { 1025 retval |= CARDBUS_XV_CARD; 1026 } 1027 if (PCCARD_VCC_YV & status) { 1028 retval |= CARDBUS_YV_CARD; 1029 } 1030 return retval; 1031 } else { 1032 return 0; 1033 } 1034 break; 1035 case CARDBUS_RESET: 1036 return cb_reset(sc); 1037 break; 1038 case CARDBUS_IO_ENABLE: /* fallthrough */ 1039 case CARDBUS_IO_DISABLE: /* fallthrough */ 1040 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1041 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1042 case CARDBUS_BM_ENABLE: /* fallthrough */ 1043 case CARDBUS_BM_DISABLE: /* fallthrough */ 1044 return pccbb_cardenable(sc, command); 1045 break; 1046 } 1047 1048 return 0; 1049 } 1050 1051 1052 1053 /* 1054 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1055 * This function returns true when it succeeds and returns false when 1056 * it fails. 1057 */ 1058 STATIC int 1059 pccbb_power(ct, command) 1060 cardbus_chipset_tag_t ct; 1061 int command; 1062 { 1063 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1064 1065 u_int32_t status, sock_ctrl; 1066 bus_space_tag_t memt = sc->sc_base_memt; 1067 bus_space_handle_t memh = sc->sc_base_memh; 1068 1069 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1070 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1071 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1072 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1073 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1074 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1075 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1076 "UNKNOWN", 1077 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1078 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1079 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1080 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1081 "UNKNOWN", 1082 command)); 1083 1084 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1085 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1086 1087 switch (command & CARDBUS_VCCMASK) { 1088 case CARDBUS_VCC_UC: 1089 break; 1090 case CARDBUS_VCC_5V: 1091 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1092 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1093 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1094 } else { 1095 printf("%s: BAD voltage request: no 5 V card\n", sc->sc_dev.dv_xname); 1096 } 1097 break; 1098 case CARDBUS_VCC_3V: 1099 if (CB_SOCKET_STAT_3VCARD & status) { 1100 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1101 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1102 } else { 1103 printf("%s: BAD voltage request: no 3.3 V card\n", sc->sc_dev.dv_xname); 1104 } 1105 break; 1106 case CARDBUS_VCC_0V: 1107 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1108 break; 1109 default: 1110 return 0; /* power NEVER changed */ 1111 break; 1112 } 1113 1114 switch (command & CARDBUS_VPPMASK) { 1115 case CARDBUS_VPP_UC: 1116 break; 1117 case CARDBUS_VPP_0V: 1118 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1119 break; 1120 case CARDBUS_VPP_VCC: 1121 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1122 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1123 break; 1124 case CARDBUS_VPP_12V: 1125 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1126 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1127 break; 1128 } 1129 1130 #if 0 1131 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1132 #endif 1133 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1134 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1135 1136 delay(20*1000); /* wait 20 ms: Vcc setup time */ 1137 /* XXX 1138 delay 200 ms: though the standard defines that the Vcc set-up time 1139 is 20 ms, some PC-Card bridge requires longer duration. 1140 */ 1141 delay(200*1000); 1142 1143 1144 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1145 printf("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1146 sc->sc_dev.dv_xname, sock_ctrl ,status); 1147 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1148 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1149 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V": 1150 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V": 1151 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV": 1152 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV": 1153 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V": 1154 "UNKNOWN", 1155 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC": 1156 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ?"CARDBUS_VPP_12V": 1157 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ?"CARDBUS_VPP_VCC": 1158 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1159 "UNKNOWN", 1160 command)); 1161 #if 0 1162 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1163 u_int32_t force = bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1164 /* Reset Bad Vcc request */ 1165 force &= ~CB_SOCKET_FORCE_BADVCC; 1166 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1167 printf("new status 0x%x\n", bus_space_read_4(memt, memh,CB_SOCKET_STAT)); 1168 return 1; 1169 } 1170 #endif 1171 return 0; 1172 } 1173 return 1; /* power changed correctly */ 1174 } 1175 1176 1177 1178 1179 1180 1181 #if defined CB_PCMCIA_POLL 1182 struct cb_poll_str { 1183 void *arg; 1184 int (* func) __P((void *)); 1185 int level; 1186 pccard_chipset_tag_t ct; 1187 int count; 1188 }; 1189 1190 static struct cb_poll_str cb_poll[10]; 1191 static int cb_poll_n = 0; 1192 1193 static void cb_pcmcia_poll __P((void *arg)); 1194 1195 static void 1196 cb_pcmcia_poll(arg) 1197 void *arg; 1198 { 1199 struct cb_poll_str *poll = arg; 1200 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1201 struct pccbb_softc *sc = psc->cpc_parent; 1202 int s; 1203 u_int32_t spsr; /* socket present-state reg */ 1204 1205 timeout(cb_pcmcia_poll, arg, hz/10); 1206 switch (poll->level) { 1207 case IPL_NET: 1208 s = splnet(); 1209 break; 1210 case IPL_BIO: 1211 s = splbio(); 1212 break; 1213 case IPL_TTY: /* fallthrough */ 1214 default: 1215 s = spltty(); 1216 break; 1217 } 1218 1219 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 1220 1221 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1222 if (!(spsr & 0x40)) { /* CINT low */ 1223 #else 1224 if (1) { 1225 #endif 1226 if ((*poll->func)(poll->arg) == 1) { 1227 ++poll->count; 1228 printf("intr: reported from poller, 0x%x\n", spsr); 1229 #if defined LEVEL2 1230 } else { 1231 printf("intr: miss! 0x%x\n", spsr); 1232 #endif 1233 } 1234 } 1235 splx(s); 1236 } 1237 #endif /* defined CB_PCMCIA_POLL */ 1238 1239 1240 1241 1242 /* 1243 * static int pccbb_detect_card(struct pccbb_softc *sc) 1244 * return value: 0 if no card exists. 1245 * 1 if 16-bit card exists. 1246 * 2 if cardbus card exists. 1247 */ 1248 static int 1249 pccbb_detect_card(sc) 1250 struct pccbb_softc *sc; 1251 { 1252 bus_space_handle_t base_memh = sc->sc_base_memh; 1253 bus_space_tag_t base_memt = sc->sc_base_memt; 1254 u_int32_t sockstat = bus_space_read_4(base_memt,base_memh, CB_SOCKET_STAT); 1255 int retval = 0; 1256 1257 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { /* CD1 and CD2 asserted */ 1258 /* card must be present */ 1259 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { /* NOTACARD DEASSERTED */ 1260 if (CB_SOCKET_STAT_CB & sockstat) { /* CardBus mode */ 1261 retval = 2; 1262 } else if (CB_SOCKET_STAT_16BIT & sockstat) { /* 16-bit mode */ 1263 retval = 1; 1264 } 1265 } 1266 } 1267 return retval; 1268 } 1269 1270 1271 1272 1273 /* 1274 * STATIC int cb_reset(struct pccbb_softc *sc) 1275 * This function resets CardBus card. 1276 */ 1277 STATIC int 1278 cb_reset(sc) 1279 struct pccbb_softc *sc; 1280 { 1281 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1282 bcr |= (0x40 << 16); /* Reset bit Assert (bit 6 at 0x3E) */ 1283 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1284 /* Reset Assert at least 20 ms */ 1285 delay(20*1000); 1286 1287 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1288 bcr &= ~(0x40 << 16); /* Reset bit Deassert (bit 6 at 0x3E) */ 1289 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1290 delay(20*1000); 1291 } 1292 /* No card found on the slot. Keep Reset. */ 1293 return 1; 1294 } 1295 1296 1297 1298 1299 /* 1300 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1301 * This function detect card Voltage. 1302 */ 1303 STATIC int 1304 cb_detect_voltage(sc) 1305 struct pccbb_softc *sc; 1306 { 1307 u_int32_t psr; /* socket present-state reg */ 1308 bus_space_tag_t iot = sc->sc_base_memt; 1309 bus_space_handle_t ioh = sc->sc_base_memh; 1310 int vol = PCCARD_VCC_UKN; /* set 0 */ 1311 1312 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1313 1314 if (0x400u & psr) { 1315 vol |= PCCARD_VCC_5V; 1316 } 1317 if (0x800u & psr) { 1318 vol |= PCCARD_VCC_3V; 1319 } 1320 1321 return vol; 1322 } 1323 1324 1325 1326 1327 1328 1329 STATIC int 1330 cbbprint(aux, pcic) 1331 void *aux; 1332 const char *pcic; 1333 { 1334 /* 1335 struct cbslot_attach_args *cba = aux; 1336 1337 if (cba->cba_slot >= 0) { 1338 printf(" slot %d", cba->cba_slot); 1339 } 1340 */ 1341 return UNCONF; 1342 } 1343 1344 1345 1346 1347 /* 1348 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1349 * This function enables and disables the card 1350 */ 1351 STATIC int 1352 pccbb_cardenable(sc, function) 1353 struct pccbb_softc *sc; 1354 int function; 1355 { 1356 u_int32_t command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1357 1358 DPRINTF(("pccbb_cardenable:")); 1359 switch (function) { 1360 case CARDBUS_IO_ENABLE: 1361 command |= PCI_COMMAND_IO_ENABLE; 1362 break; 1363 case CARDBUS_IO_DISABLE: 1364 command &= ~PCI_COMMAND_IO_ENABLE; 1365 break; 1366 case CARDBUS_MEM_ENABLE: 1367 command |= PCI_COMMAND_MEM_ENABLE; 1368 break; 1369 case CARDBUS_MEM_DISABLE: 1370 command &= ~PCI_COMMAND_MEM_ENABLE; 1371 break; 1372 case CARDBUS_BM_ENABLE: 1373 command |= PCI_COMMAND_MASTER_ENABLE; 1374 break; 1375 case CARDBUS_BM_DISABLE: 1376 command &= ~PCI_COMMAND_MASTER_ENABLE; 1377 break; 1378 default: 1379 return 0; 1380 } 1381 1382 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1383 DPRINTF((" command reg 0x%x\n", command)); 1384 return 1; 1385 } 1386 1387 1388 1389 1390 1391 1392 #if !rbus 1393 /* 1394 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1395 */ 1396 static int 1397 pccbb_io_open(ct, win, start, end) 1398 cardbus_chipset_tag_t ct; 1399 int win; 1400 u_int32_t start, end; 1401 { 1402 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1403 int basereg; 1404 int limitreg; 1405 1406 if ((win < 0) || (win > 2)) { 1407 #if defined DIAGNOSTIC 1408 printf("cardbus_io_open: window out of range %d\n", win); 1409 #endif 1410 return 0; 1411 } 1412 1413 basereg = win*8 + 0x2c; 1414 limitreg = win*8 + 0x30; 1415 1416 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1417 start, basereg, end, limitreg)); 1418 1419 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1420 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1421 return 1; 1422 } 1423 1424 /* 1425 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1426 */ 1427 static int 1428 pccbb_io_close(ct, win) 1429 cardbus_chipset_tag_t ct; 1430 int win; 1431 { 1432 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1433 int basereg; 1434 int limitreg; 1435 1436 if ((win < 0) || (win > 2)) { 1437 #if defined DIAGNOSTIC 1438 printf("cardbus_io_close: window out of range %d\n", win); 1439 #endif 1440 return 0; 1441 } 1442 1443 basereg = win*8 + 0x2c; 1444 limitreg = win*8 + 0x30; 1445 1446 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1447 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1448 return 1; 1449 } 1450 1451 /* 1452 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1453 */ 1454 static int 1455 pccbb_mem_open(ct, win, start, end) 1456 cardbus_chipset_tag_t ct; 1457 int win; 1458 u_int32_t start, end; 1459 { 1460 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1461 int basereg; 1462 int limitreg; 1463 1464 if ((win < 0) || (win > 2)) { 1465 #if defined DIAGNOSTIC 1466 printf("cardbus_mem_open: window out of range %d\n", win); 1467 #endif 1468 return 0; 1469 } 1470 1471 basereg = win*8 + 0x1c; 1472 limitreg = win*8 + 0x20; 1473 1474 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1475 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1476 return 1; 1477 } 1478 1479 1480 /* 1481 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1482 */ 1483 static int 1484 pccbb_mem_close(ct, win) 1485 cardbus_chipset_tag_t ct; 1486 int win; 1487 { 1488 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1489 int basereg; 1490 int limitreg; 1491 1492 if ((win < 0) || (win > 2)) { 1493 #if defined DIAGNOSTIC 1494 printf("cardbus_mem_close: window out of range %d\n", win); 1495 #endif 1496 return 0; 1497 } 1498 1499 basereg = win*8 + 0x1c; 1500 limitreg = win*8 + 0x20; 1501 1502 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1503 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1504 return 1; 1505 } 1506 #endif 1507 1508 1509 1510 static void * 1511 pccbb_intr_establish(ct, irq, level, func, arg) 1512 cardbus_chipset_tag_t ct; 1513 int irq, level; 1514 int (* func) __P((void *)); 1515 void *arg; 1516 { 1517 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1518 1519 switch (sc->sc_chipset) { 1520 case CB_TI113X: 1521 { 1522 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1523 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* functional intr enabled */ 1524 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1525 } 1526 break; 1527 default: 1528 break; 1529 } 1530 1531 return pci_intr_establish(sc->sc_pc, irq, level, func, arg); 1532 } 1533 1534 1535 1536 1537 static void 1538 pccbb_intr_disestablish(ct, ih) 1539 cardbus_chipset_tag_t ct; 1540 void *ih; 1541 { 1542 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1543 1544 switch (sc->sc_chipset) { 1545 case CB_TI113X: 1546 { 1547 pcireg_t cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1548 cbctrl &= ~PCI113X_CBCTRL_PCI_INTR; /* functional intr disabled */ 1549 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1550 } 1551 break; 1552 default: 1553 break; 1554 } 1555 1556 pci_intr_disestablish(sc->sc_pc, ih); 1557 } 1558 1559 1560 1561 1562 1563 #if defined SHOW_REGS 1564 static void 1565 cb_show_regs(pc, tag, memt, memh) 1566 pci_chipset_tag_t pc; 1567 pcitag_t tag; 1568 bus_space_tag_t memt; 1569 bus_space_handle_t memh; 1570 { 1571 int i; 1572 printf("PCI config regs:"); 1573 for (i = 0; i < 0x50; i += 4) { 1574 if (i % 16 == 0) { 1575 printf("\n 0x%02x:", i); 1576 } 1577 printf(" %08x", pci_conf_read(pc, tag, i)); 1578 } 1579 for (i = 0x80; i < 0xb0; i += 4) { 1580 if (i % 16 == 0) { 1581 printf("\n 0x%02x:", i); 1582 } 1583 printf(" %08x", pci_conf_read(pc, tag, i)); 1584 } 1585 1586 if (memh == 0) { 1587 printf("\n"); 1588 return; 1589 } 1590 1591 printf("\nsocket regs:"); 1592 for (i = 0; i <= 0x10; i += 0x04) { 1593 printf(" %08x", bus_space_read_4(memt, memh, i)); 1594 } 1595 printf("\nExCA regs:"); 1596 for (i = 0; i < 0x08; ++i) { 1597 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1598 } 1599 printf("\n"); 1600 return; 1601 } 1602 #endif 1603 1604 1605 1606 /* 1607 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1608 * int busno, int devno, int function) 1609 * This is the function to make a tag to access config space of 1610 * a CardBus Card. It works same as pci_conf_read. 1611 */ 1612 static cardbustag_t 1613 pccbb_make_tag(cc, busno, devno, function) 1614 cardbus_chipset_tag_t cc; 1615 int busno, devno, function; 1616 { 1617 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1618 1619 return pci_make_tag(sc->sc_pc, busno, devno, function); 1620 } 1621 1622 1623 static void 1624 pccbb_free_tag(cc, tag) 1625 cardbus_chipset_tag_t cc; 1626 cardbustag_t tag; 1627 { 1628 } 1629 1630 1631 /* 1632 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1633 * cardbustag_t tag, int offset) 1634 * This is the function to read the config space of a CardBus Card. 1635 * It works same as pci_conf_read. 1636 */ 1637 static cardbusreg_t 1638 pccbb_conf_read(cc, tag, offset) 1639 cardbus_chipset_tag_t cc; 1640 cardbustag_t tag; 1641 int offset; /* register offset */ 1642 { 1643 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1644 1645 return pci_conf_read(sc->sc_pc, tag, offset); 1646 } 1647 1648 1649 1650 /* 1651 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1652 * int offs, cardbusreg_t val) 1653 * This is the function to write the config space of a CardBus Card. 1654 * It works same as pci_conf_write. 1655 */ 1656 static void 1657 pccbb_conf_write(cc, tag, reg, val) 1658 cardbus_chipset_tag_t cc; 1659 cardbustag_t tag; 1660 int reg; /* register offset */ 1661 cardbusreg_t val; 1662 { 1663 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1664 1665 pci_conf_write(sc->sc_pc, tag, reg, val); 1666 } 1667 1668 1669 1670 1671 1672 #if 0 1673 STATIC int 1674 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1675 bus_addr_t start, bus_size_t size, 1676 bus_size_t align, bus_addr_t mask, /* address line width */ 1677 int speed, int flags, /* bus width */ 1678 bus_space_handle_t *iohp) 1679 #endif 1680 1681 1682 /* 1683 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1684 * bus_addr_t start, bus_size_t size, 1685 * bus_size_t align, 1686 * struct pcmcia_io_handle *pcihp 1687 * 1688 * This function only allocates I/O region for pccard. This function 1689 * never maps the allcated region to pccard I/O area. 1690 * 1691 * XXX: The interface of this function is not very good, I believe. 1692 */ 1693 STATIC int 1694 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1695 pcmcia_chipset_handle_t pch; 1696 bus_addr_t start; /* start address */ 1697 bus_size_t size; 1698 bus_size_t align; 1699 struct pcmcia_io_handle *pcihp; 1700 { 1701 struct pcic_handle *ph = (struct pcic_handle *)pch; 1702 bus_addr_t ioaddr; 1703 int flags = 0; 1704 bus_space_tag_t iot; 1705 bus_space_handle_t ioh; 1706 #if rbus 1707 rbus_tag_t rb; 1708 #endif 1709 if (align == 0) { 1710 align = size; /* XXX: funny??? */ 1711 } 1712 1713 1714 /* 1715 * Allocate some arbitrary I/O space. 1716 */ 1717 1718 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1719 1720 #if rbus 1721 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1722 if (rbus_space_alloc(rb, start, size, 0x3ff /* XXX: I assume all card decode lower 10 bits by its hardware */, 1723 align, 0, &ioaddr, &ioh)) { 1724 return 1; 1725 } 1726 #else 1727 if (start) { 1728 ioaddr = start; 1729 if (bus_space_map(iot, start, size, 0, &ioh)) { 1730 return 1; 1731 } 1732 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1733 (u_long) ioaddr, (u_long) size)); 1734 } else { 1735 flags |= PCMCIA_IO_ALLOCATED; 1736 if (bus_space_alloc(iot, 0x700/* ph->sc->sc_iobase */, 1737 0x800/* ph->sc->sc_iobase + ph->sc->sc_iosize*/, 1738 size, align, 0, 0, &ioaddr, &ioh)) { 1739 /* No room be able to be get. */ 1740 return 1; 1741 } 1742 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1743 (u_long) ioaddr, (u_long) size)); 1744 } 1745 #endif 1746 1747 pcihp->iot = iot; 1748 pcihp->ioh = ioh; 1749 pcihp->addr = ioaddr; 1750 pcihp->size = size; 1751 pcihp->flags = flags; 1752 1753 return 0; 1754 } 1755 1756 1757 1758 1759 1760 /* 1761 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1762 * struct pcmcia_io_handle *pcihp) 1763 * 1764 * This function only frees I/O region for pccard. 1765 * 1766 * XXX: The interface of this function is not very good, I believe. 1767 */ 1768 void 1769 pccbb_pcmcia_io_free(pch, pcihp) 1770 pcmcia_chipset_handle_t pch; 1771 struct pcmcia_io_handle *pcihp; 1772 { 1773 #if !rbus 1774 bus_space_tag_t iot = pcihp->iot; 1775 #endif 1776 bus_space_handle_t ioh = pcihp->ioh; 1777 bus_size_t size = pcihp->size; 1778 1779 #if rbus 1780 struct pccbb_softc *sc = (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1781 rbus_tag_t rb = sc->sc_rbus_iot; 1782 1783 rbus_space_free(rb, ioh, size, NULL); 1784 #else 1785 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1786 bus_space_free(iot, ioh, size); 1787 else 1788 bus_space_unmap(iot, ioh, size); 1789 #endif 1790 } 1791 1792 1793 1794 /* 1795 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1796 * bus_addr_t offset, bus_size_t size, 1797 * struct pcmcia_io_handle *pcihp, 1798 * int *windowp) 1799 * 1800 * This function maps the allocated I/O region to pccard. This function 1801 * never allocates any I/O region for pccard I/O area. I don't 1802 * understand why the original authors of pcmciabus separated alloc and 1803 * map. I believe the two must be unite. 1804 * 1805 * XXX: no wait timing control? 1806 */ 1807 int 1808 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1809 pcmcia_chipset_handle_t pch; 1810 int width; 1811 bus_addr_t offset; 1812 bus_size_t size; 1813 struct pcmcia_io_handle *pcihp; 1814 int *windowp; 1815 { 1816 struct pcic_handle *ph = (struct pcic_handle *) pch; 1817 bus_addr_t ioaddr = pcihp->addr + offset; 1818 int i, win; 1819 #if defined CBB_DEBUG 1820 static char *width_names[] = { "dynamic", "io8", "io16" }; 1821 #endif 1822 1823 /* Sanity check I/O handle. */ 1824 1825 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1826 panic("pccbb_pcmcia_io_map iot is bogus"); 1827 } 1828 1829 /* XXX Sanity check offset/size. */ 1830 1831 win = -1; 1832 for (i = 0; i < PCIC_IO_WINS; i++) { 1833 if ((ph->ioalloc & (1 << i)) == 0) { 1834 win = i; 1835 ph->ioalloc |= (1 << i); 1836 break; 1837 } 1838 } 1839 1840 if (win == -1) { 1841 return 1; 1842 } 1843 1844 *windowp = win; 1845 1846 /* XXX this is pretty gross */ 1847 1848 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1849 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1850 1851 /* XXX wtf is this doing here? */ 1852 1853 #if 0 1854 printf(" port 0x%lx", (u_long) ioaddr); 1855 if (size > 1) { 1856 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1857 } 1858 #endif 1859 1860 ph->io[win].addr = ioaddr; 1861 ph->io[win].size = size; 1862 ph->io[win].width = width; 1863 1864 /* actual dirty register-value changing in the function below. */ 1865 pccbb_pcmcia_do_io_map(ph, win); 1866 1867 return 0; 1868 } 1869 1870 1871 1872 /* 1873 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1874 * 1875 * This function changes register-value to map I/O region for pccard. 1876 */ 1877 static void 1878 pccbb_pcmcia_do_io_map(ph, win) 1879 struct pcic_handle *ph; 1880 int win; 1881 { 1882 static u_int8_t pcic_iowidth[3] = { 1883 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1884 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_8BIT, 1885 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | PCIC_IOCTL_IO0_DATASIZE_16BIT, 1886 }; 1887 1888 #define PCIC_SIA_START_LOW 0 1889 #define PCIC_SIA_START_HIGH 1 1890 #define PCIC_SIA_STOP_LOW 2 1891 #define PCIC_SIA_STOP_HIGH 3 1892 1893 int regbase_win = 0x8 + win*0x04; 1894 u_int8_t ioctl, enable; 1895 1896 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1897 win, (long) ph->io[win].addr, (long) ph->io[win].size, 1898 ph->io[win].width * 8)); 1899 1900 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1901 ph->io[win].addr & 0xff); 1902 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1903 (ph->io[win].addr >> 8) & 0xff); 1904 1905 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1906 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1907 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1908 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1909 1910 ioctl = Pcic_read(ph, PCIC_IOCTL); 1911 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1912 switch (win) { 1913 case 0: 1914 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1915 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK); 1916 ioctl |= pcic_iowidth[ph->io[win].width]; 1917 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1918 break; 1919 case 1: 1920 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1921 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK); 1922 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1923 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1924 break; 1925 } 1926 Pcic_write(ph, PCIC_IOCTL, ioctl); 1927 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1928 #if defined CBB_DEBUG 1929 { 1930 u_int8_t start_low = Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1931 u_int8_t start_high = Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1932 u_int8_t stop_low = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1933 u_int8_t stop_high = Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1934 printf(" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1935 start_low, start_high, stop_low, stop_high, ioctl, enable); 1936 } 1937 #endif 1938 } 1939 1940 1941 1942 /* 1943 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1944 * 1945 * This function unmapss I/O region. No return value. 1946 */ 1947 STATIC void 1948 pccbb_pcmcia_io_unmap(pch, win) 1949 pcmcia_chipset_handle_t pch; 1950 int win; 1951 { 1952 struct pcic_handle *ph = (struct pcic_handle *)pch; 1953 int reg; 1954 1955 if (win >= PCIC_IO_WINS || win < 0) { 1956 panic("pccbb_pcmcia_io_unmap: window out of range"); 1957 } 1958 1959 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1960 switch (win) { 1961 case 0: 1962 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1963 break; 1964 case 1: 1965 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1966 break; 1967 } 1968 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 1969 1970 ph->ioalloc &= ~(1 << win); 1971 } 1972 1973 1974 1975 1976 1977 /* 1978 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1979 * 1980 * This function enables the card. All information is stored in 1981 * the first argument, pcmcia_chipset_handle_t. 1982 */ 1983 static void 1984 pccbb_pcmcia_wait_ready(ph) 1985 struct pcic_handle *ph; 1986 { 1987 int i; 1988 1989 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 1990 Pcic_read(ph, PCIC_IF_STATUS))); 1991 1992 for (i = 0; i < 10000; i++) { 1993 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 1994 return; 1995 } 1996 delay(500); 1997 #ifdef CBB_DEBUG 1998 if ((i > 5000) && (i%100 == 99)) 1999 printf("."); 2000 #endif 2001 } 2002 2003 #ifdef DIAGNOSTIC 2004 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2005 Pcic_read(ph, PCIC_IF_STATUS)); 2006 #endif 2007 } 2008 2009 2010 2011 /* 2012 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2013 * 2014 * This function enables the card. All information is stored in 2015 * the first argument, pcmcia_chipset_handle_t. 2016 */ 2017 STATIC void 2018 pccbb_pcmcia_socket_enable(pch) 2019 pcmcia_chipset_handle_t pch; 2020 { 2021 struct pcic_handle *ph = (struct pcic_handle *)pch; 2022 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2023 int cardtype, win; 2024 u_int8_t power, intr; 2025 pcireg_t spsr; 2026 int voltage; 2027 #define PCIC_INTR_PCI PCIC_INTR_ENABLE 2028 2029 /* this bit is mostly stolen from pcic_attach_card */ 2030 2031 DPRINTF(("pccbb_pcmcia_socket_enable:\n")); 2032 2033 /* get card Vcc info */ 2034 2035 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2036 if (spsr & CB_SOCKET_STAT_5VCARD) { 2037 DPRINTF(("5V card\n")); 2038 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2039 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2040 DPRINTF(("3V card\n")); 2041 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2042 } else { 2043 printf("?V card, 0x%x\n", spsr); /* XXX */ 2044 return; 2045 } 2046 2047 /* assert reset bit */ 2048 2049 intr = Pcic_read(ph, PCIC_INTR); 2050 intr &= ~PCIC_INTR_RESET; 2051 intr |= PCIC_INTR_PCI; /* XXX */ 2052 Pcic_write(ph, PCIC_INTR, intr); 2053 2054 /* disable socket i/o: negate output enable bit */ 2055 2056 power = Pcic_read(ph, PCIC_PWRCTL); 2057 power &= ~PCIC_PWRCTL_OE; 2058 Pcic_write(ph, PCIC_PWRCTL, power); 2059 2060 /* power down the socket to reset it, clear the card reset pin */ 2061 2062 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2063 2064 /* 2065 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2066 * we are changing Vcc (Toff). 2067 */ 2068 /* delay(300*1000); too much */ 2069 2070 /* power up the socket */ 2071 pccbb_power(sc, voltage); 2072 2073 /* 2074 * wait 100ms until power raise (Tpr) and 20ms to become 2075 * stable (Tsu(Vcc)). 2076 * 2077 * some machines require some more time to be settled 2078 * (another 200ms is added here). 2079 */ 2080 /* delay((100 + 20 + 200)*1000); too much */ 2081 2082 power = Pcic_read(ph, PCIC_PWRCTL); 2083 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2084 2085 /* 2086 * hold RESET at least 10us. 2087 */ 2088 delay(10); 2089 delay(2*1000); /* XXX: TI1130 requires it. */ 2090 delay(20*1000); /* XXX: TI1130 requires it. */ 2091 2092 /* clear the reset flag */ 2093 2094 intr = Pcic_read(ph, PCIC_INTR); 2095 Pcic_write(ph, PCIC_INTR, intr | PCIC_INTR_RESET); 2096 2097 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2098 2099 delay(20000); 2100 2101 /* wait for the chip to finish initializing */ 2102 2103 pccbb_pcmcia_wait_ready(ph); 2104 2105 /* zero out the address windows */ 2106 2107 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2108 2109 /* set the card type */ 2110 2111 cardtype = pcmcia_card_gettype(ph->pcmcia); 2112 2113 intr = Pcic_read(ph, PCIC_INTR); 2114 intr &= ~PCIC_INTR_CARDTYPE_MASK; 2115 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2116 PCIC_INTR_CARDTYPE_IO : 2117 PCIC_INTR_CARDTYPE_MEM); 2118 Pcic_write(ph, PCIC_INTR, intr); 2119 2120 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2121 ph->ph_parent->dv_xname, ph->sock, 2122 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2123 2124 /* reinstall all the memory and io mappings */ 2125 2126 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2127 if (ph->memalloc & (1 << win)) { 2128 pccbb_pcmcia_do_mem_map(ph, win); 2129 } 2130 } 2131 2132 for (win = 0; win < PCIC_IO_WINS; ++win) { 2133 if (ph->ioalloc & (1 << win)) { 2134 pccbb_pcmcia_do_io_map(ph, win); 2135 } 2136 } 2137 } 2138 2139 2140 2141 /* 2142 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2143 * 2144 * This function disables the card. All information is stored in 2145 * the first argument, pcmcia_chipset_handle_t. 2146 */ 2147 STATIC void 2148 pccbb_pcmcia_socket_disable(pch) 2149 pcmcia_chipset_handle_t pch; 2150 { 2151 struct pcic_handle *ph = (struct pcic_handle *)pch; 2152 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2153 u_int8_t power, intr; 2154 2155 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2156 2157 /* reset signal asserting... */ 2158 2159 intr = Pcic_read(ph, PCIC_INTR); 2160 intr &= ~PCIC_INTR_RESET; 2161 Pcic_write(ph, PCIC_INTR, intr); 2162 delay(2*1000); 2163 2164 /* power down the socket */ 2165 power = Pcic_read(ph, PCIC_PWRCTL); 2166 power &= ~PCIC_PWRCTL_OE; 2167 Pcic_write(ph, PCIC_PWRCTL, power); 2168 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2169 2170 /* 2171 * wait 300ms until power fails (Tpf). 2172 */ 2173 delay(300 * 1000); 2174 } 2175 2176 2177 2178 /* 2179 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2180 * 2181 * This function detects whether a card is in the slot or not. 2182 * If a card is inserted, return 1. Otherwise, return 0. 2183 */ 2184 STATIC int 2185 pccbb_pcmcia_card_detect(pch) 2186 pcmcia_chipset_handle_t pch; 2187 { 2188 struct pcic_handle *ph = (struct pcic_handle *)pch; 2189 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2190 2191 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2192 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2193 } 2194 2195 2196 2197 #if 0 2198 STATIC int 2199 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2200 bus_addr_t start, bus_size_t size, 2201 bus_size_t align, 2202 int speed, int flags, /* bus width */ 2203 bus_space_tag_t *memtp 2204 bus_space_handle_t *memhp) 2205 #endif 2206 2207 2208 /* 2209 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2210 * bus_size_t size, 2211 * struct pcmcia_mem_handle *pcmhp) 2212 * 2213 * This function only allocates memory region for pccard. This 2214 * function never maps the allcated region to pccard memory area. 2215 * 2216 * XXX: Why the argument of start address is not in? 2217 */ 2218 STATIC int 2219 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2220 pcmcia_chipset_handle_t pch; 2221 bus_size_t size; 2222 struct pcmcia_mem_handle *pcmhp; 2223 { 2224 struct pcic_handle *ph = (struct pcic_handle *)pch; 2225 bus_space_handle_t memh; 2226 bus_addr_t addr; 2227 bus_size_t sizepg; 2228 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2229 #if rbus 2230 rbus_tag_t rb; 2231 #endif 2232 2233 /* out of sc->memh, allocate as many pages as necessary */ 2234 2235 /* convert size to PCIC pages */ 2236 /* 2237 This is not enough; when the requested region is on the 2238 page boundaries, this may calculate wrong result. 2239 */ 2240 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2241 #if 0 2242 if (sizepg > PCIC_MAX_MEM_PAGES) { 2243 return 1; 2244 } 2245 #endif 2246 2247 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2248 return 1; 2249 } 2250 2251 addr = 0; /* XXX gcc -Wuninitialized */ 2252 2253 #if rbus 2254 rb = sc->sc_rbus_memt; 2255 if (rbus_space_alloc(rb, 0, sizepg*PCIC_MEM_PAGESIZE, 2256 sizepg*PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 2257 0, &addr, &memh)) { 2258 return 1; 2259 } 2260 2261 #else 2262 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2263 sizepg*PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2264 0 /* boundary */, 0 /* flags */, 2265 &addr, &memh)) { 2266 return 1; 2267 } 2268 #endif 2269 2270 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2271 addr, size, sizepg*PCIC_MEM_PAGESIZE)); 2272 2273 pcmhp->memt = sc->sc_memt; 2274 pcmhp->memh = memh; 2275 pcmhp->addr = addr; 2276 pcmhp->size = size; 2277 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2278 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2279 pcmhp->mhandle = 0; 2280 /* No offset??? Funny. */ 2281 2282 return 0; 2283 } 2284 2285 2286 2287 2288 /* 2289 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2290 * struct pcmcia_mem_handle *pcmhp) 2291 * 2292 * This function release the memory space allocated by the fuction 2293 * pccbb_pcmcia_mem_alloc(). 2294 */ 2295 STATIC void 2296 pccbb_pcmcia_mem_free(pch, pcmhp) 2297 pcmcia_chipset_handle_t pch; 2298 struct pcmcia_mem_handle *pcmhp; 2299 { 2300 #if rbus 2301 struct pcic_handle *ph = (struct pcic_handle *)pch; 2302 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2303 2304 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2305 #else 2306 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2307 #endif 2308 } 2309 2310 2311 2312 2313 /* 2314 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2315 * 2316 * This function release the memory space allocated by the fuction 2317 * pccbb_pcmcia_mem_alloc(). 2318 */ 2319 STATIC void 2320 pccbb_pcmcia_do_mem_map(ph, win) 2321 struct pcic_handle *ph; 2322 int win; 2323 { 2324 int regbase_win; 2325 bus_addr_t phys_addr; 2326 bus_addr_t phys_end; 2327 2328 #define PCIC_SMM_START_LOW 0 2329 #define PCIC_SMM_START_HIGH 1 2330 #define PCIC_SMM_STOP_LOW 2 2331 #define PCIC_SMM_STOP_HIGH 3 2332 #define PCIC_CMA_LOW 4 2333 #define PCIC_CMA_HIGH 5 2334 2335 u_int8_t start_low, start_high = 0; 2336 u_int8_t stop_low, stop_high; 2337 u_int8_t off_low, off_high; 2338 u_int8_t mem_window; 2339 int reg; 2340 2341 regbase_win = 0x10 + win*0x08; 2342 2343 phys_addr = ph->mem[win].addr; 2344 phys_end = phys_addr + ph->mem[win].size; 2345 2346 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2347 phys_addr, phys_end, ph->mem[win].offset)); 2348 2349 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2350 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2351 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2352 2353 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; /* bit 19:12 */ 2354 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) /* bit 23:20 */ 2355 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2356 /* bit 31:24, for 32-bit address */ 2357 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; /* bit 31:24 */ 2358 2359 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2360 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2361 2362 if (((struct pccbb_softc *)ph->ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2363 Pcic_write(ph, 0x40 + win, mem_window); 2364 } 2365 2366 2367 #if 0 2368 /* XXX do I want 16 bit all the time? */ 2369 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 2370 #endif 2371 2372 2373 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2374 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2375 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2376 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2377 2378 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2379 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2380 2381 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2382 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2383 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2384 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2385 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2386 2387 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2388 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2389 2390 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2391 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2392 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2393 2394 #if defined CBB_DEBUG 2395 { 2396 int r1, r2, r3, r4, r5, r6, r7 = 0; 2397 2398 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2399 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2400 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2401 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2402 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2403 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2404 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2405 r7 = Pcic_read(ph, 0x40 + win); 2406 } 2407 2408 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2409 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2410 if (((struct pccbb_softc *)(ph->ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2411 DPRINTF((" %02x",r7)); 2412 } 2413 DPRINTF(("\n")); 2414 } 2415 #endif 2416 } 2417 2418 2419 2420 2421 /* 2422 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2423 * bus_addr_t card_addr, bus_size_t size, 2424 * struct pcmcia_mem_handle *pcmhp, 2425 * bus_addr_t *offsetp, int *windowp) 2426 * 2427 * This function maps memory space allocated by the fuction 2428 * pccbb_pcmcia_mem_alloc(). 2429 */ 2430 STATIC int 2431 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2432 pcmcia_chipset_handle_t pch; 2433 int kind; 2434 bus_addr_t card_addr; 2435 bus_size_t size; 2436 struct pcmcia_mem_handle *pcmhp; 2437 bus_addr_t *offsetp; 2438 int *windowp; 2439 { 2440 struct pcic_handle *ph = (struct pcic_handle *)pch; 2441 bus_addr_t busaddr; 2442 long card_offset; 2443 int win; 2444 2445 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2446 if ((ph->memalloc & (1 << win)) == 0) { 2447 ph->memalloc |= (1 << win); 2448 break; 2449 } 2450 } 2451 2452 if (win == PCIC_MEM_WINS) { 2453 return 1; 2454 } 2455 2456 *windowp = win; 2457 2458 /* XXX this is pretty gross */ 2459 2460 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2461 panic("pccbb_pcmcia_mem_map memt is bogus"); 2462 } 2463 2464 busaddr = pcmhp->addr; 2465 2466 /* 2467 * compute the address offset to the pcmcia address space for the 2468 * pcic. this is intentionally signed. The masks and shifts below 2469 * will cause TRT to happen in the pcic registers. Deal with making 2470 * sure the address is aligned, and return the alignment offset. 2471 */ 2472 2473 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2474 card_addr -= *offsetp; 2475 2476 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2477 "%lx\n", win, (u_long)busaddr, (u_long)*offsetp, (u_long)size, 2478 (u_long)card_addr)); 2479 2480 /* 2481 * include the offset in the size, and decrement size by one, since 2482 * the hw wants start/stop 2483 */ 2484 size += *offsetp - 1; 2485 2486 card_offset = (((long) card_addr) - ((long) busaddr)); 2487 2488 ph->mem[win].addr = busaddr; 2489 ph->mem[win].size = size; 2490 ph->mem[win].offset = card_offset; 2491 ph->mem[win].kind = kind; 2492 2493 pccbb_pcmcia_do_mem_map(ph, win); 2494 2495 return 0; 2496 } 2497 2498 2499 2500 /* 2501 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2502 * int window) 2503 * 2504 * This function unmaps memory space which mapped by the fuction 2505 * pccbb_pcmcia_mem_map(). 2506 */ 2507 STATIC void 2508 pccbb_pcmcia_mem_unmap(pch, window) 2509 pcmcia_chipset_handle_t pch; 2510 int window; 2511 { 2512 struct pcic_handle *ph = (struct pcic_handle *)pch; 2513 int reg; 2514 2515 if (window >= PCIC_MEM_WINS) { 2516 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2517 } 2518 2519 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2520 reg &= ~(1 << window); 2521 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2522 2523 ph->memalloc &= ~(1 << window); 2524 } 2525 2526 2527 2528 #if defined PCCBB_PCMCIA_POLL 2529 struct pccbb_poll_str { 2530 void *arg; 2531 int (* func) __P((void *)); 2532 int level; 2533 struct pcic_handle *ph; 2534 int count; 2535 int num; 2536 }; 2537 2538 static struct pccbb_poll_str pccbb_poll[10]; 2539 static int pccbb_poll_n = 0; 2540 2541 static void pccbb_pcmcia_poll __P((void *arg)); 2542 2543 static void 2544 pccbb_pcmcia_poll(arg) 2545 void *arg; 2546 { 2547 struct pccbb_poll_str *poll = arg; 2548 struct pcic_handle *ph = poll->ph; 2549 struct pccbb_softc *sc = ph->sc; 2550 int s; 2551 u_int32_t spsr; /* socket present-state reg */ 2552 2553 timeout(pccbb_pcmcia_poll, arg, hz*2); 2554 switch (poll->level) { 2555 case IPL_NET: 2556 s = splnet(); 2557 break; 2558 case IPL_BIO: 2559 s = splbio(); 2560 break; 2561 case IPL_TTY: /* fallthrough */ 2562 default: 2563 s = spltty(); 2564 break; 2565 } 2566 2567 spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT); 2568 2569 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2570 if (!(spsr & 0x40)) /* CINT low */ 2571 #else 2572 if (1) 2573 #endif 2574 { 2575 if ((*poll->func)(poll->arg) > 0) { 2576 ++poll->count; 2577 // printf("intr: reported from poller, 0x%x\n", spsr); 2578 #if defined LEVEL2 2579 } else { 2580 printf("intr: miss! 0x%x\n", spsr); 2581 #endif 2582 } 2583 } 2584 splx(s); 2585 } 2586 #endif /* defined CB_PCMCIA_POLL */ 2587 2588 2589 2590 /* 2591 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2592 * struct pcmcia_function *pf, 2593 * int ipl, 2594 * int (*func)(void *), 2595 * void *arg); 2596 * 2597 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2598 */ 2599 STATIC void * 2600 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2601 pcmcia_chipset_handle_t pch; 2602 struct pcmcia_function *pf; 2603 int ipl; 2604 int (*func) __P((void *)); 2605 void *arg; 2606 { 2607 struct pcic_handle *ph = (struct pcic_handle *)pch; 2608 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2609 pci_intr_handle_t handle; 2610 void *ih; 2611 2612 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2613 /* what should I do? */ 2614 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2615 DPRINTF(("%s does not provide edge nor pulse interrupt\n", 2616 sc->sc_dev.dv_xname)); 2617 return NULL; 2618 } 2619 /* 2620 * XXX Noooooo! The interrupt flag must set properly!! 2621 * dumb pcmcia driver!! 2622 */ 2623 } 2624 2625 if (pci_intr_map(sc->sc_pc, sc->sc_intrtag, sc->sc_intrpin, 2626 sc->sc_intrline, &handle)) { 2627 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 2628 return NULL; 2629 } 2630 DPRINTF(("pccbb_pcmcia_intr_establish: line %d, handle %d\n", 2631 sc->sc_intrline, handle)); 2632 2633 if (NULL != (ih = pci_intr_establish(sc->sc_pc, handle, ipl, func, arg))) 2634 { 2635 u_int32_t cbctrl; 2636 2637 if ((CB_TI113X == sc->sc_chipset)) { 2638 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 2639 cbctrl |= PCI113X_CBCTRL_PCI_INTR; /* PCI functional intr req */ 2640 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 2641 } 2642 } 2643 #if defined PCCBB_PCMCIA_POLL 2644 if (pccbb_poll_n < 10) { 2645 pccbb_poll[pccbb_poll_n].arg = arg; 2646 pccbb_poll[pccbb_poll_n].func = func; 2647 pccbb_poll[pccbb_poll_n].level = ipl; 2648 pccbb_poll[pccbb_poll_n].count = 0; 2649 pccbb_poll[pccbb_poll_n].num = pccbb_poll_n; 2650 pccbb_poll[pccbb_poll_n].ph = ph; 2651 timeout(pccbb_pcmcia_poll, &pccbb_poll[pccbb_poll_n++], hz*2); 2652 printf("polling set\n"); 2653 } 2654 #endif 2655 #if defined SHOW_REGS 2656 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); 2657 #endif 2658 2659 return ih; 2660 } 2661 2662 2663 2664 2665 /* 2666 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2667 * void *ih) 2668 * 2669 * This function disables PC-Card interrupt. 2670 */ 2671 STATIC void 2672 pccbb_pcmcia_intr_disestablish(pch, ih) 2673 pcmcia_chipset_handle_t pch; 2674 void *ih; 2675 { 2676 struct pcic_handle *ph = (struct pcic_handle *)pch; 2677 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2678 2679 pci_intr_disestablish(sc->sc_pc, ih); 2680 } 2681 2682 2683 2684 2685 #if rbus 2686 /* 2687 * static int 2688 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2689 * bus_addr_t addr, bus_size_t size, 2690 * bus_addr_t mask, bus_size_t align, 2691 * int flags, bus_addr_t *addrp; 2692 * bus_space_handle_t *bshp) 2693 * 2694 * This function allocates a portion of memory or io space for 2695 * clients. This function is called from CardBus card drivers. 2696 */ 2697 static int 2698 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2699 cardbus_chipset_tag_t ct; 2700 rbus_tag_t rb; 2701 bus_addr_t addr; 2702 bus_size_t size; 2703 bus_addr_t mask; 2704 bus_size_t align; 2705 int flags; 2706 bus_addr_t *addrp; 2707 bus_space_handle_t *bshp; 2708 { 2709 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2710 2711 DPRINTF(("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", addr, size, mask, align)); 2712 2713 if (align == 0) { 2714 align = size; 2715 } 2716 2717 if (rb->rb_bt == sc->sc_memt) { 2718 if (align < 16) { 2719 return 1; 2720 } 2721 } else if (rb->rb_bt == sc->sc_iot) { 2722 if (align < 4) { 2723 return 1; 2724 } 2725 } else { 2726 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2727 rb->rb_bt)); 2728 return 1; 2729 /* XXX: panic here? */ 2730 } 2731 2732 /* XXX: hack for avoiding ISA image */ 2733 if (mask < 0x3ff) { 2734 mask = 0x3ff; 2735 addr = 0x300; 2736 } 2737 2738 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2739 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2740 return 1; 2741 } 2742 2743 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2744 2745 return 0; 2746 } 2747 2748 2749 2750 2751 2752 /* 2753 * static int 2754 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2755 * bus_space_handle_t *bshp, bus_size_t size); 2756 * 2757 * This function is called from CardBus card drivers. 2758 */ 2759 static int 2760 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2761 cardbus_chipset_tag_t ct; 2762 rbus_tag_t rb; 2763 bus_space_handle_t bsh; 2764 bus_size_t size; 2765 { 2766 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2767 bus_space_tag_t bt = rb->rb_bt; 2768 2769 pccbb_close_win(sc, bt, bsh, size); 2770 2771 if (bt == sc->sc_memt) { 2772 } else if (bt == sc->sc_iot) { 2773 } else { 2774 return 1; 2775 /* XXX: panic here? */ 2776 } 2777 2778 return rbus_space_free(rb, bsh, size, NULL); 2779 } 2780 #endif /* rbus */ 2781 2782 2783 #if rbus 2784 2785 static int 2786 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2787 struct pccbb_softc *sc; 2788 bus_space_tag_t bst; 2789 bus_addr_t addr; 2790 bus_size_t size; 2791 bus_space_handle_t bsh; 2792 int flags; 2793 { 2794 struct pccbb_win_chain **top; 2795 bus_addr_t align; 2796 2797 top = &sc->sc_iowindow; 2798 align = 0x04; 2799 if (sc->sc_memt == bst) { 2800 top = &sc->sc_memwindow; 2801 align = 0x1000; 2802 DPRINTF(("using memory window, %x %x %x\n\n", 2803 sc->sc_iot, sc->sc_memt, bst)); 2804 } 2805 2806 if (pccbb_winlist_insert(top, addr, size, bsh, flags)) { 2807 printf("winlist insert fails:\n"); 2808 } 2809 pccbb_winset(align, sc, bst); 2810 2811 return 0; 2812 } 2813 2814 2815 2816 static int 2817 pccbb_close_win(sc, bst, bsh, size) 2818 struct pccbb_softc *sc; 2819 bus_space_tag_t bst; 2820 bus_space_handle_t bsh; 2821 bus_size_t size; 2822 { 2823 struct pccbb_win_chain **top; 2824 bus_addr_t align; 2825 2826 top = &sc->sc_iowindow; 2827 align = 0x04; 2828 if (sc->sc_memt == bst) { 2829 top = &sc->sc_memwindow; 2830 align = 0x1000; 2831 } 2832 2833 if (pccbb_winlist_delete(top, bsh, size)) { 2834 printf("winlist delete fails:\n"); 2835 } 2836 pccbb_winset(align, sc, bst); 2837 2838 return 0; 2839 } 2840 2841 2842 static int 2843 pccbb_winlist_insert(top, start, size, bsh, flags) 2844 struct pccbb_win_chain **top; 2845 bus_addr_t start; 2846 bus_size_t size; 2847 bus_space_handle_t bsh; 2848 int flags; 2849 { 2850 struct pccbb_win_chain *chainp = *top; 2851 struct pccbb_win_chain *before = *top; 2852 struct pccbb_win_chain *elem; 2853 2854 if (*top == NULL) { 2855 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2856 return 1; /* fail */ 2857 } 2858 2859 elem->wc_start = start; 2860 elem->wc_end = start + size - 1; 2861 elem->wc_handle = bsh; 2862 elem->wc_flags = flags; 2863 2864 *top = elem; 2865 elem->wc_next = NULL; 2866 return 0; 2867 } 2868 2869 for(; chainp && chainp->wc_start <= start; chainp = chainp->wc_next) { 2870 before = chainp; 2871 } 2872 2873 if (chainp != NULL) { 2874 if (chainp->wc_start < start + size) { 2875 printf("fatal! 0x%lx 0x%lx\n", chainp->wc_start, start+size); 2876 return 1; 2877 } 2878 } 2879 if ((before != *top) && (before->wc_end >= start)) { 2880 printf("fatal!! 0x%lx 0x%lx\n", before->wc_end, start); 2881 return 1; 2882 } 2883 2884 if (NULL == (elem = (struct pccbb_win_chain *)malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, M_NOWAIT))) { 2885 return 1; /* fail */ 2886 } 2887 2888 elem->wc_start = start; 2889 elem->wc_end = start + size - 1; 2890 elem->wc_handle = bsh; 2891 elem->wc_flags = flags; 2892 2893 elem->wc_next = chainp; 2894 if (chainp == *top) { 2895 *top = elem; 2896 } else { 2897 before->wc_next = elem; 2898 } 2899 return 0; 2900 } 2901 2902 2903 2904 2905 static int 2906 pccbb_winlist_delete(top, bsh, size) 2907 struct pccbb_win_chain **top; 2908 bus_space_handle_t bsh; 2909 bus_size_t size; 2910 { 2911 struct pccbb_win_chain *chainp = *top; 2912 struct pccbb_win_chain **before = top; 2913 2914 for (; chainp && chainp->wc_handle != bsh; chainp = chainp->wc_next) { 2915 before = &chainp->wc_next; 2916 } 2917 2918 if (chainp == NULL) { 2919 return 1; /* fail: no candidate to remove */ 2920 } 2921 2922 if (chainp->wc_end - chainp->wc_start != size - 1) { 2923 printf("fatal!!! 0x%lx\n", chainp->wc_start); 2924 return 1; /* fail: no candidate to remove */ 2925 } 2926 2927 *before = chainp->wc_next; 2928 free(chainp, M_DEVBUF); 2929 2930 return 0; 2931 } 2932 2933 2934 2935 static void 2936 pccbb_winset(align, sc, bst) 2937 bus_addr_t align; 2938 struct pccbb_softc *sc; 2939 bus_space_tag_t bst; 2940 { 2941 pci_chipset_tag_t pc; 2942 pcitag_t tag; 2943 bus_addr_t mask = ~(align - 1); 2944 struct { 2945 cardbusreg_t win_start; 2946 cardbusreg_t win_limit; 2947 int win_flags; 2948 } win[2]; 2949 struct pccbb_win_chain *chainp; 2950 int offs; 2951 2952 win[0].win_start = 0xffffffff; 2953 win[0].win_limit = 0; 2954 win[1].win_start = 0xffffffff; 2955 win[1].win_limit = 0; 2956 2957 chainp = sc->sc_iowindow; 2958 offs = 0x2c; 2959 if (sc->sc_memt == bst) { 2960 chainp = sc->sc_memwindow; 2961 offs = 0x1c; 2962 } 2963 2964 if (chainp) { 2965 win[0].win_start = chainp->wc_start & mask; 2966 win[0].win_limit = chainp->wc_end & mask; 2967 win[0].win_flags = chainp->wc_flags; 2968 chainp = chainp->wc_next; 2969 } 2970 2971 for(; chainp; chainp = chainp->wc_next) { 2972 if (win[1].win_start == 0xffffffff) { 2973 /* window 1 is not used */ 2974 if ((win[0].win_flags == chainp->wc_flags) && 2975 (win[0].win_limit + align >= (chainp->wc_start & mask))) { 2976 /* concatinate */ 2977 win[0].win_limit = chainp->wc_end & mask; 2978 } else { 2979 /* make new window */ 2980 win[1].win_start = chainp->wc_start & mask; 2981 win[1].win_limit = chainp->wc_end & mask; 2982 win[1].win_flags = chainp->wc_flags; 2983 } 2984 continue; 2985 } 2986 2987 /* Both windows are engagad. */ 2988 if (win[0].win_flags == win[1].win_flags) { 2989 /* same flags */ 2990 if (win[0].win_flags == chainp->wc_flags) { 2991 2992 win[1].win_limit = chainp->wc_end & mask; 2993 2994 if (win[1].win_start - (win[0].win_limit + align) 2995 < (chainp->wc_start & mask) - (win[1].win_limit + align)) { 2996 win[0].win_limit = win[1].win_limit; 2997 win[1].win_start = chainp->wc_start & mask; 2998 } 2999 } else { 3000 /* different flags */ 3001 3002 /* concatinate win0 and win1 */ 3003 win[0].win_limit = win[1].win_limit; 3004 /* allocate win[1] to new space */ 3005 win[1].win_start = chainp->wc_start & mask; 3006 win[1].win_limit = chainp->wc_end & mask; 3007 win[1].win_flags = chainp->wc_flags; 3008 } 3009 } else { 3010 /* the flags of win[0] and win[1] is different */ 3011 if (win[0].win_flags == chainp->wc_flags) { 3012 win[0].win_limit = chainp->wc_end & mask; 3013 } else { 3014 win[1].win_limit = chainp->wc_end & mask; 3015 } 3016 } 3017 } 3018 3019 pc = sc->sc_pc; 3020 tag = sc->sc_tag; 3021 pci_conf_write(pc, tag, offs, win[0].win_start); 3022 pci_conf_write(pc, tag, offs+4, win[0].win_limit); 3023 pci_conf_write(pc, tag, offs+8, win[1].win_start); 3024 pci_conf_write(pc, tag, offs+12, win[1].win_limit); 3025 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3026 pci_conf_read(pc, tag, offs), 3027 pci_conf_read(pc, tag, offs+4) + align, 3028 pci_conf_read(pc, tag, offs+8), 3029 pci_conf_read(pc, tag, offs+12) + align)); 3030 3031 if (bst == sc->sc_memt) { 3032 if (win[0].win_start & PCCBB_MEM_CACHABLE) { 3033 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3034 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3035 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3036 } 3037 if (win[1].win_start & PCCBB_MEM_CACHABLE) { 3038 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3039 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3040 pci_conf_write(pc,tag, PCI_BCR_INTR, bcr); 3041 } 3042 } 3043 } 3044 3045 #endif /* rbus */ 3046
Indexes created Sun Sep 28 16:09:52 GMT 2025