pccbb.c revision 1.80
1 /* $NetBSD: pccbb.c,v 1.80 2002/10/01 09:09:16 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.80 2002/10/01 09:09:16 haya Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, NULL, NULL) 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 330 /* Ricoh chips */ 331 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 332 PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 344 /* Toshiba products */ 345 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 346 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 348 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 350 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 354 /* Cirrus Logic products */ 355 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 356 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 360 /* sentinel, or Generic chip */ 361 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 362 }; 363 364 static int 365 cb_chipset(pci_id, flagp) 366 u_int32_t pci_id; 367 int *flagp; 368 { 369 const struct yenta_chipinfo *yc; 370 371 /* Loop over except the last default entry. */ 372 for (yc = yc_chipsets; yc < yc_chipsets + 373 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 374 if (pci_id == yc->yc_id) 375 break; 376 377 if (flagp != NULL) 378 *flagp = yc->yc_flags; 379 380 return (yc->yc_chiptype); 381 } 382 383 static void 384 pccbb_shutdown(void *arg) 385 { 386 struct pccbb_softc *sc = arg; 387 pcireg_t command; 388 389 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 390 391 /* 392 * turn off power 393 * 394 * XXX - do not turn off power if chipset is TI 113X because 395 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 396 */ 397 if (sc->sc_chipset != CB_TI113X) { 398 pccbb_power((cardbus_chipset_tag_t)sc, 399 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 400 } 401 402 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 403 0); 404 405 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 406 407 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 408 PCI_COMMAND_MASTER_ENABLE); 409 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 410 411 } 412 413 void 414 pccbbattach(parent, self, aux) 415 struct device *parent; 416 struct device *self; 417 void *aux; 418 { 419 struct pccbb_softc *sc = (void *)self; 420 struct pci_attach_args *pa = aux; 421 pci_chipset_tag_t pc = pa->pa_pc; 422 pcireg_t busreg, reg, sock_base; 423 bus_addr_t sockbase; 424 char devinfo[256]; 425 int flags; 426 int pwrmgt_offs; 427 428 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 429 430 pci_devinfo(pa->pa_id, 0, 0, devinfo); 431 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 432 #ifdef CBB_DEBUG 433 printf(" (chipflags %x)", flags); 434 #endif 435 printf("\n"); 436 437 TAILQ_INIT(&sc->sc_memwindow); 438 TAILQ_INIT(&sc->sc_iowindow); 439 440 #if rbus 441 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 442 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 443 444 #if 0 445 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 446 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 447 #endif 448 #endif /* rbus */ 449 450 sc->sc_base_memh = 0; 451 452 /* power management: set D0 state */ 453 sc->sc_pwrmgt_offs = 0; 454 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 455 &pwrmgt_offs, 0)) { 456 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + 4); 457 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 458 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 459 reg &= ~PCI_PMCSR_STATE_MASK; 460 reg |= PCI_PMCSR_STATE_D0; 461 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 462 pci_conf_write(pc, pa->pa_tag, pwrmgt_offs + 4, reg); 463 } 464 465 sc->sc_pwrmgt_offs = pwrmgt_offs; 466 } 467 468 /* 469 * MAP socket registers and ExCA registers on memory-space 470 * When no valid address is set on socket base registers (on pci 471 * config space), get it not polite way. 472 */ 473 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 474 475 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 476 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 477 /* The address must be valid. */ 478 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 479 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 480 printf("%s: can't map socket base address 0x%x\n", 481 sc->sc_dev.dv_xname, sock_base); 482 /* 483 * I think it's funny: socket base registers must be 484 * mapped on memory space, but ... 485 */ 486 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 487 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 488 NULL)) { 489 printf("%s: can't map socket base address" 490 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 491 (unsigned long)sockbase); 492 /* give up... allocate reg space via rbus. */ 493 sc->sc_base_memh = 0; 494 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 495 } 496 } else { 497 DPRINTF(("%s: socket base address 0x%lx\n", 498 sc->sc_dev.dv_xname, sockbase)); 499 } 500 } 501 502 sc->sc_mem_start = 0; /* XXX */ 503 sc->sc_mem_end = 0xffffffff; /* XXX */ 504 505 /* 506 * When interrupt isn't routed correctly, give up probing cbb and do 507 * not kill pcic-compatible port. 508 */ 509 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 510 printf("%s: NOT USED because of unconfigured interrupt\n", 511 sc->sc_dev.dv_xname); 512 return; 513 } 514 515 /* 516 * When bus number isn't set correctly, give up using 32-bit CardBus 517 * mode. 518 */ 519 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 520 #if notyet 521 if (((busreg >> 8) & 0xff) == 0) { 522 printf("%s: CardBus support disabled because of unconfigured bus number\n", 523 sc->sc_dev.dv_xname); 524 flags |= PCCBB_PCMCIA_16BITONLY; 525 } 526 #endif 527 528 /* pccbb_machdep.c end */ 529 530 #if defined CBB_DEBUG 531 { 532 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 533 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 534 intrname[pa->pa_intrpin], pa->pa_intrline); 535 } 536 #endif 537 538 /* setup softc */ 539 sc->sc_pc = pc; 540 sc->sc_iot = pa->pa_iot; 541 sc->sc_memt = pa->pa_memt; 542 sc->sc_dmat = pa->pa_dmat; 543 sc->sc_tag = pa->pa_tag; 544 sc->sc_function = pa->pa_function; 545 sc->sc_sockbase = sock_base; 546 sc->sc_busnum = busreg; 547 548 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 549 550 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 551 552 shutdownhook_establish(pccbb_shutdown, sc); 553 554 /* Disable legacy register mapping. */ 555 switch (sc->sc_chipset) { 556 case CB_RX5C46X: /* fallthrough */ 557 #if 0 558 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 559 case CB_RX5C47X: 560 #endif 561 /* 562 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 563 * cannot be disabled by substituting 0 into PCI_LEGACY 564 * register. Ricoh CardBus bridges have special bits on Bridge 565 * control reg (addr 0x3e on PCI config space). 566 */ 567 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 568 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 569 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 570 break; 571 572 default: 573 /* XXX I don't know proper way to kill legacy I/O. */ 574 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 575 break; 576 } 577 578 config_defer(self, pccbb_pci_callback); 579 } 580 581 582 583 584 /* 585 * static void pccbb_pci_callback(struct device *self) 586 * 587 * The actual attach routine: get memory space for YENTA register 588 * space, setup YENTA register and route interrupt. 589 * 590 * This function should be deferred because this device may obtain 591 * memory space dynamically. This function must avoid obtaining 592 * memory area which has already kept for another device. 593 */ 594 static void 595 pccbb_pci_callback(self) 596 struct device *self; 597 { 598 struct pccbb_softc *sc = (void *)self; 599 pci_chipset_tag_t pc = sc->sc_pc; 600 pci_intr_handle_t ih; 601 const char *intrstr = NULL; 602 bus_addr_t sockbase; 603 struct cbslot_attach_args cba; 604 struct pcmciabus_attach_args paa; 605 struct cardslot_attach_args caa; 606 struct cardslot_softc *csc; 607 608 if (0 == sc->sc_base_memh) { 609 /* The socket registers aren't mapped correctly. */ 610 #if rbus 611 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 612 (sc->sc_chipset == CB_RX5C47X 613 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 614 0, &sockbase, &sc->sc_base_memh)) { 615 return; 616 } 617 sc->sc_base_memt = sc->sc_memt; 618 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 619 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 620 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 621 PCI_SOCKBASE))); 622 #else 623 sc->sc_base_memt = sc->sc_memt; 624 #if !defined CBB_PCI_BASE 625 #define CBB_PCI_BASE 0x20000000 626 #endif 627 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 628 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 629 /* cannot allocate memory space */ 630 return; 631 } 632 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 633 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 634 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 635 sc->sc_tag, PCI_SOCKBASE))); 636 sc->sc_sockbase = sockbase; 637 #endif 638 } 639 640 /* bus bridge initialization */ 641 pccbb_chipinit(sc); 642 643 /* clear data structure for child device interrupt handlers */ 644 LIST_INIT(&sc->sc_pil); 645 sc->sc_pil_intr_enable = 1; 646 647 /* Map and establish the interrupt. */ 648 if (pci_intr_map(&sc->sc_pa, &ih)) { 649 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 650 return; 651 } 652 intrstr = pci_intr_string(pc, ih); 653 654 /* 655 * XXX pccbbintr should be called under the priority lower 656 * than any other hard interrputs. 657 */ 658 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 659 660 if (sc->sc_ih == NULL) { 661 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 662 if (intrstr != NULL) { 663 printf(" at %s", intrstr); 664 } 665 printf("\n"); 666 return; 667 } 668 669 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 670 powerhook_establish(pccbb_powerhook, sc); 671 672 { 673 u_int32_t sockstat; 674 675 sockstat = bus_space_read_4(sc->sc_base_memt, 676 sc->sc_base_memh, CB_SOCKET_STAT); 677 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 678 sc->sc_flags |= CBB_CARDEXIST; 679 } 680 } 681 682 /* 683 * attach cardbus 684 */ 685 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 686 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 687 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 688 689 /* initialize cbslot_attach */ 690 cba.cba_busname = "cardbus"; 691 cba.cba_iot = sc->sc_iot; 692 cba.cba_memt = sc->sc_memt; 693 cba.cba_dmat = sc->sc_dmat; 694 cba.cba_bus = (busreg >> 8) & 0x0ff; 695 cba.cba_cc = (void *)sc; 696 cba.cba_cf = &pccbb_funcs; 697 cba.cba_intrline = sc->sc_pa.pa_intrline; 698 699 #if rbus 700 cba.cba_rbus_iot = sc->sc_rbus_iot; 701 cba.cba_rbus_memt = sc->sc_rbus_memt; 702 #endif 703 704 cba.cba_cacheline = PCI_CACHELINE(bhlc); 705 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 706 707 if (bootverbose) { 708 printf("%s: cacheline 0x%x lattimer 0x%x\n", 709 sc->sc_dev.dv_xname, cba.cba_cacheline, 710 cba.cba_lattimer); 711 printf("%s: bhlc 0x%x lscp 0x%x\n", 712 sc->sc_dev.dv_xname, bhlc, busreg); 713 } 714 #if defined SHOW_REGS 715 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 716 sc->sc_base_memh); 717 #endif 718 } 719 720 pccbb_pcmcia_attach_setup(sc, &paa); 721 caa.caa_cb_attach = NULL; 722 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 723 caa.caa_cb_attach = &cba; 724 } 725 caa.caa_16_attach = &paa; 726 caa.caa_ph = &sc->sc_pcmcia_h; 727 728 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 729 DPRINTF(("pccbbattach: found cardslot\n")); 730 sc->sc_csc = csc; 731 } 732 733 return; 734 } 735 736 737 738 739 740 /* 741 * static void pccbb_chipinit(struct pccbb_softc *sc) 742 * 743 * This function initialize YENTA chip registers listed below: 744 * 1) PCI command reg, 745 * 2) PCI and CardBus latency timer, 746 * 3) route PCI interrupt, 747 * 4) close all memory and io windows. 748 * 5) turn off bus power. 749 * 6) card detect interrupt on. 750 * 7) clear interrupt 751 */ 752 static void 753 pccbb_chipinit(sc) 754 struct pccbb_softc *sc; 755 { 756 pci_chipset_tag_t pc = sc->sc_pc; 757 pcitag_t tag = sc->sc_tag; 758 bus_space_tag_t bmt = sc->sc_base_memt; 759 bus_space_handle_t bmh = sc->sc_base_memh; 760 pcireg_t reg; 761 762 /* 763 * Set PCI command reg. 764 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 765 */ 766 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 767 /* I believe it is harmless. */ 768 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 769 PCI_COMMAND_MASTER_ENABLE); 770 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 771 772 /* 773 * Set CardBus latency timer. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 776 if (PCI_CB_LATENCY(reg) < 0x20) { 777 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 778 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 779 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 780 } 781 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 782 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 783 784 /* 785 * Set PCI latency timer. 786 */ 787 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 788 if (PCI_LATTIMER(reg) < 0x10) { 789 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 790 reg |= (0x10 << PCI_LATTIMER_SHIFT); 791 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 792 } 793 DPRINTF(("PCI latency timer 0x%x (%x)\n", 794 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 795 796 797 /* Route functional interrupts to PCI. */ 798 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 799 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 800 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 801 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 802 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 803 804 switch (sc->sc_chipset) { 805 case CB_TI113X: 806 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 807 /* This bit is shared, but may read as 0 on some chips, so set 808 it explicitly on both functions. */ 809 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 810 /* CSC intr enable */ 811 reg |= PCI113X_CBCTRL_PCI_CSC; 812 /* functional intr prohibit | prohibit ISA routing */ 813 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 814 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 815 break; 816 817 case CB_TI12XX: 818 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 819 reg |= PCI12XX_SYSCTRL_VCCPROT; 820 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 821 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 822 reg |= PCI12XX_CBCTRL_CSC; 823 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 824 break; 825 826 case CB_TOPIC95B: 827 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 828 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 829 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 830 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 831 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 832 sc->sc_dev.dv_xname, reg)); 833 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 834 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 835 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 836 DPRINTF(("0x%x\n", reg)); 837 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 838 break; 839 840 case CB_TOPIC97: 841 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 842 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 843 sc->sc_dev.dv_xname, reg)); 844 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 845 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 846 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 847 reg |= TOPIC97_SLOT_CTRL_PCIINT; 848 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 849 DPRINTF(("0x%x\n", reg)); 850 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 851 /* make sure to assert LV card support bits */ 852 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 853 0x800 + 0x3e, 854 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 855 0x800 + 0x3e) | 0x03); 856 break; 857 } 858 859 /* Close all memory and I/O windows. */ 860 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 861 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 862 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 863 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 864 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 865 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 866 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 867 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 868 869 /* reset 16-bit pcmcia bus */ 870 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 871 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 872 873 /* turn off power */ 874 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 875 876 /* CSC Interrupt: Card detect interrupt on */ 877 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 878 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 879 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 880 /* reset interrupt */ 881 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 882 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 883 } 884 885 886 887 888 /* 889 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 890 * struct pcmciabus_attach_args *paa) 891 * 892 * This function attaches 16-bit PCcard bus. 893 */ 894 STATIC void 895 pccbb_pcmcia_attach_setup(sc, paa) 896 struct pccbb_softc *sc; 897 struct pcmciabus_attach_args *paa; 898 { 899 struct pcic_handle *ph = &sc->sc_pcmcia_h; 900 #if rbus 901 rbus_tag_t rb; 902 #endif 903 904 /* initialize pcmcia part in pccbb_softc */ 905 ph->ph_parent = (struct device *)sc; 906 ph->sock = sc->sc_function; 907 ph->flags = 0; 908 ph->shutdown = 0; 909 ph->ih_irq = sc->sc_pa.pa_intrline; 910 ph->ph_bus_t = sc->sc_base_memt; 911 ph->ph_bus_h = sc->sc_base_memh; 912 ph->ph_read = pccbb_pcmcia_read; 913 ph->ph_write = pccbb_pcmcia_write; 914 sc->sc_pct = &pccbb_pcmcia_funcs; 915 916 /* 917 * We need to do a few things here: 918 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 919 * setting the IRQ numbers to 0. 920 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 921 * routing of CSC interrupts (e.g. card removal) to PCI while in 922 * PCMCIA mode. We just leave this set all the time. 923 * 3) Enable card insertion/removal interrupts in case the chip also 924 * needs that while in PCMCIA mode. 925 * 4) Clear any pending CSC interrupt. 926 */ 927 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 928 if (sc->sc_chipset == CB_TI113X) { 929 Pcic_write(ph, PCIC_CSC_INTR, 0); 930 } else { 931 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 932 Pcic_read(ph, PCIC_CSC); 933 } 934 935 /* initialize pcmcia bus attachment */ 936 paa->paa_busname = "pcmcia"; 937 paa->pct = sc->sc_pct; 938 paa->pch = ph; 939 paa->iobase = 0; /* I don't use them */ 940 paa->iosize = 0; 941 #if rbus 942 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 943 paa->iobase = rb->rb_start + rb->rb_offset; 944 paa->iosize = rb->rb_end - rb->rb_start; 945 #endif 946 947 return; 948 } 949 950 #if 0 951 STATIC void 952 pccbb_pcmcia_attach_card(ph) 953 struct pcic_handle *ph; 954 { 955 if (ph->flags & PCIC_FLAG_CARDP) { 956 panic("pccbb_pcmcia_attach_card: already attached"); 957 } 958 959 /* call the MI attach function */ 960 pcmcia_card_attach(ph->pcmcia); 961 962 ph->flags |= PCIC_FLAG_CARDP; 963 } 964 965 STATIC void 966 pccbb_pcmcia_detach_card(ph, flags) 967 struct pcic_handle *ph; 968 int flags; 969 { 970 if (!(ph->flags & PCIC_FLAG_CARDP)) { 971 panic("pccbb_pcmcia_detach_card: already detached"); 972 } 973 974 ph->flags &= ~PCIC_FLAG_CARDP; 975 976 /* call the MI detach function */ 977 pcmcia_card_detach(ph->pcmcia, flags); 978 } 979 #endif 980 981 /* 982 * int pccbbintr(arg) 983 * void *arg; 984 * This routine handles the interrupt from Yenta PCI-CardBus bridge 985 * itself. 986 */ 987 int 988 pccbbintr(arg) 989 void *arg; 990 { 991 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 992 u_int32_t sockevent, sockstate; 993 bus_space_tag_t memt = sc->sc_base_memt; 994 bus_space_handle_t memh = sc->sc_base_memh; 995 struct pcic_handle *ph = &sc->sc_pcmcia_h; 996 997 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 998 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 999 Pcic_read(ph, PCIC_CSC); 1000 1001 if (sockevent == 0) { 1002 /* This intr is not for me: it may be for my child devices. */ 1003 if (sc->sc_pil_intr_enable) { 1004 return pccbbintr_function(sc); 1005 } else { 1006 return 0; 1007 } 1008 } 1009 1010 if (sockevent & CB_SOCKET_EVENT_CD) { 1011 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1012 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 1013 /* A card should be removed. */ 1014 if (sc->sc_flags & CBB_CARDEXIST) { 1015 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1016 sockevent)); 1017 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1018 sc->sc_flags &= ~CBB_CARDEXIST; 1019 if (sc->sc_csc->sc_status & 1020 CARDSLOT_STATUS_CARD_16) { 1021 #if 0 1022 struct pcic_handle *ph = 1023 &sc->sc_pcmcia_h; 1024 1025 pcmcia_card_deactivate(ph->pcmcia); 1026 pccbb_pcmcia_socket_disable(ph); 1027 pccbb_pcmcia_detach_card(ph, 1028 DETACH_FORCE); 1029 #endif 1030 cardslot_event_throw(sc->sc_csc, 1031 CARDSLOT_EVENT_REMOVAL_16); 1032 } else if (sc->sc_csc->sc_status & 1033 CARDSLOT_STATUS_CARD_CB) { 1034 /* Cardbus intr removed */ 1035 cardslot_event_throw(sc->sc_csc, 1036 CARDSLOT_EVENT_REMOVAL_CB); 1037 } 1038 } else if (sc->sc_flags & CBB_INSERTING) { 1039 sc->sc_flags &= ~CBB_INSERTING; 1040 callout_stop(&sc->sc_insert_ch); 1041 } 1042 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1043 /* 1044 * The pccbbintr may called from powerdown hook when 1045 * the system resumed, to detect the card 1046 * insertion/removal during suspension. 1047 */ 1048 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1049 if (sc->sc_flags & CBB_INSERTING) { 1050 callout_stop(&sc->sc_insert_ch); 1051 } 1052 callout_reset(&sc->sc_insert_ch, hz / 5, 1053 pci113x_insert, sc); 1054 sc->sc_flags |= CBB_INSERTING; 1055 } 1056 } 1057 1058 return (1); 1059 } 1060 1061 /* 1062 * static int pccbbintr_function(struct pccbb_softc *sc) 1063 * 1064 * This function calls each interrupt handler registered at the 1065 * bridge. The interrupt handlers are called in registered order. 1066 */ 1067 static int 1068 pccbbintr_function(sc) 1069 struct pccbb_softc *sc; 1070 { 1071 int retval = 0, val; 1072 struct pccbb_intrhand_list *pil; 1073 int s, splchanged; 1074 1075 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1076 pil = LIST_NEXT(pil, pil_next)) { 1077 /* 1078 * XXX priority change. gross. I use if-else 1079 * sentense instead of switch-case sentense because of 1080 * avoiding duplicate case value error. More than one 1081 * IPL_XXX use same value. It depends on 1082 * implimentation. 1083 */ 1084 splchanged = 1; 1085 if (pil->pil_level == IPL_SERIAL) { 1086 s = splserial(); 1087 } else if (pil->pil_level == IPL_HIGH) { 1088 s = splhigh(); 1089 } else if (pil->pil_level == IPL_CLOCK) { 1090 s = splclock(); 1091 } else if (pil->pil_level == IPL_AUDIO) { 1092 s = splaudio(); 1093 } else if (pil->pil_level == IPL_IMP) { 1094 s = splvm(); /* XXX */ 1095 } else if (pil->pil_level == IPL_TTY) { 1096 s = spltty(); 1097 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1098 s = splsoftserial(); 1099 } else if (pil->pil_level == IPL_NET) { 1100 s = splnet(); 1101 } else { 1102 splchanged = 0; 1103 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1104 } 1105 1106 val = (*pil->pil_func)(pil->pil_arg); 1107 1108 if (splchanged != 0) { 1109 splx(s); 1110 } 1111 1112 retval = retval == 1 ? 1 : 1113 retval == 0 ? val : val != 0 ? val : retval; 1114 } 1115 1116 return retval; 1117 } 1118 1119 static void 1120 pci113x_insert(arg) 1121 void *arg; 1122 { 1123 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1124 u_int32_t sockevent, sockstate; 1125 1126 if (!(sc->sc_flags & CBB_INSERTING)) { 1127 /* We add a card only under inserting state. */ 1128 return; 1129 } 1130 sc->sc_flags &= ~CBB_INSERTING; 1131 1132 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1133 CB_SOCKET_EVENT); 1134 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1135 CB_SOCKET_STAT); 1136 1137 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1138 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1139 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1140 sc->sc_flags |= CBB_CARDEXIST; 1141 /* call pccard interrupt handler here */ 1142 if (sockstate & CB_SOCKET_STAT_16BIT) { 1143 /* 16-bit card found */ 1144 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1145 cardslot_event_throw(sc->sc_csc, 1146 CARDSLOT_EVENT_INSERTION_16); 1147 } else if (sockstate & CB_SOCKET_STAT_CB) { 1148 /* cardbus card found */ 1149 /* cardbus_attach_card(sc->sc_csc); */ 1150 cardslot_event_throw(sc->sc_csc, 1151 CARDSLOT_EVENT_INSERTION_CB); 1152 } else { 1153 /* who are you? */ 1154 } 1155 } else { 1156 callout_reset(&sc->sc_insert_ch, hz / 10, 1157 pci113x_insert, sc); 1158 } 1159 } 1160 1161 #define PCCBB_PCMCIA_OFFSET 0x800 1162 static u_int8_t 1163 pccbb_pcmcia_read(ph, reg) 1164 struct pcic_handle *ph; 1165 int reg; 1166 { 1167 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1168 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1169 1170 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1171 PCCBB_PCMCIA_OFFSET + reg); 1172 } 1173 1174 static void 1175 pccbb_pcmcia_write(ph, reg, val) 1176 struct pcic_handle *ph; 1177 int reg; 1178 u_int8_t val; 1179 { 1180 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1181 val); 1182 1183 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1184 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1185 } 1186 1187 /* 1188 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1189 */ 1190 STATIC int 1191 pccbb_ctrl(ct, command) 1192 cardbus_chipset_tag_t ct; 1193 int command; 1194 { 1195 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1196 1197 switch (command) { 1198 case CARDBUS_CD: 1199 if (2 == pccbb_detect_card(sc)) { 1200 int retval = 0; 1201 int status = cb_detect_voltage(sc); 1202 if (PCCARD_VCC_5V & status) { 1203 retval |= CARDBUS_5V_CARD; 1204 } 1205 if (PCCARD_VCC_3V & status) { 1206 retval |= CARDBUS_3V_CARD; 1207 } 1208 if (PCCARD_VCC_XV & status) { 1209 retval |= CARDBUS_XV_CARD; 1210 } 1211 if (PCCARD_VCC_YV & status) { 1212 retval |= CARDBUS_YV_CARD; 1213 } 1214 return retval; 1215 } else { 1216 return 0; 1217 } 1218 break; 1219 case CARDBUS_RESET: 1220 return cb_reset(sc); 1221 break; 1222 case CARDBUS_IO_ENABLE: /* fallthrough */ 1223 case CARDBUS_IO_DISABLE: /* fallthrough */ 1224 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1225 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1226 case CARDBUS_BM_ENABLE: /* fallthrough */ 1227 case CARDBUS_BM_DISABLE: /* fallthrough */ 1228 /* XXX: I think we don't need to call this function below. */ 1229 return pccbb_cardenable(sc, command); 1230 break; 1231 } 1232 1233 return 0; 1234 } 1235 1236 /* 1237 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1238 * This function returns true when it succeeds and returns false when 1239 * it fails. 1240 */ 1241 STATIC int 1242 pccbb_power(ct, command) 1243 cardbus_chipset_tag_t ct; 1244 int command; 1245 { 1246 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1247 1248 u_int32_t status, sock_ctrl, reg_ctrl; 1249 bus_space_tag_t memt = sc->sc_base_memt; 1250 bus_space_handle_t memh = sc->sc_base_memh; 1251 1252 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1253 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1254 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1258 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1259 "UNKNOWN", 1260 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1261 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1263 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1264 "UNKNOWN", command)); 1265 1266 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1267 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1268 1269 switch (command & CARDBUS_VCCMASK) { 1270 case CARDBUS_VCC_UC: 1271 break; 1272 case CARDBUS_VCC_5V: 1273 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1274 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1275 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1276 } else { 1277 printf("%s: BAD voltage request: no 5 V card\n", 1278 sc->sc_dev.dv_xname); 1279 } 1280 break; 1281 case CARDBUS_VCC_3V: 1282 if (CB_SOCKET_STAT_3VCARD & status) { 1283 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1284 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1285 } else { 1286 printf("%s: BAD voltage request: no 3.3 V card\n", 1287 sc->sc_dev.dv_xname); 1288 } 1289 break; 1290 case CARDBUS_VCC_0V: 1291 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1292 break; 1293 default: 1294 return 0; /* power NEVER changed */ 1295 break; 1296 } 1297 1298 switch (command & CARDBUS_VPPMASK) { 1299 case CARDBUS_VPP_UC: 1300 break; 1301 case CARDBUS_VPP_0V: 1302 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1303 break; 1304 case CARDBUS_VPP_VCC: 1305 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1306 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1307 break; 1308 case CARDBUS_VPP_12V: 1309 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1310 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1311 break; 1312 } 1313 1314 #if 0 1315 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1316 #endif 1317 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1318 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1319 1320 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1321 printf 1322 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1323 sc->sc_dev.dv_xname, sock_ctrl, status); 1324 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1325 (command & CARDBUS_VCCMASK) == 1326 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1327 CARDBUS_VCCMASK) == 1328 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1329 CARDBUS_VCCMASK) == 1330 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1331 CARDBUS_VCCMASK) == 1332 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1333 CARDBUS_VCCMASK) == 1334 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1335 CARDBUS_VCCMASK) == 1336 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1337 (command & CARDBUS_VPPMASK) == 1338 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1339 CARDBUS_VPPMASK) == 1340 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1341 CARDBUS_VPPMASK) == 1342 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1343 CARDBUS_VPPMASK) == 1344 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1345 #if 0 1346 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1347 u_int32_t force = 1348 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1349 /* Reset Bad Vcc request */ 1350 force &= ~CB_SOCKET_FORCE_BADVCC; 1351 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1352 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1353 CB_SOCKET_STAT)); 1354 return 1; 1355 } 1356 #endif 1357 return 0; 1358 } 1359 1360 if (sc->sc_chipset == CB_TOPIC97) { 1361 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1362 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1363 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1364 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1365 else 1366 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1367 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1368 } 1369 1370 /* 1371 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1372 * time is 20 ms, some PC-Card bridge requires longer duration. 1373 */ 1374 #if 0 /* XXX called on interrupt context */ 1375 DELAY_MS(300, sc); 1376 #else 1377 delay(300 * 1000); 1378 #endif 1379 1380 return 1; /* power changed correctly */ 1381 } 1382 1383 #if defined CB_PCMCIA_POLL 1384 struct cb_poll_str { 1385 void *arg; 1386 int (*func) __P((void *)); 1387 int level; 1388 pccard_chipset_tag_t ct; 1389 int count; 1390 struct callout poll_ch; 1391 }; 1392 1393 static struct cb_poll_str cb_poll[10]; 1394 static int cb_poll_n = 0; 1395 1396 static void cb_pcmcia_poll __P((void *arg)); 1397 1398 static void 1399 cb_pcmcia_poll(arg) 1400 void *arg; 1401 { 1402 struct cb_poll_str *poll = arg; 1403 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1404 struct pccbb_softc *sc = psc->cpc_parent; 1405 int s; 1406 u_int32_t spsr; /* socket present-state reg */ 1407 1408 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1409 switch (poll->level) { 1410 case IPL_NET: 1411 s = splnet(); 1412 break; 1413 case IPL_BIO: 1414 s = splbio(); 1415 break; 1416 case IPL_TTY: /* fallthrough */ 1417 default: 1418 s = spltty(); 1419 break; 1420 } 1421 1422 spsr = 1423 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1424 CB_SOCKET_STAT); 1425 1426 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1427 if (!(spsr & 0x40)) { /* CINT low */ 1428 #else 1429 if (1) { 1430 #endif 1431 if ((*poll->func) (poll->arg) == 1) { 1432 ++poll->count; 1433 printf("intr: reported from poller, 0x%x\n", spsr); 1434 #if defined LEVEL2 1435 } else { 1436 printf("intr: miss! 0x%x\n", spsr); 1437 #endif 1438 } 1439 } 1440 splx(s); 1441 } 1442 #endif /* defined CB_PCMCIA_POLL */ 1443 1444 /* 1445 * static int pccbb_detect_card(struct pccbb_softc *sc) 1446 * return value: 0 if no card exists. 1447 * 1 if 16-bit card exists. 1448 * 2 if cardbus card exists. 1449 */ 1450 static int 1451 pccbb_detect_card(sc) 1452 struct pccbb_softc *sc; 1453 { 1454 bus_space_handle_t base_memh = sc->sc_base_memh; 1455 bus_space_tag_t base_memt = sc->sc_base_memt; 1456 u_int32_t sockstat = 1457 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1458 int retval = 0; 1459 1460 /* CD1 and CD2 asserted */ 1461 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1462 /* card must be present */ 1463 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1464 /* NOTACARD DEASSERTED */ 1465 if (CB_SOCKET_STAT_CB & sockstat) { 1466 /* CardBus mode */ 1467 retval = 2; 1468 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1469 /* 16-bit mode */ 1470 retval = 1; 1471 } 1472 } 1473 } 1474 return retval; 1475 } 1476 1477 /* 1478 * STATIC int cb_reset(struct pccbb_softc *sc) 1479 * This function resets CardBus card. 1480 */ 1481 STATIC int 1482 cb_reset(sc) 1483 struct pccbb_softc *sc; 1484 { 1485 /* 1486 * Reset Assert at least 20 ms 1487 * Some machines request longer duration. 1488 */ 1489 int reset_duration = 1490 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1491 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1492 1493 /* Reset bit Assert (bit 6 at 0x3E) */ 1494 bcr |= CB_BCR_RESET_ENABLE; 1495 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1496 DELAY_MS(reset_duration, sc); 1497 1498 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1499 /* Reset bit Deassert (bit 6 at 0x3E) */ 1500 bcr &= ~CB_BCR_RESET_ENABLE; 1501 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1502 DELAY_MS(reset_duration, sc); 1503 } 1504 /* No card found on the slot. Keep Reset. */ 1505 return 1; 1506 } 1507 1508 /* 1509 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1510 * This function detect card Voltage. 1511 */ 1512 STATIC int 1513 cb_detect_voltage(sc) 1514 struct pccbb_softc *sc; 1515 { 1516 u_int32_t psr; /* socket present-state reg */ 1517 bus_space_tag_t iot = sc->sc_base_memt; 1518 bus_space_handle_t ioh = sc->sc_base_memh; 1519 int vol = PCCARD_VCC_UKN; /* set 0 */ 1520 1521 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1522 1523 if (0x400u & psr) { 1524 vol |= PCCARD_VCC_5V; 1525 } 1526 if (0x800u & psr) { 1527 vol |= PCCARD_VCC_3V; 1528 } 1529 1530 return vol; 1531 } 1532 1533 STATIC int 1534 cbbprint(aux, pcic) 1535 void *aux; 1536 const char *pcic; 1537 { 1538 /* 1539 struct cbslot_attach_args *cba = aux; 1540 1541 if (cba->cba_slot >= 0) { 1542 printf(" slot %d", cba->cba_slot); 1543 } 1544 */ 1545 return UNCONF; 1546 } 1547 1548 /* 1549 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1550 * This function enables and disables the card 1551 */ 1552 STATIC int 1553 pccbb_cardenable(sc, function) 1554 struct pccbb_softc *sc; 1555 int function; 1556 { 1557 u_int32_t command = 1558 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1559 1560 DPRINTF(("pccbb_cardenable:")); 1561 switch (function) { 1562 case CARDBUS_IO_ENABLE: 1563 command |= PCI_COMMAND_IO_ENABLE; 1564 break; 1565 case CARDBUS_IO_DISABLE: 1566 command &= ~PCI_COMMAND_IO_ENABLE; 1567 break; 1568 case CARDBUS_MEM_ENABLE: 1569 command |= PCI_COMMAND_MEM_ENABLE; 1570 break; 1571 case CARDBUS_MEM_DISABLE: 1572 command &= ~PCI_COMMAND_MEM_ENABLE; 1573 break; 1574 case CARDBUS_BM_ENABLE: 1575 command |= PCI_COMMAND_MASTER_ENABLE; 1576 break; 1577 case CARDBUS_BM_DISABLE: 1578 command &= ~PCI_COMMAND_MASTER_ENABLE; 1579 break; 1580 default: 1581 return 0; 1582 } 1583 1584 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1585 DPRINTF((" command reg 0x%x\n", command)); 1586 return 1; 1587 } 1588 1589 #if !rbus 1590 /* 1591 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1592 */ 1593 static int 1594 pccbb_io_open(ct, win, start, end) 1595 cardbus_chipset_tag_t ct; 1596 int win; 1597 u_int32_t start, end; 1598 { 1599 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1600 int basereg; 1601 int limitreg; 1602 1603 if ((win < 0) || (win > 2)) { 1604 #if defined DIAGNOSTIC 1605 printf("cardbus_io_open: window out of range %d\n", win); 1606 #endif 1607 return 0; 1608 } 1609 1610 basereg = win * 8 + 0x2c; 1611 limitreg = win * 8 + 0x30; 1612 1613 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1614 start, basereg, end, limitreg)); 1615 1616 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1617 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1618 return 1; 1619 } 1620 1621 /* 1622 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1623 */ 1624 static int 1625 pccbb_io_close(ct, win) 1626 cardbus_chipset_tag_t ct; 1627 int win; 1628 { 1629 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1630 int basereg; 1631 int limitreg; 1632 1633 if ((win < 0) || (win > 2)) { 1634 #if defined DIAGNOSTIC 1635 printf("cardbus_io_close: window out of range %d\n", win); 1636 #endif 1637 return 0; 1638 } 1639 1640 basereg = win * 8 + 0x2c; 1641 limitreg = win * 8 + 0x30; 1642 1643 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1644 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1645 return 1; 1646 } 1647 1648 /* 1649 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1650 */ 1651 static int 1652 pccbb_mem_open(ct, win, start, end) 1653 cardbus_chipset_tag_t ct; 1654 int win; 1655 u_int32_t start, end; 1656 { 1657 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1658 int basereg; 1659 int limitreg; 1660 1661 if ((win < 0) || (win > 2)) { 1662 #if defined DIAGNOSTIC 1663 printf("cardbus_mem_open: window out of range %d\n", win); 1664 #endif 1665 return 0; 1666 } 1667 1668 basereg = win * 8 + 0x1c; 1669 limitreg = win * 8 + 0x20; 1670 1671 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1672 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1673 return 1; 1674 } 1675 1676 /* 1677 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1678 */ 1679 static int 1680 pccbb_mem_close(ct, win) 1681 cardbus_chipset_tag_t ct; 1682 int win; 1683 { 1684 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1685 int basereg; 1686 int limitreg; 1687 1688 if ((win < 0) || (win > 2)) { 1689 #if defined DIAGNOSTIC 1690 printf("cardbus_mem_close: window out of range %d\n", win); 1691 #endif 1692 return 0; 1693 } 1694 1695 basereg = win * 8 + 0x1c; 1696 limitreg = win * 8 + 0x20; 1697 1698 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1699 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1700 return 1; 1701 } 1702 #endif 1703 1704 /* 1705 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1706 * int irq, 1707 * int level, 1708 * int (* func) __P((void *)), 1709 * void *arg) 1710 * 1711 * This function registers an interrupt handler at the bridge, in 1712 * order not to call the interrupt handlers of child devices when 1713 * a card-deletion interrupt occurs. 1714 * 1715 * The arguments irq and level are not used. 1716 */ 1717 static void * 1718 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1719 cardbus_chipset_tag_t ct; 1720 int irq, level; 1721 int (*func) __P((void *)); 1722 void *arg; 1723 { 1724 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1725 1726 return pccbb_intr_establish(sc, irq, level, func, arg); 1727 } 1728 1729 1730 /* 1731 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1732 * void *ih) 1733 * 1734 * This function removes an interrupt handler pointed by ih. 1735 */ 1736 static void 1737 pccbb_cb_intr_disestablish(ct, ih) 1738 cardbus_chipset_tag_t ct; 1739 void *ih; 1740 { 1741 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1742 1743 pccbb_intr_disestablish(sc, ih); 1744 } 1745 1746 1747 void 1748 pccbb_intr_route(sc) 1749 struct pccbb_softc *sc; 1750 { 1751 pcireg_t reg; 1752 1753 /* initialize bridge intr routing */ 1754 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1755 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1756 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1757 1758 switch (sc->sc_chipset) { 1759 case CB_TI113X: 1760 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1761 /* functional intr enabled */ 1762 reg |= PCI113X_CBCTRL_PCI_INTR; 1763 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1764 break; 1765 default: 1766 break; 1767 } 1768 } 1769 1770 /* 1771 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1772 * int irq, 1773 * int level, 1774 * int (* func) __P((void *)), 1775 * void *arg) 1776 * 1777 * This function registers an interrupt handler at the bridge, in 1778 * order not to call the interrupt handlers of child devices when 1779 * a card-deletion interrupt occurs. 1780 * 1781 * The arguments irq is not used because pccbb selects intr vector. 1782 */ 1783 static void * 1784 pccbb_intr_establish(sc, irq, level, func, arg) 1785 struct pccbb_softc *sc; 1786 int irq, level; 1787 int (*func) __P((void *)); 1788 void *arg; 1789 { 1790 struct pccbb_intrhand_list *pil, *newpil; 1791 1792 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1793 1794 if (LIST_EMPTY(&sc->sc_pil)) { 1795 pccbb_intr_route(sc); 1796 } 1797 1798 /* 1799 * Allocate a room for interrupt handler structure. 1800 */ 1801 if (NULL == (newpil = 1802 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1803 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1804 return NULL; 1805 } 1806 1807 newpil->pil_func = func; 1808 newpil->pil_arg = arg; 1809 newpil->pil_level = level; 1810 1811 if (LIST_EMPTY(&sc->sc_pil)) { 1812 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1813 } else { 1814 for (pil = LIST_FIRST(&sc->sc_pil); 1815 LIST_NEXT(pil, pil_next) != NULL; 1816 pil = LIST_NEXT(pil, pil_next)); 1817 LIST_INSERT_AFTER(pil, newpil, pil_next); 1818 } 1819 1820 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1821 1822 return newpil; 1823 } 1824 1825 /* 1826 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1827 * void *ih) 1828 * 1829 * This function removes an interrupt handler pointed by ih. ih 1830 * should be the value returned by cardbus_intr_establish() or 1831 * NULL. 1832 * 1833 * When ih is NULL, this function will do nothing. 1834 */ 1835 static void 1836 pccbb_intr_disestablish(sc, ih) 1837 struct pccbb_softc *sc; 1838 void *ih; 1839 { 1840 struct pccbb_intrhand_list *pil; 1841 pcireg_t reg; 1842 1843 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1844 1845 if (ih == NULL) { 1846 /* intr handler is not set */ 1847 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1848 return; 1849 } 1850 1851 #ifdef DIAGNOSTIC 1852 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1853 pil = LIST_NEXT(pil, pil_next)) { 1854 printf("pccbb_intr_disestablish: pil %p\n", pil); 1855 if (pil == ih) { 1856 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1857 break; 1858 } 1859 } 1860 if (pil == NULL) { 1861 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1862 sc->sc_dev.dv_xname, ih); 1863 } 1864 #endif 1865 1866 pil = (struct pccbb_intrhand_list *)ih; 1867 LIST_REMOVE(pil, pil_next); 1868 free(pil, M_DEVBUF); 1869 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1870 1871 if (LIST_EMPTY(&sc->sc_pil)) { 1872 /* No interrupt handlers */ 1873 1874 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1875 1876 /* stop routing PCI intr */ 1877 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1878 reg |= CB_BCR_INTR_IREQ_ENABLE; 1879 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1880 1881 switch (sc->sc_chipset) { 1882 case CB_TI113X: 1883 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1884 /* functional intr disabled */ 1885 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1886 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1887 break; 1888 default: 1889 break; 1890 } 1891 } 1892 } 1893 1894 #if defined SHOW_REGS 1895 static void 1896 cb_show_regs(pc, tag, memt, memh) 1897 pci_chipset_tag_t pc; 1898 pcitag_t tag; 1899 bus_space_tag_t memt; 1900 bus_space_handle_t memh; 1901 { 1902 int i; 1903 printf("PCI config regs:"); 1904 for (i = 0; i < 0x50; i += 4) { 1905 if (i % 16 == 0) { 1906 printf("\n 0x%02x:", i); 1907 } 1908 printf(" %08x", pci_conf_read(pc, tag, i)); 1909 } 1910 for (i = 0x80; i < 0xb0; i += 4) { 1911 if (i % 16 == 0) { 1912 printf("\n 0x%02x:", i); 1913 } 1914 printf(" %08x", pci_conf_read(pc, tag, i)); 1915 } 1916 1917 if (memh == 0) { 1918 printf("\n"); 1919 return; 1920 } 1921 1922 printf("\nsocket regs:"); 1923 for (i = 0; i <= 0x10; i += 0x04) { 1924 printf(" %08x", bus_space_read_4(memt, memh, i)); 1925 } 1926 printf("\nExCA regs:"); 1927 for (i = 0; i < 0x08; ++i) { 1928 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1929 } 1930 printf("\n"); 1931 return; 1932 } 1933 #endif 1934 1935 /* 1936 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1937 * int busno, int devno, int function) 1938 * This is the function to make a tag to access config space of 1939 * a CardBus Card. It works same as pci_conf_read. 1940 */ 1941 static cardbustag_t 1942 pccbb_make_tag(cc, busno, devno, function) 1943 cardbus_chipset_tag_t cc; 1944 int busno, devno, function; 1945 { 1946 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1947 1948 return pci_make_tag(sc->sc_pc, busno, devno, function); 1949 } 1950 1951 static void 1952 pccbb_free_tag(cc, tag) 1953 cardbus_chipset_tag_t cc; 1954 cardbustag_t tag; 1955 { 1956 } 1957 1958 /* 1959 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1960 * cardbustag_t tag, int offset) 1961 * This is the function to read the config space of a CardBus Card. 1962 * It works same as pci_conf_read. 1963 */ 1964 static cardbusreg_t 1965 pccbb_conf_read(cc, tag, offset) 1966 cardbus_chipset_tag_t cc; 1967 cardbustag_t tag; 1968 int offset; /* register offset */ 1969 { 1970 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1971 1972 return pci_conf_read(sc->sc_pc, tag, offset); 1973 } 1974 1975 /* 1976 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1977 * int offs, cardbusreg_t val) 1978 * This is the function to write the config space of a CardBus Card. 1979 * It works same as pci_conf_write. 1980 */ 1981 static void 1982 pccbb_conf_write(cc, tag, reg, val) 1983 cardbus_chipset_tag_t cc; 1984 cardbustag_t tag; 1985 int reg; /* register offset */ 1986 cardbusreg_t val; 1987 { 1988 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1989 1990 pci_conf_write(sc->sc_pc, tag, reg, val); 1991 } 1992 1993 #if 0 1994 STATIC int 1995 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1996 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1997 int speed, int flags, 1998 bus_space_handle_t * iohp) 1999 #endif 2000 /* 2001 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2002 * bus_addr_t start, bus_size_t size, 2003 * bus_size_t align, 2004 * struct pcmcia_io_handle *pcihp 2005 * 2006 * This function only allocates I/O region for pccard. This function 2007 * never maps the allocated region to pccard I/O area. 2008 * 2009 * XXX: The interface of this function is not very good, I believe. 2010 */ 2011 STATIC int 2012 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2013 pcmcia_chipset_handle_t pch; 2014 bus_addr_t start; /* start address */ 2015 bus_size_t size; 2016 bus_size_t align; 2017 struct pcmcia_io_handle *pcihp; 2018 { 2019 struct pcic_handle *ph = (struct pcic_handle *)pch; 2020 bus_addr_t ioaddr; 2021 int flags = 0; 2022 bus_space_tag_t iot; 2023 bus_space_handle_t ioh; 2024 bus_addr_t mask; 2025 #if rbus 2026 rbus_tag_t rb; 2027 #endif 2028 if (align == 0) { 2029 align = size; /* XXX: funny??? */ 2030 } 2031 2032 if (start != 0) { 2033 /* XXX: assume all card decode lower 10 bits by its hardware */ 2034 mask = 0x3ff; 2035 /* enforce to use only masked address */ 2036 start &= mask; 2037 } else { 2038 /* 2039 * calculate mask: 2040 * 1. get the most significant bit of size (call it msb). 2041 * 2. compare msb with the value of size. 2042 * 3. if size is larger, shift msb left once. 2043 * 4. obtain mask value to decrement msb. 2044 */ 2045 bus_size_t size_tmp = size; 2046 int shifts = 0; 2047 2048 mask = 1; 2049 while (size_tmp) { 2050 ++shifts; 2051 size_tmp >>= 1; 2052 } 2053 mask = (1 << shifts); 2054 if (mask < size) { 2055 mask <<= 1; 2056 } 2057 --mask; 2058 } 2059 2060 /* 2061 * Allocate some arbitrary I/O space. 2062 */ 2063 2064 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2065 2066 #if rbus 2067 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2068 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2069 return 1; 2070 } 2071 #else 2072 if (start) { 2073 ioaddr = start; 2074 if (bus_space_map(iot, start, size, 0, &ioh)) { 2075 return 1; 2076 } 2077 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2078 (u_long) ioaddr, (u_long) size)); 2079 } else { 2080 flags |= PCMCIA_IO_ALLOCATED; 2081 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2082 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2083 size, align, 0, 0, &ioaddr, &ioh)) { 2084 /* No room be able to be get. */ 2085 return 1; 2086 } 2087 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2088 (u_long) ioaddr, (u_long) size)); 2089 } 2090 #endif 2091 2092 pcihp->iot = iot; 2093 pcihp->ioh = ioh; 2094 pcihp->addr = ioaddr; 2095 pcihp->size = size; 2096 pcihp->flags = flags; 2097 2098 return 0; 2099 } 2100 2101 /* 2102 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2103 * struct pcmcia_io_handle *pcihp) 2104 * 2105 * This function only frees I/O region for pccard. 2106 * 2107 * XXX: The interface of this function is not very good, I believe. 2108 */ 2109 void 2110 pccbb_pcmcia_io_free(pch, pcihp) 2111 pcmcia_chipset_handle_t pch; 2112 struct pcmcia_io_handle *pcihp; 2113 { 2114 #if !rbus 2115 bus_space_tag_t iot = pcihp->iot; 2116 #endif 2117 bus_space_handle_t ioh = pcihp->ioh; 2118 bus_size_t size = pcihp->size; 2119 2120 #if rbus 2121 struct pccbb_softc *sc = 2122 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2123 rbus_tag_t rb = sc->sc_rbus_iot; 2124 2125 rbus_space_free(rb, ioh, size, NULL); 2126 #else 2127 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2128 bus_space_free(iot, ioh, size); 2129 else 2130 bus_space_unmap(iot, ioh, size); 2131 #endif 2132 } 2133 2134 /* 2135 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2136 * bus_addr_t offset, bus_size_t size, 2137 * struct pcmcia_io_handle *pcihp, 2138 * int *windowp) 2139 * 2140 * This function maps the allocated I/O region to pccard. This function 2141 * never allocates any I/O region for pccard I/O area. I don't 2142 * understand why the original authors of pcmciabus separated alloc and 2143 * map. I believe the two must be unite. 2144 * 2145 * XXX: no wait timing control? 2146 */ 2147 int 2148 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2149 pcmcia_chipset_handle_t pch; 2150 int width; 2151 bus_addr_t offset; 2152 bus_size_t size; 2153 struct pcmcia_io_handle *pcihp; 2154 int *windowp; 2155 { 2156 struct pcic_handle *ph = (struct pcic_handle *)pch; 2157 bus_addr_t ioaddr = pcihp->addr + offset; 2158 int i, win; 2159 #if defined CBB_DEBUG 2160 static char *width_names[] = { "dynamic", "io8", "io16" }; 2161 #endif 2162 2163 /* Sanity check I/O handle. */ 2164 2165 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2166 panic("pccbb_pcmcia_io_map iot is bogus"); 2167 } 2168 2169 /* XXX Sanity check offset/size. */ 2170 2171 win = -1; 2172 for (i = 0; i < PCIC_IO_WINS; i++) { 2173 if ((ph->ioalloc & (1 << i)) == 0) { 2174 win = i; 2175 ph->ioalloc |= (1 << i); 2176 break; 2177 } 2178 } 2179 2180 if (win == -1) { 2181 return 1; 2182 } 2183 2184 *windowp = win; 2185 2186 /* XXX this is pretty gross */ 2187 2188 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2189 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2190 2191 /* XXX wtf is this doing here? */ 2192 2193 #if 0 2194 printf(" port 0x%lx", (u_long) ioaddr); 2195 if (size > 1) { 2196 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2197 } 2198 #endif 2199 2200 ph->io[win].addr = ioaddr; 2201 ph->io[win].size = size; 2202 ph->io[win].width = width; 2203 2204 /* actual dirty register-value changing in the function below. */ 2205 pccbb_pcmcia_do_io_map(ph, win); 2206 2207 return 0; 2208 } 2209 2210 /* 2211 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2212 * 2213 * This function changes register-value to map I/O region for pccard. 2214 */ 2215 static void 2216 pccbb_pcmcia_do_io_map(ph, win) 2217 struct pcic_handle *ph; 2218 int win; 2219 { 2220 static u_int8_t pcic_iowidth[3] = { 2221 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2222 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2223 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2224 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2225 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2226 }; 2227 2228 #define PCIC_SIA_START_LOW 0 2229 #define PCIC_SIA_START_HIGH 1 2230 #define PCIC_SIA_STOP_LOW 2 2231 #define PCIC_SIA_STOP_HIGH 3 2232 2233 int regbase_win = 0x8 + win * 0x04; 2234 u_int8_t ioctl, enable; 2235 2236 DPRINTF( 2237 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2238 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2239 ph->io[win].width * 8)); 2240 2241 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2242 ph->io[win].addr & 0xff); 2243 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2244 (ph->io[win].addr >> 8) & 0xff); 2245 2246 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2247 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2248 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2249 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2250 2251 ioctl = Pcic_read(ph, PCIC_IOCTL); 2252 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2253 switch (win) { 2254 case 0: 2255 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2256 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2257 PCIC_IOCTL_IO0_DATASIZE_MASK); 2258 ioctl |= pcic_iowidth[ph->io[win].width]; 2259 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2260 break; 2261 case 1: 2262 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2263 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2264 PCIC_IOCTL_IO1_DATASIZE_MASK); 2265 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2266 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2267 break; 2268 } 2269 Pcic_write(ph, PCIC_IOCTL, ioctl); 2270 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2271 #if defined CBB_DEBUG 2272 { 2273 u_int8_t start_low = 2274 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2275 u_int8_t start_high = 2276 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2277 u_int8_t stop_low = 2278 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2279 u_int8_t stop_high = 2280 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2281 printf 2282 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2283 start_low, start_high, stop_low, stop_high, ioctl, enable); 2284 } 2285 #endif 2286 } 2287 2288 /* 2289 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2290 * 2291 * This function unmaps I/O region. No return value. 2292 */ 2293 STATIC void 2294 pccbb_pcmcia_io_unmap(pch, win) 2295 pcmcia_chipset_handle_t pch; 2296 int win; 2297 { 2298 struct pcic_handle *ph = (struct pcic_handle *)pch; 2299 int reg; 2300 2301 if (win >= PCIC_IO_WINS || win < 0) { 2302 panic("pccbb_pcmcia_io_unmap: window out of range"); 2303 } 2304 2305 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2306 switch (win) { 2307 case 0: 2308 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2309 break; 2310 case 1: 2311 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2312 break; 2313 } 2314 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2315 2316 ph->ioalloc &= ~(1 << win); 2317 } 2318 2319 /* 2320 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2321 * 2322 * This function enables the card. All information is stored in 2323 * the first argument, pcmcia_chipset_handle_t. 2324 */ 2325 static void 2326 pccbb_pcmcia_wait_ready(ph) 2327 struct pcic_handle *ph; 2328 { 2329 int i; 2330 2331 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2332 Pcic_read(ph, PCIC_IF_STATUS))); 2333 2334 for (i = 0; i < 2000; i++) { 2335 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2336 return; 2337 } 2338 DELAY_MS(2, ph->ph_parent); 2339 #ifdef CBB_DEBUG 2340 if ((i > 1000) && (i % 25 == 24)) 2341 printf("."); 2342 #endif 2343 } 2344 2345 #ifdef DIAGNOSTIC 2346 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2347 Pcic_read(ph, PCIC_IF_STATUS)); 2348 #endif 2349 } 2350 2351 /* 2352 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2353 * 2354 * This function enables the card. All information is stored in 2355 * the first argument, pcmcia_chipset_handle_t. 2356 */ 2357 STATIC void 2358 pccbb_pcmcia_socket_enable(pch) 2359 pcmcia_chipset_handle_t pch; 2360 { 2361 struct pcic_handle *ph = (struct pcic_handle *)pch; 2362 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2363 int cardtype, win; 2364 u_int8_t power, intr; 2365 pcireg_t spsr; 2366 int voltage; 2367 2368 /* this bit is mostly stolen from pcic_attach_card */ 2369 2370 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2371 2372 /* get card Vcc info */ 2373 2374 spsr = 2375 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2376 CB_SOCKET_STAT); 2377 if (spsr & CB_SOCKET_STAT_5VCARD) { 2378 DPRINTF(("5V card\n")); 2379 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2380 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2381 DPRINTF(("3V card\n")); 2382 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2383 } else { 2384 printf("?V card, 0x%x\n", spsr); /* XXX */ 2385 return; 2386 } 2387 2388 /* disable socket: negate output enable bit and power off */ 2389 2390 power = 0; 2391 Pcic_write(ph, PCIC_PWRCTL, power); 2392 2393 /* power down the socket to reset it, clear the card reset pin */ 2394 2395 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2396 2397 /* 2398 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2399 * we are changing Vcc (Toff). 2400 */ 2401 /* delay(300*1000); too much */ 2402 2403 /* assert reset bit */ 2404 intr = Pcic_read(ph, PCIC_INTR); 2405 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2406 Pcic_write(ph, PCIC_INTR, intr); 2407 2408 /* power up the socket and output enable */ 2409 power = Pcic_read(ph, PCIC_PWRCTL); 2410 power |= PCIC_PWRCTL_OE; 2411 Pcic_write(ph, PCIC_PWRCTL, power); 2412 pccbb_power(sc, voltage); 2413 2414 /* 2415 * hold RESET at least 20 ms: the spec says only 10 us is 2416 * enough, but TI1130 requires at least 20 ms. 2417 */ 2418 #if 0 /* XXX called on interrupt context */ 2419 DELAY_MS(20, sc); 2420 #else 2421 delay(20 * 1000); 2422 #endif 2423 2424 /* clear the reset flag */ 2425 2426 intr |= PCIC_INTR_RESET; 2427 Pcic_write(ph, PCIC_INTR, intr); 2428 2429 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2430 2431 #if 0 /* XXX called on interrupt context */ 2432 DELAY_MS(20, sc); 2433 #else 2434 delay(20 * 1000); 2435 #endif 2436 2437 /* wait for the chip to finish initializing */ 2438 2439 pccbb_pcmcia_wait_ready(ph); 2440 2441 /* zero out the address windows */ 2442 2443 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2444 2445 /* set the card type */ 2446 2447 cardtype = pcmcia_card_gettype(ph->pcmcia); 2448 2449 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2450 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2451 Pcic_write(ph, PCIC_INTR, intr); 2452 2453 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2454 ph->ph_parent->dv_xname, ph->sock, 2455 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2456 2457 /* reinstall all the memory and io mappings */ 2458 2459 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2460 if (ph->memalloc & (1 << win)) { 2461 pccbb_pcmcia_do_mem_map(ph, win); 2462 } 2463 } 2464 2465 for (win = 0; win < PCIC_IO_WINS; ++win) { 2466 if (ph->ioalloc & (1 << win)) { 2467 pccbb_pcmcia_do_io_map(ph, win); 2468 } 2469 } 2470 } 2471 2472 /* 2473 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2474 * 2475 * This function disables the card. All information is stored in 2476 * the first argument, pcmcia_chipset_handle_t. 2477 */ 2478 STATIC void 2479 pccbb_pcmcia_socket_disable(pch) 2480 pcmcia_chipset_handle_t pch; 2481 { 2482 struct pcic_handle *ph = (struct pcic_handle *)pch; 2483 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2484 u_int8_t power, intr; 2485 2486 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2487 2488 /* reset signal asserting... */ 2489 2490 intr = Pcic_read(ph, PCIC_INTR); 2491 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2492 Pcic_write(ph, PCIC_INTR, intr); 2493 delay(2 * 1000); 2494 2495 /* power down the socket */ 2496 power = Pcic_read(ph, PCIC_PWRCTL); 2497 power &= ~PCIC_PWRCTL_OE; 2498 Pcic_write(ph, PCIC_PWRCTL, power); 2499 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2500 /* 2501 * wait 300ms until power fails (Tpf). 2502 */ 2503 #if 0 /* XXX called on interrupt context */ 2504 DELAY_MS(300, sc); 2505 #else 2506 delay(300 * 1000); 2507 #endif 2508 } 2509 2510 /* 2511 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2512 * 2513 * This function detects whether a card is in the slot or not. 2514 * If a card is inserted, return 1. Otherwise, return 0. 2515 */ 2516 STATIC int 2517 pccbb_pcmcia_card_detect(pch) 2518 pcmcia_chipset_handle_t pch; 2519 { 2520 struct pcic_handle *ph = (struct pcic_handle *)pch; 2521 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2522 2523 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2524 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2525 } 2526 2527 #if 0 2528 STATIC int 2529 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2530 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2531 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2532 #endif 2533 /* 2534 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2535 * bus_size_t size, 2536 * struct pcmcia_mem_handle *pcmhp) 2537 * 2538 * This function only allocates memory region for pccard. This 2539 * function never maps the allocated region to pccard memory area. 2540 * 2541 * XXX: Why the argument of start address is not in? 2542 */ 2543 STATIC int 2544 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2545 pcmcia_chipset_handle_t pch; 2546 bus_size_t size; 2547 struct pcmcia_mem_handle *pcmhp; 2548 { 2549 struct pcic_handle *ph = (struct pcic_handle *)pch; 2550 bus_space_handle_t memh; 2551 bus_addr_t addr; 2552 bus_size_t sizepg; 2553 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2554 #if rbus 2555 rbus_tag_t rb; 2556 #endif 2557 2558 /* out of sc->memh, allocate as many pages as necessary */ 2559 2560 /* convert size to PCIC pages */ 2561 /* 2562 * This is not enough; when the requested region is on the page 2563 * boundaries, this may calculate wrong result. 2564 */ 2565 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2566 #if 0 2567 if (sizepg > PCIC_MAX_MEM_PAGES) { 2568 return 1; 2569 } 2570 #endif 2571 2572 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2573 return 1; 2574 } 2575 2576 addr = 0; /* XXX gcc -Wuninitialized */ 2577 2578 #if rbus 2579 rb = sc->sc_rbus_memt; 2580 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2581 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2582 &addr, &memh)) { 2583 return 1; 2584 } 2585 #else 2586 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2587 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2588 0, /* boundary */ 2589 0, /* flags */ 2590 &addr, &memh)) { 2591 return 1; 2592 } 2593 #endif 2594 2595 DPRINTF( 2596 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2597 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2598 2599 pcmhp->memt = sc->sc_memt; 2600 pcmhp->memh = memh; 2601 pcmhp->addr = addr; 2602 pcmhp->size = size; 2603 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2604 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2605 pcmhp->mhandle = 0; 2606 /* No offset??? Funny. */ 2607 2608 return 0; 2609 } 2610 2611 /* 2612 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2613 * struct pcmcia_mem_handle *pcmhp) 2614 * 2615 * This function release the memory space allocated by the function 2616 * pccbb_pcmcia_mem_alloc(). 2617 */ 2618 STATIC void 2619 pccbb_pcmcia_mem_free(pch, pcmhp) 2620 pcmcia_chipset_handle_t pch; 2621 struct pcmcia_mem_handle *pcmhp; 2622 { 2623 #if rbus 2624 struct pcic_handle *ph = (struct pcic_handle *)pch; 2625 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2626 2627 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2628 #else 2629 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2630 #endif 2631 } 2632 2633 /* 2634 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2635 * 2636 * This function release the memory space allocated by the function 2637 * pccbb_pcmcia_mem_alloc(). 2638 */ 2639 STATIC void 2640 pccbb_pcmcia_do_mem_map(ph, win) 2641 struct pcic_handle *ph; 2642 int win; 2643 { 2644 int regbase_win; 2645 bus_addr_t phys_addr; 2646 bus_addr_t phys_end; 2647 2648 #define PCIC_SMM_START_LOW 0 2649 #define PCIC_SMM_START_HIGH 1 2650 #define PCIC_SMM_STOP_LOW 2 2651 #define PCIC_SMM_STOP_HIGH 3 2652 #define PCIC_CMA_LOW 4 2653 #define PCIC_CMA_HIGH 5 2654 2655 u_int8_t start_low, start_high = 0; 2656 u_int8_t stop_low, stop_high; 2657 u_int8_t off_low, off_high; 2658 u_int8_t mem_window; 2659 int reg; 2660 2661 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2662 int mem8 = 2663 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2664 || (kind == PCMCIA_MEM_ATTR); 2665 2666 regbase_win = 0x10 + win * 0x08; 2667 2668 phys_addr = ph->mem[win].addr; 2669 phys_end = phys_addr + ph->mem[win].size; 2670 2671 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2672 phys_addr, phys_end, ph->mem[win].offset)); 2673 2674 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2675 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2676 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2677 2678 /* bit 19:12 */ 2679 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2680 /* bit 23:20 and bit 7 on */ 2681 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2682 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2683 /* bit 31:24, for 32-bit address */ 2684 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2685 2686 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2687 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2688 2689 if (((struct pccbb_softc *)ph-> 2690 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2691 Pcic_write(ph, 0x40 + win, mem_window); 2692 } 2693 2694 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2695 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2696 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2697 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2698 2699 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2700 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2701 2702 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2703 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2704 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2705 | ((kind == PCMCIA_MEM_ATTR) ? 2706 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2707 2708 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2709 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2710 2711 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2712 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2713 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2714 2715 #if defined CBB_DEBUG 2716 { 2717 int r1, r2, r3, r4, r5, r6, r7 = 0; 2718 2719 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2720 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2721 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2722 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2723 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2724 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2725 if (((struct pccbb_softc *)(ph-> 2726 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2727 r7 = Pcic_read(ph, 0x40 + win); 2728 } 2729 2730 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2731 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2732 if (((struct pccbb_softc *)(ph-> 2733 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2734 DPRINTF((" %02x", r7)); 2735 } 2736 DPRINTF(("\n")); 2737 } 2738 #endif 2739 } 2740 2741 /* 2742 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2743 * bus_addr_t card_addr, bus_size_t size, 2744 * struct pcmcia_mem_handle *pcmhp, 2745 * bus_addr_t *offsetp, int *windowp) 2746 * 2747 * This function maps memory space allocated by the function 2748 * pccbb_pcmcia_mem_alloc(). 2749 */ 2750 STATIC int 2751 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2752 pcmcia_chipset_handle_t pch; 2753 int kind; 2754 bus_addr_t card_addr; 2755 bus_size_t size; 2756 struct pcmcia_mem_handle *pcmhp; 2757 bus_addr_t *offsetp; 2758 int *windowp; 2759 { 2760 struct pcic_handle *ph = (struct pcic_handle *)pch; 2761 bus_addr_t busaddr; 2762 long card_offset; 2763 int win; 2764 2765 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2766 if ((ph->memalloc & (1 << win)) == 0) { 2767 ph->memalloc |= (1 << win); 2768 break; 2769 } 2770 } 2771 2772 if (win == PCIC_MEM_WINS) { 2773 return 1; 2774 } 2775 2776 *windowp = win; 2777 2778 /* XXX this is pretty gross */ 2779 2780 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2781 panic("pccbb_pcmcia_mem_map memt is bogus"); 2782 } 2783 2784 busaddr = pcmhp->addr; 2785 2786 /* 2787 * compute the address offset to the pcmcia address space for the 2788 * pcic. this is intentionally signed. The masks and shifts below 2789 * will cause TRT to happen in the pcic registers. Deal with making 2790 * sure the address is aligned, and return the alignment offset. 2791 */ 2792 2793 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2794 card_addr -= *offsetp; 2795 2796 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2797 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2798 (u_long) card_addr)); 2799 2800 /* 2801 * include the offset in the size, and decrement size by one, since 2802 * the hw wants start/stop 2803 */ 2804 size += *offsetp - 1; 2805 2806 card_offset = (((long)card_addr) - ((long)busaddr)); 2807 2808 ph->mem[win].addr = busaddr; 2809 ph->mem[win].size = size; 2810 ph->mem[win].offset = card_offset; 2811 ph->mem[win].kind = kind; 2812 2813 pccbb_pcmcia_do_mem_map(ph, win); 2814 2815 return 0; 2816 } 2817 2818 /* 2819 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2820 * int window) 2821 * 2822 * This function unmaps memory space which mapped by the function 2823 * pccbb_pcmcia_mem_map(). 2824 */ 2825 STATIC void 2826 pccbb_pcmcia_mem_unmap(pch, window) 2827 pcmcia_chipset_handle_t pch; 2828 int window; 2829 { 2830 struct pcic_handle *ph = (struct pcic_handle *)pch; 2831 int reg; 2832 2833 if (window >= PCIC_MEM_WINS) { 2834 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2835 } 2836 2837 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2838 reg &= ~(1 << window); 2839 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2840 2841 ph->memalloc &= ~(1 << window); 2842 } 2843 2844 #if defined PCCBB_PCMCIA_POLL 2845 struct pccbb_poll_str { 2846 void *arg; 2847 int (*func) __P((void *)); 2848 int level; 2849 struct pcic_handle *ph; 2850 int count; 2851 int num; 2852 struct callout poll_ch; 2853 }; 2854 2855 static struct pccbb_poll_str pccbb_poll[10]; 2856 static int pccbb_poll_n = 0; 2857 2858 static void pccbb_pcmcia_poll __P((void *arg)); 2859 2860 static void 2861 pccbb_pcmcia_poll(arg) 2862 void *arg; 2863 { 2864 struct pccbb_poll_str *poll = arg; 2865 struct pcic_handle *ph = poll->ph; 2866 struct pccbb_softc *sc = ph->sc; 2867 int s; 2868 u_int32_t spsr; /* socket present-state reg */ 2869 2870 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2871 switch (poll->level) { 2872 case IPL_NET: 2873 s = splnet(); 2874 break; 2875 case IPL_BIO: 2876 s = splbio(); 2877 break; 2878 case IPL_TTY: /* fallthrough */ 2879 default: 2880 s = spltty(); 2881 break; 2882 } 2883 2884 spsr = 2885 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2886 CB_SOCKET_STAT); 2887 2888 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2889 if (!(spsr & 0x40)) /* CINT low */ 2890 #else 2891 if (1) 2892 #endif 2893 { 2894 if ((*poll->func) (poll->arg) > 0) { 2895 ++poll->count; 2896 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2897 #if defined LEVEL2 2898 } else { 2899 printf("intr: miss! 0x%x\n", spsr); 2900 #endif 2901 } 2902 } 2903 splx(s); 2904 } 2905 #endif /* defined CB_PCMCIA_POLL */ 2906 2907 /* 2908 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2909 * struct pcmcia_function *pf, 2910 * int ipl, 2911 * int (*func)(void *), 2912 * void *arg); 2913 * 2914 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2915 */ 2916 STATIC void * 2917 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2918 pcmcia_chipset_handle_t pch; 2919 struct pcmcia_function *pf; 2920 int ipl; 2921 int (*func) __P((void *)); 2922 void *arg; 2923 { 2924 struct pcic_handle *ph = (struct pcic_handle *)pch; 2925 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2926 2927 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2928 /* what should I do? */ 2929 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2930 DPRINTF( 2931 ("%s does not provide edge nor pulse interrupt\n", 2932 sc->sc_dev.dv_xname)); 2933 return NULL; 2934 } 2935 /* 2936 * XXX Noooooo! The interrupt flag must set properly!! 2937 * dumb pcmcia driver!! 2938 */ 2939 } 2940 2941 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2942 } 2943 2944 /* 2945 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2946 * void *ih) 2947 * 2948 * This function disables PC-Card interrupt. 2949 */ 2950 STATIC void 2951 pccbb_pcmcia_intr_disestablish(pch, ih) 2952 pcmcia_chipset_handle_t pch; 2953 void *ih; 2954 { 2955 struct pcic_handle *ph = (struct pcic_handle *)pch; 2956 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2957 2958 pccbb_intr_disestablish(sc, ih); 2959 } 2960 2961 #if rbus 2962 /* 2963 * static int 2964 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2965 * bus_addr_t addr, bus_size_t size, 2966 * bus_addr_t mask, bus_size_t align, 2967 * int flags, bus_addr_t *addrp; 2968 * bus_space_handle_t *bshp) 2969 * 2970 * This function allocates a portion of memory or io space for 2971 * clients. This function is called from CardBus card drivers. 2972 */ 2973 static int 2974 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2975 cardbus_chipset_tag_t ct; 2976 rbus_tag_t rb; 2977 bus_addr_t addr; 2978 bus_size_t size; 2979 bus_addr_t mask; 2980 bus_size_t align; 2981 int flags; 2982 bus_addr_t *addrp; 2983 bus_space_handle_t *bshp; 2984 { 2985 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2986 2987 DPRINTF( 2988 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2989 addr, size, mask, align)); 2990 2991 if (align == 0) { 2992 align = size; 2993 } 2994 2995 if (rb->rb_bt == sc->sc_memt) { 2996 if (align < 16) { 2997 return 1; 2998 } 2999 /* 3000 * XXX: align more than 0x1000 to avoid overwrapping 3001 * memory windows for two or more devices. 0x1000 3002 * means memory window's granularity. 3003 * 3004 * Two or more devices should be able to share same 3005 * memory window region. However, overrapping memory 3006 * window is not good because some devices, such as 3007 * 3Com 3C575[BC], have a broken address decoder and 3008 * intrude other's memory region. 3009 */ 3010 if (align < 0x1000) { 3011 align = 0x1000; 3012 } 3013 } else if (rb->rb_bt == sc->sc_iot) { 3014 if (align < 4) { 3015 return 1; 3016 } 3017 /* XXX: hack for avoiding ISA image */ 3018 if (mask < 0x0100) { 3019 mask = 0x3ff; 3020 addr = 0x300; 3021 } 3022 3023 } else { 3024 DPRINTF( 3025 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 3026 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 3027 return 1; 3028 /* XXX: panic here? */ 3029 } 3030 3031 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3032 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3033 return 1; 3034 } 3035 3036 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3037 3038 return 0; 3039 } 3040 3041 /* 3042 * static int 3043 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3044 * bus_space_handle_t *bshp, bus_size_t size); 3045 * 3046 * This function is called from CardBus card drivers. 3047 */ 3048 static int 3049 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3050 cardbus_chipset_tag_t ct; 3051 rbus_tag_t rb; 3052 bus_space_handle_t bsh; 3053 bus_size_t size; 3054 { 3055 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3056 bus_space_tag_t bt = rb->rb_bt; 3057 3058 pccbb_close_win(sc, bt, bsh, size); 3059 3060 if (bt == sc->sc_memt) { 3061 } else if (bt == sc->sc_iot) { 3062 } else { 3063 return 1; 3064 /* XXX: panic here? */ 3065 } 3066 3067 return rbus_space_free(rb, bsh, size, NULL); 3068 } 3069 #endif /* rbus */ 3070 3071 #if rbus 3072 3073 static int 3074 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3075 struct pccbb_softc *sc; 3076 bus_space_tag_t bst; 3077 bus_addr_t addr; 3078 bus_size_t size; 3079 bus_space_handle_t bsh; 3080 int flags; 3081 { 3082 struct pccbb_win_chain_head *head; 3083 bus_addr_t align; 3084 3085 head = &sc->sc_iowindow; 3086 align = 0x04; 3087 if (sc->sc_memt == bst) { 3088 head = &sc->sc_memwindow; 3089 align = 0x1000; 3090 DPRINTF(("using memory window, %x %x %x\n\n", 3091 sc->sc_iot, sc->sc_memt, bst)); 3092 } 3093 3094 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3095 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3096 sc->sc_dev.dv_xname, 3097 (head == &sc->sc_memwindow) ? "mem" : "io"); 3098 } 3099 pccbb_winset(align, sc, bst); 3100 3101 return 0; 3102 } 3103 3104 static int 3105 pccbb_close_win(sc, bst, bsh, size) 3106 struct pccbb_softc *sc; 3107 bus_space_tag_t bst; 3108 bus_space_handle_t bsh; 3109 bus_size_t size; 3110 { 3111 struct pccbb_win_chain_head *head; 3112 bus_addr_t align; 3113 3114 head = &sc->sc_iowindow; 3115 align = 0x04; 3116 if (sc->sc_memt == bst) { 3117 head = &sc->sc_memwindow; 3118 align = 0x1000; 3119 } 3120 3121 if (pccbb_winlist_delete(head, bsh, size)) { 3122 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3123 sc->sc_dev.dv_xname, 3124 (head == &sc->sc_memwindow) ? "mem" : "io"); 3125 } 3126 pccbb_winset(align, sc, bst); 3127 3128 return 0; 3129 } 3130 3131 static int 3132 pccbb_winlist_insert(head, start, size, bsh, flags) 3133 struct pccbb_win_chain_head *head; 3134 bus_addr_t start; 3135 bus_size_t size; 3136 bus_space_handle_t bsh; 3137 int flags; 3138 { 3139 struct pccbb_win_chain *chainp, *elem; 3140 3141 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3142 M_NOWAIT)) == NULL) 3143 return (1); /* fail */ 3144 3145 elem->wc_start = start; 3146 elem->wc_end = start + (size - 1); 3147 elem->wc_handle = bsh; 3148 elem->wc_flags = flags; 3149 3150 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3151 chainp = TAILQ_NEXT(chainp, wc_list)) { 3152 if (chainp->wc_end < start) 3153 continue; 3154 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3155 return (0); 3156 } 3157 3158 TAILQ_INSERT_TAIL(head, elem, wc_list); 3159 return (0); 3160 } 3161 3162 static int 3163 pccbb_winlist_delete(head, bsh, size) 3164 struct pccbb_win_chain_head *head; 3165 bus_space_handle_t bsh; 3166 bus_size_t size; 3167 { 3168 struct pccbb_win_chain *chainp; 3169 3170 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3171 chainp = TAILQ_NEXT(chainp, wc_list)) { 3172 if (chainp->wc_handle != bsh) 3173 continue; 3174 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3175 printf("pccbb_winlist_delete: window 0x%lx size " 3176 "inconsistent: 0x%lx, 0x%lx\n", 3177 (unsigned long)chainp->wc_start, 3178 (unsigned long)(chainp->wc_end - chainp->wc_start), 3179 (unsigned long)(size - 1)); 3180 return 1; 3181 } 3182 3183 TAILQ_REMOVE(head, chainp, wc_list); 3184 free(chainp, M_DEVBUF); 3185 3186 return 0; 3187 } 3188 3189 return 1; /* fail: no candidate to remove */ 3190 } 3191 3192 static void 3193 pccbb_winset(align, sc, bst) 3194 bus_addr_t align; 3195 struct pccbb_softc *sc; 3196 bus_space_tag_t bst; 3197 { 3198 pci_chipset_tag_t pc; 3199 pcitag_t tag; 3200 bus_addr_t mask = ~(align - 1); 3201 struct { 3202 cardbusreg_t win_start; 3203 cardbusreg_t win_limit; 3204 int win_flags; 3205 } win[2]; 3206 struct pccbb_win_chain *chainp; 3207 int offs; 3208 3209 win[0].win_start = win[1].win_start = 0xffffffff; 3210 win[0].win_limit = win[1].win_limit = 0; 3211 win[0].win_flags = win[1].win_flags = 0; 3212 3213 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3214 offs = 0x2c; 3215 if (sc->sc_memt == bst) { 3216 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3217 offs = 0x1c; 3218 } 3219 3220 if (chainp != NULL) { 3221 win[0].win_start = chainp->wc_start & mask; 3222 win[0].win_limit = chainp->wc_end & mask; 3223 win[0].win_flags = chainp->wc_flags; 3224 chainp = TAILQ_NEXT(chainp, wc_list); 3225 } 3226 3227 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3228 if (win[1].win_start == 0xffffffff) { 3229 /* window 1 is not used */ 3230 if ((win[0].win_flags == chainp->wc_flags) && 3231 (win[0].win_limit + align >= 3232 (chainp->wc_start & mask))) { 3233 /* concatenate */ 3234 win[0].win_limit = chainp->wc_end & mask; 3235 } else { 3236 /* make new window */ 3237 win[1].win_start = chainp->wc_start & mask; 3238 win[1].win_limit = chainp->wc_end & mask; 3239 win[1].win_flags = chainp->wc_flags; 3240 } 3241 continue; 3242 } 3243 3244 /* Both windows are engaged. */ 3245 if (win[0].win_flags == win[1].win_flags) { 3246 /* same flags */ 3247 if (win[0].win_flags == chainp->wc_flags) { 3248 if (win[1].win_start - (win[0].win_limit + 3249 align) < 3250 (chainp->wc_start & mask) - 3251 ((chainp->wc_end & mask) + align)) { 3252 /* 3253 * merge window 0 and 1, and set win1 3254 * to chainp 3255 */ 3256 win[0].win_limit = win[1].win_limit; 3257 win[1].win_start = 3258 chainp->wc_start & mask; 3259 win[1].win_limit = 3260 chainp->wc_end & mask; 3261 } else { 3262 win[1].win_limit = 3263 chainp->wc_end & mask; 3264 } 3265 } else { 3266 /* different flags */ 3267 3268 /* concatenate win0 and win1 */ 3269 win[0].win_limit = win[1].win_limit; 3270 /* allocate win[1] to new space */ 3271 win[1].win_start = chainp->wc_start & mask; 3272 win[1].win_limit = chainp->wc_end & mask; 3273 win[1].win_flags = chainp->wc_flags; 3274 } 3275 } else { 3276 /* the flags of win[0] and win[1] is different */ 3277 if (win[0].win_flags == chainp->wc_flags) { 3278 win[0].win_limit = chainp->wc_end & mask; 3279 /* 3280 * XXX this creates overlapping windows, so 3281 * what should the poor bridge do if one is 3282 * cachable, and the other is not? 3283 */ 3284 printf("%s: overlapping windows\n", 3285 sc->sc_dev.dv_xname); 3286 } else { 3287 win[1].win_limit = chainp->wc_end & mask; 3288 } 3289 } 3290 } 3291 3292 pc = sc->sc_pc; 3293 tag = sc->sc_tag; 3294 pci_conf_write(pc, tag, offs, win[0].win_start); 3295 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3296 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3297 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3298 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3299 pci_conf_read(pc, tag, offs), 3300 pci_conf_read(pc, tag, offs + 4) + align, 3301 pci_conf_read(pc, tag, offs + 8), 3302 pci_conf_read(pc, tag, offs + 12) + align)); 3303 3304 if (bst == sc->sc_memt) { 3305 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3306 3307 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3308 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3309 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3310 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3311 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3312 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3313 } 3314 } 3315 3316 #endif /* rbus */ 3317 3318 static void 3319 pccbb_powerhook(why, arg) 3320 int why; 3321 void *arg; 3322 { 3323 struct pccbb_softc *sc = arg; 3324 pcireg_t reg; 3325 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3326 bus_space_handle_t base_memh = sc->sc_base_memh; 3327 3328 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3329 3330 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3331 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3332 if (sc->sc_pil_intr_enable) { 3333 (void)pccbbintr_function(sc); 3334 } 3335 sc->sc_pil_intr_enable = 0; 3336 3337 /* ToDo: deactivate or suspend child devices */ 3338 3339 } 3340 3341 if (why == PWR_RESUME) { 3342 if (sc->sc_pwrmgt_offs != 0) { 3343 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3344 sc->sc_pwrmgt_offs + 4); 3345 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3346 reg & 0x100) { 3347 /* powrstate != D0 */ 3348 3349 printf("%s going back to D0 mode\n", 3350 sc->sc_dev.dv_xname); 3351 reg &= ~PCI_PMCSR_STATE_MASK; 3352 reg |= PCI_PMCSR_STATE_D0; 3353 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3354 pci_conf_write(sc->sc_pc, sc->sc_tag, 3355 sc->sc_pwrmgt_offs + 4, reg); 3356 3357 pci_conf_write(sc->sc_pc, sc->sc_tag, 3358 PCI_SOCKBASE, sc->sc_sockbase); 3359 pci_conf_write(sc->sc_pc, sc->sc_tag, 3360 PCI_BUSNUM, sc->sc_busnum); 3361 pccbb_chipinit(sc); 3362 /* setup memory and io space window for CB */ 3363 pccbb_winset(0x1000, sc, sc->sc_memt); 3364 pccbb_winset(0x04, sc, sc->sc_iot); 3365 } 3366 } 3367 3368 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3369 /* BIOS did not recover this register */ 3370 pci_conf_write (sc->sc_pc, sc->sc_tag, 3371 PCI_SOCKBASE, sc->sc_sockbase); 3372 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3373 /* BIOS did not recover this register */ 3374 pci_conf_write (sc->sc_pc, sc->sc_tag, 3375 PCI_BUSNUM, sc->sc_busnum); 3376 /* CSC Interrupt: Card detect interrupt on */ 3377 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3378 /* Card detect intr is turned on. */ 3379 reg |= CB_SOCKET_MASK_CD; 3380 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3381 /* reset interrupt */ 3382 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3383 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3384 3385 /* 3386 * check for card insertion or removal during suspend period. 3387 * XXX: the code can't cope with card swap (remove then 3388 * insert). how can we detect such situation? 3389 */ 3390 (void)pccbbintr(sc); 3391 3392 sc->sc_pil_intr_enable = 1; 3393 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3394 3395 /* ToDo: activate or wakeup child devices */ 3396 } 3397 } 3398
Indexes created Fri Sep 26 20:09:58 GMT 2025