pccbb.c revision 1.84
1 /* $NetBSD: pccbb.c,v 1.84 2002/11/09 08:51:14 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.84 2002/11/09 08:51:14 martin Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, NULL, NULL); 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 332 /* Ricoh chips */ 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 346 /* Toshiba products */ 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 348 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 350 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 356 /* Cirrus Logic products */ 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 362 /* sentinel, or Generic chip */ 363 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 364 }; 365 366 static int 367 cb_chipset(pci_id, flagp) 368 u_int32_t pci_id; 369 int *flagp; 370 { 371 const struct yenta_chipinfo *yc; 372 373 /* Loop over except the last default entry. */ 374 for (yc = yc_chipsets; yc < yc_chipsets + 375 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 376 if (pci_id == yc->yc_id) 377 break; 378 379 if (flagp != NULL) 380 *flagp = yc->yc_flags; 381 382 return (yc->yc_chiptype); 383 } 384 385 static void 386 pccbb_shutdown(void *arg) 387 { 388 struct pccbb_softc *sc = arg; 389 pcireg_t command; 390 391 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 392 393 /* 394 * turn off power 395 * 396 * XXX - do not turn off power if chipset is TI 113X because 397 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 398 */ 399 if (sc->sc_chipset != CB_TI113X) { 400 pccbb_power((cardbus_chipset_tag_t)sc, 401 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 402 } 403 404 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 405 0); 406 407 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 408 409 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 410 PCI_COMMAND_MASTER_ENABLE); 411 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 412 413 } 414 415 void 416 pccbbattach(parent, self, aux) 417 struct device *parent; 418 struct device *self; 419 void *aux; 420 { 421 struct pccbb_softc *sc = (void *)self; 422 struct pci_attach_args *pa = aux; 423 pci_chipset_tag_t pc = pa->pa_pc; 424 pcireg_t busreg, reg, sock_base; 425 bus_addr_t sockbase; 426 char devinfo[256]; 427 int flags; 428 int pwrmgt_offs; 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo); 433 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 434 #ifdef CBB_DEBUG 435 printf(" (chipflags %x)", flags); 436 #endif 437 printf("\n"); 438 439 TAILQ_INIT(&sc->sc_memwindow); 440 TAILQ_INIT(&sc->sc_iowindow); 441 442 #if rbus 443 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 444 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 445 446 #if 0 447 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 448 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 449 #endif 450 #endif /* rbus */ 451 452 sc->sc_base_memh = 0; 453 454 /* power management: set D0 state */ 455 sc->sc_pwrmgt_offs = 0; 456 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 457 &pwrmgt_offs, 0)) { 458 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + 4); 459 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 460 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 461 reg &= ~PCI_PMCSR_STATE_MASK; 462 reg |= PCI_PMCSR_STATE_D0; 463 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 464 pci_conf_write(pc, pa->pa_tag, pwrmgt_offs + 4, reg); 465 } 466 467 sc->sc_pwrmgt_offs = pwrmgt_offs; 468 } 469 470 /* 471 * MAP socket registers and ExCA registers on memory-space 472 * When no valid address is set on socket base registers (on pci 473 * config space), get it not polite way. 474 */ 475 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 476 477 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 478 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 479 /* The address must be valid. */ 480 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 481 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 482 printf("%s: can't map socket base address 0x%x\n", 483 sc->sc_dev.dv_xname, sock_base); 484 /* 485 * I think it's funny: socket base registers must be 486 * mapped on memory space, but ... 487 */ 488 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 489 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 490 NULL)) { 491 printf("%s: can't map socket base address" 492 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 493 (unsigned long)sockbase); 494 /* give up... allocate reg space via rbus. */ 495 sc->sc_base_memh = 0; 496 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 497 } 498 } else { 499 DPRINTF(("%s: socket base address 0x%lx\n", 500 sc->sc_dev.dv_xname, sockbase)); 501 } 502 } 503 504 sc->sc_mem_start = 0; /* XXX */ 505 sc->sc_mem_end = 0xffffffff; /* XXX */ 506 507 /* 508 * When interrupt isn't routed correctly, give up probing cbb and do 509 * not kill pcic-compatible port. 510 */ 511 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 512 printf("%s: NOT USED because of unconfigured interrupt\n", 513 sc->sc_dev.dv_xname); 514 return; 515 } 516 517 /* 518 * When bus number isn't set correctly, give up using 32-bit CardBus 519 * mode. 520 */ 521 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 522 #if notyet 523 if (((busreg >> 8) & 0xff) == 0) { 524 printf("%s: CardBus support disabled because of unconfigured bus number\n", 525 sc->sc_dev.dv_xname); 526 flags |= PCCBB_PCMCIA_16BITONLY; 527 } 528 #endif 529 530 /* pccbb_machdep.c end */ 531 532 #if defined CBB_DEBUG 533 { 534 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 535 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 536 intrname[pa->pa_intrpin], pa->pa_intrline); 537 } 538 #endif 539 540 /* setup softc */ 541 sc->sc_pc = pc; 542 sc->sc_iot = pa->pa_iot; 543 sc->sc_memt = pa->pa_memt; 544 sc->sc_dmat = pa->pa_dmat; 545 sc->sc_tag = pa->pa_tag; 546 sc->sc_function = pa->pa_function; 547 sc->sc_sockbase = sock_base; 548 sc->sc_busnum = busreg; 549 550 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 551 552 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 553 554 shutdownhook_establish(pccbb_shutdown, sc); 555 556 /* Disable legacy register mapping. */ 557 switch (sc->sc_chipset) { 558 case CB_RX5C46X: /* fallthrough */ 559 #if 0 560 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 561 case CB_RX5C47X: 562 #endif 563 /* 564 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 565 * cannot be disabled by substituting 0 into PCI_LEGACY 566 * register. Ricoh CardBus bridges have special bits on Bridge 567 * control reg (addr 0x3e on PCI config space). 568 */ 569 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 570 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 571 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 572 break; 573 574 default: 575 /* XXX I don't know proper way to kill legacy I/O. */ 576 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 577 break; 578 } 579 580 config_defer(self, pccbb_pci_callback); 581 } 582 583 584 585 586 /* 587 * static void pccbb_pci_callback(struct device *self) 588 * 589 * The actual attach routine: get memory space for YENTA register 590 * space, setup YENTA register and route interrupt. 591 * 592 * This function should be deferred because this device may obtain 593 * memory space dynamically. This function must avoid obtaining 594 * memory area which has already kept for another device. 595 */ 596 static void 597 pccbb_pci_callback(self) 598 struct device *self; 599 { 600 struct pccbb_softc *sc = (void *)self; 601 pci_chipset_tag_t pc = sc->sc_pc; 602 pci_intr_handle_t ih; 603 const char *intrstr = NULL; 604 bus_addr_t sockbase; 605 struct cbslot_attach_args cba; 606 struct pcmciabus_attach_args paa; 607 struct cardslot_attach_args caa; 608 struct cardslot_softc *csc; 609 610 if (0 == sc->sc_base_memh) { 611 /* The socket registers aren't mapped correctly. */ 612 #if rbus 613 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 614 (sc->sc_chipset == CB_RX5C47X 615 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 616 0, &sockbase, &sc->sc_base_memh)) { 617 return; 618 } 619 sc->sc_base_memt = sc->sc_memt; 620 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 621 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 622 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 623 PCI_SOCKBASE))); 624 #else 625 sc->sc_base_memt = sc->sc_memt; 626 #if !defined CBB_PCI_BASE 627 #define CBB_PCI_BASE 0x20000000 628 #endif 629 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 630 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 631 /* cannot allocate memory space */ 632 return; 633 } 634 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 635 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 636 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 637 sc->sc_tag, PCI_SOCKBASE))); 638 sc->sc_sockbase = sockbase; 639 #endif 640 } 641 642 /* bus bridge initialization */ 643 pccbb_chipinit(sc); 644 645 /* clear data structure for child device interrupt handlers */ 646 LIST_INIT(&sc->sc_pil); 647 sc->sc_pil_intr_enable = 1; 648 649 /* Map and establish the interrupt. */ 650 if (pci_intr_map(&sc->sc_pa, &ih)) { 651 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 652 return; 653 } 654 intrstr = pci_intr_string(pc, ih); 655 656 /* 657 * XXX pccbbintr should be called under the priority lower 658 * than any other hard interrputs. 659 */ 660 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 661 662 if (sc->sc_ih == NULL) { 663 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 664 if (intrstr != NULL) { 665 printf(" at %s", intrstr); 666 } 667 printf("\n"); 668 return; 669 } 670 671 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 672 powerhook_establish(pccbb_powerhook, sc); 673 674 { 675 u_int32_t sockstat; 676 677 sockstat = bus_space_read_4(sc->sc_base_memt, 678 sc->sc_base_memh, CB_SOCKET_STAT); 679 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 680 sc->sc_flags |= CBB_CARDEXIST; 681 } 682 } 683 684 /* 685 * attach cardbus 686 */ 687 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 688 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 689 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 690 691 /* initialize cbslot_attach */ 692 cba.cba_busname = "cardbus"; 693 cba.cba_iot = sc->sc_iot; 694 cba.cba_memt = sc->sc_memt; 695 cba.cba_dmat = sc->sc_dmat; 696 cba.cba_bus = (busreg >> 8) & 0x0ff; 697 cba.cba_cc = (void *)sc; 698 cba.cba_cf = &pccbb_funcs; 699 cba.cba_intrline = sc->sc_pa.pa_intrline; 700 701 #if rbus 702 cba.cba_rbus_iot = sc->sc_rbus_iot; 703 cba.cba_rbus_memt = sc->sc_rbus_memt; 704 #endif 705 706 cba.cba_cacheline = PCI_CACHELINE(bhlc); 707 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 708 709 if (bootverbose) { 710 printf("%s: cacheline 0x%x lattimer 0x%x\n", 711 sc->sc_dev.dv_xname, cba.cba_cacheline, 712 cba.cba_lattimer); 713 printf("%s: bhlc 0x%x lscp 0x%x\n", 714 sc->sc_dev.dv_xname, bhlc, busreg); 715 } 716 #if defined SHOW_REGS 717 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 718 sc->sc_base_memh); 719 #endif 720 } 721 722 pccbb_pcmcia_attach_setup(sc, &paa); 723 caa.caa_cb_attach = NULL; 724 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 725 caa.caa_cb_attach = &cba; 726 } 727 caa.caa_16_attach = &paa; 728 caa.caa_ph = &sc->sc_pcmcia_h; 729 730 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 731 DPRINTF(("pccbbattach: found cardslot\n")); 732 sc->sc_csc = csc; 733 } 734 735 return; 736 } 737 738 739 740 741 742 /* 743 * static void pccbb_chipinit(struct pccbb_softc *sc) 744 * 745 * This function initialize YENTA chip registers listed below: 746 * 1) PCI command reg, 747 * 2) PCI and CardBus latency timer, 748 * 3) route PCI interrupt, 749 * 4) close all memory and io windows. 750 * 5) turn off bus power. 751 * 6) card detect interrupt on. 752 * 7) clear interrupt 753 */ 754 static void 755 pccbb_chipinit(sc) 756 struct pccbb_softc *sc; 757 { 758 pci_chipset_tag_t pc = sc->sc_pc; 759 pcitag_t tag = sc->sc_tag; 760 bus_space_tag_t bmt = sc->sc_base_memt; 761 bus_space_handle_t bmh = sc->sc_base_memh; 762 pcireg_t reg; 763 764 /* 765 * Set PCI command reg. 766 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 767 */ 768 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 769 /* I believe it is harmless. */ 770 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 771 PCI_COMMAND_MASTER_ENABLE); 772 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 773 774 /* 775 * Set CardBus latency timer. 776 */ 777 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 778 if (PCI_CB_LATENCY(reg) < 0x20) { 779 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 780 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 781 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 782 } 783 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 784 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 785 786 /* 787 * Set PCI latency timer. 788 */ 789 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 790 if (PCI_LATTIMER(reg) < 0x10) { 791 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 792 reg |= (0x10 << PCI_LATTIMER_SHIFT); 793 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 794 } 795 DPRINTF(("PCI latency timer 0x%x (%x)\n", 796 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 797 798 799 /* Route functional interrupts to PCI. */ 800 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 801 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 802 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 803 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 804 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 805 806 switch (sc->sc_chipset) { 807 case CB_TI113X: 808 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 809 /* This bit is shared, but may read as 0 on some chips, so set 810 it explicitly on both functions. */ 811 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 812 /* CSC intr enable */ 813 reg |= PCI113X_CBCTRL_PCI_CSC; 814 /* functional intr prohibit | prohibit ISA routing */ 815 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 816 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 817 break; 818 819 case CB_TI12XX: 820 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 821 reg |= PCI12XX_SYSCTRL_VCCPROT; 822 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 823 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 824 reg |= PCI12XX_CBCTRL_CSC; 825 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 826 break; 827 828 case CB_TOPIC95B: 829 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 830 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 831 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 832 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 833 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 834 sc->sc_dev.dv_xname, reg)); 835 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 836 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 837 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 838 DPRINTF(("0x%x\n", reg)); 839 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 840 break; 841 842 case CB_TOPIC97: 843 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 844 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 845 sc->sc_dev.dv_xname, reg)); 846 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 847 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 848 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 849 reg |= TOPIC97_SLOT_CTRL_PCIINT; 850 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 851 DPRINTF(("0x%x\n", reg)); 852 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 853 /* make sure to assert LV card support bits */ 854 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 855 0x800 + 0x3e, 856 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 857 0x800 + 0x3e) | 0x03); 858 break; 859 } 860 861 /* Close all memory and I/O windows. */ 862 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 863 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 864 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 865 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 866 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 867 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 868 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 869 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 870 871 /* reset 16-bit pcmcia bus */ 872 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 873 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 874 875 /* turn off power */ 876 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 877 878 /* CSC Interrupt: Card detect interrupt on */ 879 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 880 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 881 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 882 /* reset interrupt */ 883 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 884 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 885 } 886 887 888 889 890 /* 891 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 892 * struct pcmciabus_attach_args *paa) 893 * 894 * This function attaches 16-bit PCcard bus. 895 */ 896 STATIC void 897 pccbb_pcmcia_attach_setup(sc, paa) 898 struct pccbb_softc *sc; 899 struct pcmciabus_attach_args *paa; 900 { 901 struct pcic_handle *ph = &sc->sc_pcmcia_h; 902 #if rbus 903 rbus_tag_t rb; 904 #endif 905 906 /* initialize pcmcia part in pccbb_softc */ 907 ph->ph_parent = (struct device *)sc; 908 ph->sock = sc->sc_function; 909 ph->flags = 0; 910 ph->shutdown = 0; 911 ph->ih_irq = sc->sc_pa.pa_intrline; 912 ph->ph_bus_t = sc->sc_base_memt; 913 ph->ph_bus_h = sc->sc_base_memh; 914 ph->ph_read = pccbb_pcmcia_read; 915 ph->ph_write = pccbb_pcmcia_write; 916 sc->sc_pct = &pccbb_pcmcia_funcs; 917 918 /* 919 * We need to do a few things here: 920 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 921 * setting the IRQ numbers to 0. 922 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 923 * routing of CSC interrupts (e.g. card removal) to PCI while in 924 * PCMCIA mode. We just leave this set all the time. 925 * 3) Enable card insertion/removal interrupts in case the chip also 926 * needs that while in PCMCIA mode. 927 * 4) Clear any pending CSC interrupt. 928 */ 929 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 930 if (sc->sc_chipset == CB_TI113X) { 931 Pcic_write(ph, PCIC_CSC_INTR, 0); 932 } else { 933 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 934 Pcic_read(ph, PCIC_CSC); 935 } 936 937 /* initialize pcmcia bus attachment */ 938 paa->paa_busname = "pcmcia"; 939 paa->pct = sc->sc_pct; 940 paa->pch = ph; 941 paa->iobase = 0; /* I don't use them */ 942 paa->iosize = 0; 943 #if rbus 944 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 945 paa->iobase = rb->rb_start + rb->rb_offset; 946 paa->iosize = rb->rb_end - rb->rb_start; 947 #endif 948 949 return; 950 } 951 952 #if 0 953 STATIC void 954 pccbb_pcmcia_attach_card(ph) 955 struct pcic_handle *ph; 956 { 957 if (ph->flags & PCIC_FLAG_CARDP) { 958 panic("pccbb_pcmcia_attach_card: already attached"); 959 } 960 961 /* call the MI attach function */ 962 pcmcia_card_attach(ph->pcmcia); 963 964 ph->flags |= PCIC_FLAG_CARDP; 965 } 966 967 STATIC void 968 pccbb_pcmcia_detach_card(ph, flags) 969 struct pcic_handle *ph; 970 int flags; 971 { 972 if (!(ph->flags & PCIC_FLAG_CARDP)) { 973 panic("pccbb_pcmcia_detach_card: already detached"); 974 } 975 976 ph->flags &= ~PCIC_FLAG_CARDP; 977 978 /* call the MI detach function */ 979 pcmcia_card_detach(ph->pcmcia, flags); 980 } 981 #endif 982 983 /* 984 * int pccbbintr(arg) 985 * void *arg; 986 * This routine handles the interrupt from Yenta PCI-CardBus bridge 987 * itself. 988 */ 989 int 990 pccbbintr(arg) 991 void *arg; 992 { 993 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 994 u_int32_t sockevent, sockstate; 995 bus_space_tag_t memt = sc->sc_base_memt; 996 bus_space_handle_t memh = sc->sc_base_memh; 997 struct pcic_handle *ph = &sc->sc_pcmcia_h; 998 999 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1000 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1001 Pcic_read(ph, PCIC_CSC); 1002 1003 if (sockevent == 0) { 1004 /* This intr is not for me: it may be for my child devices. */ 1005 if (sc->sc_pil_intr_enable) { 1006 return pccbbintr_function(sc); 1007 } else { 1008 return 0; 1009 } 1010 } 1011 1012 if (sockevent & CB_SOCKET_EVENT_CD) { 1013 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1014 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 1015 /* A card should be removed. */ 1016 if (sc->sc_flags & CBB_CARDEXIST) { 1017 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1018 sockevent)); 1019 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1020 sc->sc_flags &= ~CBB_CARDEXIST; 1021 if (sc->sc_csc->sc_status & 1022 CARDSLOT_STATUS_CARD_16) { 1023 #if 0 1024 struct pcic_handle *ph = 1025 &sc->sc_pcmcia_h; 1026 1027 pcmcia_card_deactivate(ph->pcmcia); 1028 pccbb_pcmcia_socket_disable(ph); 1029 pccbb_pcmcia_detach_card(ph, 1030 DETACH_FORCE); 1031 #endif 1032 cardslot_event_throw(sc->sc_csc, 1033 CARDSLOT_EVENT_REMOVAL_16); 1034 } else if (sc->sc_csc->sc_status & 1035 CARDSLOT_STATUS_CARD_CB) { 1036 /* Cardbus intr removed */ 1037 cardslot_event_throw(sc->sc_csc, 1038 CARDSLOT_EVENT_REMOVAL_CB); 1039 } 1040 } else if (sc->sc_flags & CBB_INSERTING) { 1041 sc->sc_flags &= ~CBB_INSERTING; 1042 callout_stop(&sc->sc_insert_ch); 1043 } 1044 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1045 /* 1046 * The pccbbintr may called from powerdown hook when 1047 * the system resumed, to detect the card 1048 * insertion/removal during suspension. 1049 */ 1050 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1051 if (sc->sc_flags & CBB_INSERTING) { 1052 callout_stop(&sc->sc_insert_ch); 1053 } 1054 callout_reset(&sc->sc_insert_ch, hz / 5, 1055 pci113x_insert, sc); 1056 sc->sc_flags |= CBB_INSERTING; 1057 } 1058 } 1059 1060 return (1); 1061 } 1062 1063 /* 1064 * static int pccbbintr_function(struct pccbb_softc *sc) 1065 * 1066 * This function calls each interrupt handler registered at the 1067 * bridge. The interrupt handlers are called in registered order. 1068 */ 1069 static int 1070 pccbbintr_function(sc) 1071 struct pccbb_softc *sc; 1072 { 1073 int retval = 0, val; 1074 struct pccbb_intrhand_list *pil; 1075 int s, splchanged; 1076 1077 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1078 pil = LIST_NEXT(pil, pil_next)) { 1079 /* 1080 * XXX priority change. gross. I use if-else 1081 * sentense instead of switch-case sentense because of 1082 * avoiding duplicate case value error. More than one 1083 * IPL_XXX use same value. It depends on 1084 * implimentation. 1085 */ 1086 splchanged = 1; 1087 if (pil->pil_level == IPL_SERIAL) { 1088 s = splserial(); 1089 } else if (pil->pil_level == IPL_HIGH) { 1090 s = splhigh(); 1091 } else if (pil->pil_level == IPL_CLOCK) { 1092 s = splclock(); 1093 } else if (pil->pil_level == IPL_AUDIO) { 1094 s = splaudio(); 1095 } else if (pil->pil_level == IPL_IMP) { 1096 s = splvm(); /* XXX */ 1097 } else if (pil->pil_level == IPL_TTY) { 1098 s = spltty(); 1099 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1100 s = splsoftserial(); 1101 } else if (pil->pil_level == IPL_NET) { 1102 s = splnet(); 1103 } else { 1104 splchanged = 0; 1105 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1106 } 1107 1108 val = (*pil->pil_func)(pil->pil_arg); 1109 1110 if (splchanged != 0) { 1111 splx(s); 1112 } 1113 1114 retval = retval == 1 ? 1 : 1115 retval == 0 ? val : val != 0 ? val : retval; 1116 } 1117 1118 return retval; 1119 } 1120 1121 static void 1122 pci113x_insert(arg) 1123 void *arg; 1124 { 1125 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1126 u_int32_t sockevent, sockstate; 1127 1128 if (!(sc->sc_flags & CBB_INSERTING)) { 1129 /* We add a card only under inserting state. */ 1130 return; 1131 } 1132 sc->sc_flags &= ~CBB_INSERTING; 1133 1134 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1135 CB_SOCKET_EVENT); 1136 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1137 CB_SOCKET_STAT); 1138 1139 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1140 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1141 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1142 sc->sc_flags |= CBB_CARDEXIST; 1143 /* call pccard interrupt handler here */ 1144 if (sockstate & CB_SOCKET_STAT_16BIT) { 1145 /* 16-bit card found */ 1146 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1147 cardslot_event_throw(sc->sc_csc, 1148 CARDSLOT_EVENT_INSERTION_16); 1149 } else if (sockstate & CB_SOCKET_STAT_CB) { 1150 /* cardbus card found */ 1151 /* cardbus_attach_card(sc->sc_csc); */ 1152 cardslot_event_throw(sc->sc_csc, 1153 CARDSLOT_EVENT_INSERTION_CB); 1154 } else { 1155 /* who are you? */ 1156 } 1157 } else { 1158 callout_reset(&sc->sc_insert_ch, hz / 10, 1159 pci113x_insert, sc); 1160 } 1161 } 1162 1163 #define PCCBB_PCMCIA_OFFSET 0x800 1164 static u_int8_t 1165 pccbb_pcmcia_read(ph, reg) 1166 struct pcic_handle *ph; 1167 int reg; 1168 { 1169 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1170 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1171 1172 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1173 PCCBB_PCMCIA_OFFSET + reg); 1174 } 1175 1176 static void 1177 pccbb_pcmcia_write(ph, reg, val) 1178 struct pcic_handle *ph; 1179 int reg; 1180 u_int8_t val; 1181 { 1182 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1183 val); 1184 1185 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1186 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1187 } 1188 1189 /* 1190 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1191 */ 1192 STATIC int 1193 pccbb_ctrl(ct, command) 1194 cardbus_chipset_tag_t ct; 1195 int command; 1196 { 1197 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1198 1199 switch (command) { 1200 case CARDBUS_CD: 1201 if (2 == pccbb_detect_card(sc)) { 1202 int retval = 0; 1203 int status = cb_detect_voltage(sc); 1204 if (PCCARD_VCC_5V & status) { 1205 retval |= CARDBUS_5V_CARD; 1206 } 1207 if (PCCARD_VCC_3V & status) { 1208 retval |= CARDBUS_3V_CARD; 1209 } 1210 if (PCCARD_VCC_XV & status) { 1211 retval |= CARDBUS_XV_CARD; 1212 } 1213 if (PCCARD_VCC_YV & status) { 1214 retval |= CARDBUS_YV_CARD; 1215 } 1216 return retval; 1217 } else { 1218 return 0; 1219 } 1220 break; 1221 case CARDBUS_RESET: 1222 return cb_reset(sc); 1223 break; 1224 case CARDBUS_IO_ENABLE: /* fallthrough */ 1225 case CARDBUS_IO_DISABLE: /* fallthrough */ 1226 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1227 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1228 case CARDBUS_BM_ENABLE: /* fallthrough */ 1229 case CARDBUS_BM_DISABLE: /* fallthrough */ 1230 /* XXX: I think we don't need to call this function below. */ 1231 return pccbb_cardenable(sc, command); 1232 break; 1233 } 1234 1235 return 0; 1236 } 1237 1238 /* 1239 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1240 * This function returns true when it succeeds and returns false when 1241 * it fails. 1242 */ 1243 STATIC int 1244 pccbb_power(ct, command) 1245 cardbus_chipset_tag_t ct; 1246 int command; 1247 { 1248 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1249 1250 u_int32_t status, sock_ctrl, reg_ctrl; 1251 bus_space_tag_t memt = sc->sc_base_memt; 1252 bus_space_handle_t memh = sc->sc_base_memh; 1253 1254 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1258 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1259 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1260 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1261 "UNKNOWN", 1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1263 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1264 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1265 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1266 "UNKNOWN", command)); 1267 1268 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1269 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1270 1271 switch (command & CARDBUS_VCCMASK) { 1272 case CARDBUS_VCC_UC: 1273 break; 1274 case CARDBUS_VCC_5V: 1275 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1276 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1277 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1278 } else { 1279 printf("%s: BAD voltage request: no 5 V card\n", 1280 sc->sc_dev.dv_xname); 1281 } 1282 break; 1283 case CARDBUS_VCC_3V: 1284 if (CB_SOCKET_STAT_3VCARD & status) { 1285 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1286 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1287 } else { 1288 printf("%s: BAD voltage request: no 3.3 V card\n", 1289 sc->sc_dev.dv_xname); 1290 } 1291 break; 1292 case CARDBUS_VCC_0V: 1293 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1294 break; 1295 default: 1296 return 0; /* power NEVER changed */ 1297 break; 1298 } 1299 1300 switch (command & CARDBUS_VPPMASK) { 1301 case CARDBUS_VPP_UC: 1302 break; 1303 case CARDBUS_VPP_0V: 1304 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1305 break; 1306 case CARDBUS_VPP_VCC: 1307 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1308 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1309 break; 1310 case CARDBUS_VPP_12V: 1311 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1312 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1313 break; 1314 } 1315 1316 #if 0 1317 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1318 #endif 1319 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1320 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1321 1322 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1323 printf 1324 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1325 sc->sc_dev.dv_xname, sock_ctrl, status); 1326 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1327 (command & CARDBUS_VCCMASK) == 1328 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1329 CARDBUS_VCCMASK) == 1330 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1331 CARDBUS_VCCMASK) == 1332 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1333 CARDBUS_VCCMASK) == 1334 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1335 CARDBUS_VCCMASK) == 1336 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1337 CARDBUS_VCCMASK) == 1338 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1339 (command & CARDBUS_VPPMASK) == 1340 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1341 CARDBUS_VPPMASK) == 1342 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1343 CARDBUS_VPPMASK) == 1344 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1345 CARDBUS_VPPMASK) == 1346 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1347 #if 0 1348 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1349 u_int32_t force = 1350 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1351 /* Reset Bad Vcc request */ 1352 force &= ~CB_SOCKET_FORCE_BADVCC; 1353 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1354 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1355 CB_SOCKET_STAT)); 1356 return 1; 1357 } 1358 #endif 1359 return 0; 1360 } 1361 1362 if (sc->sc_chipset == CB_TOPIC97) { 1363 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1364 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1365 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1366 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1367 else 1368 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1369 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1370 } 1371 1372 /* 1373 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1374 * time is 20 ms, some PC-Card bridge requires longer duration. 1375 */ 1376 #if 0 /* XXX called on interrupt context */ 1377 DELAY_MS(300, sc); 1378 #else 1379 delay(300 * 1000); 1380 #endif 1381 1382 return 1; /* power changed correctly */ 1383 } 1384 1385 #if defined CB_PCMCIA_POLL 1386 struct cb_poll_str { 1387 void *arg; 1388 int (*func) __P((void *)); 1389 int level; 1390 pccard_chipset_tag_t ct; 1391 int count; 1392 struct callout poll_ch; 1393 }; 1394 1395 static struct cb_poll_str cb_poll[10]; 1396 static int cb_poll_n = 0; 1397 1398 static void cb_pcmcia_poll __P((void *arg)); 1399 1400 static void 1401 cb_pcmcia_poll(arg) 1402 void *arg; 1403 { 1404 struct cb_poll_str *poll = arg; 1405 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1406 struct pccbb_softc *sc = psc->cpc_parent; 1407 int s; 1408 u_int32_t spsr; /* socket present-state reg */ 1409 1410 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1411 switch (poll->level) { 1412 case IPL_NET: 1413 s = splnet(); 1414 break; 1415 case IPL_BIO: 1416 s = splbio(); 1417 break; 1418 case IPL_TTY: /* fallthrough */ 1419 default: 1420 s = spltty(); 1421 break; 1422 } 1423 1424 spsr = 1425 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1426 CB_SOCKET_STAT); 1427 1428 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1429 if (!(spsr & 0x40)) { /* CINT low */ 1430 #else 1431 if (1) { 1432 #endif 1433 if ((*poll->func) (poll->arg) == 1) { 1434 ++poll->count; 1435 printf("intr: reported from poller, 0x%x\n", spsr); 1436 #if defined LEVEL2 1437 } else { 1438 printf("intr: miss! 0x%x\n", spsr); 1439 #endif 1440 } 1441 } 1442 splx(s); 1443 } 1444 #endif /* defined CB_PCMCIA_POLL */ 1445 1446 /* 1447 * static int pccbb_detect_card(struct pccbb_softc *sc) 1448 * return value: 0 if no card exists. 1449 * 1 if 16-bit card exists. 1450 * 2 if cardbus card exists. 1451 */ 1452 static int 1453 pccbb_detect_card(sc) 1454 struct pccbb_softc *sc; 1455 { 1456 bus_space_handle_t base_memh = sc->sc_base_memh; 1457 bus_space_tag_t base_memt = sc->sc_base_memt; 1458 u_int32_t sockstat = 1459 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1460 int retval = 0; 1461 1462 /* CD1 and CD2 asserted */ 1463 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1464 /* card must be present */ 1465 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1466 /* NOTACARD DEASSERTED */ 1467 if (CB_SOCKET_STAT_CB & sockstat) { 1468 /* CardBus mode */ 1469 retval = 2; 1470 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1471 /* 16-bit mode */ 1472 retval = 1; 1473 } 1474 } 1475 } 1476 return retval; 1477 } 1478 1479 /* 1480 * STATIC int cb_reset(struct pccbb_softc *sc) 1481 * This function resets CardBus card. 1482 */ 1483 STATIC int 1484 cb_reset(sc) 1485 struct pccbb_softc *sc; 1486 { 1487 /* 1488 * Reset Assert at least 20 ms 1489 * Some machines request longer duration. 1490 */ 1491 int reset_duration = 1492 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1493 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1494 1495 /* Reset bit Assert (bit 6 at 0x3E) */ 1496 bcr |= CB_BCR_RESET_ENABLE; 1497 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1498 DELAY_MS(reset_duration, sc); 1499 1500 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1501 /* Reset bit Deassert (bit 6 at 0x3E) */ 1502 bcr &= ~CB_BCR_RESET_ENABLE; 1503 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1504 DELAY_MS(reset_duration, sc); 1505 } 1506 /* No card found on the slot. Keep Reset. */ 1507 return 1; 1508 } 1509 1510 /* 1511 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1512 * This function detect card Voltage. 1513 */ 1514 STATIC int 1515 cb_detect_voltage(sc) 1516 struct pccbb_softc *sc; 1517 { 1518 u_int32_t psr; /* socket present-state reg */ 1519 bus_space_tag_t iot = sc->sc_base_memt; 1520 bus_space_handle_t ioh = sc->sc_base_memh; 1521 int vol = PCCARD_VCC_UKN; /* set 0 */ 1522 1523 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1524 1525 if (0x400u & psr) { 1526 vol |= PCCARD_VCC_5V; 1527 } 1528 if (0x800u & psr) { 1529 vol |= PCCARD_VCC_3V; 1530 } 1531 1532 return vol; 1533 } 1534 1535 STATIC int 1536 cbbprint(aux, pcic) 1537 void *aux; 1538 const char *pcic; 1539 { 1540 /* 1541 struct cbslot_attach_args *cba = aux; 1542 1543 if (cba->cba_slot >= 0) { 1544 printf(" slot %d", cba->cba_slot); 1545 } 1546 */ 1547 return UNCONF; 1548 } 1549 1550 /* 1551 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1552 * This function enables and disables the card 1553 */ 1554 STATIC int 1555 pccbb_cardenable(sc, function) 1556 struct pccbb_softc *sc; 1557 int function; 1558 { 1559 u_int32_t command = 1560 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1561 1562 DPRINTF(("pccbb_cardenable:")); 1563 switch (function) { 1564 case CARDBUS_IO_ENABLE: 1565 command |= PCI_COMMAND_IO_ENABLE; 1566 break; 1567 case CARDBUS_IO_DISABLE: 1568 command &= ~PCI_COMMAND_IO_ENABLE; 1569 break; 1570 case CARDBUS_MEM_ENABLE: 1571 command |= PCI_COMMAND_MEM_ENABLE; 1572 break; 1573 case CARDBUS_MEM_DISABLE: 1574 command &= ~PCI_COMMAND_MEM_ENABLE; 1575 break; 1576 case CARDBUS_BM_ENABLE: 1577 command |= PCI_COMMAND_MASTER_ENABLE; 1578 break; 1579 case CARDBUS_BM_DISABLE: 1580 command &= ~PCI_COMMAND_MASTER_ENABLE; 1581 break; 1582 default: 1583 return 0; 1584 } 1585 1586 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1587 DPRINTF((" command reg 0x%x\n", command)); 1588 return 1; 1589 } 1590 1591 #if !rbus 1592 /* 1593 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1594 */ 1595 static int 1596 pccbb_io_open(ct, win, start, end) 1597 cardbus_chipset_tag_t ct; 1598 int win; 1599 u_int32_t start, end; 1600 { 1601 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1602 int basereg; 1603 int limitreg; 1604 1605 if ((win < 0) || (win > 2)) { 1606 #if defined DIAGNOSTIC 1607 printf("cardbus_io_open: window out of range %d\n", win); 1608 #endif 1609 return 0; 1610 } 1611 1612 basereg = win * 8 + 0x2c; 1613 limitreg = win * 8 + 0x30; 1614 1615 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1616 start, basereg, end, limitreg)); 1617 1618 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1619 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1620 return 1; 1621 } 1622 1623 /* 1624 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1625 */ 1626 static int 1627 pccbb_io_close(ct, win) 1628 cardbus_chipset_tag_t ct; 1629 int win; 1630 { 1631 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1632 int basereg; 1633 int limitreg; 1634 1635 if ((win < 0) || (win > 2)) { 1636 #if defined DIAGNOSTIC 1637 printf("cardbus_io_close: window out of range %d\n", win); 1638 #endif 1639 return 0; 1640 } 1641 1642 basereg = win * 8 + 0x2c; 1643 limitreg = win * 8 + 0x30; 1644 1645 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1646 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1647 return 1; 1648 } 1649 1650 /* 1651 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1652 */ 1653 static int 1654 pccbb_mem_open(ct, win, start, end) 1655 cardbus_chipset_tag_t ct; 1656 int win; 1657 u_int32_t start, end; 1658 { 1659 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1660 int basereg; 1661 int limitreg; 1662 1663 if ((win < 0) || (win > 2)) { 1664 #if defined DIAGNOSTIC 1665 printf("cardbus_mem_open: window out of range %d\n", win); 1666 #endif 1667 return 0; 1668 } 1669 1670 basereg = win * 8 + 0x1c; 1671 limitreg = win * 8 + 0x20; 1672 1673 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1674 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1675 return 1; 1676 } 1677 1678 /* 1679 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1680 */ 1681 static int 1682 pccbb_mem_close(ct, win) 1683 cardbus_chipset_tag_t ct; 1684 int win; 1685 { 1686 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1687 int basereg; 1688 int limitreg; 1689 1690 if ((win < 0) || (win > 2)) { 1691 #if defined DIAGNOSTIC 1692 printf("cardbus_mem_close: window out of range %d\n", win); 1693 #endif 1694 return 0; 1695 } 1696 1697 basereg = win * 8 + 0x1c; 1698 limitreg = win * 8 + 0x20; 1699 1700 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1701 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1702 return 1; 1703 } 1704 #endif 1705 1706 /* 1707 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1708 * int irq, 1709 * int level, 1710 * int (* func) __P((void *)), 1711 * void *arg) 1712 * 1713 * This function registers an interrupt handler at the bridge, in 1714 * order not to call the interrupt handlers of child devices when 1715 * a card-deletion interrupt occurs. 1716 * 1717 * The arguments irq and level are not used. 1718 */ 1719 static void * 1720 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1721 cardbus_chipset_tag_t ct; 1722 int irq, level; 1723 int (*func) __P((void *)); 1724 void *arg; 1725 { 1726 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1727 1728 return pccbb_intr_establish(sc, irq, level, func, arg); 1729 } 1730 1731 1732 /* 1733 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1734 * void *ih) 1735 * 1736 * This function removes an interrupt handler pointed by ih. 1737 */ 1738 static void 1739 pccbb_cb_intr_disestablish(ct, ih) 1740 cardbus_chipset_tag_t ct; 1741 void *ih; 1742 { 1743 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1744 1745 pccbb_intr_disestablish(sc, ih); 1746 } 1747 1748 1749 void 1750 pccbb_intr_route(sc) 1751 struct pccbb_softc *sc; 1752 { 1753 pcireg_t reg; 1754 1755 /* initialize bridge intr routing */ 1756 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1757 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1758 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1759 1760 switch (sc->sc_chipset) { 1761 case CB_TI113X: 1762 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1763 /* functional intr enabled */ 1764 reg |= PCI113X_CBCTRL_PCI_INTR; 1765 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1766 break; 1767 default: 1768 break; 1769 } 1770 } 1771 1772 /* 1773 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1774 * int irq, 1775 * int level, 1776 * int (* func) __P((void *)), 1777 * void *arg) 1778 * 1779 * This function registers an interrupt handler at the bridge, in 1780 * order not to call the interrupt handlers of child devices when 1781 * a card-deletion interrupt occurs. 1782 * 1783 * The arguments irq is not used because pccbb selects intr vector. 1784 */ 1785 static void * 1786 pccbb_intr_establish(sc, irq, level, func, arg) 1787 struct pccbb_softc *sc; 1788 int irq, level; 1789 int (*func) __P((void *)); 1790 void *arg; 1791 { 1792 struct pccbb_intrhand_list *pil, *newpil; 1793 1794 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1795 1796 if (LIST_EMPTY(&sc->sc_pil)) { 1797 pccbb_intr_route(sc); 1798 } 1799 1800 /* 1801 * Allocate a room for interrupt handler structure. 1802 */ 1803 if (NULL == (newpil = 1804 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1805 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1806 return NULL; 1807 } 1808 1809 newpil->pil_func = func; 1810 newpil->pil_arg = arg; 1811 newpil->pil_level = level; 1812 1813 if (LIST_EMPTY(&sc->sc_pil)) { 1814 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1815 } else { 1816 for (pil = LIST_FIRST(&sc->sc_pil); 1817 LIST_NEXT(pil, pil_next) != NULL; 1818 pil = LIST_NEXT(pil, pil_next)); 1819 LIST_INSERT_AFTER(pil, newpil, pil_next); 1820 } 1821 1822 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1823 LIST_FIRST(&sc->sc_pil))); 1824 1825 return newpil; 1826 } 1827 1828 /* 1829 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1830 * void *ih) 1831 * 1832 * This function removes an interrupt handler pointed by ih. ih 1833 * should be the value returned by cardbus_intr_establish() or 1834 * NULL. 1835 * 1836 * When ih is NULL, this function will do nothing. 1837 */ 1838 static void 1839 pccbb_intr_disestablish(sc, ih) 1840 struct pccbb_softc *sc; 1841 void *ih; 1842 { 1843 struct pccbb_intrhand_list *pil; 1844 pcireg_t reg; 1845 1846 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1847 LIST_FIRST(&sc->sc_pil))); 1848 1849 if (ih == NULL) { 1850 /* intr handler is not set */ 1851 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1852 return; 1853 } 1854 1855 #ifdef DIAGNOSTIC 1856 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1857 pil = LIST_NEXT(pil, pil_next)) { 1858 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1859 if (pil == ih) { 1860 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1861 break; 1862 } 1863 } 1864 if (pil == NULL) { 1865 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1866 sc->sc_dev.dv_xname, ih); 1867 } 1868 #endif 1869 1870 pil = (struct pccbb_intrhand_list *)ih; 1871 LIST_REMOVE(pil, pil_next); 1872 free(pil, M_DEVBUF); 1873 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1874 1875 if (LIST_EMPTY(&sc->sc_pil)) { 1876 /* No interrupt handlers */ 1877 1878 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1879 1880 /* stop routing PCI intr */ 1881 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1882 reg |= CB_BCR_INTR_IREQ_ENABLE; 1883 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1884 1885 switch (sc->sc_chipset) { 1886 case CB_TI113X: 1887 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1888 /* functional intr disabled */ 1889 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1890 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1891 break; 1892 default: 1893 break; 1894 } 1895 } 1896 } 1897 1898 #if defined SHOW_REGS 1899 static void 1900 cb_show_regs(pc, tag, memt, memh) 1901 pci_chipset_tag_t pc; 1902 pcitag_t tag; 1903 bus_space_tag_t memt; 1904 bus_space_handle_t memh; 1905 { 1906 int i; 1907 printf("PCI config regs:"); 1908 for (i = 0; i < 0x50; i += 4) { 1909 if (i % 16 == 0) { 1910 printf("\n 0x%02x:", i); 1911 } 1912 printf(" %08x", pci_conf_read(pc, tag, i)); 1913 } 1914 for (i = 0x80; i < 0xb0; i += 4) { 1915 if (i % 16 == 0) { 1916 printf("\n 0x%02x:", i); 1917 } 1918 printf(" %08x", pci_conf_read(pc, tag, i)); 1919 } 1920 1921 if (memh == 0) { 1922 printf("\n"); 1923 return; 1924 } 1925 1926 printf("\nsocket regs:"); 1927 for (i = 0; i <= 0x10; i += 0x04) { 1928 printf(" %08x", bus_space_read_4(memt, memh, i)); 1929 } 1930 printf("\nExCA regs:"); 1931 for (i = 0; i < 0x08; ++i) { 1932 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1933 } 1934 printf("\n"); 1935 return; 1936 } 1937 #endif 1938 1939 /* 1940 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1941 * int busno, int devno, int function) 1942 * This is the function to make a tag to access config space of 1943 * a CardBus Card. It works same as pci_conf_read. 1944 */ 1945 static cardbustag_t 1946 pccbb_make_tag(cc, busno, devno, function) 1947 cardbus_chipset_tag_t cc; 1948 int busno, devno, function; 1949 { 1950 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1951 1952 return pci_make_tag(sc->sc_pc, busno, devno, function); 1953 } 1954 1955 static void 1956 pccbb_free_tag(cc, tag) 1957 cardbus_chipset_tag_t cc; 1958 cardbustag_t tag; 1959 { 1960 } 1961 1962 /* 1963 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1964 * cardbustag_t tag, int offset) 1965 * This is the function to read the config space of a CardBus Card. 1966 * It works same as pci_conf_read. 1967 */ 1968 static cardbusreg_t 1969 pccbb_conf_read(cc, tag, offset) 1970 cardbus_chipset_tag_t cc; 1971 cardbustag_t tag; 1972 int offset; /* register offset */ 1973 { 1974 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1975 1976 return pci_conf_read(sc->sc_pc, tag, offset); 1977 } 1978 1979 /* 1980 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1981 * int offs, cardbusreg_t val) 1982 * This is the function to write the config space of a CardBus Card. 1983 * It works same as pci_conf_write. 1984 */ 1985 static void 1986 pccbb_conf_write(cc, tag, reg, val) 1987 cardbus_chipset_tag_t cc; 1988 cardbustag_t tag; 1989 int reg; /* register offset */ 1990 cardbusreg_t val; 1991 { 1992 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1993 1994 pci_conf_write(sc->sc_pc, tag, reg, val); 1995 } 1996 1997 #if 0 1998 STATIC int 1999 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2000 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2001 int speed, int flags, 2002 bus_space_handle_t * iohp) 2003 #endif 2004 /* 2005 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2006 * bus_addr_t start, bus_size_t size, 2007 * bus_size_t align, 2008 * struct pcmcia_io_handle *pcihp 2009 * 2010 * This function only allocates I/O region for pccard. This function 2011 * never maps the allocated region to pccard I/O area. 2012 * 2013 * XXX: The interface of this function is not very good, I believe. 2014 */ 2015 STATIC int 2016 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2017 pcmcia_chipset_handle_t pch; 2018 bus_addr_t start; /* start address */ 2019 bus_size_t size; 2020 bus_size_t align; 2021 struct pcmcia_io_handle *pcihp; 2022 { 2023 struct pcic_handle *ph = (struct pcic_handle *)pch; 2024 bus_addr_t ioaddr; 2025 int flags = 0; 2026 bus_space_tag_t iot; 2027 bus_space_handle_t ioh; 2028 bus_addr_t mask; 2029 #if rbus 2030 rbus_tag_t rb; 2031 #endif 2032 if (align == 0) { 2033 align = size; /* XXX: funny??? */ 2034 } 2035 2036 if (start != 0) { 2037 /* XXX: assume all card decode lower 10 bits by its hardware */ 2038 mask = 0x3ff; 2039 /* enforce to use only masked address */ 2040 start &= mask; 2041 } else { 2042 /* 2043 * calculate mask: 2044 * 1. get the most significant bit of size (call it msb). 2045 * 2. compare msb with the value of size. 2046 * 3. if size is larger, shift msb left once. 2047 * 4. obtain mask value to decrement msb. 2048 */ 2049 bus_size_t size_tmp = size; 2050 int shifts = 0; 2051 2052 mask = 1; 2053 while (size_tmp) { 2054 ++shifts; 2055 size_tmp >>= 1; 2056 } 2057 mask = (1 << shifts); 2058 if (mask < size) { 2059 mask <<= 1; 2060 } 2061 --mask; 2062 } 2063 2064 /* 2065 * Allocate some arbitrary I/O space. 2066 */ 2067 2068 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2069 2070 #if rbus 2071 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2072 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2073 return 1; 2074 } 2075 DPRINTF(("pccbb_pcmcia_io_alloc alloc port %lx+%lx\n", 2076 (u_long) ioaddr, (u_long) size)); 2077 #else 2078 if (start) { 2079 ioaddr = start; 2080 if (bus_space_map(iot, start, size, 0, &ioh)) { 2081 return 1; 2082 } 2083 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2084 (u_long) ioaddr, (u_long) size)); 2085 } else { 2086 flags |= PCMCIA_IO_ALLOCATED; 2087 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2088 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2089 size, align, 0, 0, &ioaddr, &ioh)) { 2090 /* No room be able to be get. */ 2091 return 1; 2092 } 2093 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2094 (u_long) ioaddr, (u_long) size)); 2095 } 2096 #endif 2097 2098 pcihp->iot = iot; 2099 pcihp->ioh = ioh; 2100 pcihp->addr = ioaddr; 2101 pcihp->size = size; 2102 pcihp->flags = flags; 2103 2104 return 0; 2105 } 2106 2107 /* 2108 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2109 * struct pcmcia_io_handle *pcihp) 2110 * 2111 * This function only frees I/O region for pccard. 2112 * 2113 * XXX: The interface of this function is not very good, I believe. 2114 */ 2115 void 2116 pccbb_pcmcia_io_free(pch, pcihp) 2117 pcmcia_chipset_handle_t pch; 2118 struct pcmcia_io_handle *pcihp; 2119 { 2120 #if !rbus 2121 bus_space_tag_t iot = pcihp->iot; 2122 #endif 2123 bus_space_handle_t ioh = pcihp->ioh; 2124 bus_size_t size = pcihp->size; 2125 2126 #if rbus 2127 struct pccbb_softc *sc = 2128 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2129 rbus_tag_t rb = sc->sc_rbus_iot; 2130 2131 rbus_space_free(rb, ioh, size, NULL); 2132 #else 2133 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2134 bus_space_free(iot, ioh, size); 2135 else 2136 bus_space_unmap(iot, ioh, size); 2137 #endif 2138 } 2139 2140 /* 2141 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2142 * bus_addr_t offset, bus_size_t size, 2143 * struct pcmcia_io_handle *pcihp, 2144 * int *windowp) 2145 * 2146 * This function maps the allocated I/O region to pccard. This function 2147 * never allocates any I/O region for pccard I/O area. I don't 2148 * understand why the original authors of pcmciabus separated alloc and 2149 * map. I believe the two must be unite. 2150 * 2151 * XXX: no wait timing control? 2152 */ 2153 int 2154 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2155 pcmcia_chipset_handle_t pch; 2156 int width; 2157 bus_addr_t offset; 2158 bus_size_t size; 2159 struct pcmcia_io_handle *pcihp; 2160 int *windowp; 2161 { 2162 struct pcic_handle *ph = (struct pcic_handle *)pch; 2163 bus_addr_t ioaddr = pcihp->addr + offset; 2164 int i, win; 2165 #if defined CBB_DEBUG 2166 static char *width_names[] = { "dynamic", "io8", "io16" }; 2167 #endif 2168 2169 /* Sanity check I/O handle. */ 2170 2171 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2172 panic("pccbb_pcmcia_io_map iot is bogus"); 2173 } 2174 2175 /* XXX Sanity check offset/size. */ 2176 2177 win = -1; 2178 for (i = 0; i < PCIC_IO_WINS; i++) { 2179 if ((ph->ioalloc & (1 << i)) == 0) { 2180 win = i; 2181 ph->ioalloc |= (1 << i); 2182 break; 2183 } 2184 } 2185 2186 if (win == -1) { 2187 return 1; 2188 } 2189 2190 *windowp = win; 2191 2192 /* XXX this is pretty gross */ 2193 2194 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2195 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2196 2197 /* XXX wtf is this doing here? */ 2198 2199 #if 0 2200 printf(" port 0x%lx", (u_long) ioaddr); 2201 if (size > 1) { 2202 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2203 } 2204 #endif 2205 2206 ph->io[win].addr = ioaddr; 2207 ph->io[win].size = size; 2208 ph->io[win].width = width; 2209 2210 /* actual dirty register-value changing in the function below. */ 2211 pccbb_pcmcia_do_io_map(ph, win); 2212 2213 return 0; 2214 } 2215 2216 /* 2217 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2218 * 2219 * This function changes register-value to map I/O region for pccard. 2220 */ 2221 static void 2222 pccbb_pcmcia_do_io_map(ph, win) 2223 struct pcic_handle *ph; 2224 int win; 2225 { 2226 static u_int8_t pcic_iowidth[3] = { 2227 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2228 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2229 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2230 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2231 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2232 }; 2233 2234 #define PCIC_SIA_START_LOW 0 2235 #define PCIC_SIA_START_HIGH 1 2236 #define PCIC_SIA_STOP_LOW 2 2237 #define PCIC_SIA_STOP_HIGH 3 2238 2239 int regbase_win = 0x8 + win * 0x04; 2240 u_int8_t ioctl, enable; 2241 2242 DPRINTF( 2243 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2244 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2245 ph->io[win].width * 8)); 2246 2247 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2248 ph->io[win].addr & 0xff); 2249 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2250 (ph->io[win].addr >> 8) & 0xff); 2251 2252 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2253 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2254 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2255 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2256 2257 ioctl = Pcic_read(ph, PCIC_IOCTL); 2258 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2259 switch (win) { 2260 case 0: 2261 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2262 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2263 PCIC_IOCTL_IO0_DATASIZE_MASK); 2264 ioctl |= pcic_iowidth[ph->io[win].width]; 2265 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2266 break; 2267 case 1: 2268 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2269 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2270 PCIC_IOCTL_IO1_DATASIZE_MASK); 2271 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2272 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2273 break; 2274 } 2275 Pcic_write(ph, PCIC_IOCTL, ioctl); 2276 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2277 #if defined CBB_DEBUG 2278 { 2279 u_int8_t start_low = 2280 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2281 u_int8_t start_high = 2282 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2283 u_int8_t stop_low = 2284 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2285 u_int8_t stop_high = 2286 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2287 printf 2288 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2289 start_low, start_high, stop_low, stop_high, ioctl, enable); 2290 } 2291 #endif 2292 } 2293 2294 /* 2295 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2296 * 2297 * This function unmaps I/O region. No return value. 2298 */ 2299 STATIC void 2300 pccbb_pcmcia_io_unmap(pch, win) 2301 pcmcia_chipset_handle_t pch; 2302 int win; 2303 { 2304 struct pcic_handle *ph = (struct pcic_handle *)pch; 2305 int reg; 2306 2307 if (win >= PCIC_IO_WINS || win < 0) { 2308 panic("pccbb_pcmcia_io_unmap: window out of range"); 2309 } 2310 2311 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2312 switch (win) { 2313 case 0: 2314 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2315 break; 2316 case 1: 2317 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2318 break; 2319 } 2320 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2321 2322 ph->ioalloc &= ~(1 << win); 2323 } 2324 2325 /* 2326 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2327 * 2328 * This function enables the card. All information is stored in 2329 * the first argument, pcmcia_chipset_handle_t. 2330 */ 2331 static void 2332 pccbb_pcmcia_wait_ready(ph) 2333 struct pcic_handle *ph; 2334 { 2335 int i; 2336 2337 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2338 Pcic_read(ph, PCIC_IF_STATUS))); 2339 2340 for (i = 0; i < 2000; i++) { 2341 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2342 return; 2343 } 2344 DELAY_MS(2, ph->ph_parent); 2345 #ifdef CBB_DEBUG 2346 if ((i > 1000) && (i % 25 == 24)) 2347 printf("."); 2348 #endif 2349 } 2350 2351 #ifdef DIAGNOSTIC 2352 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2353 Pcic_read(ph, PCIC_IF_STATUS)); 2354 #endif 2355 } 2356 2357 /* 2358 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2359 * 2360 * This function enables the card. All information is stored in 2361 * the first argument, pcmcia_chipset_handle_t. 2362 */ 2363 STATIC void 2364 pccbb_pcmcia_socket_enable(pch) 2365 pcmcia_chipset_handle_t pch; 2366 { 2367 struct pcic_handle *ph = (struct pcic_handle *)pch; 2368 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2369 int cardtype, win; 2370 u_int8_t power, intr; 2371 pcireg_t spsr; 2372 int voltage; 2373 2374 /* this bit is mostly stolen from pcic_attach_card */ 2375 2376 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2377 2378 /* get card Vcc info */ 2379 2380 spsr = 2381 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2382 CB_SOCKET_STAT); 2383 if (spsr & CB_SOCKET_STAT_5VCARD) { 2384 DPRINTF(("5V card\n")); 2385 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2386 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2387 DPRINTF(("3V card\n")); 2388 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2389 } else { 2390 printf("?V card, 0x%x\n", spsr); /* XXX */ 2391 return; 2392 } 2393 2394 /* disable socket: negate output enable bit and power off */ 2395 2396 power = 0; 2397 Pcic_write(ph, PCIC_PWRCTL, power); 2398 2399 /* power down the socket to reset it, clear the card reset pin */ 2400 2401 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2402 2403 /* 2404 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2405 * we are changing Vcc (Toff). 2406 */ 2407 /* delay(300*1000); too much */ 2408 2409 /* assert reset bit */ 2410 intr = Pcic_read(ph, PCIC_INTR); 2411 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2412 Pcic_write(ph, PCIC_INTR, intr); 2413 2414 /* power up the socket and output enable */ 2415 power = Pcic_read(ph, PCIC_PWRCTL); 2416 power |= PCIC_PWRCTL_OE; 2417 Pcic_write(ph, PCIC_PWRCTL, power); 2418 pccbb_power(sc, voltage); 2419 2420 /* 2421 * hold RESET at least 20 ms: the spec says only 10 us is 2422 * enough, but TI1130 requires at least 20 ms. 2423 */ 2424 #if 0 /* XXX called on interrupt context */ 2425 DELAY_MS(20, sc); 2426 #else 2427 delay(20 * 1000); 2428 #endif 2429 2430 /* clear the reset flag */ 2431 2432 intr |= PCIC_INTR_RESET; 2433 Pcic_write(ph, PCIC_INTR, intr); 2434 2435 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2436 2437 #if 0 /* XXX called on interrupt context */ 2438 DELAY_MS(20, sc); 2439 #else 2440 delay(20 * 1000); 2441 #endif 2442 2443 /* wait for the chip to finish initializing */ 2444 2445 pccbb_pcmcia_wait_ready(ph); 2446 2447 /* zero out the address windows */ 2448 2449 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2450 2451 /* set the card type */ 2452 2453 cardtype = pcmcia_card_gettype(ph->pcmcia); 2454 2455 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2456 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2457 Pcic_write(ph, PCIC_INTR, intr); 2458 2459 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2460 ph->ph_parent->dv_xname, ph->sock, 2461 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2462 2463 /* reinstall all the memory and io mappings */ 2464 2465 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2466 if (ph->memalloc & (1 << win)) { 2467 pccbb_pcmcia_do_mem_map(ph, win); 2468 } 2469 } 2470 2471 for (win = 0; win < PCIC_IO_WINS; ++win) { 2472 if (ph->ioalloc & (1 << win)) { 2473 pccbb_pcmcia_do_io_map(ph, win); 2474 } 2475 } 2476 } 2477 2478 /* 2479 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2480 * 2481 * This function disables the card. All information is stored in 2482 * the first argument, pcmcia_chipset_handle_t. 2483 */ 2484 STATIC void 2485 pccbb_pcmcia_socket_disable(pch) 2486 pcmcia_chipset_handle_t pch; 2487 { 2488 struct pcic_handle *ph = (struct pcic_handle *)pch; 2489 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2490 u_int8_t power, intr; 2491 2492 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2493 2494 /* reset signal asserting... */ 2495 2496 intr = Pcic_read(ph, PCIC_INTR); 2497 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2498 Pcic_write(ph, PCIC_INTR, intr); 2499 delay(2 * 1000); 2500 2501 /* power down the socket */ 2502 power = Pcic_read(ph, PCIC_PWRCTL); 2503 power &= ~PCIC_PWRCTL_OE; 2504 Pcic_write(ph, PCIC_PWRCTL, power); 2505 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2506 /* 2507 * wait 300ms until power fails (Tpf). 2508 */ 2509 #if 0 /* XXX called on interrupt context */ 2510 DELAY_MS(300, sc); 2511 #else 2512 delay(300 * 1000); 2513 #endif 2514 } 2515 2516 /* 2517 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2518 * 2519 * This function detects whether a card is in the slot or not. 2520 * If a card is inserted, return 1. Otherwise, return 0. 2521 */ 2522 STATIC int 2523 pccbb_pcmcia_card_detect(pch) 2524 pcmcia_chipset_handle_t pch; 2525 { 2526 struct pcic_handle *ph = (struct pcic_handle *)pch; 2527 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2528 2529 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2530 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2531 } 2532 2533 #if 0 2534 STATIC int 2535 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2536 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2537 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2538 #endif 2539 /* 2540 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2541 * bus_size_t size, 2542 * struct pcmcia_mem_handle *pcmhp) 2543 * 2544 * This function only allocates memory region for pccard. This 2545 * function never maps the allocated region to pccard memory area. 2546 * 2547 * XXX: Why the argument of start address is not in? 2548 */ 2549 STATIC int 2550 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2551 pcmcia_chipset_handle_t pch; 2552 bus_size_t size; 2553 struct pcmcia_mem_handle *pcmhp; 2554 { 2555 struct pcic_handle *ph = (struct pcic_handle *)pch; 2556 bus_space_handle_t memh; 2557 bus_addr_t addr; 2558 bus_size_t sizepg; 2559 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2560 #if rbus 2561 rbus_tag_t rb; 2562 #endif 2563 2564 /* out of sc->memh, allocate as many pages as necessary */ 2565 2566 /* convert size to PCIC pages */ 2567 /* 2568 * This is not enough; when the requested region is on the page 2569 * boundaries, this may calculate wrong result. 2570 */ 2571 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2572 #if 0 2573 if (sizepg > PCIC_MAX_MEM_PAGES) { 2574 return 1; 2575 } 2576 #endif 2577 2578 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2579 return 1; 2580 } 2581 2582 addr = 0; /* XXX gcc -Wuninitialized */ 2583 2584 #if rbus 2585 rb = sc->sc_rbus_memt; 2586 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2587 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2588 &addr, &memh)) { 2589 return 1; 2590 } 2591 #else 2592 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2593 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2594 0, /* boundary */ 2595 0, /* flags */ 2596 &addr, &memh)) { 2597 return 1; 2598 } 2599 #endif 2600 2601 DPRINTF( 2602 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2603 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2604 2605 pcmhp->memt = sc->sc_memt; 2606 pcmhp->memh = memh; 2607 pcmhp->addr = addr; 2608 pcmhp->size = size; 2609 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2610 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2611 pcmhp->mhandle = 0; 2612 /* No offset??? Funny. */ 2613 2614 return 0; 2615 } 2616 2617 /* 2618 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2619 * struct pcmcia_mem_handle *pcmhp) 2620 * 2621 * This function release the memory space allocated by the function 2622 * pccbb_pcmcia_mem_alloc(). 2623 */ 2624 STATIC void 2625 pccbb_pcmcia_mem_free(pch, pcmhp) 2626 pcmcia_chipset_handle_t pch; 2627 struct pcmcia_mem_handle *pcmhp; 2628 { 2629 #if rbus 2630 struct pcic_handle *ph = (struct pcic_handle *)pch; 2631 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2632 2633 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2634 #else 2635 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2636 #endif 2637 } 2638 2639 /* 2640 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2641 * 2642 * This function release the memory space allocated by the function 2643 * pccbb_pcmcia_mem_alloc(). 2644 */ 2645 STATIC void 2646 pccbb_pcmcia_do_mem_map(ph, win) 2647 struct pcic_handle *ph; 2648 int win; 2649 { 2650 int regbase_win; 2651 bus_addr_t phys_addr; 2652 bus_addr_t phys_end; 2653 2654 #define PCIC_SMM_START_LOW 0 2655 #define PCIC_SMM_START_HIGH 1 2656 #define PCIC_SMM_STOP_LOW 2 2657 #define PCIC_SMM_STOP_HIGH 3 2658 #define PCIC_CMA_LOW 4 2659 #define PCIC_CMA_HIGH 5 2660 2661 u_int8_t start_low, start_high = 0; 2662 u_int8_t stop_low, stop_high; 2663 u_int8_t off_low, off_high; 2664 u_int8_t mem_window; 2665 int reg; 2666 2667 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2668 int mem8 = 2669 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2670 || (kind == PCMCIA_MEM_ATTR); 2671 2672 regbase_win = 0x10 + win * 0x08; 2673 2674 phys_addr = ph->mem[win].addr; 2675 phys_end = phys_addr + ph->mem[win].size; 2676 2677 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2678 phys_addr, phys_end, ph->mem[win].offset)); 2679 2680 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2681 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2682 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2683 2684 /* bit 19:12 */ 2685 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2686 /* bit 23:20 and bit 7 on */ 2687 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2688 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2689 /* bit 31:24, for 32-bit address */ 2690 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2691 2692 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2693 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2694 2695 if (((struct pccbb_softc *)ph-> 2696 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2697 Pcic_write(ph, 0x40 + win, mem_window); 2698 } 2699 2700 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2701 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2702 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2703 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2704 2705 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2706 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2707 2708 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2709 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2710 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2711 | ((kind == PCMCIA_MEM_ATTR) ? 2712 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2713 2714 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2715 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2716 2717 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2718 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2719 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2720 2721 #if defined CBB_DEBUG 2722 { 2723 int r1, r2, r3, r4, r5, r6, r7 = 0; 2724 2725 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2726 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2727 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2728 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2729 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2730 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2731 if (((struct pccbb_softc *)(ph-> 2732 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2733 r7 = Pcic_read(ph, 0x40 + win); 2734 } 2735 2736 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2737 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2738 if (((struct pccbb_softc *)(ph-> 2739 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2740 DPRINTF((" %02x", r7)); 2741 } 2742 DPRINTF(("\n")); 2743 } 2744 #endif 2745 } 2746 2747 /* 2748 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2749 * bus_addr_t card_addr, bus_size_t size, 2750 * struct pcmcia_mem_handle *pcmhp, 2751 * bus_addr_t *offsetp, int *windowp) 2752 * 2753 * This function maps memory space allocated by the function 2754 * pccbb_pcmcia_mem_alloc(). 2755 */ 2756 STATIC int 2757 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2758 pcmcia_chipset_handle_t pch; 2759 int kind; 2760 bus_addr_t card_addr; 2761 bus_size_t size; 2762 struct pcmcia_mem_handle *pcmhp; 2763 bus_addr_t *offsetp; 2764 int *windowp; 2765 { 2766 struct pcic_handle *ph = (struct pcic_handle *)pch; 2767 bus_addr_t busaddr; 2768 long card_offset; 2769 int win; 2770 2771 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2772 if ((ph->memalloc & (1 << win)) == 0) { 2773 ph->memalloc |= (1 << win); 2774 break; 2775 } 2776 } 2777 2778 if (win == PCIC_MEM_WINS) { 2779 return 1; 2780 } 2781 2782 *windowp = win; 2783 2784 /* XXX this is pretty gross */ 2785 2786 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2787 panic("pccbb_pcmcia_mem_map memt is bogus"); 2788 } 2789 2790 busaddr = pcmhp->addr; 2791 2792 /* 2793 * compute the address offset to the pcmcia address space for the 2794 * pcic. this is intentionally signed. The masks and shifts below 2795 * will cause TRT to happen in the pcic registers. Deal with making 2796 * sure the address is aligned, and return the alignment offset. 2797 */ 2798 2799 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2800 card_addr -= *offsetp; 2801 2802 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2803 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2804 (u_long) card_addr)); 2805 2806 /* 2807 * include the offset in the size, and decrement size by one, since 2808 * the hw wants start/stop 2809 */ 2810 size += *offsetp - 1; 2811 2812 card_offset = (((long)card_addr) - ((long)busaddr)); 2813 2814 ph->mem[win].addr = busaddr; 2815 ph->mem[win].size = size; 2816 ph->mem[win].offset = card_offset; 2817 ph->mem[win].kind = kind; 2818 2819 pccbb_pcmcia_do_mem_map(ph, win); 2820 2821 return 0; 2822 } 2823 2824 /* 2825 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2826 * int window) 2827 * 2828 * This function unmaps memory space which mapped by the function 2829 * pccbb_pcmcia_mem_map(). 2830 */ 2831 STATIC void 2832 pccbb_pcmcia_mem_unmap(pch, window) 2833 pcmcia_chipset_handle_t pch; 2834 int window; 2835 { 2836 struct pcic_handle *ph = (struct pcic_handle *)pch; 2837 int reg; 2838 2839 if (window >= PCIC_MEM_WINS) { 2840 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2841 } 2842 2843 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2844 reg &= ~(1 << window); 2845 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2846 2847 ph->memalloc &= ~(1 << window); 2848 } 2849 2850 #if defined PCCBB_PCMCIA_POLL 2851 struct pccbb_poll_str { 2852 void *arg; 2853 int (*func) __P((void *)); 2854 int level; 2855 struct pcic_handle *ph; 2856 int count; 2857 int num; 2858 struct callout poll_ch; 2859 }; 2860 2861 static struct pccbb_poll_str pccbb_poll[10]; 2862 static int pccbb_poll_n = 0; 2863 2864 static void pccbb_pcmcia_poll __P((void *arg)); 2865 2866 static void 2867 pccbb_pcmcia_poll(arg) 2868 void *arg; 2869 { 2870 struct pccbb_poll_str *poll = arg; 2871 struct pcic_handle *ph = poll->ph; 2872 struct pccbb_softc *sc = ph->sc; 2873 int s; 2874 u_int32_t spsr; /* socket present-state reg */ 2875 2876 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2877 switch (poll->level) { 2878 case IPL_NET: 2879 s = splnet(); 2880 break; 2881 case IPL_BIO: 2882 s = splbio(); 2883 break; 2884 case IPL_TTY: /* fallthrough */ 2885 default: 2886 s = spltty(); 2887 break; 2888 } 2889 2890 spsr = 2891 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2892 CB_SOCKET_STAT); 2893 2894 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2895 if (!(spsr & 0x40)) /* CINT low */ 2896 #else 2897 if (1) 2898 #endif 2899 { 2900 if ((*poll->func) (poll->arg) > 0) { 2901 ++poll->count; 2902 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2903 #if defined LEVEL2 2904 } else { 2905 printf("intr: miss! 0x%x\n", spsr); 2906 #endif 2907 } 2908 } 2909 splx(s); 2910 } 2911 #endif /* defined CB_PCMCIA_POLL */ 2912 2913 /* 2914 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2915 * struct pcmcia_function *pf, 2916 * int ipl, 2917 * int (*func)(void *), 2918 * void *arg); 2919 * 2920 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2921 */ 2922 STATIC void * 2923 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2924 pcmcia_chipset_handle_t pch; 2925 struct pcmcia_function *pf; 2926 int ipl; 2927 int (*func) __P((void *)); 2928 void *arg; 2929 { 2930 struct pcic_handle *ph = (struct pcic_handle *)pch; 2931 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2932 2933 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2934 /* what should I do? */ 2935 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2936 DPRINTF( 2937 ("%s does not provide edge nor pulse interrupt\n", 2938 sc->sc_dev.dv_xname)); 2939 return NULL; 2940 } 2941 /* 2942 * XXX Noooooo! The interrupt flag must set properly!! 2943 * dumb pcmcia driver!! 2944 */ 2945 } 2946 2947 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2948 } 2949 2950 /* 2951 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2952 * void *ih) 2953 * 2954 * This function disables PC-Card interrupt. 2955 */ 2956 STATIC void 2957 pccbb_pcmcia_intr_disestablish(pch, ih) 2958 pcmcia_chipset_handle_t pch; 2959 void *ih; 2960 { 2961 struct pcic_handle *ph = (struct pcic_handle *)pch; 2962 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2963 2964 pccbb_intr_disestablish(sc, ih); 2965 } 2966 2967 #if rbus 2968 /* 2969 * static int 2970 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2971 * bus_addr_t addr, bus_size_t size, 2972 * bus_addr_t mask, bus_size_t align, 2973 * int flags, bus_addr_t *addrp; 2974 * bus_space_handle_t *bshp) 2975 * 2976 * This function allocates a portion of memory or io space for 2977 * clients. This function is called from CardBus card drivers. 2978 */ 2979 static int 2980 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2981 cardbus_chipset_tag_t ct; 2982 rbus_tag_t rb; 2983 bus_addr_t addr; 2984 bus_size_t size; 2985 bus_addr_t mask; 2986 bus_size_t align; 2987 int flags; 2988 bus_addr_t *addrp; 2989 bus_space_handle_t *bshp; 2990 { 2991 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2992 2993 DPRINTF( 2994 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2995 addr, size, mask, align)); 2996 2997 if (align == 0) { 2998 align = size; 2999 } 3000 3001 if (rb->rb_bt == sc->sc_memt) { 3002 if (align < 16) { 3003 return 1; 3004 } 3005 /* 3006 * XXX: align more than 0x1000 to avoid overwrapping 3007 * memory windows for two or more devices. 0x1000 3008 * means memory window's granularity. 3009 * 3010 * Two or more devices should be able to share same 3011 * memory window region. However, overrapping memory 3012 * window is not good because some devices, such as 3013 * 3Com 3C575[BC], have a broken address decoder and 3014 * intrude other's memory region. 3015 */ 3016 if (align < 0x1000) { 3017 align = 0x1000; 3018 } 3019 } else if (rb->rb_bt == sc->sc_iot) { 3020 if (align < 4) { 3021 return 1; 3022 } 3023 /* XXX: hack for avoiding ISA image */ 3024 if (mask < 0x0100) { 3025 mask = 0x3ff; 3026 addr = 0x300; 3027 } 3028 3029 } else { 3030 DPRINTF( 3031 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 3032 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 3033 return 1; 3034 /* XXX: panic here? */ 3035 } 3036 3037 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3038 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3039 return 1; 3040 } 3041 3042 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3043 3044 return 0; 3045 } 3046 3047 /* 3048 * static int 3049 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3050 * bus_space_handle_t *bshp, bus_size_t size); 3051 * 3052 * This function is called from CardBus card drivers. 3053 */ 3054 static int 3055 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3056 cardbus_chipset_tag_t ct; 3057 rbus_tag_t rb; 3058 bus_space_handle_t bsh; 3059 bus_size_t size; 3060 { 3061 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3062 bus_space_tag_t bt = rb->rb_bt; 3063 3064 pccbb_close_win(sc, bt, bsh, size); 3065 3066 if (bt == sc->sc_memt) { 3067 } else if (bt == sc->sc_iot) { 3068 } else { 3069 return 1; 3070 /* XXX: panic here? */ 3071 } 3072 3073 return rbus_space_free(rb, bsh, size, NULL); 3074 } 3075 #endif /* rbus */ 3076 3077 #if rbus 3078 3079 static int 3080 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3081 struct pccbb_softc *sc; 3082 bus_space_tag_t bst; 3083 bus_addr_t addr; 3084 bus_size_t size; 3085 bus_space_handle_t bsh; 3086 int flags; 3087 { 3088 struct pccbb_win_chain_head *head; 3089 bus_addr_t align; 3090 3091 head = &sc->sc_iowindow; 3092 align = 0x04; 3093 if (sc->sc_memt == bst) { 3094 head = &sc->sc_memwindow; 3095 align = 0x1000; 3096 DPRINTF(("using memory window, %x %x %x\n\n", 3097 sc->sc_iot, sc->sc_memt, bst)); 3098 } 3099 3100 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3101 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3102 sc->sc_dev.dv_xname, 3103 (head == &sc->sc_memwindow) ? "mem" : "io"); 3104 } 3105 pccbb_winset(align, sc, bst); 3106 3107 return 0; 3108 } 3109 3110 static int 3111 pccbb_close_win(sc, bst, bsh, size) 3112 struct pccbb_softc *sc; 3113 bus_space_tag_t bst; 3114 bus_space_handle_t bsh; 3115 bus_size_t size; 3116 { 3117 struct pccbb_win_chain_head *head; 3118 bus_addr_t align; 3119 3120 head = &sc->sc_iowindow; 3121 align = 0x04; 3122 if (sc->sc_memt == bst) { 3123 head = &sc->sc_memwindow; 3124 align = 0x1000; 3125 } 3126 3127 if (pccbb_winlist_delete(head, bsh, size)) { 3128 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3129 sc->sc_dev.dv_xname, 3130 (head == &sc->sc_memwindow) ? "mem" : "io"); 3131 } 3132 pccbb_winset(align, sc, bst); 3133 3134 return 0; 3135 } 3136 3137 static int 3138 pccbb_winlist_insert(head, start, size, bsh, flags) 3139 struct pccbb_win_chain_head *head; 3140 bus_addr_t start; 3141 bus_size_t size; 3142 bus_space_handle_t bsh; 3143 int flags; 3144 { 3145 struct pccbb_win_chain *chainp, *elem; 3146 3147 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3148 M_NOWAIT)) == NULL) 3149 return (1); /* fail */ 3150 3151 elem->wc_start = start; 3152 elem->wc_end = start + (size - 1); 3153 elem->wc_handle = bsh; 3154 elem->wc_flags = flags; 3155 3156 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3157 chainp = TAILQ_NEXT(chainp, wc_list)) { 3158 if (chainp->wc_end < start) 3159 continue; 3160 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3161 return (0); 3162 } 3163 3164 TAILQ_INSERT_TAIL(head, elem, wc_list); 3165 return (0); 3166 } 3167 3168 static int 3169 pccbb_winlist_delete(head, bsh, size) 3170 struct pccbb_win_chain_head *head; 3171 bus_space_handle_t bsh; 3172 bus_size_t size; 3173 { 3174 struct pccbb_win_chain *chainp; 3175 3176 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3177 chainp = TAILQ_NEXT(chainp, wc_list)) { 3178 if (chainp->wc_handle != bsh) 3179 continue; 3180 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3181 printf("pccbb_winlist_delete: window 0x%lx size " 3182 "inconsistent: 0x%lx, 0x%lx\n", 3183 (unsigned long)chainp->wc_start, 3184 (unsigned long)(chainp->wc_end - chainp->wc_start), 3185 (unsigned long)(size - 1)); 3186 return 1; 3187 } 3188 3189 TAILQ_REMOVE(head, chainp, wc_list); 3190 free(chainp, M_DEVBUF); 3191 3192 return 0; 3193 } 3194 3195 return 1; /* fail: no candidate to remove */ 3196 } 3197 3198 static void 3199 pccbb_winset(align, sc, bst) 3200 bus_addr_t align; 3201 struct pccbb_softc *sc; 3202 bus_space_tag_t bst; 3203 { 3204 pci_chipset_tag_t pc; 3205 pcitag_t tag; 3206 bus_addr_t mask = ~(align - 1); 3207 struct { 3208 cardbusreg_t win_start; 3209 cardbusreg_t win_limit; 3210 int win_flags; 3211 } win[2]; 3212 struct pccbb_win_chain *chainp; 3213 int offs; 3214 3215 win[0].win_start = win[1].win_start = 0xffffffff; 3216 win[0].win_limit = win[1].win_limit = 0; 3217 win[0].win_flags = win[1].win_flags = 0; 3218 3219 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3220 offs = 0x2c; 3221 if (sc->sc_memt == bst) { 3222 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3223 offs = 0x1c; 3224 } 3225 3226 if (chainp != NULL) { 3227 win[0].win_start = chainp->wc_start & mask; 3228 win[0].win_limit = chainp->wc_end & mask; 3229 win[0].win_flags = chainp->wc_flags; 3230 chainp = TAILQ_NEXT(chainp, wc_list); 3231 } 3232 3233 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3234 if (win[1].win_start == 0xffffffff) { 3235 /* window 1 is not used */ 3236 if ((win[0].win_flags == chainp->wc_flags) && 3237 (win[0].win_limit + align >= 3238 (chainp->wc_start & mask))) { 3239 /* concatenate */ 3240 win[0].win_limit = chainp->wc_end & mask; 3241 } else { 3242 /* make new window */ 3243 win[1].win_start = chainp->wc_start & mask; 3244 win[1].win_limit = chainp->wc_end & mask; 3245 win[1].win_flags = chainp->wc_flags; 3246 } 3247 continue; 3248 } 3249 3250 /* Both windows are engaged. */ 3251 if (win[0].win_flags == win[1].win_flags) { 3252 /* same flags */ 3253 if (win[0].win_flags == chainp->wc_flags) { 3254 if (win[1].win_start - (win[0].win_limit + 3255 align) < 3256 (chainp->wc_start & mask) - 3257 ((chainp->wc_end & mask) + align)) { 3258 /* 3259 * merge window 0 and 1, and set win1 3260 * to chainp 3261 */ 3262 win[0].win_limit = win[1].win_limit; 3263 win[1].win_start = 3264 chainp->wc_start & mask; 3265 win[1].win_limit = 3266 chainp->wc_end & mask; 3267 } else { 3268 win[1].win_limit = 3269 chainp->wc_end & mask; 3270 } 3271 } else { 3272 /* different flags */ 3273 3274 /* concatenate win0 and win1 */ 3275 win[0].win_limit = win[1].win_limit; 3276 /* allocate win[1] to new space */ 3277 win[1].win_start = chainp->wc_start & mask; 3278 win[1].win_limit = chainp->wc_end & mask; 3279 win[1].win_flags = chainp->wc_flags; 3280 } 3281 } else { 3282 /* the flags of win[0] and win[1] is different */ 3283 if (win[0].win_flags == chainp->wc_flags) { 3284 win[0].win_limit = chainp->wc_end & mask; 3285 /* 3286 * XXX this creates overlapping windows, so 3287 * what should the poor bridge do if one is 3288 * cachable, and the other is not? 3289 */ 3290 printf("%s: overlapping windows\n", 3291 sc->sc_dev.dv_xname); 3292 } else { 3293 win[1].win_limit = chainp->wc_end & mask; 3294 } 3295 } 3296 } 3297 3298 pc = sc->sc_pc; 3299 tag = sc->sc_tag; 3300 pci_conf_write(pc, tag, offs, win[0].win_start); 3301 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3302 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3303 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3304 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3305 pci_conf_read(pc, tag, offs), 3306 pci_conf_read(pc, tag, offs + 4) + align, 3307 pci_conf_read(pc, tag, offs + 8), 3308 pci_conf_read(pc, tag, offs + 12) + align)); 3309 3310 if (bst == sc->sc_memt) { 3311 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3312 3313 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3314 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3315 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3316 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3317 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3318 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3319 } 3320 } 3321 3322 #endif /* rbus */ 3323 3324 static void 3325 pccbb_powerhook(why, arg) 3326 int why; 3327 void *arg; 3328 { 3329 struct pccbb_softc *sc = arg; 3330 pcireg_t reg; 3331 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3332 bus_space_handle_t base_memh = sc->sc_base_memh; 3333 3334 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3335 3336 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3337 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3338 if (sc->sc_pil_intr_enable) { 3339 (void)pccbbintr_function(sc); 3340 } 3341 sc->sc_pil_intr_enable = 0; 3342 3343 /* ToDo: deactivate or suspend child devices */ 3344 3345 } 3346 3347 if (why == PWR_RESUME) { 3348 if (sc->sc_pwrmgt_offs != 0) { 3349 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3350 sc->sc_pwrmgt_offs + 4); 3351 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3352 reg & 0x100) { 3353 /* powrstate != D0 */ 3354 3355 printf("%s going back to D0 mode\n", 3356 sc->sc_dev.dv_xname); 3357 reg &= ~PCI_PMCSR_STATE_MASK; 3358 reg |= PCI_PMCSR_STATE_D0; 3359 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3360 pci_conf_write(sc->sc_pc, sc->sc_tag, 3361 sc->sc_pwrmgt_offs + 4, reg); 3362 3363 pci_conf_write(sc->sc_pc, sc->sc_tag, 3364 PCI_SOCKBASE, sc->sc_sockbase); 3365 pci_conf_write(sc->sc_pc, sc->sc_tag, 3366 PCI_BUSNUM, sc->sc_busnum); 3367 pccbb_chipinit(sc); 3368 /* setup memory and io space window for CB */ 3369 pccbb_winset(0x1000, sc, sc->sc_memt); 3370 pccbb_winset(0x04, sc, sc->sc_iot); 3371 } 3372 } 3373 3374 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3375 /* BIOS did not recover this register */ 3376 pci_conf_write (sc->sc_pc, sc->sc_tag, 3377 PCI_SOCKBASE, sc->sc_sockbase); 3378 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3379 /* BIOS did not recover this register */ 3380 pci_conf_write (sc->sc_pc, sc->sc_tag, 3381 PCI_BUSNUM, sc->sc_busnum); 3382 /* CSC Interrupt: Card detect interrupt on */ 3383 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3384 /* Card detect intr is turned on. */ 3385 reg |= CB_SOCKET_MASK_CD; 3386 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3387 /* reset interrupt */ 3388 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3389 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3390 3391 /* 3392 * check for card insertion or removal during suspend period. 3393 * XXX: the code can't cope with card swap (remove then 3394 * insert). how can we detect such situation? 3395 */ 3396 (void)pccbbintr(sc); 3397 3398 sc->sc_pil_intr_enable = 1; 3399 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3400 3401 /* ToDo: activate or wakeup child devices */ 3402 } 3403 } 3404
Indexes created Thu Sep 25 16:09:42 GMT 2025