pccbb.c revision 1.86
1 /* $NetBSD: pccbb.c,v 1.86 2003/01/01 00:10:23 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.86 2003/01/01 00:10:23 thorpej Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, NULL, NULL); 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 332 /* Ricoh chips */ 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 346 /* Toshiba products */ 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 348 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 350 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 356 /* Cirrus Logic products */ 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 362 /* sentinel, or Generic chip */ 363 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 364 }; 365 366 static int 367 cb_chipset(pci_id, flagp) 368 u_int32_t pci_id; 369 int *flagp; 370 { 371 const struct yenta_chipinfo *yc; 372 373 /* Loop over except the last default entry. */ 374 for (yc = yc_chipsets; yc < yc_chipsets + 375 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 376 if (pci_id == yc->yc_id) 377 break; 378 379 if (flagp != NULL) 380 *flagp = yc->yc_flags; 381 382 return (yc->yc_chiptype); 383 } 384 385 static void 386 pccbb_shutdown(void *arg) 387 { 388 struct pccbb_softc *sc = arg; 389 pcireg_t command; 390 391 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 392 393 /* 394 * turn off power 395 * 396 * XXX - do not turn off power if chipset is TI 113X because 397 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 398 */ 399 if (sc->sc_chipset != CB_TI113X) { 400 pccbb_power((cardbus_chipset_tag_t)sc, 401 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 402 } 403 404 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 405 0); 406 407 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 408 409 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 410 PCI_COMMAND_MASTER_ENABLE); 411 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 412 413 } 414 415 void 416 pccbbattach(parent, self, aux) 417 struct device *parent; 418 struct device *self; 419 void *aux; 420 { 421 struct pccbb_softc *sc = (void *)self; 422 struct pci_attach_args *pa = aux; 423 pci_chipset_tag_t pc = pa->pa_pc; 424 pcireg_t busreg, reg, sock_base; 425 bus_addr_t sockbase; 426 char devinfo[256]; 427 int flags; 428 int pwrmgt_offs; 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo); 433 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 434 #ifdef CBB_DEBUG 435 printf(" (chipflags %x)", flags); 436 #endif 437 printf("\n"); 438 439 TAILQ_INIT(&sc->sc_memwindow); 440 TAILQ_INIT(&sc->sc_iowindow); 441 442 #if rbus 443 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 444 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 445 446 #if 0 447 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 448 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 449 #endif 450 #endif /* rbus */ 451 452 sc->sc_base_memh = 0; 453 454 /* power management: set D0 state */ 455 sc->sc_pwrmgt_offs = 0; 456 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 457 &pwrmgt_offs, 0)) { 458 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 459 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 460 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 461 reg &= ~PCI_PMCSR_STATE_MASK; 462 reg |= PCI_PMCSR_STATE_D0; 463 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 464 pci_conf_write(pc, pa->pa_tag, 465 pwrmgt_offs + PCI_PMCSR, reg); 466 } 467 468 sc->sc_pwrmgt_offs = pwrmgt_offs; 469 } 470 471 /* 472 * MAP socket registers and ExCA registers on memory-space 473 * When no valid address is set on socket base registers (on pci 474 * config space), get it not polite way. 475 */ 476 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 477 478 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 479 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 480 /* The address must be valid. */ 481 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 482 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 483 printf("%s: can't map socket base address 0x%x\n", 484 sc->sc_dev.dv_xname, sock_base); 485 /* 486 * I think it's funny: socket base registers must be 487 * mapped on memory space, but ... 488 */ 489 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 490 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 491 NULL)) { 492 printf("%s: can't map socket base address" 493 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 494 (unsigned long)sockbase); 495 /* give up... allocate reg space via rbus. */ 496 sc->sc_base_memh = 0; 497 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 498 } 499 } else { 500 DPRINTF(("%s: socket base address 0x%lx\n", 501 sc->sc_dev.dv_xname, sockbase)); 502 } 503 } 504 505 sc->sc_mem_start = 0; /* XXX */ 506 sc->sc_mem_end = 0xffffffff; /* XXX */ 507 508 /* 509 * When interrupt isn't routed correctly, give up probing cbb and do 510 * not kill pcic-compatible port. 511 */ 512 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 513 printf("%s: NOT USED because of unconfigured interrupt\n", 514 sc->sc_dev.dv_xname); 515 return; 516 } 517 518 /* 519 * When bus number isn't set correctly, give up using 32-bit CardBus 520 * mode. 521 */ 522 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 523 #if notyet 524 if (((busreg >> 8) & 0xff) == 0) { 525 printf("%s: CardBus support disabled because of unconfigured bus number\n", 526 sc->sc_dev.dv_xname); 527 flags |= PCCBB_PCMCIA_16BITONLY; 528 } 529 #endif 530 531 /* pccbb_machdep.c end */ 532 533 #if defined CBB_DEBUG 534 { 535 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 536 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 537 intrname[pa->pa_intrpin], pa->pa_intrline); 538 } 539 #endif 540 541 /* setup softc */ 542 sc->sc_pc = pc; 543 sc->sc_iot = pa->pa_iot; 544 sc->sc_memt = pa->pa_memt; 545 sc->sc_dmat = pa->pa_dmat; 546 sc->sc_tag = pa->pa_tag; 547 sc->sc_function = pa->pa_function; 548 sc->sc_sockbase = sock_base; 549 sc->sc_busnum = busreg; 550 551 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 552 553 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 554 555 shutdownhook_establish(pccbb_shutdown, sc); 556 557 /* Disable legacy register mapping. */ 558 switch (sc->sc_chipset) { 559 case CB_RX5C46X: /* fallthrough */ 560 #if 0 561 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 562 case CB_RX5C47X: 563 #endif 564 /* 565 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 566 * cannot be disabled by substituting 0 into PCI_LEGACY 567 * register. Ricoh CardBus bridges have special bits on Bridge 568 * control reg (addr 0x3e on PCI config space). 569 */ 570 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 571 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 572 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 573 break; 574 575 default: 576 /* XXX I don't know proper way to kill legacy I/O. */ 577 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 578 break; 579 } 580 581 config_defer(self, pccbb_pci_callback); 582 } 583 584 585 586 587 /* 588 * static void pccbb_pci_callback(struct device *self) 589 * 590 * The actual attach routine: get memory space for YENTA register 591 * space, setup YENTA register and route interrupt. 592 * 593 * This function should be deferred because this device may obtain 594 * memory space dynamically. This function must avoid obtaining 595 * memory area which has already kept for another device. 596 */ 597 static void 598 pccbb_pci_callback(self) 599 struct device *self; 600 { 601 struct pccbb_softc *sc = (void *)self; 602 pci_chipset_tag_t pc = sc->sc_pc; 603 pci_intr_handle_t ih; 604 const char *intrstr = NULL; 605 bus_addr_t sockbase; 606 struct cbslot_attach_args cba; 607 struct pcmciabus_attach_args paa; 608 struct cardslot_attach_args caa; 609 struct cardslot_softc *csc; 610 611 if (0 == sc->sc_base_memh) { 612 /* The socket registers aren't mapped correctly. */ 613 #if rbus 614 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 615 (sc->sc_chipset == CB_RX5C47X 616 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 617 0, &sockbase, &sc->sc_base_memh)) { 618 return; 619 } 620 sc->sc_base_memt = sc->sc_memt; 621 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 622 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 623 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 624 PCI_SOCKBASE))); 625 #else 626 sc->sc_base_memt = sc->sc_memt; 627 #if !defined CBB_PCI_BASE 628 #define CBB_PCI_BASE 0x20000000 629 #endif 630 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 631 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 632 /* cannot allocate memory space */ 633 return; 634 } 635 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 636 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 637 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 638 sc->sc_tag, PCI_SOCKBASE))); 639 sc->sc_sockbase = sockbase; 640 #endif 641 } 642 643 /* bus bridge initialization */ 644 pccbb_chipinit(sc); 645 646 /* clear data structure for child device interrupt handlers */ 647 LIST_INIT(&sc->sc_pil); 648 sc->sc_pil_intr_enable = 1; 649 650 /* Map and establish the interrupt. */ 651 if (pci_intr_map(&sc->sc_pa, &ih)) { 652 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 653 return; 654 } 655 intrstr = pci_intr_string(pc, ih); 656 657 /* 658 * XXX pccbbintr should be called under the priority lower 659 * than any other hard interrputs. 660 */ 661 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 662 663 if (sc->sc_ih == NULL) { 664 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 665 if (intrstr != NULL) { 666 printf(" at %s", intrstr); 667 } 668 printf("\n"); 669 return; 670 } 671 672 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 673 powerhook_establish(pccbb_powerhook, sc); 674 675 { 676 u_int32_t sockstat; 677 678 sockstat = bus_space_read_4(sc->sc_base_memt, 679 sc->sc_base_memh, CB_SOCKET_STAT); 680 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 681 sc->sc_flags |= CBB_CARDEXIST; 682 } 683 } 684 685 /* 686 * attach cardbus 687 */ 688 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 689 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 690 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 691 692 /* initialize cbslot_attach */ 693 cba.cba_busname = "cardbus"; 694 cba.cba_iot = sc->sc_iot; 695 cba.cba_memt = sc->sc_memt; 696 cba.cba_dmat = sc->sc_dmat; 697 cba.cba_bus = (busreg >> 8) & 0x0ff; 698 cba.cba_cc = (void *)sc; 699 cba.cba_cf = &pccbb_funcs; 700 cba.cba_intrline = sc->sc_pa.pa_intrline; 701 702 #if rbus 703 cba.cba_rbus_iot = sc->sc_rbus_iot; 704 cba.cba_rbus_memt = sc->sc_rbus_memt; 705 #endif 706 707 cba.cba_cacheline = PCI_CACHELINE(bhlc); 708 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 709 710 if (bootverbose) { 711 printf("%s: cacheline 0x%x lattimer 0x%x\n", 712 sc->sc_dev.dv_xname, cba.cba_cacheline, 713 cba.cba_lattimer); 714 printf("%s: bhlc 0x%x lscp 0x%x\n", 715 sc->sc_dev.dv_xname, bhlc, busreg); 716 } 717 #if defined SHOW_REGS 718 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 719 sc->sc_base_memh); 720 #endif 721 } 722 723 pccbb_pcmcia_attach_setup(sc, &paa); 724 caa.caa_cb_attach = NULL; 725 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 726 caa.caa_cb_attach = &cba; 727 } 728 caa.caa_16_attach = &paa; 729 caa.caa_ph = &sc->sc_pcmcia_h; 730 731 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 732 DPRINTF(("pccbbattach: found cardslot\n")); 733 sc->sc_csc = csc; 734 } 735 736 return; 737 } 738 739 740 741 742 743 /* 744 * static void pccbb_chipinit(struct pccbb_softc *sc) 745 * 746 * This function initialize YENTA chip registers listed below: 747 * 1) PCI command reg, 748 * 2) PCI and CardBus latency timer, 749 * 3) route PCI interrupt, 750 * 4) close all memory and io windows. 751 * 5) turn off bus power. 752 * 6) card detect interrupt on. 753 * 7) clear interrupt 754 */ 755 static void 756 pccbb_chipinit(sc) 757 struct pccbb_softc *sc; 758 { 759 pci_chipset_tag_t pc = sc->sc_pc; 760 pcitag_t tag = sc->sc_tag; 761 bus_space_tag_t bmt = sc->sc_base_memt; 762 bus_space_handle_t bmh = sc->sc_base_memh; 763 pcireg_t reg; 764 765 /* 766 * Set PCI command reg. 767 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 768 */ 769 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 770 /* I believe it is harmless. */ 771 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 772 PCI_COMMAND_MASTER_ENABLE); 773 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 774 775 /* 776 * Set CardBus latency timer. 777 */ 778 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 779 if (PCI_CB_LATENCY(reg) < 0x20) { 780 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 781 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 782 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 783 } 784 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 785 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 786 787 /* 788 * Set PCI latency timer. 789 */ 790 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 791 if (PCI_LATTIMER(reg) < 0x10) { 792 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 793 reg |= (0x10 << PCI_LATTIMER_SHIFT); 794 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 795 } 796 DPRINTF(("PCI latency timer 0x%x (%x)\n", 797 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 798 799 800 /* Route functional interrupts to PCI. */ 801 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 802 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 803 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 804 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 805 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 806 807 switch (sc->sc_chipset) { 808 case CB_TI113X: 809 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 810 /* This bit is shared, but may read as 0 on some chips, so set 811 it explicitly on both functions. */ 812 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 813 /* CSC intr enable */ 814 reg |= PCI113X_CBCTRL_PCI_CSC; 815 /* functional intr prohibit | prohibit ISA routing */ 816 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 817 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 818 break; 819 820 case CB_TI12XX: 821 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 822 reg |= PCI12XX_SYSCTRL_VCCPROT; 823 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 824 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 825 reg |= PCI12XX_CBCTRL_CSC; 826 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 827 break; 828 829 case CB_TOPIC95B: 830 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 831 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 832 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 833 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 834 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 835 sc->sc_dev.dv_xname, reg)); 836 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 837 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 838 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 839 DPRINTF(("0x%x\n", reg)); 840 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 841 break; 842 843 case CB_TOPIC97: 844 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 845 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 846 sc->sc_dev.dv_xname, reg)); 847 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 848 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 849 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 850 reg |= TOPIC97_SLOT_CTRL_PCIINT; 851 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 852 DPRINTF(("0x%x\n", reg)); 853 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 854 /* make sure to assert LV card support bits */ 855 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 856 0x800 + 0x3e, 857 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 858 0x800 + 0x3e) | 0x03); 859 break; 860 } 861 862 /* Close all memory and I/O windows. */ 863 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 864 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 865 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 866 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 867 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 868 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 869 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 870 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 871 872 /* reset 16-bit pcmcia bus */ 873 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 874 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 875 876 /* turn off power */ 877 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 878 879 /* CSC Interrupt: Card detect interrupt on */ 880 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 881 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 882 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 883 /* reset interrupt */ 884 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 885 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 886 } 887 888 889 890 891 /* 892 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 893 * struct pcmciabus_attach_args *paa) 894 * 895 * This function attaches 16-bit PCcard bus. 896 */ 897 STATIC void 898 pccbb_pcmcia_attach_setup(sc, paa) 899 struct pccbb_softc *sc; 900 struct pcmciabus_attach_args *paa; 901 { 902 struct pcic_handle *ph = &sc->sc_pcmcia_h; 903 #if rbus 904 rbus_tag_t rb; 905 #endif 906 907 /* initialize pcmcia part in pccbb_softc */ 908 ph->ph_parent = (struct device *)sc; 909 ph->sock = sc->sc_function; 910 ph->flags = 0; 911 ph->shutdown = 0; 912 ph->ih_irq = sc->sc_pa.pa_intrline; 913 ph->ph_bus_t = sc->sc_base_memt; 914 ph->ph_bus_h = sc->sc_base_memh; 915 ph->ph_read = pccbb_pcmcia_read; 916 ph->ph_write = pccbb_pcmcia_write; 917 sc->sc_pct = &pccbb_pcmcia_funcs; 918 919 /* 920 * We need to do a few things here: 921 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 922 * setting the IRQ numbers to 0. 923 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 924 * routing of CSC interrupts (e.g. card removal) to PCI while in 925 * PCMCIA mode. We just leave this set all the time. 926 * 3) Enable card insertion/removal interrupts in case the chip also 927 * needs that while in PCMCIA mode. 928 * 4) Clear any pending CSC interrupt. 929 */ 930 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 931 if (sc->sc_chipset == CB_TI113X) { 932 Pcic_write(ph, PCIC_CSC_INTR, 0); 933 } else { 934 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 935 Pcic_read(ph, PCIC_CSC); 936 } 937 938 /* initialize pcmcia bus attachment */ 939 paa->paa_busname = "pcmcia"; 940 paa->pct = sc->sc_pct; 941 paa->pch = ph; 942 paa->iobase = 0; /* I don't use them */ 943 paa->iosize = 0; 944 #if rbus 945 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 946 paa->iobase = rb->rb_start + rb->rb_offset; 947 paa->iosize = rb->rb_end - rb->rb_start; 948 #endif 949 950 return; 951 } 952 953 #if 0 954 STATIC void 955 pccbb_pcmcia_attach_card(ph) 956 struct pcic_handle *ph; 957 { 958 if (ph->flags & PCIC_FLAG_CARDP) { 959 panic("pccbb_pcmcia_attach_card: already attached"); 960 } 961 962 /* call the MI attach function */ 963 pcmcia_card_attach(ph->pcmcia); 964 965 ph->flags |= PCIC_FLAG_CARDP; 966 } 967 968 STATIC void 969 pccbb_pcmcia_detach_card(ph, flags) 970 struct pcic_handle *ph; 971 int flags; 972 { 973 if (!(ph->flags & PCIC_FLAG_CARDP)) { 974 panic("pccbb_pcmcia_detach_card: already detached"); 975 } 976 977 ph->flags &= ~PCIC_FLAG_CARDP; 978 979 /* call the MI detach function */ 980 pcmcia_card_detach(ph->pcmcia, flags); 981 } 982 #endif 983 984 /* 985 * int pccbbintr(arg) 986 * void *arg; 987 * This routine handles the interrupt from Yenta PCI-CardBus bridge 988 * itself. 989 */ 990 int 991 pccbbintr(arg) 992 void *arg; 993 { 994 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 995 u_int32_t sockevent, sockstate; 996 bus_space_tag_t memt = sc->sc_base_memt; 997 bus_space_handle_t memh = sc->sc_base_memh; 998 struct pcic_handle *ph = &sc->sc_pcmcia_h; 999 1000 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1001 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1002 Pcic_read(ph, PCIC_CSC); 1003 1004 if (sockevent == 0) { 1005 /* This intr is not for me: it may be for my child devices. */ 1006 if (sc->sc_pil_intr_enable) { 1007 return pccbbintr_function(sc); 1008 } else { 1009 return 0; 1010 } 1011 } 1012 1013 if (sockevent & CB_SOCKET_EVENT_CD) { 1014 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1015 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 1016 /* A card should be removed. */ 1017 if (sc->sc_flags & CBB_CARDEXIST) { 1018 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1019 sockevent)); 1020 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1021 sc->sc_flags &= ~CBB_CARDEXIST; 1022 if (sc->sc_csc->sc_status & 1023 CARDSLOT_STATUS_CARD_16) { 1024 #if 0 1025 struct pcic_handle *ph = 1026 &sc->sc_pcmcia_h; 1027 1028 pcmcia_card_deactivate(ph->pcmcia); 1029 pccbb_pcmcia_socket_disable(ph); 1030 pccbb_pcmcia_detach_card(ph, 1031 DETACH_FORCE); 1032 #endif 1033 cardslot_event_throw(sc->sc_csc, 1034 CARDSLOT_EVENT_REMOVAL_16); 1035 } else if (sc->sc_csc->sc_status & 1036 CARDSLOT_STATUS_CARD_CB) { 1037 /* Cardbus intr removed */ 1038 cardslot_event_throw(sc->sc_csc, 1039 CARDSLOT_EVENT_REMOVAL_CB); 1040 } 1041 } else if (sc->sc_flags & CBB_INSERTING) { 1042 sc->sc_flags &= ~CBB_INSERTING; 1043 callout_stop(&sc->sc_insert_ch); 1044 } 1045 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1046 /* 1047 * The pccbbintr may called from powerdown hook when 1048 * the system resumed, to detect the card 1049 * insertion/removal during suspension. 1050 */ 1051 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1052 if (sc->sc_flags & CBB_INSERTING) { 1053 callout_stop(&sc->sc_insert_ch); 1054 } 1055 callout_reset(&sc->sc_insert_ch, hz / 5, 1056 pci113x_insert, sc); 1057 sc->sc_flags |= CBB_INSERTING; 1058 } 1059 } 1060 1061 return (1); 1062 } 1063 1064 /* 1065 * static int pccbbintr_function(struct pccbb_softc *sc) 1066 * 1067 * This function calls each interrupt handler registered at the 1068 * bridge. The interrupt handlers are called in registered order. 1069 */ 1070 static int 1071 pccbbintr_function(sc) 1072 struct pccbb_softc *sc; 1073 { 1074 int retval = 0, val; 1075 struct pccbb_intrhand_list *pil; 1076 int s, splchanged; 1077 1078 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1079 pil = LIST_NEXT(pil, pil_next)) { 1080 /* 1081 * XXX priority change. gross. I use if-else 1082 * sentense instead of switch-case sentense because of 1083 * avoiding duplicate case value error. More than one 1084 * IPL_XXX use same value. It depends on 1085 * implimentation. 1086 */ 1087 splchanged = 1; 1088 if (pil->pil_level == IPL_SERIAL) { 1089 s = splserial(); 1090 } else if (pil->pil_level == IPL_HIGH) { 1091 s = splhigh(); 1092 } else if (pil->pil_level == IPL_CLOCK) { 1093 s = splclock(); 1094 } else if (pil->pil_level == IPL_AUDIO) { 1095 s = splaudio(); 1096 } else if (pil->pil_level == IPL_IMP) { 1097 s = splvm(); /* XXX */ 1098 } else if (pil->pil_level == IPL_TTY) { 1099 s = spltty(); 1100 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1101 s = splsoftserial(); 1102 } else if (pil->pil_level == IPL_NET) { 1103 s = splnet(); 1104 } else { 1105 splchanged = 0; 1106 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1107 } 1108 1109 val = (*pil->pil_func)(pil->pil_arg); 1110 1111 if (splchanged != 0) { 1112 splx(s); 1113 } 1114 1115 retval = retval == 1 ? 1 : 1116 retval == 0 ? val : val != 0 ? val : retval; 1117 } 1118 1119 return retval; 1120 } 1121 1122 static void 1123 pci113x_insert(arg) 1124 void *arg; 1125 { 1126 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1127 u_int32_t sockevent, sockstate; 1128 1129 if (!(sc->sc_flags & CBB_INSERTING)) { 1130 /* We add a card only under inserting state. */ 1131 return; 1132 } 1133 sc->sc_flags &= ~CBB_INSERTING; 1134 1135 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1136 CB_SOCKET_EVENT); 1137 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1138 CB_SOCKET_STAT); 1139 1140 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1141 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1142 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1143 sc->sc_flags |= CBB_CARDEXIST; 1144 /* call pccard interrupt handler here */ 1145 if (sockstate & CB_SOCKET_STAT_16BIT) { 1146 /* 16-bit card found */ 1147 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1148 cardslot_event_throw(sc->sc_csc, 1149 CARDSLOT_EVENT_INSERTION_16); 1150 } else if (sockstate & CB_SOCKET_STAT_CB) { 1151 /* cardbus card found */ 1152 /* cardbus_attach_card(sc->sc_csc); */ 1153 cardslot_event_throw(sc->sc_csc, 1154 CARDSLOT_EVENT_INSERTION_CB); 1155 } else { 1156 /* who are you? */ 1157 } 1158 } else { 1159 callout_reset(&sc->sc_insert_ch, hz / 10, 1160 pci113x_insert, sc); 1161 } 1162 } 1163 1164 #define PCCBB_PCMCIA_OFFSET 0x800 1165 static u_int8_t 1166 pccbb_pcmcia_read(ph, reg) 1167 struct pcic_handle *ph; 1168 int reg; 1169 { 1170 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1171 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1172 1173 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1174 PCCBB_PCMCIA_OFFSET + reg); 1175 } 1176 1177 static void 1178 pccbb_pcmcia_write(ph, reg, val) 1179 struct pcic_handle *ph; 1180 int reg; 1181 u_int8_t val; 1182 { 1183 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1184 val); 1185 1186 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1187 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1188 } 1189 1190 /* 1191 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1192 */ 1193 STATIC int 1194 pccbb_ctrl(ct, command) 1195 cardbus_chipset_tag_t ct; 1196 int command; 1197 { 1198 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1199 1200 switch (command) { 1201 case CARDBUS_CD: 1202 if (2 == pccbb_detect_card(sc)) { 1203 int retval = 0; 1204 int status = cb_detect_voltage(sc); 1205 if (PCCARD_VCC_5V & status) { 1206 retval |= CARDBUS_5V_CARD; 1207 } 1208 if (PCCARD_VCC_3V & status) { 1209 retval |= CARDBUS_3V_CARD; 1210 } 1211 if (PCCARD_VCC_XV & status) { 1212 retval |= CARDBUS_XV_CARD; 1213 } 1214 if (PCCARD_VCC_YV & status) { 1215 retval |= CARDBUS_YV_CARD; 1216 } 1217 return retval; 1218 } else { 1219 return 0; 1220 } 1221 break; 1222 case CARDBUS_RESET: 1223 return cb_reset(sc); 1224 break; 1225 case CARDBUS_IO_ENABLE: /* fallthrough */ 1226 case CARDBUS_IO_DISABLE: /* fallthrough */ 1227 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1228 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1229 case CARDBUS_BM_ENABLE: /* fallthrough */ 1230 case CARDBUS_BM_DISABLE: /* fallthrough */ 1231 /* XXX: I think we don't need to call this function below. */ 1232 return pccbb_cardenable(sc, command); 1233 break; 1234 } 1235 1236 return 0; 1237 } 1238 1239 /* 1240 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1241 * This function returns true when it succeeds and returns false when 1242 * it fails. 1243 */ 1244 STATIC int 1245 pccbb_power(ct, command) 1246 cardbus_chipset_tag_t ct; 1247 int command; 1248 { 1249 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1250 1251 u_int32_t status, sock_ctrl, reg_ctrl; 1252 bus_space_tag_t memt = sc->sc_base_memt; 1253 bus_space_handle_t memh = sc->sc_base_memh; 1254 1255 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1258 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1259 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1260 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1261 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1262 "UNKNOWN", 1263 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1264 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1265 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1266 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1267 "UNKNOWN", command)); 1268 1269 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1270 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1271 1272 switch (command & CARDBUS_VCCMASK) { 1273 case CARDBUS_VCC_UC: 1274 break; 1275 case CARDBUS_VCC_5V: 1276 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1277 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1278 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1279 } else { 1280 printf("%s: BAD voltage request: no 5 V card\n", 1281 sc->sc_dev.dv_xname); 1282 } 1283 break; 1284 case CARDBUS_VCC_3V: 1285 if (CB_SOCKET_STAT_3VCARD & status) { 1286 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1287 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1288 } else { 1289 printf("%s: BAD voltage request: no 3.3 V card\n", 1290 sc->sc_dev.dv_xname); 1291 } 1292 break; 1293 case CARDBUS_VCC_0V: 1294 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1295 break; 1296 default: 1297 return 0; /* power NEVER changed */ 1298 break; 1299 } 1300 1301 switch (command & CARDBUS_VPPMASK) { 1302 case CARDBUS_VPP_UC: 1303 break; 1304 case CARDBUS_VPP_0V: 1305 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1306 break; 1307 case CARDBUS_VPP_VCC: 1308 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1309 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1310 break; 1311 case CARDBUS_VPP_12V: 1312 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1313 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1314 break; 1315 } 1316 1317 #if 0 1318 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1319 #endif 1320 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1321 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1322 1323 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1324 printf 1325 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1326 sc->sc_dev.dv_xname, sock_ctrl, status); 1327 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1328 (command & CARDBUS_VCCMASK) == 1329 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1330 CARDBUS_VCCMASK) == 1331 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1332 CARDBUS_VCCMASK) == 1333 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1334 CARDBUS_VCCMASK) == 1335 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1336 CARDBUS_VCCMASK) == 1337 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1338 CARDBUS_VCCMASK) == 1339 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1340 (command & CARDBUS_VPPMASK) == 1341 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1342 CARDBUS_VPPMASK) == 1343 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1344 CARDBUS_VPPMASK) == 1345 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1346 CARDBUS_VPPMASK) == 1347 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1348 #if 0 1349 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1350 u_int32_t force = 1351 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1352 /* Reset Bad Vcc request */ 1353 force &= ~CB_SOCKET_FORCE_BADVCC; 1354 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1355 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1356 CB_SOCKET_STAT)); 1357 return 1; 1358 } 1359 #endif 1360 return 0; 1361 } 1362 1363 if (sc->sc_chipset == CB_TOPIC97) { 1364 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1365 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1366 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1367 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1368 else 1369 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1370 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1371 } 1372 1373 /* 1374 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1375 * time is 20 ms, some PC-Card bridge requires longer duration. 1376 */ 1377 #if 0 /* XXX called on interrupt context */ 1378 DELAY_MS(300, sc); 1379 #else 1380 delay(300 * 1000); 1381 #endif 1382 1383 return 1; /* power changed correctly */ 1384 } 1385 1386 #if defined CB_PCMCIA_POLL 1387 struct cb_poll_str { 1388 void *arg; 1389 int (*func) __P((void *)); 1390 int level; 1391 pccard_chipset_tag_t ct; 1392 int count; 1393 struct callout poll_ch; 1394 }; 1395 1396 static struct cb_poll_str cb_poll[10]; 1397 static int cb_poll_n = 0; 1398 1399 static void cb_pcmcia_poll __P((void *arg)); 1400 1401 static void 1402 cb_pcmcia_poll(arg) 1403 void *arg; 1404 { 1405 struct cb_poll_str *poll = arg; 1406 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1407 struct pccbb_softc *sc = psc->cpc_parent; 1408 int s; 1409 u_int32_t spsr; /* socket present-state reg */ 1410 1411 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1412 switch (poll->level) { 1413 case IPL_NET: 1414 s = splnet(); 1415 break; 1416 case IPL_BIO: 1417 s = splbio(); 1418 break; 1419 case IPL_TTY: /* fallthrough */ 1420 default: 1421 s = spltty(); 1422 break; 1423 } 1424 1425 spsr = 1426 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1427 CB_SOCKET_STAT); 1428 1429 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1430 if (!(spsr & 0x40)) { /* CINT low */ 1431 #else 1432 if (1) { 1433 #endif 1434 if ((*poll->func) (poll->arg) == 1) { 1435 ++poll->count; 1436 printf("intr: reported from poller, 0x%x\n", spsr); 1437 #if defined LEVEL2 1438 } else { 1439 printf("intr: miss! 0x%x\n", spsr); 1440 #endif 1441 } 1442 } 1443 splx(s); 1444 } 1445 #endif /* defined CB_PCMCIA_POLL */ 1446 1447 /* 1448 * static int pccbb_detect_card(struct pccbb_softc *sc) 1449 * return value: 0 if no card exists. 1450 * 1 if 16-bit card exists. 1451 * 2 if cardbus card exists. 1452 */ 1453 static int 1454 pccbb_detect_card(sc) 1455 struct pccbb_softc *sc; 1456 { 1457 bus_space_handle_t base_memh = sc->sc_base_memh; 1458 bus_space_tag_t base_memt = sc->sc_base_memt; 1459 u_int32_t sockstat = 1460 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1461 int retval = 0; 1462 1463 /* CD1 and CD2 asserted */ 1464 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1465 /* card must be present */ 1466 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1467 /* NOTACARD DEASSERTED */ 1468 if (CB_SOCKET_STAT_CB & sockstat) { 1469 /* CardBus mode */ 1470 retval = 2; 1471 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1472 /* 16-bit mode */ 1473 retval = 1; 1474 } 1475 } 1476 } 1477 return retval; 1478 } 1479 1480 /* 1481 * STATIC int cb_reset(struct pccbb_softc *sc) 1482 * This function resets CardBus card. 1483 */ 1484 STATIC int 1485 cb_reset(sc) 1486 struct pccbb_softc *sc; 1487 { 1488 /* 1489 * Reset Assert at least 20 ms 1490 * Some machines request longer duration. 1491 */ 1492 int reset_duration = 1493 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1494 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1495 1496 /* Reset bit Assert (bit 6 at 0x3E) */ 1497 bcr |= CB_BCR_RESET_ENABLE; 1498 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1499 DELAY_MS(reset_duration, sc); 1500 1501 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1502 /* Reset bit Deassert (bit 6 at 0x3E) */ 1503 bcr &= ~CB_BCR_RESET_ENABLE; 1504 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1505 DELAY_MS(reset_duration, sc); 1506 } 1507 /* No card found on the slot. Keep Reset. */ 1508 return 1; 1509 } 1510 1511 /* 1512 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1513 * This function detect card Voltage. 1514 */ 1515 STATIC int 1516 cb_detect_voltage(sc) 1517 struct pccbb_softc *sc; 1518 { 1519 u_int32_t psr; /* socket present-state reg */ 1520 bus_space_tag_t iot = sc->sc_base_memt; 1521 bus_space_handle_t ioh = sc->sc_base_memh; 1522 int vol = PCCARD_VCC_UKN; /* set 0 */ 1523 1524 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1525 1526 if (0x400u & psr) { 1527 vol |= PCCARD_VCC_5V; 1528 } 1529 if (0x800u & psr) { 1530 vol |= PCCARD_VCC_3V; 1531 } 1532 1533 return vol; 1534 } 1535 1536 STATIC int 1537 cbbprint(aux, pcic) 1538 void *aux; 1539 const char *pcic; 1540 { 1541 /* 1542 struct cbslot_attach_args *cba = aux; 1543 1544 if (cba->cba_slot >= 0) { 1545 aprint_normal(" slot %d", cba->cba_slot); 1546 } 1547 */ 1548 return UNCONF; 1549 } 1550 1551 /* 1552 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1553 * This function enables and disables the card 1554 */ 1555 STATIC int 1556 pccbb_cardenable(sc, function) 1557 struct pccbb_softc *sc; 1558 int function; 1559 { 1560 u_int32_t command = 1561 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1562 1563 DPRINTF(("pccbb_cardenable:")); 1564 switch (function) { 1565 case CARDBUS_IO_ENABLE: 1566 command |= PCI_COMMAND_IO_ENABLE; 1567 break; 1568 case CARDBUS_IO_DISABLE: 1569 command &= ~PCI_COMMAND_IO_ENABLE; 1570 break; 1571 case CARDBUS_MEM_ENABLE: 1572 command |= PCI_COMMAND_MEM_ENABLE; 1573 break; 1574 case CARDBUS_MEM_DISABLE: 1575 command &= ~PCI_COMMAND_MEM_ENABLE; 1576 break; 1577 case CARDBUS_BM_ENABLE: 1578 command |= PCI_COMMAND_MASTER_ENABLE; 1579 break; 1580 case CARDBUS_BM_DISABLE: 1581 command &= ~PCI_COMMAND_MASTER_ENABLE; 1582 break; 1583 default: 1584 return 0; 1585 } 1586 1587 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1588 DPRINTF((" command reg 0x%x\n", command)); 1589 return 1; 1590 } 1591 1592 #if !rbus 1593 /* 1594 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1595 */ 1596 static int 1597 pccbb_io_open(ct, win, start, end) 1598 cardbus_chipset_tag_t ct; 1599 int win; 1600 u_int32_t start, end; 1601 { 1602 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1603 int basereg; 1604 int limitreg; 1605 1606 if ((win < 0) || (win > 2)) { 1607 #if defined DIAGNOSTIC 1608 printf("cardbus_io_open: window out of range %d\n", win); 1609 #endif 1610 return 0; 1611 } 1612 1613 basereg = win * 8 + 0x2c; 1614 limitreg = win * 8 + 0x30; 1615 1616 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1617 start, basereg, end, limitreg)); 1618 1619 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1620 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1621 return 1; 1622 } 1623 1624 /* 1625 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1626 */ 1627 static int 1628 pccbb_io_close(ct, win) 1629 cardbus_chipset_tag_t ct; 1630 int win; 1631 { 1632 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1633 int basereg; 1634 int limitreg; 1635 1636 if ((win < 0) || (win > 2)) { 1637 #if defined DIAGNOSTIC 1638 printf("cardbus_io_close: window out of range %d\n", win); 1639 #endif 1640 return 0; 1641 } 1642 1643 basereg = win * 8 + 0x2c; 1644 limitreg = win * 8 + 0x30; 1645 1646 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1647 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1648 return 1; 1649 } 1650 1651 /* 1652 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1653 */ 1654 static int 1655 pccbb_mem_open(ct, win, start, end) 1656 cardbus_chipset_tag_t ct; 1657 int win; 1658 u_int32_t start, end; 1659 { 1660 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1661 int basereg; 1662 int limitreg; 1663 1664 if ((win < 0) || (win > 2)) { 1665 #if defined DIAGNOSTIC 1666 printf("cardbus_mem_open: window out of range %d\n", win); 1667 #endif 1668 return 0; 1669 } 1670 1671 basereg = win * 8 + 0x1c; 1672 limitreg = win * 8 + 0x20; 1673 1674 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1675 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1676 return 1; 1677 } 1678 1679 /* 1680 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1681 */ 1682 static int 1683 pccbb_mem_close(ct, win) 1684 cardbus_chipset_tag_t ct; 1685 int win; 1686 { 1687 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1688 int basereg; 1689 int limitreg; 1690 1691 if ((win < 0) || (win > 2)) { 1692 #if defined DIAGNOSTIC 1693 printf("cardbus_mem_close: window out of range %d\n", win); 1694 #endif 1695 return 0; 1696 } 1697 1698 basereg = win * 8 + 0x1c; 1699 limitreg = win * 8 + 0x20; 1700 1701 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1702 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1703 return 1; 1704 } 1705 #endif 1706 1707 /* 1708 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1709 * int irq, 1710 * int level, 1711 * int (* func) __P((void *)), 1712 * void *arg) 1713 * 1714 * This function registers an interrupt handler at the bridge, in 1715 * order not to call the interrupt handlers of child devices when 1716 * a card-deletion interrupt occurs. 1717 * 1718 * The arguments irq and level are not used. 1719 */ 1720 static void * 1721 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1722 cardbus_chipset_tag_t ct; 1723 int irq, level; 1724 int (*func) __P((void *)); 1725 void *arg; 1726 { 1727 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1728 1729 return pccbb_intr_establish(sc, irq, level, func, arg); 1730 } 1731 1732 1733 /* 1734 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1735 * void *ih) 1736 * 1737 * This function removes an interrupt handler pointed by ih. 1738 */ 1739 static void 1740 pccbb_cb_intr_disestablish(ct, ih) 1741 cardbus_chipset_tag_t ct; 1742 void *ih; 1743 { 1744 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1745 1746 pccbb_intr_disestablish(sc, ih); 1747 } 1748 1749 1750 void 1751 pccbb_intr_route(sc) 1752 struct pccbb_softc *sc; 1753 { 1754 pcireg_t reg; 1755 1756 /* initialize bridge intr routing */ 1757 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1758 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1759 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1760 1761 switch (sc->sc_chipset) { 1762 case CB_TI113X: 1763 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1764 /* functional intr enabled */ 1765 reg |= PCI113X_CBCTRL_PCI_INTR; 1766 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1767 break; 1768 default: 1769 break; 1770 } 1771 } 1772 1773 /* 1774 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1775 * int irq, 1776 * int level, 1777 * int (* func) __P((void *)), 1778 * void *arg) 1779 * 1780 * This function registers an interrupt handler at the bridge, in 1781 * order not to call the interrupt handlers of child devices when 1782 * a card-deletion interrupt occurs. 1783 * 1784 * The arguments irq is not used because pccbb selects intr vector. 1785 */ 1786 static void * 1787 pccbb_intr_establish(sc, irq, level, func, arg) 1788 struct pccbb_softc *sc; 1789 int irq, level; 1790 int (*func) __P((void *)); 1791 void *arg; 1792 { 1793 struct pccbb_intrhand_list *pil, *newpil; 1794 1795 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1796 1797 if (LIST_EMPTY(&sc->sc_pil)) { 1798 pccbb_intr_route(sc); 1799 } 1800 1801 /* 1802 * Allocate a room for interrupt handler structure. 1803 */ 1804 if (NULL == (newpil = 1805 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1806 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1807 return NULL; 1808 } 1809 1810 newpil->pil_func = func; 1811 newpil->pil_arg = arg; 1812 newpil->pil_level = level; 1813 1814 if (LIST_EMPTY(&sc->sc_pil)) { 1815 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1816 } else { 1817 for (pil = LIST_FIRST(&sc->sc_pil); 1818 LIST_NEXT(pil, pil_next) != NULL; 1819 pil = LIST_NEXT(pil, pil_next)); 1820 LIST_INSERT_AFTER(pil, newpil, pil_next); 1821 } 1822 1823 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1824 LIST_FIRST(&sc->sc_pil))); 1825 1826 return newpil; 1827 } 1828 1829 /* 1830 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1831 * void *ih) 1832 * 1833 * This function removes an interrupt handler pointed by ih. ih 1834 * should be the value returned by cardbus_intr_establish() or 1835 * NULL. 1836 * 1837 * When ih is NULL, this function will do nothing. 1838 */ 1839 static void 1840 pccbb_intr_disestablish(sc, ih) 1841 struct pccbb_softc *sc; 1842 void *ih; 1843 { 1844 struct pccbb_intrhand_list *pil; 1845 pcireg_t reg; 1846 1847 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1848 LIST_FIRST(&sc->sc_pil))); 1849 1850 if (ih == NULL) { 1851 /* intr handler is not set */ 1852 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1853 return; 1854 } 1855 1856 #ifdef DIAGNOSTIC 1857 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1858 pil = LIST_NEXT(pil, pil_next)) { 1859 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1860 if (pil == ih) { 1861 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1862 break; 1863 } 1864 } 1865 if (pil == NULL) { 1866 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1867 sc->sc_dev.dv_xname, ih); 1868 } 1869 #endif 1870 1871 pil = (struct pccbb_intrhand_list *)ih; 1872 LIST_REMOVE(pil, pil_next); 1873 free(pil, M_DEVBUF); 1874 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1875 1876 if (LIST_EMPTY(&sc->sc_pil)) { 1877 /* No interrupt handlers */ 1878 1879 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1880 1881 /* stop routing PCI intr */ 1882 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1883 reg |= CB_BCR_INTR_IREQ_ENABLE; 1884 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1885 1886 switch (sc->sc_chipset) { 1887 case CB_TI113X: 1888 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1889 /* functional intr disabled */ 1890 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1891 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1892 break; 1893 default: 1894 break; 1895 } 1896 } 1897 } 1898 1899 #if defined SHOW_REGS 1900 static void 1901 cb_show_regs(pc, tag, memt, memh) 1902 pci_chipset_tag_t pc; 1903 pcitag_t tag; 1904 bus_space_tag_t memt; 1905 bus_space_handle_t memh; 1906 { 1907 int i; 1908 printf("PCI config regs:"); 1909 for (i = 0; i < 0x50; i += 4) { 1910 if (i % 16 == 0) { 1911 printf("\n 0x%02x:", i); 1912 } 1913 printf(" %08x", pci_conf_read(pc, tag, i)); 1914 } 1915 for (i = 0x80; i < 0xb0; i += 4) { 1916 if (i % 16 == 0) { 1917 printf("\n 0x%02x:", i); 1918 } 1919 printf(" %08x", pci_conf_read(pc, tag, i)); 1920 } 1921 1922 if (memh == 0) { 1923 printf("\n"); 1924 return; 1925 } 1926 1927 printf("\nsocket regs:"); 1928 for (i = 0; i <= 0x10; i += 0x04) { 1929 printf(" %08x", bus_space_read_4(memt, memh, i)); 1930 } 1931 printf("\nExCA regs:"); 1932 for (i = 0; i < 0x08; ++i) { 1933 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1934 } 1935 printf("\n"); 1936 return; 1937 } 1938 #endif 1939 1940 /* 1941 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1942 * int busno, int devno, int function) 1943 * This is the function to make a tag to access config space of 1944 * a CardBus Card. It works same as pci_conf_read. 1945 */ 1946 static cardbustag_t 1947 pccbb_make_tag(cc, busno, devno, function) 1948 cardbus_chipset_tag_t cc; 1949 int busno, devno, function; 1950 { 1951 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1952 1953 return pci_make_tag(sc->sc_pc, busno, devno, function); 1954 } 1955 1956 static void 1957 pccbb_free_tag(cc, tag) 1958 cardbus_chipset_tag_t cc; 1959 cardbustag_t tag; 1960 { 1961 } 1962 1963 /* 1964 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1965 * cardbustag_t tag, int offset) 1966 * This is the function to read the config space of a CardBus Card. 1967 * It works same as pci_conf_read. 1968 */ 1969 static cardbusreg_t 1970 pccbb_conf_read(cc, tag, offset) 1971 cardbus_chipset_tag_t cc; 1972 cardbustag_t tag; 1973 int offset; /* register offset */ 1974 { 1975 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1976 1977 return pci_conf_read(sc->sc_pc, tag, offset); 1978 } 1979 1980 /* 1981 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1982 * int offs, cardbusreg_t val) 1983 * This is the function to write the config space of a CardBus Card. 1984 * It works same as pci_conf_write. 1985 */ 1986 static void 1987 pccbb_conf_write(cc, tag, reg, val) 1988 cardbus_chipset_tag_t cc; 1989 cardbustag_t tag; 1990 int reg; /* register offset */ 1991 cardbusreg_t val; 1992 { 1993 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1994 1995 pci_conf_write(sc->sc_pc, tag, reg, val); 1996 } 1997 1998 #if 0 1999 STATIC int 2000 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2001 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2002 int speed, int flags, 2003 bus_space_handle_t * iohp) 2004 #endif 2005 /* 2006 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2007 * bus_addr_t start, bus_size_t size, 2008 * bus_size_t align, 2009 * struct pcmcia_io_handle *pcihp 2010 * 2011 * This function only allocates I/O region for pccard. This function 2012 * never maps the allocated region to pccard I/O area. 2013 * 2014 * XXX: The interface of this function is not very good, I believe. 2015 */ 2016 STATIC int 2017 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2018 pcmcia_chipset_handle_t pch; 2019 bus_addr_t start; /* start address */ 2020 bus_size_t size; 2021 bus_size_t align; 2022 struct pcmcia_io_handle *pcihp; 2023 { 2024 struct pcic_handle *ph = (struct pcic_handle *)pch; 2025 bus_addr_t ioaddr; 2026 int flags = 0; 2027 bus_space_tag_t iot; 2028 bus_space_handle_t ioh; 2029 bus_addr_t mask; 2030 #if rbus 2031 rbus_tag_t rb; 2032 #endif 2033 if (align == 0) { 2034 align = size; /* XXX: funny??? */ 2035 } 2036 2037 if (start != 0) { 2038 /* XXX: assume all card decode lower 10 bits by its hardware */ 2039 mask = 0x3ff; 2040 /* enforce to use only masked address */ 2041 start &= mask; 2042 } else { 2043 /* 2044 * calculate mask: 2045 * 1. get the most significant bit of size (call it msb). 2046 * 2. compare msb with the value of size. 2047 * 3. if size is larger, shift msb left once. 2048 * 4. obtain mask value to decrement msb. 2049 */ 2050 bus_size_t size_tmp = size; 2051 int shifts = 0; 2052 2053 mask = 1; 2054 while (size_tmp) { 2055 ++shifts; 2056 size_tmp >>= 1; 2057 } 2058 mask = (1 << shifts); 2059 if (mask < size) { 2060 mask <<= 1; 2061 } 2062 --mask; 2063 } 2064 2065 /* 2066 * Allocate some arbitrary I/O space. 2067 */ 2068 2069 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2070 2071 #if rbus 2072 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2073 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2074 return 1; 2075 } 2076 DPRINTF(("pccbb_pcmcia_io_alloc alloc port %lx+%lx\n", 2077 (u_long) ioaddr, (u_long) size)); 2078 #else 2079 if (start) { 2080 ioaddr = start; 2081 if (bus_space_map(iot, start, size, 0, &ioh)) { 2082 return 1; 2083 } 2084 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2085 (u_long) ioaddr, (u_long) size)); 2086 } else { 2087 flags |= PCMCIA_IO_ALLOCATED; 2088 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2089 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2090 size, align, 0, 0, &ioaddr, &ioh)) { 2091 /* No room be able to be get. */ 2092 return 1; 2093 } 2094 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2095 (u_long) ioaddr, (u_long) size)); 2096 } 2097 #endif 2098 2099 pcihp->iot = iot; 2100 pcihp->ioh = ioh; 2101 pcihp->addr = ioaddr; 2102 pcihp->size = size; 2103 pcihp->flags = flags; 2104 2105 return 0; 2106 } 2107 2108 /* 2109 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2110 * struct pcmcia_io_handle *pcihp) 2111 * 2112 * This function only frees I/O region for pccard. 2113 * 2114 * XXX: The interface of this function is not very good, I believe. 2115 */ 2116 void 2117 pccbb_pcmcia_io_free(pch, pcihp) 2118 pcmcia_chipset_handle_t pch; 2119 struct pcmcia_io_handle *pcihp; 2120 { 2121 #if !rbus 2122 bus_space_tag_t iot = pcihp->iot; 2123 #endif 2124 bus_space_handle_t ioh = pcihp->ioh; 2125 bus_size_t size = pcihp->size; 2126 2127 #if rbus 2128 struct pccbb_softc *sc = 2129 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2130 rbus_tag_t rb = sc->sc_rbus_iot; 2131 2132 rbus_space_free(rb, ioh, size, NULL); 2133 #else 2134 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2135 bus_space_free(iot, ioh, size); 2136 else 2137 bus_space_unmap(iot, ioh, size); 2138 #endif 2139 } 2140 2141 /* 2142 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2143 * bus_addr_t offset, bus_size_t size, 2144 * struct pcmcia_io_handle *pcihp, 2145 * int *windowp) 2146 * 2147 * This function maps the allocated I/O region to pccard. This function 2148 * never allocates any I/O region for pccard I/O area. I don't 2149 * understand why the original authors of pcmciabus separated alloc and 2150 * map. I believe the two must be unite. 2151 * 2152 * XXX: no wait timing control? 2153 */ 2154 int 2155 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2156 pcmcia_chipset_handle_t pch; 2157 int width; 2158 bus_addr_t offset; 2159 bus_size_t size; 2160 struct pcmcia_io_handle *pcihp; 2161 int *windowp; 2162 { 2163 struct pcic_handle *ph = (struct pcic_handle *)pch; 2164 bus_addr_t ioaddr = pcihp->addr + offset; 2165 int i, win; 2166 #if defined CBB_DEBUG 2167 static char *width_names[] = { "dynamic", "io8", "io16" }; 2168 #endif 2169 2170 /* Sanity check I/O handle. */ 2171 2172 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2173 panic("pccbb_pcmcia_io_map iot is bogus"); 2174 } 2175 2176 /* XXX Sanity check offset/size. */ 2177 2178 win = -1; 2179 for (i = 0; i < PCIC_IO_WINS; i++) { 2180 if ((ph->ioalloc & (1 << i)) == 0) { 2181 win = i; 2182 ph->ioalloc |= (1 << i); 2183 break; 2184 } 2185 } 2186 2187 if (win == -1) { 2188 return 1; 2189 } 2190 2191 *windowp = win; 2192 2193 /* XXX this is pretty gross */ 2194 2195 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2196 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2197 2198 /* XXX wtf is this doing here? */ 2199 2200 #if 0 2201 printf(" port 0x%lx", (u_long) ioaddr); 2202 if (size > 1) { 2203 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2204 } 2205 #endif 2206 2207 ph->io[win].addr = ioaddr; 2208 ph->io[win].size = size; 2209 ph->io[win].width = width; 2210 2211 /* actual dirty register-value changing in the function below. */ 2212 pccbb_pcmcia_do_io_map(ph, win); 2213 2214 return 0; 2215 } 2216 2217 /* 2218 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2219 * 2220 * This function changes register-value to map I/O region for pccard. 2221 */ 2222 static void 2223 pccbb_pcmcia_do_io_map(ph, win) 2224 struct pcic_handle *ph; 2225 int win; 2226 { 2227 static u_int8_t pcic_iowidth[3] = { 2228 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2229 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2230 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2231 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2232 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2233 }; 2234 2235 #define PCIC_SIA_START_LOW 0 2236 #define PCIC_SIA_START_HIGH 1 2237 #define PCIC_SIA_STOP_LOW 2 2238 #define PCIC_SIA_STOP_HIGH 3 2239 2240 int regbase_win = 0x8 + win * 0x04; 2241 u_int8_t ioctl, enable; 2242 2243 DPRINTF( 2244 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2245 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2246 ph->io[win].width * 8)); 2247 2248 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2249 ph->io[win].addr & 0xff); 2250 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2251 (ph->io[win].addr >> 8) & 0xff); 2252 2253 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2254 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2255 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2256 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2257 2258 ioctl = Pcic_read(ph, PCIC_IOCTL); 2259 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2260 switch (win) { 2261 case 0: 2262 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2263 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2264 PCIC_IOCTL_IO0_DATASIZE_MASK); 2265 ioctl |= pcic_iowidth[ph->io[win].width]; 2266 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2267 break; 2268 case 1: 2269 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2270 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2271 PCIC_IOCTL_IO1_DATASIZE_MASK); 2272 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2273 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2274 break; 2275 } 2276 Pcic_write(ph, PCIC_IOCTL, ioctl); 2277 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2278 #if defined CBB_DEBUG 2279 { 2280 u_int8_t start_low = 2281 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2282 u_int8_t start_high = 2283 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2284 u_int8_t stop_low = 2285 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2286 u_int8_t stop_high = 2287 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2288 printf 2289 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2290 start_low, start_high, stop_low, stop_high, ioctl, enable); 2291 } 2292 #endif 2293 } 2294 2295 /* 2296 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2297 * 2298 * This function unmaps I/O region. No return value. 2299 */ 2300 STATIC void 2301 pccbb_pcmcia_io_unmap(pch, win) 2302 pcmcia_chipset_handle_t pch; 2303 int win; 2304 { 2305 struct pcic_handle *ph = (struct pcic_handle *)pch; 2306 int reg; 2307 2308 if (win >= PCIC_IO_WINS || win < 0) { 2309 panic("pccbb_pcmcia_io_unmap: window out of range"); 2310 } 2311 2312 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2313 switch (win) { 2314 case 0: 2315 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2316 break; 2317 case 1: 2318 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2319 break; 2320 } 2321 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2322 2323 ph->ioalloc &= ~(1 << win); 2324 } 2325 2326 /* 2327 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2328 * 2329 * This function enables the card. All information is stored in 2330 * the first argument, pcmcia_chipset_handle_t. 2331 */ 2332 static void 2333 pccbb_pcmcia_wait_ready(ph) 2334 struct pcic_handle *ph; 2335 { 2336 int i; 2337 2338 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2339 Pcic_read(ph, PCIC_IF_STATUS))); 2340 2341 for (i = 0; i < 2000; i++) { 2342 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2343 return; 2344 } 2345 DELAY_MS(2, ph->ph_parent); 2346 #ifdef CBB_DEBUG 2347 if ((i > 1000) && (i % 25 == 24)) 2348 printf("."); 2349 #endif 2350 } 2351 2352 #ifdef DIAGNOSTIC 2353 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2354 Pcic_read(ph, PCIC_IF_STATUS)); 2355 #endif 2356 } 2357 2358 /* 2359 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2360 * 2361 * This function enables the card. All information is stored in 2362 * the first argument, pcmcia_chipset_handle_t. 2363 */ 2364 STATIC void 2365 pccbb_pcmcia_socket_enable(pch) 2366 pcmcia_chipset_handle_t pch; 2367 { 2368 struct pcic_handle *ph = (struct pcic_handle *)pch; 2369 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2370 int cardtype, win; 2371 u_int8_t power, intr; 2372 pcireg_t spsr; 2373 int voltage; 2374 2375 /* this bit is mostly stolen from pcic_attach_card */ 2376 2377 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2378 2379 /* get card Vcc info */ 2380 2381 spsr = 2382 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2383 CB_SOCKET_STAT); 2384 if (spsr & CB_SOCKET_STAT_5VCARD) { 2385 DPRINTF(("5V card\n")); 2386 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2387 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2388 DPRINTF(("3V card\n")); 2389 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2390 } else { 2391 printf("?V card, 0x%x\n", spsr); /* XXX */ 2392 return; 2393 } 2394 2395 /* disable socket: negate output enable bit and power off */ 2396 2397 power = 0; 2398 Pcic_write(ph, PCIC_PWRCTL, power); 2399 2400 /* power down the socket to reset it, clear the card reset pin */ 2401 2402 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2403 2404 /* 2405 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2406 * we are changing Vcc (Toff). 2407 */ 2408 /* delay(300*1000); too much */ 2409 2410 /* assert reset bit */ 2411 intr = Pcic_read(ph, PCIC_INTR); 2412 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2413 Pcic_write(ph, PCIC_INTR, intr); 2414 2415 /* power up the socket and output enable */ 2416 power = Pcic_read(ph, PCIC_PWRCTL); 2417 power |= PCIC_PWRCTL_OE; 2418 Pcic_write(ph, PCIC_PWRCTL, power); 2419 pccbb_power(sc, voltage); 2420 2421 /* 2422 * hold RESET at least 20 ms: the spec says only 10 us is 2423 * enough, but TI1130 requires at least 20 ms. 2424 */ 2425 #if 0 /* XXX called on interrupt context */ 2426 DELAY_MS(20, sc); 2427 #else 2428 delay(20 * 1000); 2429 #endif 2430 2431 /* clear the reset flag */ 2432 2433 intr |= PCIC_INTR_RESET; 2434 Pcic_write(ph, PCIC_INTR, intr); 2435 2436 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2437 2438 #if 0 /* XXX called on interrupt context */ 2439 DELAY_MS(20, sc); 2440 #else 2441 delay(20 * 1000); 2442 #endif 2443 2444 /* wait for the chip to finish initializing */ 2445 2446 pccbb_pcmcia_wait_ready(ph); 2447 2448 /* zero out the address windows */ 2449 2450 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2451 2452 /* set the card type */ 2453 2454 cardtype = pcmcia_card_gettype(ph->pcmcia); 2455 2456 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2457 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2458 Pcic_write(ph, PCIC_INTR, intr); 2459 2460 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2461 ph->ph_parent->dv_xname, ph->sock, 2462 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2463 2464 /* reinstall all the memory and io mappings */ 2465 2466 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2467 if (ph->memalloc & (1 << win)) { 2468 pccbb_pcmcia_do_mem_map(ph, win); 2469 } 2470 } 2471 2472 for (win = 0; win < PCIC_IO_WINS; ++win) { 2473 if (ph->ioalloc & (1 << win)) { 2474 pccbb_pcmcia_do_io_map(ph, win); 2475 } 2476 } 2477 } 2478 2479 /* 2480 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2481 * 2482 * This function disables the card. All information is stored in 2483 * the first argument, pcmcia_chipset_handle_t. 2484 */ 2485 STATIC void 2486 pccbb_pcmcia_socket_disable(pch) 2487 pcmcia_chipset_handle_t pch; 2488 { 2489 struct pcic_handle *ph = (struct pcic_handle *)pch; 2490 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2491 u_int8_t power, intr; 2492 2493 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2494 2495 /* reset signal asserting... */ 2496 2497 intr = Pcic_read(ph, PCIC_INTR); 2498 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2499 Pcic_write(ph, PCIC_INTR, intr); 2500 delay(2 * 1000); 2501 2502 /* power down the socket */ 2503 power = Pcic_read(ph, PCIC_PWRCTL); 2504 power &= ~PCIC_PWRCTL_OE; 2505 Pcic_write(ph, PCIC_PWRCTL, power); 2506 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2507 /* 2508 * wait 300ms until power fails (Tpf). 2509 */ 2510 #if 0 /* XXX called on interrupt context */ 2511 DELAY_MS(300, sc); 2512 #else 2513 delay(300 * 1000); 2514 #endif 2515 } 2516 2517 /* 2518 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2519 * 2520 * This function detects whether a card is in the slot or not. 2521 * If a card is inserted, return 1. Otherwise, return 0. 2522 */ 2523 STATIC int 2524 pccbb_pcmcia_card_detect(pch) 2525 pcmcia_chipset_handle_t pch; 2526 { 2527 struct pcic_handle *ph = (struct pcic_handle *)pch; 2528 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2529 2530 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2531 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2532 } 2533 2534 #if 0 2535 STATIC int 2536 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2537 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2538 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2539 #endif 2540 /* 2541 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2542 * bus_size_t size, 2543 * struct pcmcia_mem_handle *pcmhp) 2544 * 2545 * This function only allocates memory region for pccard. This 2546 * function never maps the allocated region to pccard memory area. 2547 * 2548 * XXX: Why the argument of start address is not in? 2549 */ 2550 STATIC int 2551 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2552 pcmcia_chipset_handle_t pch; 2553 bus_size_t size; 2554 struct pcmcia_mem_handle *pcmhp; 2555 { 2556 struct pcic_handle *ph = (struct pcic_handle *)pch; 2557 bus_space_handle_t memh; 2558 bus_addr_t addr; 2559 bus_size_t sizepg; 2560 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2561 #if rbus 2562 rbus_tag_t rb; 2563 #endif 2564 2565 /* out of sc->memh, allocate as many pages as necessary */ 2566 2567 /* convert size to PCIC pages */ 2568 /* 2569 * This is not enough; when the requested region is on the page 2570 * boundaries, this may calculate wrong result. 2571 */ 2572 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2573 #if 0 2574 if (sizepg > PCIC_MAX_MEM_PAGES) { 2575 return 1; 2576 } 2577 #endif 2578 2579 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2580 return 1; 2581 } 2582 2583 addr = 0; /* XXX gcc -Wuninitialized */ 2584 2585 #if rbus 2586 rb = sc->sc_rbus_memt; 2587 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2588 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2589 &addr, &memh)) { 2590 return 1; 2591 } 2592 #else 2593 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2594 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2595 0, /* boundary */ 2596 0, /* flags */ 2597 &addr, &memh)) { 2598 return 1; 2599 } 2600 #endif 2601 2602 DPRINTF( 2603 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2604 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2605 2606 pcmhp->memt = sc->sc_memt; 2607 pcmhp->memh = memh; 2608 pcmhp->addr = addr; 2609 pcmhp->size = size; 2610 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2611 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2612 pcmhp->mhandle = 0; 2613 /* No offset??? Funny. */ 2614 2615 return 0; 2616 } 2617 2618 /* 2619 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2620 * struct pcmcia_mem_handle *pcmhp) 2621 * 2622 * This function release the memory space allocated by the function 2623 * pccbb_pcmcia_mem_alloc(). 2624 */ 2625 STATIC void 2626 pccbb_pcmcia_mem_free(pch, pcmhp) 2627 pcmcia_chipset_handle_t pch; 2628 struct pcmcia_mem_handle *pcmhp; 2629 { 2630 #if rbus 2631 struct pcic_handle *ph = (struct pcic_handle *)pch; 2632 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2633 2634 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2635 #else 2636 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2637 #endif 2638 } 2639 2640 /* 2641 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2642 * 2643 * This function release the memory space allocated by the function 2644 * pccbb_pcmcia_mem_alloc(). 2645 */ 2646 STATIC void 2647 pccbb_pcmcia_do_mem_map(ph, win) 2648 struct pcic_handle *ph; 2649 int win; 2650 { 2651 int regbase_win; 2652 bus_addr_t phys_addr; 2653 bus_addr_t phys_end; 2654 2655 #define PCIC_SMM_START_LOW 0 2656 #define PCIC_SMM_START_HIGH 1 2657 #define PCIC_SMM_STOP_LOW 2 2658 #define PCIC_SMM_STOP_HIGH 3 2659 #define PCIC_CMA_LOW 4 2660 #define PCIC_CMA_HIGH 5 2661 2662 u_int8_t start_low, start_high = 0; 2663 u_int8_t stop_low, stop_high; 2664 u_int8_t off_low, off_high; 2665 u_int8_t mem_window; 2666 int reg; 2667 2668 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2669 int mem8 = 2670 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2671 || (kind == PCMCIA_MEM_ATTR); 2672 2673 regbase_win = 0x10 + win * 0x08; 2674 2675 phys_addr = ph->mem[win].addr; 2676 phys_end = phys_addr + ph->mem[win].size; 2677 2678 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2679 phys_addr, phys_end, ph->mem[win].offset)); 2680 2681 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2682 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2683 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2684 2685 /* bit 19:12 */ 2686 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2687 /* bit 23:20 and bit 7 on */ 2688 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2689 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2690 /* bit 31:24, for 32-bit address */ 2691 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2692 2693 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2694 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2695 2696 if (((struct pccbb_softc *)ph-> 2697 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2698 Pcic_write(ph, 0x40 + win, mem_window); 2699 } 2700 2701 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2702 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2703 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2704 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2705 2706 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2707 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2708 2709 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2710 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2711 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2712 | ((kind == PCMCIA_MEM_ATTR) ? 2713 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2714 2715 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2716 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2717 2718 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2719 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2720 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2721 2722 #if defined CBB_DEBUG 2723 { 2724 int r1, r2, r3, r4, r5, r6, r7 = 0; 2725 2726 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2727 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2728 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2729 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2730 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2731 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2732 if (((struct pccbb_softc *)(ph-> 2733 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2734 r7 = Pcic_read(ph, 0x40 + win); 2735 } 2736 2737 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2738 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2739 if (((struct pccbb_softc *)(ph-> 2740 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2741 DPRINTF((" %02x", r7)); 2742 } 2743 DPRINTF(("\n")); 2744 } 2745 #endif 2746 } 2747 2748 /* 2749 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2750 * bus_addr_t card_addr, bus_size_t size, 2751 * struct pcmcia_mem_handle *pcmhp, 2752 * bus_addr_t *offsetp, int *windowp) 2753 * 2754 * This function maps memory space allocated by the function 2755 * pccbb_pcmcia_mem_alloc(). 2756 */ 2757 STATIC int 2758 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2759 pcmcia_chipset_handle_t pch; 2760 int kind; 2761 bus_addr_t card_addr; 2762 bus_size_t size; 2763 struct pcmcia_mem_handle *pcmhp; 2764 bus_addr_t *offsetp; 2765 int *windowp; 2766 { 2767 struct pcic_handle *ph = (struct pcic_handle *)pch; 2768 bus_addr_t busaddr; 2769 long card_offset; 2770 int win; 2771 2772 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2773 if ((ph->memalloc & (1 << win)) == 0) { 2774 ph->memalloc |= (1 << win); 2775 break; 2776 } 2777 } 2778 2779 if (win == PCIC_MEM_WINS) { 2780 return 1; 2781 } 2782 2783 *windowp = win; 2784 2785 /* XXX this is pretty gross */ 2786 2787 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2788 panic("pccbb_pcmcia_mem_map memt is bogus"); 2789 } 2790 2791 busaddr = pcmhp->addr; 2792 2793 /* 2794 * compute the address offset to the pcmcia address space for the 2795 * pcic. this is intentionally signed. The masks and shifts below 2796 * will cause TRT to happen in the pcic registers. Deal with making 2797 * sure the address is aligned, and return the alignment offset. 2798 */ 2799 2800 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2801 card_addr -= *offsetp; 2802 2803 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2804 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2805 (u_long) card_addr)); 2806 2807 /* 2808 * include the offset in the size, and decrement size by one, since 2809 * the hw wants start/stop 2810 */ 2811 size += *offsetp - 1; 2812 2813 card_offset = (((long)card_addr) - ((long)busaddr)); 2814 2815 ph->mem[win].addr = busaddr; 2816 ph->mem[win].size = size; 2817 ph->mem[win].offset = card_offset; 2818 ph->mem[win].kind = kind; 2819 2820 pccbb_pcmcia_do_mem_map(ph, win); 2821 2822 return 0; 2823 } 2824 2825 /* 2826 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2827 * int window) 2828 * 2829 * This function unmaps memory space which mapped by the function 2830 * pccbb_pcmcia_mem_map(). 2831 */ 2832 STATIC void 2833 pccbb_pcmcia_mem_unmap(pch, window) 2834 pcmcia_chipset_handle_t pch; 2835 int window; 2836 { 2837 struct pcic_handle *ph = (struct pcic_handle *)pch; 2838 int reg; 2839 2840 if (window >= PCIC_MEM_WINS) { 2841 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2842 } 2843 2844 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2845 reg &= ~(1 << window); 2846 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2847 2848 ph->memalloc &= ~(1 << window); 2849 } 2850 2851 #if defined PCCBB_PCMCIA_POLL 2852 struct pccbb_poll_str { 2853 void *arg; 2854 int (*func) __P((void *)); 2855 int level; 2856 struct pcic_handle *ph; 2857 int count; 2858 int num; 2859 struct callout poll_ch; 2860 }; 2861 2862 static struct pccbb_poll_str pccbb_poll[10]; 2863 static int pccbb_poll_n = 0; 2864 2865 static void pccbb_pcmcia_poll __P((void *arg)); 2866 2867 static void 2868 pccbb_pcmcia_poll(arg) 2869 void *arg; 2870 { 2871 struct pccbb_poll_str *poll = arg; 2872 struct pcic_handle *ph = poll->ph; 2873 struct pccbb_softc *sc = ph->sc; 2874 int s; 2875 u_int32_t spsr; /* socket present-state reg */ 2876 2877 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2878 switch (poll->level) { 2879 case IPL_NET: 2880 s = splnet(); 2881 break; 2882 case IPL_BIO: 2883 s = splbio(); 2884 break; 2885 case IPL_TTY: /* fallthrough */ 2886 default: 2887 s = spltty(); 2888 break; 2889 } 2890 2891 spsr = 2892 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2893 CB_SOCKET_STAT); 2894 2895 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2896 if (!(spsr & 0x40)) /* CINT low */ 2897 #else 2898 if (1) 2899 #endif 2900 { 2901 if ((*poll->func) (poll->arg) > 0) { 2902 ++poll->count; 2903 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2904 #if defined LEVEL2 2905 } else { 2906 printf("intr: miss! 0x%x\n", spsr); 2907 #endif 2908 } 2909 } 2910 splx(s); 2911 } 2912 #endif /* defined CB_PCMCIA_POLL */ 2913 2914 /* 2915 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2916 * struct pcmcia_function *pf, 2917 * int ipl, 2918 * int (*func)(void *), 2919 * void *arg); 2920 * 2921 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2922 */ 2923 STATIC void * 2924 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2925 pcmcia_chipset_handle_t pch; 2926 struct pcmcia_function *pf; 2927 int ipl; 2928 int (*func) __P((void *)); 2929 void *arg; 2930 { 2931 struct pcic_handle *ph = (struct pcic_handle *)pch; 2932 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2933 2934 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2935 /* what should I do? */ 2936 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2937 DPRINTF( 2938 ("%s does not provide edge nor pulse interrupt\n", 2939 sc->sc_dev.dv_xname)); 2940 return NULL; 2941 } 2942 /* 2943 * XXX Noooooo! The interrupt flag must set properly!! 2944 * dumb pcmcia driver!! 2945 */ 2946 } 2947 2948 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2949 } 2950 2951 /* 2952 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2953 * void *ih) 2954 * 2955 * This function disables PC-Card interrupt. 2956 */ 2957 STATIC void 2958 pccbb_pcmcia_intr_disestablish(pch, ih) 2959 pcmcia_chipset_handle_t pch; 2960 void *ih; 2961 { 2962 struct pcic_handle *ph = (struct pcic_handle *)pch; 2963 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2964 2965 pccbb_intr_disestablish(sc, ih); 2966 } 2967 2968 #if rbus 2969 /* 2970 * static int 2971 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2972 * bus_addr_t addr, bus_size_t size, 2973 * bus_addr_t mask, bus_size_t align, 2974 * int flags, bus_addr_t *addrp; 2975 * bus_space_handle_t *bshp) 2976 * 2977 * This function allocates a portion of memory or io space for 2978 * clients. This function is called from CardBus card drivers. 2979 */ 2980 static int 2981 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2982 cardbus_chipset_tag_t ct; 2983 rbus_tag_t rb; 2984 bus_addr_t addr; 2985 bus_size_t size; 2986 bus_addr_t mask; 2987 bus_size_t align; 2988 int flags; 2989 bus_addr_t *addrp; 2990 bus_space_handle_t *bshp; 2991 { 2992 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2993 2994 DPRINTF( 2995 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2996 addr, size, mask, align)); 2997 2998 if (align == 0) { 2999 align = size; 3000 } 3001 3002 if (rb->rb_bt == sc->sc_memt) { 3003 if (align < 16) { 3004 return 1; 3005 } 3006 /* 3007 * XXX: align more than 0x1000 to avoid overwrapping 3008 * memory windows for two or more devices. 0x1000 3009 * means memory window's granularity. 3010 * 3011 * Two or more devices should be able to share same 3012 * memory window region. However, overrapping memory 3013 * window is not good because some devices, such as 3014 * 3Com 3C575[BC], have a broken address decoder and 3015 * intrude other's memory region. 3016 */ 3017 if (align < 0x1000) { 3018 align = 0x1000; 3019 } 3020 } else if (rb->rb_bt == sc->sc_iot) { 3021 if (align < 4) { 3022 return 1; 3023 } 3024 /* XXX: hack for avoiding ISA image */ 3025 if (mask < 0x0100) { 3026 mask = 0x3ff; 3027 addr = 0x300; 3028 } 3029 3030 } else { 3031 DPRINTF( 3032 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 3033 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 3034 return 1; 3035 /* XXX: panic here? */ 3036 } 3037 3038 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3039 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3040 return 1; 3041 } 3042 3043 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3044 3045 return 0; 3046 } 3047 3048 /* 3049 * static int 3050 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3051 * bus_space_handle_t *bshp, bus_size_t size); 3052 * 3053 * This function is called from CardBus card drivers. 3054 */ 3055 static int 3056 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3057 cardbus_chipset_tag_t ct; 3058 rbus_tag_t rb; 3059 bus_space_handle_t bsh; 3060 bus_size_t size; 3061 { 3062 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3063 bus_space_tag_t bt = rb->rb_bt; 3064 3065 pccbb_close_win(sc, bt, bsh, size); 3066 3067 if (bt == sc->sc_memt) { 3068 } else if (bt == sc->sc_iot) { 3069 } else { 3070 return 1; 3071 /* XXX: panic here? */ 3072 } 3073 3074 return rbus_space_free(rb, bsh, size, NULL); 3075 } 3076 #endif /* rbus */ 3077 3078 #if rbus 3079 3080 static int 3081 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3082 struct pccbb_softc *sc; 3083 bus_space_tag_t bst; 3084 bus_addr_t addr; 3085 bus_size_t size; 3086 bus_space_handle_t bsh; 3087 int flags; 3088 { 3089 struct pccbb_win_chain_head *head; 3090 bus_addr_t align; 3091 3092 head = &sc->sc_iowindow; 3093 align = 0x04; 3094 if (sc->sc_memt == bst) { 3095 head = &sc->sc_memwindow; 3096 align = 0x1000; 3097 DPRINTF(("using memory window, %x %x %x\n\n", 3098 sc->sc_iot, sc->sc_memt, bst)); 3099 } 3100 3101 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3102 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3103 sc->sc_dev.dv_xname, 3104 (head == &sc->sc_memwindow) ? "mem" : "io"); 3105 } 3106 pccbb_winset(align, sc, bst); 3107 3108 return 0; 3109 } 3110 3111 static int 3112 pccbb_close_win(sc, bst, bsh, size) 3113 struct pccbb_softc *sc; 3114 bus_space_tag_t bst; 3115 bus_space_handle_t bsh; 3116 bus_size_t size; 3117 { 3118 struct pccbb_win_chain_head *head; 3119 bus_addr_t align; 3120 3121 head = &sc->sc_iowindow; 3122 align = 0x04; 3123 if (sc->sc_memt == bst) { 3124 head = &sc->sc_memwindow; 3125 align = 0x1000; 3126 } 3127 3128 if (pccbb_winlist_delete(head, bsh, size)) { 3129 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3130 sc->sc_dev.dv_xname, 3131 (head == &sc->sc_memwindow) ? "mem" : "io"); 3132 } 3133 pccbb_winset(align, sc, bst); 3134 3135 return 0; 3136 } 3137 3138 static int 3139 pccbb_winlist_insert(head, start, size, bsh, flags) 3140 struct pccbb_win_chain_head *head; 3141 bus_addr_t start; 3142 bus_size_t size; 3143 bus_space_handle_t bsh; 3144 int flags; 3145 { 3146 struct pccbb_win_chain *chainp, *elem; 3147 3148 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3149 M_NOWAIT)) == NULL) 3150 return (1); /* fail */ 3151 3152 elem->wc_start = start; 3153 elem->wc_end = start + (size - 1); 3154 elem->wc_handle = bsh; 3155 elem->wc_flags = flags; 3156 3157 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3158 chainp = TAILQ_NEXT(chainp, wc_list)) { 3159 if (chainp->wc_end < start) 3160 continue; 3161 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3162 return (0); 3163 } 3164 3165 TAILQ_INSERT_TAIL(head, elem, wc_list); 3166 return (0); 3167 } 3168 3169 static int 3170 pccbb_winlist_delete(head, bsh, size) 3171 struct pccbb_win_chain_head *head; 3172 bus_space_handle_t bsh; 3173 bus_size_t size; 3174 { 3175 struct pccbb_win_chain *chainp; 3176 3177 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3178 chainp = TAILQ_NEXT(chainp, wc_list)) { 3179 if (chainp->wc_handle != bsh) 3180 continue; 3181 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3182 printf("pccbb_winlist_delete: window 0x%lx size " 3183 "inconsistent: 0x%lx, 0x%lx\n", 3184 (unsigned long)chainp->wc_start, 3185 (unsigned long)(chainp->wc_end - chainp->wc_start), 3186 (unsigned long)(size - 1)); 3187 return 1; 3188 } 3189 3190 TAILQ_REMOVE(head, chainp, wc_list); 3191 free(chainp, M_DEVBUF); 3192 3193 return 0; 3194 } 3195 3196 return 1; /* fail: no candidate to remove */ 3197 } 3198 3199 static void 3200 pccbb_winset(align, sc, bst) 3201 bus_addr_t align; 3202 struct pccbb_softc *sc; 3203 bus_space_tag_t bst; 3204 { 3205 pci_chipset_tag_t pc; 3206 pcitag_t tag; 3207 bus_addr_t mask = ~(align - 1); 3208 struct { 3209 cardbusreg_t win_start; 3210 cardbusreg_t win_limit; 3211 int win_flags; 3212 } win[2]; 3213 struct pccbb_win_chain *chainp; 3214 int offs; 3215 3216 win[0].win_start = win[1].win_start = 0xffffffff; 3217 win[0].win_limit = win[1].win_limit = 0; 3218 win[0].win_flags = win[1].win_flags = 0; 3219 3220 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3221 offs = 0x2c; 3222 if (sc->sc_memt == bst) { 3223 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3224 offs = 0x1c; 3225 } 3226 3227 if (chainp != NULL) { 3228 win[0].win_start = chainp->wc_start & mask; 3229 win[0].win_limit = chainp->wc_end & mask; 3230 win[0].win_flags = chainp->wc_flags; 3231 chainp = TAILQ_NEXT(chainp, wc_list); 3232 } 3233 3234 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3235 if (win[1].win_start == 0xffffffff) { 3236 /* window 1 is not used */ 3237 if ((win[0].win_flags == chainp->wc_flags) && 3238 (win[0].win_limit + align >= 3239 (chainp->wc_start & mask))) { 3240 /* concatenate */ 3241 win[0].win_limit = chainp->wc_end & mask; 3242 } else { 3243 /* make new window */ 3244 win[1].win_start = chainp->wc_start & mask; 3245 win[1].win_limit = chainp->wc_end & mask; 3246 win[1].win_flags = chainp->wc_flags; 3247 } 3248 continue; 3249 } 3250 3251 /* Both windows are engaged. */ 3252 if (win[0].win_flags == win[1].win_flags) { 3253 /* same flags */ 3254 if (win[0].win_flags == chainp->wc_flags) { 3255 if (win[1].win_start - (win[0].win_limit + 3256 align) < 3257 (chainp->wc_start & mask) - 3258 ((chainp->wc_end & mask) + align)) { 3259 /* 3260 * merge window 0 and 1, and set win1 3261 * to chainp 3262 */ 3263 win[0].win_limit = win[1].win_limit; 3264 win[1].win_start = 3265 chainp->wc_start & mask; 3266 win[1].win_limit = 3267 chainp->wc_end & mask; 3268 } else { 3269 win[1].win_limit = 3270 chainp->wc_end & mask; 3271 } 3272 } else { 3273 /* different flags */ 3274 3275 /* concatenate win0 and win1 */ 3276 win[0].win_limit = win[1].win_limit; 3277 /* allocate win[1] to new space */ 3278 win[1].win_start = chainp->wc_start & mask; 3279 win[1].win_limit = chainp->wc_end & mask; 3280 win[1].win_flags = chainp->wc_flags; 3281 } 3282 } else { 3283 /* the flags of win[0] and win[1] is different */ 3284 if (win[0].win_flags == chainp->wc_flags) { 3285 win[0].win_limit = chainp->wc_end & mask; 3286 /* 3287 * XXX this creates overlapping windows, so 3288 * what should the poor bridge do if one is 3289 * cachable, and the other is not? 3290 */ 3291 printf("%s: overlapping windows\n", 3292 sc->sc_dev.dv_xname); 3293 } else { 3294 win[1].win_limit = chainp->wc_end & mask; 3295 } 3296 } 3297 } 3298 3299 pc = sc->sc_pc; 3300 tag = sc->sc_tag; 3301 pci_conf_write(pc, tag, offs, win[0].win_start); 3302 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3303 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3304 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3305 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3306 pci_conf_read(pc, tag, offs), 3307 pci_conf_read(pc, tag, offs + 4) + align, 3308 pci_conf_read(pc, tag, offs + 8), 3309 pci_conf_read(pc, tag, offs + 12) + align)); 3310 3311 if (bst == sc->sc_memt) { 3312 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3313 3314 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3315 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3316 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3317 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3318 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3319 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3320 } 3321 } 3322 3323 #endif /* rbus */ 3324 3325 static void 3326 pccbb_powerhook(why, arg) 3327 int why; 3328 void *arg; 3329 { 3330 struct pccbb_softc *sc = arg; 3331 pcireg_t reg; 3332 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3333 bus_space_handle_t base_memh = sc->sc_base_memh; 3334 3335 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3336 3337 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3338 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3339 if (sc->sc_pil_intr_enable) { 3340 (void)pccbbintr_function(sc); 3341 } 3342 sc->sc_pil_intr_enable = 0; 3343 3344 /* ToDo: deactivate or suspend child devices */ 3345 3346 } 3347 3348 if (why == PWR_RESUME) { 3349 if (sc->sc_pwrmgt_offs != 0) { 3350 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3351 sc->sc_pwrmgt_offs + 4); 3352 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3353 reg & 0x100) { 3354 /* powrstate != D0 */ 3355 3356 printf("%s going back to D0 mode\n", 3357 sc->sc_dev.dv_xname); 3358 reg &= ~PCI_PMCSR_STATE_MASK; 3359 reg |= PCI_PMCSR_STATE_D0; 3360 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3361 pci_conf_write(sc->sc_pc, sc->sc_tag, 3362 sc->sc_pwrmgt_offs + 4, reg); 3363 3364 pci_conf_write(sc->sc_pc, sc->sc_tag, 3365 PCI_SOCKBASE, sc->sc_sockbase); 3366 pci_conf_write(sc->sc_pc, sc->sc_tag, 3367 PCI_BUSNUM, sc->sc_busnum); 3368 pccbb_chipinit(sc); 3369 /* setup memory and io space window for CB */ 3370 pccbb_winset(0x1000, sc, sc->sc_memt); 3371 pccbb_winset(0x04, sc, sc->sc_iot); 3372 } 3373 } 3374 3375 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3376 /* BIOS did not recover this register */ 3377 pci_conf_write (sc->sc_pc, sc->sc_tag, 3378 PCI_SOCKBASE, sc->sc_sockbase); 3379 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3380 /* BIOS did not recover this register */ 3381 pci_conf_write (sc->sc_pc, sc->sc_tag, 3382 PCI_BUSNUM, sc->sc_busnum); 3383 /* CSC Interrupt: Card detect interrupt on */ 3384 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3385 /* Card detect intr is turned on. */ 3386 reg |= CB_SOCKET_MASK_CD; 3387 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3388 /* reset interrupt */ 3389 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3390 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3391 3392 /* 3393 * check for card insertion or removal during suspend period. 3394 * XXX: the code can't cope with card swap (remove then 3395 * insert). how can we detect such situation? 3396 */ 3397 (void)pccbbintr(sc); 3398 3399 sc->sc_pil_intr_enable = 1; 3400 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3401 3402 /* ToDo: activate or wakeup child devices */ 3403 } 3404 } 3405
Indexes created Fri Sep 26 20:09:58 GMT 2025