pccbb.c revision 1.87
1 /* $NetBSD: pccbb.c,v 1.87 2003/01/20 02:29:56 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.87 2003/01/20 02:29:56 simonb Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, NULL, NULL); 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 332 /* Ricoh chips */ 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 346 /* Toshiba products */ 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 348 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 350 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 356 /* Cirrus Logic products */ 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 362 /* sentinel, or Generic chip */ 363 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 364 }; 365 366 static int 367 cb_chipset(pci_id, flagp) 368 u_int32_t pci_id; 369 int *flagp; 370 { 371 const struct yenta_chipinfo *yc; 372 373 /* Loop over except the last default entry. */ 374 for (yc = yc_chipsets; yc < yc_chipsets + 375 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 376 if (pci_id == yc->yc_id) 377 break; 378 379 if (flagp != NULL) 380 *flagp = yc->yc_flags; 381 382 return (yc->yc_chiptype); 383 } 384 385 static void 386 pccbb_shutdown(void *arg) 387 { 388 struct pccbb_softc *sc = arg; 389 pcireg_t command; 390 391 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 392 393 /* 394 * turn off power 395 * 396 * XXX - do not turn off power if chipset is TI 113X because 397 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 398 */ 399 if (sc->sc_chipset != CB_TI113X) { 400 pccbb_power((cardbus_chipset_tag_t)sc, 401 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 402 } 403 404 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 405 0); 406 407 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 408 409 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 410 PCI_COMMAND_MASTER_ENABLE); 411 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 412 413 } 414 415 void 416 pccbbattach(parent, self, aux) 417 struct device *parent; 418 struct device *self; 419 void *aux; 420 { 421 struct pccbb_softc *sc = (void *)self; 422 struct pci_attach_args *pa = aux; 423 pci_chipset_tag_t pc = pa->pa_pc; 424 pcireg_t busreg, reg, sock_base; 425 bus_addr_t sockbase; 426 char devinfo[256]; 427 int flags; 428 int pwrmgt_offs; 429 430 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 431 432 pci_devinfo(pa->pa_id, 0, 0, devinfo); 433 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 434 #ifdef CBB_DEBUG 435 printf(" (chipflags %x)", flags); 436 #endif 437 printf("\n"); 438 439 TAILQ_INIT(&sc->sc_memwindow); 440 TAILQ_INIT(&sc->sc_iowindow); 441 442 #if rbus 443 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 444 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 445 446 #if 0 447 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 448 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 449 #endif 450 #endif /* rbus */ 451 452 sc->sc_base_memh = 0; 453 454 /* power management: set D0 state */ 455 sc->sc_pwrmgt_offs = 0; 456 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 457 &pwrmgt_offs, 0)) { 458 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 459 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 460 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 461 reg &= ~PCI_PMCSR_STATE_MASK; 462 reg |= PCI_PMCSR_STATE_D0; 463 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 464 pci_conf_write(pc, pa->pa_tag, 465 pwrmgt_offs + PCI_PMCSR, reg); 466 } 467 468 sc->sc_pwrmgt_offs = pwrmgt_offs; 469 } 470 471 /* 472 * MAP socket registers and ExCA registers on memory-space 473 * When no valid address is set on socket base registers (on pci 474 * config space), get it not polite way. 475 */ 476 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 477 478 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 479 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 480 /* The address must be valid. */ 481 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 482 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 483 printf("%s: can't map socket base address 0x%x\n", 484 sc->sc_dev.dv_xname, sock_base); 485 /* 486 * I think it's funny: socket base registers must be 487 * mapped on memory space, but ... 488 */ 489 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 490 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 491 NULL)) { 492 printf("%s: can't map socket base address" 493 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 494 (unsigned long)sockbase); 495 /* give up... allocate reg space via rbus. */ 496 sc->sc_base_memh = 0; 497 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 498 } 499 } else { 500 DPRINTF(("%s: socket base address 0x%lx\n", 501 sc->sc_dev.dv_xname, sockbase)); 502 } 503 } 504 505 sc->sc_mem_start = 0; /* XXX */ 506 sc->sc_mem_end = 0xffffffff; /* XXX */ 507 508 /* 509 * When interrupt isn't routed correctly, give up probing cbb and do 510 * not kill pcic-compatible port. 511 */ 512 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 513 printf("%s: NOT USED because of unconfigured interrupt\n", 514 sc->sc_dev.dv_xname); 515 return; 516 } 517 518 /* 519 * When bus number isn't set correctly, give up using 32-bit CardBus 520 * mode. 521 */ 522 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 523 #if notyet 524 if (((busreg >> 8) & 0xff) == 0) { 525 printf("%s: CardBus support disabled because of unconfigured bus number\n", 526 sc->sc_dev.dv_xname); 527 flags |= PCCBB_PCMCIA_16BITONLY; 528 } 529 #endif 530 531 /* pccbb_machdep.c end */ 532 533 #if defined CBB_DEBUG 534 { 535 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 536 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 537 intrname[pa->pa_intrpin], pa->pa_intrline); 538 } 539 #endif 540 541 /* setup softc */ 542 sc->sc_pc = pc; 543 sc->sc_iot = pa->pa_iot; 544 sc->sc_memt = pa->pa_memt; 545 sc->sc_dmat = pa->pa_dmat; 546 sc->sc_tag = pa->pa_tag; 547 sc->sc_function = pa->pa_function; 548 sc->sc_sockbase = sock_base; 549 sc->sc_busnum = busreg; 550 551 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 552 553 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 554 555 shutdownhook_establish(pccbb_shutdown, sc); 556 557 /* Disable legacy register mapping. */ 558 switch (sc->sc_chipset) { 559 case CB_RX5C46X: /* fallthrough */ 560 #if 0 561 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 562 case CB_RX5C47X: 563 #endif 564 /* 565 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 566 * cannot be disabled by substituting 0 into PCI_LEGACY 567 * register. Ricoh CardBus bridges have special bits on Bridge 568 * control reg (addr 0x3e on PCI config space). 569 */ 570 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 571 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 572 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 573 break; 574 575 default: 576 /* XXX I don't know proper way to kill legacy I/O. */ 577 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 578 break; 579 } 580 581 config_defer(self, pccbb_pci_callback); 582 } 583 584 585 586 587 /* 588 * static void pccbb_pci_callback(struct device *self) 589 * 590 * The actual attach routine: get memory space for YENTA register 591 * space, setup YENTA register and route interrupt. 592 * 593 * This function should be deferred because this device may obtain 594 * memory space dynamically. This function must avoid obtaining 595 * memory area which has already kept for another device. 596 */ 597 static void 598 pccbb_pci_callback(self) 599 struct device *self; 600 { 601 struct pccbb_softc *sc = (void *)self; 602 pci_chipset_tag_t pc = sc->sc_pc; 603 pci_intr_handle_t ih; 604 const char *intrstr = NULL; 605 bus_addr_t sockbase; 606 struct cbslot_attach_args cba; 607 struct pcmciabus_attach_args paa; 608 struct cardslot_attach_args caa; 609 struct cardslot_softc *csc; 610 611 if (0 == sc->sc_base_memh) { 612 /* The socket registers aren't mapped correctly. */ 613 #if rbus 614 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 615 (sc->sc_chipset == CB_RX5C47X 616 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 617 0, &sockbase, &sc->sc_base_memh)) { 618 return; 619 } 620 sc->sc_base_memt = sc->sc_memt; 621 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 622 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 623 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 624 PCI_SOCKBASE))); 625 #else 626 sc->sc_base_memt = sc->sc_memt; 627 #if !defined CBB_PCI_BASE 628 #define CBB_PCI_BASE 0x20000000 629 #endif 630 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 631 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 632 /* cannot allocate memory space */ 633 return; 634 } 635 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 636 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 637 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 638 sc->sc_tag, PCI_SOCKBASE))); 639 sc->sc_sockbase = sockbase; 640 #endif 641 } 642 643 /* bus bridge initialization */ 644 pccbb_chipinit(sc); 645 646 /* clear data structure for child device interrupt handlers */ 647 LIST_INIT(&sc->sc_pil); 648 sc->sc_pil_intr_enable = 1; 649 650 /* Map and establish the interrupt. */ 651 if (pci_intr_map(&sc->sc_pa, &ih)) { 652 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 653 return; 654 } 655 intrstr = pci_intr_string(pc, ih); 656 657 /* 658 * XXX pccbbintr should be called under the priority lower 659 * than any other hard interrputs. 660 */ 661 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 662 663 if (sc->sc_ih == NULL) { 664 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 665 if (intrstr != NULL) { 666 printf(" at %s", intrstr); 667 } 668 printf("\n"); 669 return; 670 } 671 672 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 673 powerhook_establish(pccbb_powerhook, sc); 674 675 { 676 u_int32_t sockstat; 677 678 sockstat = bus_space_read_4(sc->sc_base_memt, 679 sc->sc_base_memh, CB_SOCKET_STAT); 680 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 681 sc->sc_flags |= CBB_CARDEXIST; 682 } 683 } 684 685 /* 686 * attach cardbus 687 */ 688 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 689 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 690 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 691 692 /* initialize cbslot_attach */ 693 cba.cba_busname = "cardbus"; 694 cba.cba_iot = sc->sc_iot; 695 cba.cba_memt = sc->sc_memt; 696 cba.cba_dmat = sc->sc_dmat; 697 cba.cba_bus = (busreg >> 8) & 0x0ff; 698 cba.cba_cc = (void *)sc; 699 cba.cba_cf = &pccbb_funcs; 700 cba.cba_intrline = sc->sc_pa.pa_intrline; 701 702 #if rbus 703 cba.cba_rbus_iot = sc->sc_rbus_iot; 704 cba.cba_rbus_memt = sc->sc_rbus_memt; 705 #endif 706 707 cba.cba_cacheline = PCI_CACHELINE(bhlc); 708 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 709 710 if (bootverbose) { 711 printf("%s: cacheline 0x%x lattimer 0x%x\n", 712 sc->sc_dev.dv_xname, cba.cba_cacheline, 713 cba.cba_lattimer); 714 printf("%s: bhlc 0x%x lscp 0x%x\n", 715 sc->sc_dev.dv_xname, bhlc, busreg); 716 } 717 #if defined SHOW_REGS 718 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 719 sc->sc_base_memh); 720 #endif 721 } 722 723 pccbb_pcmcia_attach_setup(sc, &paa); 724 caa.caa_cb_attach = NULL; 725 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 726 caa.caa_cb_attach = &cba; 727 } 728 caa.caa_16_attach = &paa; 729 caa.caa_ph = &sc->sc_pcmcia_h; 730 731 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 732 DPRINTF(("pccbbattach: found cardslot\n")); 733 sc->sc_csc = csc; 734 } 735 736 return; 737 } 738 739 740 741 742 743 /* 744 * static void pccbb_chipinit(struct pccbb_softc *sc) 745 * 746 * This function initialize YENTA chip registers listed below: 747 * 1) PCI command reg, 748 * 2) PCI and CardBus latency timer, 749 * 3) route PCI interrupt, 750 * 4) close all memory and io windows. 751 * 5) turn off bus power. 752 * 6) card detect interrupt on. 753 * 7) clear interrupt 754 */ 755 static void 756 pccbb_chipinit(sc) 757 struct pccbb_softc *sc; 758 { 759 pci_chipset_tag_t pc = sc->sc_pc; 760 pcitag_t tag = sc->sc_tag; 761 bus_space_tag_t bmt = sc->sc_base_memt; 762 bus_space_handle_t bmh = sc->sc_base_memh; 763 pcireg_t reg; 764 765 /* 766 * Set PCI command reg. 767 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 768 */ 769 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 770 /* I believe it is harmless. */ 771 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 772 PCI_COMMAND_MASTER_ENABLE); 773 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 774 775 /* 776 * Set CardBus latency timer. 777 */ 778 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 779 if (PCI_CB_LATENCY(reg) < 0x20) { 780 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 781 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 782 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 783 } 784 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 785 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 786 787 /* 788 * Set PCI latency timer. 789 */ 790 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 791 if (PCI_LATTIMER(reg) < 0x10) { 792 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 793 reg |= (0x10 << PCI_LATTIMER_SHIFT); 794 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 795 } 796 DPRINTF(("PCI latency timer 0x%x (%x)\n", 797 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 798 799 800 /* Route functional interrupts to PCI. */ 801 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 802 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 803 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 804 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 805 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 806 807 switch (sc->sc_chipset) { 808 case CB_TI113X: 809 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 810 /* This bit is shared, but may read as 0 on some chips, so set 811 it explicitly on both functions. */ 812 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 813 /* CSC intr enable */ 814 reg |= PCI113X_CBCTRL_PCI_CSC; 815 /* functional intr prohibit | prohibit ISA routing */ 816 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 817 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 818 break; 819 820 case CB_TI12XX: 821 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 822 reg |= PCI12XX_SYSCTRL_VCCPROT; 823 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 824 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 825 reg |= PCI12XX_CBCTRL_CSC; 826 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 827 break; 828 829 case CB_TOPIC95B: 830 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 831 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 832 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 833 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 834 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 835 sc->sc_dev.dv_xname, reg)); 836 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 837 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 838 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 839 DPRINTF(("0x%x\n", reg)); 840 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 841 break; 842 843 case CB_TOPIC97: 844 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 845 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 846 sc->sc_dev.dv_xname, reg)); 847 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 848 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 849 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 850 reg |= TOPIC97_SLOT_CTRL_PCIINT; 851 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 852 DPRINTF(("0x%x\n", reg)); 853 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 854 /* make sure to assert LV card support bits */ 855 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 856 0x800 + 0x3e, 857 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 858 0x800 + 0x3e) | 0x03); 859 break; 860 } 861 862 /* Close all memory and I/O windows. */ 863 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 864 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 865 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 866 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 867 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 868 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 869 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 870 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 871 872 /* reset 16-bit pcmcia bus */ 873 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 874 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 875 876 /* turn off power */ 877 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 878 879 /* CSC Interrupt: Card detect interrupt on */ 880 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 881 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 882 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 883 /* reset interrupt */ 884 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 885 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 886 } 887 888 889 890 891 /* 892 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 893 * struct pcmciabus_attach_args *paa) 894 * 895 * This function attaches 16-bit PCcard bus. 896 */ 897 STATIC void 898 pccbb_pcmcia_attach_setup(sc, paa) 899 struct pccbb_softc *sc; 900 struct pcmciabus_attach_args *paa; 901 { 902 struct pcic_handle *ph = &sc->sc_pcmcia_h; 903 #if rbus 904 rbus_tag_t rb; 905 #endif 906 907 /* initialize pcmcia part in pccbb_softc */ 908 ph->ph_parent = (struct device *)sc; 909 ph->sock = sc->sc_function; 910 ph->flags = 0; 911 ph->shutdown = 0; 912 ph->ih_irq = sc->sc_pa.pa_intrline; 913 ph->ph_bus_t = sc->sc_base_memt; 914 ph->ph_bus_h = sc->sc_base_memh; 915 ph->ph_read = pccbb_pcmcia_read; 916 ph->ph_write = pccbb_pcmcia_write; 917 sc->sc_pct = &pccbb_pcmcia_funcs; 918 919 /* 920 * We need to do a few things here: 921 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 922 * setting the IRQ numbers to 0. 923 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 924 * routing of CSC interrupts (e.g. card removal) to PCI while in 925 * PCMCIA mode. We just leave this set all the time. 926 * 3) Enable card insertion/removal interrupts in case the chip also 927 * needs that while in PCMCIA mode. 928 * 4) Clear any pending CSC interrupt. 929 */ 930 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 931 if (sc->sc_chipset == CB_TI113X) { 932 Pcic_write(ph, PCIC_CSC_INTR, 0); 933 } else { 934 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 935 Pcic_read(ph, PCIC_CSC); 936 } 937 938 /* initialize pcmcia bus attachment */ 939 paa->paa_busname = "pcmcia"; 940 paa->pct = sc->sc_pct; 941 paa->pch = ph; 942 paa->iobase = 0; /* I don't use them */ 943 paa->iosize = 0; 944 #if rbus 945 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 946 paa->iobase = rb->rb_start + rb->rb_offset; 947 paa->iosize = rb->rb_end - rb->rb_start; 948 #endif 949 950 return; 951 } 952 953 #if 0 954 STATIC void 955 pccbb_pcmcia_attach_card(ph) 956 struct pcic_handle *ph; 957 { 958 if (ph->flags & PCIC_FLAG_CARDP) { 959 panic("pccbb_pcmcia_attach_card: already attached"); 960 } 961 962 /* call the MI attach function */ 963 pcmcia_card_attach(ph->pcmcia); 964 965 ph->flags |= PCIC_FLAG_CARDP; 966 } 967 968 STATIC void 969 pccbb_pcmcia_detach_card(ph, flags) 970 struct pcic_handle *ph; 971 int flags; 972 { 973 if (!(ph->flags & PCIC_FLAG_CARDP)) { 974 panic("pccbb_pcmcia_detach_card: already detached"); 975 } 976 977 ph->flags &= ~PCIC_FLAG_CARDP; 978 979 /* call the MI detach function */ 980 pcmcia_card_detach(ph->pcmcia, flags); 981 } 982 #endif 983 984 /* 985 * int pccbbintr(arg) 986 * void *arg; 987 * This routine handles the interrupt from Yenta PCI-CardBus bridge 988 * itself. 989 */ 990 int 991 pccbbintr(arg) 992 void *arg; 993 { 994 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 995 u_int32_t sockevent, sockstate; 996 bus_space_tag_t memt = sc->sc_base_memt; 997 bus_space_handle_t memh = sc->sc_base_memh; 998 struct pcic_handle *ph = &sc->sc_pcmcia_h; 999 1000 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1001 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1002 Pcic_read(ph, PCIC_CSC); 1003 1004 if (sockevent == 0) { 1005 /* This intr is not for me: it may be for my child devices. */ 1006 if (sc->sc_pil_intr_enable) { 1007 return pccbbintr_function(sc); 1008 } else { 1009 return 0; 1010 } 1011 } 1012 1013 if (sockevent & CB_SOCKET_EVENT_CD) { 1014 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1015 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 1016 /* A card should be removed. */ 1017 if (sc->sc_flags & CBB_CARDEXIST) { 1018 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1019 sockevent)); 1020 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1021 sc->sc_flags &= ~CBB_CARDEXIST; 1022 if (sc->sc_csc->sc_status & 1023 CARDSLOT_STATUS_CARD_16) { 1024 #if 0 1025 struct pcic_handle *ph = 1026 &sc->sc_pcmcia_h; 1027 1028 pcmcia_card_deactivate(ph->pcmcia); 1029 pccbb_pcmcia_socket_disable(ph); 1030 pccbb_pcmcia_detach_card(ph, 1031 DETACH_FORCE); 1032 #endif 1033 cardslot_event_throw(sc->sc_csc, 1034 CARDSLOT_EVENT_REMOVAL_16); 1035 } else if (sc->sc_csc->sc_status & 1036 CARDSLOT_STATUS_CARD_CB) { 1037 /* Cardbus intr removed */ 1038 cardslot_event_throw(sc->sc_csc, 1039 CARDSLOT_EVENT_REMOVAL_CB); 1040 } 1041 } else if (sc->sc_flags & CBB_INSERTING) { 1042 sc->sc_flags &= ~CBB_INSERTING; 1043 callout_stop(&sc->sc_insert_ch); 1044 } 1045 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1046 /* 1047 * The pccbbintr may called from powerdown hook when 1048 * the system resumed, to detect the card 1049 * insertion/removal during suspension. 1050 */ 1051 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1052 if (sc->sc_flags & CBB_INSERTING) { 1053 callout_stop(&sc->sc_insert_ch); 1054 } 1055 callout_reset(&sc->sc_insert_ch, hz / 5, 1056 pci113x_insert, sc); 1057 sc->sc_flags |= CBB_INSERTING; 1058 } 1059 } 1060 1061 return (1); 1062 } 1063 1064 /* 1065 * static int pccbbintr_function(struct pccbb_softc *sc) 1066 * 1067 * This function calls each interrupt handler registered at the 1068 * bridge. The interrupt handlers are called in registered order. 1069 */ 1070 static int 1071 pccbbintr_function(sc) 1072 struct pccbb_softc *sc; 1073 { 1074 int retval = 0, val; 1075 struct pccbb_intrhand_list *pil; 1076 int s, splchanged; 1077 1078 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1079 pil = LIST_NEXT(pil, pil_next)) { 1080 /* 1081 * XXX priority change. gross. I use if-else 1082 * sentense instead of switch-case sentense because of 1083 * avoiding duplicate case value error. More than one 1084 * IPL_XXX use same value. It depends on 1085 * implimentation. 1086 */ 1087 splchanged = 1; 1088 if (pil->pil_level == IPL_SERIAL) { 1089 s = splserial(); 1090 } else if (pil->pil_level == IPL_HIGH) { 1091 s = splhigh(); 1092 } else if (pil->pil_level == IPL_CLOCK) { 1093 s = splclock(); 1094 } else if (pil->pil_level == IPL_AUDIO) { 1095 s = splaudio(); 1096 } else if (pil->pil_level == IPL_IMP) { 1097 s = splvm(); /* XXX */ 1098 } else if (pil->pil_level == IPL_TTY) { 1099 s = spltty(); 1100 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1101 s = splsoftserial(); 1102 } else if (pil->pil_level == IPL_NET) { 1103 s = splnet(); 1104 } else { 1105 splchanged = 0; 1106 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1107 } 1108 1109 val = (*pil->pil_func)(pil->pil_arg); 1110 1111 if (splchanged != 0) { 1112 splx(s); 1113 } 1114 1115 retval = retval == 1 ? 1 : 1116 retval == 0 ? val : val != 0 ? val : retval; 1117 } 1118 1119 return retval; 1120 } 1121 1122 static void 1123 pci113x_insert(arg) 1124 void *arg; 1125 { 1126 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1127 u_int32_t sockevent, sockstate; 1128 1129 if (!(sc->sc_flags & CBB_INSERTING)) { 1130 /* We add a card only under inserting state. */ 1131 return; 1132 } 1133 sc->sc_flags &= ~CBB_INSERTING; 1134 1135 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1136 CB_SOCKET_EVENT); 1137 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1138 CB_SOCKET_STAT); 1139 1140 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1141 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1142 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1143 sc->sc_flags |= CBB_CARDEXIST; 1144 /* call pccard interrupt handler here */ 1145 if (sockstate & CB_SOCKET_STAT_16BIT) { 1146 /* 16-bit card found */ 1147 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1148 cardslot_event_throw(sc->sc_csc, 1149 CARDSLOT_EVENT_INSERTION_16); 1150 } else if (sockstate & CB_SOCKET_STAT_CB) { 1151 /* cardbus card found */ 1152 /* cardbus_attach_card(sc->sc_csc); */ 1153 cardslot_event_throw(sc->sc_csc, 1154 CARDSLOT_EVENT_INSERTION_CB); 1155 } else { 1156 /* who are you? */ 1157 } 1158 } else { 1159 callout_reset(&sc->sc_insert_ch, hz / 10, 1160 pci113x_insert, sc); 1161 } 1162 } 1163 1164 #define PCCBB_PCMCIA_OFFSET 0x800 1165 static u_int8_t 1166 pccbb_pcmcia_read(ph, reg) 1167 struct pcic_handle *ph; 1168 int reg; 1169 { 1170 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1171 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1172 1173 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1174 PCCBB_PCMCIA_OFFSET + reg); 1175 } 1176 1177 static void 1178 pccbb_pcmcia_write(ph, reg, val) 1179 struct pcic_handle *ph; 1180 int reg; 1181 u_int8_t val; 1182 { 1183 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1184 val); 1185 1186 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1187 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1188 } 1189 1190 /* 1191 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1192 */ 1193 STATIC int 1194 pccbb_ctrl(ct, command) 1195 cardbus_chipset_tag_t ct; 1196 int command; 1197 { 1198 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1199 1200 switch (command) { 1201 case CARDBUS_CD: 1202 if (2 == pccbb_detect_card(sc)) { 1203 int retval = 0; 1204 int status = cb_detect_voltage(sc); 1205 if (PCCARD_VCC_5V & status) { 1206 retval |= CARDBUS_5V_CARD; 1207 } 1208 if (PCCARD_VCC_3V & status) { 1209 retval |= CARDBUS_3V_CARD; 1210 } 1211 if (PCCARD_VCC_XV & status) { 1212 retval |= CARDBUS_XV_CARD; 1213 } 1214 if (PCCARD_VCC_YV & status) { 1215 retval |= CARDBUS_YV_CARD; 1216 } 1217 return retval; 1218 } else { 1219 return 0; 1220 } 1221 case CARDBUS_RESET: 1222 return cb_reset(sc); 1223 case CARDBUS_IO_ENABLE: /* fallthrough */ 1224 case CARDBUS_IO_DISABLE: /* fallthrough */ 1225 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1226 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1227 case CARDBUS_BM_ENABLE: /* fallthrough */ 1228 case CARDBUS_BM_DISABLE: /* fallthrough */ 1229 /* XXX: I think we don't need to call this function below. */ 1230 return pccbb_cardenable(sc, command); 1231 } 1232 1233 return 0; 1234 } 1235 1236 /* 1237 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1238 * This function returns true when it succeeds and returns false when 1239 * it fails. 1240 */ 1241 STATIC int 1242 pccbb_power(ct, command) 1243 cardbus_chipset_tag_t ct; 1244 int command; 1245 { 1246 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1247 1248 u_int32_t status, sock_ctrl, reg_ctrl; 1249 bus_space_tag_t memt = sc->sc_base_memt; 1250 bus_space_handle_t memh = sc->sc_base_memh; 1251 1252 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1253 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1254 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1258 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1259 "UNKNOWN", 1260 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1261 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1263 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1264 "UNKNOWN", command)); 1265 1266 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1267 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1268 1269 switch (command & CARDBUS_VCCMASK) { 1270 case CARDBUS_VCC_UC: 1271 break; 1272 case CARDBUS_VCC_5V: 1273 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1274 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1275 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1276 } else { 1277 printf("%s: BAD voltage request: no 5 V card\n", 1278 sc->sc_dev.dv_xname); 1279 } 1280 break; 1281 case CARDBUS_VCC_3V: 1282 if (CB_SOCKET_STAT_3VCARD & status) { 1283 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1284 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1285 } else { 1286 printf("%s: BAD voltage request: no 3.3 V card\n", 1287 sc->sc_dev.dv_xname); 1288 } 1289 break; 1290 case CARDBUS_VCC_0V: 1291 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1292 break; 1293 default: 1294 return 0; /* power NEVER changed */ 1295 } 1296 1297 switch (command & CARDBUS_VPPMASK) { 1298 case CARDBUS_VPP_UC: 1299 break; 1300 case CARDBUS_VPP_0V: 1301 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1302 break; 1303 case CARDBUS_VPP_VCC: 1304 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1305 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1306 break; 1307 case CARDBUS_VPP_12V: 1308 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1309 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1310 break; 1311 } 1312 1313 #if 0 1314 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1315 #endif 1316 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1317 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1318 1319 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1320 printf 1321 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1322 sc->sc_dev.dv_xname, sock_ctrl, status); 1323 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1324 (command & CARDBUS_VCCMASK) == 1325 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1326 CARDBUS_VCCMASK) == 1327 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1328 CARDBUS_VCCMASK) == 1329 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1330 CARDBUS_VCCMASK) == 1331 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1332 CARDBUS_VCCMASK) == 1333 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1334 CARDBUS_VCCMASK) == 1335 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1336 (command & CARDBUS_VPPMASK) == 1337 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1338 CARDBUS_VPPMASK) == 1339 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1340 CARDBUS_VPPMASK) == 1341 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1342 CARDBUS_VPPMASK) == 1343 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1344 #if 0 1345 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1346 u_int32_t force = 1347 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1348 /* Reset Bad Vcc request */ 1349 force &= ~CB_SOCKET_FORCE_BADVCC; 1350 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1351 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1352 CB_SOCKET_STAT)); 1353 return 1; 1354 } 1355 #endif 1356 return 0; 1357 } 1358 1359 if (sc->sc_chipset == CB_TOPIC97) { 1360 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1361 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1362 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1363 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1364 else 1365 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1366 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1367 } 1368 1369 /* 1370 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1371 * time is 20 ms, some PC-Card bridge requires longer duration. 1372 */ 1373 #if 0 /* XXX called on interrupt context */ 1374 DELAY_MS(300, sc); 1375 #else 1376 delay(300 * 1000); 1377 #endif 1378 1379 return 1; /* power changed correctly */ 1380 } 1381 1382 #if defined CB_PCMCIA_POLL 1383 struct cb_poll_str { 1384 void *arg; 1385 int (*func) __P((void *)); 1386 int level; 1387 pccard_chipset_tag_t ct; 1388 int count; 1389 struct callout poll_ch; 1390 }; 1391 1392 static struct cb_poll_str cb_poll[10]; 1393 static int cb_poll_n = 0; 1394 1395 static void cb_pcmcia_poll __P((void *arg)); 1396 1397 static void 1398 cb_pcmcia_poll(arg) 1399 void *arg; 1400 { 1401 struct cb_poll_str *poll = arg; 1402 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1403 struct pccbb_softc *sc = psc->cpc_parent; 1404 int s; 1405 u_int32_t spsr; /* socket present-state reg */ 1406 1407 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1408 switch (poll->level) { 1409 case IPL_NET: 1410 s = splnet(); 1411 break; 1412 case IPL_BIO: 1413 s = splbio(); 1414 break; 1415 case IPL_TTY: /* fallthrough */ 1416 default: 1417 s = spltty(); 1418 break; 1419 } 1420 1421 spsr = 1422 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1423 CB_SOCKET_STAT); 1424 1425 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1426 if (!(spsr & 0x40)) { /* CINT low */ 1427 #else 1428 if (1) { 1429 #endif 1430 if ((*poll->func) (poll->arg) == 1) { 1431 ++poll->count; 1432 printf("intr: reported from poller, 0x%x\n", spsr); 1433 #if defined LEVEL2 1434 } else { 1435 printf("intr: miss! 0x%x\n", spsr); 1436 #endif 1437 } 1438 } 1439 splx(s); 1440 } 1441 #endif /* defined CB_PCMCIA_POLL */ 1442 1443 /* 1444 * static int pccbb_detect_card(struct pccbb_softc *sc) 1445 * return value: 0 if no card exists. 1446 * 1 if 16-bit card exists. 1447 * 2 if cardbus card exists. 1448 */ 1449 static int 1450 pccbb_detect_card(sc) 1451 struct pccbb_softc *sc; 1452 { 1453 bus_space_handle_t base_memh = sc->sc_base_memh; 1454 bus_space_tag_t base_memt = sc->sc_base_memt; 1455 u_int32_t sockstat = 1456 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1457 int retval = 0; 1458 1459 /* CD1 and CD2 asserted */ 1460 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1461 /* card must be present */ 1462 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1463 /* NOTACARD DEASSERTED */ 1464 if (CB_SOCKET_STAT_CB & sockstat) { 1465 /* CardBus mode */ 1466 retval = 2; 1467 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1468 /* 16-bit mode */ 1469 retval = 1; 1470 } 1471 } 1472 } 1473 return retval; 1474 } 1475 1476 /* 1477 * STATIC int cb_reset(struct pccbb_softc *sc) 1478 * This function resets CardBus card. 1479 */ 1480 STATIC int 1481 cb_reset(sc) 1482 struct pccbb_softc *sc; 1483 { 1484 /* 1485 * Reset Assert at least 20 ms 1486 * Some machines request longer duration. 1487 */ 1488 int reset_duration = 1489 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1490 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1491 1492 /* Reset bit Assert (bit 6 at 0x3E) */ 1493 bcr |= CB_BCR_RESET_ENABLE; 1494 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1495 DELAY_MS(reset_duration, sc); 1496 1497 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1498 /* Reset bit Deassert (bit 6 at 0x3E) */ 1499 bcr &= ~CB_BCR_RESET_ENABLE; 1500 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1501 DELAY_MS(reset_duration, sc); 1502 } 1503 /* No card found on the slot. Keep Reset. */ 1504 return 1; 1505 } 1506 1507 /* 1508 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1509 * This function detect card Voltage. 1510 */ 1511 STATIC int 1512 cb_detect_voltage(sc) 1513 struct pccbb_softc *sc; 1514 { 1515 u_int32_t psr; /* socket present-state reg */ 1516 bus_space_tag_t iot = sc->sc_base_memt; 1517 bus_space_handle_t ioh = sc->sc_base_memh; 1518 int vol = PCCARD_VCC_UKN; /* set 0 */ 1519 1520 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1521 1522 if (0x400u & psr) { 1523 vol |= PCCARD_VCC_5V; 1524 } 1525 if (0x800u & psr) { 1526 vol |= PCCARD_VCC_3V; 1527 } 1528 1529 return vol; 1530 } 1531 1532 STATIC int 1533 cbbprint(aux, pcic) 1534 void *aux; 1535 const char *pcic; 1536 { 1537 /* 1538 struct cbslot_attach_args *cba = aux; 1539 1540 if (cba->cba_slot >= 0) { 1541 aprint_normal(" slot %d", cba->cba_slot); 1542 } 1543 */ 1544 return UNCONF; 1545 } 1546 1547 /* 1548 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1549 * This function enables and disables the card 1550 */ 1551 STATIC int 1552 pccbb_cardenable(sc, function) 1553 struct pccbb_softc *sc; 1554 int function; 1555 { 1556 u_int32_t command = 1557 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1558 1559 DPRINTF(("pccbb_cardenable:")); 1560 switch (function) { 1561 case CARDBUS_IO_ENABLE: 1562 command |= PCI_COMMAND_IO_ENABLE; 1563 break; 1564 case CARDBUS_IO_DISABLE: 1565 command &= ~PCI_COMMAND_IO_ENABLE; 1566 break; 1567 case CARDBUS_MEM_ENABLE: 1568 command |= PCI_COMMAND_MEM_ENABLE; 1569 break; 1570 case CARDBUS_MEM_DISABLE: 1571 command &= ~PCI_COMMAND_MEM_ENABLE; 1572 break; 1573 case CARDBUS_BM_ENABLE: 1574 command |= PCI_COMMAND_MASTER_ENABLE; 1575 break; 1576 case CARDBUS_BM_DISABLE: 1577 command &= ~PCI_COMMAND_MASTER_ENABLE; 1578 break; 1579 default: 1580 return 0; 1581 } 1582 1583 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1584 DPRINTF((" command reg 0x%x\n", command)); 1585 return 1; 1586 } 1587 1588 #if !rbus 1589 /* 1590 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1591 */ 1592 static int 1593 pccbb_io_open(ct, win, start, end) 1594 cardbus_chipset_tag_t ct; 1595 int win; 1596 u_int32_t start, end; 1597 { 1598 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1599 int basereg; 1600 int limitreg; 1601 1602 if ((win < 0) || (win > 2)) { 1603 #if defined DIAGNOSTIC 1604 printf("cardbus_io_open: window out of range %d\n", win); 1605 #endif 1606 return 0; 1607 } 1608 1609 basereg = win * 8 + 0x2c; 1610 limitreg = win * 8 + 0x30; 1611 1612 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1613 start, basereg, end, limitreg)); 1614 1615 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1616 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1617 return 1; 1618 } 1619 1620 /* 1621 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1622 */ 1623 static int 1624 pccbb_io_close(ct, win) 1625 cardbus_chipset_tag_t ct; 1626 int win; 1627 { 1628 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1629 int basereg; 1630 int limitreg; 1631 1632 if ((win < 0) || (win > 2)) { 1633 #if defined DIAGNOSTIC 1634 printf("cardbus_io_close: window out of range %d\n", win); 1635 #endif 1636 return 0; 1637 } 1638 1639 basereg = win * 8 + 0x2c; 1640 limitreg = win * 8 + 0x30; 1641 1642 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1643 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1644 return 1; 1645 } 1646 1647 /* 1648 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1649 */ 1650 static int 1651 pccbb_mem_open(ct, win, start, end) 1652 cardbus_chipset_tag_t ct; 1653 int win; 1654 u_int32_t start, end; 1655 { 1656 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1657 int basereg; 1658 int limitreg; 1659 1660 if ((win < 0) || (win > 2)) { 1661 #if defined DIAGNOSTIC 1662 printf("cardbus_mem_open: window out of range %d\n", win); 1663 #endif 1664 return 0; 1665 } 1666 1667 basereg = win * 8 + 0x1c; 1668 limitreg = win * 8 + 0x20; 1669 1670 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1671 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1672 return 1; 1673 } 1674 1675 /* 1676 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1677 */ 1678 static int 1679 pccbb_mem_close(ct, win) 1680 cardbus_chipset_tag_t ct; 1681 int win; 1682 { 1683 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1684 int basereg; 1685 int limitreg; 1686 1687 if ((win < 0) || (win > 2)) { 1688 #if defined DIAGNOSTIC 1689 printf("cardbus_mem_close: window out of range %d\n", win); 1690 #endif 1691 return 0; 1692 } 1693 1694 basereg = win * 8 + 0x1c; 1695 limitreg = win * 8 + 0x20; 1696 1697 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1698 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1699 return 1; 1700 } 1701 #endif 1702 1703 /* 1704 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1705 * int irq, 1706 * int level, 1707 * int (* func) __P((void *)), 1708 * void *arg) 1709 * 1710 * This function registers an interrupt handler at the bridge, in 1711 * order not to call the interrupt handlers of child devices when 1712 * a card-deletion interrupt occurs. 1713 * 1714 * The arguments irq and level are not used. 1715 */ 1716 static void * 1717 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1718 cardbus_chipset_tag_t ct; 1719 int irq, level; 1720 int (*func) __P((void *)); 1721 void *arg; 1722 { 1723 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1724 1725 return pccbb_intr_establish(sc, irq, level, func, arg); 1726 } 1727 1728 1729 /* 1730 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1731 * void *ih) 1732 * 1733 * This function removes an interrupt handler pointed by ih. 1734 */ 1735 static void 1736 pccbb_cb_intr_disestablish(ct, ih) 1737 cardbus_chipset_tag_t ct; 1738 void *ih; 1739 { 1740 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1741 1742 pccbb_intr_disestablish(sc, ih); 1743 } 1744 1745 1746 void 1747 pccbb_intr_route(sc) 1748 struct pccbb_softc *sc; 1749 { 1750 pcireg_t reg; 1751 1752 /* initialize bridge intr routing */ 1753 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1754 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1755 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1756 1757 switch (sc->sc_chipset) { 1758 case CB_TI113X: 1759 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1760 /* functional intr enabled */ 1761 reg |= PCI113X_CBCTRL_PCI_INTR; 1762 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1763 break; 1764 default: 1765 break; 1766 } 1767 } 1768 1769 /* 1770 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1771 * int irq, 1772 * int level, 1773 * int (* func) __P((void *)), 1774 * void *arg) 1775 * 1776 * This function registers an interrupt handler at the bridge, in 1777 * order not to call the interrupt handlers of child devices when 1778 * a card-deletion interrupt occurs. 1779 * 1780 * The arguments irq is not used because pccbb selects intr vector. 1781 */ 1782 static void * 1783 pccbb_intr_establish(sc, irq, level, func, arg) 1784 struct pccbb_softc *sc; 1785 int irq, level; 1786 int (*func) __P((void *)); 1787 void *arg; 1788 { 1789 struct pccbb_intrhand_list *pil, *newpil; 1790 1791 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1792 1793 if (LIST_EMPTY(&sc->sc_pil)) { 1794 pccbb_intr_route(sc); 1795 } 1796 1797 /* 1798 * Allocate a room for interrupt handler structure. 1799 */ 1800 if (NULL == (newpil = 1801 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1802 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1803 return NULL; 1804 } 1805 1806 newpil->pil_func = func; 1807 newpil->pil_arg = arg; 1808 newpil->pil_level = level; 1809 1810 if (LIST_EMPTY(&sc->sc_pil)) { 1811 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1812 } else { 1813 for (pil = LIST_FIRST(&sc->sc_pil); 1814 LIST_NEXT(pil, pil_next) != NULL; 1815 pil = LIST_NEXT(pil, pil_next)); 1816 LIST_INSERT_AFTER(pil, newpil, pil_next); 1817 } 1818 1819 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1820 LIST_FIRST(&sc->sc_pil))); 1821 1822 return newpil; 1823 } 1824 1825 /* 1826 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1827 * void *ih) 1828 * 1829 * This function removes an interrupt handler pointed by ih. ih 1830 * should be the value returned by cardbus_intr_establish() or 1831 * NULL. 1832 * 1833 * When ih is NULL, this function will do nothing. 1834 */ 1835 static void 1836 pccbb_intr_disestablish(sc, ih) 1837 struct pccbb_softc *sc; 1838 void *ih; 1839 { 1840 struct pccbb_intrhand_list *pil; 1841 pcireg_t reg; 1842 1843 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1844 LIST_FIRST(&sc->sc_pil))); 1845 1846 if (ih == NULL) { 1847 /* intr handler is not set */ 1848 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1849 return; 1850 } 1851 1852 #ifdef DIAGNOSTIC 1853 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1854 pil = LIST_NEXT(pil, pil_next)) { 1855 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1856 if (pil == ih) { 1857 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1858 break; 1859 } 1860 } 1861 if (pil == NULL) { 1862 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1863 sc->sc_dev.dv_xname, ih); 1864 } 1865 #endif 1866 1867 pil = (struct pccbb_intrhand_list *)ih; 1868 LIST_REMOVE(pil, pil_next); 1869 free(pil, M_DEVBUF); 1870 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1871 1872 if (LIST_EMPTY(&sc->sc_pil)) { 1873 /* No interrupt handlers */ 1874 1875 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1876 1877 /* stop routing PCI intr */ 1878 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1879 reg |= CB_BCR_INTR_IREQ_ENABLE; 1880 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1881 1882 switch (sc->sc_chipset) { 1883 case CB_TI113X: 1884 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1885 /* functional intr disabled */ 1886 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1887 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1888 break; 1889 default: 1890 break; 1891 } 1892 } 1893 } 1894 1895 #if defined SHOW_REGS 1896 static void 1897 cb_show_regs(pc, tag, memt, memh) 1898 pci_chipset_tag_t pc; 1899 pcitag_t tag; 1900 bus_space_tag_t memt; 1901 bus_space_handle_t memh; 1902 { 1903 int i; 1904 printf("PCI config regs:"); 1905 for (i = 0; i < 0x50; i += 4) { 1906 if (i % 16 == 0) { 1907 printf("\n 0x%02x:", i); 1908 } 1909 printf(" %08x", pci_conf_read(pc, tag, i)); 1910 } 1911 for (i = 0x80; i < 0xb0; i += 4) { 1912 if (i % 16 == 0) { 1913 printf("\n 0x%02x:", i); 1914 } 1915 printf(" %08x", pci_conf_read(pc, tag, i)); 1916 } 1917 1918 if (memh == 0) { 1919 printf("\n"); 1920 return; 1921 } 1922 1923 printf("\nsocket regs:"); 1924 for (i = 0; i <= 0x10; i += 0x04) { 1925 printf(" %08x", bus_space_read_4(memt, memh, i)); 1926 } 1927 printf("\nExCA regs:"); 1928 for (i = 0; i < 0x08; ++i) { 1929 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1930 } 1931 printf("\n"); 1932 return; 1933 } 1934 #endif 1935 1936 /* 1937 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1938 * int busno, int devno, int function) 1939 * This is the function to make a tag to access config space of 1940 * a CardBus Card. It works same as pci_conf_read. 1941 */ 1942 static cardbustag_t 1943 pccbb_make_tag(cc, busno, devno, function) 1944 cardbus_chipset_tag_t cc; 1945 int busno, devno, function; 1946 { 1947 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1948 1949 return pci_make_tag(sc->sc_pc, busno, devno, function); 1950 } 1951 1952 static void 1953 pccbb_free_tag(cc, tag) 1954 cardbus_chipset_tag_t cc; 1955 cardbustag_t tag; 1956 { 1957 } 1958 1959 /* 1960 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1961 * cardbustag_t tag, int offset) 1962 * This is the function to read the config space of a CardBus Card. 1963 * It works same as pci_conf_read. 1964 */ 1965 static cardbusreg_t 1966 pccbb_conf_read(cc, tag, offset) 1967 cardbus_chipset_tag_t cc; 1968 cardbustag_t tag; 1969 int offset; /* register offset */ 1970 { 1971 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1972 1973 return pci_conf_read(sc->sc_pc, tag, offset); 1974 } 1975 1976 /* 1977 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1978 * int offs, cardbusreg_t val) 1979 * This is the function to write the config space of a CardBus Card. 1980 * It works same as pci_conf_write. 1981 */ 1982 static void 1983 pccbb_conf_write(cc, tag, reg, val) 1984 cardbus_chipset_tag_t cc; 1985 cardbustag_t tag; 1986 int reg; /* register offset */ 1987 cardbusreg_t val; 1988 { 1989 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1990 1991 pci_conf_write(sc->sc_pc, tag, reg, val); 1992 } 1993 1994 #if 0 1995 STATIC int 1996 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1997 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1998 int speed, int flags, 1999 bus_space_handle_t * iohp) 2000 #endif 2001 /* 2002 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2003 * bus_addr_t start, bus_size_t size, 2004 * bus_size_t align, 2005 * struct pcmcia_io_handle *pcihp 2006 * 2007 * This function only allocates I/O region for pccard. This function 2008 * never maps the allocated region to pccard I/O area. 2009 * 2010 * XXX: The interface of this function is not very good, I believe. 2011 */ 2012 STATIC int 2013 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2014 pcmcia_chipset_handle_t pch; 2015 bus_addr_t start; /* start address */ 2016 bus_size_t size; 2017 bus_size_t align; 2018 struct pcmcia_io_handle *pcihp; 2019 { 2020 struct pcic_handle *ph = (struct pcic_handle *)pch; 2021 bus_addr_t ioaddr; 2022 int flags = 0; 2023 bus_space_tag_t iot; 2024 bus_space_handle_t ioh; 2025 bus_addr_t mask; 2026 #if rbus 2027 rbus_tag_t rb; 2028 #endif 2029 if (align == 0) { 2030 align = size; /* XXX: funny??? */ 2031 } 2032 2033 if (start != 0) { 2034 /* XXX: assume all card decode lower 10 bits by its hardware */ 2035 mask = 0x3ff; 2036 /* enforce to use only masked address */ 2037 start &= mask; 2038 } else { 2039 /* 2040 * calculate mask: 2041 * 1. get the most significant bit of size (call it msb). 2042 * 2. compare msb with the value of size. 2043 * 3. if size is larger, shift msb left once. 2044 * 4. obtain mask value to decrement msb. 2045 */ 2046 bus_size_t size_tmp = size; 2047 int shifts = 0; 2048 2049 mask = 1; 2050 while (size_tmp) { 2051 ++shifts; 2052 size_tmp >>= 1; 2053 } 2054 mask = (1 << shifts); 2055 if (mask < size) { 2056 mask <<= 1; 2057 } 2058 --mask; 2059 } 2060 2061 /* 2062 * Allocate some arbitrary I/O space. 2063 */ 2064 2065 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2066 2067 #if rbus 2068 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2069 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2070 return 1; 2071 } 2072 DPRINTF(("pccbb_pcmcia_io_alloc alloc port %lx+%lx\n", 2073 (u_long) ioaddr, (u_long) size)); 2074 #else 2075 if (start) { 2076 ioaddr = start; 2077 if (bus_space_map(iot, start, size, 0, &ioh)) { 2078 return 1; 2079 } 2080 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2081 (u_long) ioaddr, (u_long) size)); 2082 } else { 2083 flags |= PCMCIA_IO_ALLOCATED; 2084 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2085 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2086 size, align, 0, 0, &ioaddr, &ioh)) { 2087 /* No room be able to be get. */ 2088 return 1; 2089 } 2090 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2091 (u_long) ioaddr, (u_long) size)); 2092 } 2093 #endif 2094 2095 pcihp->iot = iot; 2096 pcihp->ioh = ioh; 2097 pcihp->addr = ioaddr; 2098 pcihp->size = size; 2099 pcihp->flags = flags; 2100 2101 return 0; 2102 } 2103 2104 /* 2105 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2106 * struct pcmcia_io_handle *pcihp) 2107 * 2108 * This function only frees I/O region for pccard. 2109 * 2110 * XXX: The interface of this function is not very good, I believe. 2111 */ 2112 void 2113 pccbb_pcmcia_io_free(pch, pcihp) 2114 pcmcia_chipset_handle_t pch; 2115 struct pcmcia_io_handle *pcihp; 2116 { 2117 #if !rbus 2118 bus_space_tag_t iot = pcihp->iot; 2119 #endif 2120 bus_space_handle_t ioh = pcihp->ioh; 2121 bus_size_t size = pcihp->size; 2122 2123 #if rbus 2124 struct pccbb_softc *sc = 2125 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2126 rbus_tag_t rb = sc->sc_rbus_iot; 2127 2128 rbus_space_free(rb, ioh, size, NULL); 2129 #else 2130 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2131 bus_space_free(iot, ioh, size); 2132 else 2133 bus_space_unmap(iot, ioh, size); 2134 #endif 2135 } 2136 2137 /* 2138 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2139 * bus_addr_t offset, bus_size_t size, 2140 * struct pcmcia_io_handle *pcihp, 2141 * int *windowp) 2142 * 2143 * This function maps the allocated I/O region to pccard. This function 2144 * never allocates any I/O region for pccard I/O area. I don't 2145 * understand why the original authors of pcmciabus separated alloc and 2146 * map. I believe the two must be unite. 2147 * 2148 * XXX: no wait timing control? 2149 */ 2150 int 2151 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2152 pcmcia_chipset_handle_t pch; 2153 int width; 2154 bus_addr_t offset; 2155 bus_size_t size; 2156 struct pcmcia_io_handle *pcihp; 2157 int *windowp; 2158 { 2159 struct pcic_handle *ph = (struct pcic_handle *)pch; 2160 bus_addr_t ioaddr = pcihp->addr + offset; 2161 int i, win; 2162 #if defined CBB_DEBUG 2163 static char *width_names[] = { "dynamic", "io8", "io16" }; 2164 #endif 2165 2166 /* Sanity check I/O handle. */ 2167 2168 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2169 panic("pccbb_pcmcia_io_map iot is bogus"); 2170 } 2171 2172 /* XXX Sanity check offset/size. */ 2173 2174 win = -1; 2175 for (i = 0; i < PCIC_IO_WINS; i++) { 2176 if ((ph->ioalloc & (1 << i)) == 0) { 2177 win = i; 2178 ph->ioalloc |= (1 << i); 2179 break; 2180 } 2181 } 2182 2183 if (win == -1) { 2184 return 1; 2185 } 2186 2187 *windowp = win; 2188 2189 /* XXX this is pretty gross */ 2190 2191 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2192 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2193 2194 /* XXX wtf is this doing here? */ 2195 2196 #if 0 2197 printf(" port 0x%lx", (u_long) ioaddr); 2198 if (size > 1) { 2199 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2200 } 2201 #endif 2202 2203 ph->io[win].addr = ioaddr; 2204 ph->io[win].size = size; 2205 ph->io[win].width = width; 2206 2207 /* actual dirty register-value changing in the function below. */ 2208 pccbb_pcmcia_do_io_map(ph, win); 2209 2210 return 0; 2211 } 2212 2213 /* 2214 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2215 * 2216 * This function changes register-value to map I/O region for pccard. 2217 */ 2218 static void 2219 pccbb_pcmcia_do_io_map(ph, win) 2220 struct pcic_handle *ph; 2221 int win; 2222 { 2223 static u_int8_t pcic_iowidth[3] = { 2224 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2225 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2226 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2227 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2228 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2229 }; 2230 2231 #define PCIC_SIA_START_LOW 0 2232 #define PCIC_SIA_START_HIGH 1 2233 #define PCIC_SIA_STOP_LOW 2 2234 #define PCIC_SIA_STOP_HIGH 3 2235 2236 int regbase_win = 0x8 + win * 0x04; 2237 u_int8_t ioctl, enable; 2238 2239 DPRINTF( 2240 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2241 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2242 ph->io[win].width * 8)); 2243 2244 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2245 ph->io[win].addr & 0xff); 2246 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2247 (ph->io[win].addr >> 8) & 0xff); 2248 2249 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2250 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2251 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2252 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2253 2254 ioctl = Pcic_read(ph, PCIC_IOCTL); 2255 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2256 switch (win) { 2257 case 0: 2258 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2259 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2260 PCIC_IOCTL_IO0_DATASIZE_MASK); 2261 ioctl |= pcic_iowidth[ph->io[win].width]; 2262 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2263 break; 2264 case 1: 2265 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2266 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2267 PCIC_IOCTL_IO1_DATASIZE_MASK); 2268 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2269 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2270 break; 2271 } 2272 Pcic_write(ph, PCIC_IOCTL, ioctl); 2273 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2274 #if defined CBB_DEBUG 2275 { 2276 u_int8_t start_low = 2277 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2278 u_int8_t start_high = 2279 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2280 u_int8_t stop_low = 2281 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2282 u_int8_t stop_high = 2283 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2284 printf 2285 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2286 start_low, start_high, stop_low, stop_high, ioctl, enable); 2287 } 2288 #endif 2289 } 2290 2291 /* 2292 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2293 * 2294 * This function unmaps I/O region. No return value. 2295 */ 2296 STATIC void 2297 pccbb_pcmcia_io_unmap(pch, win) 2298 pcmcia_chipset_handle_t pch; 2299 int win; 2300 { 2301 struct pcic_handle *ph = (struct pcic_handle *)pch; 2302 int reg; 2303 2304 if (win >= PCIC_IO_WINS || win < 0) { 2305 panic("pccbb_pcmcia_io_unmap: window out of range"); 2306 } 2307 2308 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2309 switch (win) { 2310 case 0: 2311 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2312 break; 2313 case 1: 2314 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2315 break; 2316 } 2317 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2318 2319 ph->ioalloc &= ~(1 << win); 2320 } 2321 2322 /* 2323 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2324 * 2325 * This function enables the card. All information is stored in 2326 * the first argument, pcmcia_chipset_handle_t. 2327 */ 2328 static void 2329 pccbb_pcmcia_wait_ready(ph) 2330 struct pcic_handle *ph; 2331 { 2332 int i; 2333 2334 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2335 Pcic_read(ph, PCIC_IF_STATUS))); 2336 2337 for (i = 0; i < 2000; i++) { 2338 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2339 return; 2340 } 2341 DELAY_MS(2, ph->ph_parent); 2342 #ifdef CBB_DEBUG 2343 if ((i > 1000) && (i % 25 == 24)) 2344 printf("."); 2345 #endif 2346 } 2347 2348 #ifdef DIAGNOSTIC 2349 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2350 Pcic_read(ph, PCIC_IF_STATUS)); 2351 #endif 2352 } 2353 2354 /* 2355 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2356 * 2357 * This function enables the card. All information is stored in 2358 * the first argument, pcmcia_chipset_handle_t. 2359 */ 2360 STATIC void 2361 pccbb_pcmcia_socket_enable(pch) 2362 pcmcia_chipset_handle_t pch; 2363 { 2364 struct pcic_handle *ph = (struct pcic_handle *)pch; 2365 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2366 int cardtype, win; 2367 u_int8_t power, intr; 2368 pcireg_t spsr; 2369 int voltage; 2370 2371 /* this bit is mostly stolen from pcic_attach_card */ 2372 2373 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2374 2375 /* get card Vcc info */ 2376 2377 spsr = 2378 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2379 CB_SOCKET_STAT); 2380 if (spsr & CB_SOCKET_STAT_5VCARD) { 2381 DPRINTF(("5V card\n")); 2382 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2383 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2384 DPRINTF(("3V card\n")); 2385 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2386 } else { 2387 printf("?V card, 0x%x\n", spsr); /* XXX */ 2388 return; 2389 } 2390 2391 /* disable socket: negate output enable bit and power off */ 2392 2393 power = 0; 2394 Pcic_write(ph, PCIC_PWRCTL, power); 2395 2396 /* power down the socket to reset it, clear the card reset pin */ 2397 2398 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2399 2400 /* 2401 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2402 * we are changing Vcc (Toff). 2403 */ 2404 /* delay(300*1000); too much */ 2405 2406 /* assert reset bit */ 2407 intr = Pcic_read(ph, PCIC_INTR); 2408 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2409 Pcic_write(ph, PCIC_INTR, intr); 2410 2411 /* power up the socket and output enable */ 2412 power = Pcic_read(ph, PCIC_PWRCTL); 2413 power |= PCIC_PWRCTL_OE; 2414 Pcic_write(ph, PCIC_PWRCTL, power); 2415 pccbb_power(sc, voltage); 2416 2417 /* 2418 * hold RESET at least 20 ms: the spec says only 10 us is 2419 * enough, but TI1130 requires at least 20 ms. 2420 */ 2421 #if 0 /* XXX called on interrupt context */ 2422 DELAY_MS(20, sc); 2423 #else 2424 delay(20 * 1000); 2425 #endif 2426 2427 /* clear the reset flag */ 2428 2429 intr |= PCIC_INTR_RESET; 2430 Pcic_write(ph, PCIC_INTR, intr); 2431 2432 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2433 2434 #if 0 /* XXX called on interrupt context */ 2435 DELAY_MS(20, sc); 2436 #else 2437 delay(20 * 1000); 2438 #endif 2439 2440 /* wait for the chip to finish initializing */ 2441 2442 pccbb_pcmcia_wait_ready(ph); 2443 2444 /* zero out the address windows */ 2445 2446 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2447 2448 /* set the card type */ 2449 2450 cardtype = pcmcia_card_gettype(ph->pcmcia); 2451 2452 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2453 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2454 Pcic_write(ph, PCIC_INTR, intr); 2455 2456 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2457 ph->ph_parent->dv_xname, ph->sock, 2458 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2459 2460 /* reinstall all the memory and io mappings */ 2461 2462 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2463 if (ph->memalloc & (1 << win)) { 2464 pccbb_pcmcia_do_mem_map(ph, win); 2465 } 2466 } 2467 2468 for (win = 0; win < PCIC_IO_WINS; ++win) { 2469 if (ph->ioalloc & (1 << win)) { 2470 pccbb_pcmcia_do_io_map(ph, win); 2471 } 2472 } 2473 } 2474 2475 /* 2476 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2477 * 2478 * This function disables the card. All information is stored in 2479 * the first argument, pcmcia_chipset_handle_t. 2480 */ 2481 STATIC void 2482 pccbb_pcmcia_socket_disable(pch) 2483 pcmcia_chipset_handle_t pch; 2484 { 2485 struct pcic_handle *ph = (struct pcic_handle *)pch; 2486 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2487 u_int8_t power, intr; 2488 2489 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2490 2491 /* reset signal asserting... */ 2492 2493 intr = Pcic_read(ph, PCIC_INTR); 2494 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2495 Pcic_write(ph, PCIC_INTR, intr); 2496 delay(2 * 1000); 2497 2498 /* power down the socket */ 2499 power = Pcic_read(ph, PCIC_PWRCTL); 2500 power &= ~PCIC_PWRCTL_OE; 2501 Pcic_write(ph, PCIC_PWRCTL, power); 2502 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2503 /* 2504 * wait 300ms until power fails (Tpf). 2505 */ 2506 #if 0 /* XXX called on interrupt context */ 2507 DELAY_MS(300, sc); 2508 #else 2509 delay(300 * 1000); 2510 #endif 2511 } 2512 2513 /* 2514 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2515 * 2516 * This function detects whether a card is in the slot or not. 2517 * If a card is inserted, return 1. Otherwise, return 0. 2518 */ 2519 STATIC int 2520 pccbb_pcmcia_card_detect(pch) 2521 pcmcia_chipset_handle_t pch; 2522 { 2523 struct pcic_handle *ph = (struct pcic_handle *)pch; 2524 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2525 2526 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2527 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2528 } 2529 2530 #if 0 2531 STATIC int 2532 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2533 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2534 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2535 #endif 2536 /* 2537 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2538 * bus_size_t size, 2539 * struct pcmcia_mem_handle *pcmhp) 2540 * 2541 * This function only allocates memory region for pccard. This 2542 * function never maps the allocated region to pccard memory area. 2543 * 2544 * XXX: Why the argument of start address is not in? 2545 */ 2546 STATIC int 2547 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2548 pcmcia_chipset_handle_t pch; 2549 bus_size_t size; 2550 struct pcmcia_mem_handle *pcmhp; 2551 { 2552 struct pcic_handle *ph = (struct pcic_handle *)pch; 2553 bus_space_handle_t memh; 2554 bus_addr_t addr; 2555 bus_size_t sizepg; 2556 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2557 #if rbus 2558 rbus_tag_t rb; 2559 #endif 2560 2561 /* out of sc->memh, allocate as many pages as necessary */ 2562 2563 /* convert size to PCIC pages */ 2564 /* 2565 * This is not enough; when the requested region is on the page 2566 * boundaries, this may calculate wrong result. 2567 */ 2568 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2569 #if 0 2570 if (sizepg > PCIC_MAX_MEM_PAGES) { 2571 return 1; 2572 } 2573 #endif 2574 2575 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2576 return 1; 2577 } 2578 2579 addr = 0; /* XXX gcc -Wuninitialized */ 2580 2581 #if rbus 2582 rb = sc->sc_rbus_memt; 2583 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2584 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2585 &addr, &memh)) { 2586 return 1; 2587 } 2588 #else 2589 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2590 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2591 0, /* boundary */ 2592 0, /* flags */ 2593 &addr, &memh)) { 2594 return 1; 2595 } 2596 #endif 2597 2598 DPRINTF( 2599 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2600 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2601 2602 pcmhp->memt = sc->sc_memt; 2603 pcmhp->memh = memh; 2604 pcmhp->addr = addr; 2605 pcmhp->size = size; 2606 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2607 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2608 pcmhp->mhandle = 0; 2609 /* No offset??? Funny. */ 2610 2611 return 0; 2612 } 2613 2614 /* 2615 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2616 * struct pcmcia_mem_handle *pcmhp) 2617 * 2618 * This function release the memory space allocated by the function 2619 * pccbb_pcmcia_mem_alloc(). 2620 */ 2621 STATIC void 2622 pccbb_pcmcia_mem_free(pch, pcmhp) 2623 pcmcia_chipset_handle_t pch; 2624 struct pcmcia_mem_handle *pcmhp; 2625 { 2626 #if rbus 2627 struct pcic_handle *ph = (struct pcic_handle *)pch; 2628 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2629 2630 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2631 #else 2632 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2633 #endif 2634 } 2635 2636 /* 2637 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2638 * 2639 * This function release the memory space allocated by the function 2640 * pccbb_pcmcia_mem_alloc(). 2641 */ 2642 STATIC void 2643 pccbb_pcmcia_do_mem_map(ph, win) 2644 struct pcic_handle *ph; 2645 int win; 2646 { 2647 int regbase_win; 2648 bus_addr_t phys_addr; 2649 bus_addr_t phys_end; 2650 2651 #define PCIC_SMM_START_LOW 0 2652 #define PCIC_SMM_START_HIGH 1 2653 #define PCIC_SMM_STOP_LOW 2 2654 #define PCIC_SMM_STOP_HIGH 3 2655 #define PCIC_CMA_LOW 4 2656 #define PCIC_CMA_HIGH 5 2657 2658 u_int8_t start_low, start_high = 0; 2659 u_int8_t stop_low, stop_high; 2660 u_int8_t off_low, off_high; 2661 u_int8_t mem_window; 2662 int reg; 2663 2664 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2665 int mem8 = 2666 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2667 || (kind == PCMCIA_MEM_ATTR); 2668 2669 regbase_win = 0x10 + win * 0x08; 2670 2671 phys_addr = ph->mem[win].addr; 2672 phys_end = phys_addr + ph->mem[win].size; 2673 2674 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2675 phys_addr, phys_end, ph->mem[win].offset)); 2676 2677 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2678 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2679 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2680 2681 /* bit 19:12 */ 2682 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2683 /* bit 23:20 and bit 7 on */ 2684 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2685 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2686 /* bit 31:24, for 32-bit address */ 2687 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2688 2689 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2690 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2691 2692 if (((struct pccbb_softc *)ph-> 2693 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2694 Pcic_write(ph, 0x40 + win, mem_window); 2695 } 2696 2697 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2698 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2699 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2700 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2701 2702 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2703 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2704 2705 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2706 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2707 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2708 | ((kind == PCMCIA_MEM_ATTR) ? 2709 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2710 2711 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2712 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2713 2714 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2715 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2716 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2717 2718 #if defined CBB_DEBUG 2719 { 2720 int r1, r2, r3, r4, r5, r6, r7 = 0; 2721 2722 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2723 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2724 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2725 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2726 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2727 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2728 if (((struct pccbb_softc *)(ph-> 2729 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2730 r7 = Pcic_read(ph, 0x40 + win); 2731 } 2732 2733 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2734 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2735 if (((struct pccbb_softc *)(ph-> 2736 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2737 DPRINTF((" %02x", r7)); 2738 } 2739 DPRINTF(("\n")); 2740 } 2741 #endif 2742 } 2743 2744 /* 2745 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2746 * bus_addr_t card_addr, bus_size_t size, 2747 * struct pcmcia_mem_handle *pcmhp, 2748 * bus_addr_t *offsetp, int *windowp) 2749 * 2750 * This function maps memory space allocated by the function 2751 * pccbb_pcmcia_mem_alloc(). 2752 */ 2753 STATIC int 2754 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2755 pcmcia_chipset_handle_t pch; 2756 int kind; 2757 bus_addr_t card_addr; 2758 bus_size_t size; 2759 struct pcmcia_mem_handle *pcmhp; 2760 bus_addr_t *offsetp; 2761 int *windowp; 2762 { 2763 struct pcic_handle *ph = (struct pcic_handle *)pch; 2764 bus_addr_t busaddr; 2765 long card_offset; 2766 int win; 2767 2768 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2769 if ((ph->memalloc & (1 << win)) == 0) { 2770 ph->memalloc |= (1 << win); 2771 break; 2772 } 2773 } 2774 2775 if (win == PCIC_MEM_WINS) { 2776 return 1; 2777 } 2778 2779 *windowp = win; 2780 2781 /* XXX this is pretty gross */ 2782 2783 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2784 panic("pccbb_pcmcia_mem_map memt is bogus"); 2785 } 2786 2787 busaddr = pcmhp->addr; 2788 2789 /* 2790 * compute the address offset to the pcmcia address space for the 2791 * pcic. this is intentionally signed. The masks and shifts below 2792 * will cause TRT to happen in the pcic registers. Deal with making 2793 * sure the address is aligned, and return the alignment offset. 2794 */ 2795 2796 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2797 card_addr -= *offsetp; 2798 2799 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2800 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2801 (u_long) card_addr)); 2802 2803 /* 2804 * include the offset in the size, and decrement size by one, since 2805 * the hw wants start/stop 2806 */ 2807 size += *offsetp - 1; 2808 2809 card_offset = (((long)card_addr) - ((long)busaddr)); 2810 2811 ph->mem[win].addr = busaddr; 2812 ph->mem[win].size = size; 2813 ph->mem[win].offset = card_offset; 2814 ph->mem[win].kind = kind; 2815 2816 pccbb_pcmcia_do_mem_map(ph, win); 2817 2818 return 0; 2819 } 2820 2821 /* 2822 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2823 * int window) 2824 * 2825 * This function unmaps memory space which mapped by the function 2826 * pccbb_pcmcia_mem_map(). 2827 */ 2828 STATIC void 2829 pccbb_pcmcia_mem_unmap(pch, window) 2830 pcmcia_chipset_handle_t pch; 2831 int window; 2832 { 2833 struct pcic_handle *ph = (struct pcic_handle *)pch; 2834 int reg; 2835 2836 if (window >= PCIC_MEM_WINS) { 2837 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2838 } 2839 2840 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2841 reg &= ~(1 << window); 2842 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2843 2844 ph->memalloc &= ~(1 << window); 2845 } 2846 2847 #if defined PCCBB_PCMCIA_POLL 2848 struct pccbb_poll_str { 2849 void *arg; 2850 int (*func) __P((void *)); 2851 int level; 2852 struct pcic_handle *ph; 2853 int count; 2854 int num; 2855 struct callout poll_ch; 2856 }; 2857 2858 static struct pccbb_poll_str pccbb_poll[10]; 2859 static int pccbb_poll_n = 0; 2860 2861 static void pccbb_pcmcia_poll __P((void *arg)); 2862 2863 static void 2864 pccbb_pcmcia_poll(arg) 2865 void *arg; 2866 { 2867 struct pccbb_poll_str *poll = arg; 2868 struct pcic_handle *ph = poll->ph; 2869 struct pccbb_softc *sc = ph->sc; 2870 int s; 2871 u_int32_t spsr; /* socket present-state reg */ 2872 2873 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2874 switch (poll->level) { 2875 case IPL_NET: 2876 s = splnet(); 2877 break; 2878 case IPL_BIO: 2879 s = splbio(); 2880 break; 2881 case IPL_TTY: /* fallthrough */ 2882 default: 2883 s = spltty(); 2884 break; 2885 } 2886 2887 spsr = 2888 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2889 CB_SOCKET_STAT); 2890 2891 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2892 if (!(spsr & 0x40)) /* CINT low */ 2893 #else 2894 if (1) 2895 #endif 2896 { 2897 if ((*poll->func) (poll->arg) > 0) { 2898 ++poll->count; 2899 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2900 #if defined LEVEL2 2901 } else { 2902 printf("intr: miss! 0x%x\n", spsr); 2903 #endif 2904 } 2905 } 2906 splx(s); 2907 } 2908 #endif /* defined CB_PCMCIA_POLL */ 2909 2910 /* 2911 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2912 * struct pcmcia_function *pf, 2913 * int ipl, 2914 * int (*func)(void *), 2915 * void *arg); 2916 * 2917 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2918 */ 2919 STATIC void * 2920 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2921 pcmcia_chipset_handle_t pch; 2922 struct pcmcia_function *pf; 2923 int ipl; 2924 int (*func) __P((void *)); 2925 void *arg; 2926 { 2927 struct pcic_handle *ph = (struct pcic_handle *)pch; 2928 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2929 2930 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2931 /* what should I do? */ 2932 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2933 DPRINTF( 2934 ("%s does not provide edge nor pulse interrupt\n", 2935 sc->sc_dev.dv_xname)); 2936 return NULL; 2937 } 2938 /* 2939 * XXX Noooooo! The interrupt flag must set properly!! 2940 * dumb pcmcia driver!! 2941 */ 2942 } 2943 2944 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2945 } 2946 2947 /* 2948 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2949 * void *ih) 2950 * 2951 * This function disables PC-Card interrupt. 2952 */ 2953 STATIC void 2954 pccbb_pcmcia_intr_disestablish(pch, ih) 2955 pcmcia_chipset_handle_t pch; 2956 void *ih; 2957 { 2958 struct pcic_handle *ph = (struct pcic_handle *)pch; 2959 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2960 2961 pccbb_intr_disestablish(sc, ih); 2962 } 2963 2964 #if rbus 2965 /* 2966 * static int 2967 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2968 * bus_addr_t addr, bus_size_t size, 2969 * bus_addr_t mask, bus_size_t align, 2970 * int flags, bus_addr_t *addrp; 2971 * bus_space_handle_t *bshp) 2972 * 2973 * This function allocates a portion of memory or io space for 2974 * clients. This function is called from CardBus card drivers. 2975 */ 2976 static int 2977 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2978 cardbus_chipset_tag_t ct; 2979 rbus_tag_t rb; 2980 bus_addr_t addr; 2981 bus_size_t size; 2982 bus_addr_t mask; 2983 bus_size_t align; 2984 int flags; 2985 bus_addr_t *addrp; 2986 bus_space_handle_t *bshp; 2987 { 2988 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2989 2990 DPRINTF( 2991 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2992 addr, size, mask, align)); 2993 2994 if (align == 0) { 2995 align = size; 2996 } 2997 2998 if (rb->rb_bt == sc->sc_memt) { 2999 if (align < 16) { 3000 return 1; 3001 } 3002 /* 3003 * XXX: align more than 0x1000 to avoid overwrapping 3004 * memory windows for two or more devices. 0x1000 3005 * means memory window's granularity. 3006 * 3007 * Two or more devices should be able to share same 3008 * memory window region. However, overrapping memory 3009 * window is not good because some devices, such as 3010 * 3Com 3C575[BC], have a broken address decoder and 3011 * intrude other's memory region. 3012 */ 3013 if (align < 0x1000) { 3014 align = 0x1000; 3015 } 3016 } else if (rb->rb_bt == sc->sc_iot) { 3017 if (align < 4) { 3018 return 1; 3019 } 3020 /* XXX: hack for avoiding ISA image */ 3021 if (mask < 0x0100) { 3022 mask = 0x3ff; 3023 addr = 0x300; 3024 } 3025 3026 } else { 3027 DPRINTF( 3028 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 3029 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 3030 return 1; 3031 /* XXX: panic here? */ 3032 } 3033 3034 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3035 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3036 return 1; 3037 } 3038 3039 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3040 3041 return 0; 3042 } 3043 3044 /* 3045 * static int 3046 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3047 * bus_space_handle_t *bshp, bus_size_t size); 3048 * 3049 * This function is called from CardBus card drivers. 3050 */ 3051 static int 3052 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3053 cardbus_chipset_tag_t ct; 3054 rbus_tag_t rb; 3055 bus_space_handle_t bsh; 3056 bus_size_t size; 3057 { 3058 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3059 bus_space_tag_t bt = rb->rb_bt; 3060 3061 pccbb_close_win(sc, bt, bsh, size); 3062 3063 if (bt == sc->sc_memt) { 3064 } else if (bt == sc->sc_iot) { 3065 } else { 3066 return 1; 3067 /* XXX: panic here? */ 3068 } 3069 3070 return rbus_space_free(rb, bsh, size, NULL); 3071 } 3072 #endif /* rbus */ 3073 3074 #if rbus 3075 3076 static int 3077 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3078 struct pccbb_softc *sc; 3079 bus_space_tag_t bst; 3080 bus_addr_t addr; 3081 bus_size_t size; 3082 bus_space_handle_t bsh; 3083 int flags; 3084 { 3085 struct pccbb_win_chain_head *head; 3086 bus_addr_t align; 3087 3088 head = &sc->sc_iowindow; 3089 align = 0x04; 3090 if (sc->sc_memt == bst) { 3091 head = &sc->sc_memwindow; 3092 align = 0x1000; 3093 DPRINTF(("using memory window, %x %x %x\n\n", 3094 sc->sc_iot, sc->sc_memt, bst)); 3095 } 3096 3097 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3098 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3099 sc->sc_dev.dv_xname, 3100 (head == &sc->sc_memwindow) ? "mem" : "io"); 3101 } 3102 pccbb_winset(align, sc, bst); 3103 3104 return 0; 3105 } 3106 3107 static int 3108 pccbb_close_win(sc, bst, bsh, size) 3109 struct pccbb_softc *sc; 3110 bus_space_tag_t bst; 3111 bus_space_handle_t bsh; 3112 bus_size_t size; 3113 { 3114 struct pccbb_win_chain_head *head; 3115 bus_addr_t align; 3116 3117 head = &sc->sc_iowindow; 3118 align = 0x04; 3119 if (sc->sc_memt == bst) { 3120 head = &sc->sc_memwindow; 3121 align = 0x1000; 3122 } 3123 3124 if (pccbb_winlist_delete(head, bsh, size)) { 3125 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3126 sc->sc_dev.dv_xname, 3127 (head == &sc->sc_memwindow) ? "mem" : "io"); 3128 } 3129 pccbb_winset(align, sc, bst); 3130 3131 return 0; 3132 } 3133 3134 static int 3135 pccbb_winlist_insert(head, start, size, bsh, flags) 3136 struct pccbb_win_chain_head *head; 3137 bus_addr_t start; 3138 bus_size_t size; 3139 bus_space_handle_t bsh; 3140 int flags; 3141 { 3142 struct pccbb_win_chain *chainp, *elem; 3143 3144 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3145 M_NOWAIT)) == NULL) 3146 return (1); /* fail */ 3147 3148 elem->wc_start = start; 3149 elem->wc_end = start + (size - 1); 3150 elem->wc_handle = bsh; 3151 elem->wc_flags = flags; 3152 3153 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3154 chainp = TAILQ_NEXT(chainp, wc_list)) { 3155 if (chainp->wc_end < start) 3156 continue; 3157 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3158 return (0); 3159 } 3160 3161 TAILQ_INSERT_TAIL(head, elem, wc_list); 3162 return (0); 3163 } 3164 3165 static int 3166 pccbb_winlist_delete(head, bsh, size) 3167 struct pccbb_win_chain_head *head; 3168 bus_space_handle_t bsh; 3169 bus_size_t size; 3170 { 3171 struct pccbb_win_chain *chainp; 3172 3173 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3174 chainp = TAILQ_NEXT(chainp, wc_list)) { 3175 if (chainp->wc_handle != bsh) 3176 continue; 3177 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3178 printf("pccbb_winlist_delete: window 0x%lx size " 3179 "inconsistent: 0x%lx, 0x%lx\n", 3180 (unsigned long)chainp->wc_start, 3181 (unsigned long)(chainp->wc_end - chainp->wc_start), 3182 (unsigned long)(size - 1)); 3183 return 1; 3184 } 3185 3186 TAILQ_REMOVE(head, chainp, wc_list); 3187 free(chainp, M_DEVBUF); 3188 3189 return 0; 3190 } 3191 3192 return 1; /* fail: no candidate to remove */ 3193 } 3194 3195 static void 3196 pccbb_winset(align, sc, bst) 3197 bus_addr_t align; 3198 struct pccbb_softc *sc; 3199 bus_space_tag_t bst; 3200 { 3201 pci_chipset_tag_t pc; 3202 pcitag_t tag; 3203 bus_addr_t mask = ~(align - 1); 3204 struct { 3205 cardbusreg_t win_start; 3206 cardbusreg_t win_limit; 3207 int win_flags; 3208 } win[2]; 3209 struct pccbb_win_chain *chainp; 3210 int offs; 3211 3212 win[0].win_start = win[1].win_start = 0xffffffff; 3213 win[0].win_limit = win[1].win_limit = 0; 3214 win[0].win_flags = win[1].win_flags = 0; 3215 3216 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3217 offs = 0x2c; 3218 if (sc->sc_memt == bst) { 3219 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3220 offs = 0x1c; 3221 } 3222 3223 if (chainp != NULL) { 3224 win[0].win_start = chainp->wc_start & mask; 3225 win[0].win_limit = chainp->wc_end & mask; 3226 win[0].win_flags = chainp->wc_flags; 3227 chainp = TAILQ_NEXT(chainp, wc_list); 3228 } 3229 3230 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3231 if (win[1].win_start == 0xffffffff) { 3232 /* window 1 is not used */ 3233 if ((win[0].win_flags == chainp->wc_flags) && 3234 (win[0].win_limit + align >= 3235 (chainp->wc_start & mask))) { 3236 /* concatenate */ 3237 win[0].win_limit = chainp->wc_end & mask; 3238 } else { 3239 /* make new window */ 3240 win[1].win_start = chainp->wc_start & mask; 3241 win[1].win_limit = chainp->wc_end & mask; 3242 win[1].win_flags = chainp->wc_flags; 3243 } 3244 continue; 3245 } 3246 3247 /* Both windows are engaged. */ 3248 if (win[0].win_flags == win[1].win_flags) { 3249 /* same flags */ 3250 if (win[0].win_flags == chainp->wc_flags) { 3251 if (win[1].win_start - (win[0].win_limit + 3252 align) < 3253 (chainp->wc_start & mask) - 3254 ((chainp->wc_end & mask) + align)) { 3255 /* 3256 * merge window 0 and 1, and set win1 3257 * to chainp 3258 */ 3259 win[0].win_limit = win[1].win_limit; 3260 win[1].win_start = 3261 chainp->wc_start & mask; 3262 win[1].win_limit = 3263 chainp->wc_end & mask; 3264 } else { 3265 win[1].win_limit = 3266 chainp->wc_end & mask; 3267 } 3268 } else { 3269 /* different flags */ 3270 3271 /* concatenate win0 and win1 */ 3272 win[0].win_limit = win[1].win_limit; 3273 /* allocate win[1] to new space */ 3274 win[1].win_start = chainp->wc_start & mask; 3275 win[1].win_limit = chainp->wc_end & mask; 3276 win[1].win_flags = chainp->wc_flags; 3277 } 3278 } else { 3279 /* the flags of win[0] and win[1] is different */ 3280 if (win[0].win_flags == chainp->wc_flags) { 3281 win[0].win_limit = chainp->wc_end & mask; 3282 /* 3283 * XXX this creates overlapping windows, so 3284 * what should the poor bridge do if one is 3285 * cachable, and the other is not? 3286 */ 3287 printf("%s: overlapping windows\n", 3288 sc->sc_dev.dv_xname); 3289 } else { 3290 win[1].win_limit = chainp->wc_end & mask; 3291 } 3292 } 3293 } 3294 3295 pc = sc->sc_pc; 3296 tag = sc->sc_tag; 3297 pci_conf_write(pc, tag, offs, win[0].win_start); 3298 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3299 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3300 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3301 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3302 pci_conf_read(pc, tag, offs), 3303 pci_conf_read(pc, tag, offs + 4) + align, 3304 pci_conf_read(pc, tag, offs + 8), 3305 pci_conf_read(pc, tag, offs + 12) + align)); 3306 3307 if (bst == sc->sc_memt) { 3308 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3309 3310 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3311 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3312 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3313 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3314 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3315 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3316 } 3317 } 3318 3319 #endif /* rbus */ 3320 3321 static void 3322 pccbb_powerhook(why, arg) 3323 int why; 3324 void *arg; 3325 { 3326 struct pccbb_softc *sc = arg; 3327 pcireg_t reg; 3328 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3329 bus_space_handle_t base_memh = sc->sc_base_memh; 3330 3331 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3332 3333 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3334 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3335 if (sc->sc_pil_intr_enable) { 3336 (void)pccbbintr_function(sc); 3337 } 3338 sc->sc_pil_intr_enable = 0; 3339 3340 /* ToDo: deactivate or suspend child devices */ 3341 3342 } 3343 3344 if (why == PWR_RESUME) { 3345 if (sc->sc_pwrmgt_offs != 0) { 3346 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3347 sc->sc_pwrmgt_offs + 4); 3348 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3349 reg & 0x100) { 3350 /* powrstate != D0 */ 3351 3352 printf("%s going back to D0 mode\n", 3353 sc->sc_dev.dv_xname); 3354 reg &= ~PCI_PMCSR_STATE_MASK; 3355 reg |= PCI_PMCSR_STATE_D0; 3356 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3357 pci_conf_write(sc->sc_pc, sc->sc_tag, 3358 sc->sc_pwrmgt_offs + 4, reg); 3359 3360 pci_conf_write(sc->sc_pc, sc->sc_tag, 3361 PCI_SOCKBASE, sc->sc_sockbase); 3362 pci_conf_write(sc->sc_pc, sc->sc_tag, 3363 PCI_BUSNUM, sc->sc_busnum); 3364 pccbb_chipinit(sc); 3365 /* setup memory and io space window for CB */ 3366 pccbb_winset(0x1000, sc, sc->sc_memt); 3367 pccbb_winset(0x04, sc, sc->sc_iot); 3368 } 3369 } 3370 3371 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3372 /* BIOS did not recover this register */ 3373 pci_conf_write (sc->sc_pc, sc->sc_tag, 3374 PCI_SOCKBASE, sc->sc_sockbase); 3375 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3376 /* BIOS did not recover this register */ 3377 pci_conf_write (sc->sc_pc, sc->sc_tag, 3378 PCI_BUSNUM, sc->sc_busnum); 3379 /* CSC Interrupt: Card detect interrupt on */ 3380 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3381 /* Card detect intr is turned on. */ 3382 reg |= CB_SOCKET_MASK_CD; 3383 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3384 /* reset interrupt */ 3385 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3386 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3387 3388 /* 3389 * check for card insertion or removal during suspend period. 3390 * XXX: the code can't cope with card swap (remove then 3391 * insert). how can we detect such situation? 3392 */ 3393 (void)pccbbintr(sc); 3394 3395 sc->sc_pil_intr_enable = 1; 3396 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3397 3398 /* ToDo: activate or wakeup child devices */ 3399 } 3400 } 3401
Indexes created Wed Oct 15 07:09:58 GMT 2025