pccbb.c revision 1.90
1 /* $NetBSD: pccbb.c,v 1.90 2003/06/19 10:48:58 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.90 2003/06/19 10:48:58 msaitoh Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, NULL, NULL); 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 332 /* Ricoh chips */ 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 346 /* Toshiba products */ 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 348 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 350 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 356 /* Cirrus Logic products */ 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 362 /* sentinel, or Generic chip */ 363 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 364 }; 365 366 static int 367 cb_chipset(pci_id, flagp) 368 u_int32_t pci_id; 369 int *flagp; 370 { 371 const struct yenta_chipinfo *yc; 372 373 /* Loop over except the last default entry. */ 374 for (yc = yc_chipsets; yc < yc_chipsets + 375 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 376 if (pci_id == yc->yc_id) 377 break; 378 379 if (flagp != NULL) 380 *flagp = yc->yc_flags; 381 382 return (yc->yc_chiptype); 383 } 384 385 static void 386 pccbb_shutdown(void *arg) 387 { 388 struct pccbb_softc *sc = arg; 389 pcireg_t command; 390 391 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 392 393 /* 394 * turn off power 395 * 396 * XXX - do not turn off power if chipset is TI 113X because 397 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 398 */ 399 if (sc->sc_chipset != CB_TI113X) { 400 pccbb_power((cardbus_chipset_tag_t)sc, 401 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 402 } 403 404 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 405 0); 406 407 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 408 409 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 410 PCI_COMMAND_MASTER_ENABLE); 411 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 412 413 } 414 415 void 416 pccbbattach(parent, self, aux) 417 struct device *parent; 418 struct device *self; 419 void *aux; 420 { 421 struct pccbb_softc *sc = (void *)self; 422 struct pci_attach_args *pa = aux; 423 pci_chipset_tag_t pc = pa->pa_pc; 424 pcireg_t busreg, reg, sock_base; 425 bus_addr_t sockbase; 426 char devinfo[256]; 427 int flags; 428 int pwrmgt_offs; 429 430 #ifdef __HAVE_PCCBB_ATTACH_HOOK 431 pccbb_attach_hook(parent, self, pa); 432 #endif 433 434 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 435 436 pci_devinfo(pa->pa_id, 0, 0, devinfo); 437 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 438 #ifdef CBB_DEBUG 439 printf(" (chipflags %x)", flags); 440 #endif 441 printf("\n"); 442 443 TAILQ_INIT(&sc->sc_memwindow); 444 TAILQ_INIT(&sc->sc_iowindow); 445 446 #if rbus 447 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 448 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 449 450 #if 0 451 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 452 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 453 #endif 454 #endif /* rbus */ 455 456 sc->sc_flags &= ~CBB_MEMHMAPPED; 457 458 /* power management: set D0 state */ 459 sc->sc_pwrmgt_offs = 0; 460 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 461 &pwrmgt_offs, 0)) { 462 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 463 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 464 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 465 reg &= ~PCI_PMCSR_STATE_MASK; 466 reg |= PCI_PMCSR_STATE_D0; 467 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 468 pci_conf_write(pc, pa->pa_tag, 469 pwrmgt_offs + PCI_PMCSR, reg); 470 } 471 472 sc->sc_pwrmgt_offs = pwrmgt_offs; 473 } 474 475 /* 476 * MAP socket registers and ExCA registers on memory-space 477 * When no valid address is set on socket base registers (on pci 478 * config space), get it not polite way. 479 */ 480 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 481 482 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 483 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 484 /* The address must be valid. */ 485 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 486 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 487 printf("%s: can't map socket base address 0x%x\n", 488 sc->sc_dev.dv_xname, sock_base); 489 /* 490 * I think it's funny: socket base registers must be 491 * mapped on memory space, but ... 492 */ 493 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 494 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 495 NULL)) { 496 printf("%s: can't map socket base address" 497 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 498 (unsigned long)sockbase); 499 /* give up... allocate reg space via rbus. */ 500 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 501 } else 502 sc->sc_flags |= CBB_MEMHMAPPED; 503 } else { 504 DPRINTF(("%s: socket base address 0x%lx\n", 505 sc->sc_dev.dv_xname, sockbase)); 506 sc->sc_flags |= CBB_MEMHMAPPED; 507 } 508 } 509 510 sc->sc_mem_start = 0; /* XXX */ 511 sc->sc_mem_end = 0xffffffff; /* XXX */ 512 513 /* 514 * When interrupt isn't routed correctly, give up probing cbb and do 515 * not kill pcic-compatible port. 516 */ 517 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 518 printf("%s: NOT USED because of unconfigured interrupt\n", 519 sc->sc_dev.dv_xname); 520 return; 521 } 522 523 /* 524 * When bus number isn't set correctly, give up using 32-bit CardBus 525 * mode. 526 */ 527 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 528 #if notyet 529 if (((busreg >> 8) & 0xff) == 0) { 530 printf("%s: CardBus support disabled because of unconfigured bus number\n", 531 sc->sc_dev.dv_xname); 532 flags |= PCCBB_PCMCIA_16BITONLY; 533 } 534 #endif 535 536 /* pccbb_machdep.c end */ 537 538 #if defined CBB_DEBUG 539 { 540 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 541 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 542 intrname[pa->pa_intrpin], pa->pa_intrline); 543 } 544 #endif 545 546 /* setup softc */ 547 sc->sc_pc = pc; 548 sc->sc_iot = pa->pa_iot; 549 sc->sc_memt = pa->pa_memt; 550 sc->sc_dmat = pa->pa_dmat; 551 sc->sc_tag = pa->pa_tag; 552 sc->sc_function = pa->pa_function; 553 sc->sc_sockbase = sock_base; 554 sc->sc_busnum = busreg; 555 556 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 557 558 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 559 560 shutdownhook_establish(pccbb_shutdown, sc); 561 562 /* Disable legacy register mapping. */ 563 switch (sc->sc_chipset) { 564 case CB_RX5C46X: /* fallthrough */ 565 #if 0 566 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 567 case CB_RX5C47X: 568 #endif 569 /* 570 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 571 * cannot be disabled by substituting 0 into PCI_LEGACY 572 * register. Ricoh CardBus bridges have special bits on Bridge 573 * control reg (addr 0x3e on PCI config space). 574 */ 575 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 576 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 577 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 578 break; 579 580 default: 581 /* XXX I don't know proper way to kill legacy I/O. */ 582 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 583 break; 584 } 585 586 config_defer(self, pccbb_pci_callback); 587 } 588 589 590 591 592 /* 593 * static void pccbb_pci_callback(struct device *self) 594 * 595 * The actual attach routine: get memory space for YENTA register 596 * space, setup YENTA register and route interrupt. 597 * 598 * This function should be deferred because this device may obtain 599 * memory space dynamically. This function must avoid obtaining 600 * memory area which has already kept for another device. 601 */ 602 static void 603 pccbb_pci_callback(self) 604 struct device *self; 605 { 606 struct pccbb_softc *sc = (void *)self; 607 pci_chipset_tag_t pc = sc->sc_pc; 608 pci_intr_handle_t ih; 609 const char *intrstr = NULL; 610 bus_addr_t sockbase; 611 struct cbslot_attach_args cba; 612 struct pcmciabus_attach_args paa; 613 struct cardslot_attach_args caa; 614 struct cardslot_softc *csc; 615 616 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 617 /* The socket registers aren't mapped correctly. */ 618 #if rbus 619 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 620 (sc->sc_chipset == CB_RX5C47X 621 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 622 0, &sockbase, &sc->sc_base_memh)) { 623 return; 624 } 625 sc->sc_base_memt = sc->sc_memt; 626 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 627 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 628 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 629 PCI_SOCKBASE))); 630 #else 631 sc->sc_base_memt = sc->sc_memt; 632 #if !defined CBB_PCI_BASE 633 #define CBB_PCI_BASE 0x20000000 634 #endif 635 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 636 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 637 /* cannot allocate memory space */ 638 return; 639 } 640 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 641 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 642 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 643 sc->sc_tag, PCI_SOCKBASE))); 644 sc->sc_sockbase = sockbase; 645 #endif 646 sc->sc_flags |= CBB_MEMHMAPPED; 647 } 648 649 /* bus bridge initialization */ 650 pccbb_chipinit(sc); 651 652 /* clear data structure for child device interrupt handlers */ 653 LIST_INIT(&sc->sc_pil); 654 sc->sc_pil_intr_enable = 1; 655 656 /* Map and establish the interrupt. */ 657 if (pci_intr_map(&sc->sc_pa, &ih)) { 658 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 659 return; 660 } 661 intrstr = pci_intr_string(pc, ih); 662 663 /* 664 * XXX pccbbintr should be called under the priority lower 665 * than any other hard interrputs. 666 */ 667 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 668 669 if (sc->sc_ih == NULL) { 670 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 671 if (intrstr != NULL) { 672 printf(" at %s", intrstr); 673 } 674 printf("\n"); 675 return; 676 } 677 678 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 679 powerhook_establish(pccbb_powerhook, sc); 680 681 { 682 u_int32_t sockstat; 683 684 sockstat = bus_space_read_4(sc->sc_base_memt, 685 sc->sc_base_memh, CB_SOCKET_STAT); 686 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 687 sc->sc_flags |= CBB_CARDEXIST; 688 } 689 } 690 691 /* 692 * attach cardbus 693 */ 694 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 695 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 696 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 697 698 /* initialize cbslot_attach */ 699 cba.cba_busname = "cardbus"; 700 cba.cba_iot = sc->sc_iot; 701 cba.cba_memt = sc->sc_memt; 702 cba.cba_dmat = sc->sc_dmat; 703 cba.cba_bus = (busreg >> 8) & 0x0ff; 704 cba.cba_cc = (void *)sc; 705 cba.cba_cf = &pccbb_funcs; 706 cba.cba_intrline = sc->sc_pa.pa_intrline; 707 708 #if rbus 709 cba.cba_rbus_iot = sc->sc_rbus_iot; 710 cba.cba_rbus_memt = sc->sc_rbus_memt; 711 #endif 712 713 cba.cba_cacheline = PCI_CACHELINE(bhlc); 714 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 715 716 if (bootverbose) { 717 printf("%s: cacheline 0x%x lattimer 0x%x\n", 718 sc->sc_dev.dv_xname, cba.cba_cacheline, 719 cba.cba_lattimer); 720 printf("%s: bhlc 0x%x lscp 0x%x\n", 721 sc->sc_dev.dv_xname, bhlc, busreg); 722 } 723 #if defined SHOW_REGS 724 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 725 sc->sc_base_memh); 726 #endif 727 } 728 729 pccbb_pcmcia_attach_setup(sc, &paa); 730 caa.caa_cb_attach = NULL; 731 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 732 caa.caa_cb_attach = &cba; 733 } 734 caa.caa_16_attach = &paa; 735 caa.caa_ph = &sc->sc_pcmcia_h; 736 737 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 738 DPRINTF(("pccbbattach: found cardslot\n")); 739 sc->sc_csc = csc; 740 } 741 742 return; 743 } 744 745 746 747 748 749 /* 750 * static void pccbb_chipinit(struct pccbb_softc *sc) 751 * 752 * This function initialize YENTA chip registers listed below: 753 * 1) PCI command reg, 754 * 2) PCI and CardBus latency timer, 755 * 3) route PCI interrupt, 756 * 4) close all memory and io windows. 757 * 5) turn off bus power. 758 * 6) card detect interrupt on. 759 * 7) clear interrupt 760 */ 761 static void 762 pccbb_chipinit(sc) 763 struct pccbb_softc *sc; 764 { 765 pci_chipset_tag_t pc = sc->sc_pc; 766 pcitag_t tag = sc->sc_tag; 767 bus_space_tag_t bmt = sc->sc_base_memt; 768 bus_space_handle_t bmh = sc->sc_base_memh; 769 pcireg_t reg; 770 771 /* 772 * Set PCI command reg. 773 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 776 /* I believe it is harmless. */ 777 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 778 PCI_COMMAND_MASTER_ENABLE); 779 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 780 781 /* 782 * Set CardBus latency timer. 783 */ 784 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 785 if (PCI_CB_LATENCY(reg) < 0x20) { 786 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 787 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 788 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 789 } 790 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 791 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 792 793 /* 794 * Set PCI latency timer. 795 */ 796 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 797 if (PCI_LATTIMER(reg) < 0x10) { 798 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 799 reg |= (0x10 << PCI_LATTIMER_SHIFT); 800 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 801 } 802 DPRINTF(("PCI latency timer 0x%x (%x)\n", 803 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 804 805 806 /* Route functional interrupts to PCI. */ 807 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 808 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 809 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 810 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 811 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 812 813 switch (sc->sc_chipset) { 814 case CB_TI113X: 815 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 816 /* This bit is shared, but may read as 0 on some chips, so set 817 it explicitly on both functions. */ 818 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 819 /* CSC intr enable */ 820 reg |= PCI113X_CBCTRL_PCI_CSC; 821 /* functional intr prohibit | prohibit ISA routing */ 822 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 823 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 824 break; 825 826 case CB_TI12XX: 827 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 828 reg |= PCI12XX_SYSCTRL_VCCPROT; 829 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 830 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 831 reg |= PCI12XX_CBCTRL_CSC; 832 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 833 break; 834 835 case CB_TOPIC95B: 836 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 837 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 838 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 839 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 840 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 841 sc->sc_dev.dv_xname, reg)); 842 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 843 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 844 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 845 DPRINTF(("0x%x\n", reg)); 846 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 847 break; 848 849 case CB_TOPIC97: 850 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 851 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 852 sc->sc_dev.dv_xname, reg)); 853 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 854 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 855 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 856 reg |= TOPIC97_SLOT_CTRL_PCIINT; 857 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 858 DPRINTF(("0x%x\n", reg)); 859 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 860 /* make sure to assert LV card support bits */ 861 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 862 0x800 + 0x3e, 863 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 864 0x800 + 0x3e) | 0x03); 865 break; 866 } 867 868 /* Close all memory and I/O windows. */ 869 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 870 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 871 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 872 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 873 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 874 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 875 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 876 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 877 878 /* reset 16-bit pcmcia bus */ 879 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 880 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 881 882 /* turn off power */ 883 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 884 885 /* CSC Interrupt: Card detect interrupt on */ 886 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 887 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 888 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 889 /* reset interrupt */ 890 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 891 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 892 } 893 894 895 896 897 /* 898 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 899 * struct pcmciabus_attach_args *paa) 900 * 901 * This function attaches 16-bit PCcard bus. 902 */ 903 STATIC void 904 pccbb_pcmcia_attach_setup(sc, paa) 905 struct pccbb_softc *sc; 906 struct pcmciabus_attach_args *paa; 907 { 908 struct pcic_handle *ph = &sc->sc_pcmcia_h; 909 #if rbus 910 rbus_tag_t rb; 911 #endif 912 913 /* initialize pcmcia part in pccbb_softc */ 914 ph->ph_parent = (struct device *)sc; 915 ph->sock = sc->sc_function; 916 ph->flags = 0; 917 ph->shutdown = 0; 918 ph->ih_irq = sc->sc_pa.pa_intrline; 919 ph->ph_bus_t = sc->sc_base_memt; 920 ph->ph_bus_h = sc->sc_base_memh; 921 ph->ph_read = pccbb_pcmcia_read; 922 ph->ph_write = pccbb_pcmcia_write; 923 sc->sc_pct = &pccbb_pcmcia_funcs; 924 925 /* 926 * We need to do a few things here: 927 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 928 * setting the IRQ numbers to 0. 929 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 930 * routing of CSC interrupts (e.g. card removal) to PCI while in 931 * PCMCIA mode. We just leave this set all the time. 932 * 3) Enable card insertion/removal interrupts in case the chip also 933 * needs that while in PCMCIA mode. 934 * 4) Clear any pending CSC interrupt. 935 */ 936 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 937 if (sc->sc_chipset == CB_TI113X) { 938 Pcic_write(ph, PCIC_CSC_INTR, 0); 939 } else { 940 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 941 Pcic_read(ph, PCIC_CSC); 942 } 943 944 /* initialize pcmcia bus attachment */ 945 paa->paa_busname = "pcmcia"; 946 paa->pct = sc->sc_pct; 947 paa->pch = ph; 948 paa->iobase = 0; /* I don't use them */ 949 paa->iosize = 0; 950 #if rbus 951 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 952 paa->iobase = rb->rb_start + rb->rb_offset; 953 paa->iosize = rb->rb_end - rb->rb_start; 954 #endif 955 956 return; 957 } 958 959 #if 0 960 STATIC void 961 pccbb_pcmcia_attach_card(ph) 962 struct pcic_handle *ph; 963 { 964 if (ph->flags & PCIC_FLAG_CARDP) { 965 panic("pccbb_pcmcia_attach_card: already attached"); 966 } 967 968 /* call the MI attach function */ 969 pcmcia_card_attach(ph->pcmcia); 970 971 ph->flags |= PCIC_FLAG_CARDP; 972 } 973 974 STATIC void 975 pccbb_pcmcia_detach_card(ph, flags) 976 struct pcic_handle *ph; 977 int flags; 978 { 979 if (!(ph->flags & PCIC_FLAG_CARDP)) { 980 panic("pccbb_pcmcia_detach_card: already detached"); 981 } 982 983 ph->flags &= ~PCIC_FLAG_CARDP; 984 985 /* call the MI detach function */ 986 pcmcia_card_detach(ph->pcmcia, flags); 987 } 988 #endif 989 990 /* 991 * int pccbbintr(arg) 992 * void *arg; 993 * This routine handles the interrupt from Yenta PCI-CardBus bridge 994 * itself. 995 */ 996 int 997 pccbbintr(arg) 998 void *arg; 999 { 1000 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1001 u_int32_t sockevent, sockstate; 1002 bus_space_tag_t memt = sc->sc_base_memt; 1003 bus_space_handle_t memh = sc->sc_base_memh; 1004 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1005 1006 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1007 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1008 Pcic_read(ph, PCIC_CSC); 1009 1010 if (sockevent == 0) { 1011 /* This intr is not for me: it may be for my child devices. */ 1012 if (sc->sc_pil_intr_enable) { 1013 return pccbbintr_function(sc); 1014 } else { 1015 return 0; 1016 } 1017 } 1018 1019 if (sockevent & CB_SOCKET_EVENT_CD) { 1020 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1021 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1022 /* A card should be removed. */ 1023 if (sc->sc_flags & CBB_CARDEXIST) { 1024 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1025 sockevent)); 1026 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1027 sc->sc_flags &= ~CBB_CARDEXIST; 1028 if (sc->sc_csc->sc_status & 1029 CARDSLOT_STATUS_CARD_16) { 1030 #if 0 1031 struct pcic_handle *ph = 1032 &sc->sc_pcmcia_h; 1033 1034 pcmcia_card_deactivate(ph->pcmcia); 1035 pccbb_pcmcia_socket_disable(ph); 1036 pccbb_pcmcia_detach_card(ph, 1037 DETACH_FORCE); 1038 #endif 1039 cardslot_event_throw(sc->sc_csc, 1040 CARDSLOT_EVENT_REMOVAL_16); 1041 } else if (sc->sc_csc->sc_status & 1042 CARDSLOT_STATUS_CARD_CB) { 1043 /* Cardbus intr removed */ 1044 cardslot_event_throw(sc->sc_csc, 1045 CARDSLOT_EVENT_REMOVAL_CB); 1046 } 1047 } else if (sc->sc_flags & CBB_INSERTING) { 1048 sc->sc_flags &= ~CBB_INSERTING; 1049 callout_stop(&sc->sc_insert_ch); 1050 } 1051 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1052 /* 1053 * The pccbbintr may called from powerdown hook when 1054 * the system resumed, to detect the card 1055 * insertion/removal during suspension. 1056 */ 1057 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1058 if (sc->sc_flags & CBB_INSERTING) { 1059 callout_stop(&sc->sc_insert_ch); 1060 } 1061 callout_reset(&sc->sc_insert_ch, hz / 5, 1062 pci113x_insert, sc); 1063 sc->sc_flags |= CBB_INSERTING; 1064 } 1065 } 1066 1067 return (1); 1068 } 1069 1070 /* 1071 * static int pccbbintr_function(struct pccbb_softc *sc) 1072 * 1073 * This function calls each interrupt handler registered at the 1074 * bridge. The interrupt handlers are called in registered order. 1075 */ 1076 static int 1077 pccbbintr_function(sc) 1078 struct pccbb_softc *sc; 1079 { 1080 int retval = 0, val; 1081 struct pccbb_intrhand_list *pil; 1082 int s, splchanged; 1083 1084 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1085 pil = LIST_NEXT(pil, pil_next)) { 1086 /* 1087 * XXX priority change. gross. I use if-else 1088 * sentense instead of switch-case sentense because of 1089 * avoiding duplicate case value error. More than one 1090 * IPL_XXX use same value. It depends on 1091 * implimentation. 1092 */ 1093 splchanged = 1; 1094 if (pil->pil_level == IPL_SERIAL) { 1095 s = splserial(); 1096 } else if (pil->pil_level == IPL_HIGH) { 1097 s = splhigh(); 1098 } else if (pil->pil_level == IPL_CLOCK) { 1099 s = splclock(); 1100 } else if (pil->pil_level == IPL_AUDIO) { 1101 s = splaudio(); 1102 } else if (pil->pil_level == IPL_VM) { 1103 s = splvm(); 1104 } else if (pil->pil_level == IPL_TTY) { 1105 s = spltty(); 1106 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1107 s = splsoftserial(); 1108 } else if (pil->pil_level == IPL_NET) { 1109 s = splnet(); 1110 } else { 1111 splchanged = 0; 1112 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1113 } 1114 1115 val = (*pil->pil_func)(pil->pil_arg); 1116 1117 if (splchanged != 0) { 1118 splx(s); 1119 } 1120 1121 retval = retval == 1 ? 1 : 1122 retval == 0 ? val : val != 0 ? val : retval; 1123 } 1124 1125 return retval; 1126 } 1127 1128 static void 1129 pci113x_insert(arg) 1130 void *arg; 1131 { 1132 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1133 u_int32_t sockevent, sockstate; 1134 1135 if (!(sc->sc_flags & CBB_INSERTING)) { 1136 /* We add a card only under inserting state. */ 1137 return; 1138 } 1139 sc->sc_flags &= ~CBB_INSERTING; 1140 1141 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1142 CB_SOCKET_EVENT); 1143 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1144 CB_SOCKET_STAT); 1145 1146 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1147 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1148 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1149 sc->sc_flags |= CBB_CARDEXIST; 1150 /* call pccard interrupt handler here */ 1151 if (sockstate & CB_SOCKET_STAT_16BIT) { 1152 /* 16-bit card found */ 1153 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1154 cardslot_event_throw(sc->sc_csc, 1155 CARDSLOT_EVENT_INSERTION_16); 1156 } else if (sockstate & CB_SOCKET_STAT_CB) { 1157 /* cardbus card found */ 1158 /* cardbus_attach_card(sc->sc_csc); */ 1159 cardslot_event_throw(sc->sc_csc, 1160 CARDSLOT_EVENT_INSERTION_CB); 1161 } else { 1162 /* who are you? */ 1163 } 1164 } else { 1165 callout_reset(&sc->sc_insert_ch, hz / 10, 1166 pci113x_insert, sc); 1167 } 1168 } 1169 1170 #define PCCBB_PCMCIA_OFFSET 0x800 1171 static u_int8_t 1172 pccbb_pcmcia_read(ph, reg) 1173 struct pcic_handle *ph; 1174 int reg; 1175 { 1176 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1177 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1178 1179 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1180 PCCBB_PCMCIA_OFFSET + reg); 1181 } 1182 1183 static void 1184 pccbb_pcmcia_write(ph, reg, val) 1185 struct pcic_handle *ph; 1186 int reg; 1187 u_int8_t val; 1188 { 1189 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1190 val); 1191 1192 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1193 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1194 } 1195 1196 /* 1197 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1198 */ 1199 STATIC int 1200 pccbb_ctrl(ct, command) 1201 cardbus_chipset_tag_t ct; 1202 int command; 1203 { 1204 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1205 1206 switch (command) { 1207 case CARDBUS_CD: 1208 if (2 == pccbb_detect_card(sc)) { 1209 int retval = 0; 1210 int status = cb_detect_voltage(sc); 1211 if (PCCARD_VCC_5V & status) { 1212 retval |= CARDBUS_5V_CARD; 1213 } 1214 if (PCCARD_VCC_3V & status) { 1215 retval |= CARDBUS_3V_CARD; 1216 } 1217 if (PCCARD_VCC_XV & status) { 1218 retval |= CARDBUS_XV_CARD; 1219 } 1220 if (PCCARD_VCC_YV & status) { 1221 retval |= CARDBUS_YV_CARD; 1222 } 1223 return retval; 1224 } else { 1225 return 0; 1226 } 1227 case CARDBUS_RESET: 1228 return cb_reset(sc); 1229 case CARDBUS_IO_ENABLE: /* fallthrough */ 1230 case CARDBUS_IO_DISABLE: /* fallthrough */ 1231 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1232 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1233 case CARDBUS_BM_ENABLE: /* fallthrough */ 1234 case CARDBUS_BM_DISABLE: /* fallthrough */ 1235 /* XXX: I think we don't need to call this function below. */ 1236 return pccbb_cardenable(sc, command); 1237 } 1238 1239 return 0; 1240 } 1241 1242 /* 1243 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1244 * This function returns true when it succeeds and returns false when 1245 * it fails. 1246 */ 1247 STATIC int 1248 pccbb_power(ct, command) 1249 cardbus_chipset_tag_t ct; 1250 int command; 1251 { 1252 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1253 1254 u_int32_t status, sock_ctrl, reg_ctrl; 1255 bus_space_tag_t memt = sc->sc_base_memt; 1256 bus_space_handle_t memh = sc->sc_base_memh; 1257 1258 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1259 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1260 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1261 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1262 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1263 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1264 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1265 "UNKNOWN", 1266 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1267 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1268 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1269 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1270 "UNKNOWN", command)); 1271 1272 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1273 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1274 1275 switch (command & CARDBUS_VCCMASK) { 1276 case CARDBUS_VCC_UC: 1277 break; 1278 case CARDBUS_VCC_5V: 1279 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1280 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1281 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1282 } else { 1283 printf("%s: BAD voltage request: no 5 V card\n", 1284 sc->sc_dev.dv_xname); 1285 } 1286 break; 1287 case CARDBUS_VCC_3V: 1288 if (CB_SOCKET_STAT_3VCARD & status) { 1289 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1290 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1291 } else { 1292 printf("%s: BAD voltage request: no 3.3 V card\n", 1293 sc->sc_dev.dv_xname); 1294 } 1295 break; 1296 case CARDBUS_VCC_0V: 1297 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1298 break; 1299 default: 1300 return 0; /* power NEVER changed */ 1301 } 1302 1303 switch (command & CARDBUS_VPPMASK) { 1304 case CARDBUS_VPP_UC: 1305 break; 1306 case CARDBUS_VPP_0V: 1307 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1308 break; 1309 case CARDBUS_VPP_VCC: 1310 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1311 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1312 break; 1313 case CARDBUS_VPP_12V: 1314 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1315 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1316 break; 1317 } 1318 1319 #if 0 1320 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1321 #endif 1322 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1323 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1324 1325 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1326 printf 1327 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1328 sc->sc_dev.dv_xname, sock_ctrl, status); 1329 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1330 (command & CARDBUS_VCCMASK) == 1331 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1332 CARDBUS_VCCMASK) == 1333 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1334 CARDBUS_VCCMASK) == 1335 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1336 CARDBUS_VCCMASK) == 1337 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1338 CARDBUS_VCCMASK) == 1339 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1340 CARDBUS_VCCMASK) == 1341 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1342 (command & CARDBUS_VPPMASK) == 1343 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1344 CARDBUS_VPPMASK) == 1345 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1346 CARDBUS_VPPMASK) == 1347 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1348 CARDBUS_VPPMASK) == 1349 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1350 #if 0 1351 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1352 u_int32_t force = 1353 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1354 /* Reset Bad Vcc request */ 1355 force &= ~CB_SOCKET_FORCE_BADVCC; 1356 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1357 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1358 CB_SOCKET_STAT)); 1359 return 1; 1360 } 1361 #endif 1362 return 0; 1363 } 1364 1365 if (sc->sc_chipset == CB_TOPIC97) { 1366 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1367 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1368 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1369 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1370 else 1371 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1372 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1373 } 1374 1375 /* 1376 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1377 * time is 20 ms, some PC-Card bridge requires longer duration. 1378 */ 1379 #if 0 /* XXX called on interrupt context */ 1380 DELAY_MS(300, sc); 1381 #else 1382 delay(300 * 1000); 1383 #endif 1384 1385 return 1; /* power changed correctly */ 1386 } 1387 1388 #if defined CB_PCMCIA_POLL 1389 struct cb_poll_str { 1390 void *arg; 1391 int (*func) __P((void *)); 1392 int level; 1393 pccard_chipset_tag_t ct; 1394 int count; 1395 struct callout poll_ch; 1396 }; 1397 1398 static struct cb_poll_str cb_poll[10]; 1399 static int cb_poll_n = 0; 1400 1401 static void cb_pcmcia_poll __P((void *arg)); 1402 1403 static void 1404 cb_pcmcia_poll(arg) 1405 void *arg; 1406 { 1407 struct cb_poll_str *poll = arg; 1408 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1409 struct pccbb_softc *sc = psc->cpc_parent; 1410 int s; 1411 u_int32_t spsr; /* socket present-state reg */ 1412 1413 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1414 switch (poll->level) { 1415 case IPL_NET: 1416 s = splnet(); 1417 break; 1418 case IPL_BIO: 1419 s = splbio(); 1420 break; 1421 case IPL_TTY: /* fallthrough */ 1422 default: 1423 s = spltty(); 1424 break; 1425 } 1426 1427 spsr = 1428 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1429 CB_SOCKET_STAT); 1430 1431 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1432 if (!(spsr & 0x40)) { /* CINT low */ 1433 #else 1434 if (1) { 1435 #endif 1436 if ((*poll->func) (poll->arg) == 1) { 1437 ++poll->count; 1438 printf("intr: reported from poller, 0x%x\n", spsr); 1439 #if defined LEVEL2 1440 } else { 1441 printf("intr: miss! 0x%x\n", spsr); 1442 #endif 1443 } 1444 } 1445 splx(s); 1446 } 1447 #endif /* defined CB_PCMCIA_POLL */ 1448 1449 /* 1450 * static int pccbb_detect_card(struct pccbb_softc *sc) 1451 * return value: 0 if no card exists. 1452 * 1 if 16-bit card exists. 1453 * 2 if cardbus card exists. 1454 */ 1455 static int 1456 pccbb_detect_card(sc) 1457 struct pccbb_softc *sc; 1458 { 1459 bus_space_handle_t base_memh = sc->sc_base_memh; 1460 bus_space_tag_t base_memt = sc->sc_base_memt; 1461 u_int32_t sockstat = 1462 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1463 int retval = 0; 1464 1465 /* CD1 and CD2 asserted */ 1466 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1467 /* card must be present */ 1468 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1469 /* NOTACARD DEASSERTED */ 1470 if (CB_SOCKET_STAT_CB & sockstat) { 1471 /* CardBus mode */ 1472 retval = 2; 1473 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1474 /* 16-bit mode */ 1475 retval = 1; 1476 } 1477 } 1478 } 1479 return retval; 1480 } 1481 1482 /* 1483 * STATIC int cb_reset(struct pccbb_softc *sc) 1484 * This function resets CardBus card. 1485 */ 1486 STATIC int 1487 cb_reset(sc) 1488 struct pccbb_softc *sc; 1489 { 1490 /* 1491 * Reset Assert at least 20 ms 1492 * Some machines request longer duration. 1493 */ 1494 int reset_duration = 1495 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1496 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1497 1498 /* Reset bit Assert (bit 6 at 0x3E) */ 1499 bcr |= CB_BCR_RESET_ENABLE; 1500 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1501 DELAY_MS(reset_duration, sc); 1502 1503 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1504 /* Reset bit Deassert (bit 6 at 0x3E) */ 1505 bcr &= ~CB_BCR_RESET_ENABLE; 1506 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1507 DELAY_MS(reset_duration, sc); 1508 } 1509 /* No card found on the slot. Keep Reset. */ 1510 return 1; 1511 } 1512 1513 /* 1514 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1515 * This function detect card Voltage. 1516 */ 1517 STATIC int 1518 cb_detect_voltage(sc) 1519 struct pccbb_softc *sc; 1520 { 1521 u_int32_t psr; /* socket present-state reg */ 1522 bus_space_tag_t iot = sc->sc_base_memt; 1523 bus_space_handle_t ioh = sc->sc_base_memh; 1524 int vol = PCCARD_VCC_UKN; /* set 0 */ 1525 1526 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1527 1528 if (0x400u & psr) { 1529 vol |= PCCARD_VCC_5V; 1530 } 1531 if (0x800u & psr) { 1532 vol |= PCCARD_VCC_3V; 1533 } 1534 1535 return vol; 1536 } 1537 1538 STATIC int 1539 cbbprint(aux, pcic) 1540 void *aux; 1541 const char *pcic; 1542 { 1543 /* 1544 struct cbslot_attach_args *cba = aux; 1545 1546 if (cba->cba_slot >= 0) { 1547 aprint_normal(" slot %d", cba->cba_slot); 1548 } 1549 */ 1550 return UNCONF; 1551 } 1552 1553 /* 1554 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1555 * This function enables and disables the card 1556 */ 1557 STATIC int 1558 pccbb_cardenable(sc, function) 1559 struct pccbb_softc *sc; 1560 int function; 1561 { 1562 u_int32_t command = 1563 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1564 1565 DPRINTF(("pccbb_cardenable:")); 1566 switch (function) { 1567 case CARDBUS_IO_ENABLE: 1568 command |= PCI_COMMAND_IO_ENABLE; 1569 break; 1570 case CARDBUS_IO_DISABLE: 1571 command &= ~PCI_COMMAND_IO_ENABLE; 1572 break; 1573 case CARDBUS_MEM_ENABLE: 1574 command |= PCI_COMMAND_MEM_ENABLE; 1575 break; 1576 case CARDBUS_MEM_DISABLE: 1577 command &= ~PCI_COMMAND_MEM_ENABLE; 1578 break; 1579 case CARDBUS_BM_ENABLE: 1580 command |= PCI_COMMAND_MASTER_ENABLE; 1581 break; 1582 case CARDBUS_BM_DISABLE: 1583 command &= ~PCI_COMMAND_MASTER_ENABLE; 1584 break; 1585 default: 1586 return 0; 1587 } 1588 1589 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1590 DPRINTF((" command reg 0x%x\n", command)); 1591 return 1; 1592 } 1593 1594 #if !rbus 1595 /* 1596 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1597 */ 1598 static int 1599 pccbb_io_open(ct, win, start, end) 1600 cardbus_chipset_tag_t ct; 1601 int win; 1602 u_int32_t start, end; 1603 { 1604 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1605 int basereg; 1606 int limitreg; 1607 1608 if ((win < 0) || (win > 2)) { 1609 #if defined DIAGNOSTIC 1610 printf("cardbus_io_open: window out of range %d\n", win); 1611 #endif 1612 return 0; 1613 } 1614 1615 basereg = win * 8 + 0x2c; 1616 limitreg = win * 8 + 0x30; 1617 1618 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1619 start, basereg, end, limitreg)); 1620 1621 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1622 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1623 return 1; 1624 } 1625 1626 /* 1627 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1628 */ 1629 static int 1630 pccbb_io_close(ct, win) 1631 cardbus_chipset_tag_t ct; 1632 int win; 1633 { 1634 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1635 int basereg; 1636 int limitreg; 1637 1638 if ((win < 0) || (win > 2)) { 1639 #if defined DIAGNOSTIC 1640 printf("cardbus_io_close: window out of range %d\n", win); 1641 #endif 1642 return 0; 1643 } 1644 1645 basereg = win * 8 + 0x2c; 1646 limitreg = win * 8 + 0x30; 1647 1648 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1649 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1650 return 1; 1651 } 1652 1653 /* 1654 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1655 */ 1656 static int 1657 pccbb_mem_open(ct, win, start, end) 1658 cardbus_chipset_tag_t ct; 1659 int win; 1660 u_int32_t start, end; 1661 { 1662 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1663 int basereg; 1664 int limitreg; 1665 1666 if ((win < 0) || (win > 2)) { 1667 #if defined DIAGNOSTIC 1668 printf("cardbus_mem_open: window out of range %d\n", win); 1669 #endif 1670 return 0; 1671 } 1672 1673 basereg = win * 8 + 0x1c; 1674 limitreg = win * 8 + 0x20; 1675 1676 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1677 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1678 return 1; 1679 } 1680 1681 /* 1682 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1683 */ 1684 static int 1685 pccbb_mem_close(ct, win) 1686 cardbus_chipset_tag_t ct; 1687 int win; 1688 { 1689 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1690 int basereg; 1691 int limitreg; 1692 1693 if ((win < 0) || (win > 2)) { 1694 #if defined DIAGNOSTIC 1695 printf("cardbus_mem_close: window out of range %d\n", win); 1696 #endif 1697 return 0; 1698 } 1699 1700 basereg = win * 8 + 0x1c; 1701 limitreg = win * 8 + 0x20; 1702 1703 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1704 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1705 return 1; 1706 } 1707 #endif 1708 1709 /* 1710 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1711 * int irq, 1712 * int level, 1713 * int (* func) __P((void *)), 1714 * void *arg) 1715 * 1716 * This function registers an interrupt handler at the bridge, in 1717 * order not to call the interrupt handlers of child devices when 1718 * a card-deletion interrupt occurs. 1719 * 1720 * The arguments irq and level are not used. 1721 */ 1722 static void * 1723 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1724 cardbus_chipset_tag_t ct; 1725 int irq, level; 1726 int (*func) __P((void *)); 1727 void *arg; 1728 { 1729 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1730 1731 return pccbb_intr_establish(sc, irq, level, func, arg); 1732 } 1733 1734 1735 /* 1736 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1737 * void *ih) 1738 * 1739 * This function removes an interrupt handler pointed by ih. 1740 */ 1741 static void 1742 pccbb_cb_intr_disestablish(ct, ih) 1743 cardbus_chipset_tag_t ct; 1744 void *ih; 1745 { 1746 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1747 1748 pccbb_intr_disestablish(sc, ih); 1749 } 1750 1751 1752 void 1753 pccbb_intr_route(sc) 1754 struct pccbb_softc *sc; 1755 { 1756 pcireg_t reg; 1757 1758 /* initialize bridge intr routing */ 1759 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1760 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1761 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1762 1763 switch (sc->sc_chipset) { 1764 case CB_TI113X: 1765 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1766 /* functional intr enabled */ 1767 reg |= PCI113X_CBCTRL_PCI_INTR; 1768 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1769 break; 1770 default: 1771 break; 1772 } 1773 } 1774 1775 /* 1776 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1777 * int irq, 1778 * int level, 1779 * int (* func) __P((void *)), 1780 * void *arg) 1781 * 1782 * This function registers an interrupt handler at the bridge, in 1783 * order not to call the interrupt handlers of child devices when 1784 * a card-deletion interrupt occurs. 1785 * 1786 * The arguments irq is not used because pccbb selects intr vector. 1787 */ 1788 static void * 1789 pccbb_intr_establish(sc, irq, level, func, arg) 1790 struct pccbb_softc *sc; 1791 int irq, level; 1792 int (*func) __P((void *)); 1793 void *arg; 1794 { 1795 struct pccbb_intrhand_list *pil, *newpil; 1796 1797 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1798 1799 if (LIST_EMPTY(&sc->sc_pil)) { 1800 pccbb_intr_route(sc); 1801 } 1802 1803 /* 1804 * Allocate a room for interrupt handler structure. 1805 */ 1806 if (NULL == (newpil = 1807 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1808 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1809 return NULL; 1810 } 1811 1812 newpil->pil_func = func; 1813 newpil->pil_arg = arg; 1814 newpil->pil_level = level; 1815 1816 if (LIST_EMPTY(&sc->sc_pil)) { 1817 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1818 } else { 1819 for (pil = LIST_FIRST(&sc->sc_pil); 1820 LIST_NEXT(pil, pil_next) != NULL; 1821 pil = LIST_NEXT(pil, pil_next)); 1822 LIST_INSERT_AFTER(pil, newpil, pil_next); 1823 } 1824 1825 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1826 LIST_FIRST(&sc->sc_pil))); 1827 1828 return newpil; 1829 } 1830 1831 /* 1832 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1833 * void *ih) 1834 * 1835 * This function removes an interrupt handler pointed by ih. ih 1836 * should be the value returned by cardbus_intr_establish() or 1837 * NULL. 1838 * 1839 * When ih is NULL, this function will do nothing. 1840 */ 1841 static void 1842 pccbb_intr_disestablish(sc, ih) 1843 struct pccbb_softc *sc; 1844 void *ih; 1845 { 1846 struct pccbb_intrhand_list *pil; 1847 pcireg_t reg; 1848 1849 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1850 LIST_FIRST(&sc->sc_pil))); 1851 1852 if (ih == NULL) { 1853 /* intr handler is not set */ 1854 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1855 return; 1856 } 1857 1858 #ifdef DIAGNOSTIC 1859 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1860 pil = LIST_NEXT(pil, pil_next)) { 1861 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1862 if (pil == ih) { 1863 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1864 break; 1865 } 1866 } 1867 if (pil == NULL) { 1868 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1869 sc->sc_dev.dv_xname, ih); 1870 } 1871 #endif 1872 1873 pil = (struct pccbb_intrhand_list *)ih; 1874 LIST_REMOVE(pil, pil_next); 1875 free(pil, M_DEVBUF); 1876 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1877 1878 if (LIST_EMPTY(&sc->sc_pil)) { 1879 /* No interrupt handlers */ 1880 1881 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1882 1883 /* stop routing PCI intr */ 1884 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1885 reg |= CB_BCR_INTR_IREQ_ENABLE; 1886 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1887 1888 switch (sc->sc_chipset) { 1889 case CB_TI113X: 1890 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1891 /* functional intr disabled */ 1892 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1893 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1894 break; 1895 default: 1896 break; 1897 } 1898 } 1899 } 1900 1901 #if defined SHOW_REGS 1902 static void 1903 cb_show_regs(pc, tag, memt, memh) 1904 pci_chipset_tag_t pc; 1905 pcitag_t tag; 1906 bus_space_tag_t memt; 1907 bus_space_handle_t memh; 1908 { 1909 int i; 1910 printf("PCI config regs:"); 1911 for (i = 0; i < 0x50; i += 4) { 1912 if (i % 16 == 0) { 1913 printf("\n 0x%02x:", i); 1914 } 1915 printf(" %08x", pci_conf_read(pc, tag, i)); 1916 } 1917 for (i = 0x80; i < 0xb0; i += 4) { 1918 if (i % 16 == 0) { 1919 printf("\n 0x%02x:", i); 1920 } 1921 printf(" %08x", pci_conf_read(pc, tag, i)); 1922 } 1923 1924 if (memh == 0) { 1925 printf("\n"); 1926 return; 1927 } 1928 1929 printf("\nsocket regs:"); 1930 for (i = 0; i <= 0x10; i += 0x04) { 1931 printf(" %08x", bus_space_read_4(memt, memh, i)); 1932 } 1933 printf("\nExCA regs:"); 1934 for (i = 0; i < 0x08; ++i) { 1935 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1936 } 1937 printf("\n"); 1938 return; 1939 } 1940 #endif 1941 1942 /* 1943 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1944 * int busno, int devno, int function) 1945 * This is the function to make a tag to access config space of 1946 * a CardBus Card. It works same as pci_conf_read. 1947 */ 1948 static cardbustag_t 1949 pccbb_make_tag(cc, busno, devno, function) 1950 cardbus_chipset_tag_t cc; 1951 int busno, devno, function; 1952 { 1953 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1954 1955 return pci_make_tag(sc->sc_pc, busno, devno, function); 1956 } 1957 1958 static void 1959 pccbb_free_tag(cc, tag) 1960 cardbus_chipset_tag_t cc; 1961 cardbustag_t tag; 1962 { 1963 } 1964 1965 /* 1966 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1967 * cardbustag_t tag, int offset) 1968 * This is the function to read the config space of a CardBus Card. 1969 * It works same as pci_conf_read. 1970 */ 1971 static cardbusreg_t 1972 pccbb_conf_read(cc, tag, offset) 1973 cardbus_chipset_tag_t cc; 1974 cardbustag_t tag; 1975 int offset; /* register offset */ 1976 { 1977 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1978 1979 return pci_conf_read(sc->sc_pc, tag, offset); 1980 } 1981 1982 /* 1983 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1984 * int offs, cardbusreg_t val) 1985 * This is the function to write the config space of a CardBus Card. 1986 * It works same as pci_conf_write. 1987 */ 1988 static void 1989 pccbb_conf_write(cc, tag, reg, val) 1990 cardbus_chipset_tag_t cc; 1991 cardbustag_t tag; 1992 int reg; /* register offset */ 1993 cardbusreg_t val; 1994 { 1995 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1996 1997 pci_conf_write(sc->sc_pc, tag, reg, val); 1998 } 1999 2000 #if 0 2001 STATIC int 2002 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2003 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2004 int speed, int flags, 2005 bus_space_handle_t * iohp) 2006 #endif 2007 /* 2008 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2009 * bus_addr_t start, bus_size_t size, 2010 * bus_size_t align, 2011 * struct pcmcia_io_handle *pcihp 2012 * 2013 * This function only allocates I/O region for pccard. This function 2014 * never maps the allocated region to pccard I/O area. 2015 * 2016 * XXX: The interface of this function is not very good, I believe. 2017 */ 2018 STATIC int 2019 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2020 pcmcia_chipset_handle_t pch; 2021 bus_addr_t start; /* start address */ 2022 bus_size_t size; 2023 bus_size_t align; 2024 struct pcmcia_io_handle *pcihp; 2025 { 2026 struct pcic_handle *ph = (struct pcic_handle *)pch; 2027 bus_addr_t ioaddr; 2028 int flags = 0; 2029 bus_space_tag_t iot; 2030 bus_space_handle_t ioh; 2031 bus_addr_t mask; 2032 #if rbus 2033 rbus_tag_t rb; 2034 #endif 2035 if (align == 0) { 2036 align = size; /* XXX: funny??? */ 2037 } 2038 2039 if (start != 0) { 2040 /* XXX: assume all card decode lower 10 bits by its hardware */ 2041 mask = 0x3ff; 2042 /* enforce to use only masked address */ 2043 start &= mask; 2044 } else { 2045 /* 2046 * calculate mask: 2047 * 1. get the most significant bit of size (call it msb). 2048 * 2. compare msb with the value of size. 2049 * 3. if size is larger, shift msb left once. 2050 * 4. obtain mask value to decrement msb. 2051 */ 2052 bus_size_t size_tmp = size; 2053 int shifts = 0; 2054 2055 mask = 1; 2056 while (size_tmp) { 2057 ++shifts; 2058 size_tmp >>= 1; 2059 } 2060 mask = (1 << shifts); 2061 if (mask < size) { 2062 mask <<= 1; 2063 } 2064 --mask; 2065 } 2066 2067 /* 2068 * Allocate some arbitrary I/O space. 2069 */ 2070 2071 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2072 2073 #if rbus 2074 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2075 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2076 return 1; 2077 } 2078 DPRINTF(("pccbb_pcmcia_io_alloc alloc port %lx+%lx\n", 2079 (u_long) ioaddr, (u_long) size)); 2080 #else 2081 if (start) { 2082 ioaddr = start; 2083 if (bus_space_map(iot, start, size, 0, &ioh)) { 2084 return 1; 2085 } 2086 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2087 (u_long) ioaddr, (u_long) size)); 2088 } else { 2089 flags |= PCMCIA_IO_ALLOCATED; 2090 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2091 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2092 size, align, 0, 0, &ioaddr, &ioh)) { 2093 /* No room be able to be get. */ 2094 return 1; 2095 } 2096 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2097 (u_long) ioaddr, (u_long) size)); 2098 } 2099 #endif 2100 2101 pcihp->iot = iot; 2102 pcihp->ioh = ioh; 2103 pcihp->addr = ioaddr; 2104 pcihp->size = size; 2105 pcihp->flags = flags; 2106 2107 return 0; 2108 } 2109 2110 /* 2111 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2112 * struct pcmcia_io_handle *pcihp) 2113 * 2114 * This function only frees I/O region for pccard. 2115 * 2116 * XXX: The interface of this function is not very good, I believe. 2117 */ 2118 void 2119 pccbb_pcmcia_io_free(pch, pcihp) 2120 pcmcia_chipset_handle_t pch; 2121 struct pcmcia_io_handle *pcihp; 2122 { 2123 #if !rbus 2124 bus_space_tag_t iot = pcihp->iot; 2125 #endif 2126 bus_space_handle_t ioh = pcihp->ioh; 2127 bus_size_t size = pcihp->size; 2128 2129 #if rbus 2130 struct pccbb_softc *sc = 2131 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2132 rbus_tag_t rb = sc->sc_rbus_iot; 2133 2134 rbus_space_free(rb, ioh, size, NULL); 2135 #else 2136 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2137 bus_space_free(iot, ioh, size); 2138 else 2139 bus_space_unmap(iot, ioh, size); 2140 #endif 2141 } 2142 2143 /* 2144 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2145 * bus_addr_t offset, bus_size_t size, 2146 * struct pcmcia_io_handle *pcihp, 2147 * int *windowp) 2148 * 2149 * This function maps the allocated I/O region to pccard. This function 2150 * never allocates any I/O region for pccard I/O area. I don't 2151 * understand why the original authors of pcmciabus separated alloc and 2152 * map. I believe the two must be unite. 2153 * 2154 * XXX: no wait timing control? 2155 */ 2156 int 2157 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2158 pcmcia_chipset_handle_t pch; 2159 int width; 2160 bus_addr_t offset; 2161 bus_size_t size; 2162 struct pcmcia_io_handle *pcihp; 2163 int *windowp; 2164 { 2165 struct pcic_handle *ph = (struct pcic_handle *)pch; 2166 bus_addr_t ioaddr = pcihp->addr + offset; 2167 int i, win; 2168 #if defined CBB_DEBUG 2169 static char *width_names[] = { "dynamic", "io8", "io16" }; 2170 #endif 2171 2172 /* Sanity check I/O handle. */ 2173 2174 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2175 panic("pccbb_pcmcia_io_map iot is bogus"); 2176 } 2177 2178 /* XXX Sanity check offset/size. */ 2179 2180 win = -1; 2181 for (i = 0; i < PCIC_IO_WINS; i++) { 2182 if ((ph->ioalloc & (1 << i)) == 0) { 2183 win = i; 2184 ph->ioalloc |= (1 << i); 2185 break; 2186 } 2187 } 2188 2189 if (win == -1) { 2190 return 1; 2191 } 2192 2193 *windowp = win; 2194 2195 /* XXX this is pretty gross */ 2196 2197 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2198 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2199 2200 /* XXX wtf is this doing here? */ 2201 2202 #if 0 2203 printf(" port 0x%lx", (u_long) ioaddr); 2204 if (size > 1) { 2205 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2206 } 2207 #endif 2208 2209 ph->io[win].addr = ioaddr; 2210 ph->io[win].size = size; 2211 ph->io[win].width = width; 2212 2213 /* actual dirty register-value changing in the function below. */ 2214 pccbb_pcmcia_do_io_map(ph, win); 2215 2216 return 0; 2217 } 2218 2219 /* 2220 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2221 * 2222 * This function changes register-value to map I/O region for pccard. 2223 */ 2224 static void 2225 pccbb_pcmcia_do_io_map(ph, win) 2226 struct pcic_handle *ph; 2227 int win; 2228 { 2229 static u_int8_t pcic_iowidth[3] = { 2230 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2231 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2232 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2233 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2234 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2235 }; 2236 2237 #define PCIC_SIA_START_LOW 0 2238 #define PCIC_SIA_START_HIGH 1 2239 #define PCIC_SIA_STOP_LOW 2 2240 #define PCIC_SIA_STOP_HIGH 3 2241 2242 int regbase_win = 0x8 + win * 0x04; 2243 u_int8_t ioctl, enable; 2244 2245 DPRINTF( 2246 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2247 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2248 ph->io[win].width * 8)); 2249 2250 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2251 ph->io[win].addr & 0xff); 2252 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2253 (ph->io[win].addr >> 8) & 0xff); 2254 2255 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2256 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2257 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2258 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2259 2260 ioctl = Pcic_read(ph, PCIC_IOCTL); 2261 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2262 switch (win) { 2263 case 0: 2264 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2265 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2266 PCIC_IOCTL_IO0_DATASIZE_MASK); 2267 ioctl |= pcic_iowidth[ph->io[win].width]; 2268 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2269 break; 2270 case 1: 2271 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2272 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2273 PCIC_IOCTL_IO1_DATASIZE_MASK); 2274 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2275 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2276 break; 2277 } 2278 Pcic_write(ph, PCIC_IOCTL, ioctl); 2279 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2280 #if defined CBB_DEBUG 2281 { 2282 u_int8_t start_low = 2283 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2284 u_int8_t start_high = 2285 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2286 u_int8_t stop_low = 2287 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2288 u_int8_t stop_high = 2289 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2290 printf 2291 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2292 start_low, start_high, stop_low, stop_high, ioctl, enable); 2293 } 2294 #endif 2295 } 2296 2297 /* 2298 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2299 * 2300 * This function unmaps I/O region. No return value. 2301 */ 2302 STATIC void 2303 pccbb_pcmcia_io_unmap(pch, win) 2304 pcmcia_chipset_handle_t pch; 2305 int win; 2306 { 2307 struct pcic_handle *ph = (struct pcic_handle *)pch; 2308 int reg; 2309 2310 if (win >= PCIC_IO_WINS || win < 0) { 2311 panic("pccbb_pcmcia_io_unmap: window out of range"); 2312 } 2313 2314 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2315 switch (win) { 2316 case 0: 2317 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2318 break; 2319 case 1: 2320 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2321 break; 2322 } 2323 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2324 2325 ph->ioalloc &= ~(1 << win); 2326 } 2327 2328 /* 2329 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2330 * 2331 * This function enables the card. All information is stored in 2332 * the first argument, pcmcia_chipset_handle_t. 2333 */ 2334 static void 2335 pccbb_pcmcia_wait_ready(ph) 2336 struct pcic_handle *ph; 2337 { 2338 int i; 2339 2340 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2341 Pcic_read(ph, PCIC_IF_STATUS))); 2342 2343 for (i = 0; i < 2000; i++) { 2344 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2345 return; 2346 } 2347 DELAY_MS(2, ph->ph_parent); 2348 #ifdef CBB_DEBUG 2349 if ((i > 1000) && (i % 25 == 24)) 2350 printf("."); 2351 #endif 2352 } 2353 2354 #ifdef DIAGNOSTIC 2355 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2356 Pcic_read(ph, PCIC_IF_STATUS)); 2357 #endif 2358 } 2359 2360 /* 2361 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2362 * 2363 * This function enables the card. All information is stored in 2364 * the first argument, pcmcia_chipset_handle_t. 2365 */ 2366 STATIC void 2367 pccbb_pcmcia_socket_enable(pch) 2368 pcmcia_chipset_handle_t pch; 2369 { 2370 struct pcic_handle *ph = (struct pcic_handle *)pch; 2371 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2372 int cardtype, win; 2373 u_int8_t power, intr; 2374 pcireg_t spsr; 2375 int voltage; 2376 2377 /* this bit is mostly stolen from pcic_attach_card */ 2378 2379 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2380 2381 /* get card Vcc info */ 2382 2383 spsr = 2384 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2385 CB_SOCKET_STAT); 2386 if (spsr & CB_SOCKET_STAT_5VCARD) { 2387 DPRINTF(("5V card\n")); 2388 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2389 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2390 DPRINTF(("3V card\n")); 2391 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2392 } else { 2393 printf("?V card, 0x%x\n", spsr); /* XXX */ 2394 return; 2395 } 2396 2397 /* disable socket: negate output enable bit and power off */ 2398 2399 power = 0; 2400 Pcic_write(ph, PCIC_PWRCTL, power); 2401 2402 /* power down the socket to reset it, clear the card reset pin */ 2403 2404 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2405 2406 /* 2407 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2408 * we are changing Vcc (Toff). 2409 */ 2410 /* delay(300*1000); too much */ 2411 2412 /* assert reset bit */ 2413 intr = Pcic_read(ph, PCIC_INTR); 2414 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2415 Pcic_write(ph, PCIC_INTR, intr); 2416 2417 /* power up the socket and output enable */ 2418 power = Pcic_read(ph, PCIC_PWRCTL); 2419 power |= PCIC_PWRCTL_OE; 2420 Pcic_write(ph, PCIC_PWRCTL, power); 2421 pccbb_power(sc, voltage); 2422 2423 /* 2424 * hold RESET at least 20 ms: the spec says only 10 us is 2425 * enough, but TI1130 requires at least 20 ms. 2426 */ 2427 #if 0 /* XXX called on interrupt context */ 2428 DELAY_MS(20, sc); 2429 #else 2430 delay(20 * 1000); 2431 #endif 2432 2433 /* clear the reset flag */ 2434 2435 intr |= PCIC_INTR_RESET; 2436 Pcic_write(ph, PCIC_INTR, intr); 2437 2438 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2439 2440 #if 0 /* XXX called on interrupt context */ 2441 DELAY_MS(20, sc); 2442 #else 2443 delay(20 * 1000); 2444 #endif 2445 2446 /* wait for the chip to finish initializing */ 2447 2448 pccbb_pcmcia_wait_ready(ph); 2449 2450 /* zero out the address windows */ 2451 2452 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2453 2454 /* set the card type */ 2455 2456 cardtype = pcmcia_card_gettype(ph->pcmcia); 2457 2458 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2459 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2460 Pcic_write(ph, PCIC_INTR, intr); 2461 2462 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2463 ph->ph_parent->dv_xname, ph->sock, 2464 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2465 2466 /* reinstall all the memory and io mappings */ 2467 2468 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2469 if (ph->memalloc & (1 << win)) { 2470 pccbb_pcmcia_do_mem_map(ph, win); 2471 } 2472 } 2473 2474 for (win = 0; win < PCIC_IO_WINS; ++win) { 2475 if (ph->ioalloc & (1 << win)) { 2476 pccbb_pcmcia_do_io_map(ph, win); 2477 } 2478 } 2479 } 2480 2481 /* 2482 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2483 * 2484 * This function disables the card. All information is stored in 2485 * the first argument, pcmcia_chipset_handle_t. 2486 */ 2487 STATIC void 2488 pccbb_pcmcia_socket_disable(pch) 2489 pcmcia_chipset_handle_t pch; 2490 { 2491 struct pcic_handle *ph = (struct pcic_handle *)pch; 2492 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2493 u_int8_t power, intr; 2494 2495 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2496 2497 /* reset signal asserting... */ 2498 2499 intr = Pcic_read(ph, PCIC_INTR); 2500 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2501 Pcic_write(ph, PCIC_INTR, intr); 2502 delay(2 * 1000); 2503 2504 /* power down the socket */ 2505 power = Pcic_read(ph, PCIC_PWRCTL); 2506 power &= ~PCIC_PWRCTL_OE; 2507 Pcic_write(ph, PCIC_PWRCTL, power); 2508 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2509 /* 2510 * wait 300ms until power fails (Tpf). 2511 */ 2512 #if 0 /* XXX called on interrupt context */ 2513 DELAY_MS(300, sc); 2514 #else 2515 delay(300 * 1000); 2516 #endif 2517 } 2518 2519 /* 2520 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2521 * 2522 * This function detects whether a card is in the slot or not. 2523 * If a card is inserted, return 1. Otherwise, return 0. 2524 */ 2525 STATIC int 2526 pccbb_pcmcia_card_detect(pch) 2527 pcmcia_chipset_handle_t pch; 2528 { 2529 struct pcic_handle *ph = (struct pcic_handle *)pch; 2530 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2531 2532 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2533 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2534 } 2535 2536 #if 0 2537 STATIC int 2538 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2539 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2540 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2541 #endif 2542 /* 2543 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2544 * bus_size_t size, 2545 * struct pcmcia_mem_handle *pcmhp) 2546 * 2547 * This function only allocates memory region for pccard. This 2548 * function never maps the allocated region to pccard memory area. 2549 * 2550 * XXX: Why the argument of start address is not in? 2551 */ 2552 STATIC int 2553 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2554 pcmcia_chipset_handle_t pch; 2555 bus_size_t size; 2556 struct pcmcia_mem_handle *pcmhp; 2557 { 2558 struct pcic_handle *ph = (struct pcic_handle *)pch; 2559 bus_space_handle_t memh; 2560 bus_addr_t addr; 2561 bus_size_t sizepg; 2562 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2563 #if rbus 2564 rbus_tag_t rb; 2565 #endif 2566 2567 /* out of sc->memh, allocate as many pages as necessary */ 2568 2569 /* convert size to PCIC pages */ 2570 /* 2571 * This is not enough; when the requested region is on the page 2572 * boundaries, this may calculate wrong result. 2573 */ 2574 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2575 #if 0 2576 if (sizepg > PCIC_MAX_MEM_PAGES) { 2577 return 1; 2578 } 2579 #endif 2580 2581 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2582 return 1; 2583 } 2584 2585 addr = 0; /* XXX gcc -Wuninitialized */ 2586 2587 #if rbus 2588 rb = sc->sc_rbus_memt; 2589 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2590 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2591 &addr, &memh)) { 2592 return 1; 2593 } 2594 #else 2595 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2596 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2597 0, /* boundary */ 2598 0, /* flags */ 2599 &addr, &memh)) { 2600 return 1; 2601 } 2602 #endif 2603 2604 DPRINTF( 2605 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2606 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2607 2608 pcmhp->memt = sc->sc_memt; 2609 pcmhp->memh = memh; 2610 pcmhp->addr = addr; 2611 pcmhp->size = size; 2612 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2613 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2614 pcmhp->mhandle = 0; 2615 /* No offset??? Funny. */ 2616 2617 return 0; 2618 } 2619 2620 /* 2621 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2622 * struct pcmcia_mem_handle *pcmhp) 2623 * 2624 * This function release the memory space allocated by the function 2625 * pccbb_pcmcia_mem_alloc(). 2626 */ 2627 STATIC void 2628 pccbb_pcmcia_mem_free(pch, pcmhp) 2629 pcmcia_chipset_handle_t pch; 2630 struct pcmcia_mem_handle *pcmhp; 2631 { 2632 #if rbus 2633 struct pcic_handle *ph = (struct pcic_handle *)pch; 2634 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2635 2636 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2637 #else 2638 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2639 #endif 2640 } 2641 2642 /* 2643 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2644 * 2645 * This function release the memory space allocated by the function 2646 * pccbb_pcmcia_mem_alloc(). 2647 */ 2648 STATIC void 2649 pccbb_pcmcia_do_mem_map(ph, win) 2650 struct pcic_handle *ph; 2651 int win; 2652 { 2653 int regbase_win; 2654 bus_addr_t phys_addr; 2655 bus_addr_t phys_end; 2656 2657 #define PCIC_SMM_START_LOW 0 2658 #define PCIC_SMM_START_HIGH 1 2659 #define PCIC_SMM_STOP_LOW 2 2660 #define PCIC_SMM_STOP_HIGH 3 2661 #define PCIC_CMA_LOW 4 2662 #define PCIC_CMA_HIGH 5 2663 2664 u_int8_t start_low, start_high = 0; 2665 u_int8_t stop_low, stop_high; 2666 u_int8_t off_low, off_high; 2667 u_int8_t mem_window; 2668 int reg; 2669 2670 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2671 int mem8 = 2672 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2673 || (kind == PCMCIA_MEM_ATTR); 2674 2675 regbase_win = 0x10 + win * 0x08; 2676 2677 phys_addr = ph->mem[win].addr; 2678 phys_end = phys_addr + ph->mem[win].size; 2679 2680 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2681 phys_addr, phys_end, ph->mem[win].offset)); 2682 2683 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2684 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2685 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2686 2687 /* bit 19:12 */ 2688 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2689 /* bit 23:20 and bit 7 on */ 2690 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2691 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2692 /* bit 31:24, for 32-bit address */ 2693 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2694 2695 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2696 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2697 2698 if (((struct pccbb_softc *)ph-> 2699 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2700 Pcic_write(ph, 0x40 + win, mem_window); 2701 } 2702 2703 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2704 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2705 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2706 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2707 2708 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2709 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2710 2711 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2712 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2713 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2714 | ((kind == PCMCIA_MEM_ATTR) ? 2715 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2716 2717 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2718 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2719 2720 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2721 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2722 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2723 2724 #if defined CBB_DEBUG 2725 { 2726 int r1, r2, r3, r4, r5, r6, r7 = 0; 2727 2728 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2729 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2730 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2731 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2732 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2733 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2734 if (((struct pccbb_softc *)(ph-> 2735 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2736 r7 = Pcic_read(ph, 0x40 + win); 2737 } 2738 2739 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2740 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2741 if (((struct pccbb_softc *)(ph-> 2742 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2743 DPRINTF((" %02x", r7)); 2744 } 2745 DPRINTF(("\n")); 2746 } 2747 #endif 2748 } 2749 2750 /* 2751 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2752 * bus_addr_t card_addr, bus_size_t size, 2753 * struct pcmcia_mem_handle *pcmhp, 2754 * bus_addr_t *offsetp, int *windowp) 2755 * 2756 * This function maps memory space allocated by the function 2757 * pccbb_pcmcia_mem_alloc(). 2758 */ 2759 STATIC int 2760 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2761 pcmcia_chipset_handle_t pch; 2762 int kind; 2763 bus_addr_t card_addr; 2764 bus_size_t size; 2765 struct pcmcia_mem_handle *pcmhp; 2766 bus_addr_t *offsetp; 2767 int *windowp; 2768 { 2769 struct pcic_handle *ph = (struct pcic_handle *)pch; 2770 bus_addr_t busaddr; 2771 long card_offset; 2772 int win; 2773 2774 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2775 if ((ph->memalloc & (1 << win)) == 0) { 2776 ph->memalloc |= (1 << win); 2777 break; 2778 } 2779 } 2780 2781 if (win == PCIC_MEM_WINS) { 2782 return 1; 2783 } 2784 2785 *windowp = win; 2786 2787 /* XXX this is pretty gross */ 2788 2789 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2790 panic("pccbb_pcmcia_mem_map memt is bogus"); 2791 } 2792 2793 busaddr = pcmhp->addr; 2794 2795 /* 2796 * compute the address offset to the pcmcia address space for the 2797 * pcic. this is intentionally signed. The masks and shifts below 2798 * will cause TRT to happen in the pcic registers. Deal with making 2799 * sure the address is aligned, and return the alignment offset. 2800 */ 2801 2802 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2803 card_addr -= *offsetp; 2804 2805 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2806 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2807 (u_long) card_addr)); 2808 2809 /* 2810 * include the offset in the size, and decrement size by one, since 2811 * the hw wants start/stop 2812 */ 2813 size += *offsetp - 1; 2814 2815 card_offset = (((long)card_addr) - ((long)busaddr)); 2816 2817 ph->mem[win].addr = busaddr; 2818 ph->mem[win].size = size; 2819 ph->mem[win].offset = card_offset; 2820 ph->mem[win].kind = kind; 2821 2822 pccbb_pcmcia_do_mem_map(ph, win); 2823 2824 return 0; 2825 } 2826 2827 /* 2828 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2829 * int window) 2830 * 2831 * This function unmaps memory space which mapped by the function 2832 * pccbb_pcmcia_mem_map(). 2833 */ 2834 STATIC void 2835 pccbb_pcmcia_mem_unmap(pch, window) 2836 pcmcia_chipset_handle_t pch; 2837 int window; 2838 { 2839 struct pcic_handle *ph = (struct pcic_handle *)pch; 2840 int reg; 2841 2842 if (window >= PCIC_MEM_WINS) { 2843 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2844 } 2845 2846 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2847 reg &= ~(1 << window); 2848 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2849 2850 ph->memalloc &= ~(1 << window); 2851 } 2852 2853 #if defined PCCBB_PCMCIA_POLL 2854 struct pccbb_poll_str { 2855 void *arg; 2856 int (*func) __P((void *)); 2857 int level; 2858 struct pcic_handle *ph; 2859 int count; 2860 int num; 2861 struct callout poll_ch; 2862 }; 2863 2864 static struct pccbb_poll_str pccbb_poll[10]; 2865 static int pccbb_poll_n = 0; 2866 2867 static void pccbb_pcmcia_poll __P((void *arg)); 2868 2869 static void 2870 pccbb_pcmcia_poll(arg) 2871 void *arg; 2872 { 2873 struct pccbb_poll_str *poll = arg; 2874 struct pcic_handle *ph = poll->ph; 2875 struct pccbb_softc *sc = ph->sc; 2876 int s; 2877 u_int32_t spsr; /* socket present-state reg */ 2878 2879 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2880 switch (poll->level) { 2881 case IPL_NET: 2882 s = splnet(); 2883 break; 2884 case IPL_BIO: 2885 s = splbio(); 2886 break; 2887 case IPL_TTY: /* fallthrough */ 2888 default: 2889 s = spltty(); 2890 break; 2891 } 2892 2893 spsr = 2894 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2895 CB_SOCKET_STAT); 2896 2897 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2898 if (!(spsr & 0x40)) /* CINT low */ 2899 #else 2900 if (1) 2901 #endif 2902 { 2903 if ((*poll->func) (poll->arg) > 0) { 2904 ++poll->count; 2905 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2906 #if defined LEVEL2 2907 } else { 2908 printf("intr: miss! 0x%x\n", spsr); 2909 #endif 2910 } 2911 } 2912 splx(s); 2913 } 2914 #endif /* defined CB_PCMCIA_POLL */ 2915 2916 /* 2917 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2918 * struct pcmcia_function *pf, 2919 * int ipl, 2920 * int (*func)(void *), 2921 * void *arg); 2922 * 2923 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2924 */ 2925 STATIC void * 2926 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2927 pcmcia_chipset_handle_t pch; 2928 struct pcmcia_function *pf; 2929 int ipl; 2930 int (*func) __P((void *)); 2931 void *arg; 2932 { 2933 struct pcic_handle *ph = (struct pcic_handle *)pch; 2934 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2935 2936 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2937 /* what should I do? */ 2938 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2939 DPRINTF( 2940 ("%s does not provide edge nor pulse interrupt\n", 2941 sc->sc_dev.dv_xname)); 2942 return NULL; 2943 } 2944 /* 2945 * XXX Noooooo! The interrupt flag must set properly!! 2946 * dumb pcmcia driver!! 2947 */ 2948 } 2949 2950 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2951 } 2952 2953 /* 2954 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2955 * void *ih) 2956 * 2957 * This function disables PC-Card interrupt. 2958 */ 2959 STATIC void 2960 pccbb_pcmcia_intr_disestablish(pch, ih) 2961 pcmcia_chipset_handle_t pch; 2962 void *ih; 2963 { 2964 struct pcic_handle *ph = (struct pcic_handle *)pch; 2965 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2966 2967 pccbb_intr_disestablish(sc, ih); 2968 } 2969 2970 #if rbus 2971 /* 2972 * static int 2973 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2974 * bus_addr_t addr, bus_size_t size, 2975 * bus_addr_t mask, bus_size_t align, 2976 * int flags, bus_addr_t *addrp; 2977 * bus_space_handle_t *bshp) 2978 * 2979 * This function allocates a portion of memory or io space for 2980 * clients. This function is called from CardBus card drivers. 2981 */ 2982 static int 2983 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2984 cardbus_chipset_tag_t ct; 2985 rbus_tag_t rb; 2986 bus_addr_t addr; 2987 bus_size_t size; 2988 bus_addr_t mask; 2989 bus_size_t align; 2990 int flags; 2991 bus_addr_t *addrp; 2992 bus_space_handle_t *bshp; 2993 { 2994 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2995 2996 DPRINTF( 2997 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2998 addr, size, mask, align)); 2999 3000 if (align == 0) { 3001 align = size; 3002 } 3003 3004 if (rb->rb_bt == sc->sc_memt) { 3005 if (align < 16) { 3006 return 1; 3007 } 3008 /* 3009 * XXX: align more than 0x1000 to avoid overwrapping 3010 * memory windows for two or more devices. 0x1000 3011 * means memory window's granularity. 3012 * 3013 * Two or more devices should be able to share same 3014 * memory window region. However, overrapping memory 3015 * window is not good because some devices, such as 3016 * 3Com 3C575[BC], have a broken address decoder and 3017 * intrude other's memory region. 3018 */ 3019 if (align < 0x1000) { 3020 align = 0x1000; 3021 } 3022 } else if (rb->rb_bt == sc->sc_iot) { 3023 if (align < 4) { 3024 return 1; 3025 } 3026 /* XXX: hack for avoiding ISA image */ 3027 if (mask < 0x0100) { 3028 mask = 0x3ff; 3029 addr = 0x300; 3030 } 3031 3032 } else { 3033 DPRINTF( 3034 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 3035 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 3036 return 1; 3037 /* XXX: panic here? */ 3038 } 3039 3040 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3041 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3042 return 1; 3043 } 3044 3045 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3046 3047 return 0; 3048 } 3049 3050 /* 3051 * static int 3052 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3053 * bus_space_handle_t *bshp, bus_size_t size); 3054 * 3055 * This function is called from CardBus card drivers. 3056 */ 3057 static int 3058 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3059 cardbus_chipset_tag_t ct; 3060 rbus_tag_t rb; 3061 bus_space_handle_t bsh; 3062 bus_size_t size; 3063 { 3064 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3065 bus_space_tag_t bt = rb->rb_bt; 3066 3067 pccbb_close_win(sc, bt, bsh, size); 3068 3069 if (bt == sc->sc_memt) { 3070 } else if (bt == sc->sc_iot) { 3071 } else { 3072 return 1; 3073 /* XXX: panic here? */ 3074 } 3075 3076 return rbus_space_free(rb, bsh, size, NULL); 3077 } 3078 #endif /* rbus */ 3079 3080 #if rbus 3081 3082 static int 3083 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3084 struct pccbb_softc *sc; 3085 bus_space_tag_t bst; 3086 bus_addr_t addr; 3087 bus_size_t size; 3088 bus_space_handle_t bsh; 3089 int flags; 3090 { 3091 struct pccbb_win_chain_head *head; 3092 bus_addr_t align; 3093 3094 head = &sc->sc_iowindow; 3095 align = 0x04; 3096 if (sc->sc_memt == bst) { 3097 head = &sc->sc_memwindow; 3098 align = 0x1000; 3099 DPRINTF(("using memory window, %x %x %x\n\n", 3100 sc->sc_iot, sc->sc_memt, bst)); 3101 } 3102 3103 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3104 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3105 sc->sc_dev.dv_xname, 3106 (head == &sc->sc_memwindow) ? "mem" : "io"); 3107 } 3108 pccbb_winset(align, sc, bst); 3109 3110 return 0; 3111 } 3112 3113 static int 3114 pccbb_close_win(sc, bst, bsh, size) 3115 struct pccbb_softc *sc; 3116 bus_space_tag_t bst; 3117 bus_space_handle_t bsh; 3118 bus_size_t size; 3119 { 3120 struct pccbb_win_chain_head *head; 3121 bus_addr_t align; 3122 3123 head = &sc->sc_iowindow; 3124 align = 0x04; 3125 if (sc->sc_memt == bst) { 3126 head = &sc->sc_memwindow; 3127 align = 0x1000; 3128 } 3129 3130 if (pccbb_winlist_delete(head, bsh, size)) { 3131 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3132 sc->sc_dev.dv_xname, 3133 (head == &sc->sc_memwindow) ? "mem" : "io"); 3134 } 3135 pccbb_winset(align, sc, bst); 3136 3137 return 0; 3138 } 3139 3140 static int 3141 pccbb_winlist_insert(head, start, size, bsh, flags) 3142 struct pccbb_win_chain_head *head; 3143 bus_addr_t start; 3144 bus_size_t size; 3145 bus_space_handle_t bsh; 3146 int flags; 3147 { 3148 struct pccbb_win_chain *chainp, *elem; 3149 3150 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3151 M_NOWAIT)) == NULL) 3152 return (1); /* fail */ 3153 3154 elem->wc_start = start; 3155 elem->wc_end = start + (size - 1); 3156 elem->wc_handle = bsh; 3157 elem->wc_flags = flags; 3158 3159 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3160 chainp = TAILQ_NEXT(chainp, wc_list)) { 3161 if (chainp->wc_end < start) 3162 continue; 3163 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3164 return (0); 3165 } 3166 3167 TAILQ_INSERT_TAIL(head, elem, wc_list); 3168 return (0); 3169 } 3170 3171 static int 3172 pccbb_winlist_delete(head, bsh, size) 3173 struct pccbb_win_chain_head *head; 3174 bus_space_handle_t bsh; 3175 bus_size_t size; 3176 { 3177 struct pccbb_win_chain *chainp; 3178 3179 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3180 chainp = TAILQ_NEXT(chainp, wc_list)) { 3181 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3182 continue; 3183 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3184 printf("pccbb_winlist_delete: window 0x%lx size " 3185 "inconsistent: 0x%lx, 0x%lx\n", 3186 (unsigned long)chainp->wc_start, 3187 (unsigned long)(chainp->wc_end - chainp->wc_start), 3188 (unsigned long)(size - 1)); 3189 return 1; 3190 } 3191 3192 TAILQ_REMOVE(head, chainp, wc_list); 3193 free(chainp, M_DEVBUF); 3194 3195 return 0; 3196 } 3197 3198 return 1; /* fail: no candidate to remove */ 3199 } 3200 3201 static void 3202 pccbb_winset(align, sc, bst) 3203 bus_addr_t align; 3204 struct pccbb_softc *sc; 3205 bus_space_tag_t bst; 3206 { 3207 pci_chipset_tag_t pc; 3208 pcitag_t tag; 3209 bus_addr_t mask = ~(align - 1); 3210 struct { 3211 cardbusreg_t win_start; 3212 cardbusreg_t win_limit; 3213 int win_flags; 3214 } win[2]; 3215 struct pccbb_win_chain *chainp; 3216 int offs; 3217 3218 win[0].win_start = win[1].win_start = 0xffffffff; 3219 win[0].win_limit = win[1].win_limit = 0; 3220 win[0].win_flags = win[1].win_flags = 0; 3221 3222 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3223 offs = 0x2c; 3224 if (sc->sc_memt == bst) { 3225 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3226 offs = 0x1c; 3227 } 3228 3229 if (chainp != NULL) { 3230 win[0].win_start = chainp->wc_start & mask; 3231 win[0].win_limit = chainp->wc_end & mask; 3232 win[0].win_flags = chainp->wc_flags; 3233 chainp = TAILQ_NEXT(chainp, wc_list); 3234 } 3235 3236 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3237 if (win[1].win_start == 0xffffffff) { 3238 /* window 1 is not used */ 3239 if ((win[0].win_flags == chainp->wc_flags) && 3240 (win[0].win_limit + align >= 3241 (chainp->wc_start & mask))) { 3242 /* concatenate */ 3243 win[0].win_limit = chainp->wc_end & mask; 3244 } else { 3245 /* make new window */ 3246 win[1].win_start = chainp->wc_start & mask; 3247 win[1].win_limit = chainp->wc_end & mask; 3248 win[1].win_flags = chainp->wc_flags; 3249 } 3250 continue; 3251 } 3252 3253 /* Both windows are engaged. */ 3254 if (win[0].win_flags == win[1].win_flags) { 3255 /* same flags */ 3256 if (win[0].win_flags == chainp->wc_flags) { 3257 if (win[1].win_start - (win[0].win_limit + 3258 align) < 3259 (chainp->wc_start & mask) - 3260 ((chainp->wc_end & mask) + align)) { 3261 /* 3262 * merge window 0 and 1, and set win1 3263 * to chainp 3264 */ 3265 win[0].win_limit = win[1].win_limit; 3266 win[1].win_start = 3267 chainp->wc_start & mask; 3268 win[1].win_limit = 3269 chainp->wc_end & mask; 3270 } else { 3271 win[1].win_limit = 3272 chainp->wc_end & mask; 3273 } 3274 } else { 3275 /* different flags */ 3276 3277 /* concatenate win0 and win1 */ 3278 win[0].win_limit = win[1].win_limit; 3279 /* allocate win[1] to new space */ 3280 win[1].win_start = chainp->wc_start & mask; 3281 win[1].win_limit = chainp->wc_end & mask; 3282 win[1].win_flags = chainp->wc_flags; 3283 } 3284 } else { 3285 /* the flags of win[0] and win[1] is different */ 3286 if (win[0].win_flags == chainp->wc_flags) { 3287 win[0].win_limit = chainp->wc_end & mask; 3288 /* 3289 * XXX this creates overlapping windows, so 3290 * what should the poor bridge do if one is 3291 * cachable, and the other is not? 3292 */ 3293 printf("%s: overlapping windows\n", 3294 sc->sc_dev.dv_xname); 3295 } else { 3296 win[1].win_limit = chainp->wc_end & mask; 3297 } 3298 } 3299 } 3300 3301 pc = sc->sc_pc; 3302 tag = sc->sc_tag; 3303 pci_conf_write(pc, tag, offs, win[0].win_start); 3304 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3305 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3306 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3307 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3308 pci_conf_read(pc, tag, offs), 3309 pci_conf_read(pc, tag, offs + 4) + align, 3310 pci_conf_read(pc, tag, offs + 8), 3311 pci_conf_read(pc, tag, offs + 12) + align)); 3312 3313 if (bst == sc->sc_memt) { 3314 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3315 3316 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3317 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3318 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3319 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3320 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3321 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3322 } 3323 } 3324 3325 #endif /* rbus */ 3326 3327 static void 3328 pccbb_powerhook(why, arg) 3329 int why; 3330 void *arg; 3331 { 3332 struct pccbb_softc *sc = arg; 3333 pcireg_t reg; 3334 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3335 bus_space_handle_t base_memh = sc->sc_base_memh; 3336 3337 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3338 3339 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3340 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3341 if (sc->sc_pil_intr_enable) { 3342 (void)pccbbintr_function(sc); 3343 } 3344 sc->sc_pil_intr_enable = 0; 3345 3346 /* ToDo: deactivate or suspend child devices */ 3347 3348 } 3349 3350 if (why == PWR_RESUME) { 3351 if (sc->sc_pwrmgt_offs != 0) { 3352 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3353 sc->sc_pwrmgt_offs + 4); 3354 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3355 reg & 0x100) { 3356 /* powrstate != D0 */ 3357 3358 printf("%s going back to D0 mode\n", 3359 sc->sc_dev.dv_xname); 3360 reg &= ~PCI_PMCSR_STATE_MASK; 3361 reg |= PCI_PMCSR_STATE_D0; 3362 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3363 pci_conf_write(sc->sc_pc, sc->sc_tag, 3364 sc->sc_pwrmgt_offs + 4, reg); 3365 3366 pci_conf_write(sc->sc_pc, sc->sc_tag, 3367 PCI_SOCKBASE, sc->sc_sockbase); 3368 pci_conf_write(sc->sc_pc, sc->sc_tag, 3369 PCI_BUSNUM, sc->sc_busnum); 3370 pccbb_chipinit(sc); 3371 /* setup memory and io space window for CB */ 3372 pccbb_winset(0x1000, sc, sc->sc_memt); 3373 pccbb_winset(0x04, sc, sc->sc_iot); 3374 } 3375 } 3376 3377 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3378 /* BIOS did not recover this register */ 3379 pci_conf_write (sc->sc_pc, sc->sc_tag, 3380 PCI_SOCKBASE, sc->sc_sockbase); 3381 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3382 /* BIOS did not recover this register */ 3383 pci_conf_write (sc->sc_pc, sc->sc_tag, 3384 PCI_BUSNUM, sc->sc_busnum); 3385 /* CSC Interrupt: Card detect interrupt on */ 3386 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3387 /* Card detect intr is turned on. */ 3388 reg |= CB_SOCKET_MASK_CD; 3389 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3390 /* reset interrupt */ 3391 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3392 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3393 3394 /* 3395 * check for card insertion or removal during suspend period. 3396 * XXX: the code can't cope with card swap (remove then 3397 * insert). how can we detect such situation? 3398 */ 3399 (void)pccbbintr(sc); 3400 3401 sc->sc_pil_intr_enable = 1; 3402 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3403 3404 /* ToDo: activate or wakeup child devices */ 3405 } 3406 } 3407
Indexes created Thu Sep 25 16:09:42 GMT 2025