pccbb.c revision 1.93
1 /* $NetBSD: pccbb.c,v 1.93 2003/12/10 02:55:48 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.93 2003/12/10 02:55:48 briggs Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static int pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, NULL, NULL); 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 332 /* Ricoh chips */ 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 346 /* Toshiba products */ 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 348 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 350 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 356 /* Cirrus Logic products */ 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 362 /* sentinel, or Generic chip */ 363 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 364 }; 365 366 static int 367 cb_chipset(pci_id, flagp) 368 u_int32_t pci_id; 369 int *flagp; 370 { 371 const struct yenta_chipinfo *yc; 372 373 /* Loop over except the last default entry. */ 374 for (yc = yc_chipsets; yc < yc_chipsets + 375 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 376 if (pci_id == yc->yc_id) 377 break; 378 379 if (flagp != NULL) 380 *flagp = yc->yc_flags; 381 382 return (yc->yc_chiptype); 383 } 384 385 static void 386 pccbb_shutdown(void *arg) 387 { 388 struct pccbb_softc *sc = arg; 389 pcireg_t command; 390 391 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 392 393 /* 394 * turn off power 395 * 396 * XXX - do not turn off power if chipset is TI 113X because 397 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 398 */ 399 if (sc->sc_chipset != CB_TI113X) { 400 pccbb_power((cardbus_chipset_tag_t)sc, 401 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 402 } 403 404 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 405 0); 406 407 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 408 409 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 410 PCI_COMMAND_MASTER_ENABLE); 411 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 412 413 } 414 415 void 416 pccbbattach(parent, self, aux) 417 struct device *parent; 418 struct device *self; 419 void *aux; 420 { 421 struct pccbb_softc *sc = (void *)self; 422 struct pci_attach_args *pa = aux; 423 pci_chipset_tag_t pc = pa->pa_pc; 424 pcireg_t busreg, reg, sock_base; 425 bus_addr_t sockbase; 426 char devinfo[256]; 427 int flags; 428 int pwrmgt_offs; 429 430 #ifdef __HAVE_PCCBB_ATTACH_HOOK 431 pccbb_attach_hook(parent, self, pa); 432 #endif 433 434 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 435 436 pci_devinfo(pa->pa_id, 0, 0, devinfo); 437 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 438 #ifdef CBB_DEBUG 439 printf(" (chipflags %x)", flags); 440 #endif 441 printf("\n"); 442 443 TAILQ_INIT(&sc->sc_memwindow); 444 TAILQ_INIT(&sc->sc_iowindow); 445 446 #if rbus 447 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 448 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 449 450 #if 0 451 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 452 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 453 #endif 454 #endif /* rbus */ 455 456 sc->sc_flags &= ~CBB_MEMHMAPPED; 457 458 /* power management: set D0 state */ 459 sc->sc_pwrmgt_offs = 0; 460 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 461 &pwrmgt_offs, 0)) { 462 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 463 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 464 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 465 reg &= ~PCI_PMCSR_STATE_MASK; 466 reg |= PCI_PMCSR_STATE_D0; 467 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 468 pci_conf_write(pc, pa->pa_tag, 469 pwrmgt_offs + PCI_PMCSR, reg); 470 } 471 472 sc->sc_pwrmgt_offs = pwrmgt_offs; 473 } 474 475 /* 476 * MAP socket registers and ExCA registers on memory-space 477 * When no valid address is set on socket base registers (on pci 478 * config space), get it not polite way. 479 */ 480 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 481 482 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 483 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 484 /* The address must be valid. */ 485 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 486 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 487 printf("%s: can't map socket base address 0x%x\n", 488 sc->sc_dev.dv_xname, sock_base); 489 /* 490 * I think it's funny: socket base registers must be 491 * mapped on memory space, but ... 492 */ 493 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 494 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 495 NULL)) { 496 printf("%s: can't map socket base address" 497 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 498 (unsigned long)sockbase); 499 /* give up... allocate reg space via rbus. */ 500 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 501 } else 502 sc->sc_flags |= CBB_MEMHMAPPED; 503 } else { 504 DPRINTF(("%s: socket base address 0x%lx\n", 505 sc->sc_dev.dv_xname, sockbase)); 506 sc->sc_flags |= CBB_MEMHMAPPED; 507 } 508 } 509 510 sc->sc_mem_start = 0; /* XXX */ 511 sc->sc_mem_end = 0xffffffff; /* XXX */ 512 513 /* 514 * When interrupt isn't routed correctly, give up probing cbb and do 515 * not kill pcic-compatible port. 516 */ 517 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 518 printf("%s: NOT USED because of unconfigured interrupt\n", 519 sc->sc_dev.dv_xname); 520 return; 521 } 522 523 /* 524 * When bus number isn't set correctly, give up using 32-bit CardBus 525 * mode. 526 */ 527 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 528 #if notyet 529 if (((busreg >> 8) & 0xff) == 0) { 530 printf("%s: CardBus support disabled because of unconfigured bus number\n", 531 sc->sc_dev.dv_xname); 532 flags |= PCCBB_PCMCIA_16BITONLY; 533 } 534 #endif 535 536 /* pccbb_machdep.c end */ 537 538 #if defined CBB_DEBUG 539 { 540 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 541 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 542 intrname[pa->pa_intrpin], pa->pa_intrline); 543 } 544 #endif 545 546 /* setup softc */ 547 sc->sc_pc = pc; 548 sc->sc_iot = pa->pa_iot; 549 sc->sc_memt = pa->pa_memt; 550 sc->sc_dmat = pa->pa_dmat; 551 sc->sc_tag = pa->pa_tag; 552 sc->sc_function = pa->pa_function; 553 sc->sc_sockbase = sock_base; 554 sc->sc_busnum = busreg; 555 556 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 557 558 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 559 560 shutdownhook_establish(pccbb_shutdown, sc); 561 562 /* Disable legacy register mapping. */ 563 switch (sc->sc_chipset) { 564 case CB_RX5C46X: /* fallthrough */ 565 #if 0 566 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 567 case CB_RX5C47X: 568 #endif 569 /* 570 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 571 * cannot be disabled by substituting 0 into PCI_LEGACY 572 * register. Ricoh CardBus bridges have special bits on Bridge 573 * control reg (addr 0x3e on PCI config space). 574 */ 575 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 576 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 577 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 578 break; 579 580 default: 581 /* XXX I don't know proper way to kill legacy I/O. */ 582 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 583 break; 584 } 585 586 config_defer(self, pccbb_pci_callback); 587 } 588 589 590 591 592 /* 593 * static void pccbb_pci_callback(struct device *self) 594 * 595 * The actual attach routine: get memory space for YENTA register 596 * space, setup YENTA register and route interrupt. 597 * 598 * This function should be deferred because this device may obtain 599 * memory space dynamically. This function must avoid obtaining 600 * memory area which has already kept for another device. 601 */ 602 static void 603 pccbb_pci_callback(self) 604 struct device *self; 605 { 606 struct pccbb_softc *sc = (void *)self; 607 pci_chipset_tag_t pc = sc->sc_pc; 608 pci_intr_handle_t ih; 609 const char *intrstr = NULL; 610 bus_addr_t sockbase; 611 struct cbslot_attach_args cba; 612 struct pcmciabus_attach_args paa; 613 struct cardslot_attach_args caa; 614 struct cardslot_softc *csc; 615 616 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 617 /* The socket registers aren't mapped correctly. */ 618 #if rbus 619 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 620 (sc->sc_chipset == CB_RX5C47X 621 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 622 0, &sockbase, &sc->sc_base_memh)) { 623 return; 624 } 625 sc->sc_base_memt = sc->sc_memt; 626 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 627 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 628 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 629 PCI_SOCKBASE))); 630 #else 631 sc->sc_base_memt = sc->sc_memt; 632 #if !defined CBB_PCI_BASE 633 #define CBB_PCI_BASE 0x20000000 634 #endif 635 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 636 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 637 /* cannot allocate memory space */ 638 return; 639 } 640 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 641 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 642 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 643 sc->sc_tag, PCI_SOCKBASE))); 644 sc->sc_sockbase = sockbase; 645 #endif 646 sc->sc_flags |= CBB_MEMHMAPPED; 647 } 648 649 /* bus bridge initialization */ 650 pccbb_chipinit(sc); 651 652 /* clear data structure for child device interrupt handlers */ 653 LIST_INIT(&sc->sc_pil); 654 sc->sc_pil_intr_enable = 1; 655 656 /* Map and establish the interrupt. */ 657 if (pci_intr_map(&sc->sc_pa, &ih)) { 658 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 659 return; 660 } 661 intrstr = pci_intr_string(pc, ih); 662 663 /* 664 * XXX pccbbintr should be called under the priority lower 665 * than any other hard interrputs. 666 */ 667 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 668 669 if (sc->sc_ih == NULL) { 670 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 671 if (intrstr != NULL) { 672 printf(" at %s", intrstr); 673 } 674 printf("\n"); 675 return; 676 } 677 678 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 679 powerhook_establish(pccbb_powerhook, sc); 680 681 { 682 u_int32_t sockstat; 683 684 sockstat = bus_space_read_4(sc->sc_base_memt, 685 sc->sc_base_memh, CB_SOCKET_STAT); 686 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 687 sc->sc_flags |= CBB_CARDEXIST; 688 } 689 } 690 691 /* 692 * attach cardbus 693 */ 694 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 695 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 696 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 697 698 /* initialize cbslot_attach */ 699 cba.cba_busname = "cardbus"; 700 cba.cba_iot = sc->sc_iot; 701 cba.cba_memt = sc->sc_memt; 702 cba.cba_dmat = sc->sc_dmat; 703 cba.cba_bus = (busreg >> 8) & 0x0ff; 704 cba.cba_cc = (void *)sc; 705 cba.cba_cf = &pccbb_funcs; 706 cba.cba_intrline = sc->sc_pa.pa_intrline; 707 708 #if rbus 709 cba.cba_rbus_iot = sc->sc_rbus_iot; 710 cba.cba_rbus_memt = sc->sc_rbus_memt; 711 #endif 712 713 cba.cba_cacheline = PCI_CACHELINE(bhlc); 714 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 715 716 if (bootverbose) { 717 printf("%s: cacheline 0x%x lattimer 0x%x\n", 718 sc->sc_dev.dv_xname, cba.cba_cacheline, 719 cba.cba_lattimer); 720 printf("%s: bhlc 0x%x lscp 0x%x\n", 721 sc->sc_dev.dv_xname, bhlc, busreg); 722 } 723 #if defined SHOW_REGS 724 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 725 sc->sc_base_memh); 726 #endif 727 } 728 729 pccbb_pcmcia_attach_setup(sc, &paa); 730 caa.caa_cb_attach = NULL; 731 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 732 caa.caa_cb_attach = &cba; 733 } 734 caa.caa_16_attach = &paa; 735 caa.caa_ph = &sc->sc_pcmcia_h; 736 737 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 738 DPRINTF(("pccbbattach: found cardslot\n")); 739 sc->sc_csc = csc; 740 } 741 742 return; 743 } 744 745 746 747 748 749 /* 750 * static void pccbb_chipinit(struct pccbb_softc *sc) 751 * 752 * This function initialize YENTA chip registers listed below: 753 * 1) PCI command reg, 754 * 2) PCI and CardBus latency timer, 755 * 3) route PCI interrupt, 756 * 4) close all memory and io windows. 757 * 5) turn off bus power. 758 * 6) card detect interrupt on. 759 * 7) clear interrupt 760 */ 761 static void 762 pccbb_chipinit(sc) 763 struct pccbb_softc *sc; 764 { 765 pci_chipset_tag_t pc = sc->sc_pc; 766 pcitag_t tag = sc->sc_tag; 767 bus_space_tag_t bmt = sc->sc_base_memt; 768 bus_space_handle_t bmh = sc->sc_base_memh; 769 pcireg_t reg; 770 771 /* 772 * Set PCI command reg. 773 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 774 */ 775 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 776 /* I believe it is harmless. */ 777 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 778 PCI_COMMAND_MASTER_ENABLE); 779 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 780 781 /* 782 * Set CardBus latency timer. 783 */ 784 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 785 if (PCI_CB_LATENCY(reg) < 0x20) { 786 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 787 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 788 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 789 } 790 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 791 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 792 793 /* 794 * Set PCI latency timer. 795 */ 796 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 797 if (PCI_LATTIMER(reg) < 0x10) { 798 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 799 reg |= (0x10 << PCI_LATTIMER_SHIFT); 800 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 801 } 802 DPRINTF(("PCI latency timer 0x%x (%x)\n", 803 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 804 805 806 /* Route functional interrupts to PCI. */ 807 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 808 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 809 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 810 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 811 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 812 813 switch (sc->sc_chipset) { 814 case CB_TI113X: 815 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 816 /* This bit is shared, but may read as 0 on some chips, so set 817 it explicitly on both functions. */ 818 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 819 /* CSC intr enable */ 820 reg |= PCI113X_CBCTRL_PCI_CSC; 821 /* functional intr prohibit | prohibit ISA routing */ 822 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 823 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 824 break; 825 826 case CB_TI12XX: 827 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 828 reg |= PCI12XX_SYSCTRL_VCCPROT; 829 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 830 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 831 reg |= PCI12XX_CBCTRL_CSC; 832 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 833 break; 834 835 case CB_TOPIC95B: 836 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 837 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 838 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 839 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 840 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 841 sc->sc_dev.dv_xname, reg)); 842 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 843 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 844 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 845 DPRINTF(("0x%x\n", reg)); 846 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 847 break; 848 849 case CB_TOPIC97: 850 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 851 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 852 sc->sc_dev.dv_xname, reg)); 853 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 854 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 855 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 856 reg |= TOPIC97_SLOT_CTRL_PCIINT; 857 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 858 DPRINTF(("0x%x\n", reg)); 859 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 860 /* make sure to assert LV card support bits */ 861 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 862 0x800 + 0x3e, 863 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 864 0x800 + 0x3e) | 0x03); 865 break; 866 } 867 868 /* Close all memory and I/O windows. */ 869 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 870 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 871 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 872 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 873 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 874 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 875 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 876 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 877 878 /* reset 16-bit pcmcia bus */ 879 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 880 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 881 882 /* turn off power */ 883 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 884 885 /* CSC Interrupt: Card detect interrupt on */ 886 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 887 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 888 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 889 /* reset interrupt */ 890 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 891 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 892 } 893 894 895 896 897 /* 898 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 899 * struct pcmciabus_attach_args *paa) 900 * 901 * This function attaches 16-bit PCcard bus. 902 */ 903 STATIC void 904 pccbb_pcmcia_attach_setup(sc, paa) 905 struct pccbb_softc *sc; 906 struct pcmciabus_attach_args *paa; 907 { 908 struct pcic_handle *ph = &sc->sc_pcmcia_h; 909 #if rbus 910 rbus_tag_t rb; 911 #endif 912 913 /* initialize pcmcia part in pccbb_softc */ 914 ph->ph_parent = (struct device *)sc; 915 ph->sock = sc->sc_function; 916 ph->flags = 0; 917 ph->shutdown = 0; 918 ph->ih_irq = sc->sc_pa.pa_intrline; 919 ph->ph_bus_t = sc->sc_base_memt; 920 ph->ph_bus_h = sc->sc_base_memh; 921 ph->ph_read = pccbb_pcmcia_read; 922 ph->ph_write = pccbb_pcmcia_write; 923 sc->sc_pct = &pccbb_pcmcia_funcs; 924 925 /* 926 * We need to do a few things here: 927 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 928 * setting the IRQ numbers to 0. 929 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 930 * routing of CSC interrupts (e.g. card removal) to PCI while in 931 * PCMCIA mode. We just leave this set all the time. 932 * 3) Enable card insertion/removal interrupts in case the chip also 933 * needs that while in PCMCIA mode. 934 * 4) Clear any pending CSC interrupt. 935 */ 936 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 937 if (sc->sc_chipset == CB_TI113X) { 938 Pcic_write(ph, PCIC_CSC_INTR, 0); 939 } else { 940 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 941 Pcic_read(ph, PCIC_CSC); 942 } 943 944 /* initialize pcmcia bus attachment */ 945 paa->paa_busname = "pcmcia"; 946 paa->pct = sc->sc_pct; 947 paa->pch = ph; 948 paa->iobase = 0; /* I don't use them */ 949 paa->iosize = 0; 950 #if rbus 951 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 952 paa->iobase = rb->rb_start + rb->rb_offset; 953 paa->iosize = rb->rb_end - rb->rb_start; 954 #endif 955 956 return; 957 } 958 959 #if 0 960 STATIC void 961 pccbb_pcmcia_attach_card(ph) 962 struct pcic_handle *ph; 963 { 964 if (ph->flags & PCIC_FLAG_CARDP) { 965 panic("pccbb_pcmcia_attach_card: already attached"); 966 } 967 968 /* call the MI attach function */ 969 pcmcia_card_attach(ph->pcmcia); 970 971 ph->flags |= PCIC_FLAG_CARDP; 972 } 973 974 STATIC void 975 pccbb_pcmcia_detach_card(ph, flags) 976 struct pcic_handle *ph; 977 int flags; 978 { 979 if (!(ph->flags & PCIC_FLAG_CARDP)) { 980 panic("pccbb_pcmcia_detach_card: already detached"); 981 } 982 983 ph->flags &= ~PCIC_FLAG_CARDP; 984 985 /* call the MI detach function */ 986 pcmcia_card_detach(ph->pcmcia, flags); 987 } 988 #endif 989 990 /* 991 * int pccbbintr(arg) 992 * void *arg; 993 * This routine handles the interrupt from Yenta PCI-CardBus bridge 994 * itself. 995 */ 996 int 997 pccbbintr(arg) 998 void *arg; 999 { 1000 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1001 u_int32_t sockevent, sockstate; 1002 bus_space_tag_t memt = sc->sc_base_memt; 1003 bus_space_handle_t memh = sc->sc_base_memh; 1004 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1005 1006 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1007 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1008 Pcic_read(ph, PCIC_CSC); 1009 1010 if (sockevent == 0) { 1011 /* This intr is not for me: it may be for my child devices. */ 1012 if (sc->sc_pil_intr_enable) { 1013 return pccbbintr_function(sc); 1014 } else { 1015 return 0; 1016 } 1017 } 1018 1019 if (sockevent & CB_SOCKET_EVENT_CD) { 1020 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1021 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1022 /* A card should be removed. */ 1023 if (sc->sc_flags & CBB_CARDEXIST) { 1024 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1025 sockevent)); 1026 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1027 sc->sc_flags &= ~CBB_CARDEXIST; 1028 if (sc->sc_csc->sc_status & 1029 CARDSLOT_STATUS_CARD_16) { 1030 #if 0 1031 struct pcic_handle *ph = 1032 &sc->sc_pcmcia_h; 1033 1034 pcmcia_card_deactivate(ph->pcmcia); 1035 pccbb_pcmcia_socket_disable(ph); 1036 pccbb_pcmcia_detach_card(ph, 1037 DETACH_FORCE); 1038 #endif 1039 cardslot_event_throw(sc->sc_csc, 1040 CARDSLOT_EVENT_REMOVAL_16); 1041 } else if (sc->sc_csc->sc_status & 1042 CARDSLOT_STATUS_CARD_CB) { 1043 /* Cardbus intr removed */ 1044 cardslot_event_throw(sc->sc_csc, 1045 CARDSLOT_EVENT_REMOVAL_CB); 1046 } 1047 } else if (sc->sc_flags & CBB_INSERTING) { 1048 sc->sc_flags &= ~CBB_INSERTING; 1049 callout_stop(&sc->sc_insert_ch); 1050 } 1051 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1052 /* 1053 * The pccbbintr may called from powerdown hook when 1054 * the system resumed, to detect the card 1055 * insertion/removal during suspension. 1056 */ 1057 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1058 if (sc->sc_flags & CBB_INSERTING) { 1059 callout_stop(&sc->sc_insert_ch); 1060 } 1061 callout_reset(&sc->sc_insert_ch, hz / 5, 1062 pci113x_insert, sc); 1063 sc->sc_flags |= CBB_INSERTING; 1064 } 1065 } 1066 1067 return (1); 1068 } 1069 1070 /* 1071 * static int pccbbintr_function(struct pccbb_softc *sc) 1072 * 1073 * This function calls each interrupt handler registered at the 1074 * bridge. The interrupt handlers are called in registered order. 1075 */ 1076 static int 1077 pccbbintr_function(sc) 1078 struct pccbb_softc *sc; 1079 { 1080 int retval = 0, val; 1081 struct pccbb_intrhand_list *pil; 1082 /*###1082 [cc] warning: `s' might be used uninitialized in this function%%%*/ 1083 int s, splchanged; 1084 1085 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1086 pil = LIST_NEXT(pil, pil_next)) { 1087 /* 1088 * XXX priority change. gross. I use if-else 1089 * sentense instead of switch-case sentense because of 1090 * avoiding duplicate case value error. More than one 1091 * IPL_XXX use same value. It depends on 1092 * implimentation. 1093 */ 1094 splchanged = 1; 1095 if (pil->pil_level == IPL_SERIAL) { 1096 s = splserial(); 1097 } else if (pil->pil_level == IPL_HIGH) { 1098 s = splhigh(); 1099 } else if (pil->pil_level == IPL_CLOCK) { 1100 s = splclock(); 1101 } else if (pil->pil_level == IPL_AUDIO) { 1102 s = splaudio(); 1103 } else if (pil->pil_level == IPL_VM) { 1104 s = splvm(); 1105 } else if (pil->pil_level == IPL_TTY) { 1106 s = spltty(); 1107 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1108 s = splsoftserial(); 1109 } else if (pil->pil_level == IPL_NET) { 1110 s = splnet(); 1111 } else { 1112 s = 0; /* XXX: gcc */ 1113 splchanged = 0; 1114 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1115 } 1116 1117 val = (*pil->pil_func)(pil->pil_arg); 1118 1119 if (splchanged != 0) { 1120 splx(s); 1121 } 1122 1123 retval = retval == 1 ? 1 : 1124 retval == 0 ? val : val != 0 ? val : retval; 1125 } 1126 1127 return retval; 1128 } 1129 1130 static void 1131 pci113x_insert(arg) 1132 void *arg; 1133 { 1134 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1135 u_int32_t sockevent, sockstate; 1136 1137 if (!(sc->sc_flags & CBB_INSERTING)) { 1138 /* We add a card only under inserting state. */ 1139 return; 1140 } 1141 sc->sc_flags &= ~CBB_INSERTING; 1142 1143 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1144 CB_SOCKET_EVENT); 1145 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1146 CB_SOCKET_STAT); 1147 1148 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1149 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1150 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1151 sc->sc_flags |= CBB_CARDEXIST; 1152 /* call pccard interrupt handler here */ 1153 if (sockstate & CB_SOCKET_STAT_16BIT) { 1154 /* 16-bit card found */ 1155 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1156 cardslot_event_throw(sc->sc_csc, 1157 CARDSLOT_EVENT_INSERTION_16); 1158 } else if (sockstate & CB_SOCKET_STAT_CB) { 1159 /* cardbus card found */ 1160 /* cardbus_attach_card(sc->sc_csc); */ 1161 cardslot_event_throw(sc->sc_csc, 1162 CARDSLOT_EVENT_INSERTION_CB); 1163 } else { 1164 /* who are you? */ 1165 } 1166 } else { 1167 callout_reset(&sc->sc_insert_ch, hz / 10, 1168 pci113x_insert, sc); 1169 } 1170 } 1171 1172 #define PCCBB_PCMCIA_OFFSET 0x800 1173 static u_int8_t 1174 pccbb_pcmcia_read(ph, reg) 1175 struct pcic_handle *ph; 1176 int reg; 1177 { 1178 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1179 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1180 1181 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1182 PCCBB_PCMCIA_OFFSET + reg); 1183 } 1184 1185 static void 1186 pccbb_pcmcia_write(ph, reg, val) 1187 struct pcic_handle *ph; 1188 int reg; 1189 u_int8_t val; 1190 { 1191 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1192 val); 1193 1194 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1195 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1196 } 1197 1198 /* 1199 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1200 */ 1201 STATIC int 1202 pccbb_ctrl(ct, command) 1203 cardbus_chipset_tag_t ct; 1204 int command; 1205 { 1206 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1207 1208 switch (command) { 1209 case CARDBUS_CD: 1210 if (2 == pccbb_detect_card(sc)) { 1211 int retval = 0; 1212 int status = cb_detect_voltage(sc); 1213 if (PCCARD_VCC_5V & status) { 1214 retval |= CARDBUS_5V_CARD; 1215 } 1216 if (PCCARD_VCC_3V & status) { 1217 retval |= CARDBUS_3V_CARD; 1218 } 1219 if (PCCARD_VCC_XV & status) { 1220 retval |= CARDBUS_XV_CARD; 1221 } 1222 if (PCCARD_VCC_YV & status) { 1223 retval |= CARDBUS_YV_CARD; 1224 } 1225 return retval; 1226 } else { 1227 return 0; 1228 } 1229 case CARDBUS_RESET: 1230 return cb_reset(sc); 1231 case CARDBUS_IO_ENABLE: /* fallthrough */ 1232 case CARDBUS_IO_DISABLE: /* fallthrough */ 1233 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1234 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1235 case CARDBUS_BM_ENABLE: /* fallthrough */ 1236 case CARDBUS_BM_DISABLE: /* fallthrough */ 1237 /* XXX: I think we don't need to call this function below. */ 1238 return pccbb_cardenable(sc, command); 1239 } 1240 1241 return 0; 1242 } 1243 1244 /* 1245 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1246 * This function returns true when it succeeds and returns false when 1247 * it fails. 1248 */ 1249 STATIC int 1250 pccbb_power(ct, command) 1251 cardbus_chipset_tag_t ct; 1252 int command; 1253 { 1254 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1255 1256 u_int32_t status, sock_ctrl, reg_ctrl; 1257 bus_space_tag_t memt = sc->sc_base_memt; 1258 bus_space_handle_t memh = sc->sc_base_memh; 1259 1260 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1261 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1262 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1263 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1264 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1265 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1266 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1267 "UNKNOWN", 1268 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1269 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1270 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1271 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1272 "UNKNOWN", command)); 1273 1274 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1275 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1276 1277 switch (command & CARDBUS_VCCMASK) { 1278 case CARDBUS_VCC_UC: 1279 break; 1280 case CARDBUS_VCC_5V: 1281 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1282 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1283 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1284 } else { 1285 printf("%s: BAD voltage request: no 5 V card\n", 1286 sc->sc_dev.dv_xname); 1287 return 0; 1288 } 1289 break; 1290 case CARDBUS_VCC_3V: 1291 if (CB_SOCKET_STAT_3VCARD & status) { 1292 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1293 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1294 } else { 1295 printf("%s: BAD voltage request: no 3.3 V card\n", 1296 sc->sc_dev.dv_xname); 1297 return 0; 1298 } 1299 break; 1300 case CARDBUS_VCC_0V: 1301 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1302 break; 1303 default: 1304 return 0; /* power NEVER changed */ 1305 } 1306 1307 switch (command & CARDBUS_VPPMASK) { 1308 case CARDBUS_VPP_UC: 1309 break; 1310 case CARDBUS_VPP_0V: 1311 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1312 break; 1313 case CARDBUS_VPP_VCC: 1314 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1315 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1316 break; 1317 case CARDBUS_VPP_12V: 1318 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1319 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1320 break; 1321 } 1322 1323 #if 0 1324 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1325 #endif 1326 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1327 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1328 1329 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1330 printf 1331 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1332 sc->sc_dev.dv_xname, sock_ctrl, status); 1333 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1334 (command & CARDBUS_VCCMASK) == 1335 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1336 CARDBUS_VCCMASK) == 1337 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1338 CARDBUS_VCCMASK) == 1339 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1340 CARDBUS_VCCMASK) == 1341 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1342 CARDBUS_VCCMASK) == 1343 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1344 CARDBUS_VCCMASK) == 1345 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1346 (command & CARDBUS_VPPMASK) == 1347 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1348 CARDBUS_VPPMASK) == 1349 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1350 CARDBUS_VPPMASK) == 1351 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1352 CARDBUS_VPPMASK) == 1353 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1354 #if 0 1355 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1356 u_int32_t force = 1357 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1358 /* Reset Bad Vcc request */ 1359 force &= ~CB_SOCKET_FORCE_BADVCC; 1360 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1361 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1362 CB_SOCKET_STAT)); 1363 return 1; 1364 } 1365 #endif 1366 return 0; 1367 } 1368 1369 if (sc->sc_chipset == CB_TOPIC97) { 1370 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1371 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1372 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1373 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1374 else 1375 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1376 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1377 } 1378 1379 /* 1380 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1381 * time is 20 ms, some PC-Card bridge requires longer duration. 1382 */ 1383 #if 0 /* XXX called on interrupt context */ 1384 DELAY_MS(300, sc); 1385 #else 1386 delay(300 * 1000); 1387 #endif 1388 1389 return 1; /* power changed correctly */ 1390 } 1391 1392 #if defined CB_PCMCIA_POLL 1393 struct cb_poll_str { 1394 void *arg; 1395 int (*func) __P((void *)); 1396 int level; 1397 pccard_chipset_tag_t ct; 1398 int count; 1399 struct callout poll_ch; 1400 }; 1401 1402 static struct cb_poll_str cb_poll[10]; 1403 static int cb_poll_n = 0; 1404 1405 static void cb_pcmcia_poll __P((void *arg)); 1406 1407 static void 1408 cb_pcmcia_poll(arg) 1409 void *arg; 1410 { 1411 struct cb_poll_str *poll = arg; 1412 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1413 struct pccbb_softc *sc = psc->cpc_parent; 1414 int s; 1415 u_int32_t spsr; /* socket present-state reg */ 1416 1417 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1418 switch (poll->level) { 1419 case IPL_NET: 1420 s = splnet(); 1421 break; 1422 case IPL_BIO: 1423 s = splbio(); 1424 break; 1425 case IPL_TTY: /* fallthrough */ 1426 default: 1427 s = spltty(); 1428 break; 1429 } 1430 1431 spsr = 1432 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1433 CB_SOCKET_STAT); 1434 1435 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1436 if (!(spsr & 0x40)) { /* CINT low */ 1437 #else 1438 if (1) { 1439 #endif 1440 if ((*poll->func) (poll->arg) == 1) { 1441 ++poll->count; 1442 printf("intr: reported from poller, 0x%x\n", spsr); 1443 #if defined LEVEL2 1444 } else { 1445 printf("intr: miss! 0x%x\n", spsr); 1446 #endif 1447 } 1448 } 1449 splx(s); 1450 } 1451 #endif /* defined CB_PCMCIA_POLL */ 1452 1453 /* 1454 * static int pccbb_detect_card(struct pccbb_softc *sc) 1455 * return value: 0 if no card exists. 1456 * 1 if 16-bit card exists. 1457 * 2 if cardbus card exists. 1458 */ 1459 static int 1460 pccbb_detect_card(sc) 1461 struct pccbb_softc *sc; 1462 { 1463 bus_space_handle_t base_memh = sc->sc_base_memh; 1464 bus_space_tag_t base_memt = sc->sc_base_memt; 1465 u_int32_t sockstat = 1466 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1467 int retval = 0; 1468 1469 /* CD1 and CD2 asserted */ 1470 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1471 /* card must be present */ 1472 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1473 /* NOTACARD DEASSERTED */ 1474 if (CB_SOCKET_STAT_CB & sockstat) { 1475 /* CardBus mode */ 1476 retval = 2; 1477 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1478 /* 16-bit mode */ 1479 retval = 1; 1480 } 1481 } 1482 } 1483 return retval; 1484 } 1485 1486 /* 1487 * STATIC int cb_reset(struct pccbb_softc *sc) 1488 * This function resets CardBus card. 1489 */ 1490 STATIC int 1491 cb_reset(sc) 1492 struct pccbb_softc *sc; 1493 { 1494 /* 1495 * Reset Assert at least 20 ms 1496 * Some machines request longer duration. 1497 */ 1498 int reset_duration = 1499 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1500 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1501 1502 /* Reset bit Assert (bit 6 at 0x3E) */ 1503 bcr |= CB_BCR_RESET_ENABLE; 1504 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1505 DELAY_MS(reset_duration, sc); 1506 1507 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1508 /* Reset bit Deassert (bit 6 at 0x3E) */ 1509 bcr &= ~CB_BCR_RESET_ENABLE; 1510 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1511 DELAY_MS(reset_duration, sc); 1512 } 1513 /* No card found on the slot. Keep Reset. */ 1514 return 1; 1515 } 1516 1517 /* 1518 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1519 * This function detect card Voltage. 1520 */ 1521 STATIC int 1522 cb_detect_voltage(sc) 1523 struct pccbb_softc *sc; 1524 { 1525 u_int32_t psr; /* socket present-state reg */ 1526 bus_space_tag_t iot = sc->sc_base_memt; 1527 bus_space_handle_t ioh = sc->sc_base_memh; 1528 int vol = PCCARD_VCC_UKN; /* set 0 */ 1529 1530 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1531 1532 if (0x400u & psr) { 1533 vol |= PCCARD_VCC_5V; 1534 } 1535 if (0x800u & psr) { 1536 vol |= PCCARD_VCC_3V; 1537 } 1538 1539 return vol; 1540 } 1541 1542 STATIC int 1543 cbbprint(aux, pcic) 1544 void *aux; 1545 const char *pcic; 1546 { 1547 /* 1548 struct cbslot_attach_args *cba = aux; 1549 1550 if (cba->cba_slot >= 0) { 1551 aprint_normal(" slot %d", cba->cba_slot); 1552 } 1553 */ 1554 return UNCONF; 1555 } 1556 1557 /* 1558 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1559 * This function enables and disables the card 1560 */ 1561 STATIC int 1562 pccbb_cardenable(sc, function) 1563 struct pccbb_softc *sc; 1564 int function; 1565 { 1566 u_int32_t command = 1567 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1568 1569 DPRINTF(("pccbb_cardenable:")); 1570 switch (function) { 1571 case CARDBUS_IO_ENABLE: 1572 command |= PCI_COMMAND_IO_ENABLE; 1573 break; 1574 case CARDBUS_IO_DISABLE: 1575 command &= ~PCI_COMMAND_IO_ENABLE; 1576 break; 1577 case CARDBUS_MEM_ENABLE: 1578 command |= PCI_COMMAND_MEM_ENABLE; 1579 break; 1580 case CARDBUS_MEM_DISABLE: 1581 command &= ~PCI_COMMAND_MEM_ENABLE; 1582 break; 1583 case CARDBUS_BM_ENABLE: 1584 command |= PCI_COMMAND_MASTER_ENABLE; 1585 break; 1586 case CARDBUS_BM_DISABLE: 1587 command &= ~PCI_COMMAND_MASTER_ENABLE; 1588 break; 1589 default: 1590 return 0; 1591 } 1592 1593 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1594 DPRINTF((" command reg 0x%x\n", command)); 1595 return 1; 1596 } 1597 1598 #if !rbus 1599 /* 1600 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1601 */ 1602 static int 1603 pccbb_io_open(ct, win, start, end) 1604 cardbus_chipset_tag_t ct; 1605 int win; 1606 u_int32_t start, end; 1607 { 1608 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1609 int basereg; 1610 int limitreg; 1611 1612 if ((win < 0) || (win > 2)) { 1613 #if defined DIAGNOSTIC 1614 printf("cardbus_io_open: window out of range %d\n", win); 1615 #endif 1616 return 0; 1617 } 1618 1619 basereg = win * 8 + 0x2c; 1620 limitreg = win * 8 + 0x30; 1621 1622 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1623 start, basereg, end, limitreg)); 1624 1625 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1626 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1627 return 1; 1628 } 1629 1630 /* 1631 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1632 */ 1633 static int 1634 pccbb_io_close(ct, win) 1635 cardbus_chipset_tag_t ct; 1636 int win; 1637 { 1638 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1639 int basereg; 1640 int limitreg; 1641 1642 if ((win < 0) || (win > 2)) { 1643 #if defined DIAGNOSTIC 1644 printf("cardbus_io_close: window out of range %d\n", win); 1645 #endif 1646 return 0; 1647 } 1648 1649 basereg = win * 8 + 0x2c; 1650 limitreg = win * 8 + 0x30; 1651 1652 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1653 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1654 return 1; 1655 } 1656 1657 /* 1658 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1659 */ 1660 static int 1661 pccbb_mem_open(ct, win, start, end) 1662 cardbus_chipset_tag_t ct; 1663 int win; 1664 u_int32_t start, end; 1665 { 1666 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1667 int basereg; 1668 int limitreg; 1669 1670 if ((win < 0) || (win > 2)) { 1671 #if defined DIAGNOSTIC 1672 printf("cardbus_mem_open: window out of range %d\n", win); 1673 #endif 1674 return 0; 1675 } 1676 1677 basereg = win * 8 + 0x1c; 1678 limitreg = win * 8 + 0x20; 1679 1680 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1681 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1682 return 1; 1683 } 1684 1685 /* 1686 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1687 */ 1688 static int 1689 pccbb_mem_close(ct, win) 1690 cardbus_chipset_tag_t ct; 1691 int win; 1692 { 1693 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1694 int basereg; 1695 int limitreg; 1696 1697 if ((win < 0) || (win > 2)) { 1698 #if defined DIAGNOSTIC 1699 printf("cardbus_mem_close: window out of range %d\n", win); 1700 #endif 1701 return 0; 1702 } 1703 1704 basereg = win * 8 + 0x1c; 1705 limitreg = win * 8 + 0x20; 1706 1707 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1708 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1709 return 1; 1710 } 1711 #endif 1712 1713 /* 1714 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1715 * int irq, 1716 * int level, 1717 * int (* func) __P((void *)), 1718 * void *arg) 1719 * 1720 * This function registers an interrupt handler at the bridge, in 1721 * order not to call the interrupt handlers of child devices when 1722 * a card-deletion interrupt occurs. 1723 * 1724 * The arguments irq and level are not used. 1725 */ 1726 static void * 1727 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1728 cardbus_chipset_tag_t ct; 1729 int irq, level; 1730 int (*func) __P((void *)); 1731 void *arg; 1732 { 1733 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1734 1735 return pccbb_intr_establish(sc, irq, level, func, arg); 1736 } 1737 1738 1739 /* 1740 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1741 * void *ih) 1742 * 1743 * This function removes an interrupt handler pointed by ih. 1744 */ 1745 static void 1746 pccbb_cb_intr_disestablish(ct, ih) 1747 cardbus_chipset_tag_t ct; 1748 void *ih; 1749 { 1750 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1751 1752 pccbb_intr_disestablish(sc, ih); 1753 } 1754 1755 1756 void 1757 pccbb_intr_route(sc) 1758 struct pccbb_softc *sc; 1759 { 1760 pcireg_t reg; 1761 1762 /* initialize bridge intr routing */ 1763 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1764 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1765 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1766 1767 switch (sc->sc_chipset) { 1768 case CB_TI113X: 1769 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1770 /* functional intr enabled */ 1771 reg |= PCI113X_CBCTRL_PCI_INTR; 1772 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1773 break; 1774 default: 1775 break; 1776 } 1777 } 1778 1779 /* 1780 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1781 * int irq, 1782 * int level, 1783 * int (* func) __P((void *)), 1784 * void *arg) 1785 * 1786 * This function registers an interrupt handler at the bridge, in 1787 * order not to call the interrupt handlers of child devices when 1788 * a card-deletion interrupt occurs. 1789 * 1790 * The arguments irq is not used because pccbb selects intr vector. 1791 */ 1792 static void * 1793 pccbb_intr_establish(sc, irq, level, func, arg) 1794 struct pccbb_softc *sc; 1795 int irq, level; 1796 int (*func) __P((void *)); 1797 void *arg; 1798 { 1799 struct pccbb_intrhand_list *pil, *newpil; 1800 1801 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1802 1803 if (LIST_EMPTY(&sc->sc_pil)) { 1804 pccbb_intr_route(sc); 1805 } 1806 1807 /* 1808 * Allocate a room for interrupt handler structure. 1809 */ 1810 if (NULL == (newpil = 1811 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1812 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1813 return NULL; 1814 } 1815 1816 newpil->pil_func = func; 1817 newpil->pil_arg = arg; 1818 newpil->pil_level = level; 1819 1820 if (LIST_EMPTY(&sc->sc_pil)) { 1821 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1822 } else { 1823 for (pil = LIST_FIRST(&sc->sc_pil); 1824 LIST_NEXT(pil, pil_next) != NULL; 1825 pil = LIST_NEXT(pil, pil_next)); 1826 LIST_INSERT_AFTER(pil, newpil, pil_next); 1827 } 1828 1829 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1830 LIST_FIRST(&sc->sc_pil))); 1831 1832 return newpil; 1833 } 1834 1835 /* 1836 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1837 * void *ih) 1838 * 1839 * This function removes an interrupt handler pointed by ih. ih 1840 * should be the value returned by cardbus_intr_establish() or 1841 * NULL. 1842 * 1843 * When ih is NULL, this function will do nothing. 1844 */ 1845 static void 1846 pccbb_intr_disestablish(sc, ih) 1847 struct pccbb_softc *sc; 1848 void *ih; 1849 { 1850 struct pccbb_intrhand_list *pil; 1851 pcireg_t reg; 1852 1853 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1854 LIST_FIRST(&sc->sc_pil))); 1855 1856 if (ih == NULL) { 1857 /* intr handler is not set */ 1858 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1859 return; 1860 } 1861 1862 #ifdef DIAGNOSTIC 1863 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1864 pil = LIST_NEXT(pil, pil_next)) { 1865 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1866 if (pil == ih) { 1867 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1868 break; 1869 } 1870 } 1871 if (pil == NULL) { 1872 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1873 sc->sc_dev.dv_xname, ih); 1874 } 1875 #endif 1876 1877 pil = (struct pccbb_intrhand_list *)ih; 1878 LIST_REMOVE(pil, pil_next); 1879 free(pil, M_DEVBUF); 1880 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1881 1882 if (LIST_EMPTY(&sc->sc_pil)) { 1883 /* No interrupt handlers */ 1884 1885 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1886 1887 /* stop routing PCI intr */ 1888 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1889 reg |= CB_BCR_INTR_IREQ_ENABLE; 1890 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1891 1892 switch (sc->sc_chipset) { 1893 case CB_TI113X: 1894 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1895 /* functional intr disabled */ 1896 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1897 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1898 break; 1899 default: 1900 break; 1901 } 1902 } 1903 } 1904 1905 #if defined SHOW_REGS 1906 static void 1907 cb_show_regs(pc, tag, memt, memh) 1908 pci_chipset_tag_t pc; 1909 pcitag_t tag; 1910 bus_space_tag_t memt; 1911 bus_space_handle_t memh; 1912 { 1913 int i; 1914 printf("PCI config regs:"); 1915 for (i = 0; i < 0x50; i += 4) { 1916 if (i % 16 == 0) { 1917 printf("\n 0x%02x:", i); 1918 } 1919 printf(" %08x", pci_conf_read(pc, tag, i)); 1920 } 1921 for (i = 0x80; i < 0xb0; i += 4) { 1922 if (i % 16 == 0) { 1923 printf("\n 0x%02x:", i); 1924 } 1925 printf(" %08x", pci_conf_read(pc, tag, i)); 1926 } 1927 1928 if (memh == 0) { 1929 printf("\n"); 1930 return; 1931 } 1932 1933 printf("\nsocket regs:"); 1934 for (i = 0; i <= 0x10; i += 0x04) { 1935 printf(" %08x", bus_space_read_4(memt, memh, i)); 1936 } 1937 printf("\nExCA regs:"); 1938 for (i = 0; i < 0x08; ++i) { 1939 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1940 } 1941 printf("\n"); 1942 return; 1943 } 1944 #endif 1945 1946 /* 1947 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1948 * int busno, int devno, int function) 1949 * This is the function to make a tag to access config space of 1950 * a CardBus Card. It works same as pci_conf_read. 1951 */ 1952 static cardbustag_t 1953 pccbb_make_tag(cc, busno, devno, function) 1954 cardbus_chipset_tag_t cc; 1955 int busno, devno, function; 1956 { 1957 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1958 1959 return pci_make_tag(sc->sc_pc, busno, devno, function); 1960 } 1961 1962 static void 1963 pccbb_free_tag(cc, tag) 1964 cardbus_chipset_tag_t cc; 1965 cardbustag_t tag; 1966 { 1967 } 1968 1969 /* 1970 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1971 * cardbustag_t tag, int offset) 1972 * This is the function to read the config space of a CardBus Card. 1973 * It works same as pci_conf_read. 1974 */ 1975 static cardbusreg_t 1976 pccbb_conf_read(cc, tag, offset) 1977 cardbus_chipset_tag_t cc; 1978 cardbustag_t tag; 1979 int offset; /* register offset */ 1980 { 1981 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1982 1983 return pci_conf_read(sc->sc_pc, tag, offset); 1984 } 1985 1986 /* 1987 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1988 * int offs, cardbusreg_t val) 1989 * This is the function to write the config space of a CardBus Card. 1990 * It works same as pci_conf_write. 1991 */ 1992 static void 1993 pccbb_conf_write(cc, tag, reg, val) 1994 cardbus_chipset_tag_t cc; 1995 cardbustag_t tag; 1996 int reg; /* register offset */ 1997 cardbusreg_t val; 1998 { 1999 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2000 2001 pci_conf_write(sc->sc_pc, tag, reg, val); 2002 } 2003 2004 #if 0 2005 STATIC int 2006 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2007 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2008 int speed, int flags, 2009 bus_space_handle_t * iohp) 2010 #endif 2011 /* 2012 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2013 * bus_addr_t start, bus_size_t size, 2014 * bus_size_t align, 2015 * struct pcmcia_io_handle *pcihp 2016 * 2017 * This function only allocates I/O region for pccard. This function 2018 * never maps the allocated region to pccard I/O area. 2019 * 2020 * XXX: The interface of this function is not very good, I believe. 2021 */ 2022 STATIC int 2023 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2024 pcmcia_chipset_handle_t pch; 2025 bus_addr_t start; /* start address */ 2026 bus_size_t size; 2027 bus_size_t align; 2028 struct pcmcia_io_handle *pcihp; 2029 { 2030 struct pcic_handle *ph = (struct pcic_handle *)pch; 2031 bus_addr_t ioaddr; 2032 int flags = 0; 2033 bus_space_tag_t iot; 2034 bus_space_handle_t ioh; 2035 bus_addr_t mask; 2036 #if rbus 2037 rbus_tag_t rb; 2038 #endif 2039 if (align == 0) { 2040 align = size; /* XXX: funny??? */ 2041 } 2042 2043 if (start != 0) { 2044 /* XXX: assume all card decode lower 10 bits by its hardware */ 2045 mask = 0x3ff; 2046 /* enforce to use only masked address */ 2047 start &= mask; 2048 } else { 2049 /* 2050 * calculate mask: 2051 * 1. get the most significant bit of size (call it msb). 2052 * 2. compare msb with the value of size. 2053 * 3. if size is larger, shift msb left once. 2054 * 4. obtain mask value to decrement msb. 2055 */ 2056 bus_size_t size_tmp = size; 2057 int shifts = 0; 2058 2059 mask = 1; 2060 while (size_tmp) { 2061 ++shifts; 2062 size_tmp >>= 1; 2063 } 2064 mask = (1 << shifts); 2065 if (mask < size) { 2066 mask <<= 1; 2067 } 2068 --mask; 2069 } 2070 2071 /* 2072 * Allocate some arbitrary I/O space. 2073 */ 2074 2075 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2076 2077 #if rbus 2078 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2079 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2080 return 1; 2081 } 2082 DPRINTF(("pccbb_pcmcia_io_alloc alloc port %lx+%lx\n", 2083 (u_long) ioaddr, (u_long) size)); 2084 #else 2085 if (start) { 2086 ioaddr = start; 2087 if (bus_space_map(iot, start, size, 0, &ioh)) { 2088 return 1; 2089 } 2090 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 2091 (u_long) ioaddr, (u_long) size)); 2092 } else { 2093 flags |= PCMCIA_IO_ALLOCATED; 2094 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2095 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2096 size, align, 0, 0, &ioaddr, &ioh)) { 2097 /* No room be able to be get. */ 2098 return 1; 2099 } 2100 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2101 (u_long) ioaddr, (u_long) size)); 2102 } 2103 #endif 2104 2105 pcihp->iot = iot; 2106 pcihp->ioh = ioh; 2107 pcihp->addr = ioaddr; 2108 pcihp->size = size; 2109 pcihp->flags = flags; 2110 2111 return 0; 2112 } 2113 2114 /* 2115 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2116 * struct pcmcia_io_handle *pcihp) 2117 * 2118 * This function only frees I/O region for pccard. 2119 * 2120 * XXX: The interface of this function is not very good, I believe. 2121 */ 2122 void 2123 pccbb_pcmcia_io_free(pch, pcihp) 2124 pcmcia_chipset_handle_t pch; 2125 struct pcmcia_io_handle *pcihp; 2126 { 2127 #if !rbus 2128 bus_space_tag_t iot = pcihp->iot; 2129 #endif 2130 bus_space_handle_t ioh = pcihp->ioh; 2131 bus_size_t size = pcihp->size; 2132 2133 #if rbus 2134 struct pccbb_softc *sc = 2135 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2136 rbus_tag_t rb = sc->sc_rbus_iot; 2137 2138 rbus_space_free(rb, ioh, size, NULL); 2139 #else 2140 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2141 bus_space_free(iot, ioh, size); 2142 else 2143 bus_space_unmap(iot, ioh, size); 2144 #endif 2145 } 2146 2147 /* 2148 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2149 * bus_addr_t offset, bus_size_t size, 2150 * struct pcmcia_io_handle *pcihp, 2151 * int *windowp) 2152 * 2153 * This function maps the allocated I/O region to pccard. This function 2154 * never allocates any I/O region for pccard I/O area. I don't 2155 * understand why the original authors of pcmciabus separated alloc and 2156 * map. I believe the two must be unite. 2157 * 2158 * XXX: no wait timing control? 2159 */ 2160 int 2161 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2162 pcmcia_chipset_handle_t pch; 2163 int width; 2164 bus_addr_t offset; 2165 bus_size_t size; 2166 struct pcmcia_io_handle *pcihp; 2167 int *windowp; 2168 { 2169 struct pcic_handle *ph = (struct pcic_handle *)pch; 2170 bus_addr_t ioaddr = pcihp->addr + offset; 2171 int i, win; 2172 #if defined CBB_DEBUG 2173 static char *width_names[] = { "dynamic", "io8", "io16" }; 2174 #endif 2175 2176 /* Sanity check I/O handle. */ 2177 2178 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2179 panic("pccbb_pcmcia_io_map iot is bogus"); 2180 } 2181 2182 /* XXX Sanity check offset/size. */ 2183 2184 win = -1; 2185 for (i = 0; i < PCIC_IO_WINS; i++) { 2186 if ((ph->ioalloc & (1 << i)) == 0) { 2187 win = i; 2188 ph->ioalloc |= (1 << i); 2189 break; 2190 } 2191 } 2192 2193 if (win == -1) { 2194 return 1; 2195 } 2196 2197 *windowp = win; 2198 2199 /* XXX this is pretty gross */ 2200 2201 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2202 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2203 2204 /* XXX wtf is this doing here? */ 2205 2206 #if 0 2207 printf(" port 0x%lx", (u_long) ioaddr); 2208 if (size > 1) { 2209 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2210 } 2211 #endif 2212 2213 ph->io[win].addr = ioaddr; 2214 ph->io[win].size = size; 2215 ph->io[win].width = width; 2216 2217 /* actual dirty register-value changing in the function below. */ 2218 pccbb_pcmcia_do_io_map(ph, win); 2219 2220 return 0; 2221 } 2222 2223 /* 2224 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2225 * 2226 * This function changes register-value to map I/O region for pccard. 2227 */ 2228 static void 2229 pccbb_pcmcia_do_io_map(ph, win) 2230 struct pcic_handle *ph; 2231 int win; 2232 { 2233 static u_int8_t pcic_iowidth[3] = { 2234 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2235 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2236 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2237 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2238 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2239 }; 2240 2241 #define PCIC_SIA_START_LOW 0 2242 #define PCIC_SIA_START_HIGH 1 2243 #define PCIC_SIA_STOP_LOW 2 2244 #define PCIC_SIA_STOP_HIGH 3 2245 2246 int regbase_win = 0x8 + win * 0x04; 2247 u_int8_t ioctl, enable; 2248 2249 DPRINTF( 2250 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2251 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2252 ph->io[win].width * 8)); 2253 2254 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2255 ph->io[win].addr & 0xff); 2256 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2257 (ph->io[win].addr >> 8) & 0xff); 2258 2259 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2260 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2261 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2262 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2263 2264 ioctl = Pcic_read(ph, PCIC_IOCTL); 2265 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2266 switch (win) { 2267 case 0: 2268 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2269 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2270 PCIC_IOCTL_IO0_DATASIZE_MASK); 2271 ioctl |= pcic_iowidth[ph->io[win].width]; 2272 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2273 break; 2274 case 1: 2275 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2276 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2277 PCIC_IOCTL_IO1_DATASIZE_MASK); 2278 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2279 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2280 break; 2281 } 2282 Pcic_write(ph, PCIC_IOCTL, ioctl); 2283 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2284 #if defined CBB_DEBUG 2285 { 2286 u_int8_t start_low = 2287 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2288 u_int8_t start_high = 2289 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2290 u_int8_t stop_low = 2291 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2292 u_int8_t stop_high = 2293 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2294 printf 2295 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2296 start_low, start_high, stop_low, stop_high, ioctl, enable); 2297 } 2298 #endif 2299 } 2300 2301 /* 2302 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2303 * 2304 * This function unmaps I/O region. No return value. 2305 */ 2306 STATIC void 2307 pccbb_pcmcia_io_unmap(pch, win) 2308 pcmcia_chipset_handle_t pch; 2309 int win; 2310 { 2311 struct pcic_handle *ph = (struct pcic_handle *)pch; 2312 int reg; 2313 2314 if (win >= PCIC_IO_WINS || win < 0) { 2315 panic("pccbb_pcmcia_io_unmap: window out of range"); 2316 } 2317 2318 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2319 switch (win) { 2320 case 0: 2321 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2322 break; 2323 case 1: 2324 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2325 break; 2326 } 2327 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2328 2329 ph->ioalloc &= ~(1 << win); 2330 } 2331 2332 /* 2333 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2334 * 2335 * This function enables the card. All information is stored in 2336 * the first argument, pcmcia_chipset_handle_t. 2337 */ 2338 static int 2339 pccbb_pcmcia_wait_ready(ph) 2340 struct pcic_handle *ph; 2341 { 2342 u_char stat; 2343 int i; 2344 2345 DPRINTF(("entering pccbb_pcmcia_wait_ready: status 0x%02x\n", 2346 Pcic_read(ph, PCIC_IF_STATUS))); 2347 2348 for (i = 0; i < 2000; i++) { 2349 stat = Pcic_read(ph, PCIC_IF_STATUS); 2350 if (stat & PCIC_IF_STATUS_READY) 2351 return 1; 2352 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2353 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2354 return 0; 2355 DELAY_MS(2, ph->ph_parent); 2356 #ifdef CBB_DEBUG 2357 if ((i > 1000) && (i % 25 == 24)) 2358 printf("."); 2359 #endif 2360 } 2361 2362 #ifdef DIAGNOSTIC 2363 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2364 Pcic_read(ph, PCIC_IF_STATUS)); 2365 #endif 2366 2367 return 0; 2368 } 2369 2370 /* 2371 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2372 * 2373 * This function enables the card. All information is stored in 2374 * the first argument, pcmcia_chipset_handle_t. 2375 */ 2376 STATIC void 2377 pccbb_pcmcia_socket_enable(pch) 2378 pcmcia_chipset_handle_t pch; 2379 { 2380 struct pcic_handle *ph = (struct pcic_handle *)pch; 2381 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2382 int cardtype, win; 2383 u_int8_t power, intr; 2384 pcireg_t spsr; 2385 int voltage; 2386 2387 /* this bit is mostly stolen from pcic_attach_card */ 2388 2389 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2390 2391 /* get card Vcc info */ 2392 2393 spsr = 2394 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2395 CB_SOCKET_STAT); 2396 if (spsr & CB_SOCKET_STAT_5VCARD) { 2397 DPRINTF(("5V card\n")); 2398 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2399 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2400 DPRINTF(("3V card\n")); 2401 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2402 } else { 2403 printf("?V card, 0x%x\n", spsr); /* XXX */ 2404 return; 2405 } 2406 2407 /* disable socket: negate output enable bit and power off */ 2408 2409 power = 0; 2410 Pcic_write(ph, PCIC_PWRCTL, power); 2411 2412 /* power down the socket to reset it, clear the card reset pin */ 2413 2414 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2415 2416 /* 2417 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2418 * we are changing Vcc (Toff). 2419 */ 2420 /* delay(300*1000); too much */ 2421 2422 /* assert reset bit */ 2423 intr = Pcic_read(ph, PCIC_INTR); 2424 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2425 Pcic_write(ph, PCIC_INTR, intr); 2426 2427 /* power up the socket */ 2428 power = Pcic_read(ph, PCIC_PWRCTL); 2429 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 2430 pccbb_power(sc, voltage); 2431 2432 /* now output enable */ 2433 power = Pcic_read(ph, PCIC_PWRCTL); 2434 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2435 2436 if (pccbb_power(sc, voltage) == 0) { 2437 power &= PCIC_PWRCTL_OE; 2438 Pcic_write(ph, PCIC_PWRCTL, power); 2439 intr |= PCIC_INTR_RESET; 2440 Pcic_write(ph, PCIC_INTR, intr); 2441 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2442 return; 2443 } 2444 2445 /* 2446 * hold RESET at least 20 ms: the spec says only 10 us is 2447 * enough, but TI1130 requires at least 20 ms. 2448 */ 2449 #if 0 /* XXX called on interrupt context */ 2450 DELAY_MS(20, sc); 2451 #else 2452 delay(20 * 1000); 2453 #endif 2454 2455 /* clear the reset flag */ 2456 2457 intr |= PCIC_INTR_RESET; 2458 Pcic_write(ph, PCIC_INTR, intr); 2459 2460 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2461 2462 #if 0 /* XXX called on interrupt context */ 2463 DELAY_MS(20, sc); 2464 #else 2465 delay(20 * 1000); 2466 #endif 2467 2468 /* wait for the chip to finish initializing */ 2469 2470 if (pccbb_pcmcia_wait_ready(ph) == 0) { 2471 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2472 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2473 return; 2474 } 2475 2476 /* zero out the address windows */ 2477 2478 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2479 2480 /* set the card type */ 2481 2482 cardtype = pcmcia_card_gettype(ph->pcmcia); 2483 2484 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2485 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2486 Pcic_write(ph, PCIC_INTR, intr); 2487 2488 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2489 ph->ph_parent->dv_xname, ph->sock, 2490 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2491 2492 /* reinstall all the memory and io mappings */ 2493 2494 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2495 if (ph->memalloc & (1 << win)) { 2496 pccbb_pcmcia_do_mem_map(ph, win); 2497 } 2498 } 2499 2500 for (win = 0; win < PCIC_IO_WINS; ++win) { 2501 if (ph->ioalloc & (1 << win)) { 2502 pccbb_pcmcia_do_io_map(ph, win); 2503 } 2504 } 2505 } 2506 2507 /* 2508 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2509 * 2510 * This function disables the card. All information is stored in 2511 * the first argument, pcmcia_chipset_handle_t. 2512 */ 2513 STATIC void 2514 pccbb_pcmcia_socket_disable(pch) 2515 pcmcia_chipset_handle_t pch; 2516 { 2517 struct pcic_handle *ph = (struct pcic_handle *)pch; 2518 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2519 u_int8_t power, intr; 2520 2521 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2522 2523 /* reset signal asserting... */ 2524 2525 intr = Pcic_read(ph, PCIC_INTR); 2526 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2527 Pcic_write(ph, PCIC_INTR, intr); 2528 delay(2 * 1000); 2529 2530 /* power down the socket */ 2531 power = Pcic_read(ph, PCIC_PWRCTL); 2532 power &= ~PCIC_PWRCTL_OE; 2533 Pcic_write(ph, PCIC_PWRCTL, power); 2534 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2535 /* 2536 * wait 300ms until power fails (Tpf). 2537 */ 2538 #if 0 /* XXX called on interrupt context */ 2539 DELAY_MS(300, sc); 2540 #else 2541 delay(300 * 1000); 2542 #endif 2543 } 2544 2545 /* 2546 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2547 * 2548 * This function detects whether a card is in the slot or not. 2549 * If a card is inserted, return 1. Otherwise, return 0. 2550 */ 2551 STATIC int 2552 pccbb_pcmcia_card_detect(pch) 2553 pcmcia_chipset_handle_t pch; 2554 { 2555 struct pcic_handle *ph = (struct pcic_handle *)pch; 2556 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2557 2558 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2559 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2560 } 2561 2562 #if 0 2563 STATIC int 2564 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2565 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2566 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2567 #endif 2568 /* 2569 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2570 * bus_size_t size, 2571 * struct pcmcia_mem_handle *pcmhp) 2572 * 2573 * This function only allocates memory region for pccard. This 2574 * function never maps the allocated region to pccard memory area. 2575 * 2576 * XXX: Why the argument of start address is not in? 2577 */ 2578 STATIC int 2579 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2580 pcmcia_chipset_handle_t pch; 2581 bus_size_t size; 2582 struct pcmcia_mem_handle *pcmhp; 2583 { 2584 struct pcic_handle *ph = (struct pcic_handle *)pch; 2585 bus_space_handle_t memh; 2586 bus_addr_t addr; 2587 bus_size_t sizepg; 2588 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2589 #if rbus 2590 rbus_tag_t rb; 2591 #endif 2592 2593 /* Check that the card is still there. */ 2594 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2595 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2596 return 1; 2597 2598 /* out of sc->memh, allocate as many pages as necessary */ 2599 2600 /* convert size to PCIC pages */ 2601 /* 2602 * This is not enough; when the requested region is on the page 2603 * boundaries, this may calculate wrong result. 2604 */ 2605 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2606 #if 0 2607 if (sizepg > PCIC_MAX_MEM_PAGES) { 2608 return 1; 2609 } 2610 #endif 2611 2612 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2613 return 1; 2614 } 2615 2616 addr = 0; /* XXX gcc -Wuninitialized */ 2617 2618 #if rbus 2619 rb = sc->sc_rbus_memt; 2620 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2621 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2622 &addr, &memh)) { 2623 return 1; 2624 } 2625 #else 2626 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2627 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2628 0, /* boundary */ 2629 0, /* flags */ 2630 &addr, &memh)) { 2631 return 1; 2632 } 2633 #endif 2634 2635 DPRINTF( 2636 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2637 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2638 2639 pcmhp->memt = sc->sc_memt; 2640 pcmhp->memh = memh; 2641 pcmhp->addr = addr; 2642 pcmhp->size = size; 2643 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2644 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2645 pcmhp->mhandle = 0; 2646 /* No offset??? Funny. */ 2647 2648 return 0; 2649 } 2650 2651 /* 2652 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2653 * struct pcmcia_mem_handle *pcmhp) 2654 * 2655 * This function release the memory space allocated by the function 2656 * pccbb_pcmcia_mem_alloc(). 2657 */ 2658 STATIC void 2659 pccbb_pcmcia_mem_free(pch, pcmhp) 2660 pcmcia_chipset_handle_t pch; 2661 struct pcmcia_mem_handle *pcmhp; 2662 { 2663 #if rbus 2664 struct pcic_handle *ph = (struct pcic_handle *)pch; 2665 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2666 2667 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2668 #else 2669 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2670 #endif 2671 } 2672 2673 /* 2674 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2675 * 2676 * This function release the memory space allocated by the function 2677 * pccbb_pcmcia_mem_alloc(). 2678 */ 2679 STATIC void 2680 pccbb_pcmcia_do_mem_map(ph, win) 2681 struct pcic_handle *ph; 2682 int win; 2683 { 2684 int regbase_win; 2685 bus_addr_t phys_addr; 2686 bus_addr_t phys_end; 2687 2688 #define PCIC_SMM_START_LOW 0 2689 #define PCIC_SMM_START_HIGH 1 2690 #define PCIC_SMM_STOP_LOW 2 2691 #define PCIC_SMM_STOP_HIGH 3 2692 #define PCIC_CMA_LOW 4 2693 #define PCIC_CMA_HIGH 5 2694 2695 u_int8_t start_low, start_high = 0; 2696 u_int8_t stop_low, stop_high; 2697 u_int8_t off_low, off_high; 2698 u_int8_t mem_window; 2699 int reg; 2700 2701 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2702 int mem8 = 2703 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2704 || (kind == PCMCIA_MEM_ATTR); 2705 2706 regbase_win = 0x10 + win * 0x08; 2707 2708 phys_addr = ph->mem[win].addr; 2709 phys_end = phys_addr + ph->mem[win].size; 2710 2711 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2712 phys_addr, phys_end, ph->mem[win].offset)); 2713 2714 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2715 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2716 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2717 2718 /* bit 19:12 */ 2719 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2720 /* bit 23:20 and bit 7 on */ 2721 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2722 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2723 /* bit 31:24, for 32-bit address */ 2724 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2725 2726 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2727 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2728 2729 if (((struct pccbb_softc *)ph-> 2730 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2731 Pcic_write(ph, 0x40 + win, mem_window); 2732 } 2733 2734 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2735 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2736 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2737 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2738 2739 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2740 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2741 2742 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2743 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2744 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2745 | ((kind == PCMCIA_MEM_ATTR) ? 2746 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2747 2748 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2749 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2750 2751 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2752 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2753 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2754 2755 #if defined CBB_DEBUG 2756 { 2757 int r1, r2, r3, r4, r5, r6, r7 = 0; 2758 2759 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2760 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2761 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2762 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2763 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2764 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2765 if (((struct pccbb_softc *)(ph-> 2766 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2767 r7 = Pcic_read(ph, 0x40 + win); 2768 } 2769 2770 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2771 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2772 if (((struct pccbb_softc *)(ph-> 2773 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2774 DPRINTF((" %02x", r7)); 2775 } 2776 DPRINTF(("\n")); 2777 } 2778 #endif 2779 } 2780 2781 /* 2782 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2783 * bus_addr_t card_addr, bus_size_t size, 2784 * struct pcmcia_mem_handle *pcmhp, 2785 * bus_addr_t *offsetp, int *windowp) 2786 * 2787 * This function maps memory space allocated by the function 2788 * pccbb_pcmcia_mem_alloc(). 2789 */ 2790 STATIC int 2791 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2792 pcmcia_chipset_handle_t pch; 2793 int kind; 2794 bus_addr_t card_addr; 2795 bus_size_t size; 2796 struct pcmcia_mem_handle *pcmhp; 2797 bus_addr_t *offsetp; 2798 int *windowp; 2799 { 2800 struct pcic_handle *ph = (struct pcic_handle *)pch; 2801 bus_addr_t busaddr; 2802 long card_offset; 2803 int win; 2804 2805 /* Check that the card is still there. */ 2806 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2807 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2808 return 1; 2809 2810 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2811 if ((ph->memalloc & (1 << win)) == 0) { 2812 ph->memalloc |= (1 << win); 2813 break; 2814 } 2815 } 2816 2817 if (win == PCIC_MEM_WINS) { 2818 return 1; 2819 } 2820 2821 *windowp = win; 2822 2823 /* XXX this is pretty gross */ 2824 2825 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2826 panic("pccbb_pcmcia_mem_map memt is bogus"); 2827 } 2828 2829 busaddr = pcmhp->addr; 2830 2831 /* 2832 * compute the address offset to the pcmcia address space for the 2833 * pcic. this is intentionally signed. The masks and shifts below 2834 * will cause TRT to happen in the pcic registers. Deal with making 2835 * sure the address is aligned, and return the alignment offset. 2836 */ 2837 2838 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2839 card_addr -= *offsetp; 2840 2841 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2842 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2843 (u_long) card_addr)); 2844 2845 /* 2846 * include the offset in the size, and decrement size by one, since 2847 * the hw wants start/stop 2848 */ 2849 size += *offsetp - 1; 2850 2851 card_offset = (((long)card_addr) - ((long)busaddr)); 2852 2853 ph->mem[win].addr = busaddr; 2854 ph->mem[win].size = size; 2855 ph->mem[win].offset = card_offset; 2856 ph->mem[win].kind = kind; 2857 2858 pccbb_pcmcia_do_mem_map(ph, win); 2859 2860 return 0; 2861 } 2862 2863 /* 2864 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2865 * int window) 2866 * 2867 * This function unmaps memory space which mapped by the function 2868 * pccbb_pcmcia_mem_map(). 2869 */ 2870 STATIC void 2871 pccbb_pcmcia_mem_unmap(pch, window) 2872 pcmcia_chipset_handle_t pch; 2873 int window; 2874 { 2875 struct pcic_handle *ph = (struct pcic_handle *)pch; 2876 int reg; 2877 2878 if (window >= PCIC_MEM_WINS) { 2879 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2880 } 2881 2882 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2883 reg &= ~(1 << window); 2884 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2885 2886 ph->memalloc &= ~(1 << window); 2887 } 2888 2889 #if defined PCCBB_PCMCIA_POLL 2890 struct pccbb_poll_str { 2891 void *arg; 2892 int (*func) __P((void *)); 2893 int level; 2894 struct pcic_handle *ph; 2895 int count; 2896 int num; 2897 struct callout poll_ch; 2898 }; 2899 2900 static struct pccbb_poll_str pccbb_poll[10]; 2901 static int pccbb_poll_n = 0; 2902 2903 static void pccbb_pcmcia_poll __P((void *arg)); 2904 2905 static void 2906 pccbb_pcmcia_poll(arg) 2907 void *arg; 2908 { 2909 struct pccbb_poll_str *poll = arg; 2910 struct pcic_handle *ph = poll->ph; 2911 struct pccbb_softc *sc = ph->sc; 2912 int s; 2913 u_int32_t spsr; /* socket present-state reg */ 2914 2915 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2916 switch (poll->level) { 2917 case IPL_NET: 2918 s = splnet(); 2919 break; 2920 case IPL_BIO: 2921 s = splbio(); 2922 break; 2923 case IPL_TTY: /* fallthrough */ 2924 default: 2925 s = spltty(); 2926 break; 2927 } 2928 2929 spsr = 2930 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2931 CB_SOCKET_STAT); 2932 2933 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2934 if (!(spsr & 0x40)) /* CINT low */ 2935 #else 2936 if (1) 2937 #endif 2938 { 2939 if ((*poll->func) (poll->arg) > 0) { 2940 ++poll->count; 2941 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2942 #if defined LEVEL2 2943 } else { 2944 printf("intr: miss! 0x%x\n", spsr); 2945 #endif 2946 } 2947 } 2948 splx(s); 2949 } 2950 #endif /* defined CB_PCMCIA_POLL */ 2951 2952 /* 2953 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2954 * struct pcmcia_function *pf, 2955 * int ipl, 2956 * int (*func)(void *), 2957 * void *arg); 2958 * 2959 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2960 */ 2961 STATIC void * 2962 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2963 pcmcia_chipset_handle_t pch; 2964 struct pcmcia_function *pf; 2965 int ipl; 2966 int (*func) __P((void *)); 2967 void *arg; 2968 { 2969 struct pcic_handle *ph = (struct pcic_handle *)pch; 2970 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2971 2972 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2973 /* what should I do? */ 2974 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2975 DPRINTF( 2976 ("%s does not provide edge nor pulse interrupt\n", 2977 sc->sc_dev.dv_xname)); 2978 return NULL; 2979 } 2980 /* 2981 * XXX Noooooo! The interrupt flag must set properly!! 2982 * dumb pcmcia driver!! 2983 */ 2984 } 2985 2986 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2987 } 2988 2989 /* 2990 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2991 * void *ih) 2992 * 2993 * This function disables PC-Card interrupt. 2994 */ 2995 STATIC void 2996 pccbb_pcmcia_intr_disestablish(pch, ih) 2997 pcmcia_chipset_handle_t pch; 2998 void *ih; 2999 { 3000 struct pcic_handle *ph = (struct pcic_handle *)pch; 3001 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3002 3003 pccbb_intr_disestablish(sc, ih); 3004 } 3005 3006 #if rbus 3007 /* 3008 * static int 3009 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3010 * bus_addr_t addr, bus_size_t size, 3011 * bus_addr_t mask, bus_size_t align, 3012 * int flags, bus_addr_t *addrp; 3013 * bus_space_handle_t *bshp) 3014 * 3015 * This function allocates a portion of memory or io space for 3016 * clients. This function is called from CardBus card drivers. 3017 */ 3018 static int 3019 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3020 cardbus_chipset_tag_t ct; 3021 rbus_tag_t rb; 3022 bus_addr_t addr; 3023 bus_size_t size; 3024 bus_addr_t mask; 3025 bus_size_t align; 3026 int flags; 3027 bus_addr_t *addrp; 3028 bus_space_handle_t *bshp; 3029 { 3030 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3031 3032 DPRINTF( 3033 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 3034 addr, size, mask, align)); 3035 3036 if (align == 0) { 3037 align = size; 3038 } 3039 3040 if (rb->rb_bt == sc->sc_memt) { 3041 if (align < 16) { 3042 return 1; 3043 } 3044 /* 3045 * XXX: align more than 0x1000 to avoid overwrapping 3046 * memory windows for two or more devices. 0x1000 3047 * means memory window's granularity. 3048 * 3049 * Two or more devices should be able to share same 3050 * memory window region. However, overrapping memory 3051 * window is not good because some devices, such as 3052 * 3Com 3C575[BC], have a broken address decoder and 3053 * intrude other's memory region. 3054 */ 3055 if (align < 0x1000) { 3056 align = 0x1000; 3057 } 3058 } else if (rb->rb_bt == sc->sc_iot) { 3059 if (align < 4) { 3060 return 1; 3061 } 3062 /* XXX: hack for avoiding ISA image */ 3063 if (mask < 0x0100) { 3064 mask = 0x3ff; 3065 addr = 0x300; 3066 } 3067 3068 } else { 3069 DPRINTF( 3070 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used. io: %d, mem: %d\n", 3071 rb->rb_bt, sc->sc_iot, sc->sc_memt)); 3072 return 1; 3073 /* XXX: panic here? */ 3074 } 3075 3076 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3077 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3078 return 1; 3079 } 3080 3081 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3082 3083 return 0; 3084 } 3085 3086 /* 3087 * static int 3088 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3089 * bus_space_handle_t *bshp, bus_size_t size); 3090 * 3091 * This function is called from CardBus card drivers. 3092 */ 3093 static int 3094 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3095 cardbus_chipset_tag_t ct; 3096 rbus_tag_t rb; 3097 bus_space_handle_t bsh; 3098 bus_size_t size; 3099 { 3100 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3101 bus_space_tag_t bt = rb->rb_bt; 3102 3103 pccbb_close_win(sc, bt, bsh, size); 3104 3105 if (bt == sc->sc_memt) { 3106 } else if (bt == sc->sc_iot) { 3107 } else { 3108 return 1; 3109 /* XXX: panic here? */ 3110 } 3111 3112 return rbus_space_free(rb, bsh, size, NULL); 3113 } 3114 #endif /* rbus */ 3115 3116 #if rbus 3117 3118 static int 3119 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3120 struct pccbb_softc *sc; 3121 bus_space_tag_t bst; 3122 bus_addr_t addr; 3123 bus_size_t size; 3124 bus_space_handle_t bsh; 3125 int flags; 3126 { 3127 struct pccbb_win_chain_head *head; 3128 bus_addr_t align; 3129 3130 head = &sc->sc_iowindow; 3131 align = 0x04; 3132 if (sc->sc_memt == bst) { 3133 head = &sc->sc_memwindow; 3134 align = 0x1000; 3135 DPRINTF(("using memory window, %x %x %x\n\n", 3136 sc->sc_iot, sc->sc_memt, bst)); 3137 } 3138 3139 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3140 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3141 sc->sc_dev.dv_xname, 3142 (head == &sc->sc_memwindow) ? "mem" : "io"); 3143 } 3144 pccbb_winset(align, sc, bst); 3145 3146 return 0; 3147 } 3148 3149 static int 3150 pccbb_close_win(sc, bst, bsh, size) 3151 struct pccbb_softc *sc; 3152 bus_space_tag_t bst; 3153 bus_space_handle_t bsh; 3154 bus_size_t size; 3155 { 3156 struct pccbb_win_chain_head *head; 3157 bus_addr_t align; 3158 3159 head = &sc->sc_iowindow; 3160 align = 0x04; 3161 if (sc->sc_memt == bst) { 3162 head = &sc->sc_memwindow; 3163 align = 0x1000; 3164 } 3165 3166 if (pccbb_winlist_delete(head, bsh, size)) { 3167 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3168 sc->sc_dev.dv_xname, 3169 (head == &sc->sc_memwindow) ? "mem" : "io"); 3170 } 3171 pccbb_winset(align, sc, bst); 3172 3173 return 0; 3174 } 3175 3176 static int 3177 pccbb_winlist_insert(head, start, size, bsh, flags) 3178 struct pccbb_win_chain_head *head; 3179 bus_addr_t start; 3180 bus_size_t size; 3181 bus_space_handle_t bsh; 3182 int flags; 3183 { 3184 struct pccbb_win_chain *chainp, *elem; 3185 3186 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3187 M_NOWAIT)) == NULL) 3188 return (1); /* fail */ 3189 3190 elem->wc_start = start; 3191 elem->wc_end = start + (size - 1); 3192 elem->wc_handle = bsh; 3193 elem->wc_flags = flags; 3194 3195 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3196 chainp = TAILQ_NEXT(chainp, wc_list)) { 3197 if (chainp->wc_end < start) 3198 continue; 3199 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3200 return (0); 3201 } 3202 3203 TAILQ_INSERT_TAIL(head, elem, wc_list); 3204 return (0); 3205 } 3206 3207 static int 3208 pccbb_winlist_delete(head, bsh, size) 3209 struct pccbb_win_chain_head *head; 3210 bus_space_handle_t bsh; 3211 bus_size_t size; 3212 { 3213 struct pccbb_win_chain *chainp; 3214 3215 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3216 chainp = TAILQ_NEXT(chainp, wc_list)) { 3217 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3218 continue; 3219 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3220 printf("pccbb_winlist_delete: window 0x%lx size " 3221 "inconsistent: 0x%lx, 0x%lx\n", 3222 (unsigned long)chainp->wc_start, 3223 (unsigned long)(chainp->wc_end - chainp->wc_start), 3224 (unsigned long)(size - 1)); 3225 return 1; 3226 } 3227 3228 TAILQ_REMOVE(head, chainp, wc_list); 3229 free(chainp, M_DEVBUF); 3230 3231 return 0; 3232 } 3233 3234 return 1; /* fail: no candidate to remove */ 3235 } 3236 3237 static void 3238 pccbb_winset(align, sc, bst) 3239 bus_addr_t align; 3240 struct pccbb_softc *sc; 3241 bus_space_tag_t bst; 3242 { 3243 pci_chipset_tag_t pc; 3244 pcitag_t tag; 3245 bus_addr_t mask = ~(align - 1); 3246 struct { 3247 cardbusreg_t win_start; 3248 cardbusreg_t win_limit; 3249 int win_flags; 3250 } win[2]; 3251 struct pccbb_win_chain *chainp; 3252 int offs; 3253 3254 win[0].win_start = win[1].win_start = 0xffffffff; 3255 win[0].win_limit = win[1].win_limit = 0; 3256 win[0].win_flags = win[1].win_flags = 0; 3257 3258 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3259 offs = 0x2c; 3260 if (sc->sc_memt == bst) { 3261 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3262 offs = 0x1c; 3263 } 3264 3265 if (chainp != NULL) { 3266 win[0].win_start = chainp->wc_start & mask; 3267 win[0].win_limit = chainp->wc_end & mask; 3268 win[0].win_flags = chainp->wc_flags; 3269 chainp = TAILQ_NEXT(chainp, wc_list); 3270 } 3271 3272 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3273 if (win[1].win_start == 0xffffffff) { 3274 /* window 1 is not used */ 3275 if ((win[0].win_flags == chainp->wc_flags) && 3276 (win[0].win_limit + align >= 3277 (chainp->wc_start & mask))) { 3278 /* concatenate */ 3279 win[0].win_limit = chainp->wc_end & mask; 3280 } else { 3281 /* make new window */ 3282 win[1].win_start = chainp->wc_start & mask; 3283 win[1].win_limit = chainp->wc_end & mask; 3284 win[1].win_flags = chainp->wc_flags; 3285 } 3286 continue; 3287 } 3288 3289 /* Both windows are engaged. */ 3290 if (win[0].win_flags == win[1].win_flags) { 3291 /* same flags */ 3292 if (win[0].win_flags == chainp->wc_flags) { 3293 if (win[1].win_start - (win[0].win_limit + 3294 align) < 3295 (chainp->wc_start & mask) - 3296 ((chainp->wc_end & mask) + align)) { 3297 /* 3298 * merge window 0 and 1, and set win1 3299 * to chainp 3300 */ 3301 win[0].win_limit = win[1].win_limit; 3302 win[1].win_start = 3303 chainp->wc_start & mask; 3304 win[1].win_limit = 3305 chainp->wc_end & mask; 3306 } else { 3307 win[1].win_limit = 3308 chainp->wc_end & mask; 3309 } 3310 } else { 3311 /* different flags */ 3312 3313 /* concatenate win0 and win1 */ 3314 win[0].win_limit = win[1].win_limit; 3315 /* allocate win[1] to new space */ 3316 win[1].win_start = chainp->wc_start & mask; 3317 win[1].win_limit = chainp->wc_end & mask; 3318 win[1].win_flags = chainp->wc_flags; 3319 } 3320 } else { 3321 /* the flags of win[0] and win[1] is different */ 3322 if (win[0].win_flags == chainp->wc_flags) { 3323 win[0].win_limit = chainp->wc_end & mask; 3324 /* 3325 * XXX this creates overlapping windows, so 3326 * what should the poor bridge do if one is 3327 * cachable, and the other is not? 3328 */ 3329 printf("%s: overlapping windows\n", 3330 sc->sc_dev.dv_xname); 3331 } else { 3332 win[1].win_limit = chainp->wc_end & mask; 3333 } 3334 } 3335 } 3336 3337 pc = sc->sc_pc; 3338 tag = sc->sc_tag; 3339 pci_conf_write(pc, tag, offs, win[0].win_start); 3340 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3341 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3342 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3343 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3344 pci_conf_read(pc, tag, offs), 3345 pci_conf_read(pc, tag, offs + 4) + align, 3346 pci_conf_read(pc, tag, offs + 8), 3347 pci_conf_read(pc, tag, offs + 12) + align)); 3348 3349 if (bst == sc->sc_memt) { 3350 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3351 3352 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3353 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3354 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3355 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3356 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3357 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3358 } 3359 } 3360 3361 #endif /* rbus */ 3362 3363 static void 3364 pccbb_powerhook(why, arg) 3365 int why; 3366 void *arg; 3367 { 3368 struct pccbb_softc *sc = arg; 3369 pcireg_t reg; 3370 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3371 bus_space_handle_t base_memh = sc->sc_base_memh; 3372 3373 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3374 3375 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3376 DPRINTF(("%s: power: why %d stopping intr\n", sc->sc_dev.dv_xname, why)); 3377 if (sc->sc_pil_intr_enable) { 3378 (void)pccbbintr_function(sc); 3379 } 3380 sc->sc_pil_intr_enable = 0; 3381 3382 /* ToDo: deactivate or suspend child devices */ 3383 3384 } 3385 3386 if (why == PWR_RESUME) { 3387 if (sc->sc_pwrmgt_offs != 0) { 3388 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3389 sc->sc_pwrmgt_offs + 4); 3390 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3391 reg & 0x100) { 3392 /* powrstate != D0 */ 3393 3394 printf("%s going back to D0 mode\n", 3395 sc->sc_dev.dv_xname); 3396 reg &= ~PCI_PMCSR_STATE_MASK; 3397 reg |= PCI_PMCSR_STATE_D0; 3398 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3399 pci_conf_write(sc->sc_pc, sc->sc_tag, 3400 sc->sc_pwrmgt_offs + 4, reg); 3401 3402 pci_conf_write(sc->sc_pc, sc->sc_tag, 3403 PCI_SOCKBASE, sc->sc_sockbase); 3404 pci_conf_write(sc->sc_pc, sc->sc_tag, 3405 PCI_BUSNUM, sc->sc_busnum); 3406 pccbb_chipinit(sc); 3407 /* setup memory and io space window for CB */ 3408 pccbb_winset(0x1000, sc, sc->sc_memt); 3409 pccbb_winset(0x04, sc, sc->sc_iot); 3410 } 3411 } 3412 3413 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3414 /* BIOS did not recover this register */ 3415 pci_conf_write (sc->sc_pc, sc->sc_tag, 3416 PCI_SOCKBASE, sc->sc_sockbase); 3417 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3418 /* BIOS did not recover this register */ 3419 pci_conf_write (sc->sc_pc, sc->sc_tag, 3420 PCI_BUSNUM, sc->sc_busnum); 3421 /* CSC Interrupt: Card detect interrupt on */ 3422 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3423 /* Card detect intr is turned on. */ 3424 reg |= CB_SOCKET_MASK_CD; 3425 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3426 /* reset interrupt */ 3427 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3428 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3429 3430 /* 3431 * check for card insertion or removal during suspend period. 3432 * XXX: the code can't cope with card swap (remove then 3433 * insert). how can we detect such situation? 3434 */ 3435 (void)pccbbintr(sc); 3436 3437 sc->sc_pil_intr_enable = 1; 3438 DPRINTF(("%s: power: RESUME enabling intr\n", sc->sc_dev.dv_xname)); 3439 3440 /* ToDo: activate or wakeup child devices */ 3441 } 3442 } 3443
Indexes created Fri Sep 26 20:09:58 GMT 2025