pccbb.c revision 1.95
1 /* $NetBSD: pccbb.c,v 1.95 2003/12/19 19:00:00 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.95 2003/12/19 19:00:00 christos Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static int pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, NULL, NULL); 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 332 /* Ricoh chips */ 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 346 /* Toshiba products */ 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 348 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 350 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 356 /* Cirrus Logic products */ 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 362 /* sentinel, or Generic chip */ 363 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 364 }; 365 366 static int 367 cb_chipset(pci_id, flagp) 368 u_int32_t pci_id; 369 int *flagp; 370 { 371 const struct yenta_chipinfo *yc; 372 373 /* Loop over except the last default entry. */ 374 for (yc = yc_chipsets; yc < yc_chipsets + 375 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 376 if (pci_id == yc->yc_id) 377 break; 378 379 if (flagp != NULL) 380 *flagp = yc->yc_flags; 381 382 return (yc->yc_chiptype); 383 } 384 385 static void 386 pccbb_shutdown(void *arg) 387 { 388 struct pccbb_softc *sc = arg; 389 pcireg_t command; 390 391 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 392 393 /* 394 * turn off power 395 * 396 * XXX - do not turn off power if chipset is TI 113X because 397 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 398 */ 399 if (sc->sc_chipset != CB_TI113X) { 400 pccbb_power((cardbus_chipset_tag_t)sc, 401 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 402 } 403 404 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 405 0); 406 407 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 408 409 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 410 PCI_COMMAND_MASTER_ENABLE); 411 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 412 413 } 414 415 void 416 pccbbattach(parent, self, aux) 417 struct device *parent; 418 struct device *self; 419 void *aux; 420 { 421 struct pccbb_softc *sc = (void *)self; 422 struct pci_attach_args *pa = aux; 423 pci_chipset_tag_t pc = pa->pa_pc; 424 pcireg_t busreg, reg, sock_base; 425 bus_addr_t sockbase; 426 char devinfo[256]; 427 int flags; 428 int pwrmgt_offs; 429 430 #ifdef __HAVE_PCCBB_ATTACH_HOOK 431 pccbb_attach_hook(parent, self, pa); 432 #endif 433 434 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 435 436 pci_devinfo(pa->pa_id, 0, 0, devinfo); 437 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 438 #ifdef CBB_DEBUG 439 printf(" (chipflags %x)", flags); 440 #endif 441 printf("\n"); 442 443 TAILQ_INIT(&sc->sc_memwindow); 444 TAILQ_INIT(&sc->sc_iowindow); 445 446 #if rbus 447 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 448 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 449 450 #if 0 451 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 452 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 453 #endif 454 #endif /* rbus */ 455 456 sc->sc_flags &= ~CBB_MEMHMAPPED; 457 458 /* power management: set D0 state */ 459 sc->sc_pwrmgt_offs = 0; 460 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 461 &pwrmgt_offs, 0)) { 462 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 463 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 464 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 465 reg &= ~PCI_PMCSR_STATE_MASK; 466 reg |= PCI_PMCSR_STATE_D0; 467 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 468 pci_conf_write(pc, pa->pa_tag, 469 pwrmgt_offs + PCI_PMCSR, reg); 470 } 471 472 sc->sc_pwrmgt_offs = pwrmgt_offs; 473 } 474 475 /* 476 * MAP socket registers and ExCA registers on memory-space 477 * When no valid address is set on socket base registers (on pci 478 * config space), get it not polite way. 479 */ 480 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 481 482 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 483 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 484 /* The address must be valid. */ 485 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 486 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 487 printf("%s: can't map socket base address 0x%lx\n", 488 sc->sc_dev.dv_xname, (unsigned long)sock_base); 489 /* 490 * I think it's funny: socket base registers must be 491 * mapped on memory space, but ... 492 */ 493 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 494 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 495 NULL)) { 496 printf("%s: can't map socket base address" 497 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 498 (unsigned long)sockbase); 499 /* give up... allocate reg space via rbus. */ 500 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 501 } else 502 sc->sc_flags |= CBB_MEMHMAPPED; 503 } else { 504 DPRINTF(("%s: socket base address 0x%lx\n", 505 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 506 sc->sc_flags |= CBB_MEMHMAPPED; 507 } 508 } 509 510 sc->sc_mem_start = 0; /* XXX */ 511 sc->sc_mem_end = 0xffffffff; /* XXX */ 512 513 /* 514 * When interrupt isn't routed correctly, give up probing cbb and do 515 * not kill pcic-compatible port. 516 */ 517 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 518 printf("%s: NOT USED because of unconfigured interrupt\n", 519 sc->sc_dev.dv_xname); 520 return; 521 } 522 523 /* 524 * When bus number isn't set correctly, give up using 32-bit CardBus 525 * mode. 526 */ 527 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 528 #if notyet 529 if (((busreg >> 8) & 0xff) == 0) { 530 printf("%s: CardBus support disabled because of unconfigured bus number\n", 531 sc->sc_dev.dv_xname); 532 flags |= PCCBB_PCMCIA_16BITONLY; 533 } 534 #endif 535 536 /* pccbb_machdep.c end */ 537 538 #if defined CBB_DEBUG 539 { 540 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 541 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 542 intrname[pa->pa_intrpin], pa->pa_intrline); 543 } 544 #endif 545 546 /* setup softc */ 547 sc->sc_pc = pc; 548 sc->sc_iot = pa->pa_iot; 549 sc->sc_memt = pa->pa_memt; 550 sc->sc_dmat = pa->pa_dmat; 551 sc->sc_tag = pa->pa_tag; 552 sc->sc_function = pa->pa_function; 553 sc->sc_sockbase = sock_base; 554 sc->sc_busnum = busreg; 555 556 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 557 558 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 559 560 shutdownhook_establish(pccbb_shutdown, sc); 561 562 /* Disable legacy register mapping. */ 563 switch (sc->sc_chipset) { 564 case CB_RX5C46X: /* fallthrough */ 565 #if 0 566 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 567 case CB_RX5C47X: 568 #endif 569 /* 570 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 571 * cannot be disabled by substituting 0 into PCI_LEGACY 572 * register. Ricoh CardBus bridges have special bits on Bridge 573 * control reg (addr 0x3e on PCI config space). 574 */ 575 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 576 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 577 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 578 break; 579 580 default: 581 /* XXX I don't know proper way to kill legacy I/O. */ 582 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 583 break; 584 } 585 586 config_defer(self, pccbb_pci_callback); 587 } 588 589 590 591 592 /* 593 * static void pccbb_pci_callback(struct device *self) 594 * 595 * The actual attach routine: get memory space for YENTA register 596 * space, setup YENTA register and route interrupt. 597 * 598 * This function should be deferred because this device may obtain 599 * memory space dynamically. This function must avoid obtaining 600 * memory area which has already kept for another device. 601 */ 602 static void 603 pccbb_pci_callback(self) 604 struct device *self; 605 { 606 struct pccbb_softc *sc = (void *)self; 607 pci_chipset_tag_t pc = sc->sc_pc; 608 pci_intr_handle_t ih; 609 const char *intrstr = NULL; 610 bus_addr_t sockbase; 611 struct cbslot_attach_args cba; 612 struct pcmciabus_attach_args paa; 613 struct cardslot_attach_args caa; 614 struct cardslot_softc *csc; 615 616 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 617 /* The socket registers aren't mapped correctly. */ 618 #if rbus 619 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 620 (sc->sc_chipset == CB_RX5C47X 621 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 622 0, &sockbase, &sc->sc_base_memh)) { 623 return; 624 } 625 sc->sc_base_memt = sc->sc_memt; 626 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 627 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 628 sc->sc_dev.dv_xname, (unsigned long)sockbase, 629 (unsigned long)pci_conf_read(pc, sc->sc_tag, 630 PCI_SOCKBASE))); 631 #else 632 sc->sc_base_memt = sc->sc_memt; 633 #if !defined CBB_PCI_BASE 634 #define CBB_PCI_BASE 0x20000000 635 #endif 636 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 637 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 638 /* cannot allocate memory space */ 639 return; 640 } 641 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 642 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 643 sc->sc_dev.dv_xname, (unsigned long)sock_base, 644 (unsigned long)pci_conf_read(pc, 645 sc->sc_tag, PCI_SOCKBASE))); 646 sc->sc_sockbase = sockbase; 647 #endif 648 sc->sc_flags |= CBB_MEMHMAPPED; 649 } 650 651 /* bus bridge initialization */ 652 pccbb_chipinit(sc); 653 654 /* clear data structure for child device interrupt handlers */ 655 LIST_INIT(&sc->sc_pil); 656 sc->sc_pil_intr_enable = 1; 657 658 /* Map and establish the interrupt. */ 659 if (pci_intr_map(&sc->sc_pa, &ih)) { 660 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 661 return; 662 } 663 intrstr = pci_intr_string(pc, ih); 664 665 /* 666 * XXX pccbbintr should be called under the priority lower 667 * than any other hard interrputs. 668 */ 669 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 670 671 if (sc->sc_ih == NULL) { 672 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 673 if (intrstr != NULL) { 674 printf(" at %s", intrstr); 675 } 676 printf("\n"); 677 return; 678 } 679 680 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 681 powerhook_establish(pccbb_powerhook, sc); 682 683 { 684 u_int32_t sockstat; 685 686 sockstat = bus_space_read_4(sc->sc_base_memt, 687 sc->sc_base_memh, CB_SOCKET_STAT); 688 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 689 sc->sc_flags |= CBB_CARDEXIST; 690 } 691 } 692 693 /* 694 * attach cardbus 695 */ 696 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 697 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 698 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 699 700 /* initialize cbslot_attach */ 701 cba.cba_busname = "cardbus"; 702 cba.cba_iot = sc->sc_iot; 703 cba.cba_memt = sc->sc_memt; 704 cba.cba_dmat = sc->sc_dmat; 705 cba.cba_bus = (busreg >> 8) & 0x0ff; 706 cba.cba_cc = (void *)sc; 707 cba.cba_cf = &pccbb_funcs; 708 cba.cba_intrline = sc->sc_pa.pa_intrline; 709 710 #if rbus 711 cba.cba_rbus_iot = sc->sc_rbus_iot; 712 cba.cba_rbus_memt = sc->sc_rbus_memt; 713 #endif 714 715 cba.cba_cacheline = PCI_CACHELINE(bhlc); 716 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 717 718 if (bootverbose) { 719 printf("%s: cacheline 0x%x lattimer 0x%x\n", 720 sc->sc_dev.dv_xname, cba.cba_cacheline, 721 cba.cba_lattimer); 722 printf("%s: bhlc 0x%x lscp 0x%x\n", 723 sc->sc_dev.dv_xname, bhlc, busreg); 724 } 725 #if defined SHOW_REGS 726 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 727 sc->sc_base_memh); 728 #endif 729 } 730 731 pccbb_pcmcia_attach_setup(sc, &paa); 732 caa.caa_cb_attach = NULL; 733 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 734 caa.caa_cb_attach = &cba; 735 } 736 caa.caa_16_attach = &paa; 737 caa.caa_ph = &sc->sc_pcmcia_h; 738 739 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 740 DPRINTF(("pccbbattach: found cardslot\n")); 741 sc->sc_csc = csc; 742 } 743 744 return; 745 } 746 747 748 749 750 751 /* 752 * static void pccbb_chipinit(struct pccbb_softc *sc) 753 * 754 * This function initialize YENTA chip registers listed below: 755 * 1) PCI command reg, 756 * 2) PCI and CardBus latency timer, 757 * 3) route PCI interrupt, 758 * 4) close all memory and io windows. 759 * 5) turn off bus power. 760 * 6) card detect interrupt on. 761 * 7) clear interrupt 762 */ 763 static void 764 pccbb_chipinit(sc) 765 struct pccbb_softc *sc; 766 { 767 pci_chipset_tag_t pc = sc->sc_pc; 768 pcitag_t tag = sc->sc_tag; 769 bus_space_tag_t bmt = sc->sc_base_memt; 770 bus_space_handle_t bmh = sc->sc_base_memh; 771 pcireg_t reg; 772 773 /* 774 * Set PCI command reg. 775 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 776 */ 777 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 778 /* I believe it is harmless. */ 779 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 780 PCI_COMMAND_MASTER_ENABLE); 781 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 782 783 /* 784 * Set CardBus latency timer. 785 */ 786 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 787 if (PCI_CB_LATENCY(reg) < 0x20) { 788 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 789 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 790 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 791 } 792 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 793 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 794 795 /* 796 * Set PCI latency timer. 797 */ 798 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 799 if (PCI_LATTIMER(reg) < 0x10) { 800 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 801 reg |= (0x10 << PCI_LATTIMER_SHIFT); 802 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 803 } 804 DPRINTF(("PCI latency timer 0x%x (%x)\n", 805 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 806 807 808 /* Route functional interrupts to PCI. */ 809 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 810 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 811 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 812 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 813 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 814 815 switch (sc->sc_chipset) { 816 case CB_TI113X: 817 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 818 /* This bit is shared, but may read as 0 on some chips, so set 819 it explicitly on both functions. */ 820 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 821 /* CSC intr enable */ 822 reg |= PCI113X_CBCTRL_PCI_CSC; 823 /* functional intr prohibit | prohibit ISA routing */ 824 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 825 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 826 break; 827 828 case CB_TI12XX: 829 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 830 reg |= PCI12XX_SYSCTRL_VCCPROT; 831 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 832 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 833 reg |= PCI12XX_CBCTRL_CSC; 834 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 835 break; 836 837 case CB_TOPIC95B: 838 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 839 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 840 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 841 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 842 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 843 sc->sc_dev.dv_xname, reg)); 844 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 845 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 846 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 847 DPRINTF(("0x%x\n", reg)); 848 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 849 break; 850 851 case CB_TOPIC97: 852 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 853 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 854 sc->sc_dev.dv_xname, reg)); 855 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 856 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 857 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 858 reg |= TOPIC97_SLOT_CTRL_PCIINT; 859 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 860 DPRINTF(("0x%x\n", reg)); 861 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 862 /* make sure to assert LV card support bits */ 863 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 864 0x800 + 0x3e, 865 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 866 0x800 + 0x3e) | 0x03); 867 break; 868 } 869 870 /* Close all memory and I/O windows. */ 871 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 872 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 873 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 874 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 875 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 876 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 877 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 878 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 879 880 /* reset 16-bit pcmcia bus */ 881 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 882 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 883 884 /* turn off power */ 885 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 886 887 /* CSC Interrupt: Card detect interrupt on */ 888 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 889 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 890 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 891 /* reset interrupt */ 892 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 893 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 894 } 895 896 897 898 899 /* 900 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 901 * struct pcmciabus_attach_args *paa) 902 * 903 * This function attaches 16-bit PCcard bus. 904 */ 905 STATIC void 906 pccbb_pcmcia_attach_setup(sc, paa) 907 struct pccbb_softc *sc; 908 struct pcmciabus_attach_args *paa; 909 { 910 struct pcic_handle *ph = &sc->sc_pcmcia_h; 911 #if rbus 912 rbus_tag_t rb; 913 #endif 914 915 /* initialize pcmcia part in pccbb_softc */ 916 ph->ph_parent = (struct device *)sc; 917 ph->sock = sc->sc_function; 918 ph->flags = 0; 919 ph->shutdown = 0; 920 ph->ih_irq = sc->sc_pa.pa_intrline; 921 ph->ph_bus_t = sc->sc_base_memt; 922 ph->ph_bus_h = sc->sc_base_memh; 923 ph->ph_read = pccbb_pcmcia_read; 924 ph->ph_write = pccbb_pcmcia_write; 925 sc->sc_pct = &pccbb_pcmcia_funcs; 926 927 /* 928 * We need to do a few things here: 929 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 930 * setting the IRQ numbers to 0. 931 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 932 * routing of CSC interrupts (e.g. card removal) to PCI while in 933 * PCMCIA mode. We just leave this set all the time. 934 * 3) Enable card insertion/removal interrupts in case the chip also 935 * needs that while in PCMCIA mode. 936 * 4) Clear any pending CSC interrupt. 937 */ 938 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 939 if (sc->sc_chipset == CB_TI113X) { 940 Pcic_write(ph, PCIC_CSC_INTR, 0); 941 } else { 942 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 943 Pcic_read(ph, PCIC_CSC); 944 } 945 946 /* initialize pcmcia bus attachment */ 947 paa->paa_busname = "pcmcia"; 948 paa->pct = sc->sc_pct; 949 paa->pch = ph; 950 paa->iobase = 0; /* I don't use them */ 951 paa->iosize = 0; 952 #if rbus 953 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 954 paa->iobase = rb->rb_start + rb->rb_offset; 955 paa->iosize = rb->rb_end - rb->rb_start; 956 #endif 957 958 return; 959 } 960 961 #if 0 962 STATIC void 963 pccbb_pcmcia_attach_card(ph) 964 struct pcic_handle *ph; 965 { 966 if (ph->flags & PCIC_FLAG_CARDP) { 967 panic("pccbb_pcmcia_attach_card: already attached"); 968 } 969 970 /* call the MI attach function */ 971 pcmcia_card_attach(ph->pcmcia); 972 973 ph->flags |= PCIC_FLAG_CARDP; 974 } 975 976 STATIC void 977 pccbb_pcmcia_detach_card(ph, flags) 978 struct pcic_handle *ph; 979 int flags; 980 { 981 if (!(ph->flags & PCIC_FLAG_CARDP)) { 982 panic("pccbb_pcmcia_detach_card: already detached"); 983 } 984 985 ph->flags &= ~PCIC_FLAG_CARDP; 986 987 /* call the MI detach function */ 988 pcmcia_card_detach(ph->pcmcia, flags); 989 } 990 #endif 991 992 /* 993 * int pccbbintr(arg) 994 * void *arg; 995 * This routine handles the interrupt from Yenta PCI-CardBus bridge 996 * itself. 997 */ 998 int 999 pccbbintr(arg) 1000 void *arg; 1001 { 1002 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1003 u_int32_t sockevent, sockstate; 1004 bus_space_tag_t memt = sc->sc_base_memt; 1005 bus_space_handle_t memh = sc->sc_base_memh; 1006 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1007 1008 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1009 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1010 Pcic_read(ph, PCIC_CSC); 1011 1012 if (sockevent == 0) { 1013 /* This intr is not for me: it may be for my child devices. */ 1014 if (sc->sc_pil_intr_enable) { 1015 return pccbbintr_function(sc); 1016 } else { 1017 return 0; 1018 } 1019 } 1020 1021 if (sockevent & CB_SOCKET_EVENT_CD) { 1022 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1023 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1024 /* A card should be removed. */ 1025 if (sc->sc_flags & CBB_CARDEXIST) { 1026 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1027 sockevent)); 1028 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1029 sc->sc_flags &= ~CBB_CARDEXIST; 1030 if (sc->sc_csc->sc_status & 1031 CARDSLOT_STATUS_CARD_16) { 1032 #if 0 1033 struct pcic_handle *ph = 1034 &sc->sc_pcmcia_h; 1035 1036 pcmcia_card_deactivate(ph->pcmcia); 1037 pccbb_pcmcia_socket_disable(ph); 1038 pccbb_pcmcia_detach_card(ph, 1039 DETACH_FORCE); 1040 #endif 1041 cardslot_event_throw(sc->sc_csc, 1042 CARDSLOT_EVENT_REMOVAL_16); 1043 } else if (sc->sc_csc->sc_status & 1044 CARDSLOT_STATUS_CARD_CB) { 1045 /* Cardbus intr removed */ 1046 cardslot_event_throw(sc->sc_csc, 1047 CARDSLOT_EVENT_REMOVAL_CB); 1048 } 1049 } else if (sc->sc_flags & CBB_INSERTING) { 1050 sc->sc_flags &= ~CBB_INSERTING; 1051 callout_stop(&sc->sc_insert_ch); 1052 } 1053 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1054 /* 1055 * The pccbbintr may called from powerdown hook when 1056 * the system resumed, to detect the card 1057 * insertion/removal during suspension. 1058 */ 1059 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1060 if (sc->sc_flags & CBB_INSERTING) { 1061 callout_stop(&sc->sc_insert_ch); 1062 } 1063 callout_reset(&sc->sc_insert_ch, hz / 5, 1064 pci113x_insert, sc); 1065 sc->sc_flags |= CBB_INSERTING; 1066 } 1067 } 1068 1069 return (1); 1070 } 1071 1072 /* 1073 * static int pccbbintr_function(struct pccbb_softc *sc) 1074 * 1075 * This function calls each interrupt handler registered at the 1076 * bridge. The interrupt handlers are called in registered order. 1077 */ 1078 static int 1079 pccbbintr_function(sc) 1080 struct pccbb_softc *sc; 1081 { 1082 int retval = 0, val; 1083 struct pccbb_intrhand_list *pil; 1084 int s, splchanged; 1085 1086 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1087 pil = LIST_NEXT(pil, pil_next)) { 1088 /* 1089 * XXX priority change. gross. I use if-else 1090 * sentense instead of switch-case sentense because of 1091 * avoiding duplicate case value error. More than one 1092 * IPL_XXX use same value. It depends on 1093 * implimentation. 1094 */ 1095 splchanged = 1; 1096 if (pil->pil_level == IPL_SERIAL) { 1097 s = splserial(); 1098 } else if (pil->pil_level == IPL_HIGH) { 1099 s = splhigh(); 1100 } else if (pil->pil_level == IPL_CLOCK) { 1101 s = splclock(); 1102 } else if (pil->pil_level == IPL_AUDIO) { 1103 s = splaudio(); 1104 } else if (pil->pil_level == IPL_VM) { 1105 s = splvm(); 1106 } else if (pil->pil_level == IPL_TTY) { 1107 s = spltty(); 1108 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1109 s = splsoftserial(); 1110 } else if (pil->pil_level == IPL_NET) { 1111 s = splnet(); 1112 } else { 1113 s = 0; /* XXX: gcc */ 1114 splchanged = 0; 1115 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1116 } 1117 1118 val = (*pil->pil_func)(pil->pil_arg); 1119 1120 if (splchanged != 0) { 1121 splx(s); 1122 } 1123 1124 retval = retval == 1 ? 1 : 1125 retval == 0 ? val : val != 0 ? val : retval; 1126 } 1127 1128 return retval; 1129 } 1130 1131 static void 1132 pci113x_insert(arg) 1133 void *arg; 1134 { 1135 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1136 u_int32_t sockevent, sockstate; 1137 1138 if (!(sc->sc_flags & CBB_INSERTING)) { 1139 /* We add a card only under inserting state. */ 1140 return; 1141 } 1142 sc->sc_flags &= ~CBB_INSERTING; 1143 1144 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1145 CB_SOCKET_EVENT); 1146 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1147 CB_SOCKET_STAT); 1148 1149 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1150 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1151 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1152 sc->sc_flags |= CBB_CARDEXIST; 1153 /* call pccard interrupt handler here */ 1154 if (sockstate & CB_SOCKET_STAT_16BIT) { 1155 /* 16-bit card found */ 1156 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1157 cardslot_event_throw(sc->sc_csc, 1158 CARDSLOT_EVENT_INSERTION_16); 1159 } else if (sockstate & CB_SOCKET_STAT_CB) { 1160 /* cardbus card found */ 1161 /* cardbus_attach_card(sc->sc_csc); */ 1162 cardslot_event_throw(sc->sc_csc, 1163 CARDSLOT_EVENT_INSERTION_CB); 1164 } else { 1165 /* who are you? */ 1166 } 1167 } else { 1168 callout_reset(&sc->sc_insert_ch, hz / 10, 1169 pci113x_insert, sc); 1170 } 1171 } 1172 1173 #define PCCBB_PCMCIA_OFFSET 0x800 1174 static u_int8_t 1175 pccbb_pcmcia_read(ph, reg) 1176 struct pcic_handle *ph; 1177 int reg; 1178 { 1179 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1180 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1181 1182 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1183 PCCBB_PCMCIA_OFFSET + reg); 1184 } 1185 1186 static void 1187 pccbb_pcmcia_write(ph, reg, val) 1188 struct pcic_handle *ph; 1189 int reg; 1190 u_int8_t val; 1191 { 1192 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1193 val); 1194 1195 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1196 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1197 } 1198 1199 /* 1200 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1201 */ 1202 STATIC int 1203 pccbb_ctrl(ct, command) 1204 cardbus_chipset_tag_t ct; 1205 int command; 1206 { 1207 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1208 1209 switch (command) { 1210 case CARDBUS_CD: 1211 if (2 == pccbb_detect_card(sc)) { 1212 int retval = 0; 1213 int status = cb_detect_voltage(sc); 1214 if (PCCARD_VCC_5V & status) { 1215 retval |= CARDBUS_5V_CARD; 1216 } 1217 if (PCCARD_VCC_3V & status) { 1218 retval |= CARDBUS_3V_CARD; 1219 } 1220 if (PCCARD_VCC_XV & status) { 1221 retval |= CARDBUS_XV_CARD; 1222 } 1223 if (PCCARD_VCC_YV & status) { 1224 retval |= CARDBUS_YV_CARD; 1225 } 1226 return retval; 1227 } else { 1228 return 0; 1229 } 1230 case CARDBUS_RESET: 1231 return cb_reset(sc); 1232 case CARDBUS_IO_ENABLE: /* fallthrough */ 1233 case CARDBUS_IO_DISABLE: /* fallthrough */ 1234 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1235 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1236 case CARDBUS_BM_ENABLE: /* fallthrough */ 1237 case CARDBUS_BM_DISABLE: /* fallthrough */ 1238 /* XXX: I think we don't need to call this function below. */ 1239 return pccbb_cardenable(sc, command); 1240 } 1241 1242 return 0; 1243 } 1244 1245 /* 1246 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1247 * This function returns true when it succeeds and returns false when 1248 * it fails. 1249 */ 1250 STATIC int 1251 pccbb_power(ct, command) 1252 cardbus_chipset_tag_t ct; 1253 int command; 1254 { 1255 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1256 1257 u_int32_t status, sock_ctrl, reg_ctrl; 1258 bus_space_tag_t memt = sc->sc_base_memt; 1259 bus_space_handle_t memh = sc->sc_base_memh; 1260 1261 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1262 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1263 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1264 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1265 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1266 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1267 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1268 "UNKNOWN", 1269 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1270 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1271 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1272 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1273 "UNKNOWN", command)); 1274 1275 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1276 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1277 1278 switch (command & CARDBUS_VCCMASK) { 1279 case CARDBUS_VCC_UC: 1280 break; 1281 case CARDBUS_VCC_5V: 1282 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1283 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1284 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1285 } else { 1286 printf("%s: BAD voltage request: no 5 V card\n", 1287 sc->sc_dev.dv_xname); 1288 return 0; 1289 } 1290 break; 1291 case CARDBUS_VCC_3V: 1292 if (CB_SOCKET_STAT_3VCARD & status) { 1293 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1294 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1295 } else { 1296 printf("%s: BAD voltage request: no 3.3 V card\n", 1297 sc->sc_dev.dv_xname); 1298 return 0; 1299 } 1300 break; 1301 case CARDBUS_VCC_0V: 1302 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1303 break; 1304 default: 1305 return 0; /* power NEVER changed */ 1306 } 1307 1308 switch (command & CARDBUS_VPPMASK) { 1309 case CARDBUS_VPP_UC: 1310 break; 1311 case CARDBUS_VPP_0V: 1312 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1313 break; 1314 case CARDBUS_VPP_VCC: 1315 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1316 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1317 break; 1318 case CARDBUS_VPP_12V: 1319 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1320 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1321 break; 1322 } 1323 1324 #if 0 1325 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1326 #endif 1327 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1328 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1329 1330 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1331 printf 1332 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1333 sc->sc_dev.dv_xname, sock_ctrl, status); 1334 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1335 (command & CARDBUS_VCCMASK) == 1336 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1337 CARDBUS_VCCMASK) == 1338 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1339 CARDBUS_VCCMASK) == 1340 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1341 CARDBUS_VCCMASK) == 1342 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1343 CARDBUS_VCCMASK) == 1344 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1345 CARDBUS_VCCMASK) == 1346 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1347 (command & CARDBUS_VPPMASK) == 1348 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1349 CARDBUS_VPPMASK) == 1350 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1351 CARDBUS_VPPMASK) == 1352 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1353 CARDBUS_VPPMASK) == 1354 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1355 #if 0 1356 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1357 u_int32_t force = 1358 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1359 /* Reset Bad Vcc request */ 1360 force &= ~CB_SOCKET_FORCE_BADVCC; 1361 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1362 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1363 CB_SOCKET_STAT)); 1364 return 1; 1365 } 1366 #endif 1367 return 0; 1368 } 1369 1370 if (sc->sc_chipset == CB_TOPIC97) { 1371 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1372 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1373 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1374 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1375 else 1376 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1377 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1378 } 1379 1380 /* 1381 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1382 * time is 20 ms, some PC-Card bridge requires longer duration. 1383 */ 1384 #if 0 /* XXX called on interrupt context */ 1385 DELAY_MS(300, sc); 1386 #else 1387 delay(300 * 1000); 1388 #endif 1389 1390 return 1; /* power changed correctly */ 1391 } 1392 1393 #if defined CB_PCMCIA_POLL 1394 struct cb_poll_str { 1395 void *arg; 1396 int (*func) __P((void *)); 1397 int level; 1398 pccard_chipset_tag_t ct; 1399 int count; 1400 struct callout poll_ch; 1401 }; 1402 1403 static struct cb_poll_str cb_poll[10]; 1404 static int cb_poll_n = 0; 1405 1406 static void cb_pcmcia_poll __P((void *arg)); 1407 1408 static void 1409 cb_pcmcia_poll(arg) 1410 void *arg; 1411 { 1412 struct cb_poll_str *poll = arg; 1413 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1414 struct pccbb_softc *sc = psc->cpc_parent; 1415 int s; 1416 u_int32_t spsr; /* socket present-state reg */ 1417 1418 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1419 switch (poll->level) { 1420 case IPL_NET: 1421 s = splnet(); 1422 break; 1423 case IPL_BIO: 1424 s = splbio(); 1425 break; 1426 case IPL_TTY: /* fallthrough */ 1427 default: 1428 s = spltty(); 1429 break; 1430 } 1431 1432 spsr = 1433 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1434 CB_SOCKET_STAT); 1435 1436 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1437 if (!(spsr & 0x40)) { /* CINT low */ 1438 #else 1439 if (1) { 1440 #endif 1441 if ((*poll->func) (poll->arg) == 1) { 1442 ++poll->count; 1443 printf("intr: reported from poller, 0x%x\n", spsr); 1444 #if defined LEVEL2 1445 } else { 1446 printf("intr: miss! 0x%x\n", spsr); 1447 #endif 1448 } 1449 } 1450 splx(s); 1451 } 1452 #endif /* defined CB_PCMCIA_POLL */ 1453 1454 /* 1455 * static int pccbb_detect_card(struct pccbb_softc *sc) 1456 * return value: 0 if no card exists. 1457 * 1 if 16-bit card exists. 1458 * 2 if cardbus card exists. 1459 */ 1460 static int 1461 pccbb_detect_card(sc) 1462 struct pccbb_softc *sc; 1463 { 1464 bus_space_handle_t base_memh = sc->sc_base_memh; 1465 bus_space_tag_t base_memt = sc->sc_base_memt; 1466 u_int32_t sockstat = 1467 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1468 int retval = 0; 1469 1470 /* CD1 and CD2 asserted */ 1471 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1472 /* card must be present */ 1473 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1474 /* NOTACARD DEASSERTED */ 1475 if (CB_SOCKET_STAT_CB & sockstat) { 1476 /* CardBus mode */ 1477 retval = 2; 1478 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1479 /* 16-bit mode */ 1480 retval = 1; 1481 } 1482 } 1483 } 1484 return retval; 1485 } 1486 1487 /* 1488 * STATIC int cb_reset(struct pccbb_softc *sc) 1489 * This function resets CardBus card. 1490 */ 1491 STATIC int 1492 cb_reset(sc) 1493 struct pccbb_softc *sc; 1494 { 1495 /* 1496 * Reset Assert at least 20 ms 1497 * Some machines request longer duration. 1498 */ 1499 int reset_duration = 1500 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1501 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1502 1503 /* Reset bit Assert (bit 6 at 0x3E) */ 1504 bcr |= CB_BCR_RESET_ENABLE; 1505 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1506 DELAY_MS(reset_duration, sc); 1507 1508 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1509 /* Reset bit Deassert (bit 6 at 0x3E) */ 1510 bcr &= ~CB_BCR_RESET_ENABLE; 1511 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1512 DELAY_MS(reset_duration, sc); 1513 } 1514 /* No card found on the slot. Keep Reset. */ 1515 return 1; 1516 } 1517 1518 /* 1519 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1520 * This function detect card Voltage. 1521 */ 1522 STATIC int 1523 cb_detect_voltage(sc) 1524 struct pccbb_softc *sc; 1525 { 1526 u_int32_t psr; /* socket present-state reg */ 1527 bus_space_tag_t iot = sc->sc_base_memt; 1528 bus_space_handle_t ioh = sc->sc_base_memh; 1529 int vol = PCCARD_VCC_UKN; /* set 0 */ 1530 1531 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1532 1533 if (0x400u & psr) { 1534 vol |= PCCARD_VCC_5V; 1535 } 1536 if (0x800u & psr) { 1537 vol |= PCCARD_VCC_3V; 1538 } 1539 1540 return vol; 1541 } 1542 1543 STATIC int 1544 cbbprint(aux, pcic) 1545 void *aux; 1546 const char *pcic; 1547 { 1548 /* 1549 struct cbslot_attach_args *cba = aux; 1550 1551 if (cba->cba_slot >= 0) { 1552 aprint_normal(" slot %d", cba->cba_slot); 1553 } 1554 */ 1555 return UNCONF; 1556 } 1557 1558 /* 1559 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1560 * This function enables and disables the card 1561 */ 1562 STATIC int 1563 pccbb_cardenable(sc, function) 1564 struct pccbb_softc *sc; 1565 int function; 1566 { 1567 u_int32_t command = 1568 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1569 1570 DPRINTF(("pccbb_cardenable:")); 1571 switch (function) { 1572 case CARDBUS_IO_ENABLE: 1573 command |= PCI_COMMAND_IO_ENABLE; 1574 break; 1575 case CARDBUS_IO_DISABLE: 1576 command &= ~PCI_COMMAND_IO_ENABLE; 1577 break; 1578 case CARDBUS_MEM_ENABLE: 1579 command |= PCI_COMMAND_MEM_ENABLE; 1580 break; 1581 case CARDBUS_MEM_DISABLE: 1582 command &= ~PCI_COMMAND_MEM_ENABLE; 1583 break; 1584 case CARDBUS_BM_ENABLE: 1585 command |= PCI_COMMAND_MASTER_ENABLE; 1586 break; 1587 case CARDBUS_BM_DISABLE: 1588 command &= ~PCI_COMMAND_MASTER_ENABLE; 1589 break; 1590 default: 1591 return 0; 1592 } 1593 1594 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1595 DPRINTF((" command reg 0x%x\n", command)); 1596 return 1; 1597 } 1598 1599 #if !rbus 1600 /* 1601 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1602 */ 1603 static int 1604 pccbb_io_open(ct, win, start, end) 1605 cardbus_chipset_tag_t ct; 1606 int win; 1607 u_int32_t start, end; 1608 { 1609 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1610 int basereg; 1611 int limitreg; 1612 1613 if ((win < 0) || (win > 2)) { 1614 #if defined DIAGNOSTIC 1615 printf("cardbus_io_open: window out of range %d\n", win); 1616 #endif 1617 return 0; 1618 } 1619 1620 basereg = win * 8 + 0x2c; 1621 limitreg = win * 8 + 0x30; 1622 1623 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1624 start, basereg, end, limitreg)); 1625 1626 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1627 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1628 return 1; 1629 } 1630 1631 /* 1632 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1633 */ 1634 static int 1635 pccbb_io_close(ct, win) 1636 cardbus_chipset_tag_t ct; 1637 int win; 1638 { 1639 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1640 int basereg; 1641 int limitreg; 1642 1643 if ((win < 0) || (win > 2)) { 1644 #if defined DIAGNOSTIC 1645 printf("cardbus_io_close: window out of range %d\n", win); 1646 #endif 1647 return 0; 1648 } 1649 1650 basereg = win * 8 + 0x2c; 1651 limitreg = win * 8 + 0x30; 1652 1653 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1654 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1655 return 1; 1656 } 1657 1658 /* 1659 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1660 */ 1661 static int 1662 pccbb_mem_open(ct, win, start, end) 1663 cardbus_chipset_tag_t ct; 1664 int win; 1665 u_int32_t start, end; 1666 { 1667 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1668 int basereg; 1669 int limitreg; 1670 1671 if ((win < 0) || (win > 2)) { 1672 #if defined DIAGNOSTIC 1673 printf("cardbus_mem_open: window out of range %d\n", win); 1674 #endif 1675 return 0; 1676 } 1677 1678 basereg = win * 8 + 0x1c; 1679 limitreg = win * 8 + 0x20; 1680 1681 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1682 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1683 return 1; 1684 } 1685 1686 /* 1687 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1688 */ 1689 static int 1690 pccbb_mem_close(ct, win) 1691 cardbus_chipset_tag_t ct; 1692 int win; 1693 { 1694 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1695 int basereg; 1696 int limitreg; 1697 1698 if ((win < 0) || (win > 2)) { 1699 #if defined DIAGNOSTIC 1700 printf("cardbus_mem_close: window out of range %d\n", win); 1701 #endif 1702 return 0; 1703 } 1704 1705 basereg = win * 8 + 0x1c; 1706 limitreg = win * 8 + 0x20; 1707 1708 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1709 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1710 return 1; 1711 } 1712 #endif 1713 1714 /* 1715 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1716 * int irq, 1717 * int level, 1718 * int (* func) __P((void *)), 1719 * void *arg) 1720 * 1721 * This function registers an interrupt handler at the bridge, in 1722 * order not to call the interrupt handlers of child devices when 1723 * a card-deletion interrupt occurs. 1724 * 1725 * The arguments irq and level are not used. 1726 */ 1727 static void * 1728 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1729 cardbus_chipset_tag_t ct; 1730 int irq, level; 1731 int (*func) __P((void *)); 1732 void *arg; 1733 { 1734 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1735 1736 return pccbb_intr_establish(sc, irq, level, func, arg); 1737 } 1738 1739 1740 /* 1741 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1742 * void *ih) 1743 * 1744 * This function removes an interrupt handler pointed by ih. 1745 */ 1746 static void 1747 pccbb_cb_intr_disestablish(ct, ih) 1748 cardbus_chipset_tag_t ct; 1749 void *ih; 1750 { 1751 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1752 1753 pccbb_intr_disestablish(sc, ih); 1754 } 1755 1756 1757 void 1758 pccbb_intr_route(sc) 1759 struct pccbb_softc *sc; 1760 { 1761 pcireg_t reg; 1762 1763 /* initialize bridge intr routing */ 1764 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1765 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1766 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1767 1768 switch (sc->sc_chipset) { 1769 case CB_TI113X: 1770 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1771 /* functional intr enabled */ 1772 reg |= PCI113X_CBCTRL_PCI_INTR; 1773 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1774 break; 1775 default: 1776 break; 1777 } 1778 } 1779 1780 /* 1781 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1782 * int irq, 1783 * int level, 1784 * int (* func) __P((void *)), 1785 * void *arg) 1786 * 1787 * This function registers an interrupt handler at the bridge, in 1788 * order not to call the interrupt handlers of child devices when 1789 * a card-deletion interrupt occurs. 1790 * 1791 * The arguments irq is not used because pccbb selects intr vector. 1792 */ 1793 static void * 1794 pccbb_intr_establish(sc, irq, level, func, arg) 1795 struct pccbb_softc *sc; 1796 int irq, level; 1797 int (*func) __P((void *)); 1798 void *arg; 1799 { 1800 struct pccbb_intrhand_list *pil, *newpil; 1801 1802 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1803 1804 if (LIST_EMPTY(&sc->sc_pil)) { 1805 pccbb_intr_route(sc); 1806 } 1807 1808 /* 1809 * Allocate a room for interrupt handler structure. 1810 */ 1811 if (NULL == (newpil = 1812 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1813 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1814 return NULL; 1815 } 1816 1817 newpil->pil_func = func; 1818 newpil->pil_arg = arg; 1819 newpil->pil_level = level; 1820 1821 if (LIST_EMPTY(&sc->sc_pil)) { 1822 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1823 } else { 1824 for (pil = LIST_FIRST(&sc->sc_pil); 1825 LIST_NEXT(pil, pil_next) != NULL; 1826 pil = LIST_NEXT(pil, pil_next)); 1827 LIST_INSERT_AFTER(pil, newpil, pil_next); 1828 } 1829 1830 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1831 LIST_FIRST(&sc->sc_pil))); 1832 1833 return newpil; 1834 } 1835 1836 /* 1837 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1838 * void *ih) 1839 * 1840 * This function removes an interrupt handler pointed by ih. ih 1841 * should be the value returned by cardbus_intr_establish() or 1842 * NULL. 1843 * 1844 * When ih is NULL, this function will do nothing. 1845 */ 1846 static void 1847 pccbb_intr_disestablish(sc, ih) 1848 struct pccbb_softc *sc; 1849 void *ih; 1850 { 1851 struct pccbb_intrhand_list *pil; 1852 pcireg_t reg; 1853 1854 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1855 LIST_FIRST(&sc->sc_pil))); 1856 1857 if (ih == NULL) { 1858 /* intr handler is not set */ 1859 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1860 return; 1861 } 1862 1863 #ifdef DIAGNOSTIC 1864 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1865 pil = LIST_NEXT(pil, pil_next)) { 1866 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1867 if (pil == ih) { 1868 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1869 break; 1870 } 1871 } 1872 if (pil == NULL) { 1873 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1874 sc->sc_dev.dv_xname, ih); 1875 } 1876 #endif 1877 1878 pil = (struct pccbb_intrhand_list *)ih; 1879 LIST_REMOVE(pil, pil_next); 1880 free(pil, M_DEVBUF); 1881 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1882 1883 if (LIST_EMPTY(&sc->sc_pil)) { 1884 /* No interrupt handlers */ 1885 1886 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1887 1888 /* stop routing PCI intr */ 1889 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1890 reg |= CB_BCR_INTR_IREQ_ENABLE; 1891 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1892 1893 switch (sc->sc_chipset) { 1894 case CB_TI113X: 1895 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1896 /* functional intr disabled */ 1897 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1898 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1899 break; 1900 default: 1901 break; 1902 } 1903 } 1904 } 1905 1906 #if defined SHOW_REGS 1907 static void 1908 cb_show_regs(pc, tag, memt, memh) 1909 pci_chipset_tag_t pc; 1910 pcitag_t tag; 1911 bus_space_tag_t memt; 1912 bus_space_handle_t memh; 1913 { 1914 int i; 1915 printf("PCI config regs:"); 1916 for (i = 0; i < 0x50; i += 4) { 1917 if (i % 16 == 0) { 1918 printf("\n 0x%02x:", i); 1919 } 1920 printf(" %08x", pci_conf_read(pc, tag, i)); 1921 } 1922 for (i = 0x80; i < 0xb0; i += 4) { 1923 if (i % 16 == 0) { 1924 printf("\n 0x%02x:", i); 1925 } 1926 printf(" %08x", pci_conf_read(pc, tag, i)); 1927 } 1928 1929 if (memh == 0) { 1930 printf("\n"); 1931 return; 1932 } 1933 1934 printf("\nsocket regs:"); 1935 for (i = 0; i <= 0x10; i += 0x04) { 1936 printf(" %08x", bus_space_read_4(memt, memh, i)); 1937 } 1938 printf("\nExCA regs:"); 1939 for (i = 0; i < 0x08; ++i) { 1940 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1941 } 1942 printf("\n"); 1943 return; 1944 } 1945 #endif 1946 1947 /* 1948 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1949 * int busno, int devno, int function) 1950 * This is the function to make a tag to access config space of 1951 * a CardBus Card. It works same as pci_conf_read. 1952 */ 1953 static cardbustag_t 1954 pccbb_make_tag(cc, busno, devno, function) 1955 cardbus_chipset_tag_t cc; 1956 int busno, devno, function; 1957 { 1958 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1959 1960 return pci_make_tag(sc->sc_pc, busno, devno, function); 1961 } 1962 1963 static void 1964 pccbb_free_tag(cc, tag) 1965 cardbus_chipset_tag_t cc; 1966 cardbustag_t tag; 1967 { 1968 } 1969 1970 /* 1971 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1972 * cardbustag_t tag, int offset) 1973 * This is the function to read the config space of a CardBus Card. 1974 * It works same as pci_conf_read. 1975 */ 1976 static cardbusreg_t 1977 pccbb_conf_read(cc, tag, offset) 1978 cardbus_chipset_tag_t cc; 1979 cardbustag_t tag; 1980 int offset; /* register offset */ 1981 { 1982 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1983 1984 return pci_conf_read(sc->sc_pc, tag, offset); 1985 } 1986 1987 /* 1988 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1989 * int offs, cardbusreg_t val) 1990 * This is the function to write the config space of a CardBus Card. 1991 * It works same as pci_conf_write. 1992 */ 1993 static void 1994 pccbb_conf_write(cc, tag, reg, val) 1995 cardbus_chipset_tag_t cc; 1996 cardbustag_t tag; 1997 int reg; /* register offset */ 1998 cardbusreg_t val; 1999 { 2000 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2001 2002 pci_conf_write(sc->sc_pc, tag, reg, val); 2003 } 2004 2005 #if 0 2006 STATIC int 2007 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2008 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2009 int speed, int flags, 2010 bus_space_handle_t * iohp) 2011 #endif 2012 /* 2013 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2014 * bus_addr_t start, bus_size_t size, 2015 * bus_size_t align, 2016 * struct pcmcia_io_handle *pcihp 2017 * 2018 * This function only allocates I/O region for pccard. This function 2019 * never maps the allocated region to pccard I/O area. 2020 * 2021 * XXX: The interface of this function is not very good, I believe. 2022 */ 2023 STATIC int 2024 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2025 pcmcia_chipset_handle_t pch; 2026 bus_addr_t start; /* start address */ 2027 bus_size_t size; 2028 bus_size_t align; 2029 struct pcmcia_io_handle *pcihp; 2030 { 2031 struct pcic_handle *ph = (struct pcic_handle *)pch; 2032 bus_addr_t ioaddr; 2033 int flags = 0; 2034 bus_space_tag_t iot; 2035 bus_space_handle_t ioh; 2036 bus_addr_t mask; 2037 #if rbus 2038 rbus_tag_t rb; 2039 #endif 2040 if (align == 0) { 2041 align = size; /* XXX: funny??? */ 2042 } 2043 2044 if (start != 0) { 2045 /* XXX: assume all card decode lower 10 bits by its hardware */ 2046 mask = 0x3ff; 2047 /* enforce to use only masked address */ 2048 start &= mask; 2049 } else { 2050 /* 2051 * calculate mask: 2052 * 1. get the most significant bit of size (call it msb). 2053 * 2. compare msb with the value of size. 2054 * 3. if size is larger, shift msb left once. 2055 * 4. obtain mask value to decrement msb. 2056 */ 2057 bus_size_t size_tmp = size; 2058 int shifts = 0; 2059 2060 mask = 1; 2061 while (size_tmp) { 2062 ++shifts; 2063 size_tmp >>= 1; 2064 } 2065 mask = (1 << shifts); 2066 if (mask < size) { 2067 mask <<= 1; 2068 } 2069 --mask; 2070 } 2071 2072 /* 2073 * Allocate some arbitrary I/O space. 2074 */ 2075 2076 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2077 2078 #if rbus 2079 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2080 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2081 return 1; 2082 } 2083 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2084 (u_long) ioaddr, (u_long) size)); 2085 #else 2086 if (start) { 2087 ioaddr = start; 2088 if (bus_space_map(iot, start, size, 0, &ioh)) { 2089 return 1; 2090 } 2091 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2092 (u_long) ioaddr, (u_long) size)); 2093 } else { 2094 flags |= PCMCIA_IO_ALLOCATED; 2095 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2096 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2097 size, align, 0, 0, &ioaddr, &ioh)) { 2098 /* No room be able to be get. */ 2099 return 1; 2100 } 2101 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2102 (u_long) ioaddr, (u_long) size)); 2103 } 2104 #endif 2105 2106 pcihp->iot = iot; 2107 pcihp->ioh = ioh; 2108 pcihp->addr = ioaddr; 2109 pcihp->size = size; 2110 pcihp->flags = flags; 2111 2112 return 0; 2113 } 2114 2115 /* 2116 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2117 * struct pcmcia_io_handle *pcihp) 2118 * 2119 * This function only frees I/O region for pccard. 2120 * 2121 * XXX: The interface of this function is not very good, I believe. 2122 */ 2123 void 2124 pccbb_pcmcia_io_free(pch, pcihp) 2125 pcmcia_chipset_handle_t pch; 2126 struct pcmcia_io_handle *pcihp; 2127 { 2128 #if !rbus 2129 bus_space_tag_t iot = pcihp->iot; 2130 #endif 2131 bus_space_handle_t ioh = pcihp->ioh; 2132 bus_size_t size = pcihp->size; 2133 2134 #if rbus 2135 struct pccbb_softc *sc = 2136 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2137 rbus_tag_t rb = sc->sc_rbus_iot; 2138 2139 rbus_space_free(rb, ioh, size, NULL); 2140 #else 2141 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2142 bus_space_free(iot, ioh, size); 2143 else 2144 bus_space_unmap(iot, ioh, size); 2145 #endif 2146 } 2147 2148 /* 2149 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2150 * bus_addr_t offset, bus_size_t size, 2151 * struct pcmcia_io_handle *pcihp, 2152 * int *windowp) 2153 * 2154 * This function maps the allocated I/O region to pccard. This function 2155 * never allocates any I/O region for pccard I/O area. I don't 2156 * understand why the original authors of pcmciabus separated alloc and 2157 * map. I believe the two must be unite. 2158 * 2159 * XXX: no wait timing control? 2160 */ 2161 int 2162 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2163 pcmcia_chipset_handle_t pch; 2164 int width; 2165 bus_addr_t offset; 2166 bus_size_t size; 2167 struct pcmcia_io_handle *pcihp; 2168 int *windowp; 2169 { 2170 struct pcic_handle *ph = (struct pcic_handle *)pch; 2171 bus_addr_t ioaddr = pcihp->addr + offset; 2172 int i, win; 2173 #if defined CBB_DEBUG 2174 static char *width_names[] = { "dynamic", "io8", "io16" }; 2175 #endif 2176 2177 /* Sanity check I/O handle. */ 2178 2179 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2180 panic("pccbb_pcmcia_io_map iot is bogus"); 2181 } 2182 2183 /* XXX Sanity check offset/size. */ 2184 2185 win = -1; 2186 for (i = 0; i < PCIC_IO_WINS; i++) { 2187 if ((ph->ioalloc & (1 << i)) == 0) { 2188 win = i; 2189 ph->ioalloc |= (1 << i); 2190 break; 2191 } 2192 } 2193 2194 if (win == -1) { 2195 return 1; 2196 } 2197 2198 *windowp = win; 2199 2200 /* XXX this is pretty gross */ 2201 2202 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2203 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2204 2205 /* XXX wtf is this doing here? */ 2206 2207 #if 0 2208 printf(" port 0x%lx", (u_long) ioaddr); 2209 if (size > 1) { 2210 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2211 } 2212 #endif 2213 2214 ph->io[win].addr = ioaddr; 2215 ph->io[win].size = size; 2216 ph->io[win].width = width; 2217 2218 /* actual dirty register-value changing in the function below. */ 2219 pccbb_pcmcia_do_io_map(ph, win); 2220 2221 return 0; 2222 } 2223 2224 /* 2225 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2226 * 2227 * This function changes register-value to map I/O region for pccard. 2228 */ 2229 static void 2230 pccbb_pcmcia_do_io_map(ph, win) 2231 struct pcic_handle *ph; 2232 int win; 2233 { 2234 static u_int8_t pcic_iowidth[3] = { 2235 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2236 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2237 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2238 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2239 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2240 }; 2241 2242 #define PCIC_SIA_START_LOW 0 2243 #define PCIC_SIA_START_HIGH 1 2244 #define PCIC_SIA_STOP_LOW 2 2245 #define PCIC_SIA_STOP_HIGH 3 2246 2247 int regbase_win = 0x8 + win * 0x04; 2248 u_int8_t ioctl, enable; 2249 2250 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2251 "width %d\n", win, (unsigned long)ph->io[win].addr, 2252 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2253 2254 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2255 ph->io[win].addr & 0xff); 2256 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2257 (ph->io[win].addr >> 8) & 0xff); 2258 2259 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2260 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2261 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2262 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2263 2264 ioctl = Pcic_read(ph, PCIC_IOCTL); 2265 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2266 switch (win) { 2267 case 0: 2268 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2269 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2270 PCIC_IOCTL_IO0_DATASIZE_MASK); 2271 ioctl |= pcic_iowidth[ph->io[win].width]; 2272 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2273 break; 2274 case 1: 2275 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2276 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2277 PCIC_IOCTL_IO1_DATASIZE_MASK); 2278 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2279 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2280 break; 2281 } 2282 Pcic_write(ph, PCIC_IOCTL, ioctl); 2283 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2284 #if defined CBB_DEBUG 2285 { 2286 u_int8_t start_low = 2287 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2288 u_int8_t start_high = 2289 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2290 u_int8_t stop_low = 2291 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2292 u_int8_t stop_high = 2293 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2294 printf 2295 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2296 start_low, start_high, stop_low, stop_high, ioctl, enable); 2297 } 2298 #endif 2299 } 2300 2301 /* 2302 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2303 * 2304 * This function unmaps I/O region. No return value. 2305 */ 2306 STATIC void 2307 pccbb_pcmcia_io_unmap(pch, win) 2308 pcmcia_chipset_handle_t pch; 2309 int win; 2310 { 2311 struct pcic_handle *ph = (struct pcic_handle *)pch; 2312 int reg; 2313 2314 if (win >= PCIC_IO_WINS || win < 0) { 2315 panic("pccbb_pcmcia_io_unmap: window out of range"); 2316 } 2317 2318 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2319 switch (win) { 2320 case 0: 2321 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2322 break; 2323 case 1: 2324 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2325 break; 2326 } 2327 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2328 2329 ph->ioalloc &= ~(1 << win); 2330 } 2331 2332 /* 2333 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2334 * 2335 * This function enables the card. All information is stored in 2336 * the first argument, pcmcia_chipset_handle_t. 2337 */ 2338 static int 2339 pccbb_pcmcia_wait_ready(ph) 2340 struct pcic_handle *ph; 2341 { 2342 u_char stat; 2343 int i; 2344 2345 DPRINTF(("entering pccbb_pcmcia_wait_ready: status 0x%02x\n", 2346 Pcic_read(ph, PCIC_IF_STATUS))); 2347 2348 for (i = 0; i < 2000; i++) { 2349 stat = Pcic_read(ph, PCIC_IF_STATUS); 2350 if (stat & PCIC_IF_STATUS_READY) 2351 return 1; 2352 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2353 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2354 return 0; 2355 DELAY_MS(2, ph->ph_parent); 2356 #ifdef CBB_DEBUG 2357 if ((i > 1000) && (i % 25 == 24)) 2358 printf("."); 2359 #endif 2360 } 2361 2362 #ifdef DIAGNOSTIC 2363 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2364 Pcic_read(ph, PCIC_IF_STATUS)); 2365 #endif 2366 2367 return 0; 2368 } 2369 2370 /* 2371 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2372 * 2373 * This function enables the card. All information is stored in 2374 * the first argument, pcmcia_chipset_handle_t. 2375 */ 2376 STATIC void 2377 pccbb_pcmcia_socket_enable(pch) 2378 pcmcia_chipset_handle_t pch; 2379 { 2380 struct pcic_handle *ph = (struct pcic_handle *)pch; 2381 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2382 int cardtype, win; 2383 u_int8_t power, intr; 2384 pcireg_t spsr; 2385 int voltage; 2386 2387 /* this bit is mostly stolen from pcic_attach_card */ 2388 2389 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2390 2391 /* get card Vcc info */ 2392 2393 spsr = 2394 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2395 CB_SOCKET_STAT); 2396 if (spsr & CB_SOCKET_STAT_5VCARD) { 2397 DPRINTF(("5V card\n")); 2398 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2399 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2400 DPRINTF(("3V card\n")); 2401 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2402 } else { 2403 printf("?V card, 0x%x\n", spsr); /* XXX */ 2404 return; 2405 } 2406 2407 /* disable socket: negate output enable bit and power off */ 2408 2409 power = 0; 2410 Pcic_write(ph, PCIC_PWRCTL, power); 2411 2412 /* power down the socket to reset it, clear the card reset pin */ 2413 2414 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2415 2416 /* 2417 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2418 * we are changing Vcc (Toff). 2419 */ 2420 /* delay(300*1000); too much */ 2421 2422 /* assert reset bit */ 2423 intr = Pcic_read(ph, PCIC_INTR); 2424 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2425 Pcic_write(ph, PCIC_INTR, intr); 2426 2427 /* power up the socket */ 2428 power = Pcic_read(ph, PCIC_PWRCTL); 2429 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 2430 pccbb_power(sc, voltage); 2431 2432 /* now output enable */ 2433 power = Pcic_read(ph, PCIC_PWRCTL); 2434 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2435 2436 if (pccbb_power(sc, voltage) == 0) { 2437 power &= PCIC_PWRCTL_OE; 2438 Pcic_write(ph, PCIC_PWRCTL, power); 2439 intr |= PCIC_INTR_RESET; 2440 Pcic_write(ph, PCIC_INTR, intr); 2441 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2442 return; 2443 } 2444 2445 /* 2446 * hold RESET at least 20 ms: the spec says only 10 us is 2447 * enough, but TI1130 requires at least 20 ms. 2448 */ 2449 #if 0 /* XXX called on interrupt context */ 2450 DELAY_MS(20, sc); 2451 #else 2452 delay(20 * 1000); 2453 #endif 2454 2455 /* clear the reset flag */ 2456 2457 intr |= PCIC_INTR_RESET; 2458 Pcic_write(ph, PCIC_INTR, intr); 2459 2460 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2461 2462 #if 0 /* XXX called on interrupt context */ 2463 DELAY_MS(20, sc); 2464 #else 2465 delay(20 * 1000); 2466 #endif 2467 2468 /* wait for the chip to finish initializing */ 2469 2470 if (pccbb_pcmcia_wait_ready(ph) == 0) { 2471 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2472 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2473 return; 2474 } 2475 2476 /* zero out the address windows */ 2477 2478 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2479 2480 /* set the card type */ 2481 2482 cardtype = pcmcia_card_gettype(ph->pcmcia); 2483 2484 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2485 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2486 Pcic_write(ph, PCIC_INTR, intr); 2487 2488 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2489 ph->ph_parent->dv_xname, ph->sock, 2490 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2491 2492 /* reinstall all the memory and io mappings */ 2493 2494 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2495 if (ph->memalloc & (1 << win)) { 2496 pccbb_pcmcia_do_mem_map(ph, win); 2497 } 2498 } 2499 2500 for (win = 0; win < PCIC_IO_WINS; ++win) { 2501 if (ph->ioalloc & (1 << win)) { 2502 pccbb_pcmcia_do_io_map(ph, win); 2503 } 2504 } 2505 } 2506 2507 /* 2508 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2509 * 2510 * This function disables the card. All information is stored in 2511 * the first argument, pcmcia_chipset_handle_t. 2512 */ 2513 STATIC void 2514 pccbb_pcmcia_socket_disable(pch) 2515 pcmcia_chipset_handle_t pch; 2516 { 2517 struct pcic_handle *ph = (struct pcic_handle *)pch; 2518 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2519 u_int8_t power, intr; 2520 2521 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2522 2523 /* reset signal asserting... */ 2524 2525 intr = Pcic_read(ph, PCIC_INTR); 2526 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2527 Pcic_write(ph, PCIC_INTR, intr); 2528 delay(2 * 1000); 2529 2530 /* power down the socket */ 2531 power = Pcic_read(ph, PCIC_PWRCTL); 2532 power &= ~PCIC_PWRCTL_OE; 2533 Pcic_write(ph, PCIC_PWRCTL, power); 2534 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2535 /* 2536 * wait 300ms until power fails (Tpf). 2537 */ 2538 #if 0 /* XXX called on interrupt context */ 2539 DELAY_MS(300, sc); 2540 #else 2541 delay(300 * 1000); 2542 #endif 2543 } 2544 2545 /* 2546 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2547 * 2548 * This function detects whether a card is in the slot or not. 2549 * If a card is inserted, return 1. Otherwise, return 0. 2550 */ 2551 STATIC int 2552 pccbb_pcmcia_card_detect(pch) 2553 pcmcia_chipset_handle_t pch; 2554 { 2555 struct pcic_handle *ph = (struct pcic_handle *)pch; 2556 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2557 2558 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2559 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2560 } 2561 2562 #if 0 2563 STATIC int 2564 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2565 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2566 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2567 #endif 2568 /* 2569 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2570 * bus_size_t size, 2571 * struct pcmcia_mem_handle *pcmhp) 2572 * 2573 * This function only allocates memory region for pccard. This 2574 * function never maps the allocated region to pccard memory area. 2575 * 2576 * XXX: Why the argument of start address is not in? 2577 */ 2578 STATIC int 2579 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2580 pcmcia_chipset_handle_t pch; 2581 bus_size_t size; 2582 struct pcmcia_mem_handle *pcmhp; 2583 { 2584 struct pcic_handle *ph = (struct pcic_handle *)pch; 2585 bus_space_handle_t memh; 2586 bus_addr_t addr; 2587 bus_size_t sizepg; 2588 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2589 #if rbus 2590 rbus_tag_t rb; 2591 #endif 2592 2593 /* Check that the card is still there. */ 2594 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2595 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2596 return 1; 2597 2598 /* out of sc->memh, allocate as many pages as necessary */ 2599 2600 /* convert size to PCIC pages */ 2601 /* 2602 * This is not enough; when the requested region is on the page 2603 * boundaries, this may calculate wrong result. 2604 */ 2605 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2606 #if 0 2607 if (sizepg > PCIC_MAX_MEM_PAGES) { 2608 return 1; 2609 } 2610 #endif 2611 2612 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2613 return 1; 2614 } 2615 2616 addr = 0; /* XXX gcc -Wuninitialized */ 2617 2618 #if rbus 2619 rb = sc->sc_rbus_memt; 2620 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2621 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2622 &addr, &memh)) { 2623 return 1; 2624 } 2625 #else 2626 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2627 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2628 0, /* boundary */ 2629 0, /* flags */ 2630 &addr, &memh)) { 2631 return 1; 2632 } 2633 #endif 2634 2635 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2636 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2637 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2638 2639 pcmhp->memt = sc->sc_memt; 2640 pcmhp->memh = memh; 2641 pcmhp->addr = addr; 2642 pcmhp->size = size; 2643 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2644 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2645 pcmhp->mhandle = 0; 2646 /* No offset??? Funny. */ 2647 2648 return 0; 2649 } 2650 2651 /* 2652 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2653 * struct pcmcia_mem_handle *pcmhp) 2654 * 2655 * This function release the memory space allocated by the function 2656 * pccbb_pcmcia_mem_alloc(). 2657 */ 2658 STATIC void 2659 pccbb_pcmcia_mem_free(pch, pcmhp) 2660 pcmcia_chipset_handle_t pch; 2661 struct pcmcia_mem_handle *pcmhp; 2662 { 2663 #if rbus 2664 struct pcic_handle *ph = (struct pcic_handle *)pch; 2665 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2666 2667 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2668 #else 2669 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2670 #endif 2671 } 2672 2673 /* 2674 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2675 * 2676 * This function release the memory space allocated by the function 2677 * pccbb_pcmcia_mem_alloc(). 2678 */ 2679 STATIC void 2680 pccbb_pcmcia_do_mem_map(ph, win) 2681 struct pcic_handle *ph; 2682 int win; 2683 { 2684 int regbase_win; 2685 bus_addr_t phys_addr; 2686 bus_addr_t phys_end; 2687 2688 #define PCIC_SMM_START_LOW 0 2689 #define PCIC_SMM_START_HIGH 1 2690 #define PCIC_SMM_STOP_LOW 2 2691 #define PCIC_SMM_STOP_HIGH 3 2692 #define PCIC_CMA_LOW 4 2693 #define PCIC_CMA_HIGH 5 2694 2695 u_int8_t start_low, start_high = 0; 2696 u_int8_t stop_low, stop_high; 2697 u_int8_t off_low, off_high; 2698 u_int8_t mem_window; 2699 int reg; 2700 2701 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2702 int mem8 = 2703 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2704 || (kind == PCMCIA_MEM_ATTR); 2705 2706 regbase_win = 0x10 + win * 0x08; 2707 2708 phys_addr = ph->mem[win].addr; 2709 phys_end = phys_addr + ph->mem[win].size; 2710 2711 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2712 (unsigned long)phys_addr, (unsigned long)phys_end, 2713 (unsigned long)ph->mem[win].offset)); 2714 2715 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2716 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2717 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2718 2719 /* bit 19:12 */ 2720 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2721 /* bit 23:20 and bit 7 on */ 2722 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2723 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2724 /* bit 31:24, for 32-bit address */ 2725 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2726 2727 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2728 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2729 2730 if (((struct pccbb_softc *)ph-> 2731 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2732 Pcic_write(ph, 0x40 + win, mem_window); 2733 } 2734 2735 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2736 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2737 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2738 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2739 2740 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2741 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2742 2743 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2744 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2745 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2746 | ((kind == PCMCIA_MEM_ATTR) ? 2747 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2748 2749 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2750 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2751 2752 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2753 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2754 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2755 2756 #if defined CBB_DEBUG 2757 { 2758 int r1, r2, r3, r4, r5, r6, r7 = 0; 2759 2760 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2761 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2762 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2763 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2764 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2765 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2766 if (((struct pccbb_softc *)(ph-> 2767 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2768 r7 = Pcic_read(ph, 0x40 + win); 2769 } 2770 2771 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2772 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2773 if (((struct pccbb_softc *)(ph-> 2774 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2775 DPRINTF((" %02x", r7)); 2776 } 2777 DPRINTF(("\n")); 2778 } 2779 #endif 2780 } 2781 2782 /* 2783 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2784 * bus_addr_t card_addr, bus_size_t size, 2785 * struct pcmcia_mem_handle *pcmhp, 2786 * bus_addr_t *offsetp, int *windowp) 2787 * 2788 * This function maps memory space allocated by the function 2789 * pccbb_pcmcia_mem_alloc(). 2790 */ 2791 STATIC int 2792 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2793 pcmcia_chipset_handle_t pch; 2794 int kind; 2795 bus_addr_t card_addr; 2796 bus_size_t size; 2797 struct pcmcia_mem_handle *pcmhp; 2798 bus_addr_t *offsetp; 2799 int *windowp; 2800 { 2801 struct pcic_handle *ph = (struct pcic_handle *)pch; 2802 bus_addr_t busaddr; 2803 long card_offset; 2804 int win; 2805 2806 /* Check that the card is still there. */ 2807 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2808 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2809 return 1; 2810 2811 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2812 if ((ph->memalloc & (1 << win)) == 0) { 2813 ph->memalloc |= (1 << win); 2814 break; 2815 } 2816 } 2817 2818 if (win == PCIC_MEM_WINS) { 2819 return 1; 2820 } 2821 2822 *windowp = win; 2823 2824 /* XXX this is pretty gross */ 2825 2826 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2827 panic("pccbb_pcmcia_mem_map memt is bogus"); 2828 } 2829 2830 busaddr = pcmhp->addr; 2831 2832 /* 2833 * compute the address offset to the pcmcia address space for the 2834 * pcic. this is intentionally signed. The masks and shifts below 2835 * will cause TRT to happen in the pcic registers. Deal with making 2836 * sure the address is aligned, and return the alignment offset. 2837 */ 2838 2839 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2840 card_addr -= *offsetp; 2841 2842 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2843 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2844 (u_long) card_addr)); 2845 2846 /* 2847 * include the offset in the size, and decrement size by one, since 2848 * the hw wants start/stop 2849 */ 2850 size += *offsetp - 1; 2851 2852 card_offset = (((long)card_addr) - ((long)busaddr)); 2853 2854 ph->mem[win].addr = busaddr; 2855 ph->mem[win].size = size; 2856 ph->mem[win].offset = card_offset; 2857 ph->mem[win].kind = kind; 2858 2859 pccbb_pcmcia_do_mem_map(ph, win); 2860 2861 return 0; 2862 } 2863 2864 /* 2865 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2866 * int window) 2867 * 2868 * This function unmaps memory space which mapped by the function 2869 * pccbb_pcmcia_mem_map(). 2870 */ 2871 STATIC void 2872 pccbb_pcmcia_mem_unmap(pch, window) 2873 pcmcia_chipset_handle_t pch; 2874 int window; 2875 { 2876 struct pcic_handle *ph = (struct pcic_handle *)pch; 2877 int reg; 2878 2879 if (window >= PCIC_MEM_WINS) { 2880 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2881 } 2882 2883 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2884 reg &= ~(1 << window); 2885 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2886 2887 ph->memalloc &= ~(1 << window); 2888 } 2889 2890 #if defined PCCBB_PCMCIA_POLL 2891 struct pccbb_poll_str { 2892 void *arg; 2893 int (*func) __P((void *)); 2894 int level; 2895 struct pcic_handle *ph; 2896 int count; 2897 int num; 2898 struct callout poll_ch; 2899 }; 2900 2901 static struct pccbb_poll_str pccbb_poll[10]; 2902 static int pccbb_poll_n = 0; 2903 2904 static void pccbb_pcmcia_poll __P((void *arg)); 2905 2906 static void 2907 pccbb_pcmcia_poll(arg) 2908 void *arg; 2909 { 2910 struct pccbb_poll_str *poll = arg; 2911 struct pcic_handle *ph = poll->ph; 2912 struct pccbb_softc *sc = ph->sc; 2913 int s; 2914 u_int32_t spsr; /* socket present-state reg */ 2915 2916 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2917 switch (poll->level) { 2918 case IPL_NET: 2919 s = splnet(); 2920 break; 2921 case IPL_BIO: 2922 s = splbio(); 2923 break; 2924 case IPL_TTY: /* fallthrough */ 2925 default: 2926 s = spltty(); 2927 break; 2928 } 2929 2930 spsr = 2931 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2932 CB_SOCKET_STAT); 2933 2934 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2935 if (!(spsr & 0x40)) /* CINT low */ 2936 #else 2937 if (1) 2938 #endif 2939 { 2940 if ((*poll->func) (poll->arg) > 0) { 2941 ++poll->count; 2942 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2943 #if defined LEVEL2 2944 } else { 2945 printf("intr: miss! 0x%x\n", spsr); 2946 #endif 2947 } 2948 } 2949 splx(s); 2950 } 2951 #endif /* defined CB_PCMCIA_POLL */ 2952 2953 /* 2954 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2955 * struct pcmcia_function *pf, 2956 * int ipl, 2957 * int (*func)(void *), 2958 * void *arg); 2959 * 2960 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2961 */ 2962 STATIC void * 2963 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2964 pcmcia_chipset_handle_t pch; 2965 struct pcmcia_function *pf; 2966 int ipl; 2967 int (*func) __P((void *)); 2968 void *arg; 2969 { 2970 struct pcic_handle *ph = (struct pcic_handle *)pch; 2971 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2972 2973 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2974 /* what should I do? */ 2975 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2976 DPRINTF(("%s does not provide edge nor pulse " 2977 "interrupt\n", sc->sc_dev.dv_xname)); 2978 return NULL; 2979 } 2980 /* 2981 * XXX Noooooo! The interrupt flag must set properly!! 2982 * dumb pcmcia driver!! 2983 */ 2984 } 2985 2986 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2987 } 2988 2989 /* 2990 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2991 * void *ih) 2992 * 2993 * This function disables PC-Card interrupt. 2994 */ 2995 STATIC void 2996 pccbb_pcmcia_intr_disestablish(pch, ih) 2997 pcmcia_chipset_handle_t pch; 2998 void *ih; 2999 { 3000 struct pcic_handle *ph = (struct pcic_handle *)pch; 3001 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3002 3003 pccbb_intr_disestablish(sc, ih); 3004 } 3005 3006 #if rbus 3007 /* 3008 * static int 3009 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3010 * bus_addr_t addr, bus_size_t size, 3011 * bus_addr_t mask, bus_size_t align, 3012 * int flags, bus_addr_t *addrp; 3013 * bus_space_handle_t *bshp) 3014 * 3015 * This function allocates a portion of memory or io space for 3016 * clients. This function is called from CardBus card drivers. 3017 */ 3018 static int 3019 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3020 cardbus_chipset_tag_t ct; 3021 rbus_tag_t rb; 3022 bus_addr_t addr; 3023 bus_size_t size; 3024 bus_addr_t mask; 3025 bus_size_t align; 3026 int flags; 3027 bus_addr_t *addrp; 3028 bus_space_handle_t *bshp; 3029 { 3030 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3031 3032 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3033 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3034 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3035 3036 if (align == 0) { 3037 align = size; 3038 } 3039 3040 if (rb->rb_bt == sc->sc_memt) { 3041 if (align < 16) { 3042 return 1; 3043 } 3044 /* 3045 * XXX: align more than 0x1000 to avoid overwrapping 3046 * memory windows for two or more devices. 0x1000 3047 * means memory window's granularity. 3048 * 3049 * Two or more devices should be able to share same 3050 * memory window region. However, overrapping memory 3051 * window is not good because some devices, such as 3052 * 3Com 3C575[BC], have a broken address decoder and 3053 * intrude other's memory region. 3054 */ 3055 if (align < 0x1000) { 3056 align = 0x1000; 3057 } 3058 } else if (rb->rb_bt == sc->sc_iot) { 3059 if (align < 4) { 3060 return 1; 3061 } 3062 /* XXX: hack for avoiding ISA image */ 3063 if (mask < 0x0100) { 3064 mask = 0x3ff; 3065 addr = 0x300; 3066 } 3067 3068 } else { 3069 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3070 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3071 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3072 (unsigned long)sc->sc_memt)); 3073 return 1; 3074 /* XXX: panic here? */ 3075 } 3076 3077 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3078 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3079 return 1; 3080 } 3081 3082 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3083 3084 return 0; 3085 } 3086 3087 /* 3088 * static int 3089 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3090 * bus_space_handle_t *bshp, bus_size_t size); 3091 * 3092 * This function is called from CardBus card drivers. 3093 */ 3094 static int 3095 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3096 cardbus_chipset_tag_t ct; 3097 rbus_tag_t rb; 3098 bus_space_handle_t bsh; 3099 bus_size_t size; 3100 { 3101 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3102 bus_space_tag_t bt = rb->rb_bt; 3103 3104 pccbb_close_win(sc, bt, bsh, size); 3105 3106 if (bt == sc->sc_memt) { 3107 } else if (bt == sc->sc_iot) { 3108 } else { 3109 return 1; 3110 /* XXX: panic here? */ 3111 } 3112 3113 return rbus_space_free(rb, bsh, size, NULL); 3114 } 3115 #endif /* rbus */ 3116 3117 #if rbus 3118 3119 static int 3120 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3121 struct pccbb_softc *sc; 3122 bus_space_tag_t bst; 3123 bus_addr_t addr; 3124 bus_size_t size; 3125 bus_space_handle_t bsh; 3126 int flags; 3127 { 3128 struct pccbb_win_chain_head *head; 3129 bus_addr_t align; 3130 3131 head = &sc->sc_iowindow; 3132 align = 0x04; 3133 if (sc->sc_memt == bst) { 3134 head = &sc->sc_memwindow; 3135 align = 0x1000; 3136 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3137 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3138 (unsigned long)bst)); 3139 } 3140 3141 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3142 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3143 sc->sc_dev.dv_xname, 3144 (head == &sc->sc_memwindow) ? "mem" : "io"); 3145 } 3146 pccbb_winset(align, sc, bst); 3147 3148 return 0; 3149 } 3150 3151 static int 3152 pccbb_close_win(sc, bst, bsh, size) 3153 struct pccbb_softc *sc; 3154 bus_space_tag_t bst; 3155 bus_space_handle_t bsh; 3156 bus_size_t size; 3157 { 3158 struct pccbb_win_chain_head *head; 3159 bus_addr_t align; 3160 3161 head = &sc->sc_iowindow; 3162 align = 0x04; 3163 if (sc->sc_memt == bst) { 3164 head = &sc->sc_memwindow; 3165 align = 0x1000; 3166 } 3167 3168 if (pccbb_winlist_delete(head, bsh, size)) { 3169 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3170 sc->sc_dev.dv_xname, 3171 (head == &sc->sc_memwindow) ? "mem" : "io"); 3172 } 3173 pccbb_winset(align, sc, bst); 3174 3175 return 0; 3176 } 3177 3178 static int 3179 pccbb_winlist_insert(head, start, size, bsh, flags) 3180 struct pccbb_win_chain_head *head; 3181 bus_addr_t start; 3182 bus_size_t size; 3183 bus_space_handle_t bsh; 3184 int flags; 3185 { 3186 struct pccbb_win_chain *chainp, *elem; 3187 3188 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3189 M_NOWAIT)) == NULL) 3190 return (1); /* fail */ 3191 3192 elem->wc_start = start; 3193 elem->wc_end = start + (size - 1); 3194 elem->wc_handle = bsh; 3195 elem->wc_flags = flags; 3196 3197 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3198 chainp = TAILQ_NEXT(chainp, wc_list)) { 3199 if (chainp->wc_end < start) 3200 continue; 3201 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3202 return (0); 3203 } 3204 3205 TAILQ_INSERT_TAIL(head, elem, wc_list); 3206 return (0); 3207 } 3208 3209 static int 3210 pccbb_winlist_delete(head, bsh, size) 3211 struct pccbb_win_chain_head *head; 3212 bus_space_handle_t bsh; 3213 bus_size_t size; 3214 { 3215 struct pccbb_win_chain *chainp; 3216 3217 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3218 chainp = TAILQ_NEXT(chainp, wc_list)) { 3219 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3220 continue; 3221 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3222 printf("pccbb_winlist_delete: window 0x%lx size " 3223 "inconsistent: 0x%lx, 0x%lx\n", 3224 (unsigned long)chainp->wc_start, 3225 (unsigned long)(chainp->wc_end - chainp->wc_start), 3226 (unsigned long)(size - 1)); 3227 return 1; 3228 } 3229 3230 TAILQ_REMOVE(head, chainp, wc_list); 3231 free(chainp, M_DEVBUF); 3232 3233 return 0; 3234 } 3235 3236 return 1; /* fail: no candidate to remove */ 3237 } 3238 3239 static void 3240 pccbb_winset(align, sc, bst) 3241 bus_addr_t align; 3242 struct pccbb_softc *sc; 3243 bus_space_tag_t bst; 3244 { 3245 pci_chipset_tag_t pc; 3246 pcitag_t tag; 3247 bus_addr_t mask = ~(align - 1); 3248 struct { 3249 cardbusreg_t win_start; 3250 cardbusreg_t win_limit; 3251 int win_flags; 3252 } win[2]; 3253 struct pccbb_win_chain *chainp; 3254 int offs; 3255 3256 win[0].win_start = win[1].win_start = 0xffffffff; 3257 win[0].win_limit = win[1].win_limit = 0; 3258 win[0].win_flags = win[1].win_flags = 0; 3259 3260 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3261 offs = 0x2c; 3262 if (sc->sc_memt == bst) { 3263 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3264 offs = 0x1c; 3265 } 3266 3267 if (chainp != NULL) { 3268 win[0].win_start = chainp->wc_start & mask; 3269 win[0].win_limit = chainp->wc_end & mask; 3270 win[0].win_flags = chainp->wc_flags; 3271 chainp = TAILQ_NEXT(chainp, wc_list); 3272 } 3273 3274 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3275 if (win[1].win_start == 0xffffffff) { 3276 /* window 1 is not used */ 3277 if ((win[0].win_flags == chainp->wc_flags) && 3278 (win[0].win_limit + align >= 3279 (chainp->wc_start & mask))) { 3280 /* concatenate */ 3281 win[0].win_limit = chainp->wc_end & mask; 3282 } else { 3283 /* make new window */ 3284 win[1].win_start = chainp->wc_start & mask; 3285 win[1].win_limit = chainp->wc_end & mask; 3286 win[1].win_flags = chainp->wc_flags; 3287 } 3288 continue; 3289 } 3290 3291 /* Both windows are engaged. */ 3292 if (win[0].win_flags == win[1].win_flags) { 3293 /* same flags */ 3294 if (win[0].win_flags == chainp->wc_flags) { 3295 if (win[1].win_start - (win[0].win_limit + 3296 align) < 3297 (chainp->wc_start & mask) - 3298 ((chainp->wc_end & mask) + align)) { 3299 /* 3300 * merge window 0 and 1, and set win1 3301 * to chainp 3302 */ 3303 win[0].win_limit = win[1].win_limit; 3304 win[1].win_start = 3305 chainp->wc_start & mask; 3306 win[1].win_limit = 3307 chainp->wc_end & mask; 3308 } else { 3309 win[1].win_limit = 3310 chainp->wc_end & mask; 3311 } 3312 } else { 3313 /* different flags */ 3314 3315 /* concatenate win0 and win1 */ 3316 win[0].win_limit = win[1].win_limit; 3317 /* allocate win[1] to new space */ 3318 win[1].win_start = chainp->wc_start & mask; 3319 win[1].win_limit = chainp->wc_end & mask; 3320 win[1].win_flags = chainp->wc_flags; 3321 } 3322 } else { 3323 /* the flags of win[0] and win[1] is different */ 3324 if (win[0].win_flags == chainp->wc_flags) { 3325 win[0].win_limit = chainp->wc_end & mask; 3326 /* 3327 * XXX this creates overlapping windows, so 3328 * what should the poor bridge do if one is 3329 * cachable, and the other is not? 3330 */ 3331 printf("%s: overlapping windows\n", 3332 sc->sc_dev.dv_xname); 3333 } else { 3334 win[1].win_limit = chainp->wc_end & mask; 3335 } 3336 } 3337 } 3338 3339 pc = sc->sc_pc; 3340 tag = sc->sc_tag; 3341 pci_conf_write(pc, tag, offs, win[0].win_start); 3342 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3343 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3344 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3345 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3346 (unsigned long)pci_conf_read(pc, tag, offs), 3347 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3348 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3349 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3350 3351 if (bst == sc->sc_memt) { 3352 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3353 3354 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3355 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3356 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3357 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3358 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3359 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3360 } 3361 } 3362 3363 #endif /* rbus */ 3364 3365 static void 3366 pccbb_powerhook(why, arg) 3367 int why; 3368 void *arg; 3369 { 3370 struct pccbb_softc *sc = arg; 3371 pcireg_t reg; 3372 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3373 bus_space_handle_t base_memh = sc->sc_base_memh; 3374 3375 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3376 3377 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3378 DPRINTF(("%s: power: why %d stopping intr\n", 3379 sc->sc_dev.dv_xname, why)); 3380 if (sc->sc_pil_intr_enable) { 3381 (void)pccbbintr_function(sc); 3382 } 3383 sc->sc_pil_intr_enable = 0; 3384 3385 /* ToDo: deactivate or suspend child devices */ 3386 3387 } 3388 3389 if (why == PWR_RESUME) { 3390 if (sc->sc_pwrmgt_offs != 0) { 3391 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3392 sc->sc_pwrmgt_offs + 4); 3393 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3394 reg & 0x100) { 3395 /* powrstate != D0 */ 3396 3397 printf("%s going back to D0 mode\n", 3398 sc->sc_dev.dv_xname); 3399 reg &= ~PCI_PMCSR_STATE_MASK; 3400 reg |= PCI_PMCSR_STATE_D0; 3401 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3402 pci_conf_write(sc->sc_pc, sc->sc_tag, 3403 sc->sc_pwrmgt_offs + 4, reg); 3404 3405 pci_conf_write(sc->sc_pc, sc->sc_tag, 3406 PCI_SOCKBASE, sc->sc_sockbase); 3407 pci_conf_write(sc->sc_pc, sc->sc_tag, 3408 PCI_BUSNUM, sc->sc_busnum); 3409 pccbb_chipinit(sc); 3410 /* setup memory and io space window for CB */ 3411 pccbb_winset(0x1000, sc, sc->sc_memt); 3412 pccbb_winset(0x04, sc, sc->sc_iot); 3413 } 3414 } 3415 3416 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3417 /* BIOS did not recover this register */ 3418 pci_conf_write (sc->sc_pc, sc->sc_tag, 3419 PCI_SOCKBASE, sc->sc_sockbase); 3420 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3421 /* BIOS did not recover this register */ 3422 pci_conf_write (sc->sc_pc, sc->sc_tag, 3423 PCI_BUSNUM, sc->sc_busnum); 3424 /* CSC Interrupt: Card detect interrupt on */ 3425 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3426 /* Card detect intr is turned on. */ 3427 reg |= CB_SOCKET_MASK_CD; 3428 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3429 /* reset interrupt */ 3430 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3431 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3432 3433 /* 3434 * check for card insertion or removal during suspend period. 3435 * XXX: the code can't cope with card swap (remove then 3436 * insert). how can we detect such situation? 3437 */ 3438 (void)pccbbintr(sc); 3439 3440 sc->sc_pil_intr_enable = 1; 3441 DPRINTF(("%s: power: RESUME enabling intr\n", 3442 sc->sc_dev.dv_xname)); 3443 3444 /* ToDo: activate or wakeup child devices */ 3445 } 3446 } 3447
Indexes created Fri Sep 26 08:10:20 GMT 2025