pccbb.c revision 1.97
1 /* $NetBSD: pccbb.c,v 1.97 2004/04/23 21:13:06 itojun Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.97 2004/04/23 21:13:06 itojun Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static int pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, NULL, NULL); 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 332 /* Ricoh chips */ 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 346 /* Toshiba products */ 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 348 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 350 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 356 /* Cirrus Logic products */ 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 362 /* sentinel, or Generic chip */ 363 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 364 }; 365 366 static int 367 cb_chipset(pci_id, flagp) 368 u_int32_t pci_id; 369 int *flagp; 370 { 371 const struct yenta_chipinfo *yc; 372 373 /* Loop over except the last default entry. */ 374 for (yc = yc_chipsets; yc < yc_chipsets + 375 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 376 if (pci_id == yc->yc_id) 377 break; 378 379 if (flagp != NULL) 380 *flagp = yc->yc_flags; 381 382 return (yc->yc_chiptype); 383 } 384 385 static void 386 pccbb_shutdown(void *arg) 387 { 388 struct pccbb_softc *sc = arg; 389 pcireg_t command; 390 391 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 392 393 /* 394 * turn off power 395 * 396 * XXX - do not turn off power if chipset is TI 113X because 397 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 398 */ 399 if (sc->sc_chipset != CB_TI113X) { 400 pccbb_power((cardbus_chipset_tag_t)sc, 401 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 402 } 403 404 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 405 0); 406 407 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 408 409 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 410 PCI_COMMAND_MASTER_ENABLE); 411 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 412 413 } 414 415 void 416 pccbbattach(parent, self, aux) 417 struct device *parent; 418 struct device *self; 419 void *aux; 420 { 421 struct pccbb_softc *sc = (void *)self; 422 struct pci_attach_args *pa = aux; 423 pci_chipset_tag_t pc = pa->pa_pc; 424 pcireg_t busreg, reg, sock_base; 425 bus_addr_t sockbase; 426 char devinfo[256]; 427 int flags; 428 int pwrmgt_offs; 429 430 #ifdef __HAVE_PCCBB_ATTACH_HOOK 431 pccbb_attach_hook(parent, self, pa); 432 #endif 433 434 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 435 436 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 437 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 438 #ifdef CBB_DEBUG 439 printf(" (chipflags %x)", flags); 440 #endif 441 printf("\n"); 442 443 TAILQ_INIT(&sc->sc_memwindow); 444 TAILQ_INIT(&sc->sc_iowindow); 445 446 #if rbus 447 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 448 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 449 450 #if 0 451 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 452 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 453 #endif 454 #endif /* rbus */ 455 456 sc->sc_flags &= ~CBB_MEMHMAPPED; 457 458 /* power management: set D0 state */ 459 sc->sc_pwrmgt_offs = 0; 460 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 461 &pwrmgt_offs, 0)) { 462 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 463 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 464 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 465 reg &= ~PCI_PMCSR_STATE_MASK; 466 reg |= PCI_PMCSR_STATE_D0; 467 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 468 pci_conf_write(pc, pa->pa_tag, 469 pwrmgt_offs + PCI_PMCSR, reg); 470 } 471 472 sc->sc_pwrmgt_offs = pwrmgt_offs; 473 } 474 475 /* 476 * MAP socket registers and ExCA registers on memory-space 477 * When no valid address is set on socket base registers (on pci 478 * config space), get it not polite way. 479 */ 480 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 481 482 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 483 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 484 /* The address must be valid. */ 485 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 486 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 487 printf("%s: can't map socket base address 0x%lx\n", 488 sc->sc_dev.dv_xname, (unsigned long)sock_base); 489 /* 490 * I think it's funny: socket base registers must be 491 * mapped on memory space, but ... 492 */ 493 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 494 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 495 NULL)) { 496 printf("%s: can't map socket base address" 497 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 498 (unsigned long)sockbase); 499 /* give up... allocate reg space via rbus. */ 500 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 501 } else 502 sc->sc_flags |= CBB_MEMHMAPPED; 503 } else { 504 DPRINTF(("%s: socket base address 0x%lx\n", 505 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 506 sc->sc_flags |= CBB_MEMHMAPPED; 507 } 508 } 509 510 sc->sc_mem_start = 0; /* XXX */ 511 sc->sc_mem_end = 0xffffffff; /* XXX */ 512 513 /* 514 * When interrupt isn't routed correctly, give up probing cbb and do 515 * not kill pcic-compatible port. 516 */ 517 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 518 printf("%s: NOT USED because of unconfigured interrupt\n", 519 sc->sc_dev.dv_xname); 520 return; 521 } 522 523 /* 524 * When bus number isn't set correctly, give up using 32-bit CardBus 525 * mode. 526 */ 527 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 528 #if notyet 529 if (((busreg >> 8) & 0xff) == 0) { 530 printf("%s: CardBus support disabled because of unconfigured bus number\n", 531 sc->sc_dev.dv_xname); 532 flags |= PCCBB_PCMCIA_16BITONLY; 533 } 534 #endif 535 536 /* pccbb_machdep.c end */ 537 538 #if defined CBB_DEBUG 539 { 540 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 541 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 542 intrname[pa->pa_intrpin], pa->pa_intrline); 543 } 544 #endif 545 546 /* setup softc */ 547 sc->sc_pc = pc; 548 sc->sc_iot = pa->pa_iot; 549 sc->sc_memt = pa->pa_memt; 550 sc->sc_dmat = pa->pa_dmat; 551 sc->sc_tag = pa->pa_tag; 552 sc->sc_function = pa->pa_function; 553 sc->sc_sockbase = sock_base; 554 sc->sc_busnum = busreg; 555 556 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 557 558 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 559 560 shutdownhook_establish(pccbb_shutdown, sc); 561 562 /* Disable legacy register mapping. */ 563 switch (sc->sc_chipset) { 564 case CB_RX5C46X: /* fallthrough */ 565 #if 0 566 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 567 case CB_RX5C47X: 568 #endif 569 /* 570 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 571 * cannot be disabled by substituting 0 into PCI_LEGACY 572 * register. Ricoh CardBus bridges have special bits on Bridge 573 * control reg (addr 0x3e on PCI config space). 574 */ 575 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 576 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 577 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 578 break; 579 580 default: 581 /* XXX I don't know proper way to kill legacy I/O. */ 582 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 583 break; 584 } 585 586 config_defer(self, pccbb_pci_callback); 587 } 588 589 590 591 592 /* 593 * static void pccbb_pci_callback(struct device *self) 594 * 595 * The actual attach routine: get memory space for YENTA register 596 * space, setup YENTA register and route interrupt. 597 * 598 * This function should be deferred because this device may obtain 599 * memory space dynamically. This function must avoid obtaining 600 * memory area which has already kept for another device. 601 */ 602 static void 603 pccbb_pci_callback(self) 604 struct device *self; 605 { 606 struct pccbb_softc *sc = (void *)self; 607 pci_chipset_tag_t pc = sc->sc_pc; 608 pci_intr_handle_t ih; 609 const char *intrstr = NULL; 610 bus_addr_t sockbase; 611 struct cbslot_attach_args cba; 612 struct pcmciabus_attach_args paa; 613 struct cardslot_attach_args caa; 614 struct cardslot_softc *csc; 615 616 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 617 /* The socket registers aren't mapped correctly. */ 618 #if rbus 619 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 620 (sc->sc_chipset == CB_RX5C47X 621 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 622 0, &sockbase, &sc->sc_base_memh)) { 623 return; 624 } 625 sc->sc_base_memt = sc->sc_memt; 626 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 627 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 628 sc->sc_dev.dv_xname, (unsigned long)sockbase, 629 (unsigned long)pci_conf_read(pc, sc->sc_tag, 630 PCI_SOCKBASE))); 631 #else 632 sc->sc_base_memt = sc->sc_memt; 633 #if !defined CBB_PCI_BASE 634 #define CBB_PCI_BASE 0x20000000 635 #endif 636 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 637 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 638 /* cannot allocate memory space */ 639 return; 640 } 641 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 642 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 643 sc->sc_dev.dv_xname, (unsigned long)sock_base, 644 (unsigned long)pci_conf_read(pc, 645 sc->sc_tag, PCI_SOCKBASE))); 646 sc->sc_sockbase = sockbase; 647 #endif 648 sc->sc_flags |= CBB_MEMHMAPPED; 649 } 650 651 /* bus bridge initialization */ 652 pccbb_chipinit(sc); 653 654 /* clear data structure for child device interrupt handlers */ 655 LIST_INIT(&sc->sc_pil); 656 sc->sc_pil_intr_enable = 1; 657 658 /* Map and establish the interrupt. */ 659 if (pci_intr_map(&sc->sc_pa, &ih)) { 660 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 661 return; 662 } 663 intrstr = pci_intr_string(pc, ih); 664 665 /* 666 * XXX pccbbintr should be called under the priority lower 667 * than any other hard interrputs. 668 */ 669 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 670 671 if (sc->sc_ih == NULL) { 672 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 673 if (intrstr != NULL) { 674 printf(" at %s", intrstr); 675 } 676 printf("\n"); 677 return; 678 } 679 680 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 681 powerhook_establish(pccbb_powerhook, sc); 682 683 { 684 u_int32_t sockstat; 685 686 sockstat = bus_space_read_4(sc->sc_base_memt, 687 sc->sc_base_memh, CB_SOCKET_STAT); 688 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 689 sc->sc_flags |= CBB_CARDEXIST; 690 } 691 } 692 693 /* 694 * attach cardbus 695 */ 696 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 697 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 698 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 699 700 /* initialize cbslot_attach */ 701 cba.cba_busname = "cardbus"; 702 cba.cba_iot = sc->sc_iot; 703 cba.cba_memt = sc->sc_memt; 704 cba.cba_dmat = sc->sc_dmat; 705 cba.cba_bus = (busreg >> 8) & 0x0ff; 706 cba.cba_cc = (void *)sc; 707 cba.cba_cf = &pccbb_funcs; 708 cba.cba_intrline = sc->sc_pa.pa_intrline; 709 710 #if rbus 711 cba.cba_rbus_iot = sc->sc_rbus_iot; 712 cba.cba_rbus_memt = sc->sc_rbus_memt; 713 #endif 714 715 cba.cba_cacheline = PCI_CACHELINE(bhlc); 716 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 717 718 if (bootverbose) { 719 printf("%s: cacheline 0x%x lattimer 0x%x\n", 720 sc->sc_dev.dv_xname, cba.cba_cacheline, 721 cba.cba_lattimer); 722 printf("%s: bhlc 0x%x lscp 0x%x\n", 723 sc->sc_dev.dv_xname, bhlc, busreg); 724 } 725 #if defined SHOW_REGS 726 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 727 sc->sc_base_memh); 728 #endif 729 } 730 731 pccbb_pcmcia_attach_setup(sc, &paa); 732 caa.caa_cb_attach = NULL; 733 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 734 caa.caa_cb_attach = &cba; 735 } 736 caa.caa_16_attach = &paa; 737 caa.caa_ph = &sc->sc_pcmcia_h; 738 739 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 740 DPRINTF(("pccbbattach: found cardslot\n")); 741 sc->sc_csc = csc; 742 } 743 744 return; 745 } 746 747 748 749 750 751 /* 752 * static void pccbb_chipinit(struct pccbb_softc *sc) 753 * 754 * This function initialize YENTA chip registers listed below: 755 * 1) PCI command reg, 756 * 2) PCI and CardBus latency timer, 757 * 3) route PCI interrupt, 758 * 4) close all memory and io windows. 759 * 5) turn off bus power. 760 * 6) card detect interrupt on. 761 * 7) clear interrupt 762 */ 763 static void 764 pccbb_chipinit(sc) 765 struct pccbb_softc *sc; 766 { 767 pci_chipset_tag_t pc = sc->sc_pc; 768 pcitag_t tag = sc->sc_tag; 769 bus_space_tag_t bmt = sc->sc_base_memt; 770 bus_space_handle_t bmh = sc->sc_base_memh; 771 pcireg_t reg; 772 773 /* 774 * Set PCI command reg. 775 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 776 */ 777 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 778 /* I believe it is harmless. */ 779 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 780 PCI_COMMAND_MASTER_ENABLE); 781 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 782 783 /* 784 * Set CardBus latency timer. 785 */ 786 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 787 if (PCI_CB_LATENCY(reg) < 0x20) { 788 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 789 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 790 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 791 } 792 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 793 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 794 795 /* 796 * Set PCI latency timer. 797 */ 798 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 799 if (PCI_LATTIMER(reg) < 0x10) { 800 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 801 reg |= (0x10 << PCI_LATTIMER_SHIFT); 802 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 803 } 804 DPRINTF(("PCI latency timer 0x%x (%x)\n", 805 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 806 807 808 /* Route functional interrupts to PCI. */ 809 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 810 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 811 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 812 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 813 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 814 815 switch (sc->sc_chipset) { 816 case CB_TI113X: 817 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 818 /* This bit is shared, but may read as 0 on some chips, so set 819 it explicitly on both functions. */ 820 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 821 /* CSC intr enable */ 822 reg |= PCI113X_CBCTRL_PCI_CSC; 823 /* functional intr prohibit | prohibit ISA routing */ 824 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 825 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 826 break; 827 828 case CB_TI12XX: 829 /* 830 * Some TI 12xx (and [14][45]xx) based pci cards 831 * sometimes have issues with the MFUNC register not 832 * being initialized due to a bad EEPROM on board. 833 * Laptops that this matters on have this register 834 * properly initialized. 835 * 836 * The TI125X parts have a different register. 837 */ 838 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 839 if (reg == 0) { 840 reg &= ~PCI12XX_MFUNC_PIN0; 841 reg |= PCI12XX_MFUNC_PIN0_INTA; 842 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 843 PCI12XX_SYSCTRL_INTRTIE) == 0) { 844 reg &= ~PCI12XX_MFUNC_PIN1; 845 reg |= PCI12XX_MFUNC_PIN1_INTB; 846 } 847 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 848 } 849 /* fallthrough */ 850 851 case CB_TI125X: 852 /* 853 * Disable zoom video. Some machines initialize this 854 * improperly and experience has shown that this helps 855 * prevent strange behavior. 856 */ 857 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 858 859 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 860 reg |= PCI12XX_SYSCTRL_VCCPROT; 861 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 862 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 863 reg |= PCI12XX_CBCTRL_CSC; 864 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 865 break; 866 867 case CB_TOPIC95B: 868 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 869 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 870 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 871 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 872 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 873 sc->sc_dev.dv_xname, reg)); 874 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 875 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 876 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 877 DPRINTF(("0x%x\n", reg)); 878 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 879 break; 880 881 case CB_TOPIC97: 882 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 883 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 884 sc->sc_dev.dv_xname, reg)); 885 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 886 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 887 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 888 reg |= TOPIC97_SLOT_CTRL_PCIINT; 889 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 890 DPRINTF(("0x%x\n", reg)); 891 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 892 /* make sure to assert LV card support bits */ 893 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 894 0x800 + 0x3e, 895 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 896 0x800 + 0x3e) | 0x03); 897 break; 898 } 899 900 /* Close all memory and I/O windows. */ 901 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 903 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 904 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 905 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 906 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 907 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 908 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 909 910 /* reset 16-bit pcmcia bus */ 911 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 912 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 913 914 /* turn off power */ 915 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 916 917 /* CSC Interrupt: Card detect interrupt on */ 918 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 919 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 920 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 921 /* reset interrupt */ 922 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 923 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 924 } 925 926 927 928 929 /* 930 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 931 * struct pcmciabus_attach_args *paa) 932 * 933 * This function attaches 16-bit PCcard bus. 934 */ 935 STATIC void 936 pccbb_pcmcia_attach_setup(sc, paa) 937 struct pccbb_softc *sc; 938 struct pcmciabus_attach_args *paa; 939 { 940 struct pcic_handle *ph = &sc->sc_pcmcia_h; 941 #if rbus 942 rbus_tag_t rb; 943 #endif 944 945 /* initialize pcmcia part in pccbb_softc */ 946 ph->ph_parent = (struct device *)sc; 947 ph->sock = sc->sc_function; 948 ph->flags = 0; 949 ph->shutdown = 0; 950 ph->ih_irq = sc->sc_pa.pa_intrline; 951 ph->ph_bus_t = sc->sc_base_memt; 952 ph->ph_bus_h = sc->sc_base_memh; 953 ph->ph_read = pccbb_pcmcia_read; 954 ph->ph_write = pccbb_pcmcia_write; 955 sc->sc_pct = &pccbb_pcmcia_funcs; 956 957 /* 958 * We need to do a few things here: 959 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 960 * setting the IRQ numbers to 0. 961 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 962 * routing of CSC interrupts (e.g. card removal) to PCI while in 963 * PCMCIA mode. We just leave this set all the time. 964 * 3) Enable card insertion/removal interrupts in case the chip also 965 * needs that while in PCMCIA mode. 966 * 4) Clear any pending CSC interrupt. 967 */ 968 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 969 if (sc->sc_chipset == CB_TI113X) { 970 Pcic_write(ph, PCIC_CSC_INTR, 0); 971 } else { 972 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 973 Pcic_read(ph, PCIC_CSC); 974 } 975 976 /* initialize pcmcia bus attachment */ 977 paa->paa_busname = "pcmcia"; 978 paa->pct = sc->sc_pct; 979 paa->pch = ph; 980 paa->iobase = 0; /* I don't use them */ 981 paa->iosize = 0; 982 #if rbus 983 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 984 paa->iobase = rb->rb_start + rb->rb_offset; 985 paa->iosize = rb->rb_end - rb->rb_start; 986 #endif 987 988 return; 989 } 990 991 #if 0 992 STATIC void 993 pccbb_pcmcia_attach_card(ph) 994 struct pcic_handle *ph; 995 { 996 if (ph->flags & PCIC_FLAG_CARDP) { 997 panic("pccbb_pcmcia_attach_card: already attached"); 998 } 999 1000 /* call the MI attach function */ 1001 pcmcia_card_attach(ph->pcmcia); 1002 1003 ph->flags |= PCIC_FLAG_CARDP; 1004 } 1005 1006 STATIC void 1007 pccbb_pcmcia_detach_card(ph, flags) 1008 struct pcic_handle *ph; 1009 int flags; 1010 { 1011 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1012 panic("pccbb_pcmcia_detach_card: already detached"); 1013 } 1014 1015 ph->flags &= ~PCIC_FLAG_CARDP; 1016 1017 /* call the MI detach function */ 1018 pcmcia_card_detach(ph->pcmcia, flags); 1019 } 1020 #endif 1021 1022 /* 1023 * int pccbbintr(arg) 1024 * void *arg; 1025 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1026 * itself. 1027 */ 1028 int 1029 pccbbintr(arg) 1030 void *arg; 1031 { 1032 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1033 u_int32_t sockevent, sockstate; 1034 bus_space_tag_t memt = sc->sc_base_memt; 1035 bus_space_handle_t memh = sc->sc_base_memh; 1036 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1037 1038 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1039 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1040 Pcic_read(ph, PCIC_CSC); 1041 1042 if (sockevent == 0) { 1043 /* This intr is not for me: it may be for my child devices. */ 1044 if (sc->sc_pil_intr_enable) { 1045 return pccbbintr_function(sc); 1046 } else { 1047 return 0; 1048 } 1049 } 1050 1051 if (sockevent & CB_SOCKET_EVENT_CD) { 1052 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1053 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1054 /* A card should be removed. */ 1055 if (sc->sc_flags & CBB_CARDEXIST) { 1056 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1057 sockevent)); 1058 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1059 sc->sc_flags &= ~CBB_CARDEXIST; 1060 if (sc->sc_csc->sc_status & 1061 CARDSLOT_STATUS_CARD_16) { 1062 #if 0 1063 struct pcic_handle *ph = 1064 &sc->sc_pcmcia_h; 1065 1066 pcmcia_card_deactivate(ph->pcmcia); 1067 pccbb_pcmcia_socket_disable(ph); 1068 pccbb_pcmcia_detach_card(ph, 1069 DETACH_FORCE); 1070 #endif 1071 cardslot_event_throw(sc->sc_csc, 1072 CARDSLOT_EVENT_REMOVAL_16); 1073 } else if (sc->sc_csc->sc_status & 1074 CARDSLOT_STATUS_CARD_CB) { 1075 /* Cardbus intr removed */ 1076 cardslot_event_throw(sc->sc_csc, 1077 CARDSLOT_EVENT_REMOVAL_CB); 1078 } 1079 } else if (sc->sc_flags & CBB_INSERTING) { 1080 sc->sc_flags &= ~CBB_INSERTING; 1081 callout_stop(&sc->sc_insert_ch); 1082 } 1083 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1084 /* 1085 * The pccbbintr may called from powerdown hook when 1086 * the system resumed, to detect the card 1087 * insertion/removal during suspension. 1088 */ 1089 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1090 if (sc->sc_flags & CBB_INSERTING) { 1091 callout_stop(&sc->sc_insert_ch); 1092 } 1093 callout_reset(&sc->sc_insert_ch, hz / 5, 1094 pci113x_insert, sc); 1095 sc->sc_flags |= CBB_INSERTING; 1096 } 1097 } 1098 1099 return (1); 1100 } 1101 1102 /* 1103 * static int pccbbintr_function(struct pccbb_softc *sc) 1104 * 1105 * This function calls each interrupt handler registered at the 1106 * bridge. The interrupt handlers are called in registered order. 1107 */ 1108 static int 1109 pccbbintr_function(sc) 1110 struct pccbb_softc *sc; 1111 { 1112 int retval = 0, val; 1113 struct pccbb_intrhand_list *pil; 1114 int s, splchanged; 1115 1116 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1117 pil = LIST_NEXT(pil, pil_next)) { 1118 /* 1119 * XXX priority change. gross. I use if-else 1120 * sentense instead of switch-case sentense because of 1121 * avoiding duplicate case value error. More than one 1122 * IPL_XXX use same value. It depends on 1123 * implimentation. 1124 */ 1125 splchanged = 1; 1126 if (pil->pil_level == IPL_SERIAL) { 1127 s = splserial(); 1128 } else if (pil->pil_level == IPL_HIGH) { 1129 s = splhigh(); 1130 } else if (pil->pil_level == IPL_CLOCK) { 1131 s = splclock(); 1132 } else if (pil->pil_level == IPL_AUDIO) { 1133 s = splaudio(); 1134 } else if (pil->pil_level == IPL_VM) { 1135 s = splvm(); 1136 } else if (pil->pil_level == IPL_TTY) { 1137 s = spltty(); 1138 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1139 s = splsoftserial(); 1140 } else if (pil->pil_level == IPL_NET) { 1141 s = splnet(); 1142 } else { 1143 s = 0; /* XXX: gcc */ 1144 splchanged = 0; 1145 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1146 } 1147 1148 val = (*pil->pil_func)(pil->pil_arg); 1149 1150 if (splchanged != 0) { 1151 splx(s); 1152 } 1153 1154 retval = retval == 1 ? 1 : 1155 retval == 0 ? val : val != 0 ? val : retval; 1156 } 1157 1158 return retval; 1159 } 1160 1161 static void 1162 pci113x_insert(arg) 1163 void *arg; 1164 { 1165 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1166 u_int32_t sockevent, sockstate; 1167 1168 if (!(sc->sc_flags & CBB_INSERTING)) { 1169 /* We add a card only under inserting state. */ 1170 return; 1171 } 1172 sc->sc_flags &= ~CBB_INSERTING; 1173 1174 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1175 CB_SOCKET_EVENT); 1176 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1177 CB_SOCKET_STAT); 1178 1179 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1180 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1181 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1182 sc->sc_flags |= CBB_CARDEXIST; 1183 /* call pccard interrupt handler here */ 1184 if (sockstate & CB_SOCKET_STAT_16BIT) { 1185 /* 16-bit card found */ 1186 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1187 cardslot_event_throw(sc->sc_csc, 1188 CARDSLOT_EVENT_INSERTION_16); 1189 } else if (sockstate & CB_SOCKET_STAT_CB) { 1190 /* cardbus card found */ 1191 /* cardbus_attach_card(sc->sc_csc); */ 1192 cardslot_event_throw(sc->sc_csc, 1193 CARDSLOT_EVENT_INSERTION_CB); 1194 } else { 1195 /* who are you? */ 1196 } 1197 } else { 1198 callout_reset(&sc->sc_insert_ch, hz / 10, 1199 pci113x_insert, sc); 1200 } 1201 } 1202 1203 #define PCCBB_PCMCIA_OFFSET 0x800 1204 static u_int8_t 1205 pccbb_pcmcia_read(ph, reg) 1206 struct pcic_handle *ph; 1207 int reg; 1208 { 1209 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1210 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1211 1212 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1213 PCCBB_PCMCIA_OFFSET + reg); 1214 } 1215 1216 static void 1217 pccbb_pcmcia_write(ph, reg, val) 1218 struct pcic_handle *ph; 1219 int reg; 1220 u_int8_t val; 1221 { 1222 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1223 val); 1224 1225 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1226 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1227 } 1228 1229 /* 1230 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1231 */ 1232 STATIC int 1233 pccbb_ctrl(ct, command) 1234 cardbus_chipset_tag_t ct; 1235 int command; 1236 { 1237 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1238 1239 switch (command) { 1240 case CARDBUS_CD: 1241 if (2 == pccbb_detect_card(sc)) { 1242 int retval = 0; 1243 int status = cb_detect_voltage(sc); 1244 if (PCCARD_VCC_5V & status) { 1245 retval |= CARDBUS_5V_CARD; 1246 } 1247 if (PCCARD_VCC_3V & status) { 1248 retval |= CARDBUS_3V_CARD; 1249 } 1250 if (PCCARD_VCC_XV & status) { 1251 retval |= CARDBUS_XV_CARD; 1252 } 1253 if (PCCARD_VCC_YV & status) { 1254 retval |= CARDBUS_YV_CARD; 1255 } 1256 return retval; 1257 } else { 1258 return 0; 1259 } 1260 case CARDBUS_RESET: 1261 return cb_reset(sc); 1262 case CARDBUS_IO_ENABLE: /* fallthrough */ 1263 case CARDBUS_IO_DISABLE: /* fallthrough */ 1264 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1265 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1266 case CARDBUS_BM_ENABLE: /* fallthrough */ 1267 case CARDBUS_BM_DISABLE: /* fallthrough */ 1268 /* XXX: I think we don't need to call this function below. */ 1269 return pccbb_cardenable(sc, command); 1270 } 1271 1272 return 0; 1273 } 1274 1275 /* 1276 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1277 * This function returns true when it succeeds and returns false when 1278 * it fails. 1279 */ 1280 STATIC int 1281 pccbb_power(ct, command) 1282 cardbus_chipset_tag_t ct; 1283 int command; 1284 { 1285 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1286 1287 u_int32_t status, sock_ctrl, reg_ctrl; 1288 bus_space_tag_t memt = sc->sc_base_memt; 1289 bus_space_handle_t memh = sc->sc_base_memh; 1290 1291 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1292 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1293 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1294 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1295 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1296 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1297 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1298 "UNKNOWN", 1299 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1300 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1301 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1302 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1303 "UNKNOWN", command)); 1304 1305 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1306 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1307 1308 switch (command & CARDBUS_VCCMASK) { 1309 case CARDBUS_VCC_UC: 1310 break; 1311 case CARDBUS_VCC_5V: 1312 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1313 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1314 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1315 } else { 1316 printf("%s: BAD voltage request: no 5 V card\n", 1317 sc->sc_dev.dv_xname); 1318 return 0; 1319 } 1320 break; 1321 case CARDBUS_VCC_3V: 1322 if (CB_SOCKET_STAT_3VCARD & status) { 1323 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1324 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1325 } else { 1326 printf("%s: BAD voltage request: no 3.3 V card\n", 1327 sc->sc_dev.dv_xname); 1328 return 0; 1329 } 1330 break; 1331 case CARDBUS_VCC_0V: 1332 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1333 break; 1334 default: 1335 return 0; /* power NEVER changed */ 1336 } 1337 1338 switch (command & CARDBUS_VPPMASK) { 1339 case CARDBUS_VPP_UC: 1340 break; 1341 case CARDBUS_VPP_0V: 1342 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1343 break; 1344 case CARDBUS_VPP_VCC: 1345 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1346 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1347 break; 1348 case CARDBUS_VPP_12V: 1349 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1350 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1351 break; 1352 } 1353 1354 #if 0 1355 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1356 #endif 1357 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1358 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1359 1360 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1361 printf 1362 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1363 sc->sc_dev.dv_xname, sock_ctrl, status); 1364 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1365 (command & CARDBUS_VCCMASK) == 1366 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1367 CARDBUS_VCCMASK) == 1368 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1369 CARDBUS_VCCMASK) == 1370 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1371 CARDBUS_VCCMASK) == 1372 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1373 CARDBUS_VCCMASK) == 1374 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1375 CARDBUS_VCCMASK) == 1376 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1377 (command & CARDBUS_VPPMASK) == 1378 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1379 CARDBUS_VPPMASK) == 1380 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1381 CARDBUS_VPPMASK) == 1382 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1383 CARDBUS_VPPMASK) == 1384 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1385 #if 0 1386 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1387 u_int32_t force = 1388 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1389 /* Reset Bad Vcc request */ 1390 force &= ~CB_SOCKET_FORCE_BADVCC; 1391 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1392 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1393 CB_SOCKET_STAT)); 1394 return 1; 1395 } 1396 #endif 1397 return 0; 1398 } 1399 1400 if (sc->sc_chipset == CB_TOPIC97) { 1401 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1402 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1403 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1404 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1405 else 1406 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1407 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1408 } 1409 1410 /* 1411 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1412 * time is 20 ms, some PC-Card bridge requires longer duration. 1413 */ 1414 #if 0 /* XXX called on interrupt context */ 1415 DELAY_MS(300, sc); 1416 #else 1417 delay(300 * 1000); 1418 #endif 1419 1420 return 1; /* power changed correctly */ 1421 } 1422 1423 #if defined CB_PCMCIA_POLL 1424 struct cb_poll_str { 1425 void *arg; 1426 int (*func) __P((void *)); 1427 int level; 1428 pccard_chipset_tag_t ct; 1429 int count; 1430 struct callout poll_ch; 1431 }; 1432 1433 static struct cb_poll_str cb_poll[10]; 1434 static int cb_poll_n = 0; 1435 1436 static void cb_pcmcia_poll __P((void *arg)); 1437 1438 static void 1439 cb_pcmcia_poll(arg) 1440 void *arg; 1441 { 1442 struct cb_poll_str *poll = arg; 1443 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1444 struct pccbb_softc *sc = psc->cpc_parent; 1445 int s; 1446 u_int32_t spsr; /* socket present-state reg */ 1447 1448 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1449 switch (poll->level) { 1450 case IPL_NET: 1451 s = splnet(); 1452 break; 1453 case IPL_BIO: 1454 s = splbio(); 1455 break; 1456 case IPL_TTY: /* fallthrough */ 1457 default: 1458 s = spltty(); 1459 break; 1460 } 1461 1462 spsr = 1463 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1464 CB_SOCKET_STAT); 1465 1466 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1467 if (!(spsr & 0x40)) { /* CINT low */ 1468 #else 1469 if (1) { 1470 #endif 1471 if ((*poll->func) (poll->arg) == 1) { 1472 ++poll->count; 1473 printf("intr: reported from poller, 0x%x\n", spsr); 1474 #if defined LEVEL2 1475 } else { 1476 printf("intr: miss! 0x%x\n", spsr); 1477 #endif 1478 } 1479 } 1480 splx(s); 1481 } 1482 #endif /* defined CB_PCMCIA_POLL */ 1483 1484 /* 1485 * static int pccbb_detect_card(struct pccbb_softc *sc) 1486 * return value: 0 if no card exists. 1487 * 1 if 16-bit card exists. 1488 * 2 if cardbus card exists. 1489 */ 1490 static int 1491 pccbb_detect_card(sc) 1492 struct pccbb_softc *sc; 1493 { 1494 bus_space_handle_t base_memh = sc->sc_base_memh; 1495 bus_space_tag_t base_memt = sc->sc_base_memt; 1496 u_int32_t sockstat = 1497 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1498 int retval = 0; 1499 1500 /* CD1 and CD2 asserted */ 1501 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1502 /* card must be present */ 1503 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1504 /* NOTACARD DEASSERTED */ 1505 if (CB_SOCKET_STAT_CB & sockstat) { 1506 /* CardBus mode */ 1507 retval = 2; 1508 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1509 /* 16-bit mode */ 1510 retval = 1; 1511 } 1512 } 1513 } 1514 return retval; 1515 } 1516 1517 /* 1518 * STATIC int cb_reset(struct pccbb_softc *sc) 1519 * This function resets CardBus card. 1520 */ 1521 STATIC int 1522 cb_reset(sc) 1523 struct pccbb_softc *sc; 1524 { 1525 /* 1526 * Reset Assert at least 20 ms 1527 * Some machines request longer duration. 1528 */ 1529 int reset_duration = 1530 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1531 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1532 1533 /* Reset bit Assert (bit 6 at 0x3E) */ 1534 bcr |= CB_BCR_RESET_ENABLE; 1535 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1536 DELAY_MS(reset_duration, sc); 1537 1538 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1539 /* Reset bit Deassert (bit 6 at 0x3E) */ 1540 bcr &= ~CB_BCR_RESET_ENABLE; 1541 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1542 DELAY_MS(reset_duration, sc); 1543 } 1544 /* No card found on the slot. Keep Reset. */ 1545 return 1; 1546 } 1547 1548 /* 1549 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1550 * This function detect card Voltage. 1551 */ 1552 STATIC int 1553 cb_detect_voltage(sc) 1554 struct pccbb_softc *sc; 1555 { 1556 u_int32_t psr; /* socket present-state reg */ 1557 bus_space_tag_t iot = sc->sc_base_memt; 1558 bus_space_handle_t ioh = sc->sc_base_memh; 1559 int vol = PCCARD_VCC_UKN; /* set 0 */ 1560 1561 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1562 1563 if (0x400u & psr) { 1564 vol |= PCCARD_VCC_5V; 1565 } 1566 if (0x800u & psr) { 1567 vol |= PCCARD_VCC_3V; 1568 } 1569 1570 return vol; 1571 } 1572 1573 STATIC int 1574 cbbprint(aux, pcic) 1575 void *aux; 1576 const char *pcic; 1577 { 1578 /* 1579 struct cbslot_attach_args *cba = aux; 1580 1581 if (cba->cba_slot >= 0) { 1582 aprint_normal(" slot %d", cba->cba_slot); 1583 } 1584 */ 1585 return UNCONF; 1586 } 1587 1588 /* 1589 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1590 * This function enables and disables the card 1591 */ 1592 STATIC int 1593 pccbb_cardenable(sc, function) 1594 struct pccbb_softc *sc; 1595 int function; 1596 { 1597 u_int32_t command = 1598 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1599 1600 DPRINTF(("pccbb_cardenable:")); 1601 switch (function) { 1602 case CARDBUS_IO_ENABLE: 1603 command |= PCI_COMMAND_IO_ENABLE; 1604 break; 1605 case CARDBUS_IO_DISABLE: 1606 command &= ~PCI_COMMAND_IO_ENABLE; 1607 break; 1608 case CARDBUS_MEM_ENABLE: 1609 command |= PCI_COMMAND_MEM_ENABLE; 1610 break; 1611 case CARDBUS_MEM_DISABLE: 1612 command &= ~PCI_COMMAND_MEM_ENABLE; 1613 break; 1614 case CARDBUS_BM_ENABLE: 1615 command |= PCI_COMMAND_MASTER_ENABLE; 1616 break; 1617 case CARDBUS_BM_DISABLE: 1618 command &= ~PCI_COMMAND_MASTER_ENABLE; 1619 break; 1620 default: 1621 return 0; 1622 } 1623 1624 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1625 DPRINTF((" command reg 0x%x\n", command)); 1626 return 1; 1627 } 1628 1629 #if !rbus 1630 /* 1631 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1632 */ 1633 static int 1634 pccbb_io_open(ct, win, start, end) 1635 cardbus_chipset_tag_t ct; 1636 int win; 1637 u_int32_t start, end; 1638 { 1639 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1640 int basereg; 1641 int limitreg; 1642 1643 if ((win < 0) || (win > 2)) { 1644 #if defined DIAGNOSTIC 1645 printf("cardbus_io_open: window out of range %d\n", win); 1646 #endif 1647 return 0; 1648 } 1649 1650 basereg = win * 8 + 0x2c; 1651 limitreg = win * 8 + 0x30; 1652 1653 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1654 start, basereg, end, limitreg)); 1655 1656 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1657 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1658 return 1; 1659 } 1660 1661 /* 1662 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1663 */ 1664 static int 1665 pccbb_io_close(ct, win) 1666 cardbus_chipset_tag_t ct; 1667 int win; 1668 { 1669 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1670 int basereg; 1671 int limitreg; 1672 1673 if ((win < 0) || (win > 2)) { 1674 #if defined DIAGNOSTIC 1675 printf("cardbus_io_close: window out of range %d\n", win); 1676 #endif 1677 return 0; 1678 } 1679 1680 basereg = win * 8 + 0x2c; 1681 limitreg = win * 8 + 0x30; 1682 1683 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1684 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1685 return 1; 1686 } 1687 1688 /* 1689 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1690 */ 1691 static int 1692 pccbb_mem_open(ct, win, start, end) 1693 cardbus_chipset_tag_t ct; 1694 int win; 1695 u_int32_t start, end; 1696 { 1697 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1698 int basereg; 1699 int limitreg; 1700 1701 if ((win < 0) || (win > 2)) { 1702 #if defined DIAGNOSTIC 1703 printf("cardbus_mem_open: window out of range %d\n", win); 1704 #endif 1705 return 0; 1706 } 1707 1708 basereg = win * 8 + 0x1c; 1709 limitreg = win * 8 + 0x20; 1710 1711 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1712 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1713 return 1; 1714 } 1715 1716 /* 1717 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1718 */ 1719 static int 1720 pccbb_mem_close(ct, win) 1721 cardbus_chipset_tag_t ct; 1722 int win; 1723 { 1724 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1725 int basereg; 1726 int limitreg; 1727 1728 if ((win < 0) || (win > 2)) { 1729 #if defined DIAGNOSTIC 1730 printf("cardbus_mem_close: window out of range %d\n", win); 1731 #endif 1732 return 0; 1733 } 1734 1735 basereg = win * 8 + 0x1c; 1736 limitreg = win * 8 + 0x20; 1737 1738 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1739 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1740 return 1; 1741 } 1742 #endif 1743 1744 /* 1745 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1746 * int irq, 1747 * int level, 1748 * int (* func) __P((void *)), 1749 * void *arg) 1750 * 1751 * This function registers an interrupt handler at the bridge, in 1752 * order not to call the interrupt handlers of child devices when 1753 * a card-deletion interrupt occurs. 1754 * 1755 * The arguments irq and level are not used. 1756 */ 1757 static void * 1758 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1759 cardbus_chipset_tag_t ct; 1760 int irq, level; 1761 int (*func) __P((void *)); 1762 void *arg; 1763 { 1764 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1765 1766 return pccbb_intr_establish(sc, irq, level, func, arg); 1767 } 1768 1769 1770 /* 1771 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1772 * void *ih) 1773 * 1774 * This function removes an interrupt handler pointed by ih. 1775 */ 1776 static void 1777 pccbb_cb_intr_disestablish(ct, ih) 1778 cardbus_chipset_tag_t ct; 1779 void *ih; 1780 { 1781 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1782 1783 pccbb_intr_disestablish(sc, ih); 1784 } 1785 1786 1787 void 1788 pccbb_intr_route(sc) 1789 struct pccbb_softc *sc; 1790 { 1791 pcireg_t reg; 1792 1793 /* initialize bridge intr routing */ 1794 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1795 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1796 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1797 1798 switch (sc->sc_chipset) { 1799 case CB_TI113X: 1800 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1801 /* functional intr enabled */ 1802 reg |= PCI113X_CBCTRL_PCI_INTR; 1803 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1804 break; 1805 default: 1806 break; 1807 } 1808 } 1809 1810 /* 1811 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1812 * int irq, 1813 * int level, 1814 * int (* func) __P((void *)), 1815 * void *arg) 1816 * 1817 * This function registers an interrupt handler at the bridge, in 1818 * order not to call the interrupt handlers of child devices when 1819 * a card-deletion interrupt occurs. 1820 * 1821 * The arguments irq is not used because pccbb selects intr vector. 1822 */ 1823 static void * 1824 pccbb_intr_establish(sc, irq, level, func, arg) 1825 struct pccbb_softc *sc; 1826 int irq, level; 1827 int (*func) __P((void *)); 1828 void *arg; 1829 { 1830 struct pccbb_intrhand_list *pil, *newpil; 1831 1832 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1833 1834 if (LIST_EMPTY(&sc->sc_pil)) { 1835 pccbb_intr_route(sc); 1836 } 1837 1838 /* 1839 * Allocate a room for interrupt handler structure. 1840 */ 1841 if (NULL == (newpil = 1842 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1843 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1844 return NULL; 1845 } 1846 1847 newpil->pil_func = func; 1848 newpil->pil_arg = arg; 1849 newpil->pil_level = level; 1850 1851 if (LIST_EMPTY(&sc->sc_pil)) { 1852 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1853 } else { 1854 for (pil = LIST_FIRST(&sc->sc_pil); 1855 LIST_NEXT(pil, pil_next) != NULL; 1856 pil = LIST_NEXT(pil, pil_next)); 1857 LIST_INSERT_AFTER(pil, newpil, pil_next); 1858 } 1859 1860 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1861 LIST_FIRST(&sc->sc_pil))); 1862 1863 return newpil; 1864 } 1865 1866 /* 1867 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1868 * void *ih) 1869 * 1870 * This function removes an interrupt handler pointed by ih. ih 1871 * should be the value returned by cardbus_intr_establish() or 1872 * NULL. 1873 * 1874 * When ih is NULL, this function will do nothing. 1875 */ 1876 static void 1877 pccbb_intr_disestablish(sc, ih) 1878 struct pccbb_softc *sc; 1879 void *ih; 1880 { 1881 struct pccbb_intrhand_list *pil; 1882 pcireg_t reg; 1883 1884 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1885 LIST_FIRST(&sc->sc_pil))); 1886 1887 if (ih == NULL) { 1888 /* intr handler is not set */ 1889 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1890 return; 1891 } 1892 1893 #ifdef DIAGNOSTIC 1894 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1895 pil = LIST_NEXT(pil, pil_next)) { 1896 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1897 if (pil == ih) { 1898 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1899 break; 1900 } 1901 } 1902 if (pil == NULL) { 1903 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1904 sc->sc_dev.dv_xname, ih); 1905 } 1906 #endif 1907 1908 pil = (struct pccbb_intrhand_list *)ih; 1909 LIST_REMOVE(pil, pil_next); 1910 free(pil, M_DEVBUF); 1911 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1912 1913 if (LIST_EMPTY(&sc->sc_pil)) { 1914 /* No interrupt handlers */ 1915 1916 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1917 1918 /* stop routing PCI intr */ 1919 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1920 reg |= CB_BCR_INTR_IREQ_ENABLE; 1921 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1922 1923 switch (sc->sc_chipset) { 1924 case CB_TI113X: 1925 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1926 /* functional intr disabled */ 1927 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1928 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1929 break; 1930 default: 1931 break; 1932 } 1933 } 1934 } 1935 1936 #if defined SHOW_REGS 1937 static void 1938 cb_show_regs(pc, tag, memt, memh) 1939 pci_chipset_tag_t pc; 1940 pcitag_t tag; 1941 bus_space_tag_t memt; 1942 bus_space_handle_t memh; 1943 { 1944 int i; 1945 printf("PCI config regs:"); 1946 for (i = 0; i < 0x50; i += 4) { 1947 if (i % 16 == 0) { 1948 printf("\n 0x%02x:", i); 1949 } 1950 printf(" %08x", pci_conf_read(pc, tag, i)); 1951 } 1952 for (i = 0x80; i < 0xb0; i += 4) { 1953 if (i % 16 == 0) { 1954 printf("\n 0x%02x:", i); 1955 } 1956 printf(" %08x", pci_conf_read(pc, tag, i)); 1957 } 1958 1959 if (memh == 0) { 1960 printf("\n"); 1961 return; 1962 } 1963 1964 printf("\nsocket regs:"); 1965 for (i = 0; i <= 0x10; i += 0x04) { 1966 printf(" %08x", bus_space_read_4(memt, memh, i)); 1967 } 1968 printf("\nExCA regs:"); 1969 for (i = 0; i < 0x08; ++i) { 1970 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1971 } 1972 printf("\n"); 1973 return; 1974 } 1975 #endif 1976 1977 /* 1978 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1979 * int busno, int devno, int function) 1980 * This is the function to make a tag to access config space of 1981 * a CardBus Card. It works same as pci_conf_read. 1982 */ 1983 static cardbustag_t 1984 pccbb_make_tag(cc, busno, devno, function) 1985 cardbus_chipset_tag_t cc; 1986 int busno, devno, function; 1987 { 1988 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1989 1990 return pci_make_tag(sc->sc_pc, busno, devno, function); 1991 } 1992 1993 static void 1994 pccbb_free_tag(cc, tag) 1995 cardbus_chipset_tag_t cc; 1996 cardbustag_t tag; 1997 { 1998 } 1999 2000 /* 2001 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 2002 * cardbustag_t tag, int offset) 2003 * This is the function to read the config space of a CardBus Card. 2004 * It works same as pci_conf_read. 2005 */ 2006 static cardbusreg_t 2007 pccbb_conf_read(cc, tag, offset) 2008 cardbus_chipset_tag_t cc; 2009 cardbustag_t tag; 2010 int offset; /* register offset */ 2011 { 2012 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2013 2014 return pci_conf_read(sc->sc_pc, tag, offset); 2015 } 2016 2017 /* 2018 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2019 * int offs, cardbusreg_t val) 2020 * This is the function to write the config space of a CardBus Card. 2021 * It works same as pci_conf_write. 2022 */ 2023 static void 2024 pccbb_conf_write(cc, tag, reg, val) 2025 cardbus_chipset_tag_t cc; 2026 cardbustag_t tag; 2027 int reg; /* register offset */ 2028 cardbusreg_t val; 2029 { 2030 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2031 2032 pci_conf_write(sc->sc_pc, tag, reg, val); 2033 } 2034 2035 #if 0 2036 STATIC int 2037 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2038 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2039 int speed, int flags, 2040 bus_space_handle_t * iohp) 2041 #endif 2042 /* 2043 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2044 * bus_addr_t start, bus_size_t size, 2045 * bus_size_t align, 2046 * struct pcmcia_io_handle *pcihp 2047 * 2048 * This function only allocates I/O region for pccard. This function 2049 * never maps the allocated region to pccard I/O area. 2050 * 2051 * XXX: The interface of this function is not very good, I believe. 2052 */ 2053 STATIC int 2054 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2055 pcmcia_chipset_handle_t pch; 2056 bus_addr_t start; /* start address */ 2057 bus_size_t size; 2058 bus_size_t align; 2059 struct pcmcia_io_handle *pcihp; 2060 { 2061 struct pcic_handle *ph = (struct pcic_handle *)pch; 2062 bus_addr_t ioaddr; 2063 int flags = 0; 2064 bus_space_tag_t iot; 2065 bus_space_handle_t ioh; 2066 bus_addr_t mask; 2067 #if rbus 2068 rbus_tag_t rb; 2069 #endif 2070 if (align == 0) { 2071 align = size; /* XXX: funny??? */ 2072 } 2073 2074 if (start != 0) { 2075 /* XXX: assume all card decode lower 10 bits by its hardware */ 2076 mask = 0x3ff; 2077 /* enforce to use only masked address */ 2078 start &= mask; 2079 } else { 2080 /* 2081 * calculate mask: 2082 * 1. get the most significant bit of size (call it msb). 2083 * 2. compare msb with the value of size. 2084 * 3. if size is larger, shift msb left once. 2085 * 4. obtain mask value to decrement msb. 2086 */ 2087 bus_size_t size_tmp = size; 2088 int shifts = 0; 2089 2090 mask = 1; 2091 while (size_tmp) { 2092 ++shifts; 2093 size_tmp >>= 1; 2094 } 2095 mask = (1 << shifts); 2096 if (mask < size) { 2097 mask <<= 1; 2098 } 2099 --mask; 2100 } 2101 2102 /* 2103 * Allocate some arbitrary I/O space. 2104 */ 2105 2106 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2107 2108 #if rbus 2109 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2110 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2111 return 1; 2112 } 2113 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2114 (u_long) ioaddr, (u_long) size)); 2115 #else 2116 if (start) { 2117 ioaddr = start; 2118 if (bus_space_map(iot, start, size, 0, &ioh)) { 2119 return 1; 2120 } 2121 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2122 (u_long) ioaddr, (u_long) size)); 2123 } else { 2124 flags |= PCMCIA_IO_ALLOCATED; 2125 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2126 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2127 size, align, 0, 0, &ioaddr, &ioh)) { 2128 /* No room be able to be get. */ 2129 return 1; 2130 } 2131 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2132 (u_long) ioaddr, (u_long) size)); 2133 } 2134 #endif 2135 2136 pcihp->iot = iot; 2137 pcihp->ioh = ioh; 2138 pcihp->addr = ioaddr; 2139 pcihp->size = size; 2140 pcihp->flags = flags; 2141 2142 return 0; 2143 } 2144 2145 /* 2146 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2147 * struct pcmcia_io_handle *pcihp) 2148 * 2149 * This function only frees I/O region for pccard. 2150 * 2151 * XXX: The interface of this function is not very good, I believe. 2152 */ 2153 void 2154 pccbb_pcmcia_io_free(pch, pcihp) 2155 pcmcia_chipset_handle_t pch; 2156 struct pcmcia_io_handle *pcihp; 2157 { 2158 #if !rbus 2159 bus_space_tag_t iot = pcihp->iot; 2160 #endif 2161 bus_space_handle_t ioh = pcihp->ioh; 2162 bus_size_t size = pcihp->size; 2163 2164 #if rbus 2165 struct pccbb_softc *sc = 2166 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2167 rbus_tag_t rb = sc->sc_rbus_iot; 2168 2169 rbus_space_free(rb, ioh, size, NULL); 2170 #else 2171 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2172 bus_space_free(iot, ioh, size); 2173 else 2174 bus_space_unmap(iot, ioh, size); 2175 #endif 2176 } 2177 2178 /* 2179 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2180 * bus_addr_t offset, bus_size_t size, 2181 * struct pcmcia_io_handle *pcihp, 2182 * int *windowp) 2183 * 2184 * This function maps the allocated I/O region to pccard. This function 2185 * never allocates any I/O region for pccard I/O area. I don't 2186 * understand why the original authors of pcmciabus separated alloc and 2187 * map. I believe the two must be unite. 2188 * 2189 * XXX: no wait timing control? 2190 */ 2191 int 2192 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2193 pcmcia_chipset_handle_t pch; 2194 int width; 2195 bus_addr_t offset; 2196 bus_size_t size; 2197 struct pcmcia_io_handle *pcihp; 2198 int *windowp; 2199 { 2200 struct pcic_handle *ph = (struct pcic_handle *)pch; 2201 bus_addr_t ioaddr = pcihp->addr + offset; 2202 int i, win; 2203 #if defined CBB_DEBUG 2204 static char *width_names[] = { "dynamic", "io8", "io16" }; 2205 #endif 2206 2207 /* Sanity check I/O handle. */ 2208 2209 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2210 panic("pccbb_pcmcia_io_map iot is bogus"); 2211 } 2212 2213 /* XXX Sanity check offset/size. */ 2214 2215 win = -1; 2216 for (i = 0; i < PCIC_IO_WINS; i++) { 2217 if ((ph->ioalloc & (1 << i)) == 0) { 2218 win = i; 2219 ph->ioalloc |= (1 << i); 2220 break; 2221 } 2222 } 2223 2224 if (win == -1) { 2225 return 1; 2226 } 2227 2228 *windowp = win; 2229 2230 /* XXX this is pretty gross */ 2231 2232 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2233 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2234 2235 /* XXX wtf is this doing here? */ 2236 2237 #if 0 2238 printf(" port 0x%lx", (u_long) ioaddr); 2239 if (size > 1) { 2240 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2241 } 2242 #endif 2243 2244 ph->io[win].addr = ioaddr; 2245 ph->io[win].size = size; 2246 ph->io[win].width = width; 2247 2248 /* actual dirty register-value changing in the function below. */ 2249 pccbb_pcmcia_do_io_map(ph, win); 2250 2251 return 0; 2252 } 2253 2254 /* 2255 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2256 * 2257 * This function changes register-value to map I/O region for pccard. 2258 */ 2259 static void 2260 pccbb_pcmcia_do_io_map(ph, win) 2261 struct pcic_handle *ph; 2262 int win; 2263 { 2264 static u_int8_t pcic_iowidth[3] = { 2265 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2266 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2267 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2268 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2269 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2270 }; 2271 2272 #define PCIC_SIA_START_LOW 0 2273 #define PCIC_SIA_START_HIGH 1 2274 #define PCIC_SIA_STOP_LOW 2 2275 #define PCIC_SIA_STOP_HIGH 3 2276 2277 int regbase_win = 0x8 + win * 0x04; 2278 u_int8_t ioctl, enable; 2279 2280 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2281 "width %d\n", win, (unsigned long)ph->io[win].addr, 2282 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2283 2284 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2285 ph->io[win].addr & 0xff); 2286 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2287 (ph->io[win].addr >> 8) & 0xff); 2288 2289 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2290 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2291 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2292 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2293 2294 ioctl = Pcic_read(ph, PCIC_IOCTL); 2295 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2296 switch (win) { 2297 case 0: 2298 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2299 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2300 PCIC_IOCTL_IO0_DATASIZE_MASK); 2301 ioctl |= pcic_iowidth[ph->io[win].width]; 2302 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2303 break; 2304 case 1: 2305 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2306 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2307 PCIC_IOCTL_IO1_DATASIZE_MASK); 2308 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2309 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2310 break; 2311 } 2312 Pcic_write(ph, PCIC_IOCTL, ioctl); 2313 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2314 #if defined CBB_DEBUG 2315 { 2316 u_int8_t start_low = 2317 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2318 u_int8_t start_high = 2319 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2320 u_int8_t stop_low = 2321 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2322 u_int8_t stop_high = 2323 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2324 printf 2325 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2326 start_low, start_high, stop_low, stop_high, ioctl, enable); 2327 } 2328 #endif 2329 } 2330 2331 /* 2332 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2333 * 2334 * This function unmaps I/O region. No return value. 2335 */ 2336 STATIC void 2337 pccbb_pcmcia_io_unmap(pch, win) 2338 pcmcia_chipset_handle_t pch; 2339 int win; 2340 { 2341 struct pcic_handle *ph = (struct pcic_handle *)pch; 2342 int reg; 2343 2344 if (win >= PCIC_IO_WINS || win < 0) { 2345 panic("pccbb_pcmcia_io_unmap: window out of range"); 2346 } 2347 2348 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2349 switch (win) { 2350 case 0: 2351 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2352 break; 2353 case 1: 2354 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2355 break; 2356 } 2357 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2358 2359 ph->ioalloc &= ~(1 << win); 2360 } 2361 2362 /* 2363 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2364 * 2365 * This function enables the card. All information is stored in 2366 * the first argument, pcmcia_chipset_handle_t. 2367 */ 2368 static int 2369 pccbb_pcmcia_wait_ready(ph) 2370 struct pcic_handle *ph; 2371 { 2372 u_char stat; 2373 int i; 2374 2375 DPRINTF(("entering pccbb_pcmcia_wait_ready: status 0x%02x\n", 2376 Pcic_read(ph, PCIC_IF_STATUS))); 2377 2378 for (i = 0; i < 2000; i++) { 2379 stat = Pcic_read(ph, PCIC_IF_STATUS); 2380 if (stat & PCIC_IF_STATUS_READY) 2381 return 1; 2382 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2383 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2384 return 0; 2385 DELAY_MS(2, ph->ph_parent); 2386 #ifdef CBB_DEBUG 2387 if ((i > 1000) && (i % 25 == 24)) 2388 printf("."); 2389 #endif 2390 } 2391 2392 #ifdef DIAGNOSTIC 2393 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2394 Pcic_read(ph, PCIC_IF_STATUS)); 2395 #endif 2396 2397 return 0; 2398 } 2399 2400 /* 2401 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2402 * 2403 * This function enables the card. All information is stored in 2404 * the first argument, pcmcia_chipset_handle_t. 2405 */ 2406 STATIC void 2407 pccbb_pcmcia_socket_enable(pch) 2408 pcmcia_chipset_handle_t pch; 2409 { 2410 struct pcic_handle *ph = (struct pcic_handle *)pch; 2411 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2412 int cardtype, win; 2413 u_int8_t power, intr; 2414 pcireg_t spsr; 2415 int voltage; 2416 2417 /* this bit is mostly stolen from pcic_attach_card */ 2418 2419 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2420 2421 /* get card Vcc info */ 2422 2423 spsr = 2424 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2425 CB_SOCKET_STAT); 2426 if (spsr & CB_SOCKET_STAT_5VCARD) { 2427 DPRINTF(("5V card\n")); 2428 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2429 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2430 DPRINTF(("3V card\n")); 2431 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2432 } else { 2433 printf("?V card, 0x%x\n", spsr); /* XXX */ 2434 return; 2435 } 2436 2437 /* disable socket: negate output enable bit and power off */ 2438 2439 power = 0; 2440 Pcic_write(ph, PCIC_PWRCTL, power); 2441 2442 /* power down the socket to reset it, clear the card reset pin */ 2443 2444 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2445 2446 /* 2447 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2448 * we are changing Vcc (Toff). 2449 */ 2450 /* delay(300*1000); too much */ 2451 2452 /* assert reset bit */ 2453 intr = Pcic_read(ph, PCIC_INTR); 2454 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2455 Pcic_write(ph, PCIC_INTR, intr); 2456 2457 /* power up the socket */ 2458 power = Pcic_read(ph, PCIC_PWRCTL); 2459 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 2460 pccbb_power(sc, voltage); 2461 2462 /* now output enable */ 2463 power = Pcic_read(ph, PCIC_PWRCTL); 2464 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2465 2466 if (pccbb_power(sc, voltage) == 0) { 2467 power &= PCIC_PWRCTL_OE; 2468 Pcic_write(ph, PCIC_PWRCTL, power); 2469 intr |= PCIC_INTR_RESET; 2470 Pcic_write(ph, PCIC_INTR, intr); 2471 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2472 return; 2473 } 2474 2475 /* 2476 * hold RESET at least 20 ms: the spec says only 10 us is 2477 * enough, but TI1130 requires at least 20 ms. 2478 */ 2479 #if 0 /* XXX called on interrupt context */ 2480 DELAY_MS(20, sc); 2481 #else 2482 delay(20 * 1000); 2483 #endif 2484 2485 /* clear the reset flag */ 2486 2487 intr |= PCIC_INTR_RESET; 2488 Pcic_write(ph, PCIC_INTR, intr); 2489 2490 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2491 2492 #if 0 /* XXX called on interrupt context */ 2493 DELAY_MS(20, sc); 2494 #else 2495 delay(20 * 1000); 2496 #endif 2497 2498 /* wait for the chip to finish initializing */ 2499 2500 if (pccbb_pcmcia_wait_ready(ph) == 0) { 2501 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2502 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2503 return; 2504 } 2505 2506 /* zero out the address windows */ 2507 2508 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2509 2510 /* set the card type */ 2511 2512 cardtype = pcmcia_card_gettype(ph->pcmcia); 2513 2514 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2515 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2516 Pcic_write(ph, PCIC_INTR, intr); 2517 2518 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2519 ph->ph_parent->dv_xname, ph->sock, 2520 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2521 2522 /* reinstall all the memory and io mappings */ 2523 2524 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2525 if (ph->memalloc & (1 << win)) { 2526 pccbb_pcmcia_do_mem_map(ph, win); 2527 } 2528 } 2529 2530 for (win = 0; win < PCIC_IO_WINS; ++win) { 2531 if (ph->ioalloc & (1 << win)) { 2532 pccbb_pcmcia_do_io_map(ph, win); 2533 } 2534 } 2535 } 2536 2537 /* 2538 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2539 * 2540 * This function disables the card. All information is stored in 2541 * the first argument, pcmcia_chipset_handle_t. 2542 */ 2543 STATIC void 2544 pccbb_pcmcia_socket_disable(pch) 2545 pcmcia_chipset_handle_t pch; 2546 { 2547 struct pcic_handle *ph = (struct pcic_handle *)pch; 2548 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2549 u_int8_t power, intr; 2550 2551 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2552 2553 /* reset signal asserting... */ 2554 2555 intr = Pcic_read(ph, PCIC_INTR); 2556 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2557 Pcic_write(ph, PCIC_INTR, intr); 2558 delay(2 * 1000); 2559 2560 /* power down the socket */ 2561 power = Pcic_read(ph, PCIC_PWRCTL); 2562 power &= ~PCIC_PWRCTL_OE; 2563 Pcic_write(ph, PCIC_PWRCTL, power); 2564 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2565 /* 2566 * wait 300ms until power fails (Tpf). 2567 */ 2568 #if 0 /* XXX called on interrupt context */ 2569 DELAY_MS(300, sc); 2570 #else 2571 delay(300 * 1000); 2572 #endif 2573 } 2574 2575 /* 2576 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2577 * 2578 * This function detects whether a card is in the slot or not. 2579 * If a card is inserted, return 1. Otherwise, return 0. 2580 */ 2581 STATIC int 2582 pccbb_pcmcia_card_detect(pch) 2583 pcmcia_chipset_handle_t pch; 2584 { 2585 struct pcic_handle *ph = (struct pcic_handle *)pch; 2586 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2587 2588 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2589 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2590 } 2591 2592 #if 0 2593 STATIC int 2594 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2595 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2596 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2597 #endif 2598 /* 2599 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2600 * bus_size_t size, 2601 * struct pcmcia_mem_handle *pcmhp) 2602 * 2603 * This function only allocates memory region for pccard. This 2604 * function never maps the allocated region to pccard memory area. 2605 * 2606 * XXX: Why the argument of start address is not in? 2607 */ 2608 STATIC int 2609 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2610 pcmcia_chipset_handle_t pch; 2611 bus_size_t size; 2612 struct pcmcia_mem_handle *pcmhp; 2613 { 2614 struct pcic_handle *ph = (struct pcic_handle *)pch; 2615 bus_space_handle_t memh; 2616 bus_addr_t addr; 2617 bus_size_t sizepg; 2618 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2619 #if rbus 2620 rbus_tag_t rb; 2621 #endif 2622 2623 /* Check that the card is still there. */ 2624 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2625 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2626 return 1; 2627 2628 /* out of sc->memh, allocate as many pages as necessary */ 2629 2630 /* convert size to PCIC pages */ 2631 /* 2632 * This is not enough; when the requested region is on the page 2633 * boundaries, this may calculate wrong result. 2634 */ 2635 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2636 #if 0 2637 if (sizepg > PCIC_MAX_MEM_PAGES) { 2638 return 1; 2639 } 2640 #endif 2641 2642 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2643 return 1; 2644 } 2645 2646 addr = 0; /* XXX gcc -Wuninitialized */ 2647 2648 #if rbus 2649 rb = sc->sc_rbus_memt; 2650 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2651 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2652 &addr, &memh)) { 2653 return 1; 2654 } 2655 #else 2656 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2657 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2658 0, /* boundary */ 2659 0, /* flags */ 2660 &addr, &memh)) { 2661 return 1; 2662 } 2663 #endif 2664 2665 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2666 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2667 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2668 2669 pcmhp->memt = sc->sc_memt; 2670 pcmhp->memh = memh; 2671 pcmhp->addr = addr; 2672 pcmhp->size = size; 2673 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2674 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2675 pcmhp->mhandle = 0; 2676 /* No offset??? Funny. */ 2677 2678 return 0; 2679 } 2680 2681 /* 2682 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2683 * struct pcmcia_mem_handle *pcmhp) 2684 * 2685 * This function release the memory space allocated by the function 2686 * pccbb_pcmcia_mem_alloc(). 2687 */ 2688 STATIC void 2689 pccbb_pcmcia_mem_free(pch, pcmhp) 2690 pcmcia_chipset_handle_t pch; 2691 struct pcmcia_mem_handle *pcmhp; 2692 { 2693 #if rbus 2694 struct pcic_handle *ph = (struct pcic_handle *)pch; 2695 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2696 2697 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2698 #else 2699 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2700 #endif 2701 } 2702 2703 /* 2704 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2705 * 2706 * This function release the memory space allocated by the function 2707 * pccbb_pcmcia_mem_alloc(). 2708 */ 2709 STATIC void 2710 pccbb_pcmcia_do_mem_map(ph, win) 2711 struct pcic_handle *ph; 2712 int win; 2713 { 2714 int regbase_win; 2715 bus_addr_t phys_addr; 2716 bus_addr_t phys_end; 2717 2718 #define PCIC_SMM_START_LOW 0 2719 #define PCIC_SMM_START_HIGH 1 2720 #define PCIC_SMM_STOP_LOW 2 2721 #define PCIC_SMM_STOP_HIGH 3 2722 #define PCIC_CMA_LOW 4 2723 #define PCIC_CMA_HIGH 5 2724 2725 u_int8_t start_low, start_high = 0; 2726 u_int8_t stop_low, stop_high; 2727 u_int8_t off_low, off_high; 2728 u_int8_t mem_window; 2729 int reg; 2730 2731 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2732 int mem8 = 2733 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2734 || (kind == PCMCIA_MEM_ATTR); 2735 2736 regbase_win = 0x10 + win * 0x08; 2737 2738 phys_addr = ph->mem[win].addr; 2739 phys_end = phys_addr + ph->mem[win].size; 2740 2741 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2742 (unsigned long)phys_addr, (unsigned long)phys_end, 2743 (unsigned long)ph->mem[win].offset)); 2744 2745 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2746 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2747 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2748 2749 /* bit 19:12 */ 2750 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2751 /* bit 23:20 and bit 7 on */ 2752 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2753 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2754 /* bit 31:24, for 32-bit address */ 2755 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2756 2757 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2758 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2759 2760 if (((struct pccbb_softc *)ph-> 2761 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2762 Pcic_write(ph, 0x40 + win, mem_window); 2763 } 2764 2765 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2766 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2767 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2768 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2769 2770 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2771 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2772 2773 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2774 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2775 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2776 | ((kind == PCMCIA_MEM_ATTR) ? 2777 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2778 2779 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2780 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2781 2782 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2783 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2784 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2785 2786 #if defined CBB_DEBUG 2787 { 2788 int r1, r2, r3, r4, r5, r6, r7 = 0; 2789 2790 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2791 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2792 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2793 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2794 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2795 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2796 if (((struct pccbb_softc *)(ph-> 2797 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2798 r7 = Pcic_read(ph, 0x40 + win); 2799 } 2800 2801 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2802 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2803 if (((struct pccbb_softc *)(ph-> 2804 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2805 DPRINTF((" %02x", r7)); 2806 } 2807 DPRINTF(("\n")); 2808 } 2809 #endif 2810 } 2811 2812 /* 2813 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2814 * bus_addr_t card_addr, bus_size_t size, 2815 * struct pcmcia_mem_handle *pcmhp, 2816 * bus_addr_t *offsetp, int *windowp) 2817 * 2818 * This function maps memory space allocated by the function 2819 * pccbb_pcmcia_mem_alloc(). 2820 */ 2821 STATIC int 2822 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2823 pcmcia_chipset_handle_t pch; 2824 int kind; 2825 bus_addr_t card_addr; 2826 bus_size_t size; 2827 struct pcmcia_mem_handle *pcmhp; 2828 bus_addr_t *offsetp; 2829 int *windowp; 2830 { 2831 struct pcic_handle *ph = (struct pcic_handle *)pch; 2832 bus_addr_t busaddr; 2833 long card_offset; 2834 int win; 2835 2836 /* Check that the card is still there. */ 2837 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2838 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2839 return 1; 2840 2841 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2842 if ((ph->memalloc & (1 << win)) == 0) { 2843 ph->memalloc |= (1 << win); 2844 break; 2845 } 2846 } 2847 2848 if (win == PCIC_MEM_WINS) { 2849 return 1; 2850 } 2851 2852 *windowp = win; 2853 2854 /* XXX this is pretty gross */ 2855 2856 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2857 panic("pccbb_pcmcia_mem_map memt is bogus"); 2858 } 2859 2860 busaddr = pcmhp->addr; 2861 2862 /* 2863 * compute the address offset to the pcmcia address space for the 2864 * pcic. this is intentionally signed. The masks and shifts below 2865 * will cause TRT to happen in the pcic registers. Deal with making 2866 * sure the address is aligned, and return the alignment offset. 2867 */ 2868 2869 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2870 card_addr -= *offsetp; 2871 2872 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2873 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2874 (u_long) card_addr)); 2875 2876 /* 2877 * include the offset in the size, and decrement size by one, since 2878 * the hw wants start/stop 2879 */ 2880 size += *offsetp - 1; 2881 2882 card_offset = (((long)card_addr) - ((long)busaddr)); 2883 2884 ph->mem[win].addr = busaddr; 2885 ph->mem[win].size = size; 2886 ph->mem[win].offset = card_offset; 2887 ph->mem[win].kind = kind; 2888 2889 pccbb_pcmcia_do_mem_map(ph, win); 2890 2891 return 0; 2892 } 2893 2894 /* 2895 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2896 * int window) 2897 * 2898 * This function unmaps memory space which mapped by the function 2899 * pccbb_pcmcia_mem_map(). 2900 */ 2901 STATIC void 2902 pccbb_pcmcia_mem_unmap(pch, window) 2903 pcmcia_chipset_handle_t pch; 2904 int window; 2905 { 2906 struct pcic_handle *ph = (struct pcic_handle *)pch; 2907 int reg; 2908 2909 if (window >= PCIC_MEM_WINS) { 2910 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2911 } 2912 2913 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2914 reg &= ~(1 << window); 2915 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2916 2917 ph->memalloc &= ~(1 << window); 2918 } 2919 2920 #if defined PCCBB_PCMCIA_POLL 2921 struct pccbb_poll_str { 2922 void *arg; 2923 int (*func) __P((void *)); 2924 int level; 2925 struct pcic_handle *ph; 2926 int count; 2927 int num; 2928 struct callout poll_ch; 2929 }; 2930 2931 static struct pccbb_poll_str pccbb_poll[10]; 2932 static int pccbb_poll_n = 0; 2933 2934 static void pccbb_pcmcia_poll __P((void *arg)); 2935 2936 static void 2937 pccbb_pcmcia_poll(arg) 2938 void *arg; 2939 { 2940 struct pccbb_poll_str *poll = arg; 2941 struct pcic_handle *ph = poll->ph; 2942 struct pccbb_softc *sc = ph->sc; 2943 int s; 2944 u_int32_t spsr; /* socket present-state reg */ 2945 2946 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2947 switch (poll->level) { 2948 case IPL_NET: 2949 s = splnet(); 2950 break; 2951 case IPL_BIO: 2952 s = splbio(); 2953 break; 2954 case IPL_TTY: /* fallthrough */ 2955 default: 2956 s = spltty(); 2957 break; 2958 } 2959 2960 spsr = 2961 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2962 CB_SOCKET_STAT); 2963 2964 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2965 if (!(spsr & 0x40)) /* CINT low */ 2966 #else 2967 if (1) 2968 #endif 2969 { 2970 if ((*poll->func) (poll->arg) > 0) { 2971 ++poll->count; 2972 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2973 #if defined LEVEL2 2974 } else { 2975 printf("intr: miss! 0x%x\n", spsr); 2976 #endif 2977 } 2978 } 2979 splx(s); 2980 } 2981 #endif /* defined CB_PCMCIA_POLL */ 2982 2983 /* 2984 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2985 * struct pcmcia_function *pf, 2986 * int ipl, 2987 * int (*func)(void *), 2988 * void *arg); 2989 * 2990 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2991 */ 2992 STATIC void * 2993 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2994 pcmcia_chipset_handle_t pch; 2995 struct pcmcia_function *pf; 2996 int ipl; 2997 int (*func) __P((void *)); 2998 void *arg; 2999 { 3000 struct pcic_handle *ph = (struct pcic_handle *)pch; 3001 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3002 3003 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3004 /* what should I do? */ 3005 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3006 DPRINTF(("%s does not provide edge nor pulse " 3007 "interrupt\n", sc->sc_dev.dv_xname)); 3008 return NULL; 3009 } 3010 /* 3011 * XXX Noooooo! The interrupt flag must set properly!! 3012 * dumb pcmcia driver!! 3013 */ 3014 } 3015 3016 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3017 } 3018 3019 /* 3020 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3021 * void *ih) 3022 * 3023 * This function disables PC-Card interrupt. 3024 */ 3025 STATIC void 3026 pccbb_pcmcia_intr_disestablish(pch, ih) 3027 pcmcia_chipset_handle_t pch; 3028 void *ih; 3029 { 3030 struct pcic_handle *ph = (struct pcic_handle *)pch; 3031 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3032 3033 pccbb_intr_disestablish(sc, ih); 3034 } 3035 3036 #if rbus 3037 /* 3038 * static int 3039 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3040 * bus_addr_t addr, bus_size_t size, 3041 * bus_addr_t mask, bus_size_t align, 3042 * int flags, bus_addr_t *addrp; 3043 * bus_space_handle_t *bshp) 3044 * 3045 * This function allocates a portion of memory or io space for 3046 * clients. This function is called from CardBus card drivers. 3047 */ 3048 static int 3049 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3050 cardbus_chipset_tag_t ct; 3051 rbus_tag_t rb; 3052 bus_addr_t addr; 3053 bus_size_t size; 3054 bus_addr_t mask; 3055 bus_size_t align; 3056 int flags; 3057 bus_addr_t *addrp; 3058 bus_space_handle_t *bshp; 3059 { 3060 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3061 3062 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3063 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3064 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3065 3066 if (align == 0) { 3067 align = size; 3068 } 3069 3070 if (rb->rb_bt == sc->sc_memt) { 3071 if (align < 16) { 3072 return 1; 3073 } 3074 /* 3075 * XXX: align more than 0x1000 to avoid overwrapping 3076 * memory windows for two or more devices. 0x1000 3077 * means memory window's granularity. 3078 * 3079 * Two or more devices should be able to share same 3080 * memory window region. However, overrapping memory 3081 * window is not good because some devices, such as 3082 * 3Com 3C575[BC], have a broken address decoder and 3083 * intrude other's memory region. 3084 */ 3085 if (align < 0x1000) { 3086 align = 0x1000; 3087 } 3088 } else if (rb->rb_bt == sc->sc_iot) { 3089 if (align < 4) { 3090 return 1; 3091 } 3092 /* XXX: hack for avoiding ISA image */ 3093 if (mask < 0x0100) { 3094 mask = 0x3ff; 3095 addr = 0x300; 3096 } 3097 3098 } else { 3099 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3100 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3101 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3102 (unsigned long)sc->sc_memt)); 3103 return 1; 3104 /* XXX: panic here? */ 3105 } 3106 3107 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3108 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3109 return 1; 3110 } 3111 3112 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3113 3114 return 0; 3115 } 3116 3117 /* 3118 * static int 3119 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3120 * bus_space_handle_t *bshp, bus_size_t size); 3121 * 3122 * This function is called from CardBus card drivers. 3123 */ 3124 static int 3125 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3126 cardbus_chipset_tag_t ct; 3127 rbus_tag_t rb; 3128 bus_space_handle_t bsh; 3129 bus_size_t size; 3130 { 3131 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3132 bus_space_tag_t bt = rb->rb_bt; 3133 3134 pccbb_close_win(sc, bt, bsh, size); 3135 3136 if (bt == sc->sc_memt) { 3137 } else if (bt == sc->sc_iot) { 3138 } else { 3139 return 1; 3140 /* XXX: panic here? */ 3141 } 3142 3143 return rbus_space_free(rb, bsh, size, NULL); 3144 } 3145 #endif /* rbus */ 3146 3147 #if rbus 3148 3149 static int 3150 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3151 struct pccbb_softc *sc; 3152 bus_space_tag_t bst; 3153 bus_addr_t addr; 3154 bus_size_t size; 3155 bus_space_handle_t bsh; 3156 int flags; 3157 { 3158 struct pccbb_win_chain_head *head; 3159 bus_addr_t align; 3160 3161 head = &sc->sc_iowindow; 3162 align = 0x04; 3163 if (sc->sc_memt == bst) { 3164 head = &sc->sc_memwindow; 3165 align = 0x1000; 3166 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3167 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3168 (unsigned long)bst)); 3169 } 3170 3171 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3172 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3173 sc->sc_dev.dv_xname, 3174 (head == &sc->sc_memwindow) ? "mem" : "io"); 3175 } 3176 pccbb_winset(align, sc, bst); 3177 3178 return 0; 3179 } 3180 3181 static int 3182 pccbb_close_win(sc, bst, bsh, size) 3183 struct pccbb_softc *sc; 3184 bus_space_tag_t bst; 3185 bus_space_handle_t bsh; 3186 bus_size_t size; 3187 { 3188 struct pccbb_win_chain_head *head; 3189 bus_addr_t align; 3190 3191 head = &sc->sc_iowindow; 3192 align = 0x04; 3193 if (sc->sc_memt == bst) { 3194 head = &sc->sc_memwindow; 3195 align = 0x1000; 3196 } 3197 3198 if (pccbb_winlist_delete(head, bsh, size)) { 3199 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3200 sc->sc_dev.dv_xname, 3201 (head == &sc->sc_memwindow) ? "mem" : "io"); 3202 } 3203 pccbb_winset(align, sc, bst); 3204 3205 return 0; 3206 } 3207 3208 static int 3209 pccbb_winlist_insert(head, start, size, bsh, flags) 3210 struct pccbb_win_chain_head *head; 3211 bus_addr_t start; 3212 bus_size_t size; 3213 bus_space_handle_t bsh; 3214 int flags; 3215 { 3216 struct pccbb_win_chain *chainp, *elem; 3217 3218 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3219 M_NOWAIT)) == NULL) 3220 return (1); /* fail */ 3221 3222 elem->wc_start = start; 3223 elem->wc_end = start + (size - 1); 3224 elem->wc_handle = bsh; 3225 elem->wc_flags = flags; 3226 3227 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3228 chainp = TAILQ_NEXT(chainp, wc_list)) { 3229 if (chainp->wc_end < start) 3230 continue; 3231 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3232 return (0); 3233 } 3234 3235 TAILQ_INSERT_TAIL(head, elem, wc_list); 3236 return (0); 3237 } 3238 3239 static int 3240 pccbb_winlist_delete(head, bsh, size) 3241 struct pccbb_win_chain_head *head; 3242 bus_space_handle_t bsh; 3243 bus_size_t size; 3244 { 3245 struct pccbb_win_chain *chainp; 3246 3247 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3248 chainp = TAILQ_NEXT(chainp, wc_list)) { 3249 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3250 continue; 3251 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3252 printf("pccbb_winlist_delete: window 0x%lx size " 3253 "inconsistent: 0x%lx, 0x%lx\n", 3254 (unsigned long)chainp->wc_start, 3255 (unsigned long)(chainp->wc_end - chainp->wc_start), 3256 (unsigned long)(size - 1)); 3257 return 1; 3258 } 3259 3260 TAILQ_REMOVE(head, chainp, wc_list); 3261 free(chainp, M_DEVBUF); 3262 3263 return 0; 3264 } 3265 3266 return 1; /* fail: no candidate to remove */ 3267 } 3268 3269 static void 3270 pccbb_winset(align, sc, bst) 3271 bus_addr_t align; 3272 struct pccbb_softc *sc; 3273 bus_space_tag_t bst; 3274 { 3275 pci_chipset_tag_t pc; 3276 pcitag_t tag; 3277 bus_addr_t mask = ~(align - 1); 3278 struct { 3279 cardbusreg_t win_start; 3280 cardbusreg_t win_limit; 3281 int win_flags; 3282 } win[2]; 3283 struct pccbb_win_chain *chainp; 3284 int offs; 3285 3286 win[0].win_start = win[1].win_start = 0xffffffff; 3287 win[0].win_limit = win[1].win_limit = 0; 3288 win[0].win_flags = win[1].win_flags = 0; 3289 3290 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3291 offs = 0x2c; 3292 if (sc->sc_memt == bst) { 3293 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3294 offs = 0x1c; 3295 } 3296 3297 if (chainp != NULL) { 3298 win[0].win_start = chainp->wc_start & mask; 3299 win[0].win_limit = chainp->wc_end & mask; 3300 win[0].win_flags = chainp->wc_flags; 3301 chainp = TAILQ_NEXT(chainp, wc_list); 3302 } 3303 3304 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3305 if (win[1].win_start == 0xffffffff) { 3306 /* window 1 is not used */ 3307 if ((win[0].win_flags == chainp->wc_flags) && 3308 (win[0].win_limit + align >= 3309 (chainp->wc_start & mask))) { 3310 /* concatenate */ 3311 win[0].win_limit = chainp->wc_end & mask; 3312 } else { 3313 /* make new window */ 3314 win[1].win_start = chainp->wc_start & mask; 3315 win[1].win_limit = chainp->wc_end & mask; 3316 win[1].win_flags = chainp->wc_flags; 3317 } 3318 continue; 3319 } 3320 3321 /* Both windows are engaged. */ 3322 if (win[0].win_flags == win[1].win_flags) { 3323 /* same flags */ 3324 if (win[0].win_flags == chainp->wc_flags) { 3325 if (win[1].win_start - (win[0].win_limit + 3326 align) < 3327 (chainp->wc_start & mask) - 3328 ((chainp->wc_end & mask) + align)) { 3329 /* 3330 * merge window 0 and 1, and set win1 3331 * to chainp 3332 */ 3333 win[0].win_limit = win[1].win_limit; 3334 win[1].win_start = 3335 chainp->wc_start & mask; 3336 win[1].win_limit = 3337 chainp->wc_end & mask; 3338 } else { 3339 win[1].win_limit = 3340 chainp->wc_end & mask; 3341 } 3342 } else { 3343 /* different flags */ 3344 3345 /* concatenate win0 and win1 */ 3346 win[0].win_limit = win[1].win_limit; 3347 /* allocate win[1] to new space */ 3348 win[1].win_start = chainp->wc_start & mask; 3349 win[1].win_limit = chainp->wc_end & mask; 3350 win[1].win_flags = chainp->wc_flags; 3351 } 3352 } else { 3353 /* the flags of win[0] and win[1] is different */ 3354 if (win[0].win_flags == chainp->wc_flags) { 3355 win[0].win_limit = chainp->wc_end & mask; 3356 /* 3357 * XXX this creates overlapping windows, so 3358 * what should the poor bridge do if one is 3359 * cachable, and the other is not? 3360 */ 3361 printf("%s: overlapping windows\n", 3362 sc->sc_dev.dv_xname); 3363 } else { 3364 win[1].win_limit = chainp->wc_end & mask; 3365 } 3366 } 3367 } 3368 3369 pc = sc->sc_pc; 3370 tag = sc->sc_tag; 3371 pci_conf_write(pc, tag, offs, win[0].win_start); 3372 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3373 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3374 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3375 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3376 (unsigned long)pci_conf_read(pc, tag, offs), 3377 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3378 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3379 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3380 3381 if (bst == sc->sc_memt) { 3382 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3383 3384 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3385 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3386 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3387 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3388 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3389 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3390 } 3391 } 3392 3393 #endif /* rbus */ 3394 3395 static void 3396 pccbb_powerhook(why, arg) 3397 int why; 3398 void *arg; 3399 { 3400 struct pccbb_softc *sc = arg; 3401 pcireg_t reg; 3402 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3403 bus_space_handle_t base_memh = sc->sc_base_memh; 3404 3405 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3406 3407 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3408 DPRINTF(("%s: power: why %d stopping intr\n", 3409 sc->sc_dev.dv_xname, why)); 3410 if (sc->sc_pil_intr_enable) { 3411 (void)pccbbintr_function(sc); 3412 } 3413 sc->sc_pil_intr_enable = 0; 3414 3415 /* ToDo: deactivate or suspend child devices */ 3416 3417 } 3418 3419 if (why == PWR_RESUME) { 3420 if (sc->sc_pwrmgt_offs != 0) { 3421 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3422 sc->sc_pwrmgt_offs + 4); 3423 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3424 reg & 0x100) { 3425 /* powrstate != D0 */ 3426 3427 printf("%s going back to D0 mode\n", 3428 sc->sc_dev.dv_xname); 3429 reg &= ~PCI_PMCSR_STATE_MASK; 3430 reg |= PCI_PMCSR_STATE_D0; 3431 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3432 pci_conf_write(sc->sc_pc, sc->sc_tag, 3433 sc->sc_pwrmgt_offs + 4, reg); 3434 3435 pci_conf_write(sc->sc_pc, sc->sc_tag, 3436 PCI_SOCKBASE, sc->sc_sockbase); 3437 pci_conf_write(sc->sc_pc, sc->sc_tag, 3438 PCI_BUSNUM, sc->sc_busnum); 3439 pccbb_chipinit(sc); 3440 /* setup memory and io space window for CB */ 3441 pccbb_winset(0x1000, sc, sc->sc_memt); 3442 pccbb_winset(0x04, sc, sc->sc_iot); 3443 } 3444 } 3445 3446 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3447 /* BIOS did not recover this register */ 3448 pci_conf_write (sc->sc_pc, sc->sc_tag, 3449 PCI_SOCKBASE, sc->sc_sockbase); 3450 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3451 /* BIOS did not recover this register */ 3452 pci_conf_write (sc->sc_pc, sc->sc_tag, 3453 PCI_BUSNUM, sc->sc_busnum); 3454 /* CSC Interrupt: Card detect interrupt on */ 3455 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3456 /* Card detect intr is turned on. */ 3457 reg |= CB_SOCKET_MASK_CD; 3458 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3459 /* reset interrupt */ 3460 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3461 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3462 3463 /* 3464 * check for card insertion or removal during suspend period. 3465 * XXX: the code can't cope with card swap (remove then 3466 * insert). how can we detect such situation? 3467 */ 3468 (void)pccbbintr(sc); 3469 3470 sc->sc_pil_intr_enable = 1; 3471 DPRINTF(("%s: power: RESUME enabling intr\n", 3472 sc->sc_dev.dv_xname)); 3473 3474 /* ToDo: activate or wakeup child devices */ 3475 } 3476 } 3477
Indexes created Thu Sep 25 16:09:42 GMT 2025