pccbb.c revision 1.98
1 /* $NetBSD: pccbb.c,v 1.98 2004/07/22 16:39:51 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.98 2004/07/22 16:39:51 mycroft Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static int pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, NULL, NULL); 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 332 /* Ricoh chips */ 333 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 334 PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 336 PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 344 PCCBB_PCMCIA_MEM_32}, 345 346 /* Toshiba products */ 347 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 348 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 349 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 350 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 352 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 354 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 355 356 /* Cirrus Logic products */ 357 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 358 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 359 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 360 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 361 362 /* sentinel, or Generic chip */ 363 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 364 }; 365 366 static int 367 cb_chipset(pci_id, flagp) 368 u_int32_t pci_id; 369 int *flagp; 370 { 371 const struct yenta_chipinfo *yc; 372 373 /* Loop over except the last default entry. */ 374 for (yc = yc_chipsets; yc < yc_chipsets + 375 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 376 if (pci_id == yc->yc_id) 377 break; 378 379 if (flagp != NULL) 380 *flagp = yc->yc_flags; 381 382 return (yc->yc_chiptype); 383 } 384 385 static void 386 pccbb_shutdown(void *arg) 387 { 388 struct pccbb_softc *sc = arg; 389 pcireg_t command; 390 391 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 392 393 /* 394 * turn off power 395 * 396 * XXX - do not turn off power if chipset is TI 113X because 397 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 398 */ 399 if (sc->sc_chipset != CB_TI113X) { 400 pccbb_power((cardbus_chipset_tag_t)sc, 401 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 402 } 403 404 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 405 0); 406 407 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 408 409 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 410 PCI_COMMAND_MASTER_ENABLE); 411 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 412 413 } 414 415 void 416 pccbbattach(parent, self, aux) 417 struct device *parent; 418 struct device *self; 419 void *aux; 420 { 421 struct pccbb_softc *sc = (void *)self; 422 struct pci_attach_args *pa = aux; 423 pci_chipset_tag_t pc = pa->pa_pc; 424 pcireg_t busreg, reg, sock_base; 425 bus_addr_t sockbase; 426 char devinfo[256]; 427 int flags; 428 int pwrmgt_offs; 429 430 #ifdef __HAVE_PCCBB_ATTACH_HOOK 431 pccbb_attach_hook(parent, self, pa); 432 #endif 433 434 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 435 436 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 437 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 438 #ifdef CBB_DEBUG 439 printf(" (chipflags %x)", flags); 440 #endif 441 printf("\n"); 442 443 TAILQ_INIT(&sc->sc_memwindow); 444 TAILQ_INIT(&sc->sc_iowindow); 445 446 #if rbus 447 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 448 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 449 450 #if 0 451 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 452 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 453 #endif 454 #endif /* rbus */ 455 456 sc->sc_flags &= ~CBB_MEMHMAPPED; 457 458 /* power management: set D0 state */ 459 sc->sc_pwrmgt_offs = 0; 460 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 461 &pwrmgt_offs, 0)) { 462 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 463 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 464 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 465 reg &= ~PCI_PMCSR_STATE_MASK; 466 reg |= PCI_PMCSR_STATE_D0; 467 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 468 pci_conf_write(pc, pa->pa_tag, 469 pwrmgt_offs + PCI_PMCSR, reg); 470 } 471 472 sc->sc_pwrmgt_offs = pwrmgt_offs; 473 } 474 475 /* 476 * MAP socket registers and ExCA registers on memory-space 477 * When no valid address is set on socket base registers (on pci 478 * config space), get it not polite way. 479 */ 480 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 481 482 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 483 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 484 /* The address must be valid. */ 485 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 486 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 487 printf("%s: can't map socket base address 0x%lx\n", 488 sc->sc_dev.dv_xname, (unsigned long)sock_base); 489 /* 490 * I think it's funny: socket base registers must be 491 * mapped on memory space, but ... 492 */ 493 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 494 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 495 NULL)) { 496 printf("%s: can't map socket base address" 497 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 498 (unsigned long)sockbase); 499 /* give up... allocate reg space via rbus. */ 500 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 501 } else 502 sc->sc_flags |= CBB_MEMHMAPPED; 503 } else { 504 DPRINTF(("%s: socket base address 0x%lx\n", 505 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 506 sc->sc_flags |= CBB_MEMHMAPPED; 507 } 508 } 509 510 sc->sc_mem_start = 0; /* XXX */ 511 sc->sc_mem_end = 0xffffffff; /* XXX */ 512 513 /* 514 * When interrupt isn't routed correctly, give up probing cbb and do 515 * not kill pcic-compatible port. 516 */ 517 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 518 printf("%s: NOT USED because of unconfigured interrupt\n", 519 sc->sc_dev.dv_xname); 520 return; 521 } 522 523 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 524 525 /* pccbb_machdep.c end */ 526 527 #if defined CBB_DEBUG 528 { 529 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 530 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 531 intrname[pa->pa_intrpin], pa->pa_intrline); 532 } 533 #endif 534 535 /* setup softc */ 536 sc->sc_pc = pc; 537 sc->sc_iot = pa->pa_iot; 538 sc->sc_memt = pa->pa_memt; 539 sc->sc_dmat = pa->pa_dmat; 540 sc->sc_tag = pa->pa_tag; 541 sc->sc_function = pa->pa_function; 542 sc->sc_sockbase = sock_base; 543 sc->sc_busnum = busreg; 544 545 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 546 547 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 548 549 shutdownhook_establish(pccbb_shutdown, sc); 550 551 /* Disable legacy register mapping. */ 552 switch (sc->sc_chipset) { 553 case CB_RX5C46X: /* fallthrough */ 554 #if 0 555 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 556 case CB_RX5C47X: 557 #endif 558 /* 559 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 560 * cannot be disabled by substituting 0 into PCI_LEGACY 561 * register. Ricoh CardBus bridges have special bits on Bridge 562 * control reg (addr 0x3e on PCI config space). 563 */ 564 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 565 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 566 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 567 break; 568 569 default: 570 /* XXX I don't know proper way to kill legacy I/O. */ 571 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 572 break; 573 } 574 575 config_defer(self, pccbb_pci_callback); 576 } 577 578 579 580 581 /* 582 * static void pccbb_pci_callback(struct device *self) 583 * 584 * The actual attach routine: get memory space for YENTA register 585 * space, setup YENTA register and route interrupt. 586 * 587 * This function should be deferred because this device may obtain 588 * memory space dynamically. This function must avoid obtaining 589 * memory area which has already kept for another device. 590 */ 591 static void 592 pccbb_pci_callback(self) 593 struct device *self; 594 { 595 struct pccbb_softc *sc = (void *)self; 596 pci_chipset_tag_t pc = sc->sc_pc; 597 pci_intr_handle_t ih; 598 const char *intrstr = NULL; 599 bus_addr_t sockbase; 600 struct cbslot_attach_args cba; 601 struct pcmciabus_attach_args paa; 602 struct cardslot_attach_args caa; 603 struct cardslot_softc *csc; 604 605 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 606 /* The socket registers aren't mapped correctly. */ 607 #if rbus 608 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 609 (sc->sc_chipset == CB_RX5C47X 610 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 611 0, &sockbase, &sc->sc_base_memh)) { 612 return; 613 } 614 sc->sc_base_memt = sc->sc_memt; 615 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 616 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 617 sc->sc_dev.dv_xname, (unsigned long)sockbase, 618 (unsigned long)pci_conf_read(pc, sc->sc_tag, 619 PCI_SOCKBASE))); 620 #else 621 sc->sc_base_memt = sc->sc_memt; 622 #if !defined CBB_PCI_BASE 623 #define CBB_PCI_BASE 0x20000000 624 #endif 625 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 626 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 627 /* cannot allocate memory space */ 628 return; 629 } 630 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 631 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 632 sc->sc_dev.dv_xname, (unsigned long)sock_base, 633 (unsigned long)pci_conf_read(pc, 634 sc->sc_tag, PCI_SOCKBASE))); 635 sc->sc_sockbase = sockbase; 636 #endif 637 sc->sc_flags |= CBB_MEMHMAPPED; 638 } 639 640 /* bus bridge initialization */ 641 pccbb_chipinit(sc); 642 643 /* clear data structure for child device interrupt handlers */ 644 LIST_INIT(&sc->sc_pil); 645 sc->sc_pil_intr_enable = 1; 646 647 /* Map and establish the interrupt. */ 648 if (pci_intr_map(&sc->sc_pa, &ih)) { 649 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 650 return; 651 } 652 intrstr = pci_intr_string(pc, ih); 653 654 /* 655 * XXX pccbbintr should be called under the priority lower 656 * than any other hard interrputs. 657 */ 658 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 659 660 if (sc->sc_ih == NULL) { 661 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 662 if (intrstr != NULL) { 663 printf(" at %s", intrstr); 664 } 665 printf("\n"); 666 return; 667 } 668 669 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 670 powerhook_establish(pccbb_powerhook, sc); 671 672 { 673 u_int32_t sockstat; 674 675 sockstat = bus_space_read_4(sc->sc_base_memt, 676 sc->sc_base_memh, CB_SOCKET_STAT); 677 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 678 sc->sc_flags |= CBB_CARDEXIST; 679 } 680 } 681 682 /* 683 * attach cardbus 684 */ 685 { 686 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 687 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 688 689 /* initialize cbslot_attach */ 690 cba.cba_busname = "cardbus"; 691 cba.cba_iot = sc->sc_iot; 692 cba.cba_memt = sc->sc_memt; 693 cba.cba_dmat = sc->sc_dmat; 694 cba.cba_bus = (busreg >> 8) & 0x0ff; 695 cba.cba_cc = (void *)sc; 696 cba.cba_cf = &pccbb_funcs; 697 cba.cba_intrline = sc->sc_pa.pa_intrline; 698 699 #if rbus 700 cba.cba_rbus_iot = sc->sc_rbus_iot; 701 cba.cba_rbus_memt = sc->sc_rbus_memt; 702 #endif 703 704 cba.cba_cacheline = PCI_CACHELINE(bhlc); 705 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 706 707 if (bootverbose) { 708 printf("%s: cacheline 0x%x lattimer 0x%x\n", 709 sc->sc_dev.dv_xname, cba.cba_cacheline, 710 cba.cba_lattimer); 711 printf("%s: bhlc 0x%x lscp 0x%x\n", 712 sc->sc_dev.dv_xname, bhlc, busreg); 713 } 714 #if defined SHOW_REGS 715 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 716 sc->sc_base_memh); 717 #endif 718 } 719 720 pccbb_pcmcia_attach_setup(sc, &paa); 721 caa.caa_cb_attach = NULL; 722 if (cba.cba_bus == 0) 723 printf("%s: secondary bus number uninitialized; try PCIBIOS_BUS_FIXUP\n", sc->sc_dev.dv_xname); 724 else 725 caa.caa_cb_attach = &cba; 726 caa.caa_16_attach = &paa; 727 caa.caa_ph = &sc->sc_pcmcia_h; 728 729 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 730 DPRINTF(("pccbbattach: found cardslot\n")); 731 sc->sc_csc = csc; 732 } 733 734 return; 735 } 736 737 738 739 740 741 /* 742 * static void pccbb_chipinit(struct pccbb_softc *sc) 743 * 744 * This function initialize YENTA chip registers listed below: 745 * 1) PCI command reg, 746 * 2) PCI and CardBus latency timer, 747 * 3) route PCI interrupt, 748 * 4) close all memory and io windows. 749 * 5) turn off bus power. 750 * 6) card detect interrupt on. 751 * 7) clear interrupt 752 */ 753 static void 754 pccbb_chipinit(sc) 755 struct pccbb_softc *sc; 756 { 757 pci_chipset_tag_t pc = sc->sc_pc; 758 pcitag_t tag = sc->sc_tag; 759 bus_space_tag_t bmt = sc->sc_base_memt; 760 bus_space_handle_t bmh = sc->sc_base_memh; 761 pcireg_t reg; 762 763 /* 764 * Set PCI command reg. 765 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 766 */ 767 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 768 /* I believe it is harmless. */ 769 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 770 PCI_COMMAND_MASTER_ENABLE); 771 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 772 773 /* 774 * Set CardBus latency timer. 775 */ 776 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 777 if (PCI_CB_LATENCY(reg) < 0x20) { 778 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 779 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 780 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 781 } 782 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 783 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 784 785 /* 786 * Set PCI latency timer. 787 */ 788 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 789 if (PCI_LATTIMER(reg) < 0x10) { 790 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 791 reg |= (0x10 << PCI_LATTIMER_SHIFT); 792 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 793 } 794 DPRINTF(("PCI latency timer 0x%x (%x)\n", 795 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 796 797 798 /* Route functional interrupts to PCI. */ 799 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 800 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 801 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 802 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 803 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 804 805 switch (sc->sc_chipset) { 806 case CB_TI113X: 807 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 808 /* This bit is shared, but may read as 0 on some chips, so set 809 it explicitly on both functions. */ 810 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 811 /* CSC intr enable */ 812 reg |= PCI113X_CBCTRL_PCI_CSC; 813 /* functional intr prohibit | prohibit ISA routing */ 814 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 815 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 816 break; 817 818 case CB_TI12XX: 819 /* 820 * Some TI 12xx (and [14][45]xx) based pci cards 821 * sometimes have issues with the MFUNC register not 822 * being initialized due to a bad EEPROM on board. 823 * Laptops that this matters on have this register 824 * properly initialized. 825 * 826 * The TI125X parts have a different register. 827 */ 828 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 829 if (reg == 0) { 830 reg &= ~PCI12XX_MFUNC_PIN0; 831 reg |= PCI12XX_MFUNC_PIN0_INTA; 832 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 833 PCI12XX_SYSCTRL_INTRTIE) == 0) { 834 reg &= ~PCI12XX_MFUNC_PIN1; 835 reg |= PCI12XX_MFUNC_PIN1_INTB; 836 } 837 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 838 } 839 /* fallthrough */ 840 841 case CB_TI125X: 842 /* 843 * Disable zoom video. Some machines initialize this 844 * improperly and experience has shown that this helps 845 * prevent strange behavior. 846 */ 847 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 848 849 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 850 reg |= PCI12XX_SYSCTRL_VCCPROT; 851 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 852 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 853 reg |= PCI12XX_CBCTRL_CSC; 854 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 855 break; 856 857 case CB_TOPIC95B: 858 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 859 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 860 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 861 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 862 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 863 sc->sc_dev.dv_xname, reg)); 864 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 865 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 866 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 867 DPRINTF(("0x%x\n", reg)); 868 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 869 break; 870 871 case CB_TOPIC97: 872 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 873 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 874 sc->sc_dev.dv_xname, reg)); 875 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 876 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 877 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 878 reg |= TOPIC97_SLOT_CTRL_PCIINT; 879 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 880 DPRINTF(("0x%x\n", reg)); 881 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 882 /* make sure to assert LV card support bits */ 883 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 884 0x800 + 0x3e, 885 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 886 0x800 + 0x3e) | 0x03); 887 break; 888 } 889 890 /* Close all memory and I/O windows. */ 891 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 892 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 893 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 894 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 895 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 896 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 897 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 898 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 899 900 /* reset 16-bit pcmcia bus */ 901 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 902 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 903 904 /* turn off power */ 905 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 906 907 /* CSC Interrupt: Card detect interrupt on */ 908 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 909 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 910 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 911 /* reset interrupt */ 912 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 913 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 914 } 915 916 917 918 919 /* 920 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 921 * struct pcmciabus_attach_args *paa) 922 * 923 * This function attaches 16-bit PCcard bus. 924 */ 925 STATIC void 926 pccbb_pcmcia_attach_setup(sc, paa) 927 struct pccbb_softc *sc; 928 struct pcmciabus_attach_args *paa; 929 { 930 struct pcic_handle *ph = &sc->sc_pcmcia_h; 931 #if rbus 932 rbus_tag_t rb; 933 #endif 934 935 /* initialize pcmcia part in pccbb_softc */ 936 ph->ph_parent = (struct device *)sc; 937 ph->sock = sc->sc_function; 938 ph->flags = 0; 939 ph->shutdown = 0; 940 ph->ih_irq = sc->sc_pa.pa_intrline; 941 ph->ph_bus_t = sc->sc_base_memt; 942 ph->ph_bus_h = sc->sc_base_memh; 943 ph->ph_read = pccbb_pcmcia_read; 944 ph->ph_write = pccbb_pcmcia_write; 945 sc->sc_pct = &pccbb_pcmcia_funcs; 946 947 /* 948 * We need to do a few things here: 949 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 950 * setting the IRQ numbers to 0. 951 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 952 * routing of CSC interrupts (e.g. card removal) to PCI while in 953 * PCMCIA mode. We just leave this set all the time. 954 * 3) Enable card insertion/removal interrupts in case the chip also 955 * needs that while in PCMCIA mode. 956 * 4) Clear any pending CSC interrupt. 957 */ 958 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 959 if (sc->sc_chipset == CB_TI113X) { 960 Pcic_write(ph, PCIC_CSC_INTR, 0); 961 } else { 962 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 963 Pcic_read(ph, PCIC_CSC); 964 } 965 966 /* initialize pcmcia bus attachment */ 967 paa->paa_busname = "pcmcia"; 968 paa->pct = sc->sc_pct; 969 paa->pch = ph; 970 paa->iobase = 0; /* I don't use them */ 971 paa->iosize = 0; 972 #if rbus 973 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 974 paa->iobase = rb->rb_start + rb->rb_offset; 975 paa->iosize = rb->rb_end - rb->rb_start; 976 #endif 977 978 return; 979 } 980 981 #if 0 982 STATIC void 983 pccbb_pcmcia_attach_card(ph) 984 struct pcic_handle *ph; 985 { 986 if (ph->flags & PCIC_FLAG_CARDP) { 987 panic("pccbb_pcmcia_attach_card: already attached"); 988 } 989 990 /* call the MI attach function */ 991 pcmcia_card_attach(ph->pcmcia); 992 993 ph->flags |= PCIC_FLAG_CARDP; 994 } 995 996 STATIC void 997 pccbb_pcmcia_detach_card(ph, flags) 998 struct pcic_handle *ph; 999 int flags; 1000 { 1001 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1002 panic("pccbb_pcmcia_detach_card: already detached"); 1003 } 1004 1005 ph->flags &= ~PCIC_FLAG_CARDP; 1006 1007 /* call the MI detach function */ 1008 pcmcia_card_detach(ph->pcmcia, flags); 1009 } 1010 #endif 1011 1012 /* 1013 * int pccbbintr(arg) 1014 * void *arg; 1015 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1016 * itself. 1017 */ 1018 int 1019 pccbbintr(arg) 1020 void *arg; 1021 { 1022 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1023 u_int32_t sockevent, sockstate; 1024 bus_space_tag_t memt = sc->sc_base_memt; 1025 bus_space_handle_t memh = sc->sc_base_memh; 1026 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1027 1028 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1029 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1030 Pcic_read(ph, PCIC_CSC); 1031 1032 if (sockevent == 0) { 1033 /* This intr is not for me: it may be for my child devices. */ 1034 if (sc->sc_pil_intr_enable) { 1035 return pccbbintr_function(sc); 1036 } else { 1037 return 0; 1038 } 1039 } 1040 1041 if (sockevent & CB_SOCKET_EVENT_CD) { 1042 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1043 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1044 /* A card should be removed. */ 1045 if (sc->sc_flags & CBB_CARDEXIST) { 1046 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1047 sockevent)); 1048 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1049 sc->sc_flags &= ~CBB_CARDEXIST; 1050 if (sc->sc_csc->sc_status & 1051 CARDSLOT_STATUS_CARD_16) { 1052 #if 0 1053 struct pcic_handle *ph = 1054 &sc->sc_pcmcia_h; 1055 1056 pcmcia_card_deactivate(ph->pcmcia); 1057 pccbb_pcmcia_socket_disable(ph); 1058 pccbb_pcmcia_detach_card(ph, 1059 DETACH_FORCE); 1060 #endif 1061 cardslot_event_throw(sc->sc_csc, 1062 CARDSLOT_EVENT_REMOVAL_16); 1063 } else if (sc->sc_csc->sc_status & 1064 CARDSLOT_STATUS_CARD_CB) { 1065 /* Cardbus intr removed */ 1066 cardslot_event_throw(sc->sc_csc, 1067 CARDSLOT_EVENT_REMOVAL_CB); 1068 } 1069 } else if (sc->sc_flags & CBB_INSERTING) { 1070 sc->sc_flags &= ~CBB_INSERTING; 1071 callout_stop(&sc->sc_insert_ch); 1072 } 1073 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1074 /* 1075 * The pccbbintr may called from powerdown hook when 1076 * the system resumed, to detect the card 1077 * insertion/removal during suspension. 1078 */ 1079 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1080 if (sc->sc_flags & CBB_INSERTING) { 1081 callout_stop(&sc->sc_insert_ch); 1082 } 1083 callout_reset(&sc->sc_insert_ch, hz / 5, 1084 pci113x_insert, sc); 1085 sc->sc_flags |= CBB_INSERTING; 1086 } 1087 } 1088 1089 return (1); 1090 } 1091 1092 /* 1093 * static int pccbbintr_function(struct pccbb_softc *sc) 1094 * 1095 * This function calls each interrupt handler registered at the 1096 * bridge. The interrupt handlers are called in registered order. 1097 */ 1098 static int 1099 pccbbintr_function(sc) 1100 struct pccbb_softc *sc; 1101 { 1102 int retval = 0, val; 1103 struct pccbb_intrhand_list *pil; 1104 int s, splchanged; 1105 1106 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1107 pil = LIST_NEXT(pil, pil_next)) { 1108 /* 1109 * XXX priority change. gross. I use if-else 1110 * sentense instead of switch-case sentense because of 1111 * avoiding duplicate case value error. More than one 1112 * IPL_XXX use same value. It depends on 1113 * implimentation. 1114 */ 1115 splchanged = 1; 1116 if (pil->pil_level == IPL_SERIAL) { 1117 s = splserial(); 1118 } else if (pil->pil_level == IPL_HIGH) { 1119 s = splhigh(); 1120 } else if (pil->pil_level == IPL_CLOCK) { 1121 s = splclock(); 1122 } else if (pil->pil_level == IPL_AUDIO) { 1123 s = splaudio(); 1124 } else if (pil->pil_level == IPL_VM) { 1125 s = splvm(); 1126 } else if (pil->pil_level == IPL_TTY) { 1127 s = spltty(); 1128 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1129 s = splsoftserial(); 1130 } else if (pil->pil_level == IPL_NET) { 1131 s = splnet(); 1132 } else { 1133 s = 0; /* XXX: gcc */ 1134 splchanged = 0; 1135 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1136 } 1137 1138 val = (*pil->pil_func)(pil->pil_arg); 1139 1140 if (splchanged != 0) { 1141 splx(s); 1142 } 1143 1144 retval = retval == 1 ? 1 : 1145 retval == 0 ? val : val != 0 ? val : retval; 1146 } 1147 1148 return retval; 1149 } 1150 1151 static void 1152 pci113x_insert(arg) 1153 void *arg; 1154 { 1155 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1156 u_int32_t sockevent, sockstate; 1157 1158 if (!(sc->sc_flags & CBB_INSERTING)) { 1159 /* We add a card only under inserting state. */ 1160 return; 1161 } 1162 sc->sc_flags &= ~CBB_INSERTING; 1163 1164 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1165 CB_SOCKET_EVENT); 1166 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1167 CB_SOCKET_STAT); 1168 1169 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1170 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1171 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1172 sc->sc_flags |= CBB_CARDEXIST; 1173 /* call pccard interrupt handler here */ 1174 if (sockstate & CB_SOCKET_STAT_16BIT) { 1175 /* 16-bit card found */ 1176 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1177 cardslot_event_throw(sc->sc_csc, 1178 CARDSLOT_EVENT_INSERTION_16); 1179 } else if (sockstate & CB_SOCKET_STAT_CB) { 1180 /* cardbus card found */ 1181 /* cardbus_attach_card(sc->sc_csc); */ 1182 cardslot_event_throw(sc->sc_csc, 1183 CARDSLOT_EVENT_INSERTION_CB); 1184 } else { 1185 /* who are you? */ 1186 } 1187 } else { 1188 callout_reset(&sc->sc_insert_ch, hz / 10, 1189 pci113x_insert, sc); 1190 } 1191 } 1192 1193 #define PCCBB_PCMCIA_OFFSET 0x800 1194 static u_int8_t 1195 pccbb_pcmcia_read(ph, reg) 1196 struct pcic_handle *ph; 1197 int reg; 1198 { 1199 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1200 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1201 1202 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1203 PCCBB_PCMCIA_OFFSET + reg); 1204 } 1205 1206 static void 1207 pccbb_pcmcia_write(ph, reg, val) 1208 struct pcic_handle *ph; 1209 int reg; 1210 u_int8_t val; 1211 { 1212 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1213 val); 1214 1215 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1216 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1217 } 1218 1219 /* 1220 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1221 */ 1222 STATIC int 1223 pccbb_ctrl(ct, command) 1224 cardbus_chipset_tag_t ct; 1225 int command; 1226 { 1227 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1228 1229 switch (command) { 1230 case CARDBUS_CD: 1231 if (2 == pccbb_detect_card(sc)) { 1232 int retval = 0; 1233 int status = cb_detect_voltage(sc); 1234 if (PCCARD_VCC_5V & status) { 1235 retval |= CARDBUS_5V_CARD; 1236 } 1237 if (PCCARD_VCC_3V & status) { 1238 retval |= CARDBUS_3V_CARD; 1239 } 1240 if (PCCARD_VCC_XV & status) { 1241 retval |= CARDBUS_XV_CARD; 1242 } 1243 if (PCCARD_VCC_YV & status) { 1244 retval |= CARDBUS_YV_CARD; 1245 } 1246 return retval; 1247 } else { 1248 return 0; 1249 } 1250 case CARDBUS_RESET: 1251 return cb_reset(sc); 1252 case CARDBUS_IO_ENABLE: /* fallthrough */ 1253 case CARDBUS_IO_DISABLE: /* fallthrough */ 1254 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1255 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1256 case CARDBUS_BM_ENABLE: /* fallthrough */ 1257 case CARDBUS_BM_DISABLE: /* fallthrough */ 1258 /* XXX: I think we don't need to call this function below. */ 1259 return pccbb_cardenable(sc, command); 1260 } 1261 1262 return 0; 1263 } 1264 1265 /* 1266 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1267 * This function returns true when it succeeds and returns false when 1268 * it fails. 1269 */ 1270 STATIC int 1271 pccbb_power(ct, command) 1272 cardbus_chipset_tag_t ct; 1273 int command; 1274 { 1275 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1276 1277 u_int32_t status, sock_ctrl, reg_ctrl; 1278 bus_space_tag_t memt = sc->sc_base_memt; 1279 bus_space_handle_t memh = sc->sc_base_memh; 1280 1281 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1282 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1283 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1284 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1285 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1286 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1287 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1288 "UNKNOWN", 1289 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1290 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1291 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1292 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1293 "UNKNOWN", command)); 1294 1295 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1296 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1297 1298 switch (command & CARDBUS_VCCMASK) { 1299 case CARDBUS_VCC_UC: 1300 break; 1301 case CARDBUS_VCC_5V: 1302 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1303 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1304 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1305 } else { 1306 printf("%s: BAD voltage request: no 5 V card\n", 1307 sc->sc_dev.dv_xname); 1308 return 0; 1309 } 1310 break; 1311 case CARDBUS_VCC_3V: 1312 if (CB_SOCKET_STAT_3VCARD & status) { 1313 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1314 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1315 } else { 1316 printf("%s: BAD voltage request: no 3.3 V card\n", 1317 sc->sc_dev.dv_xname); 1318 return 0; 1319 } 1320 break; 1321 case CARDBUS_VCC_0V: 1322 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1323 break; 1324 default: 1325 return 0; /* power NEVER changed */ 1326 } 1327 1328 switch (command & CARDBUS_VPPMASK) { 1329 case CARDBUS_VPP_UC: 1330 break; 1331 case CARDBUS_VPP_0V: 1332 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1333 break; 1334 case CARDBUS_VPP_VCC: 1335 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1336 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1337 break; 1338 case CARDBUS_VPP_12V: 1339 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1340 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1341 break; 1342 } 1343 1344 #if 0 1345 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1346 #endif 1347 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1348 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1349 1350 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1351 printf 1352 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1353 sc->sc_dev.dv_xname, sock_ctrl, status); 1354 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1355 (command & CARDBUS_VCCMASK) == 1356 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1357 CARDBUS_VCCMASK) == 1358 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1359 CARDBUS_VCCMASK) == 1360 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1361 CARDBUS_VCCMASK) == 1362 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1363 CARDBUS_VCCMASK) == 1364 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1365 CARDBUS_VCCMASK) == 1366 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1367 (command & CARDBUS_VPPMASK) == 1368 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1369 CARDBUS_VPPMASK) == 1370 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1371 CARDBUS_VPPMASK) == 1372 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1373 CARDBUS_VPPMASK) == 1374 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1375 #if 0 1376 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1377 u_int32_t force = 1378 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1379 /* Reset Bad Vcc request */ 1380 force &= ~CB_SOCKET_FORCE_BADVCC; 1381 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1382 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1383 CB_SOCKET_STAT)); 1384 return 1; 1385 } 1386 #endif 1387 return 0; 1388 } 1389 1390 if (sc->sc_chipset == CB_TOPIC97) { 1391 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1392 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1393 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1394 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1395 else 1396 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1397 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1398 } 1399 1400 /* 1401 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1402 * time is 20 ms, some PC-Card bridge requires longer duration. 1403 */ 1404 #if 0 /* XXX called on interrupt context */ 1405 DELAY_MS(300, sc); 1406 #else 1407 delay(300 * 1000); 1408 #endif 1409 1410 return 1; /* power changed correctly */ 1411 } 1412 1413 #if defined CB_PCMCIA_POLL 1414 struct cb_poll_str { 1415 void *arg; 1416 int (*func) __P((void *)); 1417 int level; 1418 pccard_chipset_tag_t ct; 1419 int count; 1420 struct callout poll_ch; 1421 }; 1422 1423 static struct cb_poll_str cb_poll[10]; 1424 static int cb_poll_n = 0; 1425 1426 static void cb_pcmcia_poll __P((void *arg)); 1427 1428 static void 1429 cb_pcmcia_poll(arg) 1430 void *arg; 1431 { 1432 struct cb_poll_str *poll = arg; 1433 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1434 struct pccbb_softc *sc = psc->cpc_parent; 1435 int s; 1436 u_int32_t spsr; /* socket present-state reg */ 1437 1438 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1439 switch (poll->level) { 1440 case IPL_NET: 1441 s = splnet(); 1442 break; 1443 case IPL_BIO: 1444 s = splbio(); 1445 break; 1446 case IPL_TTY: /* fallthrough */ 1447 default: 1448 s = spltty(); 1449 break; 1450 } 1451 1452 spsr = 1453 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1454 CB_SOCKET_STAT); 1455 1456 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1457 if (!(spsr & 0x40)) { /* CINT low */ 1458 #else 1459 if (1) { 1460 #endif 1461 if ((*poll->func) (poll->arg) == 1) { 1462 ++poll->count; 1463 printf("intr: reported from poller, 0x%x\n", spsr); 1464 #if defined LEVEL2 1465 } else { 1466 printf("intr: miss! 0x%x\n", spsr); 1467 #endif 1468 } 1469 } 1470 splx(s); 1471 } 1472 #endif /* defined CB_PCMCIA_POLL */ 1473 1474 /* 1475 * static int pccbb_detect_card(struct pccbb_softc *sc) 1476 * return value: 0 if no card exists. 1477 * 1 if 16-bit card exists. 1478 * 2 if cardbus card exists. 1479 */ 1480 static int 1481 pccbb_detect_card(sc) 1482 struct pccbb_softc *sc; 1483 { 1484 bus_space_handle_t base_memh = sc->sc_base_memh; 1485 bus_space_tag_t base_memt = sc->sc_base_memt; 1486 u_int32_t sockstat = 1487 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1488 int retval = 0; 1489 1490 /* CD1 and CD2 asserted */ 1491 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1492 /* card must be present */ 1493 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1494 /* NOTACARD DEASSERTED */ 1495 if (CB_SOCKET_STAT_CB & sockstat) { 1496 /* CardBus mode */ 1497 retval = 2; 1498 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1499 /* 16-bit mode */ 1500 retval = 1; 1501 } 1502 } 1503 } 1504 return retval; 1505 } 1506 1507 /* 1508 * STATIC int cb_reset(struct pccbb_softc *sc) 1509 * This function resets CardBus card. 1510 */ 1511 STATIC int 1512 cb_reset(sc) 1513 struct pccbb_softc *sc; 1514 { 1515 /* 1516 * Reset Assert at least 20 ms 1517 * Some machines request longer duration. 1518 */ 1519 int reset_duration = 1520 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1521 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1522 1523 /* Reset bit Assert (bit 6 at 0x3E) */ 1524 bcr |= CB_BCR_RESET_ENABLE; 1525 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1526 DELAY_MS(reset_duration, sc); 1527 1528 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1529 /* Reset bit Deassert (bit 6 at 0x3E) */ 1530 bcr &= ~CB_BCR_RESET_ENABLE; 1531 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1532 DELAY_MS(reset_duration, sc); 1533 } 1534 /* No card found on the slot. Keep Reset. */ 1535 return 1; 1536 } 1537 1538 /* 1539 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1540 * This function detect card Voltage. 1541 */ 1542 STATIC int 1543 cb_detect_voltage(sc) 1544 struct pccbb_softc *sc; 1545 { 1546 u_int32_t psr; /* socket present-state reg */ 1547 bus_space_tag_t iot = sc->sc_base_memt; 1548 bus_space_handle_t ioh = sc->sc_base_memh; 1549 int vol = PCCARD_VCC_UKN; /* set 0 */ 1550 1551 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1552 1553 if (0x400u & psr) { 1554 vol |= PCCARD_VCC_5V; 1555 } 1556 if (0x800u & psr) { 1557 vol |= PCCARD_VCC_3V; 1558 } 1559 1560 return vol; 1561 } 1562 1563 STATIC int 1564 cbbprint(aux, pcic) 1565 void *aux; 1566 const char *pcic; 1567 { 1568 /* 1569 struct cbslot_attach_args *cba = aux; 1570 1571 if (cba->cba_slot >= 0) { 1572 aprint_normal(" slot %d", cba->cba_slot); 1573 } 1574 */ 1575 return UNCONF; 1576 } 1577 1578 /* 1579 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1580 * This function enables and disables the card 1581 */ 1582 STATIC int 1583 pccbb_cardenable(sc, function) 1584 struct pccbb_softc *sc; 1585 int function; 1586 { 1587 u_int32_t command = 1588 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1589 1590 DPRINTF(("pccbb_cardenable:")); 1591 switch (function) { 1592 case CARDBUS_IO_ENABLE: 1593 command |= PCI_COMMAND_IO_ENABLE; 1594 break; 1595 case CARDBUS_IO_DISABLE: 1596 command &= ~PCI_COMMAND_IO_ENABLE; 1597 break; 1598 case CARDBUS_MEM_ENABLE: 1599 command |= PCI_COMMAND_MEM_ENABLE; 1600 break; 1601 case CARDBUS_MEM_DISABLE: 1602 command &= ~PCI_COMMAND_MEM_ENABLE; 1603 break; 1604 case CARDBUS_BM_ENABLE: 1605 command |= PCI_COMMAND_MASTER_ENABLE; 1606 break; 1607 case CARDBUS_BM_DISABLE: 1608 command &= ~PCI_COMMAND_MASTER_ENABLE; 1609 break; 1610 default: 1611 return 0; 1612 } 1613 1614 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1615 DPRINTF((" command reg 0x%x\n", command)); 1616 return 1; 1617 } 1618 1619 #if !rbus 1620 /* 1621 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1622 */ 1623 static int 1624 pccbb_io_open(ct, win, start, end) 1625 cardbus_chipset_tag_t ct; 1626 int win; 1627 u_int32_t start, end; 1628 { 1629 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1630 int basereg; 1631 int limitreg; 1632 1633 if ((win < 0) || (win > 2)) { 1634 #if defined DIAGNOSTIC 1635 printf("cardbus_io_open: window out of range %d\n", win); 1636 #endif 1637 return 0; 1638 } 1639 1640 basereg = win * 8 + 0x2c; 1641 limitreg = win * 8 + 0x30; 1642 1643 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1644 start, basereg, end, limitreg)); 1645 1646 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1647 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1648 return 1; 1649 } 1650 1651 /* 1652 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1653 */ 1654 static int 1655 pccbb_io_close(ct, win) 1656 cardbus_chipset_tag_t ct; 1657 int win; 1658 { 1659 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1660 int basereg; 1661 int limitreg; 1662 1663 if ((win < 0) || (win > 2)) { 1664 #if defined DIAGNOSTIC 1665 printf("cardbus_io_close: window out of range %d\n", win); 1666 #endif 1667 return 0; 1668 } 1669 1670 basereg = win * 8 + 0x2c; 1671 limitreg = win * 8 + 0x30; 1672 1673 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1674 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1675 return 1; 1676 } 1677 1678 /* 1679 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1680 */ 1681 static int 1682 pccbb_mem_open(ct, win, start, end) 1683 cardbus_chipset_tag_t ct; 1684 int win; 1685 u_int32_t start, end; 1686 { 1687 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1688 int basereg; 1689 int limitreg; 1690 1691 if ((win < 0) || (win > 2)) { 1692 #if defined DIAGNOSTIC 1693 printf("cardbus_mem_open: window out of range %d\n", win); 1694 #endif 1695 return 0; 1696 } 1697 1698 basereg = win * 8 + 0x1c; 1699 limitreg = win * 8 + 0x20; 1700 1701 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1702 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1703 return 1; 1704 } 1705 1706 /* 1707 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1708 */ 1709 static int 1710 pccbb_mem_close(ct, win) 1711 cardbus_chipset_tag_t ct; 1712 int win; 1713 { 1714 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1715 int basereg; 1716 int limitreg; 1717 1718 if ((win < 0) || (win > 2)) { 1719 #if defined DIAGNOSTIC 1720 printf("cardbus_mem_close: window out of range %d\n", win); 1721 #endif 1722 return 0; 1723 } 1724 1725 basereg = win * 8 + 0x1c; 1726 limitreg = win * 8 + 0x20; 1727 1728 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1729 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1730 return 1; 1731 } 1732 #endif 1733 1734 /* 1735 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1736 * int irq, 1737 * int level, 1738 * int (* func) __P((void *)), 1739 * void *arg) 1740 * 1741 * This function registers an interrupt handler at the bridge, in 1742 * order not to call the interrupt handlers of child devices when 1743 * a card-deletion interrupt occurs. 1744 * 1745 * The arguments irq and level are not used. 1746 */ 1747 static void * 1748 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1749 cardbus_chipset_tag_t ct; 1750 int irq, level; 1751 int (*func) __P((void *)); 1752 void *arg; 1753 { 1754 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1755 1756 return pccbb_intr_establish(sc, irq, level, func, arg); 1757 } 1758 1759 1760 /* 1761 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1762 * void *ih) 1763 * 1764 * This function removes an interrupt handler pointed by ih. 1765 */ 1766 static void 1767 pccbb_cb_intr_disestablish(ct, ih) 1768 cardbus_chipset_tag_t ct; 1769 void *ih; 1770 { 1771 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1772 1773 pccbb_intr_disestablish(sc, ih); 1774 } 1775 1776 1777 void 1778 pccbb_intr_route(sc) 1779 struct pccbb_softc *sc; 1780 { 1781 pcireg_t reg; 1782 1783 /* initialize bridge intr routing */ 1784 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1785 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1786 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1787 1788 switch (sc->sc_chipset) { 1789 case CB_TI113X: 1790 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1791 /* functional intr enabled */ 1792 reg |= PCI113X_CBCTRL_PCI_INTR; 1793 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1794 break; 1795 default: 1796 break; 1797 } 1798 } 1799 1800 /* 1801 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1802 * int irq, 1803 * int level, 1804 * int (* func) __P((void *)), 1805 * void *arg) 1806 * 1807 * This function registers an interrupt handler at the bridge, in 1808 * order not to call the interrupt handlers of child devices when 1809 * a card-deletion interrupt occurs. 1810 * 1811 * The arguments irq is not used because pccbb selects intr vector. 1812 */ 1813 static void * 1814 pccbb_intr_establish(sc, irq, level, func, arg) 1815 struct pccbb_softc *sc; 1816 int irq, level; 1817 int (*func) __P((void *)); 1818 void *arg; 1819 { 1820 struct pccbb_intrhand_list *pil, *newpil; 1821 1822 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1823 1824 if (LIST_EMPTY(&sc->sc_pil)) { 1825 pccbb_intr_route(sc); 1826 } 1827 1828 /* 1829 * Allocate a room for interrupt handler structure. 1830 */ 1831 if (NULL == (newpil = 1832 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1833 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1834 return NULL; 1835 } 1836 1837 newpil->pil_func = func; 1838 newpil->pil_arg = arg; 1839 newpil->pil_level = level; 1840 1841 if (LIST_EMPTY(&sc->sc_pil)) { 1842 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1843 } else { 1844 for (pil = LIST_FIRST(&sc->sc_pil); 1845 LIST_NEXT(pil, pil_next) != NULL; 1846 pil = LIST_NEXT(pil, pil_next)); 1847 LIST_INSERT_AFTER(pil, newpil, pil_next); 1848 } 1849 1850 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1851 LIST_FIRST(&sc->sc_pil))); 1852 1853 return newpil; 1854 } 1855 1856 /* 1857 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1858 * void *ih) 1859 * 1860 * This function removes an interrupt handler pointed by ih. ih 1861 * should be the value returned by cardbus_intr_establish() or 1862 * NULL. 1863 * 1864 * When ih is NULL, this function will do nothing. 1865 */ 1866 static void 1867 pccbb_intr_disestablish(sc, ih) 1868 struct pccbb_softc *sc; 1869 void *ih; 1870 { 1871 struct pccbb_intrhand_list *pil; 1872 pcireg_t reg; 1873 1874 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1875 LIST_FIRST(&sc->sc_pil))); 1876 1877 if (ih == NULL) { 1878 /* intr handler is not set */ 1879 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1880 return; 1881 } 1882 1883 #ifdef DIAGNOSTIC 1884 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1885 pil = LIST_NEXT(pil, pil_next)) { 1886 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1887 if (pil == ih) { 1888 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1889 break; 1890 } 1891 } 1892 if (pil == NULL) { 1893 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1894 sc->sc_dev.dv_xname, ih); 1895 } 1896 #endif 1897 1898 pil = (struct pccbb_intrhand_list *)ih; 1899 LIST_REMOVE(pil, pil_next); 1900 free(pil, M_DEVBUF); 1901 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1902 1903 if (LIST_EMPTY(&sc->sc_pil)) { 1904 /* No interrupt handlers */ 1905 1906 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1907 1908 /* stop routing PCI intr */ 1909 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1910 reg |= CB_BCR_INTR_IREQ_ENABLE; 1911 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1912 1913 switch (sc->sc_chipset) { 1914 case CB_TI113X: 1915 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1916 /* functional intr disabled */ 1917 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1918 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1919 break; 1920 default: 1921 break; 1922 } 1923 } 1924 } 1925 1926 #if defined SHOW_REGS 1927 static void 1928 cb_show_regs(pc, tag, memt, memh) 1929 pci_chipset_tag_t pc; 1930 pcitag_t tag; 1931 bus_space_tag_t memt; 1932 bus_space_handle_t memh; 1933 { 1934 int i; 1935 printf("PCI config regs:"); 1936 for (i = 0; i < 0x50; i += 4) { 1937 if (i % 16 == 0) { 1938 printf("\n 0x%02x:", i); 1939 } 1940 printf(" %08x", pci_conf_read(pc, tag, i)); 1941 } 1942 for (i = 0x80; i < 0xb0; i += 4) { 1943 if (i % 16 == 0) { 1944 printf("\n 0x%02x:", i); 1945 } 1946 printf(" %08x", pci_conf_read(pc, tag, i)); 1947 } 1948 1949 if (memh == 0) { 1950 printf("\n"); 1951 return; 1952 } 1953 1954 printf("\nsocket regs:"); 1955 for (i = 0; i <= 0x10; i += 0x04) { 1956 printf(" %08x", bus_space_read_4(memt, memh, i)); 1957 } 1958 printf("\nExCA regs:"); 1959 for (i = 0; i < 0x08; ++i) { 1960 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1961 } 1962 printf("\n"); 1963 return; 1964 } 1965 #endif 1966 1967 /* 1968 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1969 * int busno, int devno, int function) 1970 * This is the function to make a tag to access config space of 1971 * a CardBus Card. It works same as pci_conf_read. 1972 */ 1973 static cardbustag_t 1974 pccbb_make_tag(cc, busno, devno, function) 1975 cardbus_chipset_tag_t cc; 1976 int busno, devno, function; 1977 { 1978 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1979 1980 return pci_make_tag(sc->sc_pc, busno, devno, function); 1981 } 1982 1983 static void 1984 pccbb_free_tag(cc, tag) 1985 cardbus_chipset_tag_t cc; 1986 cardbustag_t tag; 1987 { 1988 } 1989 1990 /* 1991 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1992 * cardbustag_t tag, int offset) 1993 * This is the function to read the config space of a CardBus Card. 1994 * It works same as pci_conf_read. 1995 */ 1996 static cardbusreg_t 1997 pccbb_conf_read(cc, tag, offset) 1998 cardbus_chipset_tag_t cc; 1999 cardbustag_t tag; 2000 int offset; /* register offset */ 2001 { 2002 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2003 2004 return pci_conf_read(sc->sc_pc, tag, offset); 2005 } 2006 2007 /* 2008 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2009 * int offs, cardbusreg_t val) 2010 * This is the function to write the config space of a CardBus Card. 2011 * It works same as pci_conf_write. 2012 */ 2013 static void 2014 pccbb_conf_write(cc, tag, reg, val) 2015 cardbus_chipset_tag_t cc; 2016 cardbustag_t tag; 2017 int reg; /* register offset */ 2018 cardbusreg_t val; 2019 { 2020 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2021 2022 pci_conf_write(sc->sc_pc, tag, reg, val); 2023 } 2024 2025 #if 0 2026 STATIC int 2027 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2028 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2029 int speed, int flags, 2030 bus_space_handle_t * iohp) 2031 #endif 2032 /* 2033 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2034 * bus_addr_t start, bus_size_t size, 2035 * bus_size_t align, 2036 * struct pcmcia_io_handle *pcihp 2037 * 2038 * This function only allocates I/O region for pccard. This function 2039 * never maps the allocated region to pccard I/O area. 2040 * 2041 * XXX: The interface of this function is not very good, I believe. 2042 */ 2043 STATIC int 2044 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2045 pcmcia_chipset_handle_t pch; 2046 bus_addr_t start; /* start address */ 2047 bus_size_t size; 2048 bus_size_t align; 2049 struct pcmcia_io_handle *pcihp; 2050 { 2051 struct pcic_handle *ph = (struct pcic_handle *)pch; 2052 bus_addr_t ioaddr; 2053 int flags = 0; 2054 bus_space_tag_t iot; 2055 bus_space_handle_t ioh; 2056 bus_addr_t mask; 2057 #if rbus 2058 rbus_tag_t rb; 2059 #endif 2060 if (align == 0) { 2061 align = size; /* XXX: funny??? */ 2062 } 2063 2064 if (start != 0) { 2065 /* XXX: assume all card decode lower 10 bits by its hardware */ 2066 mask = 0x3ff; 2067 /* enforce to use only masked address */ 2068 start &= mask; 2069 } else { 2070 /* 2071 * calculate mask: 2072 * 1. get the most significant bit of size (call it msb). 2073 * 2. compare msb with the value of size. 2074 * 3. if size is larger, shift msb left once. 2075 * 4. obtain mask value to decrement msb. 2076 */ 2077 bus_size_t size_tmp = size; 2078 int shifts = 0; 2079 2080 mask = 1; 2081 while (size_tmp) { 2082 ++shifts; 2083 size_tmp >>= 1; 2084 } 2085 mask = (1 << shifts); 2086 if (mask < size) { 2087 mask <<= 1; 2088 } 2089 --mask; 2090 } 2091 2092 /* 2093 * Allocate some arbitrary I/O space. 2094 */ 2095 2096 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2097 2098 #if rbus 2099 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2100 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2101 return 1; 2102 } 2103 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2104 (u_long) ioaddr, (u_long) size)); 2105 #else 2106 if (start) { 2107 ioaddr = start; 2108 if (bus_space_map(iot, start, size, 0, &ioh)) { 2109 return 1; 2110 } 2111 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2112 (u_long) ioaddr, (u_long) size)); 2113 } else { 2114 flags |= PCMCIA_IO_ALLOCATED; 2115 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2116 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2117 size, align, 0, 0, &ioaddr, &ioh)) { 2118 /* No room be able to be get. */ 2119 return 1; 2120 } 2121 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2122 (u_long) ioaddr, (u_long) size)); 2123 } 2124 #endif 2125 2126 pcihp->iot = iot; 2127 pcihp->ioh = ioh; 2128 pcihp->addr = ioaddr; 2129 pcihp->size = size; 2130 pcihp->flags = flags; 2131 2132 return 0; 2133 } 2134 2135 /* 2136 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2137 * struct pcmcia_io_handle *pcihp) 2138 * 2139 * This function only frees I/O region for pccard. 2140 * 2141 * XXX: The interface of this function is not very good, I believe. 2142 */ 2143 void 2144 pccbb_pcmcia_io_free(pch, pcihp) 2145 pcmcia_chipset_handle_t pch; 2146 struct pcmcia_io_handle *pcihp; 2147 { 2148 #if !rbus 2149 bus_space_tag_t iot = pcihp->iot; 2150 #endif 2151 bus_space_handle_t ioh = pcihp->ioh; 2152 bus_size_t size = pcihp->size; 2153 2154 #if rbus 2155 struct pccbb_softc *sc = 2156 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2157 rbus_tag_t rb = sc->sc_rbus_iot; 2158 2159 rbus_space_free(rb, ioh, size, NULL); 2160 #else 2161 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2162 bus_space_free(iot, ioh, size); 2163 else 2164 bus_space_unmap(iot, ioh, size); 2165 #endif 2166 } 2167 2168 /* 2169 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2170 * bus_addr_t offset, bus_size_t size, 2171 * struct pcmcia_io_handle *pcihp, 2172 * int *windowp) 2173 * 2174 * This function maps the allocated I/O region to pccard. This function 2175 * never allocates any I/O region for pccard I/O area. I don't 2176 * understand why the original authors of pcmciabus separated alloc and 2177 * map. I believe the two must be unite. 2178 * 2179 * XXX: no wait timing control? 2180 */ 2181 int 2182 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2183 pcmcia_chipset_handle_t pch; 2184 int width; 2185 bus_addr_t offset; 2186 bus_size_t size; 2187 struct pcmcia_io_handle *pcihp; 2188 int *windowp; 2189 { 2190 struct pcic_handle *ph = (struct pcic_handle *)pch; 2191 bus_addr_t ioaddr = pcihp->addr + offset; 2192 int i, win; 2193 #if defined CBB_DEBUG 2194 static char *width_names[] = { "dynamic", "io8", "io16" }; 2195 #endif 2196 2197 /* Sanity check I/O handle. */ 2198 2199 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2200 panic("pccbb_pcmcia_io_map iot is bogus"); 2201 } 2202 2203 /* XXX Sanity check offset/size. */ 2204 2205 win = -1; 2206 for (i = 0; i < PCIC_IO_WINS; i++) { 2207 if ((ph->ioalloc & (1 << i)) == 0) { 2208 win = i; 2209 ph->ioalloc |= (1 << i); 2210 break; 2211 } 2212 } 2213 2214 if (win == -1) { 2215 return 1; 2216 } 2217 2218 *windowp = win; 2219 2220 /* XXX this is pretty gross */ 2221 2222 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2223 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2224 2225 /* XXX wtf is this doing here? */ 2226 2227 #if 0 2228 printf(" port 0x%lx", (u_long) ioaddr); 2229 if (size > 1) { 2230 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2231 } 2232 #endif 2233 2234 ph->io[win].addr = ioaddr; 2235 ph->io[win].size = size; 2236 ph->io[win].width = width; 2237 2238 /* actual dirty register-value changing in the function below. */ 2239 pccbb_pcmcia_do_io_map(ph, win); 2240 2241 return 0; 2242 } 2243 2244 /* 2245 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2246 * 2247 * This function changes register-value to map I/O region for pccard. 2248 */ 2249 static void 2250 pccbb_pcmcia_do_io_map(ph, win) 2251 struct pcic_handle *ph; 2252 int win; 2253 { 2254 static u_int8_t pcic_iowidth[3] = { 2255 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2256 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2257 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2258 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2259 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2260 }; 2261 2262 #define PCIC_SIA_START_LOW 0 2263 #define PCIC_SIA_START_HIGH 1 2264 #define PCIC_SIA_STOP_LOW 2 2265 #define PCIC_SIA_STOP_HIGH 3 2266 2267 int regbase_win = 0x8 + win * 0x04; 2268 u_int8_t ioctl, enable; 2269 2270 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2271 "width %d\n", win, (unsigned long)ph->io[win].addr, 2272 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2273 2274 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2275 ph->io[win].addr & 0xff); 2276 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2277 (ph->io[win].addr >> 8) & 0xff); 2278 2279 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2280 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2281 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2282 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2283 2284 ioctl = Pcic_read(ph, PCIC_IOCTL); 2285 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2286 switch (win) { 2287 case 0: 2288 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2289 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2290 PCIC_IOCTL_IO0_DATASIZE_MASK); 2291 ioctl |= pcic_iowidth[ph->io[win].width]; 2292 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2293 break; 2294 case 1: 2295 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2296 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2297 PCIC_IOCTL_IO1_DATASIZE_MASK); 2298 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2299 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2300 break; 2301 } 2302 Pcic_write(ph, PCIC_IOCTL, ioctl); 2303 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2304 #if defined CBB_DEBUG 2305 { 2306 u_int8_t start_low = 2307 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2308 u_int8_t start_high = 2309 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2310 u_int8_t stop_low = 2311 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2312 u_int8_t stop_high = 2313 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2314 printf 2315 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2316 start_low, start_high, stop_low, stop_high, ioctl, enable); 2317 } 2318 #endif 2319 } 2320 2321 /* 2322 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2323 * 2324 * This function unmaps I/O region. No return value. 2325 */ 2326 STATIC void 2327 pccbb_pcmcia_io_unmap(pch, win) 2328 pcmcia_chipset_handle_t pch; 2329 int win; 2330 { 2331 struct pcic_handle *ph = (struct pcic_handle *)pch; 2332 int reg; 2333 2334 if (win >= PCIC_IO_WINS || win < 0) { 2335 panic("pccbb_pcmcia_io_unmap: window out of range"); 2336 } 2337 2338 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2339 switch (win) { 2340 case 0: 2341 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2342 break; 2343 case 1: 2344 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2345 break; 2346 } 2347 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2348 2349 ph->ioalloc &= ~(1 << win); 2350 } 2351 2352 /* 2353 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2354 * 2355 * This function enables the card. All information is stored in 2356 * the first argument, pcmcia_chipset_handle_t. 2357 */ 2358 static int 2359 pccbb_pcmcia_wait_ready(ph) 2360 struct pcic_handle *ph; 2361 { 2362 u_char stat; 2363 int i; 2364 2365 DPRINTF(("entering pccbb_pcmcia_wait_ready: status 0x%02x\n", 2366 Pcic_read(ph, PCIC_IF_STATUS))); 2367 2368 for (i = 0; i < 2000; i++) { 2369 stat = Pcic_read(ph, PCIC_IF_STATUS); 2370 if (stat & PCIC_IF_STATUS_READY) 2371 return 1; 2372 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2373 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2374 return 0; 2375 DELAY_MS(2, ph->ph_parent); 2376 #ifdef CBB_DEBUG 2377 if ((i > 1000) && (i % 25 == 24)) 2378 printf("."); 2379 #endif 2380 } 2381 2382 #ifdef DIAGNOSTIC 2383 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2384 Pcic_read(ph, PCIC_IF_STATUS)); 2385 #endif 2386 2387 return 0; 2388 } 2389 2390 /* 2391 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2392 * 2393 * This function enables the card. All information is stored in 2394 * the first argument, pcmcia_chipset_handle_t. 2395 */ 2396 STATIC void 2397 pccbb_pcmcia_socket_enable(pch) 2398 pcmcia_chipset_handle_t pch; 2399 { 2400 struct pcic_handle *ph = (struct pcic_handle *)pch; 2401 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2402 int cardtype, win; 2403 u_int8_t power, intr; 2404 pcireg_t spsr; 2405 int voltage; 2406 2407 /* this bit is mostly stolen from pcic_attach_card */ 2408 2409 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2410 2411 /* get card Vcc info */ 2412 2413 spsr = 2414 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2415 CB_SOCKET_STAT); 2416 if (spsr & CB_SOCKET_STAT_5VCARD) { 2417 DPRINTF(("5V card\n")); 2418 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2419 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2420 DPRINTF(("3V card\n")); 2421 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2422 } else { 2423 printf("?V card, 0x%x\n", spsr); /* XXX */ 2424 return; 2425 } 2426 2427 /* disable socket: negate output enable bit and power off */ 2428 2429 power = 0; 2430 Pcic_write(ph, PCIC_PWRCTL, power); 2431 2432 /* power down the socket to reset it, clear the card reset pin */ 2433 2434 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2435 2436 /* 2437 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2438 * we are changing Vcc (Toff). 2439 */ 2440 /* delay(300*1000); too much */ 2441 2442 /* assert reset bit */ 2443 intr = Pcic_read(ph, PCIC_INTR); 2444 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2445 Pcic_write(ph, PCIC_INTR, intr); 2446 2447 /* power up the socket */ 2448 power = Pcic_read(ph, PCIC_PWRCTL); 2449 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 2450 pccbb_power(sc, voltage); 2451 2452 /* now output enable */ 2453 power = Pcic_read(ph, PCIC_PWRCTL); 2454 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2455 2456 if (pccbb_power(sc, voltage) == 0) { 2457 power &= PCIC_PWRCTL_OE; 2458 Pcic_write(ph, PCIC_PWRCTL, power); 2459 intr |= PCIC_INTR_RESET; 2460 Pcic_write(ph, PCIC_INTR, intr); 2461 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2462 return; 2463 } 2464 2465 /* 2466 * hold RESET at least 20 ms: the spec says only 10 us is 2467 * enough, but TI1130 requires at least 20 ms. 2468 */ 2469 #if 0 /* XXX called on interrupt context */ 2470 DELAY_MS(20, sc); 2471 #else 2472 delay(20 * 1000); 2473 #endif 2474 2475 /* clear the reset flag */ 2476 2477 intr |= PCIC_INTR_RESET; 2478 Pcic_write(ph, PCIC_INTR, intr); 2479 2480 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2481 2482 #if 0 /* XXX called on interrupt context */ 2483 DELAY_MS(20, sc); 2484 #else 2485 delay(20 * 1000); 2486 #endif 2487 2488 /* wait for the chip to finish initializing */ 2489 2490 if (pccbb_pcmcia_wait_ready(ph) == 0) { 2491 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2492 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2493 return; 2494 } 2495 2496 /* zero out the address windows */ 2497 2498 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2499 2500 /* set the card type */ 2501 2502 cardtype = pcmcia_card_gettype(ph->pcmcia); 2503 2504 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2505 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2506 Pcic_write(ph, PCIC_INTR, intr); 2507 2508 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2509 ph->ph_parent->dv_xname, ph->sock, 2510 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2511 2512 /* reinstall all the memory and io mappings */ 2513 2514 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2515 if (ph->memalloc & (1 << win)) { 2516 pccbb_pcmcia_do_mem_map(ph, win); 2517 } 2518 } 2519 2520 for (win = 0; win < PCIC_IO_WINS; ++win) { 2521 if (ph->ioalloc & (1 << win)) { 2522 pccbb_pcmcia_do_io_map(ph, win); 2523 } 2524 } 2525 } 2526 2527 /* 2528 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2529 * 2530 * This function disables the card. All information is stored in 2531 * the first argument, pcmcia_chipset_handle_t. 2532 */ 2533 STATIC void 2534 pccbb_pcmcia_socket_disable(pch) 2535 pcmcia_chipset_handle_t pch; 2536 { 2537 struct pcic_handle *ph = (struct pcic_handle *)pch; 2538 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2539 u_int8_t power, intr; 2540 2541 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2542 2543 /* reset signal asserting... */ 2544 2545 intr = Pcic_read(ph, PCIC_INTR); 2546 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2547 Pcic_write(ph, PCIC_INTR, intr); 2548 delay(2 * 1000); 2549 2550 /* power down the socket */ 2551 power = Pcic_read(ph, PCIC_PWRCTL); 2552 power &= ~PCIC_PWRCTL_OE; 2553 Pcic_write(ph, PCIC_PWRCTL, power); 2554 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2555 /* 2556 * wait 300ms until power fails (Tpf). 2557 */ 2558 #if 0 /* XXX called on interrupt context */ 2559 DELAY_MS(300, sc); 2560 #else 2561 delay(300 * 1000); 2562 #endif 2563 } 2564 2565 /* 2566 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2567 * 2568 * This function detects whether a card is in the slot or not. 2569 * If a card is inserted, return 1. Otherwise, return 0. 2570 */ 2571 STATIC int 2572 pccbb_pcmcia_card_detect(pch) 2573 pcmcia_chipset_handle_t pch; 2574 { 2575 struct pcic_handle *ph = (struct pcic_handle *)pch; 2576 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2577 2578 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2579 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2580 } 2581 2582 #if 0 2583 STATIC int 2584 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2585 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2586 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2587 #endif 2588 /* 2589 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2590 * bus_size_t size, 2591 * struct pcmcia_mem_handle *pcmhp) 2592 * 2593 * This function only allocates memory region for pccard. This 2594 * function never maps the allocated region to pccard memory area. 2595 * 2596 * XXX: Why the argument of start address is not in? 2597 */ 2598 STATIC int 2599 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2600 pcmcia_chipset_handle_t pch; 2601 bus_size_t size; 2602 struct pcmcia_mem_handle *pcmhp; 2603 { 2604 struct pcic_handle *ph = (struct pcic_handle *)pch; 2605 bus_space_handle_t memh; 2606 bus_addr_t addr; 2607 bus_size_t sizepg; 2608 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2609 #if rbus 2610 rbus_tag_t rb; 2611 #endif 2612 2613 /* Check that the card is still there. */ 2614 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2615 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2616 return 1; 2617 2618 /* out of sc->memh, allocate as many pages as necessary */ 2619 2620 /* convert size to PCIC pages */ 2621 /* 2622 * This is not enough; when the requested region is on the page 2623 * boundaries, this may calculate wrong result. 2624 */ 2625 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2626 #if 0 2627 if (sizepg > PCIC_MAX_MEM_PAGES) { 2628 return 1; 2629 } 2630 #endif 2631 2632 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2633 return 1; 2634 } 2635 2636 addr = 0; /* XXX gcc -Wuninitialized */ 2637 2638 #if rbus 2639 rb = sc->sc_rbus_memt; 2640 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2641 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2642 &addr, &memh)) { 2643 return 1; 2644 } 2645 #else 2646 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2647 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2648 0, /* boundary */ 2649 0, /* flags */ 2650 &addr, &memh)) { 2651 return 1; 2652 } 2653 #endif 2654 2655 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2656 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2657 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2658 2659 pcmhp->memt = sc->sc_memt; 2660 pcmhp->memh = memh; 2661 pcmhp->addr = addr; 2662 pcmhp->size = size; 2663 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2664 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2665 pcmhp->mhandle = 0; 2666 /* No offset??? Funny. */ 2667 2668 return 0; 2669 } 2670 2671 /* 2672 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2673 * struct pcmcia_mem_handle *pcmhp) 2674 * 2675 * This function release the memory space allocated by the function 2676 * pccbb_pcmcia_mem_alloc(). 2677 */ 2678 STATIC void 2679 pccbb_pcmcia_mem_free(pch, pcmhp) 2680 pcmcia_chipset_handle_t pch; 2681 struct pcmcia_mem_handle *pcmhp; 2682 { 2683 #if rbus 2684 struct pcic_handle *ph = (struct pcic_handle *)pch; 2685 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2686 2687 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2688 #else 2689 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2690 #endif 2691 } 2692 2693 /* 2694 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2695 * 2696 * This function release the memory space allocated by the function 2697 * pccbb_pcmcia_mem_alloc(). 2698 */ 2699 STATIC void 2700 pccbb_pcmcia_do_mem_map(ph, win) 2701 struct pcic_handle *ph; 2702 int win; 2703 { 2704 int regbase_win; 2705 bus_addr_t phys_addr; 2706 bus_addr_t phys_end; 2707 2708 #define PCIC_SMM_START_LOW 0 2709 #define PCIC_SMM_START_HIGH 1 2710 #define PCIC_SMM_STOP_LOW 2 2711 #define PCIC_SMM_STOP_HIGH 3 2712 #define PCIC_CMA_LOW 4 2713 #define PCIC_CMA_HIGH 5 2714 2715 u_int8_t start_low, start_high = 0; 2716 u_int8_t stop_low, stop_high; 2717 u_int8_t off_low, off_high; 2718 u_int8_t mem_window; 2719 int reg; 2720 2721 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2722 int mem8 = 2723 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2724 || (kind == PCMCIA_MEM_ATTR); 2725 2726 regbase_win = 0x10 + win * 0x08; 2727 2728 phys_addr = ph->mem[win].addr; 2729 phys_end = phys_addr + ph->mem[win].size; 2730 2731 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2732 (unsigned long)phys_addr, (unsigned long)phys_end, 2733 (unsigned long)ph->mem[win].offset)); 2734 2735 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2736 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2737 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2738 2739 /* bit 19:12 */ 2740 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2741 /* bit 23:20 and bit 7 on */ 2742 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2743 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2744 /* bit 31:24, for 32-bit address */ 2745 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2746 2747 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2748 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2749 2750 if (((struct pccbb_softc *)ph-> 2751 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2752 Pcic_write(ph, 0x40 + win, mem_window); 2753 } 2754 2755 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2756 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2757 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2758 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2759 2760 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2761 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2762 2763 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2764 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2765 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2766 | ((kind == PCMCIA_MEM_ATTR) ? 2767 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2768 2769 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2770 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2771 2772 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2773 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2774 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2775 2776 #if defined CBB_DEBUG 2777 { 2778 int r1, r2, r3, r4, r5, r6, r7 = 0; 2779 2780 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2781 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2782 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2783 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2784 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2785 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2786 if (((struct pccbb_softc *)(ph-> 2787 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2788 r7 = Pcic_read(ph, 0x40 + win); 2789 } 2790 2791 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2792 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2793 if (((struct pccbb_softc *)(ph-> 2794 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2795 DPRINTF((" %02x", r7)); 2796 } 2797 DPRINTF(("\n")); 2798 } 2799 #endif 2800 } 2801 2802 /* 2803 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2804 * bus_addr_t card_addr, bus_size_t size, 2805 * struct pcmcia_mem_handle *pcmhp, 2806 * bus_addr_t *offsetp, int *windowp) 2807 * 2808 * This function maps memory space allocated by the function 2809 * pccbb_pcmcia_mem_alloc(). 2810 */ 2811 STATIC int 2812 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2813 pcmcia_chipset_handle_t pch; 2814 int kind; 2815 bus_addr_t card_addr; 2816 bus_size_t size; 2817 struct pcmcia_mem_handle *pcmhp; 2818 bus_addr_t *offsetp; 2819 int *windowp; 2820 { 2821 struct pcic_handle *ph = (struct pcic_handle *)pch; 2822 bus_addr_t busaddr; 2823 long card_offset; 2824 int win; 2825 2826 /* Check that the card is still there. */ 2827 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2828 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2829 return 1; 2830 2831 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2832 if ((ph->memalloc & (1 << win)) == 0) { 2833 ph->memalloc |= (1 << win); 2834 break; 2835 } 2836 } 2837 2838 if (win == PCIC_MEM_WINS) { 2839 return 1; 2840 } 2841 2842 *windowp = win; 2843 2844 /* XXX this is pretty gross */ 2845 2846 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2847 panic("pccbb_pcmcia_mem_map memt is bogus"); 2848 } 2849 2850 busaddr = pcmhp->addr; 2851 2852 /* 2853 * compute the address offset to the pcmcia address space for the 2854 * pcic. this is intentionally signed. The masks and shifts below 2855 * will cause TRT to happen in the pcic registers. Deal with making 2856 * sure the address is aligned, and return the alignment offset. 2857 */ 2858 2859 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2860 card_addr -= *offsetp; 2861 2862 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2863 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2864 (u_long) card_addr)); 2865 2866 /* 2867 * include the offset in the size, and decrement size by one, since 2868 * the hw wants start/stop 2869 */ 2870 size += *offsetp - 1; 2871 2872 card_offset = (((long)card_addr) - ((long)busaddr)); 2873 2874 ph->mem[win].addr = busaddr; 2875 ph->mem[win].size = size; 2876 ph->mem[win].offset = card_offset; 2877 ph->mem[win].kind = kind; 2878 2879 pccbb_pcmcia_do_mem_map(ph, win); 2880 2881 return 0; 2882 } 2883 2884 /* 2885 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2886 * int window) 2887 * 2888 * This function unmaps memory space which mapped by the function 2889 * pccbb_pcmcia_mem_map(). 2890 */ 2891 STATIC void 2892 pccbb_pcmcia_mem_unmap(pch, window) 2893 pcmcia_chipset_handle_t pch; 2894 int window; 2895 { 2896 struct pcic_handle *ph = (struct pcic_handle *)pch; 2897 int reg; 2898 2899 if (window >= PCIC_MEM_WINS) { 2900 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2901 } 2902 2903 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2904 reg &= ~(1 << window); 2905 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2906 2907 ph->memalloc &= ~(1 << window); 2908 } 2909 2910 #if defined PCCBB_PCMCIA_POLL 2911 struct pccbb_poll_str { 2912 void *arg; 2913 int (*func) __P((void *)); 2914 int level; 2915 struct pcic_handle *ph; 2916 int count; 2917 int num; 2918 struct callout poll_ch; 2919 }; 2920 2921 static struct pccbb_poll_str pccbb_poll[10]; 2922 static int pccbb_poll_n = 0; 2923 2924 static void pccbb_pcmcia_poll __P((void *arg)); 2925 2926 static void 2927 pccbb_pcmcia_poll(arg) 2928 void *arg; 2929 { 2930 struct pccbb_poll_str *poll = arg; 2931 struct pcic_handle *ph = poll->ph; 2932 struct pccbb_softc *sc = ph->sc; 2933 int s; 2934 u_int32_t spsr; /* socket present-state reg */ 2935 2936 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2937 switch (poll->level) { 2938 case IPL_NET: 2939 s = splnet(); 2940 break; 2941 case IPL_BIO: 2942 s = splbio(); 2943 break; 2944 case IPL_TTY: /* fallthrough */ 2945 default: 2946 s = spltty(); 2947 break; 2948 } 2949 2950 spsr = 2951 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2952 CB_SOCKET_STAT); 2953 2954 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2955 if (!(spsr & 0x40)) /* CINT low */ 2956 #else 2957 if (1) 2958 #endif 2959 { 2960 if ((*poll->func) (poll->arg) > 0) { 2961 ++poll->count; 2962 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2963 #if defined LEVEL2 2964 } else { 2965 printf("intr: miss! 0x%x\n", spsr); 2966 #endif 2967 } 2968 } 2969 splx(s); 2970 } 2971 #endif /* defined CB_PCMCIA_POLL */ 2972 2973 /* 2974 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2975 * struct pcmcia_function *pf, 2976 * int ipl, 2977 * int (*func)(void *), 2978 * void *arg); 2979 * 2980 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2981 */ 2982 STATIC void * 2983 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2984 pcmcia_chipset_handle_t pch; 2985 struct pcmcia_function *pf; 2986 int ipl; 2987 int (*func) __P((void *)); 2988 void *arg; 2989 { 2990 struct pcic_handle *ph = (struct pcic_handle *)pch; 2991 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2992 2993 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2994 /* what should I do? */ 2995 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2996 DPRINTF(("%s does not provide edge nor pulse " 2997 "interrupt\n", sc->sc_dev.dv_xname)); 2998 return NULL; 2999 } 3000 /* 3001 * XXX Noooooo! The interrupt flag must set properly!! 3002 * dumb pcmcia driver!! 3003 */ 3004 } 3005 3006 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3007 } 3008 3009 /* 3010 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3011 * void *ih) 3012 * 3013 * This function disables PC-Card interrupt. 3014 */ 3015 STATIC void 3016 pccbb_pcmcia_intr_disestablish(pch, ih) 3017 pcmcia_chipset_handle_t pch; 3018 void *ih; 3019 { 3020 struct pcic_handle *ph = (struct pcic_handle *)pch; 3021 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3022 3023 pccbb_intr_disestablish(sc, ih); 3024 } 3025 3026 #if rbus 3027 /* 3028 * static int 3029 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3030 * bus_addr_t addr, bus_size_t size, 3031 * bus_addr_t mask, bus_size_t align, 3032 * int flags, bus_addr_t *addrp; 3033 * bus_space_handle_t *bshp) 3034 * 3035 * This function allocates a portion of memory or io space for 3036 * clients. This function is called from CardBus card drivers. 3037 */ 3038 static int 3039 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3040 cardbus_chipset_tag_t ct; 3041 rbus_tag_t rb; 3042 bus_addr_t addr; 3043 bus_size_t size; 3044 bus_addr_t mask; 3045 bus_size_t align; 3046 int flags; 3047 bus_addr_t *addrp; 3048 bus_space_handle_t *bshp; 3049 { 3050 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3051 3052 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3053 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3054 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3055 3056 if (align == 0) { 3057 align = size; 3058 } 3059 3060 if (rb->rb_bt == sc->sc_memt) { 3061 if (align < 16) { 3062 return 1; 3063 } 3064 /* 3065 * XXX: align more than 0x1000 to avoid overwrapping 3066 * memory windows for two or more devices. 0x1000 3067 * means memory window's granularity. 3068 * 3069 * Two or more devices should be able to share same 3070 * memory window region. However, overrapping memory 3071 * window is not good because some devices, such as 3072 * 3Com 3C575[BC], have a broken address decoder and 3073 * intrude other's memory region. 3074 */ 3075 if (align < 0x1000) { 3076 align = 0x1000; 3077 } 3078 } else if (rb->rb_bt == sc->sc_iot) { 3079 if (align < 4) { 3080 return 1; 3081 } 3082 /* XXX: hack for avoiding ISA image */ 3083 if (mask < 0x0100) { 3084 mask = 0x3ff; 3085 addr = 0x300; 3086 } 3087 3088 } else { 3089 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3090 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3091 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3092 (unsigned long)sc->sc_memt)); 3093 return 1; 3094 /* XXX: panic here? */ 3095 } 3096 3097 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3098 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3099 return 1; 3100 } 3101 3102 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3103 3104 return 0; 3105 } 3106 3107 /* 3108 * static int 3109 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3110 * bus_space_handle_t *bshp, bus_size_t size); 3111 * 3112 * This function is called from CardBus card drivers. 3113 */ 3114 static int 3115 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3116 cardbus_chipset_tag_t ct; 3117 rbus_tag_t rb; 3118 bus_space_handle_t bsh; 3119 bus_size_t size; 3120 { 3121 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3122 bus_space_tag_t bt = rb->rb_bt; 3123 3124 pccbb_close_win(sc, bt, bsh, size); 3125 3126 if (bt == sc->sc_memt) { 3127 } else if (bt == sc->sc_iot) { 3128 } else { 3129 return 1; 3130 /* XXX: panic here? */ 3131 } 3132 3133 return rbus_space_free(rb, bsh, size, NULL); 3134 } 3135 #endif /* rbus */ 3136 3137 #if rbus 3138 3139 static int 3140 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3141 struct pccbb_softc *sc; 3142 bus_space_tag_t bst; 3143 bus_addr_t addr; 3144 bus_size_t size; 3145 bus_space_handle_t bsh; 3146 int flags; 3147 { 3148 struct pccbb_win_chain_head *head; 3149 bus_addr_t align; 3150 3151 head = &sc->sc_iowindow; 3152 align = 0x04; 3153 if (sc->sc_memt == bst) { 3154 head = &sc->sc_memwindow; 3155 align = 0x1000; 3156 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3157 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3158 (unsigned long)bst)); 3159 } 3160 3161 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3162 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3163 sc->sc_dev.dv_xname, 3164 (head == &sc->sc_memwindow) ? "mem" : "io"); 3165 } 3166 pccbb_winset(align, sc, bst); 3167 3168 return 0; 3169 } 3170 3171 static int 3172 pccbb_close_win(sc, bst, bsh, size) 3173 struct pccbb_softc *sc; 3174 bus_space_tag_t bst; 3175 bus_space_handle_t bsh; 3176 bus_size_t size; 3177 { 3178 struct pccbb_win_chain_head *head; 3179 bus_addr_t align; 3180 3181 head = &sc->sc_iowindow; 3182 align = 0x04; 3183 if (sc->sc_memt == bst) { 3184 head = &sc->sc_memwindow; 3185 align = 0x1000; 3186 } 3187 3188 if (pccbb_winlist_delete(head, bsh, size)) { 3189 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3190 sc->sc_dev.dv_xname, 3191 (head == &sc->sc_memwindow) ? "mem" : "io"); 3192 } 3193 pccbb_winset(align, sc, bst); 3194 3195 return 0; 3196 } 3197 3198 static int 3199 pccbb_winlist_insert(head, start, size, bsh, flags) 3200 struct pccbb_win_chain_head *head; 3201 bus_addr_t start; 3202 bus_size_t size; 3203 bus_space_handle_t bsh; 3204 int flags; 3205 { 3206 struct pccbb_win_chain *chainp, *elem; 3207 3208 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3209 M_NOWAIT)) == NULL) 3210 return (1); /* fail */ 3211 3212 elem->wc_start = start; 3213 elem->wc_end = start + (size - 1); 3214 elem->wc_handle = bsh; 3215 elem->wc_flags = flags; 3216 3217 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3218 chainp = TAILQ_NEXT(chainp, wc_list)) { 3219 if (chainp->wc_end < start) 3220 continue; 3221 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3222 return (0); 3223 } 3224 3225 TAILQ_INSERT_TAIL(head, elem, wc_list); 3226 return (0); 3227 } 3228 3229 static int 3230 pccbb_winlist_delete(head, bsh, size) 3231 struct pccbb_win_chain_head *head; 3232 bus_space_handle_t bsh; 3233 bus_size_t size; 3234 { 3235 struct pccbb_win_chain *chainp; 3236 3237 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3238 chainp = TAILQ_NEXT(chainp, wc_list)) { 3239 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3240 continue; 3241 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3242 printf("pccbb_winlist_delete: window 0x%lx size " 3243 "inconsistent: 0x%lx, 0x%lx\n", 3244 (unsigned long)chainp->wc_start, 3245 (unsigned long)(chainp->wc_end - chainp->wc_start), 3246 (unsigned long)(size - 1)); 3247 return 1; 3248 } 3249 3250 TAILQ_REMOVE(head, chainp, wc_list); 3251 free(chainp, M_DEVBUF); 3252 3253 return 0; 3254 } 3255 3256 return 1; /* fail: no candidate to remove */ 3257 } 3258 3259 static void 3260 pccbb_winset(align, sc, bst) 3261 bus_addr_t align; 3262 struct pccbb_softc *sc; 3263 bus_space_tag_t bst; 3264 { 3265 pci_chipset_tag_t pc; 3266 pcitag_t tag; 3267 bus_addr_t mask = ~(align - 1); 3268 struct { 3269 cardbusreg_t win_start; 3270 cardbusreg_t win_limit; 3271 int win_flags; 3272 } win[2]; 3273 struct pccbb_win_chain *chainp; 3274 int offs; 3275 3276 win[0].win_start = win[1].win_start = 0xffffffff; 3277 win[0].win_limit = win[1].win_limit = 0; 3278 win[0].win_flags = win[1].win_flags = 0; 3279 3280 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3281 offs = 0x2c; 3282 if (sc->sc_memt == bst) { 3283 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3284 offs = 0x1c; 3285 } 3286 3287 if (chainp != NULL) { 3288 win[0].win_start = chainp->wc_start & mask; 3289 win[0].win_limit = chainp->wc_end & mask; 3290 win[0].win_flags = chainp->wc_flags; 3291 chainp = TAILQ_NEXT(chainp, wc_list); 3292 } 3293 3294 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3295 if (win[1].win_start == 0xffffffff) { 3296 /* window 1 is not used */ 3297 if ((win[0].win_flags == chainp->wc_flags) && 3298 (win[0].win_limit + align >= 3299 (chainp->wc_start & mask))) { 3300 /* concatenate */ 3301 win[0].win_limit = chainp->wc_end & mask; 3302 } else { 3303 /* make new window */ 3304 win[1].win_start = chainp->wc_start & mask; 3305 win[1].win_limit = chainp->wc_end & mask; 3306 win[1].win_flags = chainp->wc_flags; 3307 } 3308 continue; 3309 } 3310 3311 /* Both windows are engaged. */ 3312 if (win[0].win_flags == win[1].win_flags) { 3313 /* same flags */ 3314 if (win[0].win_flags == chainp->wc_flags) { 3315 if (win[1].win_start - (win[0].win_limit + 3316 align) < 3317 (chainp->wc_start & mask) - 3318 ((chainp->wc_end & mask) + align)) { 3319 /* 3320 * merge window 0 and 1, and set win1 3321 * to chainp 3322 */ 3323 win[0].win_limit = win[1].win_limit; 3324 win[1].win_start = 3325 chainp->wc_start & mask; 3326 win[1].win_limit = 3327 chainp->wc_end & mask; 3328 } else { 3329 win[1].win_limit = 3330 chainp->wc_end & mask; 3331 } 3332 } else { 3333 /* different flags */ 3334 3335 /* concatenate win0 and win1 */ 3336 win[0].win_limit = win[1].win_limit; 3337 /* allocate win[1] to new space */ 3338 win[1].win_start = chainp->wc_start & mask; 3339 win[1].win_limit = chainp->wc_end & mask; 3340 win[1].win_flags = chainp->wc_flags; 3341 } 3342 } else { 3343 /* the flags of win[0] and win[1] is different */ 3344 if (win[0].win_flags == chainp->wc_flags) { 3345 win[0].win_limit = chainp->wc_end & mask; 3346 /* 3347 * XXX this creates overlapping windows, so 3348 * what should the poor bridge do if one is 3349 * cachable, and the other is not? 3350 */ 3351 printf("%s: overlapping windows\n", 3352 sc->sc_dev.dv_xname); 3353 } else { 3354 win[1].win_limit = chainp->wc_end & mask; 3355 } 3356 } 3357 } 3358 3359 pc = sc->sc_pc; 3360 tag = sc->sc_tag; 3361 pci_conf_write(pc, tag, offs, win[0].win_start); 3362 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3363 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3364 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3365 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3366 (unsigned long)pci_conf_read(pc, tag, offs), 3367 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3368 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3369 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3370 3371 if (bst == sc->sc_memt) { 3372 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3373 3374 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3375 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3376 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3377 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3378 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3379 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3380 } 3381 } 3382 3383 #endif /* rbus */ 3384 3385 static void 3386 pccbb_powerhook(why, arg) 3387 int why; 3388 void *arg; 3389 { 3390 struct pccbb_softc *sc = arg; 3391 pcireg_t reg; 3392 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3393 bus_space_handle_t base_memh = sc->sc_base_memh; 3394 3395 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3396 3397 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3398 DPRINTF(("%s: power: why %d stopping intr\n", 3399 sc->sc_dev.dv_xname, why)); 3400 if (sc->sc_pil_intr_enable) { 3401 (void)pccbbintr_function(sc); 3402 } 3403 sc->sc_pil_intr_enable = 0; 3404 3405 /* ToDo: deactivate or suspend child devices */ 3406 3407 } 3408 3409 if (why == PWR_RESUME) { 3410 if (sc->sc_pwrmgt_offs != 0) { 3411 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3412 sc->sc_pwrmgt_offs + 4); 3413 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3414 reg & 0x100) { 3415 /* powrstate != D0 */ 3416 3417 printf("%s going back to D0 mode\n", 3418 sc->sc_dev.dv_xname); 3419 reg &= ~PCI_PMCSR_STATE_MASK; 3420 reg |= PCI_PMCSR_STATE_D0; 3421 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3422 pci_conf_write(sc->sc_pc, sc->sc_tag, 3423 sc->sc_pwrmgt_offs + 4, reg); 3424 3425 pci_conf_write(sc->sc_pc, sc->sc_tag, 3426 PCI_SOCKBASE, sc->sc_sockbase); 3427 pci_conf_write(sc->sc_pc, sc->sc_tag, 3428 PCI_BUSNUM, sc->sc_busnum); 3429 pccbb_chipinit(sc); 3430 /* setup memory and io space window for CB */ 3431 pccbb_winset(0x1000, sc, sc->sc_memt); 3432 pccbb_winset(0x04, sc, sc->sc_iot); 3433 } 3434 } 3435 3436 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3437 /* BIOS did not recover this register */ 3438 pci_conf_write (sc->sc_pc, sc->sc_tag, 3439 PCI_SOCKBASE, sc->sc_sockbase); 3440 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3441 /* BIOS did not recover this register */ 3442 pci_conf_write (sc->sc_pc, sc->sc_tag, 3443 PCI_BUSNUM, sc->sc_busnum); 3444 /* CSC Interrupt: Card detect interrupt on */ 3445 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3446 /* Card detect intr is turned on. */ 3447 reg |= CB_SOCKET_MASK_CD; 3448 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3449 /* reset interrupt */ 3450 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3451 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3452 3453 /* 3454 * check for card insertion or removal during suspend period. 3455 * XXX: the code can't cope with card swap (remove then 3456 * insert). how can we detect such situation? 3457 */ 3458 (void)pccbbintr(sc); 3459 3460 sc->sc_pil_intr_enable = 1; 3461 DPRINTF(("%s: power: RESUME enabling intr\n", 3462 sc->sc_dev.dv_xname)); 3463 3464 /* ToDo: activate or wakeup child devices */ 3465 } 3466 } 3467
Indexes created Fri Sep 26 08:10:20 GMT 2025