pccbb.c revision 1.99
1 /* $NetBSD: pccbb.c,v 1.99 2004/07/28 15:32:49 he Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.99 2004/07/28 15:32:49 he Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 #define PCCBB_PCMCIA_POLL 40 */ 41 /* #define CBB_DEBUG */ 42 43 /* 44 #define CB_PCMCIA_POLL 45 #define CB_PCMCIA_POLL_ONLY 46 #define LEVEL2 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/ioctl.h> 54 #include <sys/reboot.h> /* for bootverbose */ 55 #include <sys/syslog.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 60 #include <machine/intr.h> 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/pccbbreg.h> 68 69 #include <dev/cardbus/cardslotvar.h> 70 71 #include <dev/cardbus/cardbusvar.h> 72 73 #include <dev/pcmcia/pcmciareg.h> 74 #include <dev/pcmcia/pcmciavar.h> 75 76 #include <dev/ic/i82365reg.h> 77 #include <dev/ic/i82365var.h> 78 #include <dev/pci/pccbbvar.h> 79 80 #include "locators.h" 81 82 #ifndef __NetBSD_Version__ 83 struct cfdriver cbb_cd = { 84 NULL, "cbb", DV_DULL 85 }; 86 #endif 87 88 #ifdef CBB_DEBUG 89 #define DPRINTF(x) printf x 90 #define STATIC 91 #else 92 #define DPRINTF(x) 93 #define STATIC static 94 #endif 95 96 /* 97 * DELAY_MS() is a wait millisecond. It shall use instead of delay() 98 * if you want to wait more than 1 ms. 99 */ 100 #define DELAY_MS(time, param) \ 101 do { \ 102 if (cold == 0) { \ 103 int tick = (hz*(time))/1000; \ 104 \ 105 if (tick <= 1) { \ 106 tick = 2; \ 107 } \ 108 tsleep((void *)(param), PWAIT, "pccbb", tick); \ 109 } else { \ 110 delay((time)*1000); \ 111 } \ 112 } while (0) 113 114 int pcicbbmatch __P((struct device *, struct cfdata *, void *)); 115 void pccbbattach __P((struct device *, struct device *, void *)); 116 int pccbbintr __P((void *)); 117 static void pci113x_insert __P((void *)); 118 static int pccbbintr_function __P((struct pccbb_softc *)); 119 120 static int pccbb_detect_card __P((struct pccbb_softc *)); 121 122 static void pccbb_pcmcia_write __P((struct pcic_handle *, int, u_int8_t)); 123 static u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 124 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 125 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 126 127 STATIC int cb_reset __P((struct pccbb_softc *)); 128 STATIC int cb_detect_voltage __P((struct pccbb_softc *)); 129 STATIC int cbbprint __P((void *, const char *)); 130 131 static int cb_chipset __P((u_int32_t, int *)); 132 STATIC void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 133 struct pcmciabus_attach_args *)); 134 #if 0 135 STATIC void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 136 STATIC void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 137 STATIC void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 138 #endif 139 140 STATIC int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 141 STATIC int pccbb_power __P((cardbus_chipset_tag_t, int)); 142 STATIC int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 143 #if !rbus 144 static int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, 145 u_int32_t)); 146 static int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 147 static int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, 148 u_int32_t)); 149 static int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 150 #endif /* !rbus */ 151 static void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, 152 int level, int (*ih) (void *), void *sc)); 153 static void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 154 155 static void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, 156 int level, int (*ih) (void *), void *sc)); 157 static void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 158 159 static cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 160 static void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 161 static cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, 162 int)); 163 static void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 164 cardbusreg_t)); 165 static void pccbb_chipinit __P((struct pccbb_softc *)); 166 167 STATIC int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 STATIC void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 STATIC int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 STATIC void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 STATIC int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 STATIC void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 STATIC int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 STATIC void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 STATIC void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, int (*)(void *), void *)); 183 STATIC void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 184 void *)); 185 STATIC void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 186 STATIC void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 187 STATIC int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 188 189 static void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 190 static int pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 191 static void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 192 static void pccbb_powerhook __P((int, void *)); 193 194 /* bus-space allocation and deallocation functions */ 195 #if rbus 196 197 static int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 198 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 199 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 200 static int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 201 bus_space_handle_t, bus_size_t)); 202 203 #endif /* rbus */ 204 205 #if rbus 206 207 static int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 208 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 209 static int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t)); 211 static int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 212 bus_size_t, bus_space_handle_t, int)); 213 static int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 214 bus_space_handle_t, bus_size_t)); 215 static void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 216 bus_space_tag_t)); 217 void pccbb_winlist_show(struct pccbb_win_chain *); 218 219 #endif /* rbus */ 220 221 /* for config_defer */ 222 static void pccbb_pci_callback __P((struct device *)); 223 224 #if defined SHOW_REGS 225 static void cb_show_regs __P((pci_chipset_tag_t pc, pcitag_t tag, 226 bus_space_tag_t memt, bus_space_handle_t memh)); 227 #endif 228 229 CFATTACH_DECL(cbb_pci, sizeof(struct pccbb_softc), 230 pcicbbmatch, pccbbattach, NULL, NULL); 231 232 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 233 pccbb_pcmcia_mem_alloc, 234 pccbb_pcmcia_mem_free, 235 pccbb_pcmcia_mem_map, 236 pccbb_pcmcia_mem_unmap, 237 pccbb_pcmcia_io_alloc, 238 pccbb_pcmcia_io_free, 239 pccbb_pcmcia_io_map, 240 pccbb_pcmcia_io_unmap, 241 pccbb_pcmcia_intr_establish, 242 pccbb_pcmcia_intr_disestablish, 243 pccbb_pcmcia_socket_enable, 244 pccbb_pcmcia_socket_disable, 245 pccbb_pcmcia_card_detect 246 }; 247 248 #if rbus 249 static struct cardbus_functions pccbb_funcs = { 250 pccbb_rbus_cb_space_alloc, 251 pccbb_rbus_cb_space_free, 252 pccbb_cb_intr_establish, 253 pccbb_cb_intr_disestablish, 254 pccbb_ctrl, 255 pccbb_power, 256 pccbb_make_tag, 257 pccbb_free_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #else 262 static struct cardbus_functions pccbb_funcs = { 263 pccbb_ctrl, 264 pccbb_power, 265 pccbb_mem_open, 266 pccbb_mem_close, 267 pccbb_io_open, 268 pccbb_io_close, 269 pccbb_cb_intr_establish, 270 pccbb_cb_intr_disestablish, 271 pccbb_make_tag, 272 pccbb_conf_read, 273 pccbb_conf_write, 274 }; 275 #endif 276 277 int 278 pcicbbmatch(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 284 285 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 286 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 287 PCI_INTERFACE(pa->pa_class) == 0) { 288 return 1; 289 } 290 291 return 0; 292 } 293 294 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 295 | ((prod) << PCI_PRODUCT_SHIFT)) 296 297 const struct yenta_chipinfo { 298 pcireg_t yc_id; /* vendor tag | product tag */ 299 int yc_chiptype; 300 int yc_flags; 301 } yc_chipsets[] = { 302 /* Texas Instruments chips */ 303 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 304 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 306 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 308 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 310 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 312 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 314 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 316 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 318 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 320 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 322 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 324 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 326 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 328 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 330 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 332 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 334 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 335 336 /* Ricoh chips */ 337 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 338 PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 340 PCCBB_PCMCIA_MEM_32}, 341 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 342 PCCBB_PCMCIA_MEM_32}, 343 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 344 PCCBB_PCMCIA_MEM_32}, 345 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 346 PCCBB_PCMCIA_MEM_32}, 347 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 348 PCCBB_PCMCIA_MEM_32}, 349 350 /* Toshiba products */ 351 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 352 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 353 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 354 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 355 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 356 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 357 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 358 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 359 360 /* Cirrus Logic products */ 361 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 362 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 363 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 364 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 365 366 /* sentinel, or Generic chip */ 367 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 368 }; 369 370 static int 371 cb_chipset(pci_id, flagp) 372 u_int32_t pci_id; 373 int *flagp; 374 { 375 const struct yenta_chipinfo *yc; 376 377 /* Loop over except the last default entry. */ 378 for (yc = yc_chipsets; yc < yc_chipsets + 379 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 380 if (pci_id == yc->yc_id) 381 break; 382 383 if (flagp != NULL) 384 *flagp = yc->yc_flags; 385 386 return (yc->yc_chiptype); 387 } 388 389 static void 390 pccbb_shutdown(void *arg) 391 { 392 struct pccbb_softc *sc = arg; 393 pcireg_t command; 394 395 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 396 397 /* 398 * turn off power 399 * 400 * XXX - do not turn off power if chipset is TI 113X because 401 * only TI 1130 with PowerMac 2400 hangs in pccbb_power(). 402 */ 403 if (sc->sc_chipset != CB_TI113X) { 404 pccbb_power((cardbus_chipset_tag_t)sc, 405 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 406 } 407 408 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 409 0); 410 411 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 412 413 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 414 PCI_COMMAND_MASTER_ENABLE); 415 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 416 417 } 418 419 void 420 pccbbattach(parent, self, aux) 421 struct device *parent; 422 struct device *self; 423 void *aux; 424 { 425 struct pccbb_softc *sc = (void *)self; 426 struct pci_attach_args *pa = aux; 427 pci_chipset_tag_t pc = pa->pa_pc; 428 pcireg_t busreg, reg, sock_base; 429 bus_addr_t sockbase; 430 char devinfo[256]; 431 int flags; 432 int pwrmgt_offs; 433 434 #ifdef __HAVE_PCCBB_ATTACH_HOOK 435 pccbb_attach_hook(parent, self, pa); 436 #endif 437 438 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 439 440 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 441 printf(": %s (rev. 0x%02x)", devinfo, PCI_REVISION(pa->pa_class)); 442 #ifdef CBB_DEBUG 443 printf(" (chipflags %x)", flags); 444 #endif 445 printf("\n"); 446 447 TAILQ_INIT(&sc->sc_memwindow); 448 TAILQ_INIT(&sc->sc_iowindow); 449 450 #if rbus 451 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 452 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 453 454 #if 0 455 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 456 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 457 #endif 458 #endif /* rbus */ 459 460 sc->sc_flags &= ~CBB_MEMHMAPPED; 461 462 /* power management: set D0 state */ 463 sc->sc_pwrmgt_offs = 0; 464 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 465 &pwrmgt_offs, 0)) { 466 reg = pci_conf_read(pc, pa->pa_tag, pwrmgt_offs + PCI_PMCSR); 467 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 468 reg & 0x100 /* PCI_PMCSR_PME_EN */) { 469 reg &= ~PCI_PMCSR_STATE_MASK; 470 reg |= PCI_PMCSR_STATE_D0; 471 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 472 pci_conf_write(pc, pa->pa_tag, 473 pwrmgt_offs + PCI_PMCSR, reg); 474 } 475 476 sc->sc_pwrmgt_offs = pwrmgt_offs; 477 } 478 479 /* 480 * MAP socket registers and ExCA registers on memory-space 481 * When no valid address is set on socket base registers (on pci 482 * config space), get it not polite way. 483 */ 484 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 485 486 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 487 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 488 /* The address must be valid. */ 489 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 490 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL)) { 491 printf("%s: can't map socket base address 0x%lx\n", 492 sc->sc_dev.dv_xname, (unsigned long)sock_base); 493 /* 494 * I think it's funny: socket base registers must be 495 * mapped on memory space, but ... 496 */ 497 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 498 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 499 NULL)) { 500 printf("%s: can't map socket base address" 501 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 502 (unsigned long)sockbase); 503 /* give up... allocate reg space via rbus. */ 504 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 505 } else 506 sc->sc_flags |= CBB_MEMHMAPPED; 507 } else { 508 DPRINTF(("%s: socket base address 0x%lx\n", 509 sc->sc_dev.dv_xname, (unsigned long)sockbase)); 510 sc->sc_flags |= CBB_MEMHMAPPED; 511 } 512 } 513 514 sc->sc_mem_start = 0; /* XXX */ 515 sc->sc_mem_end = 0xffffffff; /* XXX */ 516 517 /* 518 * When interrupt isn't routed correctly, give up probing cbb and do 519 * not kill pcic-compatible port. 520 */ 521 if ((0 == pa->pa_intrline) || (255 == pa->pa_intrline)) { 522 printf("%s: NOT USED because of unconfigured interrupt\n", 523 sc->sc_dev.dv_xname); 524 return; 525 } 526 527 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 528 529 /* pccbb_machdep.c end */ 530 531 #if defined CBB_DEBUG 532 { 533 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 534 printf("%s: intrpin %s, intrtag %d\n", sc->sc_dev.dv_xname, 535 intrname[pa->pa_intrpin], pa->pa_intrline); 536 } 537 #endif 538 539 /* setup softc */ 540 sc->sc_pc = pc; 541 sc->sc_iot = pa->pa_iot; 542 sc->sc_memt = pa->pa_memt; 543 sc->sc_dmat = pa->pa_dmat; 544 sc->sc_tag = pa->pa_tag; 545 sc->sc_function = pa->pa_function; 546 sc->sc_sockbase = sock_base; 547 sc->sc_busnum = busreg; 548 549 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 550 551 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 552 553 shutdownhook_establish(pccbb_shutdown, sc); 554 555 /* Disable legacy register mapping. */ 556 switch (sc->sc_chipset) { 557 case CB_RX5C46X: /* fallthrough */ 558 #if 0 559 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 560 case CB_RX5C47X: 561 #endif 562 /* 563 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 564 * cannot be disabled by substituting 0 into PCI_LEGACY 565 * register. Ricoh CardBus bridges have special bits on Bridge 566 * control reg (addr 0x3e on PCI config space). 567 */ 568 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 569 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 570 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 571 break; 572 573 default: 574 /* XXX I don't know proper way to kill legacy I/O. */ 575 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 576 break; 577 } 578 579 config_defer(self, pccbb_pci_callback); 580 } 581 582 583 584 585 /* 586 * static void pccbb_pci_callback(struct device *self) 587 * 588 * The actual attach routine: get memory space for YENTA register 589 * space, setup YENTA register and route interrupt. 590 * 591 * This function should be deferred because this device may obtain 592 * memory space dynamically. This function must avoid obtaining 593 * memory area which has already kept for another device. 594 */ 595 static void 596 pccbb_pci_callback(self) 597 struct device *self; 598 { 599 struct pccbb_softc *sc = (void *)self; 600 pci_chipset_tag_t pc = sc->sc_pc; 601 pci_intr_handle_t ih; 602 const char *intrstr = NULL; 603 bus_addr_t sockbase; 604 struct cbslot_attach_args cba; 605 struct pcmciabus_attach_args paa; 606 struct cardslot_attach_args caa; 607 struct cardslot_softc *csc; 608 609 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 610 /* The socket registers aren't mapped correctly. */ 611 #if rbus 612 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 613 (sc->sc_chipset == CB_RX5C47X 614 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 615 0, &sockbase, &sc->sc_base_memh)) { 616 return; 617 } 618 sc->sc_base_memt = sc->sc_memt; 619 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 620 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 621 sc->sc_dev.dv_xname, (unsigned long)sockbase, 622 (unsigned long)pci_conf_read(pc, sc->sc_tag, 623 PCI_SOCKBASE))); 624 #else 625 sc->sc_base_memt = sc->sc_memt; 626 #if !defined CBB_PCI_BASE 627 #define CBB_PCI_BASE 0x20000000 628 #endif 629 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 630 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 631 /* cannot allocate memory space */ 632 return; 633 } 634 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 635 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%lx\n", 636 sc->sc_dev.dv_xname, (unsigned long)sock_base, 637 (unsigned long)pci_conf_read(pc, 638 sc->sc_tag, PCI_SOCKBASE))); 639 sc->sc_sockbase = sockbase; 640 #endif 641 sc->sc_flags |= CBB_MEMHMAPPED; 642 } 643 644 /* bus bridge initialization */ 645 pccbb_chipinit(sc); 646 647 /* clear data structure for child device interrupt handlers */ 648 LIST_INIT(&sc->sc_pil); 649 sc->sc_pil_intr_enable = 1; 650 651 /* Map and establish the interrupt. */ 652 if (pci_intr_map(&sc->sc_pa, &ih)) { 653 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 654 return; 655 } 656 intrstr = pci_intr_string(pc, ih); 657 658 /* 659 * XXX pccbbintr should be called under the priority lower 660 * than any other hard interrputs. 661 */ 662 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 663 664 if (sc->sc_ih == NULL) { 665 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 666 if (intrstr != NULL) { 667 printf(" at %s", intrstr); 668 } 669 printf("\n"); 670 return; 671 } 672 673 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 674 powerhook_establish(pccbb_powerhook, sc); 675 676 { 677 u_int32_t sockstat; 678 679 sockstat = bus_space_read_4(sc->sc_base_memt, 680 sc->sc_base_memh, CB_SOCKET_STAT); 681 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 682 sc->sc_flags |= CBB_CARDEXIST; 683 } 684 } 685 686 /* 687 * attach cardbus 688 */ 689 { 690 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 691 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 692 693 /* initialize cbslot_attach */ 694 cba.cba_busname = "cardbus"; 695 cba.cba_iot = sc->sc_iot; 696 cba.cba_memt = sc->sc_memt; 697 cba.cba_dmat = sc->sc_dmat; 698 cba.cba_bus = (busreg >> 8) & 0x0ff; 699 cba.cba_cc = (void *)sc; 700 cba.cba_cf = &pccbb_funcs; 701 cba.cba_intrline = sc->sc_pa.pa_intrline; 702 703 #if rbus 704 cba.cba_rbus_iot = sc->sc_rbus_iot; 705 cba.cba_rbus_memt = sc->sc_rbus_memt; 706 #endif 707 708 cba.cba_cacheline = PCI_CACHELINE(bhlc); 709 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 710 711 if (bootverbose) { 712 printf("%s: cacheline 0x%x lattimer 0x%x\n", 713 sc->sc_dev.dv_xname, cba.cba_cacheline, 714 cba.cba_lattimer); 715 printf("%s: bhlc 0x%x lscp 0x%x\n", 716 sc->sc_dev.dv_xname, bhlc, busreg); 717 } 718 #if defined SHOW_REGS 719 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 720 sc->sc_base_memh); 721 #endif 722 } 723 724 pccbb_pcmcia_attach_setup(sc, &paa); 725 caa.caa_cb_attach = NULL; 726 if (cba.cba_bus == 0) 727 printf("%s: secondary bus number uninitialized; try PCIBIOS_BUS_FIXUP\n", sc->sc_dev.dv_xname); 728 else 729 caa.caa_cb_attach = &cba; 730 caa.caa_16_attach = &paa; 731 caa.caa_ph = &sc->sc_pcmcia_h; 732 733 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 734 DPRINTF(("pccbbattach: found cardslot\n")); 735 sc->sc_csc = csc; 736 } 737 738 return; 739 } 740 741 742 743 744 745 /* 746 * static void pccbb_chipinit(struct pccbb_softc *sc) 747 * 748 * This function initialize YENTA chip registers listed below: 749 * 1) PCI command reg, 750 * 2) PCI and CardBus latency timer, 751 * 3) route PCI interrupt, 752 * 4) close all memory and io windows. 753 * 5) turn off bus power. 754 * 6) card detect interrupt on. 755 * 7) clear interrupt 756 */ 757 static void 758 pccbb_chipinit(sc) 759 struct pccbb_softc *sc; 760 { 761 pci_chipset_tag_t pc = sc->sc_pc; 762 pcitag_t tag = sc->sc_tag; 763 bus_space_tag_t bmt = sc->sc_base_memt; 764 bus_space_handle_t bmh = sc->sc_base_memh; 765 pcireg_t reg; 766 767 /* 768 * Set PCI command reg. 769 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 770 */ 771 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 772 /* I believe it is harmless. */ 773 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 774 PCI_COMMAND_MASTER_ENABLE); 775 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 776 777 /* 778 * Set CardBus latency timer. 779 */ 780 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 781 if (PCI_CB_LATENCY(reg) < 0x20) { 782 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 783 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 784 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 785 } 786 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 787 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 788 789 /* 790 * Set PCI latency timer. 791 */ 792 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 793 if (PCI_LATTIMER(reg) < 0x10) { 794 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 795 reg |= (0x10 << PCI_LATTIMER_SHIFT); 796 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 797 } 798 DPRINTF(("PCI latency timer 0x%x (%x)\n", 799 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 800 801 802 /* Route functional interrupts to PCI. */ 803 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 804 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 805 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 806 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 807 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 808 809 switch (sc->sc_chipset) { 810 case CB_TI113X: 811 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 812 /* This bit is shared, but may read as 0 on some chips, so set 813 it explicitly on both functions. */ 814 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 815 /* CSC intr enable */ 816 reg |= PCI113X_CBCTRL_PCI_CSC; 817 /* functional intr prohibit | prohibit ISA routing */ 818 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 819 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 820 break; 821 822 case CB_TI12XX: 823 /* 824 * Some TI 12xx (and [14][45]xx) based pci cards 825 * sometimes have issues with the MFUNC register not 826 * being initialized due to a bad EEPROM on board. 827 * Laptops that this matters on have this register 828 * properly initialized. 829 * 830 * The TI125X parts have a different register. 831 */ 832 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 833 if (reg == 0) { 834 reg &= ~PCI12XX_MFUNC_PIN0; 835 reg |= PCI12XX_MFUNC_PIN0_INTA; 836 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 837 PCI12XX_SYSCTRL_INTRTIE) == 0) { 838 reg &= ~PCI12XX_MFUNC_PIN1; 839 reg |= PCI12XX_MFUNC_PIN1_INTB; 840 } 841 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 842 } 843 /* fallthrough */ 844 845 case CB_TI125X: 846 /* 847 * Disable zoom video. Some machines initialize this 848 * improperly and experience has shown that this helps 849 * prevent strange behavior. 850 */ 851 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 852 853 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 854 reg |= PCI12XX_SYSCTRL_VCCPROT; 855 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 856 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 857 reg |= PCI12XX_CBCTRL_CSC; 858 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 859 break; 860 861 case CB_TOPIC95B: 862 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 863 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 864 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 865 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 866 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 867 sc->sc_dev.dv_xname, reg)); 868 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 869 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 870 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 871 DPRINTF(("0x%x\n", reg)); 872 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 873 break; 874 875 case CB_TOPIC97: 876 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 877 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 878 sc->sc_dev.dv_xname, reg)); 879 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 880 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 881 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 882 reg |= TOPIC97_SLOT_CTRL_PCIINT; 883 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 884 DPRINTF(("0x%x\n", reg)); 885 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 886 /* make sure to assert LV card support bits */ 887 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 888 0x800 + 0x3e, 889 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 890 0x800 + 0x3e) | 0x03); 891 break; 892 } 893 894 /* Close all memory and I/O windows. */ 895 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 896 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 897 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 898 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 899 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 901 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 902 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 903 904 /* reset 16-bit pcmcia bus */ 905 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 906 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 907 908 /* turn off power */ 909 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 910 911 /* CSC Interrupt: Card detect interrupt on */ 912 reg = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 913 reg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 914 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, reg); 915 /* reset interrupt */ 916 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 917 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 918 } 919 920 921 922 923 /* 924 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 925 * struct pcmciabus_attach_args *paa) 926 * 927 * This function attaches 16-bit PCcard bus. 928 */ 929 STATIC void 930 pccbb_pcmcia_attach_setup(sc, paa) 931 struct pccbb_softc *sc; 932 struct pcmciabus_attach_args *paa; 933 { 934 struct pcic_handle *ph = &sc->sc_pcmcia_h; 935 #if rbus 936 rbus_tag_t rb; 937 #endif 938 939 /* initialize pcmcia part in pccbb_softc */ 940 ph->ph_parent = (struct device *)sc; 941 ph->sock = sc->sc_function; 942 ph->flags = 0; 943 ph->shutdown = 0; 944 ph->ih_irq = sc->sc_pa.pa_intrline; 945 ph->ph_bus_t = sc->sc_base_memt; 946 ph->ph_bus_h = sc->sc_base_memh; 947 ph->ph_read = pccbb_pcmcia_read; 948 ph->ph_write = pccbb_pcmcia_write; 949 sc->sc_pct = &pccbb_pcmcia_funcs; 950 951 /* 952 * We need to do a few things here: 953 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 954 * setting the IRQ numbers to 0. 955 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 956 * routing of CSC interrupts (e.g. card removal) to PCI while in 957 * PCMCIA mode. We just leave this set all the time. 958 * 3) Enable card insertion/removal interrupts in case the chip also 959 * needs that while in PCMCIA mode. 960 * 4) Clear any pending CSC interrupt. 961 */ 962 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE); 963 if (sc->sc_chipset == CB_TI113X) { 964 Pcic_write(ph, PCIC_CSC_INTR, 0); 965 } else { 966 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 967 Pcic_read(ph, PCIC_CSC); 968 } 969 970 /* initialize pcmcia bus attachment */ 971 paa->paa_busname = "pcmcia"; 972 paa->pct = sc->sc_pct; 973 paa->pch = ph; 974 paa->iobase = 0; /* I don't use them */ 975 paa->iosize = 0; 976 #if rbus 977 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 978 paa->iobase = rb->rb_start + rb->rb_offset; 979 paa->iosize = rb->rb_end - rb->rb_start; 980 #endif 981 982 return; 983 } 984 985 #if 0 986 STATIC void 987 pccbb_pcmcia_attach_card(ph) 988 struct pcic_handle *ph; 989 { 990 if (ph->flags & PCIC_FLAG_CARDP) { 991 panic("pccbb_pcmcia_attach_card: already attached"); 992 } 993 994 /* call the MI attach function */ 995 pcmcia_card_attach(ph->pcmcia); 996 997 ph->flags |= PCIC_FLAG_CARDP; 998 } 999 1000 STATIC void 1001 pccbb_pcmcia_detach_card(ph, flags) 1002 struct pcic_handle *ph; 1003 int flags; 1004 { 1005 if (!(ph->flags & PCIC_FLAG_CARDP)) { 1006 panic("pccbb_pcmcia_detach_card: already detached"); 1007 } 1008 1009 ph->flags &= ~PCIC_FLAG_CARDP; 1010 1011 /* call the MI detach function */ 1012 pcmcia_card_detach(ph->pcmcia, flags); 1013 } 1014 #endif 1015 1016 /* 1017 * int pccbbintr(arg) 1018 * void *arg; 1019 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1020 * itself. 1021 */ 1022 int 1023 pccbbintr(arg) 1024 void *arg; 1025 { 1026 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1027 u_int32_t sockevent, sockstate; 1028 bus_space_tag_t memt = sc->sc_base_memt; 1029 bus_space_handle_t memh = sc->sc_base_memh; 1030 struct pcic_handle *ph = &sc->sc_pcmcia_h; 1031 1032 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1033 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1034 Pcic_read(ph, PCIC_CSC); 1035 1036 if (sockevent == 0) { 1037 /* This intr is not for me: it may be for my child devices. */ 1038 if (sc->sc_pil_intr_enable) { 1039 return pccbbintr_function(sc); 1040 } else { 1041 return 0; 1042 } 1043 } 1044 1045 if (sockevent & CB_SOCKET_EVENT_CD) { 1046 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1047 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1048 /* A card should be removed. */ 1049 if (sc->sc_flags & CBB_CARDEXIST) { 1050 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 1051 sockevent)); 1052 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1053 sc->sc_flags &= ~CBB_CARDEXIST; 1054 if (sc->sc_csc->sc_status & 1055 CARDSLOT_STATUS_CARD_16) { 1056 #if 0 1057 struct pcic_handle *ph = 1058 &sc->sc_pcmcia_h; 1059 1060 pcmcia_card_deactivate(ph->pcmcia); 1061 pccbb_pcmcia_socket_disable(ph); 1062 pccbb_pcmcia_detach_card(ph, 1063 DETACH_FORCE); 1064 #endif 1065 cardslot_event_throw(sc->sc_csc, 1066 CARDSLOT_EVENT_REMOVAL_16); 1067 } else if (sc->sc_csc->sc_status & 1068 CARDSLOT_STATUS_CARD_CB) { 1069 /* Cardbus intr removed */ 1070 cardslot_event_throw(sc->sc_csc, 1071 CARDSLOT_EVENT_REMOVAL_CB); 1072 } 1073 } else if (sc->sc_flags & CBB_INSERTING) { 1074 sc->sc_flags &= ~CBB_INSERTING; 1075 callout_stop(&sc->sc_insert_ch); 1076 } 1077 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1078 /* 1079 * The pccbbintr may called from powerdown hook when 1080 * the system resumed, to detect the card 1081 * insertion/removal during suspension. 1082 */ 1083 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1084 if (sc->sc_flags & CBB_INSERTING) { 1085 callout_stop(&sc->sc_insert_ch); 1086 } 1087 callout_reset(&sc->sc_insert_ch, hz / 5, 1088 pci113x_insert, sc); 1089 sc->sc_flags |= CBB_INSERTING; 1090 } 1091 } 1092 1093 return (1); 1094 } 1095 1096 /* 1097 * static int pccbbintr_function(struct pccbb_softc *sc) 1098 * 1099 * This function calls each interrupt handler registered at the 1100 * bridge. The interrupt handlers are called in registered order. 1101 */ 1102 static int 1103 pccbbintr_function(sc) 1104 struct pccbb_softc *sc; 1105 { 1106 int retval = 0, val; 1107 struct pccbb_intrhand_list *pil; 1108 int s, splchanged; 1109 1110 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1111 pil = LIST_NEXT(pil, pil_next)) { 1112 /* 1113 * XXX priority change. gross. I use if-else 1114 * sentense instead of switch-case sentense because of 1115 * avoiding duplicate case value error. More than one 1116 * IPL_XXX use same value. It depends on 1117 * implimentation. 1118 */ 1119 splchanged = 1; 1120 if (pil->pil_level == IPL_SERIAL) { 1121 s = splserial(); 1122 } else if (pil->pil_level == IPL_HIGH) { 1123 s = splhigh(); 1124 } else if (pil->pil_level == IPL_CLOCK) { 1125 s = splclock(); 1126 } else if (pil->pil_level == IPL_AUDIO) { 1127 s = splaudio(); 1128 } else if (pil->pil_level == IPL_VM) { 1129 s = splvm(); 1130 } else if (pil->pil_level == IPL_TTY) { 1131 s = spltty(); 1132 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1133 s = splsoftserial(); 1134 } else if (pil->pil_level == IPL_NET) { 1135 s = splnet(); 1136 } else { 1137 s = 0; /* XXX: gcc */ 1138 splchanged = 0; 1139 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1140 } 1141 1142 val = (*pil->pil_func)(pil->pil_arg); 1143 1144 if (splchanged != 0) { 1145 splx(s); 1146 } 1147 1148 retval = retval == 1 ? 1 : 1149 retval == 0 ? val : val != 0 ? val : retval; 1150 } 1151 1152 return retval; 1153 } 1154 1155 static void 1156 pci113x_insert(arg) 1157 void *arg; 1158 { 1159 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1160 u_int32_t sockevent, sockstate; 1161 1162 if (!(sc->sc_flags & CBB_INSERTING)) { 1163 /* We add a card only under inserting state. */ 1164 return; 1165 } 1166 sc->sc_flags &= ~CBB_INSERTING; 1167 1168 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1169 CB_SOCKET_EVENT); 1170 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1171 CB_SOCKET_STAT); 1172 1173 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1174 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1175 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1176 sc->sc_flags |= CBB_CARDEXIST; 1177 /* call pccard interrupt handler here */ 1178 if (sockstate & CB_SOCKET_STAT_16BIT) { 1179 /* 16-bit card found */ 1180 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1181 cardslot_event_throw(sc->sc_csc, 1182 CARDSLOT_EVENT_INSERTION_16); 1183 } else if (sockstate & CB_SOCKET_STAT_CB) { 1184 /* cardbus card found */ 1185 /* cardbus_attach_card(sc->sc_csc); */ 1186 cardslot_event_throw(sc->sc_csc, 1187 CARDSLOT_EVENT_INSERTION_CB); 1188 } else { 1189 /* who are you? */ 1190 } 1191 } else { 1192 callout_reset(&sc->sc_insert_ch, hz / 10, 1193 pci113x_insert, sc); 1194 } 1195 } 1196 1197 #define PCCBB_PCMCIA_OFFSET 0x800 1198 static u_int8_t 1199 pccbb_pcmcia_read(ph, reg) 1200 struct pcic_handle *ph; 1201 int reg; 1202 { 1203 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1204 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1205 1206 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1207 PCCBB_PCMCIA_OFFSET + reg); 1208 } 1209 1210 static void 1211 pccbb_pcmcia_write(ph, reg, val) 1212 struct pcic_handle *ph; 1213 int reg; 1214 u_int8_t val; 1215 { 1216 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1217 val); 1218 1219 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1220 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1221 } 1222 1223 /* 1224 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1225 */ 1226 STATIC int 1227 pccbb_ctrl(ct, command) 1228 cardbus_chipset_tag_t ct; 1229 int command; 1230 { 1231 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1232 1233 switch (command) { 1234 case CARDBUS_CD: 1235 if (2 == pccbb_detect_card(sc)) { 1236 int retval = 0; 1237 int status = cb_detect_voltage(sc); 1238 if (PCCARD_VCC_5V & status) { 1239 retval |= CARDBUS_5V_CARD; 1240 } 1241 if (PCCARD_VCC_3V & status) { 1242 retval |= CARDBUS_3V_CARD; 1243 } 1244 if (PCCARD_VCC_XV & status) { 1245 retval |= CARDBUS_XV_CARD; 1246 } 1247 if (PCCARD_VCC_YV & status) { 1248 retval |= CARDBUS_YV_CARD; 1249 } 1250 return retval; 1251 } else { 1252 return 0; 1253 } 1254 case CARDBUS_RESET: 1255 return cb_reset(sc); 1256 case CARDBUS_IO_ENABLE: /* fallthrough */ 1257 case CARDBUS_IO_DISABLE: /* fallthrough */ 1258 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1259 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1260 case CARDBUS_BM_ENABLE: /* fallthrough */ 1261 case CARDBUS_BM_DISABLE: /* fallthrough */ 1262 /* XXX: I think we don't need to call this function below. */ 1263 return pccbb_cardenable(sc, command); 1264 } 1265 1266 return 0; 1267 } 1268 1269 /* 1270 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1271 * This function returns true when it succeeds and returns false when 1272 * it fails. 1273 */ 1274 STATIC int 1275 pccbb_power(ct, command) 1276 cardbus_chipset_tag_t ct; 1277 int command; 1278 { 1279 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1280 1281 u_int32_t status, sock_ctrl, reg_ctrl; 1282 bus_space_tag_t memt = sc->sc_base_memt; 1283 bus_space_handle_t memh = sc->sc_base_memh; 1284 1285 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1286 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1287 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1288 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1289 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1290 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1291 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1292 "UNKNOWN", 1293 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1294 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1295 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1296 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1297 "UNKNOWN", command)); 1298 1299 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1300 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1301 1302 switch (command & CARDBUS_VCCMASK) { 1303 case CARDBUS_VCC_UC: 1304 break; 1305 case CARDBUS_VCC_5V: 1306 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1307 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1308 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1309 } else { 1310 printf("%s: BAD voltage request: no 5 V card\n", 1311 sc->sc_dev.dv_xname); 1312 return 0; 1313 } 1314 break; 1315 case CARDBUS_VCC_3V: 1316 if (CB_SOCKET_STAT_3VCARD & status) { 1317 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1318 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1319 } else { 1320 printf("%s: BAD voltage request: no 3.3 V card\n", 1321 sc->sc_dev.dv_xname); 1322 return 0; 1323 } 1324 break; 1325 case CARDBUS_VCC_0V: 1326 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1327 break; 1328 default: 1329 return 0; /* power NEVER changed */ 1330 } 1331 1332 switch (command & CARDBUS_VPPMASK) { 1333 case CARDBUS_VPP_UC: 1334 break; 1335 case CARDBUS_VPP_0V: 1336 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1337 break; 1338 case CARDBUS_VPP_VCC: 1339 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1340 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1341 break; 1342 case CARDBUS_VPP_12V: 1343 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1344 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1345 break; 1346 } 1347 1348 #if 0 1349 DPRINTF(("sock_ctrl: 0x%x\n", sock_ctrl)); 1350 #endif 1351 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1352 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1353 1354 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1355 printf 1356 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1357 sc->sc_dev.dv_xname, sock_ctrl, status); 1358 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1359 (command & CARDBUS_VCCMASK) == 1360 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1361 CARDBUS_VCCMASK) == 1362 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1363 CARDBUS_VCCMASK) == 1364 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1365 CARDBUS_VCCMASK) == 1366 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1367 CARDBUS_VCCMASK) == 1368 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1369 CARDBUS_VCCMASK) == 1370 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1371 (command & CARDBUS_VPPMASK) == 1372 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1373 CARDBUS_VPPMASK) == 1374 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1375 CARDBUS_VPPMASK) == 1376 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1377 CARDBUS_VPPMASK) == 1378 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1379 #if 0 1380 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1381 u_int32_t force = 1382 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1383 /* Reset Bad Vcc request */ 1384 force &= ~CB_SOCKET_FORCE_BADVCC; 1385 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1386 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1387 CB_SOCKET_STAT)); 1388 return 1; 1389 } 1390 #endif 1391 return 0; 1392 } 1393 1394 if (sc->sc_chipset == CB_TOPIC97) { 1395 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1396 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1397 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1398 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1399 else 1400 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1401 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1402 } 1403 1404 /* 1405 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1406 * time is 20 ms, some PC-Card bridge requires longer duration. 1407 */ 1408 #if 0 /* XXX called on interrupt context */ 1409 DELAY_MS(300, sc); 1410 #else 1411 delay(300 * 1000); 1412 #endif 1413 1414 return 1; /* power changed correctly */ 1415 } 1416 1417 #if defined CB_PCMCIA_POLL 1418 struct cb_poll_str { 1419 void *arg; 1420 int (*func) __P((void *)); 1421 int level; 1422 pccard_chipset_tag_t ct; 1423 int count; 1424 struct callout poll_ch; 1425 }; 1426 1427 static struct cb_poll_str cb_poll[10]; 1428 static int cb_poll_n = 0; 1429 1430 static void cb_pcmcia_poll __P((void *arg)); 1431 1432 static void 1433 cb_pcmcia_poll(arg) 1434 void *arg; 1435 { 1436 struct cb_poll_str *poll = arg; 1437 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1438 struct pccbb_softc *sc = psc->cpc_parent; 1439 int s; 1440 u_int32_t spsr; /* socket present-state reg */ 1441 1442 callout_reset(&poll->poll_ch, hz / 10, cb_pcmcia_poll, poll); 1443 switch (poll->level) { 1444 case IPL_NET: 1445 s = splnet(); 1446 break; 1447 case IPL_BIO: 1448 s = splbio(); 1449 break; 1450 case IPL_TTY: /* fallthrough */ 1451 default: 1452 s = spltty(); 1453 break; 1454 } 1455 1456 spsr = 1457 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1458 CB_SOCKET_STAT); 1459 1460 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1461 if (!(spsr & 0x40)) { /* CINT low */ 1462 #else 1463 if (1) { 1464 #endif 1465 if ((*poll->func) (poll->arg) == 1) { 1466 ++poll->count; 1467 printf("intr: reported from poller, 0x%x\n", spsr); 1468 #if defined LEVEL2 1469 } else { 1470 printf("intr: miss! 0x%x\n", spsr); 1471 #endif 1472 } 1473 } 1474 splx(s); 1475 } 1476 #endif /* defined CB_PCMCIA_POLL */ 1477 1478 /* 1479 * static int pccbb_detect_card(struct pccbb_softc *sc) 1480 * return value: 0 if no card exists. 1481 * 1 if 16-bit card exists. 1482 * 2 if cardbus card exists. 1483 */ 1484 static int 1485 pccbb_detect_card(sc) 1486 struct pccbb_softc *sc; 1487 { 1488 bus_space_handle_t base_memh = sc->sc_base_memh; 1489 bus_space_tag_t base_memt = sc->sc_base_memt; 1490 u_int32_t sockstat = 1491 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1492 int retval = 0; 1493 1494 /* CD1 and CD2 asserted */ 1495 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1496 /* card must be present */ 1497 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1498 /* NOTACARD DEASSERTED */ 1499 if (CB_SOCKET_STAT_CB & sockstat) { 1500 /* CardBus mode */ 1501 retval = 2; 1502 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1503 /* 16-bit mode */ 1504 retval = 1; 1505 } 1506 } 1507 } 1508 return retval; 1509 } 1510 1511 /* 1512 * STATIC int cb_reset(struct pccbb_softc *sc) 1513 * This function resets CardBus card. 1514 */ 1515 STATIC int 1516 cb_reset(sc) 1517 struct pccbb_softc *sc; 1518 { 1519 /* 1520 * Reset Assert at least 20 ms 1521 * Some machines request longer duration. 1522 */ 1523 int reset_duration = 1524 (sc->sc_chipset == CB_RX5C47X ? 400 : 40); 1525 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1526 1527 /* Reset bit Assert (bit 6 at 0x3E) */ 1528 bcr |= CB_BCR_RESET_ENABLE; 1529 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1530 DELAY_MS(reset_duration, sc); 1531 1532 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1533 /* Reset bit Deassert (bit 6 at 0x3E) */ 1534 bcr &= ~CB_BCR_RESET_ENABLE; 1535 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1536 DELAY_MS(reset_duration, sc); 1537 } 1538 /* No card found on the slot. Keep Reset. */ 1539 return 1; 1540 } 1541 1542 /* 1543 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1544 * This function detect card Voltage. 1545 */ 1546 STATIC int 1547 cb_detect_voltage(sc) 1548 struct pccbb_softc *sc; 1549 { 1550 u_int32_t psr; /* socket present-state reg */ 1551 bus_space_tag_t iot = sc->sc_base_memt; 1552 bus_space_handle_t ioh = sc->sc_base_memh; 1553 int vol = PCCARD_VCC_UKN; /* set 0 */ 1554 1555 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1556 1557 if (0x400u & psr) { 1558 vol |= PCCARD_VCC_5V; 1559 } 1560 if (0x800u & psr) { 1561 vol |= PCCARD_VCC_3V; 1562 } 1563 1564 return vol; 1565 } 1566 1567 STATIC int 1568 cbbprint(aux, pcic) 1569 void *aux; 1570 const char *pcic; 1571 { 1572 /* 1573 struct cbslot_attach_args *cba = aux; 1574 1575 if (cba->cba_slot >= 0) { 1576 aprint_normal(" slot %d", cba->cba_slot); 1577 } 1578 */ 1579 return UNCONF; 1580 } 1581 1582 /* 1583 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1584 * This function enables and disables the card 1585 */ 1586 STATIC int 1587 pccbb_cardenable(sc, function) 1588 struct pccbb_softc *sc; 1589 int function; 1590 { 1591 u_int32_t command = 1592 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1593 1594 DPRINTF(("pccbb_cardenable:")); 1595 switch (function) { 1596 case CARDBUS_IO_ENABLE: 1597 command |= PCI_COMMAND_IO_ENABLE; 1598 break; 1599 case CARDBUS_IO_DISABLE: 1600 command &= ~PCI_COMMAND_IO_ENABLE; 1601 break; 1602 case CARDBUS_MEM_ENABLE: 1603 command |= PCI_COMMAND_MEM_ENABLE; 1604 break; 1605 case CARDBUS_MEM_DISABLE: 1606 command &= ~PCI_COMMAND_MEM_ENABLE; 1607 break; 1608 case CARDBUS_BM_ENABLE: 1609 command |= PCI_COMMAND_MASTER_ENABLE; 1610 break; 1611 case CARDBUS_BM_DISABLE: 1612 command &= ~PCI_COMMAND_MASTER_ENABLE; 1613 break; 1614 default: 1615 return 0; 1616 } 1617 1618 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1619 DPRINTF((" command reg 0x%x\n", command)); 1620 return 1; 1621 } 1622 1623 #if !rbus 1624 /* 1625 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1626 */ 1627 static int 1628 pccbb_io_open(ct, win, start, end) 1629 cardbus_chipset_tag_t ct; 1630 int win; 1631 u_int32_t start, end; 1632 { 1633 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1634 int basereg; 1635 int limitreg; 1636 1637 if ((win < 0) || (win > 2)) { 1638 #if defined DIAGNOSTIC 1639 printf("cardbus_io_open: window out of range %d\n", win); 1640 #endif 1641 return 0; 1642 } 1643 1644 basereg = win * 8 + 0x2c; 1645 limitreg = win * 8 + 0x30; 1646 1647 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1648 start, basereg, end, limitreg)); 1649 1650 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1651 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1652 return 1; 1653 } 1654 1655 /* 1656 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1657 */ 1658 static int 1659 pccbb_io_close(ct, win) 1660 cardbus_chipset_tag_t ct; 1661 int win; 1662 { 1663 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1664 int basereg; 1665 int limitreg; 1666 1667 if ((win < 0) || (win > 2)) { 1668 #if defined DIAGNOSTIC 1669 printf("cardbus_io_close: window out of range %d\n", win); 1670 #endif 1671 return 0; 1672 } 1673 1674 basereg = win * 8 + 0x2c; 1675 limitreg = win * 8 + 0x30; 1676 1677 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1678 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1679 return 1; 1680 } 1681 1682 /* 1683 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1684 */ 1685 static int 1686 pccbb_mem_open(ct, win, start, end) 1687 cardbus_chipset_tag_t ct; 1688 int win; 1689 u_int32_t start, end; 1690 { 1691 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1692 int basereg; 1693 int limitreg; 1694 1695 if ((win < 0) || (win > 2)) { 1696 #if defined DIAGNOSTIC 1697 printf("cardbus_mem_open: window out of range %d\n", win); 1698 #endif 1699 return 0; 1700 } 1701 1702 basereg = win * 8 + 0x1c; 1703 limitreg = win * 8 + 0x20; 1704 1705 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1706 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1707 return 1; 1708 } 1709 1710 /* 1711 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1712 */ 1713 static int 1714 pccbb_mem_close(ct, win) 1715 cardbus_chipset_tag_t ct; 1716 int win; 1717 { 1718 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1719 int basereg; 1720 int limitreg; 1721 1722 if ((win < 0) || (win > 2)) { 1723 #if defined DIAGNOSTIC 1724 printf("cardbus_mem_close: window out of range %d\n", win); 1725 #endif 1726 return 0; 1727 } 1728 1729 basereg = win * 8 + 0x1c; 1730 limitreg = win * 8 + 0x20; 1731 1732 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1733 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1734 return 1; 1735 } 1736 #endif 1737 1738 /* 1739 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1740 * int irq, 1741 * int level, 1742 * int (* func) __P((void *)), 1743 * void *arg) 1744 * 1745 * This function registers an interrupt handler at the bridge, in 1746 * order not to call the interrupt handlers of child devices when 1747 * a card-deletion interrupt occurs. 1748 * 1749 * The arguments irq and level are not used. 1750 */ 1751 static void * 1752 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1753 cardbus_chipset_tag_t ct; 1754 int irq, level; 1755 int (*func) __P((void *)); 1756 void *arg; 1757 { 1758 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1759 1760 return pccbb_intr_establish(sc, irq, level, func, arg); 1761 } 1762 1763 1764 /* 1765 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1766 * void *ih) 1767 * 1768 * This function removes an interrupt handler pointed by ih. 1769 */ 1770 static void 1771 pccbb_cb_intr_disestablish(ct, ih) 1772 cardbus_chipset_tag_t ct; 1773 void *ih; 1774 { 1775 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1776 1777 pccbb_intr_disestablish(sc, ih); 1778 } 1779 1780 1781 void 1782 pccbb_intr_route(sc) 1783 struct pccbb_softc *sc; 1784 { 1785 pcireg_t reg; 1786 1787 /* initialize bridge intr routing */ 1788 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1789 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1790 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1791 1792 switch (sc->sc_chipset) { 1793 case CB_TI113X: 1794 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1795 /* functional intr enabled */ 1796 reg |= PCI113X_CBCTRL_PCI_INTR; 1797 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1798 break; 1799 default: 1800 break; 1801 } 1802 } 1803 1804 /* 1805 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1806 * int irq, 1807 * int level, 1808 * int (* func) __P((void *)), 1809 * void *arg) 1810 * 1811 * This function registers an interrupt handler at the bridge, in 1812 * order not to call the interrupt handlers of child devices when 1813 * a card-deletion interrupt occurs. 1814 * 1815 * The arguments irq is not used because pccbb selects intr vector. 1816 */ 1817 static void * 1818 pccbb_intr_establish(sc, irq, level, func, arg) 1819 struct pccbb_softc *sc; 1820 int irq, level; 1821 int (*func) __P((void *)); 1822 void *arg; 1823 { 1824 struct pccbb_intrhand_list *pil, *newpil; 1825 1826 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1827 1828 if (LIST_EMPTY(&sc->sc_pil)) { 1829 pccbb_intr_route(sc); 1830 } 1831 1832 /* 1833 * Allocate a room for interrupt handler structure. 1834 */ 1835 if (NULL == (newpil = 1836 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1837 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1838 return NULL; 1839 } 1840 1841 newpil->pil_func = func; 1842 newpil->pil_arg = arg; 1843 newpil->pil_level = level; 1844 1845 if (LIST_EMPTY(&sc->sc_pil)) { 1846 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1847 } else { 1848 for (pil = LIST_FIRST(&sc->sc_pil); 1849 LIST_NEXT(pil, pil_next) != NULL; 1850 pil = LIST_NEXT(pil, pil_next)); 1851 LIST_INSERT_AFTER(pil, newpil, pil_next); 1852 } 1853 1854 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1855 LIST_FIRST(&sc->sc_pil))); 1856 1857 return newpil; 1858 } 1859 1860 /* 1861 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1862 * void *ih) 1863 * 1864 * This function removes an interrupt handler pointed by ih. ih 1865 * should be the value returned by cardbus_intr_establish() or 1866 * NULL. 1867 * 1868 * When ih is NULL, this function will do nothing. 1869 */ 1870 static void 1871 pccbb_intr_disestablish(sc, ih) 1872 struct pccbb_softc *sc; 1873 void *ih; 1874 { 1875 struct pccbb_intrhand_list *pil; 1876 pcireg_t reg; 1877 1878 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1879 LIST_FIRST(&sc->sc_pil))); 1880 1881 if (ih == NULL) { 1882 /* intr handler is not set */ 1883 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1884 return; 1885 } 1886 1887 #ifdef DIAGNOSTIC 1888 for (pil = LIST_FIRST(&sc->sc_pil); pil != NULL; 1889 pil = LIST_NEXT(pil, pil_next)) { 1890 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1891 if (pil == ih) { 1892 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1893 break; 1894 } 1895 } 1896 if (pil == NULL) { 1897 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1898 sc->sc_dev.dv_xname, ih); 1899 } 1900 #endif 1901 1902 pil = (struct pccbb_intrhand_list *)ih; 1903 LIST_REMOVE(pil, pil_next); 1904 free(pil, M_DEVBUF); 1905 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1906 1907 if (LIST_EMPTY(&sc->sc_pil)) { 1908 /* No interrupt handlers */ 1909 1910 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1911 1912 /* stop routing PCI intr */ 1913 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1914 reg |= CB_BCR_INTR_IREQ_ENABLE; 1915 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1916 1917 switch (sc->sc_chipset) { 1918 case CB_TI113X: 1919 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1920 /* functional intr disabled */ 1921 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1922 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1923 break; 1924 default: 1925 break; 1926 } 1927 } 1928 } 1929 1930 #if defined SHOW_REGS 1931 static void 1932 cb_show_regs(pc, tag, memt, memh) 1933 pci_chipset_tag_t pc; 1934 pcitag_t tag; 1935 bus_space_tag_t memt; 1936 bus_space_handle_t memh; 1937 { 1938 int i; 1939 printf("PCI config regs:"); 1940 for (i = 0; i < 0x50; i += 4) { 1941 if (i % 16 == 0) { 1942 printf("\n 0x%02x:", i); 1943 } 1944 printf(" %08x", pci_conf_read(pc, tag, i)); 1945 } 1946 for (i = 0x80; i < 0xb0; i += 4) { 1947 if (i % 16 == 0) { 1948 printf("\n 0x%02x:", i); 1949 } 1950 printf(" %08x", pci_conf_read(pc, tag, i)); 1951 } 1952 1953 if (memh == 0) { 1954 printf("\n"); 1955 return; 1956 } 1957 1958 printf("\nsocket regs:"); 1959 for (i = 0; i <= 0x10; i += 0x04) { 1960 printf(" %08x", bus_space_read_4(memt, memh, i)); 1961 } 1962 printf("\nExCA regs:"); 1963 for (i = 0; i < 0x08; ++i) { 1964 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1965 } 1966 printf("\n"); 1967 return; 1968 } 1969 #endif 1970 1971 /* 1972 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1973 * int busno, int devno, int function) 1974 * This is the function to make a tag to access config space of 1975 * a CardBus Card. It works same as pci_conf_read. 1976 */ 1977 static cardbustag_t 1978 pccbb_make_tag(cc, busno, devno, function) 1979 cardbus_chipset_tag_t cc; 1980 int busno, devno, function; 1981 { 1982 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1983 1984 return pci_make_tag(sc->sc_pc, busno, devno, function); 1985 } 1986 1987 static void 1988 pccbb_free_tag(cc, tag) 1989 cardbus_chipset_tag_t cc; 1990 cardbustag_t tag; 1991 { 1992 } 1993 1994 /* 1995 * static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1996 * cardbustag_t tag, int offset) 1997 * This is the function to read the config space of a CardBus Card. 1998 * It works same as pci_conf_read. 1999 */ 2000 static cardbusreg_t 2001 pccbb_conf_read(cc, tag, offset) 2002 cardbus_chipset_tag_t cc; 2003 cardbustag_t tag; 2004 int offset; /* register offset */ 2005 { 2006 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2007 2008 return pci_conf_read(sc->sc_pc, tag, offset); 2009 } 2010 2011 /* 2012 * static void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 2013 * int offs, cardbusreg_t val) 2014 * This is the function to write the config space of a CardBus Card. 2015 * It works same as pci_conf_write. 2016 */ 2017 static void 2018 pccbb_conf_write(cc, tag, reg, val) 2019 cardbus_chipset_tag_t cc; 2020 cardbustag_t tag; 2021 int reg; /* register offset */ 2022 cardbusreg_t val; 2023 { 2024 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 2025 2026 pci_conf_write(sc->sc_pc, tag, reg, val); 2027 } 2028 2029 #if 0 2030 STATIC int 2031 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2032 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 2033 int speed, int flags, 2034 bus_space_handle_t * iohp) 2035 #endif 2036 /* 2037 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 2038 * bus_addr_t start, bus_size_t size, 2039 * bus_size_t align, 2040 * struct pcmcia_io_handle *pcihp 2041 * 2042 * This function only allocates I/O region for pccard. This function 2043 * never maps the allocated region to pccard I/O area. 2044 * 2045 * XXX: The interface of this function is not very good, I believe. 2046 */ 2047 STATIC int 2048 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 2049 pcmcia_chipset_handle_t pch; 2050 bus_addr_t start; /* start address */ 2051 bus_size_t size; 2052 bus_size_t align; 2053 struct pcmcia_io_handle *pcihp; 2054 { 2055 struct pcic_handle *ph = (struct pcic_handle *)pch; 2056 bus_addr_t ioaddr; 2057 int flags = 0; 2058 bus_space_tag_t iot; 2059 bus_space_handle_t ioh; 2060 bus_addr_t mask; 2061 #if rbus 2062 rbus_tag_t rb; 2063 #endif 2064 if (align == 0) { 2065 align = size; /* XXX: funny??? */ 2066 } 2067 2068 if (start != 0) { 2069 /* XXX: assume all card decode lower 10 bits by its hardware */ 2070 mask = 0x3ff; 2071 /* enforce to use only masked address */ 2072 start &= mask; 2073 } else { 2074 /* 2075 * calculate mask: 2076 * 1. get the most significant bit of size (call it msb). 2077 * 2. compare msb with the value of size. 2078 * 3. if size is larger, shift msb left once. 2079 * 4. obtain mask value to decrement msb. 2080 */ 2081 bus_size_t size_tmp = size; 2082 int shifts = 0; 2083 2084 mask = 1; 2085 while (size_tmp) { 2086 ++shifts; 2087 size_tmp >>= 1; 2088 } 2089 mask = (1 << shifts); 2090 if (mask < size) { 2091 mask <<= 1; 2092 } 2093 --mask; 2094 } 2095 2096 /* 2097 * Allocate some arbitrary I/O space. 2098 */ 2099 2100 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 2101 2102 #if rbus 2103 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 2104 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2105 return 1; 2106 } 2107 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2108 (u_long) ioaddr, (u_long) size)); 2109 #else 2110 if (start) { 2111 ioaddr = start; 2112 if (bus_space_map(iot, start, size, 0, &ioh)) { 2113 return 1; 2114 } 2115 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2116 (u_long) ioaddr, (u_long) size)); 2117 } else { 2118 flags |= PCMCIA_IO_ALLOCATED; 2119 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2120 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2121 size, align, 0, 0, &ioaddr, &ioh)) { 2122 /* No room be able to be get. */ 2123 return 1; 2124 } 2125 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2126 (u_long) ioaddr, (u_long) size)); 2127 } 2128 #endif 2129 2130 pcihp->iot = iot; 2131 pcihp->ioh = ioh; 2132 pcihp->addr = ioaddr; 2133 pcihp->size = size; 2134 pcihp->flags = flags; 2135 2136 return 0; 2137 } 2138 2139 /* 2140 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2141 * struct pcmcia_io_handle *pcihp) 2142 * 2143 * This function only frees I/O region for pccard. 2144 * 2145 * XXX: The interface of this function is not very good, I believe. 2146 */ 2147 void 2148 pccbb_pcmcia_io_free(pch, pcihp) 2149 pcmcia_chipset_handle_t pch; 2150 struct pcmcia_io_handle *pcihp; 2151 { 2152 #if !rbus 2153 bus_space_tag_t iot = pcihp->iot; 2154 #endif 2155 bus_space_handle_t ioh = pcihp->ioh; 2156 bus_size_t size = pcihp->size; 2157 2158 #if rbus 2159 struct pccbb_softc *sc = 2160 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 2161 rbus_tag_t rb = sc->sc_rbus_iot; 2162 2163 rbus_space_free(rb, ioh, size, NULL); 2164 #else 2165 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2166 bus_space_free(iot, ioh, size); 2167 else 2168 bus_space_unmap(iot, ioh, size); 2169 #endif 2170 } 2171 2172 /* 2173 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2174 * bus_addr_t offset, bus_size_t size, 2175 * struct pcmcia_io_handle *pcihp, 2176 * int *windowp) 2177 * 2178 * This function maps the allocated I/O region to pccard. This function 2179 * never allocates any I/O region for pccard I/O area. I don't 2180 * understand why the original authors of pcmciabus separated alloc and 2181 * map. I believe the two must be unite. 2182 * 2183 * XXX: no wait timing control? 2184 */ 2185 int 2186 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2187 pcmcia_chipset_handle_t pch; 2188 int width; 2189 bus_addr_t offset; 2190 bus_size_t size; 2191 struct pcmcia_io_handle *pcihp; 2192 int *windowp; 2193 { 2194 struct pcic_handle *ph = (struct pcic_handle *)pch; 2195 bus_addr_t ioaddr = pcihp->addr + offset; 2196 int i, win; 2197 #if defined CBB_DEBUG 2198 static char *width_names[] = { "dynamic", "io8", "io16" }; 2199 #endif 2200 2201 /* Sanity check I/O handle. */ 2202 2203 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2204 panic("pccbb_pcmcia_io_map iot is bogus"); 2205 } 2206 2207 /* XXX Sanity check offset/size. */ 2208 2209 win = -1; 2210 for (i = 0; i < PCIC_IO_WINS; i++) { 2211 if ((ph->ioalloc & (1 << i)) == 0) { 2212 win = i; 2213 ph->ioalloc |= (1 << i); 2214 break; 2215 } 2216 } 2217 2218 if (win == -1) { 2219 return 1; 2220 } 2221 2222 *windowp = win; 2223 2224 /* XXX this is pretty gross */ 2225 2226 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2227 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2228 2229 /* XXX wtf is this doing here? */ 2230 2231 #if 0 2232 printf(" port 0x%lx", (u_long) ioaddr); 2233 if (size > 1) { 2234 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2235 } 2236 #endif 2237 2238 ph->io[win].addr = ioaddr; 2239 ph->io[win].size = size; 2240 ph->io[win].width = width; 2241 2242 /* actual dirty register-value changing in the function below. */ 2243 pccbb_pcmcia_do_io_map(ph, win); 2244 2245 return 0; 2246 } 2247 2248 /* 2249 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2250 * 2251 * This function changes register-value to map I/O region for pccard. 2252 */ 2253 static void 2254 pccbb_pcmcia_do_io_map(ph, win) 2255 struct pcic_handle *ph; 2256 int win; 2257 { 2258 static u_int8_t pcic_iowidth[3] = { 2259 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2260 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2261 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2262 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2263 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2264 }; 2265 2266 #define PCIC_SIA_START_LOW 0 2267 #define PCIC_SIA_START_HIGH 1 2268 #define PCIC_SIA_STOP_LOW 2 2269 #define PCIC_SIA_STOP_HIGH 3 2270 2271 int regbase_win = 0x8 + win * 0x04; 2272 u_int8_t ioctl, enable; 2273 2274 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2275 "width %d\n", win, (unsigned long)ph->io[win].addr, 2276 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2277 2278 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2279 ph->io[win].addr & 0xff); 2280 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2281 (ph->io[win].addr >> 8) & 0xff); 2282 2283 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2284 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2285 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2286 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2287 2288 ioctl = Pcic_read(ph, PCIC_IOCTL); 2289 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2290 switch (win) { 2291 case 0: 2292 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2293 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2294 PCIC_IOCTL_IO0_DATASIZE_MASK); 2295 ioctl |= pcic_iowidth[ph->io[win].width]; 2296 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2297 break; 2298 case 1: 2299 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2300 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2301 PCIC_IOCTL_IO1_DATASIZE_MASK); 2302 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2303 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2304 break; 2305 } 2306 Pcic_write(ph, PCIC_IOCTL, ioctl); 2307 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2308 #if defined CBB_DEBUG 2309 { 2310 u_int8_t start_low = 2311 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2312 u_int8_t start_high = 2313 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2314 u_int8_t stop_low = 2315 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2316 u_int8_t stop_high = 2317 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2318 printf 2319 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2320 start_low, start_high, stop_low, stop_high, ioctl, enable); 2321 } 2322 #endif 2323 } 2324 2325 /* 2326 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2327 * 2328 * This function unmaps I/O region. No return value. 2329 */ 2330 STATIC void 2331 pccbb_pcmcia_io_unmap(pch, win) 2332 pcmcia_chipset_handle_t pch; 2333 int win; 2334 { 2335 struct pcic_handle *ph = (struct pcic_handle *)pch; 2336 int reg; 2337 2338 if (win >= PCIC_IO_WINS || win < 0) { 2339 panic("pccbb_pcmcia_io_unmap: window out of range"); 2340 } 2341 2342 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2343 switch (win) { 2344 case 0: 2345 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2346 break; 2347 case 1: 2348 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2349 break; 2350 } 2351 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2352 2353 ph->ioalloc &= ~(1 << win); 2354 } 2355 2356 /* 2357 * static void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2358 * 2359 * This function enables the card. All information is stored in 2360 * the first argument, pcmcia_chipset_handle_t. 2361 */ 2362 static int 2363 pccbb_pcmcia_wait_ready(ph) 2364 struct pcic_handle *ph; 2365 { 2366 u_char stat; 2367 int i; 2368 2369 DPRINTF(("entering pccbb_pcmcia_wait_ready: status 0x%02x\n", 2370 Pcic_read(ph, PCIC_IF_STATUS))); 2371 2372 for (i = 0; i < 2000; i++) { 2373 stat = Pcic_read(ph, PCIC_IF_STATUS); 2374 if (stat & PCIC_IF_STATUS_READY) 2375 return 1; 2376 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2377 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2378 return 0; 2379 DELAY_MS(2, ph->ph_parent); 2380 #ifdef CBB_DEBUG 2381 if ((i > 1000) && (i % 25 == 24)) 2382 printf("."); 2383 #endif 2384 } 2385 2386 #ifdef DIAGNOSTIC 2387 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2388 Pcic_read(ph, PCIC_IF_STATUS)); 2389 #endif 2390 2391 return 0; 2392 } 2393 2394 /* 2395 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2396 * 2397 * This function enables the card. All information is stored in 2398 * the first argument, pcmcia_chipset_handle_t. 2399 */ 2400 STATIC void 2401 pccbb_pcmcia_socket_enable(pch) 2402 pcmcia_chipset_handle_t pch; 2403 { 2404 struct pcic_handle *ph = (struct pcic_handle *)pch; 2405 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2406 int cardtype, win; 2407 u_int8_t power, intr; 2408 pcireg_t spsr; 2409 int voltage; 2410 2411 /* this bit is mostly stolen from pcic_attach_card */ 2412 2413 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2414 2415 /* get card Vcc info */ 2416 2417 spsr = 2418 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2419 CB_SOCKET_STAT); 2420 if (spsr & CB_SOCKET_STAT_5VCARD) { 2421 DPRINTF(("5V card\n")); 2422 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2423 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2424 DPRINTF(("3V card\n")); 2425 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2426 } else { 2427 printf("?V card, 0x%x\n", spsr); /* XXX */ 2428 return; 2429 } 2430 2431 /* disable socket: negate output enable bit and power off */ 2432 2433 power = 0; 2434 Pcic_write(ph, PCIC_PWRCTL, power); 2435 2436 /* power down the socket to reset it, clear the card reset pin */ 2437 2438 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2439 2440 /* 2441 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2442 * we are changing Vcc (Toff). 2443 */ 2444 /* delay(300*1000); too much */ 2445 2446 /* assert reset bit */ 2447 intr = Pcic_read(ph, PCIC_INTR); 2448 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2449 Pcic_write(ph, PCIC_INTR, intr); 2450 2451 /* power up the socket */ 2452 power = Pcic_read(ph, PCIC_PWRCTL); 2453 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 2454 pccbb_power(sc, voltage); 2455 2456 /* now output enable */ 2457 power = Pcic_read(ph, PCIC_PWRCTL); 2458 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2459 2460 if (pccbb_power(sc, voltage) == 0) { 2461 power &= PCIC_PWRCTL_OE; 2462 Pcic_write(ph, PCIC_PWRCTL, power); 2463 intr |= PCIC_INTR_RESET; 2464 Pcic_write(ph, PCIC_INTR, intr); 2465 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2466 return; 2467 } 2468 2469 /* 2470 * hold RESET at least 20 ms: the spec says only 10 us is 2471 * enough, but TI1130 requires at least 20 ms. 2472 */ 2473 #if 0 /* XXX called on interrupt context */ 2474 DELAY_MS(20, sc); 2475 #else 2476 delay(20 * 1000); 2477 #endif 2478 2479 /* clear the reset flag */ 2480 2481 intr |= PCIC_INTR_RESET; 2482 Pcic_write(ph, PCIC_INTR, intr); 2483 2484 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2485 2486 #if 0 /* XXX called on interrupt context */ 2487 DELAY_MS(20, sc); 2488 #else 2489 delay(20 * 1000); 2490 #endif 2491 2492 /* wait for the chip to finish initializing */ 2493 2494 if (pccbb_pcmcia_wait_ready(ph) == 0) { 2495 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2496 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2497 return; 2498 } 2499 2500 /* zero out the address windows */ 2501 2502 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2503 2504 /* set the card type */ 2505 2506 cardtype = pcmcia_card_gettype(ph->pcmcia); 2507 2508 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2509 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2510 Pcic_write(ph, PCIC_INTR, intr); 2511 2512 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2513 ph->ph_parent->dv_xname, ph->sock, 2514 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2515 2516 /* reinstall all the memory and io mappings */ 2517 2518 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2519 if (ph->memalloc & (1 << win)) { 2520 pccbb_pcmcia_do_mem_map(ph, win); 2521 } 2522 } 2523 2524 for (win = 0; win < PCIC_IO_WINS; ++win) { 2525 if (ph->ioalloc & (1 << win)) { 2526 pccbb_pcmcia_do_io_map(ph, win); 2527 } 2528 } 2529 } 2530 2531 /* 2532 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2533 * 2534 * This function disables the card. All information is stored in 2535 * the first argument, pcmcia_chipset_handle_t. 2536 */ 2537 STATIC void 2538 pccbb_pcmcia_socket_disable(pch) 2539 pcmcia_chipset_handle_t pch; 2540 { 2541 struct pcic_handle *ph = (struct pcic_handle *)pch; 2542 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2543 u_int8_t power, intr; 2544 2545 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2546 2547 /* reset signal asserting... */ 2548 2549 intr = Pcic_read(ph, PCIC_INTR); 2550 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2551 Pcic_write(ph, PCIC_INTR, intr); 2552 delay(2 * 1000); 2553 2554 /* power down the socket */ 2555 power = Pcic_read(ph, PCIC_PWRCTL); 2556 power &= ~PCIC_PWRCTL_OE; 2557 Pcic_write(ph, PCIC_PWRCTL, power); 2558 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2559 /* 2560 * wait 300ms until power fails (Tpf). 2561 */ 2562 #if 0 /* XXX called on interrupt context */ 2563 DELAY_MS(300, sc); 2564 #else 2565 delay(300 * 1000); 2566 #endif 2567 } 2568 2569 /* 2570 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2571 * 2572 * This function detects whether a card is in the slot or not. 2573 * If a card is inserted, return 1. Otherwise, return 0. 2574 */ 2575 STATIC int 2576 pccbb_pcmcia_card_detect(pch) 2577 pcmcia_chipset_handle_t pch; 2578 { 2579 struct pcic_handle *ph = (struct pcic_handle *)pch; 2580 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2581 2582 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2583 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2584 } 2585 2586 #if 0 2587 STATIC int 2588 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2589 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2590 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2591 #endif 2592 /* 2593 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2594 * bus_size_t size, 2595 * struct pcmcia_mem_handle *pcmhp) 2596 * 2597 * This function only allocates memory region for pccard. This 2598 * function never maps the allocated region to pccard memory area. 2599 * 2600 * XXX: Why the argument of start address is not in? 2601 */ 2602 STATIC int 2603 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2604 pcmcia_chipset_handle_t pch; 2605 bus_size_t size; 2606 struct pcmcia_mem_handle *pcmhp; 2607 { 2608 struct pcic_handle *ph = (struct pcic_handle *)pch; 2609 bus_space_handle_t memh; 2610 bus_addr_t addr; 2611 bus_size_t sizepg; 2612 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2613 #if rbus 2614 rbus_tag_t rb; 2615 #endif 2616 2617 /* Check that the card is still there. */ 2618 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2619 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2620 return 1; 2621 2622 /* out of sc->memh, allocate as many pages as necessary */ 2623 2624 /* convert size to PCIC pages */ 2625 /* 2626 * This is not enough; when the requested region is on the page 2627 * boundaries, this may calculate wrong result. 2628 */ 2629 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2630 #if 0 2631 if (sizepg > PCIC_MAX_MEM_PAGES) { 2632 return 1; 2633 } 2634 #endif 2635 2636 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2637 return 1; 2638 } 2639 2640 addr = 0; /* XXX gcc -Wuninitialized */ 2641 2642 #if rbus 2643 rb = sc->sc_rbus_memt; 2644 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2645 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2646 &addr, &memh)) { 2647 return 1; 2648 } 2649 #else 2650 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2651 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2652 0, /* boundary */ 2653 0, /* flags */ 2654 &addr, &memh)) { 2655 return 1; 2656 } 2657 #endif 2658 2659 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2660 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2661 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2662 2663 pcmhp->memt = sc->sc_memt; 2664 pcmhp->memh = memh; 2665 pcmhp->addr = addr; 2666 pcmhp->size = size; 2667 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2668 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2669 pcmhp->mhandle = 0; 2670 /* No offset??? Funny. */ 2671 2672 return 0; 2673 } 2674 2675 /* 2676 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2677 * struct pcmcia_mem_handle *pcmhp) 2678 * 2679 * This function release the memory space allocated by the function 2680 * pccbb_pcmcia_mem_alloc(). 2681 */ 2682 STATIC void 2683 pccbb_pcmcia_mem_free(pch, pcmhp) 2684 pcmcia_chipset_handle_t pch; 2685 struct pcmcia_mem_handle *pcmhp; 2686 { 2687 #if rbus 2688 struct pcic_handle *ph = (struct pcic_handle *)pch; 2689 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2690 2691 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2692 #else 2693 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2694 #endif 2695 } 2696 2697 /* 2698 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2699 * 2700 * This function release the memory space allocated by the function 2701 * pccbb_pcmcia_mem_alloc(). 2702 */ 2703 STATIC void 2704 pccbb_pcmcia_do_mem_map(ph, win) 2705 struct pcic_handle *ph; 2706 int win; 2707 { 2708 int regbase_win; 2709 bus_addr_t phys_addr; 2710 bus_addr_t phys_end; 2711 2712 #define PCIC_SMM_START_LOW 0 2713 #define PCIC_SMM_START_HIGH 1 2714 #define PCIC_SMM_STOP_LOW 2 2715 #define PCIC_SMM_STOP_HIGH 3 2716 #define PCIC_CMA_LOW 4 2717 #define PCIC_CMA_HIGH 5 2718 2719 u_int8_t start_low, start_high = 0; 2720 u_int8_t stop_low, stop_high; 2721 u_int8_t off_low, off_high; 2722 u_int8_t mem_window; 2723 int reg; 2724 2725 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2726 int mem8 = 2727 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2728 || (kind == PCMCIA_MEM_ATTR); 2729 2730 regbase_win = 0x10 + win * 0x08; 2731 2732 phys_addr = ph->mem[win].addr; 2733 phys_end = phys_addr + ph->mem[win].size; 2734 2735 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2736 (unsigned long)phys_addr, (unsigned long)phys_end, 2737 (unsigned long)ph->mem[win].offset)); 2738 2739 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2740 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2741 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2742 2743 /* bit 19:12 */ 2744 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2745 /* bit 23:20 and bit 7 on */ 2746 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2747 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2748 /* bit 31:24, for 32-bit address */ 2749 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2750 2751 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2752 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2753 2754 if (((struct pccbb_softc *)ph-> 2755 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2756 Pcic_write(ph, 0x40 + win, mem_window); 2757 } 2758 2759 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2760 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2761 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2762 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2763 2764 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2765 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2766 2767 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2768 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2769 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2770 | ((kind == PCMCIA_MEM_ATTR) ? 2771 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2772 2773 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2774 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2775 2776 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2777 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2778 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2779 2780 #if defined CBB_DEBUG 2781 { 2782 int r1, r2, r3, r4, r5, r6, r7 = 0; 2783 2784 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2785 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2786 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2787 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2788 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2789 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2790 if (((struct pccbb_softc *)(ph-> 2791 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2792 r7 = Pcic_read(ph, 0x40 + win); 2793 } 2794 2795 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2796 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2797 if (((struct pccbb_softc *)(ph-> 2798 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2799 DPRINTF((" %02x", r7)); 2800 } 2801 DPRINTF(("\n")); 2802 } 2803 #endif 2804 } 2805 2806 /* 2807 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2808 * bus_addr_t card_addr, bus_size_t size, 2809 * struct pcmcia_mem_handle *pcmhp, 2810 * bus_addr_t *offsetp, int *windowp) 2811 * 2812 * This function maps memory space allocated by the function 2813 * pccbb_pcmcia_mem_alloc(). 2814 */ 2815 STATIC int 2816 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2817 pcmcia_chipset_handle_t pch; 2818 int kind; 2819 bus_addr_t card_addr; 2820 bus_size_t size; 2821 struct pcmcia_mem_handle *pcmhp; 2822 bus_addr_t *offsetp; 2823 int *windowp; 2824 { 2825 struct pcic_handle *ph = (struct pcic_handle *)pch; 2826 bus_addr_t busaddr; 2827 long card_offset; 2828 int win; 2829 2830 /* Check that the card is still there. */ 2831 if ((Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2832 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2833 return 1; 2834 2835 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2836 if ((ph->memalloc & (1 << win)) == 0) { 2837 ph->memalloc |= (1 << win); 2838 break; 2839 } 2840 } 2841 2842 if (win == PCIC_MEM_WINS) { 2843 return 1; 2844 } 2845 2846 *windowp = win; 2847 2848 /* XXX this is pretty gross */ 2849 2850 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2851 panic("pccbb_pcmcia_mem_map memt is bogus"); 2852 } 2853 2854 busaddr = pcmhp->addr; 2855 2856 /* 2857 * compute the address offset to the pcmcia address space for the 2858 * pcic. this is intentionally signed. The masks and shifts below 2859 * will cause TRT to happen in the pcic registers. Deal with making 2860 * sure the address is aligned, and return the alignment offset. 2861 */ 2862 2863 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2864 card_addr -= *offsetp; 2865 2866 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2867 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2868 (u_long) card_addr)); 2869 2870 /* 2871 * include the offset in the size, and decrement size by one, since 2872 * the hw wants start/stop 2873 */ 2874 size += *offsetp - 1; 2875 2876 card_offset = (((long)card_addr) - ((long)busaddr)); 2877 2878 ph->mem[win].addr = busaddr; 2879 ph->mem[win].size = size; 2880 ph->mem[win].offset = card_offset; 2881 ph->mem[win].kind = kind; 2882 2883 pccbb_pcmcia_do_mem_map(ph, win); 2884 2885 return 0; 2886 } 2887 2888 /* 2889 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2890 * int window) 2891 * 2892 * This function unmaps memory space which mapped by the function 2893 * pccbb_pcmcia_mem_map(). 2894 */ 2895 STATIC void 2896 pccbb_pcmcia_mem_unmap(pch, window) 2897 pcmcia_chipset_handle_t pch; 2898 int window; 2899 { 2900 struct pcic_handle *ph = (struct pcic_handle *)pch; 2901 int reg; 2902 2903 if (window >= PCIC_MEM_WINS) { 2904 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2905 } 2906 2907 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2908 reg &= ~(1 << window); 2909 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2910 2911 ph->memalloc &= ~(1 << window); 2912 } 2913 2914 #if defined PCCBB_PCMCIA_POLL 2915 struct pccbb_poll_str { 2916 void *arg; 2917 int (*func) __P((void *)); 2918 int level; 2919 struct pcic_handle *ph; 2920 int count; 2921 int num; 2922 struct callout poll_ch; 2923 }; 2924 2925 static struct pccbb_poll_str pccbb_poll[10]; 2926 static int pccbb_poll_n = 0; 2927 2928 static void pccbb_pcmcia_poll __P((void *arg)); 2929 2930 static void 2931 pccbb_pcmcia_poll(arg) 2932 void *arg; 2933 { 2934 struct pccbb_poll_str *poll = arg; 2935 struct pcic_handle *ph = poll->ph; 2936 struct pccbb_softc *sc = ph->sc; 2937 int s; 2938 u_int32_t spsr; /* socket present-state reg */ 2939 2940 callout_reset(&poll->poll_ch, hz * 2, pccbb_pcmcia_poll, arg); 2941 switch (poll->level) { 2942 case IPL_NET: 2943 s = splnet(); 2944 break; 2945 case IPL_BIO: 2946 s = splbio(); 2947 break; 2948 case IPL_TTY: /* fallthrough */ 2949 default: 2950 s = spltty(); 2951 break; 2952 } 2953 2954 spsr = 2955 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2956 CB_SOCKET_STAT); 2957 2958 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2959 if (!(spsr & 0x40)) /* CINT low */ 2960 #else 2961 if (1) 2962 #endif 2963 { 2964 if ((*poll->func) (poll->arg) > 0) { 2965 ++poll->count; 2966 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2967 #if defined LEVEL2 2968 } else { 2969 printf("intr: miss! 0x%x\n", spsr); 2970 #endif 2971 } 2972 } 2973 splx(s); 2974 } 2975 #endif /* defined CB_PCMCIA_POLL */ 2976 2977 /* 2978 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2979 * struct pcmcia_function *pf, 2980 * int ipl, 2981 * int (*func)(void *), 2982 * void *arg); 2983 * 2984 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2985 */ 2986 STATIC void * 2987 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2988 pcmcia_chipset_handle_t pch; 2989 struct pcmcia_function *pf; 2990 int ipl; 2991 int (*func) __P((void *)); 2992 void *arg; 2993 { 2994 struct pcic_handle *ph = (struct pcic_handle *)pch; 2995 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2996 2997 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2998 /* what should I do? */ 2999 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 3000 DPRINTF(("%s does not provide edge nor pulse " 3001 "interrupt\n", sc->sc_dev.dv_xname)); 3002 return NULL; 3003 } 3004 /* 3005 * XXX Noooooo! The interrupt flag must set properly!! 3006 * dumb pcmcia driver!! 3007 */ 3008 } 3009 3010 return pccbb_intr_establish(sc, 0, ipl, func, arg); 3011 } 3012 3013 /* 3014 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 3015 * void *ih) 3016 * 3017 * This function disables PC-Card interrupt. 3018 */ 3019 STATIC void 3020 pccbb_pcmcia_intr_disestablish(pch, ih) 3021 pcmcia_chipset_handle_t pch; 3022 void *ih; 3023 { 3024 struct pcic_handle *ph = (struct pcic_handle *)pch; 3025 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 3026 3027 pccbb_intr_disestablish(sc, ih); 3028 } 3029 3030 #if rbus 3031 /* 3032 * static int 3033 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 3034 * bus_addr_t addr, bus_size_t size, 3035 * bus_addr_t mask, bus_size_t align, 3036 * int flags, bus_addr_t *addrp; 3037 * bus_space_handle_t *bshp) 3038 * 3039 * This function allocates a portion of memory or io space for 3040 * clients. This function is called from CardBus card drivers. 3041 */ 3042 static int 3043 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 3044 cardbus_chipset_tag_t ct; 3045 rbus_tag_t rb; 3046 bus_addr_t addr; 3047 bus_size_t size; 3048 bus_addr_t mask; 3049 bus_size_t align; 3050 int flags; 3051 bus_addr_t *addrp; 3052 bus_space_handle_t *bshp; 3053 { 3054 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3055 3056 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 3057 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 3058 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 3059 3060 if (align == 0) { 3061 align = size; 3062 } 3063 3064 if (rb->rb_bt == sc->sc_memt) { 3065 if (align < 16) { 3066 return 1; 3067 } 3068 /* 3069 * XXX: align more than 0x1000 to avoid overwrapping 3070 * memory windows for two or more devices. 0x1000 3071 * means memory window's granularity. 3072 * 3073 * Two or more devices should be able to share same 3074 * memory window region. However, overrapping memory 3075 * window is not good because some devices, such as 3076 * 3Com 3C575[BC], have a broken address decoder and 3077 * intrude other's memory region. 3078 */ 3079 if (align < 0x1000) { 3080 align = 0x1000; 3081 } 3082 } else if (rb->rb_bt == sc->sc_iot) { 3083 if (align < 4) { 3084 return 1; 3085 } 3086 /* XXX: hack for avoiding ISA image */ 3087 if (mask < 0x0100) { 3088 mask = 0x3ff; 3089 addr = 0x300; 3090 } 3091 3092 } else { 3093 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 3094 "NOT used. io: 0x%lx, mem: 0x%lx\n", 3095 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 3096 (unsigned long)sc->sc_memt)); 3097 return 1; 3098 /* XXX: panic here? */ 3099 } 3100 3101 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 3102 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 3103 return 1; 3104 } 3105 3106 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 3107 3108 return 0; 3109 } 3110 3111 /* 3112 * static int 3113 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 3114 * bus_space_handle_t *bshp, bus_size_t size); 3115 * 3116 * This function is called from CardBus card drivers. 3117 */ 3118 static int 3119 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 3120 cardbus_chipset_tag_t ct; 3121 rbus_tag_t rb; 3122 bus_space_handle_t bsh; 3123 bus_size_t size; 3124 { 3125 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 3126 bus_space_tag_t bt = rb->rb_bt; 3127 3128 pccbb_close_win(sc, bt, bsh, size); 3129 3130 if (bt == sc->sc_memt) { 3131 } else if (bt == sc->sc_iot) { 3132 } else { 3133 return 1; 3134 /* XXX: panic here? */ 3135 } 3136 3137 return rbus_space_free(rb, bsh, size, NULL); 3138 } 3139 #endif /* rbus */ 3140 3141 #if rbus 3142 3143 static int 3144 pccbb_open_win(sc, bst, addr, size, bsh, flags) 3145 struct pccbb_softc *sc; 3146 bus_space_tag_t bst; 3147 bus_addr_t addr; 3148 bus_size_t size; 3149 bus_space_handle_t bsh; 3150 int flags; 3151 { 3152 struct pccbb_win_chain_head *head; 3153 bus_addr_t align; 3154 3155 head = &sc->sc_iowindow; 3156 align = 0x04; 3157 if (sc->sc_memt == bst) { 3158 head = &sc->sc_memwindow; 3159 align = 0x1000; 3160 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 3161 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 3162 (unsigned long)bst)); 3163 } 3164 3165 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 3166 printf("%s: pccbb_open_win: %s winlist insert failed\n", 3167 sc->sc_dev.dv_xname, 3168 (head == &sc->sc_memwindow) ? "mem" : "io"); 3169 } 3170 pccbb_winset(align, sc, bst); 3171 3172 return 0; 3173 } 3174 3175 static int 3176 pccbb_close_win(sc, bst, bsh, size) 3177 struct pccbb_softc *sc; 3178 bus_space_tag_t bst; 3179 bus_space_handle_t bsh; 3180 bus_size_t size; 3181 { 3182 struct pccbb_win_chain_head *head; 3183 bus_addr_t align; 3184 3185 head = &sc->sc_iowindow; 3186 align = 0x04; 3187 if (sc->sc_memt == bst) { 3188 head = &sc->sc_memwindow; 3189 align = 0x1000; 3190 } 3191 3192 if (pccbb_winlist_delete(head, bsh, size)) { 3193 printf("%s: pccbb_close_win: %s winlist delete failed\n", 3194 sc->sc_dev.dv_xname, 3195 (head == &sc->sc_memwindow) ? "mem" : "io"); 3196 } 3197 pccbb_winset(align, sc, bst); 3198 3199 return 0; 3200 } 3201 3202 static int 3203 pccbb_winlist_insert(head, start, size, bsh, flags) 3204 struct pccbb_win_chain_head *head; 3205 bus_addr_t start; 3206 bus_size_t size; 3207 bus_space_handle_t bsh; 3208 int flags; 3209 { 3210 struct pccbb_win_chain *chainp, *elem; 3211 3212 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 3213 M_NOWAIT)) == NULL) 3214 return (1); /* fail */ 3215 3216 elem->wc_start = start; 3217 elem->wc_end = start + (size - 1); 3218 elem->wc_handle = bsh; 3219 elem->wc_flags = flags; 3220 3221 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3222 chainp = TAILQ_NEXT(chainp, wc_list)) { 3223 if (chainp->wc_end < start) 3224 continue; 3225 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 3226 return (0); 3227 } 3228 3229 TAILQ_INSERT_TAIL(head, elem, wc_list); 3230 return (0); 3231 } 3232 3233 static int 3234 pccbb_winlist_delete(head, bsh, size) 3235 struct pccbb_win_chain_head *head; 3236 bus_space_handle_t bsh; 3237 bus_size_t size; 3238 { 3239 struct pccbb_win_chain *chainp; 3240 3241 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3242 chainp = TAILQ_NEXT(chainp, wc_list)) { 3243 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 3244 continue; 3245 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3246 printf("pccbb_winlist_delete: window 0x%lx size " 3247 "inconsistent: 0x%lx, 0x%lx\n", 3248 (unsigned long)chainp->wc_start, 3249 (unsigned long)(chainp->wc_end - chainp->wc_start), 3250 (unsigned long)(size - 1)); 3251 return 1; 3252 } 3253 3254 TAILQ_REMOVE(head, chainp, wc_list); 3255 free(chainp, M_DEVBUF); 3256 3257 return 0; 3258 } 3259 3260 return 1; /* fail: no candidate to remove */ 3261 } 3262 3263 static void 3264 pccbb_winset(align, sc, bst) 3265 bus_addr_t align; 3266 struct pccbb_softc *sc; 3267 bus_space_tag_t bst; 3268 { 3269 pci_chipset_tag_t pc; 3270 pcitag_t tag; 3271 bus_addr_t mask = ~(align - 1); 3272 struct { 3273 cardbusreg_t win_start; 3274 cardbusreg_t win_limit; 3275 int win_flags; 3276 } win[2]; 3277 struct pccbb_win_chain *chainp; 3278 int offs; 3279 3280 win[0].win_start = win[1].win_start = 0xffffffff; 3281 win[0].win_limit = win[1].win_limit = 0; 3282 win[0].win_flags = win[1].win_flags = 0; 3283 3284 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3285 offs = 0x2c; 3286 if (sc->sc_memt == bst) { 3287 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3288 offs = 0x1c; 3289 } 3290 3291 if (chainp != NULL) { 3292 win[0].win_start = chainp->wc_start & mask; 3293 win[0].win_limit = chainp->wc_end & mask; 3294 win[0].win_flags = chainp->wc_flags; 3295 chainp = TAILQ_NEXT(chainp, wc_list); 3296 } 3297 3298 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3299 if (win[1].win_start == 0xffffffff) { 3300 /* window 1 is not used */ 3301 if ((win[0].win_flags == chainp->wc_flags) && 3302 (win[0].win_limit + align >= 3303 (chainp->wc_start & mask))) { 3304 /* concatenate */ 3305 win[0].win_limit = chainp->wc_end & mask; 3306 } else { 3307 /* make new window */ 3308 win[1].win_start = chainp->wc_start & mask; 3309 win[1].win_limit = chainp->wc_end & mask; 3310 win[1].win_flags = chainp->wc_flags; 3311 } 3312 continue; 3313 } 3314 3315 /* Both windows are engaged. */ 3316 if (win[0].win_flags == win[1].win_flags) { 3317 /* same flags */ 3318 if (win[0].win_flags == chainp->wc_flags) { 3319 if (win[1].win_start - (win[0].win_limit + 3320 align) < 3321 (chainp->wc_start & mask) - 3322 ((chainp->wc_end & mask) + align)) { 3323 /* 3324 * merge window 0 and 1, and set win1 3325 * to chainp 3326 */ 3327 win[0].win_limit = win[1].win_limit; 3328 win[1].win_start = 3329 chainp->wc_start & mask; 3330 win[1].win_limit = 3331 chainp->wc_end & mask; 3332 } else { 3333 win[1].win_limit = 3334 chainp->wc_end & mask; 3335 } 3336 } else { 3337 /* different flags */ 3338 3339 /* concatenate win0 and win1 */ 3340 win[0].win_limit = win[1].win_limit; 3341 /* allocate win[1] to new space */ 3342 win[1].win_start = chainp->wc_start & mask; 3343 win[1].win_limit = chainp->wc_end & mask; 3344 win[1].win_flags = chainp->wc_flags; 3345 } 3346 } else { 3347 /* the flags of win[0] and win[1] is different */ 3348 if (win[0].win_flags == chainp->wc_flags) { 3349 win[0].win_limit = chainp->wc_end & mask; 3350 /* 3351 * XXX this creates overlapping windows, so 3352 * what should the poor bridge do if one is 3353 * cachable, and the other is not? 3354 */ 3355 printf("%s: overlapping windows\n", 3356 sc->sc_dev.dv_xname); 3357 } else { 3358 win[1].win_limit = chainp->wc_end & mask; 3359 } 3360 } 3361 } 3362 3363 pc = sc->sc_pc; 3364 tag = sc->sc_tag; 3365 pci_conf_write(pc, tag, offs, win[0].win_start); 3366 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3367 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3368 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3369 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3370 (unsigned long)pci_conf_read(pc, tag, offs), 3371 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3372 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3373 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3374 3375 if (bst == sc->sc_memt) { 3376 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3377 3378 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3379 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3380 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3381 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3382 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3383 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3384 } 3385 } 3386 3387 #endif /* rbus */ 3388 3389 static void 3390 pccbb_powerhook(why, arg) 3391 int why; 3392 void *arg; 3393 { 3394 struct pccbb_softc *sc = arg; 3395 pcireg_t reg; 3396 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3397 bus_space_handle_t base_memh = sc->sc_base_memh; 3398 3399 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3400 3401 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3402 DPRINTF(("%s: power: why %d stopping intr\n", 3403 sc->sc_dev.dv_xname, why)); 3404 if (sc->sc_pil_intr_enable) { 3405 (void)pccbbintr_function(sc); 3406 } 3407 sc->sc_pil_intr_enable = 0; 3408 3409 /* ToDo: deactivate or suspend child devices */ 3410 3411 } 3412 3413 if (why == PWR_RESUME) { 3414 if (sc->sc_pwrmgt_offs != 0) { 3415 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 3416 sc->sc_pwrmgt_offs + 4); 3417 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0 || 3418 reg & 0x100) { 3419 /* powrstate != D0 */ 3420 3421 printf("%s going back to D0 mode\n", 3422 sc->sc_dev.dv_xname); 3423 reg &= ~PCI_PMCSR_STATE_MASK; 3424 reg |= PCI_PMCSR_STATE_D0; 3425 reg &= ~(0x100 /* PCI_PMCSR_PME_EN */); 3426 pci_conf_write(sc->sc_pc, sc->sc_tag, 3427 sc->sc_pwrmgt_offs + 4, reg); 3428 3429 pci_conf_write(sc->sc_pc, sc->sc_tag, 3430 PCI_SOCKBASE, sc->sc_sockbase); 3431 pci_conf_write(sc->sc_pc, sc->sc_tag, 3432 PCI_BUSNUM, sc->sc_busnum); 3433 pccbb_chipinit(sc); 3434 /* setup memory and io space window for CB */ 3435 pccbb_winset(0x1000, sc, sc->sc_memt); 3436 pccbb_winset(0x04, sc, sc->sc_iot); 3437 } 3438 } 3439 3440 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3441 /* BIOS did not recover this register */ 3442 pci_conf_write (sc->sc_pc, sc->sc_tag, 3443 PCI_SOCKBASE, sc->sc_sockbase); 3444 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3445 /* BIOS did not recover this register */ 3446 pci_conf_write (sc->sc_pc, sc->sc_tag, 3447 PCI_BUSNUM, sc->sc_busnum); 3448 /* CSC Interrupt: Card detect interrupt on */ 3449 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3450 /* Card detect intr is turned on. */ 3451 reg |= CB_SOCKET_MASK_CD; 3452 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3453 /* reset interrupt */ 3454 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3455 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3456 3457 /* 3458 * check for card insertion or removal during suspend period. 3459 * XXX: the code can't cope with card swap (remove then 3460 * insert). how can we detect such situation? 3461 */ 3462 (void)pccbbintr(sc); 3463 3464 sc->sc_pil_intr_enable = 1; 3465 DPRINTF(("%s: power: RESUME enabling intr\n", 3466 sc->sc_dev.dv_xname)); 3467 3468 /* ToDo: activate or wakeup child devices */ 3469 } 3470 } 3471
Indexes created Thu Sep 25 16:09:42 GMT 2025