pccbbreg.h revision 1.11
1 /* $NetBSD: pccbbreg.h,v 1.11 2006/06/17 17:06:52 jmcneill Exp $ */ 2 /* 3 * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by HAYAKAWA Koichi. 16 * 4. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 32 #ifndef _DEV_PCI_PCCBBREG_H_ 33 #define _DEV_PCI_PCCBBREG_H_ 34 35 36 37 38 #define PCI_SOCKBASE 0x10 /* Socket Base Address Register */ 39 #define PCI_BUSNUM 0x18 /* latency timer, Subordinate bus number */ 40 #define PCI_BCR_INTR 0x3C /* intr line, intr pin, bridge control regs */ 41 #define PCI_LEGACY 0x44 /* legacy IO register address (32 bits) */ 42 #define PCI_SYSCTRL 0x80 /* System control */ 43 #define PCI_CBCTRL 0x90 /* Retry status, Card ctrl, Device ctrl */ 44 45 #define PCI_CLASS_INTERFACE_MASK 0xffffff00 46 #define PCI_CLASS_INTERFACE_YENTA 0x06070000 47 48 #define CB_SOCKET_EVENT 0x00 /* offset of cardbus socket event reg */ 49 #define CB_SOCKET_MASK 0x04 /* offset of cardbus socket mask register */ 50 #define CB_SOCKET_STAT 0x08 /* offset of cardbus socket present-state */ 51 #define CB_SOCKET_FORCE 0x0c /* offset of cardbus socket force event */ 52 #define CB_SOCKET_CTRL 0x10 /* offset of cardbus socket control reg */ 53 54 #define PCCBB_SOCKEVENT_BITS "\020\001CSTS\002CD1\003CD2\004PWR" 55 #define PCCBB_SOCKSTATE_BITS "\020\001CSTS\002CD1\003CD3\004PWR" \ 56 "\00516BIT\006CB\007CINT\010NOTA\011DLOST\012BADVCC" \ 57 "\0135v\0143v\015Xv\016Yv\0355vS\0363vS\037XvS\040YvS" 58 59 /* CardBus latency timer, Subordinate bus no, CardBus bus no and PCI bus no */ 60 #define PCI_CB_LSCP_REG 0x18 61 /* CardBus memory and io windows */ 62 #define PCI_CB_MEMBASE0 0x1c 63 #define PCI_CB_MEMLIMIT0 0x20 64 #define PCI_CB_MEMBASE1 0x24 65 #define PCI_CB_MEMLIMIT1 0x28 66 #define PCI_CB_IOBASE0 0x2c 67 #define PCI_CB_IOLIMIT0 0x30 68 #define PCI_CB_IOBASE1 0x34 69 #define PCI_CB_IOLIMIT1 0x38 70 71 /* PCI_CB_LSCP_REG */ 72 #define PCI_CB_LATENCY_SHIFT 24 73 #define PCI_CB_LATENCY_MASK 0xff 74 #define PCI_CB_LATENCY(x) (((x) >> PCI_CB_LATENCY_SHIFT) & PCI_CB_LATENCY_MASK) 75 76 77 78 /* PCI_BCR_INTR bits for generic PCI-CardBus bridge */ 79 #define CB_BCR_RESET_ENABLE 0x00400000 80 #define CB_BCR_INTR_IREQ_ENABLE 0x00800000 81 #define CB_BCR_PREFETCH_MEMWIN0 0x01000000 82 #define CB_BCR_PREFETCH_MEMWIN1 0x02000000 83 #define CB_BCR_WRITE_POST_ENABLE 0x04000000 84 85 /* TI [14][245]xx */ 86 #define PCI12XX_MMCTRL 0x84 87 88 /* TI 12xx/14xx/15xx (except 1250, 1251, 1251B/1450) */ 89 #define PCI12XX_MFUNC 0x8c 90 #define PCI12XX_MFUNC_PIN0 0x0000000f 91 #define PCI12XX_MFUNC_PIN0_INTA 0x02 92 #define PCI12XX_MFUNC_PIN1 0x000000f0 93 #define PCI12XX_MFUNC_PIN1_INTB 0x20 94 #define PCI12XX_MFUNC_PIN2 0x00000f00 95 #define PCI12XX_MFUNC_PIN3 0x0000f000 96 #define PCI12XX_MFUNC_PIN4 0x000f0000 97 #define PCI12XX_MFUNC_PIN5 0x00f00000 98 #define PCI12XX_MFUNC_PIN6 0x0f000000 99 100 /* PCI_CBCTRL bits for TI PCI113X */ 101 #define PCI113X_CBCTRL_INT_SERIAL 0x040000 102 #define PCI113X_CBCTRL_INT_ISA 0x020000 103 #define PCI113X_CBCTRL_INT_MASK 0x060000 104 #define PCI113X_CBCTRL_RIENB 0x8000 /* Ring indicate output enable */ 105 #define PCI113X_CBCTRL_ZVENAB 0x4000 /* ZV mode enable */ 106 #define PCI113X_CBCTRL_PCI_IRQ_ENA 0x2000 /* PCI intr enable (funct and CSC) */ 107 #define PCI113X_CBCTRL_PCI_INTR 0x1000 /* PCI functional intr req */ 108 #define PCI113X_CBCTRL_PCI_CSC 0x0800 /* CSC intr route to PCI */ 109 #define PCI113X_CBCTRL_PCI_CSC_D 0x0400 /* unknown */ 110 #define PCI113X_CBCTRL_SPK_ENA 0x0200 /* Speaker enable */ 111 #define PCI113X_CBCTRL_INTR_DET 0x0100 /* functional interrupt detect */ 112 113 /* PCI_CBCTRL bits for TI PCI12XX */ 114 #define PCI12XX_SYSCTRL_INTRTIE 0x20000000u 115 #define PCI12XX_SYSCTRL_VCCPROT 0x200000 116 #define PCI12XX_SYSCTRL_PWRSAVE 0x000040 117 #define PCI12XX_SYSCTRL_SUBSYSRW 0x000020 118 #define PCI12XX_SYSCTRL_CB_DPAR 0x000010 119 #define PCI12XX_SYSCTRL_CDMA_EN 0x000008 120 #define PCI12XX_SYSCTRL_KEEPCLK 0x000002 121 #define PCI12XX_SYSCTRL_RIMUX 0x000001 122 #define PCI12XX_CBCTRL_CSC 0x20000000u 123 #define PCI12XX_CBCTRL_ASYNC_CSC 0x01000000u 124 #define PCI12XX_CBCTRL_INT_SERIAL 0x060000 125 #define PCI12XX_CBCTRL_INT_PCI_SERIAL 0x040000 126 #define PCI12XX_CBCTRL_INT_ISA 0x020000 127 #define PCI12XX_CBCTRL_INT_PCI 0x000000 128 #define PCI12XX_CBCTRL_INT_MASK 0x060000 129 #define PCI12XX_CBCTRL_RIENB 0x8000 /* Ring indicate output enable */ 130 #define PCI12XX_CBCTRL_ZVENAB 0x4000 /* ZV mode enable */ 131 #define PCI12XX_CBCTRL_AUD2MUX 0x0400 /* unknown */ 132 #define PCI12XX_CBCTRL_SPK_ENA 0x0200 /* Speaker enable */ 133 #define PCI12XX_CBCTRL_INTR_DET 0x0100 /* functional interrupt detect */ 134 135 136 /* PCI_BCR_INTR additional bit for Rx5C46[567] */ 137 #define CB_BCRI_RL_3E0_ENA 0x08000000 138 #define CB_BCRI_RL_3E2_ENA 0x10000000 139 140 141 /* PCI configuration register definition for Ricoh 5C475 */ 142 #define RICOH_PCI_MISC_CTRL 0x82 143 144 145 /* 146 * Special resister definition for Toshiba ToPIC95/97 147 * These values are borrowed from pcmcia-cs/Linux. 148 */ 149 #define TOPIC_SOCKET_CTRL 0x90 150 # define TOPIC_SOCKET_CTRL_SCR_IRQSEL 0x00000001 /* PCI intr */ 151 152 #define TOPIC_SLOT_CTRL 0xa0 153 # define TOPIC_SLOT_CTRL_SLOTON 0x00000080 154 # define TOPIC_SLOT_CTRL_SLOTEN 0x00000040 155 # define TOPIC_SLOT_CTRL_ID_LOCK 0x00000020 156 # define TOPIC_SLOT_CTRL_ID_WP 0x00000010 157 # define TOPIC_SLOT_CTRL_PORT_MASK 0x0000000c 158 # define TOPIC_SLOT_CTRL_PORT_SHIFT 2 159 # define TOPIC_SLOT_CTRL_OSF_MASK 0x00000003 160 # define TOPIC_SLOT_CTRL_OSF_SHIFT 0 161 162 # define TOPIC_SLOT_CTRL_INTB 0x00002000 163 # define TOPIC_SLOT_CTRL_INTA 0x00001000 164 # define TOPIC_SLOT_CTRL_INT_MASK 0x00003000 165 # define TOPIC_SLOT_CTRL_CLOCK_MASK 0x00000c00 166 # define TOPIC_SLOT_CTRL_CLOCK_2 0x00000800 /* PCI Clock/2 */ 167 # define TOPIC_SLOT_CTRL_CLOCK_1 0x00000400 /* PCI Clock */ 168 # define TOPIC_SLOT_CTRL_CLOCK_0 0x00000000 /* no clock */ 169 # define TOPIC97_SLOT_CTRL_STSIRQP 0x00000400 /* status change intr pulse */ 170 # define TOPIC97_SLOT_CTRL_IRQP 0x00000200 /* function intr pulse */ 171 # define TOPIC97_SLOT_CTRL_PCIINT 0x00000100 /* intr routing to PCI INT */ 172 173 # define TOPIC_SLOT_CTRL_CARDBUS 0x80000000 174 # define TOPIC_SLOT_CTRL_VS1 0x04000000 175 # define TOPIC_SLOT_CTRL_VS2 0x02000000 176 # define TOPIC_SLOT_CTRL_SWDETECT 0x01000000 177 178 #define TOPIC_REG_CTRL 0x00a4 179 # define TOPIC_REG_CTRL_RESUME_RESET 0x80000000 180 # define TOPIC_REG_CTRL_REMOVE_RESET 0x40000000 181 # define TOPIC97_REG_CTRL_CLKRUN_ENA 0x20000000 182 # define TOPIC97_REG_CTRL_TESTMODE 0x10000000 183 # define TOPIC97_REG_CTRL_IOPLUP 0x08000000 184 # define TOPIC_REG_CTRL_BUFOFF_PWROFF 0x02000000 185 # define TOPIC_REG_CTRL_BUFOFF_SIGOFF 0x01000000 186 # define TOPIC97_REG_CTRL_CB_DEV_MASK 0x0000f800 187 # define TOPIC97_REG_CTRL_CB_DEV_SHIFT 11 188 # define TOPIC97_REG_CTRL_RI_DISABLE 0x00000004 189 # define TOPIC97_REG_CTRL_CAUDIO_OFF 0x00000002 190 # define TOPIC_REG_CTRL_CAUDIO_INVERT 0x00000001 191 192 193 194 /* socket event register (CB_SOCKET_EVENT) elements */ 195 #define CB_SOCKET_EVENT_CSTS 0x01 /* CARDSTS event occurs */ 196 #define CB_SOCKET_EVENT_CD 0x06 /* CD event occurs */ 197 #define CB_SOCKET_EVENT_CD1 0x02 /* CD1 event occurs */ 198 #define CB_SOCKET_EVENT_CD2 0x04 /* CD2 event occurs */ 199 #define CB_SOCKET_EVENT_POWER 0x08 /* Power cycle event occurs */ 200 201 202 /* socket mask register (CB_SOCKET_MASK) elements */ 203 #define CB_SOCKET_MASK_CSTS 0x01 /* CARDSTS event mask */ 204 #define CB_SOCKET_MASK_CD 0x06 /* CD event mask */ 205 #define CB_SOCKET_MASK_POWER 0x08 /* Power cycle event mask */ 206 207 /* socket present-state register (CB_SOCKET_STAT) elements */ 208 #define CB_SOCKET_STAT_CARDSTS 0x01 /* card status change bit */ 209 #define CB_SOCKET_STAT_CD1 0x02 /* card detect 1 */ 210 #define CB_SOCKET_STAT_CD2 0x04 /* card detect 2 */ 211 #define CB_SOCKET_STAT_CD 0x06 /* card detect 1 and 2 */ 212 #define CB_SOCKET_STAT_PWRCYCLE 0x08 /* power cycle */ 213 #define CB_SOCKET_STAT_16BIT 0x010 /* 16-bit card */ 214 #define CB_SOCKET_STAT_CB 0x020 /* cardbus card */ 215 #define CB_SOCKET_STAT_IREQ 0x040 /* READY(~IREQ)//(~CINT) bit */ 216 #define CB_SOCKET_STAT_NOTCARD 0x080 /* Inserted card is unrecognisable */ 217 #define CB_SOCKET_STAT_DATALOST 0x0100 /* data lost */ 218 #define CB_SOCKET_STAT_BADVCC 0x0200 /* Bad Vcc Request */ 219 #define CB_SOCKET_STAT_5VCARD 0x0400 /* 5 V Card */ 220 #define CB_SOCKET_STAT_3VCARD 0x0800 /* 3.3 V Card */ 221 #define CB_SOCKET_STAT_XVCARD 0x01000 /* X.X V Card */ 222 #define CB_SOCKET_STAT_YVCARD 0x02000 /* Y.Y V Card */ 223 #define CB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */ 224 #define CB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */ 225 #define CB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */ 226 #define CB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */ 227 228 /* socket force event register (CB_SOCKET_FORCE) elements */ 229 #define CB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */ 230 231 232 /* socket control register (CB_SOCKET_CTRL) elements */ 233 #define CB_SOCKET_CTRL_VPPMASK 0x07 234 #define CB_SOCKET_CTRL_VPP_OFF 0x00 235 #define CB_SOCKET_CTRL_VPP_12V 0x01 236 #define CB_SOCKET_CTRL_VPP_5V 0x02 237 #define CB_SOCKET_CTRL_VPP_3V 0x03 238 #define CB_SOCKET_CTRL_VPP_XV 0x04 239 #define CB_SOCKET_CTRL_VPP_YV 0x05 240 241 #define CB_SOCKET_CTRL_VCCMASK 0x070 242 #define CB_SOCKET_CTRL_VCC_OFF 0x000 243 #define CB_SOCKET_CTRL_VCC_5V 0x020 244 #define CB_SOCKET_CTRL_VCC_3V 0x030 245 #define CB_SOCKET_CTRL_VCC_XV 0x040 246 #define CB_SOCKET_CTRL_VCC_YV 0x050 247 248 #define CB_SOCKET_CTRL_STOPCLK 0x080 249 250 251 252 /* PCCARD VOLTAGE */ 253 #define PCCARD_VCC_UKN 0x00 /* unknown */ 254 #define PCCARD_VCC_5V 0x01 255 #define PCCARD_VCC_3V 0x02 256 #define PCCARD_VCC_XV 0x04 257 #define PCCARD_VCC_YV 0x08 258 259 260 #endif /* _DEV_PCI_PCCBBREG_H_ */ 261
Indexes created Sun Sep 28 16:09:52 GMT 2025