pci.c revision 1.103.22.10
1 /* $NetBSD: pci.c,v 1.103.22.10 2007/12/01 04:31:37 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.103.22.10 2007/12/01 04:31:37 jmcneill Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 56 #include "locators.h" 57 58 static bool pci_child_register(device_t); 59 60 #ifdef PCI_CONFIG_DUMP 61 int pci_config_dump = 1; 62 #else 63 int pci_config_dump = 0; 64 #endif 65 66 int pciprint(void *, const char *); 67 68 #ifdef PCI_MACHDEP_ENUMERATE_BUS 69 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 70 #else 71 int pci_enumerate_bus(struct pci_softc *, const int *, 72 int (*)(struct pci_attach_args *), struct pci_attach_args *); 73 #endif 74 75 /* 76 * Important note about PCI-ISA bridges: 77 * 78 * Callbacks are used to configure these devices so that ISA/EISA bridges 79 * can attach their child busses after PCI configuration is done. 80 * 81 * This works because: 82 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 83 * (2) any ISA/EISA bridges must be attached to primary PCI 84 * busses (i.e. bus zero). 85 * 86 * That boils down to: there can only be one of these outstanding 87 * at a time, it is cleared when configuring PCI bus 0 before any 88 * subdevices have been found, and it is run after all subdevices 89 * of PCI bus 0 have been found. 90 * 91 * This is needed because there are some (legacy) PCI devices which 92 * can show up as ISA/EISA devices as well (the prime example of which 93 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 94 * and the bridge is seen before the video board is, the board can show 95 * up as an ISA device, and that can (bogusly) complicate the PCI device's 96 * attach code, or make the PCI device not be properly attached at all. 97 * 98 * We use the generic config_defer() facility to achieve this. 99 */ 100 101 static int 102 pcirescan(struct device *sc, const char *ifattr, const int *locators) 103 { 104 105 KASSERT(ifattr && !strcmp(ifattr, "pci")); 106 KASSERT(locators); 107 108 pci_enumerate_bus((struct pci_softc *)sc, locators, NULL, NULL); 109 return (0); 110 } 111 112 static int 113 pcimatch(struct device *parent, struct cfdata *cf, void *aux) 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 /* Check the locators */ 118 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 119 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 120 return (0); 121 122 /* sanity */ 123 if (pba->pba_bus < 0 || pba->pba_bus > 255) 124 return (0); 125 126 /* 127 * XXX check other (hardware?) indicators 128 */ 129 130 return (1); 131 } 132 133 static void 134 pciattach(struct device *parent, struct device *self, void *aux) 135 { 136 struct pcibus_attach_args *pba = aux; 137 struct pci_softc *sc = (struct pci_softc *)self; 138 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 139 const char *sep = ""; 140 static const int wildcard[PCICF_NLOCS] = { 141 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 142 }; 143 144 pci_attach_hook(parent, self, pba); 145 146 aprint_naive("\n"); 147 aprint_normal("\n"); 148 149 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 150 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 151 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 152 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 153 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 154 155 if (io_enabled == 0 && mem_enabled == 0) { 156 aprint_error("%s: no spaces enabled!\n", self->dv_xname); 157 return; 158 } 159 160 #define PRINT(str) \ 161 do { \ 162 aprint_normal("%s%s", sep, str); \ 163 sep = ", "; \ 164 } while (/*CONSTCOND*/0) 165 166 aprint_normal("%s: ", self->dv_xname); 167 168 if (io_enabled) 169 PRINT("i/o space"); 170 if (mem_enabled) 171 PRINT("memory space"); 172 aprint_normal(" enabled"); 173 174 if (mrl_enabled || mrm_enabled || mwi_enabled) { 175 if (mrl_enabled) 176 PRINT("rd/line"); 177 if (mrm_enabled) 178 PRINT("rd/mult"); 179 if (mwi_enabled) 180 PRINT("wr/inv"); 181 aprint_normal(" ok"); 182 } 183 184 aprint_normal("\n"); 185 186 #undef PRINT 187 188 sc->sc_iot = pba->pba_iot; 189 sc->sc_memt = pba->pba_memt; 190 sc->sc_dmat = pba->pba_dmat; 191 sc->sc_dmat64 = pba->pba_dmat64; 192 sc->sc_pc = pba->pba_pc; 193 sc->sc_bus = pba->pba_bus; 194 sc->sc_bridgetag = pba->pba_bridgetag; 195 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 196 sc->sc_intrswiz = pba->pba_intrswiz; 197 sc->sc_intrtag = pba->pba_intrtag; 198 sc->sc_flags = pba->pba_flags; 199 200 device_pnp_driver_set_child_register(&sc->sc_dev, pci_child_register); 201 202 pcirescan(&sc->sc_dev, "pci", wildcard); 203 204 if (!pnp_device_register(self, NULL, NULL)) 205 aprint_error_dev(self, "couldn't establish power handler\n"); 206 } 207 208 static int 209 pcidetach(struct device *self, int flags) 210 { 211 pnp_device_deregister(self); 212 return 0; 213 } 214 215 int 216 pciprint(void *aux, const char *pnp) 217 { 218 struct pci_attach_args *pa = aux; 219 char devinfo[256]; 220 const struct pci_quirkdata *qd; 221 222 if (pnp) { 223 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 224 aprint_normal("%s at %s", devinfo, pnp); 225 } 226 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 227 if (pci_config_dump) { 228 printf(": "); 229 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 230 if (!pnp) 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 printf("%s at %s", devinfo, pnp ? pnp : "?"); 233 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 234 #ifdef __i386__ 235 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 236 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 237 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 238 #else 239 printf("intrswiz %#lx, intrpin %#lx", 240 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 241 #endif 242 printf(", i/o %s, mem %s,", 243 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 244 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 245 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 246 PCI_PRODUCT(pa->pa_id)); 247 if (qd == NULL) { 248 printf(" no quirks"); 249 } else { 250 bitmask_snprintf(qd->quirks, 251 "\002\001multifn\002singlefn\003skipfunc0" 252 "\004skipfunc1\005skipfunc2\006skipfunc3" 253 "\007skipfunc4\010skipfunc5\011skipfunc6" 254 "\012skipfunc7", 255 devinfo, sizeof (devinfo)); 256 printf(" quirks %s", devinfo); 257 } 258 printf(")"); 259 } 260 return (UNCONF); 261 } 262 263 int 264 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 265 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 266 { 267 pci_chipset_tag_t pc = sc->sc_pc; 268 struct pci_attach_args pa; 269 pcireg_t id, csr, class, intr, bhlcr; 270 int ret, pin, bus, device, function; 271 int locs[PCICF_NLOCS]; 272 struct device *subdev; 273 274 pci_decompose_tag(pc, tag, &bus, &device, &function); 275 276 /* a driver already attached? */ 277 if (sc->PCI_SC_DEVICESC(device, function) && !match) 278 return (0); 279 280 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 281 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 282 return (0); 283 284 id = pci_conf_read(pc, tag, PCI_ID_REG); 285 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 286 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 287 288 /* Invalid vendor ID value? */ 289 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 290 return (0); 291 /* XXX Not invalid, but we've done this ~forever. */ 292 if (PCI_VENDOR(id) == 0) 293 return (0); 294 295 pa.pa_iot = sc->sc_iot; 296 pa.pa_memt = sc->sc_memt; 297 pa.pa_dmat = sc->sc_dmat; 298 pa.pa_dmat64 = sc->sc_dmat64; 299 pa.pa_pc = pc; 300 pa.pa_bus = bus; 301 pa.pa_device = device; 302 pa.pa_function = function; 303 pa.pa_tag = tag; 304 pa.pa_id = id; 305 pa.pa_class = class; 306 307 /* 308 * Set up memory, I/O enable, and PCI command flags 309 * as appropriate. 310 */ 311 pa.pa_flags = sc->sc_flags; 312 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 313 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 314 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 315 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 316 317 /* 318 * If the cache line size is not configured, then 319 * clear the MRL/MRM/MWI command-ok flags. 320 */ 321 if (PCI_CACHELINE(bhlcr) == 0) 322 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 323 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 324 325 if (sc->sc_bridgetag == NULL) { 326 pa.pa_intrswiz = 0; 327 pa.pa_intrtag = tag; 328 } else { 329 pa.pa_intrswiz = sc->sc_intrswiz + device; 330 pa.pa_intrtag = sc->sc_intrtag; 331 } 332 333 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 334 335 pin = PCI_INTERRUPT_PIN(intr); 336 pa.pa_rawintrpin = pin; 337 if (pin == PCI_INTERRUPT_PIN_NONE) { 338 /* no interrupt */ 339 pa.pa_intrpin = 0; 340 } else { 341 /* 342 * swizzle it based on the number of busses we're 343 * behind and our device number. 344 */ 345 pa.pa_intrpin = /* XXX */ 346 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 347 } 348 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 349 350 if (match != NULL) { 351 ret = (*match)(&pa); 352 if (ret != 0 && pap != NULL) 353 *pap = pa; 354 } else { 355 locs[PCICF_DEV] = device; 356 locs[PCICF_FUNCTION] = function; 357 358 subdev = config_found_sm_loc(&sc->sc_dev, "pci", locs, &pa, 359 pciprint, config_stdsubmatch); 360 sc->PCI_SC_DEVICESC(device, function) = subdev; 361 ret = (subdev != NULL); 362 } 363 364 return (ret); 365 } 366 367 static void 368 pcidevdetached(struct device *sc, struct device *dev) 369 { 370 struct pci_softc *psc = (struct pci_softc *)sc; 371 int d, f; 372 373 d = device_locator(dev, PCICF_DEV); 374 f = device_locator(dev, PCICF_FUNCTION); 375 376 KASSERT(psc->PCI_SC_DEVICESC(d, f) == dev); 377 378 psc->PCI_SC_DEVICESC(d, f) = 0; 379 } 380 381 CFATTACH_DECL2(pci, sizeof(struct pci_softc), 382 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached); 383 384 int 385 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 386 int *offset, pcireg_t *value) 387 { 388 pcireg_t reg; 389 unsigned int ofs; 390 391 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 392 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 393 return (0); 394 395 /* Determine the Capability List Pointer register to start with. */ 396 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 397 switch (PCI_HDRTYPE_TYPE(reg)) { 398 case 0: /* standard device header */ 399 case 1: /* PCI-PCI bridge header */ 400 ofs = PCI_CAPLISTPTR_REG; 401 break; 402 case 2: /* PCI-CardBus Bridge header */ 403 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 404 break; 405 default: 406 return (0); 407 } 408 409 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 410 while (ofs != 0) { 411 #ifdef DIAGNOSTIC 412 if ((ofs & 3) || (ofs < 0x40)) 413 panic("pci_get_capability"); 414 #endif 415 reg = pci_conf_read(pc, tag, ofs); 416 if (PCI_CAPLIST_CAP(reg) == capid) { 417 if (offset) 418 *offset = ofs; 419 if (value) 420 *value = reg; 421 return (1); 422 } 423 ofs = PCI_CAPLIST_NEXT(reg); 424 } 425 426 return (0); 427 } 428 429 int 430 pci_find_device(struct pci_attach_args *pa, 431 int (*match)(struct pci_attach_args *)) 432 { 433 extern struct cfdriver pci_cd; 434 struct device *pcidev; 435 int i; 436 static const int wildcard[2] = { 437 PCICF_DEV_DEFAULT, 438 PCICF_FUNCTION_DEFAULT 439 }; 440 441 for (i = 0; i < pci_cd.cd_ndevs; i++) { 442 pcidev = pci_cd.cd_devs[i]; 443 if (pcidev != NULL && 444 pci_enumerate_bus((struct pci_softc *)pcidev, wildcard, 445 match, pa) != 0) 446 return (1); 447 } 448 return (0); 449 } 450 451 #ifndef PCI_MACHDEP_ENUMERATE_BUS 452 /* 453 * Generic PCI bus enumeration routine. Used unless machine-dependent 454 * code needs to provide something else. 455 */ 456 int 457 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 458 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 459 { 460 pci_chipset_tag_t pc = sc->sc_pc; 461 int device, function, nfunctions, ret; 462 const struct pci_quirkdata *qd; 463 pcireg_t id, bhlcr; 464 pcitag_t tag; 465 #ifdef __PCI_BUS_DEVORDER 466 char devs[32]; 467 int i; 468 #endif 469 470 #ifdef __PCI_BUS_DEVORDER 471 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 472 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 473 #else 474 for (device = 0; device < sc->sc_maxndevs; device++) 475 #endif 476 { 477 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 478 (locators[PCICF_DEV] != device)) 479 continue; 480 481 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 482 483 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 484 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 485 continue; 486 487 id = pci_conf_read(pc, tag, PCI_ID_REG); 488 489 /* Invalid vendor ID value? */ 490 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 491 continue; 492 /* XXX Not invalid, but we've done this ~forever. */ 493 if (PCI_VENDOR(id) == 0) 494 continue; 495 496 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 497 498 if (qd != NULL && 499 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 500 nfunctions = 8; 501 else if (qd != NULL && 502 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 503 nfunctions = 1; 504 else 505 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 506 507 for (function = 0; function < nfunctions; function++) { 508 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 509 && (locators[PCICF_FUNCTION] != function)) 510 continue; 511 512 if (qd != NULL && 513 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 514 continue; 515 tag = pci_make_tag(pc, sc->sc_bus, device, function); 516 ret = pci_probe_device(sc, tag, match, pap); 517 if (match != NULL && ret != 0) 518 return (ret); 519 } 520 } 521 return (0); 522 } 523 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 524 525 526 /* 527 * Vital Product Data (PCI 2.2) 528 */ 529 530 int 531 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 532 pcireg_t *data) 533 { 534 uint32_t reg; 535 int ofs, i, j; 536 537 KASSERT(data != NULL); 538 KASSERT((offset + count) < 0x7fff); 539 540 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 541 return (1); 542 543 for (i = 0; i < count; offset += sizeof(*data), i++) { 544 reg &= 0x0000ffff; 545 reg &= ~PCI_VPD_OPFLAG; 546 reg |= PCI_VPD_ADDRESS(offset); 547 pci_conf_write(pc, tag, ofs, reg); 548 549 /* 550 * PCI 2.2 does not specify how long we should poll 551 * for completion nor whether the operation can fail. 552 */ 553 j = 0; 554 do { 555 if (j++ == 20) 556 return (1); 557 delay(4); 558 reg = pci_conf_read(pc, tag, ofs); 559 } while ((reg & PCI_VPD_OPFLAG) == 0); 560 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 561 } 562 563 return (0); 564 } 565 566 int 567 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 568 pcireg_t *data) 569 { 570 pcireg_t reg; 571 int ofs, i, j; 572 573 KASSERT(data != NULL); 574 KASSERT((offset + count) < 0x7fff); 575 576 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 577 return (1); 578 579 for (i = 0; i < count; offset += sizeof(*data), i++) { 580 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 581 582 reg &= 0x0000ffff; 583 reg |= PCI_VPD_OPFLAG; 584 reg |= PCI_VPD_ADDRESS(offset); 585 pci_conf_write(pc, tag, ofs, reg); 586 587 /* 588 * PCI 2.2 does not specify how long we should poll 589 * for completion nor whether the operation can fail. 590 */ 591 j = 0; 592 do { 593 if (j++ == 20) 594 return (1); 595 delay(1); 596 reg = pci_conf_read(pc, tag, ofs); 597 } while (reg & PCI_VPD_OPFLAG); 598 } 599 600 return (0); 601 } 602 603 int 604 pci_dma64_available(struct pci_attach_args *pa) 605 { 606 #ifdef _PCI_HAVE_DMA64 607 if (BUS_DMA_TAG_VALID(pa->pa_dmat64) && 608 ((uint64_t)physmem << PAGE_SHIFT) > 0xffffffffULL) 609 return 1; 610 #endif 611 return 0; 612 } 613 614 void 615 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 616 struct pci_conf_state *pcs) 617 { 618 int off; 619 620 for (off = 0; off < 16; off++) 621 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 622 623 return; 624 } 625 626 void 627 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 628 struct pci_conf_state *pcs) 629 { 630 int off; 631 pcireg_t val; 632 633 for (off = 15; off >= 0; off--) { 634 val = pci_conf_read(pc, tag, (off * 4)); 635 if (val != pcs->reg[off]) 636 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 637 } 638 639 return; 640 } 641 642 /* 643 * Power Management Capability (Rev 2.2) 644 */ 645 static int 646 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 647 int offset) 648 { 649 pcireg_t value, now; 650 651 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 652 now = value & PCI_PMCSR_STATE_MASK; 653 switch (now) { 654 case PCI_PMCSR_STATE_D0: 655 case PCI_PMCSR_STATE_D1: 656 case PCI_PMCSR_STATE_D2: 657 case PCI_PMCSR_STATE_D3: 658 *state = now; 659 return 0; 660 default: 661 return EINVAL; 662 } 663 } 664 665 int 666 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 667 { 668 int offset; 669 pcireg_t value; 670 671 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 672 return EOPNOTSUPP; 673 674 return pci_get_powerstate_int(pc, tag, state, offset); 675 } 676 677 static int 678 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 679 int offset, pcireg_t cap_reg) 680 { 681 pcireg_t value, cap, now; 682 683 cap = cap_reg >> PCI_PMCR_SHIFT; 684 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 685 now = value & PCI_PMCSR_STATE_MASK; 686 value &= ~PCI_PMCSR_STATE_MASK; 687 688 if (now == state) 689 return 0; 690 switch (state) { 691 case PCI_PMCSR_STATE_D0: 692 value |= PCI_PMCSR_STATE_D0; 693 break; 694 case PCI_PMCSR_STATE_D1: 695 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 696 printf("invalid transition from %d to D1\n", (int)now); 697 return EINVAL; 698 } 699 if (!(cap & PCI_PMCR_D1SUPP)) { 700 printf("D1 not supported\n"); 701 return EOPNOTSUPP; 702 } 703 value |= PCI_PMCSR_STATE_D1; 704 break; 705 case PCI_PMCSR_STATE_D2: 706 if (now == PCI_PMCSR_STATE_D3) { 707 printf("invalid transition from %d to D2\n", (int)now); 708 return EINVAL; 709 } 710 if (!(cap & PCI_PMCR_D2SUPP)) { 711 printf("D2 not supported\n"); 712 return EOPNOTSUPP; 713 } 714 value |= PCI_PMCSR_STATE_D2; 715 break; 716 case PCI_PMCSR_STATE_D3: 717 value |= PCI_PMCSR_STATE_D3; 718 break; 719 default: 720 return EINVAL; 721 } 722 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 723 DELAY(1000); 724 return 0; 725 } 726 727 int 728 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 729 { 730 int offset; 731 pcireg_t value; 732 733 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 734 printf("pci_set_powerstate not supported\n"); 735 return EOPNOTSUPP; 736 } 737 738 return pci_set_powerstate_int(pc, tag, state, offset, value); 739 } 740 741 int 742 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, void *sc, 743 int (*wakefun)(pci_chipset_tag_t, pcitag_t, void *, pcireg_t)) 744 { 745 struct device *dv = sc; 746 pcireg_t pmode; 747 int error; 748 749 if ((error = pci_get_powerstate(pc, tag, &pmode))) 750 return error; 751 752 switch (pmode) { 753 case PCI_PMCSR_STATE_D0: 754 break; 755 case PCI_PMCSR_STATE_D3: 756 if (wakefun == NULL) { 757 /* 758 * The card has lost all configuration data in 759 * this state, so punt. 760 */ 761 aprint_error( 762 "%s: unable to wake up from power state D3\n", 763 dv->dv_xname); 764 return EOPNOTSUPP; 765 } 766 /*FALLTHROUGH*/ 767 default: 768 if (wakefun) { 769 error = (*wakefun)(pc, tag, sc, pmode); 770 if (error) 771 return error; 772 } 773 aprint_normal("%s: waking up from power state D%d\n", 774 dv->dv_xname, pmode); 775 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 776 return error; 777 } 778 return 0; 779 } 780 781 int 782 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 783 void *sc, pcireg_t state) 784 { 785 return 0; 786 } 787 788 void 789 pci_disable_retry(pci_chipset_tag_t pc, pcitag_t tag) 790 { 791 pcireg_t retry; 792 793 /* 794 * Disable retry timeout to keep PCI Tx retries from 795 * interfering with ACPI C3 CPU state. 796 */ 797 retry = pci_conf_read(pc, tag, PCI_RETRY_TIMEOUT_REG); 798 retry &= ~PCI_RETRY_TIMEOUT_REG_MASK; 799 pci_conf_write(pc, tag, PCI_RETRY_TIMEOUT_REG, retry); 800 } 801 802 struct pci_child_power { 803 struct pci_conf_state p_pciconf; 804 pci_chipset_tag_t p_pc; 805 pcitag_t p_tag; 806 bool p_has_pm; 807 int p_pm_offset; 808 pcireg_t p_pm_cap; 809 pcireg_t p_class; 810 }; 811 812 static bool 813 pci_child_suspend(device_t dv) 814 { 815 struct pci_child_power *priv = device_pnp_bus_private(dv); 816 817 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 818 819 if (priv->p_has_pm && 820 PCI_CLASS(priv->p_class) != PCI_CLASS_DISPLAY && 821 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 822 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 823 aprint_error_dev(dv, "unsupported state, continuing.\n"); 824 return false; 825 } 826 return true; 827 } 828 829 static bool 830 pci_child_resume(device_t dv) 831 { 832 struct pci_child_power *priv = device_pnp_bus_private(dv); 833 834 if (priv->p_has_pm && 835 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 836 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 837 aprint_error_dev(dv, "unsupported state, continuing.\n"); 838 return false; 839 } 840 841 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 842 843 return true; 844 } 845 846 static void 847 pci_child_deregister(device_t dv) 848 { 849 struct pci_child_power *priv = device_pnp_bus_private(dv); 850 851 free(priv, M_DEVBUF); 852 } 853 854 static bool 855 pci_child_register(device_t child) 856 { 857 device_t self = device_parent(child); 858 struct pci_softc *sc = device_private(self); 859 struct pci_child_power *priv; 860 int device, function, off; 861 pcireg_t reg; 862 863 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 864 865 device = device_locator(child, PCICF_DEV); 866 function = device_locator(child, PCICF_FUNCTION); 867 868 priv->p_pc = sc->sc_pc; 869 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 870 function); 871 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 872 873 if (pci_get_capability(priv->p_pc, priv->p_tag, 874 PCI_CAP_PWRMGMT, &off, ®)) { 875 priv->p_has_pm = true; 876 priv->p_pm_offset = off; 877 priv->p_pm_cap = reg; 878 } else { 879 priv->p_has_pm = false; 880 priv->p_pm_offset = -1; 881 } 882 883 device_pnp_bus_register(child, priv, pci_child_suspend, 884 pci_child_resume, pci_child_deregister); 885 886 return true; 887 } 888
Indexes created Tue Sep 30 20:09:53 GMT 2025