pci.c revision 1.103.22.6
1 /* $NetBSD: pci.c,v 1.103.22.6 2007/09/11 11:59:59 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.103.22.6 2007/09/11 11:59:59 jmcneill Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <net/if.h> 54 55 #include "locators.h" 56 57 #ifdef PCI_CONFIG_DUMP 58 int pci_config_dump = 1; 59 #else 60 int pci_config_dump = 0; 61 #endif 62 63 int pciprint(void *, const char *); 64 65 #ifdef PCI_MACHDEP_ENUMERATE_BUS 66 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 67 #else 68 int pci_enumerate_bus(struct pci_softc *, const int *, 69 int (*)(struct pci_attach_args *), struct pci_attach_args *); 70 #endif 71 72 /* 73 * Important note about PCI-ISA bridges: 74 * 75 * Callbacks are used to configure these devices so that ISA/EISA bridges 76 * can attach their child busses after PCI configuration is done. 77 * 78 * This works because: 79 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 80 * (2) any ISA/EISA bridges must be attached to primary PCI 81 * busses (i.e. bus zero). 82 * 83 * That boils down to: there can only be one of these outstanding 84 * at a time, it is cleared when configuring PCI bus 0 before any 85 * subdevices have been found, and it is run after all subdevices 86 * of PCI bus 0 have been found. 87 * 88 * This is needed because there are some (legacy) PCI devices which 89 * can show up as ISA/EISA devices as well (the prime example of which 90 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 91 * and the bridge is seen before the video board is, the board can show 92 * up as an ISA device, and that can (bogusly) complicate the PCI device's 93 * attach code, or make the PCI device not be properly attached at all. 94 * 95 * We use the generic config_defer() facility to achieve this. 96 */ 97 98 static int 99 pcirescan(struct device *sc, const char *ifattr, const int *locators) 100 { 101 102 KASSERT(ifattr && !strcmp(ifattr, "pci")); 103 KASSERT(locators); 104 105 pci_enumerate_bus((struct pci_softc *)sc, locators, NULL, NULL); 106 return (0); 107 } 108 109 static int 110 pcimatch(struct device *parent, struct cfdata *cf, void *aux) 111 { 112 struct pcibus_attach_args *pba = aux; 113 114 /* Check the locators */ 115 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 116 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 117 return (0); 118 119 /* sanity */ 120 if (pba->pba_bus < 0 || pba->pba_bus > 255) 121 return (0); 122 123 /* 124 * XXX check other (hardware?) indicators 125 */ 126 127 return (1); 128 } 129 130 static void 131 pci_power_devices(struct pci_softc *sc, pnp_state_t newstate) 132 { 133 pci_chipset_tag_t pc; 134 int device, function, nfunctions; 135 pcitag_t tag; 136 pcireg_t bhlcr, id; 137 pcireg_t state; 138 #ifdef __PCI_BUS_DEVORDER 139 char devs[32]; 140 int i; 141 #endif 142 143 pc = sc->sc_pc; 144 switch (newstate) { 145 case PNP_STATE_D1: 146 state = PCI_PMCSR_STATE_D1; 147 break; 148 case PNP_STATE_D3: 149 state = PCI_PMCSR_STATE_D3; 150 break; 151 case PNP_STATE_D0: 152 state = PCI_PMCSR_STATE_D0; 153 break; 154 default: 155 /* we should never be called here */ 156 #ifdef DIAGNOSTIC 157 panic("pci_power_devices called with invalid reason %d\n", 158 newstate); 159 /* NOTREACHED */ 160 #endif 161 return; 162 } 163 164 #ifdef __PCI_BUS_DEVORDER 165 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 166 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 167 #else 168 for (device = 0; device < sc->sc_maxndevs; device++) 169 #endif 170 { 171 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 172 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 173 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 174 continue; 175 id = pci_conf_read(pc, tag, PCI_ID_REG); 176 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID || 177 PCI_VENDOR(id) == 0x0000) 178 continue; 179 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 180 181 for (function = 0; function < nfunctions; function++) { 182 tag = pci_make_tag(pc, sc->sc_bus, device, function); 183 if (sc->PCI_SC_DEVICESC(device, function) != NULL) 184 continue; 185 (void)pci_set_powerstate(pc, tag, state); 186 } 187 } 188 189 return; 190 } 191 192 static pnp_status_t 193 pci_power(device_t dv, pnp_request_t req, void *opaque) 194 { 195 struct pci_softc *sc; 196 pnp_capabilities_t *pcaps; 197 pnp_state_t *pstate; 198 199 sc = (struct pci_softc *)dv; 200 201 switch (req) { 202 case PNP_REQUEST_GET_CAPABILITIES: 203 pcaps = opaque; 204 pcaps->state |= PNP_STATE_D0 | PNP_STATE_D3; 205 break; 206 207 case PNP_REQUEST_GET_STATE: 208 pstate = opaque; 209 *pstate = PNP_STATE_D0; /* XXX */ 210 break; 211 212 case PNP_REQUEST_SET_STATE: 213 pstate = opaque; 214 215 if (*pstate == PNP_STATE_D2) 216 return PNP_STATUS_UNSUPPORTED; 217 218 pci_power_devices(sc, req); 219 break; 220 221 case PNP_REQUEST_NOTIFY: 222 /* XXX TODO */ 223 break; 224 225 default: 226 return PNP_STATUS_UNSUPPORTED; 227 } 228 229 return PNP_STATUS_SUCCESS; 230 } 231 232 static void 233 pciattach(struct device *parent, struct device *self, void *aux) 234 { 235 struct pcibus_attach_args *pba = aux; 236 struct pci_softc *sc = (struct pci_softc *)self; 237 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 238 pnp_status_t status; 239 const char *sep = ""; 240 static const int wildcard[PCICF_NLOCS] = { 241 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 242 }; 243 244 pci_attach_hook(parent, self, pba); 245 246 aprint_naive("\n"); 247 aprint_normal("\n"); 248 249 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 250 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 251 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 252 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 253 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 254 255 if (io_enabled == 0 && mem_enabled == 0) { 256 aprint_error("%s: no spaces enabled!\n", self->dv_xname); 257 return; 258 } 259 260 #define PRINT(str) \ 261 do { \ 262 aprint_normal("%s%s", sep, str); \ 263 sep = ", "; \ 264 } while (/*CONSTCOND*/0) 265 266 aprint_normal("%s: ", self->dv_xname); 267 268 if (io_enabled) 269 PRINT("i/o space"); 270 if (mem_enabled) 271 PRINT("memory space"); 272 aprint_normal(" enabled"); 273 274 if (mrl_enabled || mrm_enabled || mwi_enabled) { 275 if (mrl_enabled) 276 PRINT("rd/line"); 277 if (mrm_enabled) 278 PRINT("rd/mult"); 279 if (mwi_enabled) 280 PRINT("wr/inv"); 281 aprint_normal(" ok"); 282 } 283 284 aprint_normal("\n"); 285 286 #undef PRINT 287 288 sc->sc_iot = pba->pba_iot; 289 sc->sc_memt = pba->pba_memt; 290 sc->sc_dmat = pba->pba_dmat; 291 sc->sc_dmat64 = pba->pba_dmat64; 292 sc->sc_pc = pba->pba_pc; 293 sc->sc_bus = pba->pba_bus; 294 sc->sc_bridgetag = pba->pba_bridgetag; 295 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 296 sc->sc_intrswiz = pba->pba_intrswiz; 297 sc->sc_intrtag = pba->pba_intrtag; 298 sc->sc_flags = pba->pba_flags; 299 300 status = pnp_register(self, pci_power); 301 if (status != PNP_STATUS_SUCCESS) 302 aprint_error("%s: couldn't establish power handler\n", 303 device_xname(self)); 304 305 pcirescan(&sc->sc_dev, "pci", wildcard); 306 } 307 308 int 309 pciprint(void *aux, const char *pnp) 310 { 311 struct pci_attach_args *pa = aux; 312 char devinfo[256]; 313 const struct pci_quirkdata *qd; 314 315 if (pnp) { 316 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 317 aprint_normal("%s at %s", devinfo, pnp); 318 } 319 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 320 if (pci_config_dump) { 321 printf(": "); 322 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 323 if (!pnp) 324 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 325 printf("%s at %s", devinfo, pnp ? pnp : "?"); 326 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 327 #ifdef __i386__ 328 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 329 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 330 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 331 #else 332 printf("intrswiz %#lx, intrpin %#lx", 333 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 334 #endif 335 printf(", i/o %s, mem %s,", 336 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 337 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 338 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 339 PCI_PRODUCT(pa->pa_id)); 340 if (qd == NULL) { 341 printf(" no quirks"); 342 } else { 343 bitmask_snprintf(qd->quirks, 344 "\002\001multifn\002singlefn\003skipfunc0" 345 "\004skipfunc1\005skipfunc2\006skipfunc3" 346 "\007skipfunc4\010skipfunc5\011skipfunc6" 347 "\012skipfunc7", 348 devinfo, sizeof (devinfo)); 349 printf(" quirks %s", devinfo); 350 } 351 printf(")"); 352 } 353 return (UNCONF); 354 } 355 356 int 357 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 358 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 359 { 360 pci_chipset_tag_t pc = sc->sc_pc; 361 struct pci_attach_args pa; 362 pcireg_t id, csr, class, intr, bhlcr; 363 int ret, pin, bus, device, function; 364 int locs[PCICF_NLOCS]; 365 struct device *subdev; 366 367 pci_decompose_tag(pc, tag, &bus, &device, &function); 368 369 /* a driver already attached? */ 370 if (sc->PCI_SC_DEVICESC(device, function) && !match) 371 return (0); 372 373 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 374 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 375 return (0); 376 377 id = pci_conf_read(pc, tag, PCI_ID_REG); 378 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 379 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 380 381 /* Invalid vendor ID value? */ 382 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 383 return (0); 384 /* XXX Not invalid, but we've done this ~forever. */ 385 if (PCI_VENDOR(id) == 0) 386 return (0); 387 388 pa.pa_iot = sc->sc_iot; 389 pa.pa_memt = sc->sc_memt; 390 pa.pa_dmat = sc->sc_dmat; 391 pa.pa_dmat64 = sc->sc_dmat64; 392 pa.pa_pc = pc; 393 pa.pa_bus = bus; 394 pa.pa_device = device; 395 pa.pa_function = function; 396 pa.pa_tag = tag; 397 pa.pa_id = id; 398 pa.pa_class = class; 399 400 /* 401 * Set up memory, I/O enable, and PCI command flags 402 * as appropriate. 403 */ 404 pa.pa_flags = sc->sc_flags; 405 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 406 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 407 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 408 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 409 410 /* 411 * If the cache line size is not configured, then 412 * clear the MRL/MRM/MWI command-ok flags. 413 */ 414 if (PCI_CACHELINE(bhlcr) == 0) 415 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 416 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 417 418 if (sc->sc_bridgetag == NULL) { 419 pa.pa_intrswiz = 0; 420 pa.pa_intrtag = tag; 421 } else { 422 pa.pa_intrswiz = sc->sc_intrswiz + device; 423 pa.pa_intrtag = sc->sc_intrtag; 424 } 425 426 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 427 428 pin = PCI_INTERRUPT_PIN(intr); 429 pa.pa_rawintrpin = pin; 430 if (pin == PCI_INTERRUPT_PIN_NONE) { 431 /* no interrupt */ 432 pa.pa_intrpin = 0; 433 } else { 434 /* 435 * swizzle it based on the number of busses we're 436 * behind and our device number. 437 */ 438 pa.pa_intrpin = /* XXX */ 439 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 440 } 441 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 442 443 if (match != NULL) { 444 ret = (*match)(&pa); 445 if (ret != 0 && pap != NULL) 446 *pap = pa; 447 } else { 448 locs[PCICF_DEV] = device; 449 locs[PCICF_FUNCTION] = function; 450 451 subdev = config_found_sm_loc(&sc->sc_dev, "pci", locs, &pa, 452 pciprint, config_stdsubmatch); 453 sc->PCI_SC_DEVICESC(device, function) = subdev; 454 ret = (subdev != NULL); 455 } 456 457 return (ret); 458 } 459 460 static void 461 pcidevdetached(struct device *sc, struct device *dev) 462 { 463 struct pci_softc *psc = (struct pci_softc *)sc; 464 int d, f; 465 466 d = device_locator(dev, PCICF_DEV); 467 f = device_locator(dev, PCICF_FUNCTION); 468 469 KASSERT(psc->PCI_SC_DEVICESC(d, f) == dev); 470 471 psc->PCI_SC_DEVICESC(d, f) = 0; 472 } 473 474 int 475 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 476 int *offset, pcireg_t *value) 477 { 478 pcireg_t reg; 479 unsigned int ofs; 480 481 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 482 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 483 return (0); 484 485 /* Determine the Capability List Pointer register to start with. */ 486 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 487 switch (PCI_HDRTYPE_TYPE(reg)) { 488 case 0: /* standard device header */ 489 case 1: /* PCI-PCI bridge header */ 490 ofs = PCI_CAPLISTPTR_REG; 491 break; 492 case 2: /* PCI-CardBus Bridge header */ 493 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 494 break; 495 default: 496 return (0); 497 } 498 499 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 500 while (ofs != 0) { 501 #ifdef DIAGNOSTIC 502 if ((ofs & 3) || (ofs < 0x40)) 503 panic("pci_get_capability"); 504 #endif 505 reg = pci_conf_read(pc, tag, ofs); 506 if (PCI_CAPLIST_CAP(reg) == capid) { 507 if (offset) 508 *offset = ofs; 509 if (value) 510 *value = reg; 511 return (1); 512 } 513 ofs = PCI_CAPLIST_NEXT(reg); 514 } 515 516 return (0); 517 } 518 519 int 520 pci_find_device(struct pci_attach_args *pa, 521 int (*match)(struct pci_attach_args *)) 522 { 523 extern struct cfdriver pci_cd; 524 struct device *pcidev; 525 int i; 526 static const int wildcard[2] = { 527 PCICF_DEV_DEFAULT, 528 PCICF_FUNCTION_DEFAULT 529 }; 530 531 for (i = 0; i < pci_cd.cd_ndevs; i++) { 532 pcidev = pci_cd.cd_devs[i]; 533 if (pcidev != NULL && 534 pci_enumerate_bus((struct pci_softc *)pcidev, wildcard, 535 match, pa) != 0) 536 return (1); 537 } 538 return (0); 539 } 540 541 #ifndef PCI_MACHDEP_ENUMERATE_BUS 542 /* 543 * Generic PCI bus enumeration routine. Used unless machine-dependent 544 * code needs to provide something else. 545 */ 546 int 547 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 548 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 549 { 550 pci_chipset_tag_t pc = sc->sc_pc; 551 int device, function, nfunctions, ret; 552 const struct pci_quirkdata *qd; 553 pcireg_t id, bhlcr; 554 pcitag_t tag; 555 #ifdef __PCI_BUS_DEVORDER 556 char devs[32]; 557 int i; 558 #endif 559 560 #ifdef __PCI_BUS_DEVORDER 561 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 562 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 563 #else 564 for (device = 0; device < sc->sc_maxndevs; device++) 565 #endif 566 { 567 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 568 (locators[PCICF_DEV] != device)) 569 continue; 570 571 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 572 573 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 574 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 575 continue; 576 577 id = pci_conf_read(pc, tag, PCI_ID_REG); 578 579 /* Invalid vendor ID value? */ 580 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 581 continue; 582 /* XXX Not invalid, but we've done this ~forever. */ 583 if (PCI_VENDOR(id) == 0) 584 continue; 585 586 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 587 588 if (qd != NULL && 589 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 590 nfunctions = 8; 591 else if (qd != NULL && 592 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 593 nfunctions = 1; 594 else 595 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 596 597 for (function = 0; function < nfunctions; function++) { 598 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 599 && (locators[PCICF_FUNCTION] != function)) 600 continue; 601 602 if (qd != NULL && 603 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 604 continue; 605 tag = pci_make_tag(pc, sc->sc_bus, device, function); 606 ret = pci_probe_device(sc, tag, match, pap); 607 if (match != NULL && ret != 0) 608 return (ret); 609 } 610 } 611 return (0); 612 } 613 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 614 615 616 /* 617 * Vital Product Data (PCI 2.2) 618 */ 619 620 int 621 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 622 pcireg_t *data) 623 { 624 uint32_t reg; 625 int ofs, i, j; 626 627 KASSERT(data != NULL); 628 KASSERT((offset + count) < 0x7fff); 629 630 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 631 return (1); 632 633 for (i = 0; i < count; offset += sizeof(*data), i++) { 634 reg &= 0x0000ffff; 635 reg &= ~PCI_VPD_OPFLAG; 636 reg |= PCI_VPD_ADDRESS(offset); 637 pci_conf_write(pc, tag, ofs, reg); 638 639 /* 640 * PCI 2.2 does not specify how long we should poll 641 * for completion nor whether the operation can fail. 642 */ 643 j = 0; 644 do { 645 if (j++ == 20) 646 return (1); 647 delay(4); 648 reg = pci_conf_read(pc, tag, ofs); 649 } while ((reg & PCI_VPD_OPFLAG) == 0); 650 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 651 } 652 653 return (0); 654 } 655 656 int 657 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 658 pcireg_t *data) 659 { 660 pcireg_t reg; 661 int ofs, i, j; 662 663 KASSERT(data != NULL); 664 KASSERT((offset + count) < 0x7fff); 665 666 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 667 return (1); 668 669 for (i = 0; i < count; offset += sizeof(*data), i++) { 670 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 671 672 reg &= 0x0000ffff; 673 reg |= PCI_VPD_OPFLAG; 674 reg |= PCI_VPD_ADDRESS(offset); 675 pci_conf_write(pc, tag, ofs, reg); 676 677 /* 678 * PCI 2.2 does not specify how long we should poll 679 * for completion nor whether the operation can fail. 680 */ 681 j = 0; 682 do { 683 if (j++ == 20) 684 return (1); 685 delay(1); 686 reg = pci_conf_read(pc, tag, ofs); 687 } while (reg & PCI_VPD_OPFLAG); 688 } 689 690 return (0); 691 } 692 693 int 694 pci_dma64_available(struct pci_attach_args *pa) 695 { 696 #ifdef _PCI_HAVE_DMA64 697 if (BUS_DMA_TAG_VALID(pa->pa_dmat64) && 698 ((uint64_t)physmem << PAGE_SHIFT) > 0xffffffffULL) 699 return 1; 700 #endif 701 return 0; 702 } 703 704 void 705 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 706 struct pci_conf_state *pcs) 707 { 708 int off; 709 710 for (off = 0; off < 16; off++) 711 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 712 713 return; 714 } 715 716 void 717 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 718 struct pci_conf_state *pcs) 719 { 720 int off; 721 pcireg_t val; 722 723 for (off = 15; off >= 0; off--) { 724 val = pci_conf_read(pc, tag, (off * 4)); 725 if (val != pcs->reg[off]) 726 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 727 } 728 729 return; 730 } 731 732 /* 733 * Power Management Capability (Rev 2.2) 734 */ 735 int 736 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 737 { 738 int offset; 739 pcireg_t value, cap, now; 740 741 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 742 return EOPNOTSUPP; 743 744 cap = value >> PCI_PMCR_SHIFT; 745 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 746 now = value & PCI_PMCSR_STATE_MASK; 747 switch (now) { 748 case PCI_PMCSR_STATE_D0: 749 case PCI_PMCSR_STATE_D1: 750 case PCI_PMCSR_STATE_D2: 751 case PCI_PMCSR_STATE_D3: 752 *state = now; 753 return 0; 754 default: 755 return EINVAL; 756 } 757 } 758 759 int 760 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 761 { 762 int offset; 763 pcireg_t value, cap, now; 764 765 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 766 return EOPNOTSUPP; 767 768 cap = value >> PCI_PMCR_SHIFT; 769 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 770 now = value & PCI_PMCSR_STATE_MASK; 771 value &= ~PCI_PMCSR_STATE_MASK; 772 773 if (now == state) 774 return 0; 775 switch (state) { 776 case PCI_PMCSR_STATE_D0: 777 value |= PCI_PMCSR_STATE_D0; 778 break; 779 case PCI_PMCSR_STATE_D1: 780 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) 781 return EINVAL; 782 if (!(cap & PCI_PMCR_D1SUPP)) 783 return EOPNOTSUPP; 784 value |= PCI_PMCSR_STATE_D1; 785 break; 786 case PCI_PMCSR_STATE_D2: 787 if (now == PCI_PMCSR_STATE_D3) 788 return EINVAL; 789 if (!(cap & PCI_PMCR_D2SUPP)) 790 return EOPNOTSUPP; 791 value |= PCI_PMCSR_STATE_D2; 792 break; 793 case PCI_PMCSR_STATE_D3: 794 if (now == PCI_PMCSR_STATE_D3) 795 return 0; 796 value |= PCI_PMCSR_STATE_D3; 797 break; 798 default: 799 return EINVAL; 800 } 801 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 802 DELAY(1000); 803 return 0; 804 } 805 806 pnp_state_t 807 pci_pnp_powerstate(pcireg_t reg) 808 { 809 pnp_state_t state; 810 811 switch (reg) { 812 case PCI_PMCSR_STATE_D0: 813 state = PNP_STATE_D0; 814 break; 815 case PCI_PMCSR_STATE_D1: 816 state = PNP_STATE_D1; 817 break; 818 case PCI_PMCSR_STATE_D2: 819 state = PNP_STATE_D2; 820 break; 821 case PCI_PMCSR_STATE_D3: 822 state = PNP_STATE_D3; 823 break; 824 default: 825 state = PNP_STATE_UNKNOWN; 826 break; 827 } 828 829 return state; 830 } 831 832 pnp_state_t 833 pci_pnp_capabilities(pcireg_t reg) 834 { 835 pnp_state_t state; 836 pcireg_t cap; 837 838 cap = reg >> PCI_PMCR_SHIFT; 839 840 state = PNP_STATE_D0 | PNP_STATE_D3; 841 if (cap & PCI_PMCR_D1SUPP) 842 state |= PNP_STATE_D1; 843 if (cap & PCI_PMCR_D2SUPP) 844 state |= PNP_STATE_D2; 845 846 return state; 847 } 848 849 int 850 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, void *sc, 851 int (*wakefun)(pci_chipset_tag_t, pcitag_t, void *, pcireg_t)) 852 { 853 struct device *dv = sc; 854 pcireg_t pmode; 855 int error; 856 857 if ((error = pci_get_powerstate(pc, tag, &pmode))) 858 return error; 859 860 switch (pmode) { 861 case PCI_PMCSR_STATE_D0: 862 break; 863 case PCI_PMCSR_STATE_D3: 864 if (wakefun == NULL) { 865 /* 866 * The card has lost all configuration data in 867 * this state, so punt. 868 */ 869 aprint_error( 870 "%s: unable to wake up from power state D3\n", 871 dv->dv_xname); 872 return EOPNOTSUPP; 873 } 874 /*FALLTHROUGH*/ 875 default: 876 if (wakefun) { 877 error = (*wakefun)(pc, tag, sc, pmode); 878 if (error) 879 return error; 880 } 881 aprint_normal("%s: waking up from power state D%d\n", 882 dv->dv_xname, pmode); 883 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 884 return error; 885 } 886 return 0; 887 } 888 889 int 890 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 891 void *sc, pcireg_t state) 892 { 893 return 0; 894 } 895 896 pnp_status_t 897 pci_net_generic_power(device_t dv, pnp_request_t req, void *opaque, 898 pci_chipset_tag_t pc, pcitag_t tag, struct pci_conf_state *pciconf, 899 struct ifnet *ifp) 900 { 901 pnp_status_t status; 902 pnp_state_t *state; 903 pnp_capabilities_t *caps; 904 pcireg_t val; 905 int off, s; 906 907 status = PNP_STATUS_UNSUPPORTED; 908 909 switch (req) { 910 case PNP_REQUEST_GET_CAPABILITIES: 911 caps = opaque; 912 913 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &off, &val)) 914 return PNP_STATUS_UNSUPPORTED; 915 caps->state = pci_pnp_capabilities(val); 916 status = PNP_STATUS_SUCCESS; 917 break; 918 case PNP_REQUEST_SET_STATE: 919 state = opaque; 920 switch (*state) { 921 case PNP_STATE_D0: 922 val = PCI_PMCSR_STATE_D0; 923 break; 924 case PNP_STATE_D3: 925 val = PCI_PMCSR_STATE_D3; 926 s = splnet(); 927 (*ifp->if_stop)(ifp, 1); 928 pci_conf_capture(pc, tag, pciconf); 929 splx(s); 930 break; 931 default: 932 return PNP_STATUS_UNSUPPORTED; 933 } 934 935 if (pci_set_powerstate(pc, tag, val) == 0) { 936 status = PNP_STATUS_SUCCESS; 937 if (*state != PNP_STATE_D0) 938 break; 939 940 s = splnet(); 941 pci_conf_restore(pc, tag, pciconf); 942 943 if (ifp->if_flags & IFF_UP) { 944 ifp->if_flags &= ~IFF_RUNNING; 945 (*ifp->if_init)(ifp); 946 (*ifp->if_start)(ifp); 947 } 948 splx(s); 949 } 950 break; 951 case PNP_REQUEST_GET_STATE: 952 state = opaque; 953 if (pci_get_powerstate(pc, tag, &val) != 0) 954 return PNP_STATUS_UNSUPPORTED; 955 956 *state = pci_pnp_powerstate(val); 957 status = PNP_STATUS_SUCCESS; 958 break; 959 default: 960 status = PNP_STATUS_UNSUPPORTED; 961 } 962 963 return status; 964 } 965 966 CFATTACH_DECL2(pci, sizeof(struct pci_softc), 967 pcimatch, pciattach, NULL, NULL, pcirescan, pcidevdetached); 968
Indexes created Tue Sep 30 20:09:53 GMT 2025